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KttOPzmiC1MkwsL4cpf3lri5iSJSMewC X-Spam-Status: No, score=-12.7 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,GIT_PATCH_0,RCVD_IN_DNSWL_LOW,RCVD_IN_MSPIKE_H2,SPF_HELO_NONE,SPF_NONE,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: This is patch-v2 meant to fix compiling errors when maintainer mode is enable to BPF target. Changes from v1: + Adjust type for mask bit width in cgen-dis.c. + Looking for regressions on 134 CGEN targets. + Tweak change log message. Please let me know your comments, I'll really appreciate them. Kind regards, guillermo -- Regenerating BPF target using the maintainer mode emits: .../opcodes/bpf-opc.c:57:11: error: conversion from ‘long unsigned int’ to ‘unsigned int’ changes value from ‘18446744073709486335’ to ‘4294902015’ [-Werror=overflow] 57 | 64, 64, 0xffffffffffff00ff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_SRCLE) }, { F (F_OP_CODE) }, { F (F_DSTLE) }, { F (F_OP_SRC) }, { F (F_OP_CLASS) }, { 0 } } The use of a narrow size to handle the mask CGEN in instruction format is causing this error. Additionally eBPF `call' instructions constructed by expressions using symbols (BPF_PSEUDO_CALL) emits annotations in `src' field of the instruction, it's used to identify BPF target endianness. Regression tests to the following targets were done: bpf arm-linuxeabi arm-nacl arm-netbsdelf arm-nto arm-pe arm-symbianelf arm-vxworks arm-wince-pe aarch64-linux alpha-dec-vms alpha-linux alpha-linuxecoff alpha-netbsd alpha-unknown-freebsd4.7 am33_2.0-linux arc-linux-uclibc avr-elf bfin-elf cr16-elf cris-elf crisv32-linux crx-elf d10v-elf d30v-elf dlx-elf epiphany-elf fr30-elf frv-elf frv-linux ft32-elf h8300-elf hppa-linux hppa-hp-hpux10 hppa64-hp-hpux11.23 hppa64-linux mips-linux mips-vxworks mips64-linux mipsel-linux-gnu mipsisa32el-linux mips64-openbsd mipstx39-elf ia64-elf ia64-freebsd5 ia64-hpux ia64-linux ia64-netbsd ia64-vms ip2k-elf iq2000-elf lm32-elf m32c-elf m32r-elf m68hc11-elf m68hc12-elf m68k-elf m68k-linux m68k-netbsd mcore-elf mcore-pe mep-elf metag-linux microblaze-elf mmix mn10200-elf mn10300-elf moxie-elf ms1-elf msp430-elf mt-elf nds32le-elf nios2-linux or1k-elf pdp11-dec-aout pj-elf powerpc-eabisim powerpc-eabivle powerpc-linux powerpc-nto powerpc-wrs-vxworks powerpc64-linux powerpcle-cygwin powerpcle-elf powerpc64le-linux ppc-lynxos pru-elf riscv32-elf riscv64-elf rl78-elf rs6000-aix4.3.3 rs6000-aix5.1 rx-elf s390-linux s390x-linux score-elf sh-linux sh-nto sh-pe sh-rtems sh-vxworks shl-unknown-netbsdelf sparc-aout sparc-linux sparc-vxworks sparc64-linux sparc-sun-solaris2.12 spu-elf tic30-unknown-aout tic30-unknown-coff tic4x-coff tic54x-coff tic6x-elf tilegx-linux tilepro-linux v850-elf vax-netbsdelf visium-elf i386-darwin i386-lynxos i586-linux i686-nacl i686-pc-beos i686-pc-elf i686-pe i686-vxworks x86_64-linux x86_64-w64-mingw32 x86_64-nacl xgate-elf xstormy16-elf xtensa-elf z8k-coff z80-coff. cpu/ * bpf.cpu (define-call-insn): Add `src' operand field to the instruction. include/ *opcode/cge.h (CGEN_IFMT): Adjust mask bit width. opcodes/ * cgen-dis.c (count_decodable_bits): Adjust type for mask bit width. * bpf-opc.c: Regenerate. --- cpu/bpf.cpu | 2 +- include/opcode/cgen.h | 2 +- opcodes/bpf-opc.c | 54 +++++++++++++++++++++++-------------------- opcodes/cgen-dis.c | 2 +- 4 files changed, 32 insertions(+), 28 deletions(-) diff --git a/cpu/bpf.cpu b/cpu/bpf.cpu index 13dde7094c8..2ae74fc4c18 100644 --- a/cpu/bpf.cpu +++ b/cpu/bpf.cpu @@ -768,7 +768,7 @@ "call" (endian-isas x-endian) "call $disp32" - (+ disp32 (f-offset16 0) (f-regs 0) + (+ disp32 (f-offset16 0) (.sym src x-endian) ((.sym f-dst x-endian) 0) OP_CLASS_JMP OP_SRC_K OP_CODE_CALL) (c-call VOID "bpfbf_call" disp32 (ifield (.sym f-src x-endian))) diff --git a/include/opcode/cgen.h b/include/opcode/cgen.h index 36b88f1b5fe..6c0732b4b25 100644 --- a/include/opcode/cgen.h +++ b/include/opcode/cgen.h @@ -914,7 +914,7 @@ typedef struct Each insn's value is stored with the insn. The first step in recognizing an insn for disassembly is (opcode & mask) == value. */ - CGEN_INSN_INT mask; + CGEN_INSN_LGUINT mask; #define CGEN_IFMT_MASK(ifmt) ((ifmt)->mask) /* Instruction fields. diff --git a/opcodes/bpf-opc.c b/opcodes/bpf-opc.c index a6d8a7dd3ca..1cc06f7cbf6 100644 --- a/opcodes/bpf-opc.c +++ b/opcodes/bpf-opc.c @@ -50,99 +50,103 @@ static const CGEN_IFMT ifmt_empty ATTRIBUTE_UNUSED = { }; static const CGEN_IFMT ifmt_addile ATTRIBUTE_UNUSED = { - 64, 64, 0xff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_SRCLE) }, { F (F_OP_CODE) }, { F (F_DSTLE) }, { F (F_OP_SRC) }, { F (F_OP_CLASS) }, { 0 } } + 64, 64, 0xfffff0ff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_SRCLE) }, { F (F_OP_CODE) }, { F (F_DSTLE) }, { F (F_OP_SRC) }, { F (F_OP_CLASS) }, { 0 } } }; static const CGEN_IFMT ifmt_addrle ATTRIBUTE_UNUSED = { - 64, 64, 0xff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_SRCLE) }, { F (F_OP_CODE) }, { F (F_DSTLE) }, { F (F_OP_SRC) }, { F (F_OP_CLASS) }, { 0 } } + 64, 64, 0xffffffffffff00ff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_SRCLE) }, { F (F_OP_CODE) }, { F (F_DSTLE) }, { F (F_OP_SRC) }, { F (F_OP_CLASS) }, { 0 } } }; static const CGEN_IFMT ifmt_negle ATTRIBUTE_UNUSED = { - 64, 64, 0xff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_SRCLE) }, { F (F_OP_CODE) }, { F (F_DSTLE) }, { F (F_OP_SRC) }, { F (F_OP_CLASS) }, { 0 } } + 64, 64, 0xfffffffffffff0ff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_SRCLE) }, { F (F_OP_CODE) }, { F (F_DSTLE) }, { F (F_OP_SRC) }, { F (F_OP_CLASS) }, { 0 } } }; static const CGEN_IFMT ifmt_addibe ATTRIBUTE_UNUSED = { - 64, 64, 0xff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_DSTBE) }, { F (F_OP_CODE) }, { F (F_SRCBE) }, { F (F_OP_SRC) }, { F (F_OP_CLASS) }, { 0 } } + 64, 64, 0xffff0fff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_DSTBE) }, { F (F_OP_CODE) }, { F (F_SRCBE) }, { F (F_OP_SRC) }, { F (F_OP_CLASS) }, { 0 } } }; static const CGEN_IFMT ifmt_addrbe ATTRIBUTE_UNUSED = { - 64, 64, 0xff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_DSTBE) }, { F (F_OP_CODE) }, { F (F_SRCBE) }, { F (F_OP_SRC) }, { F (F_OP_CLASS) }, { 0 } } + 64, 64, 0xffffffffffff00ff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_DSTBE) }, { F (F_OP_CODE) }, { F (F_SRCBE) }, { F (F_OP_SRC) }, { F (F_OP_CLASS) }, { 0 } } }; static const CGEN_IFMT ifmt_negbe ATTRIBUTE_UNUSED = { - 64, 64, 0xff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_DSTBE) }, { F (F_OP_CODE) }, { F (F_SRCBE) }, { F (F_OP_SRC) }, { F (F_OP_CLASS) }, { 0 } } + 64, 64, 0xffffffffffff0fff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_DSTBE) }, { F (F_OP_CODE) }, { F (F_SRCBE) }, { F (F_OP_SRC) }, { F (F_OP_CLASS) }, { 0 } } }; static const CGEN_IFMT ifmt_endlele ATTRIBUTE_UNUSED = { - 64, 64, 0xff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_SRCLE) }, { F (F_OP_CODE) }, { F (F_DSTLE) }, { F (F_OP_SRC) }, { F (F_OP_CLASS) }, { 0 } } + 64, 64, 0xfffff0ff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_SRCLE) }, { F (F_OP_CODE) }, { F (F_DSTLE) }, { F (F_OP_SRC) }, { F (F_OP_CLASS) }, { 0 } } }; static const CGEN_IFMT ifmt_endlebe ATTRIBUTE_UNUSED = { - 64, 64, 0xff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_DSTBE) }, { F (F_OP_CODE) }, { F (F_SRCBE) }, { F (F_OP_SRC) }, { F (F_OP_CLASS) }, { 0 } } + 64, 64, 0xffff0fff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_DSTBE) }, { F (F_OP_CODE) }, { F (F_SRCBE) }, { F (F_OP_SRC) }, { F (F_OP_CLASS) }, { 0 } } }; static const CGEN_IFMT ifmt_lddwle ATTRIBUTE_UNUSED = { - 64, 128, 0xff, { { F (F_IMM64) }, { F (F_OFFSET16) }, { F (F_SRCLE) }, { F (F_OP_MODE) }, { F (F_OP_SIZE) }, { F (F_DSTLE) }, { F (F_OP_CLASS) }, { 0 } } + 64, 128, 0xfffff0ff, { { F (F_IMM64) }, { F (F_OFFSET16) }, { F (F_SRCLE) }, { F (F_OP_MODE) }, { F (F_OP_SIZE) }, { F (F_DSTLE) }, { F (F_OP_CLASS) }, { 0 } } }; static const CGEN_IFMT ifmt_lddwbe ATTRIBUTE_UNUSED = { - 64, 128, 0xff, { { F (F_IMM64) }, { F (F_OFFSET16) }, { F (F_DSTBE) }, { F (F_OP_MODE) }, { F (F_OP_SIZE) }, { F (F_SRCBE) }, { F (F_OP_CLASS) }, { 0 } } + 64, 128, 0xffff0fff, { { F (F_IMM64) }, { F (F_OFFSET16) }, { F (F_DSTBE) }, { F (F_OP_MODE) }, { F (F_OP_SIZE) }, { F (F_SRCBE) }, { F (F_OP_CLASS) }, { 0 } } }; static const CGEN_IFMT ifmt_ldabsw ATTRIBUTE_UNUSED = { - 64, 64, 0xff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_REGS) }, { F (F_OP_MODE) }, { F (F_OP_SIZE) }, { F (F_OP_CLASS) }, { 0 } } + 64, 64, 0xffffffff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_REGS) }, { F (F_OP_MODE) }, { F (F_OP_SIZE) }, { F (F_OP_CLASS) }, { 0 } } }; static const CGEN_IFMT ifmt_ldindwle ATTRIBUTE_UNUSED = { - 64, 64, 0xff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_SRCLE) }, { F (F_OP_MODE) }, { F (F_OP_SIZE) }, { F (F_DSTLE) }, { F (F_OP_CLASS) }, { 0 } } + 64, 64, 0xffff0fff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_SRCLE) }, { F (F_OP_MODE) }, { F (F_OP_SIZE) }, { F (F_DSTLE) }, { F (F_OP_CLASS) }, { 0 } } }; static const CGEN_IFMT ifmt_ldindwbe ATTRIBUTE_UNUSED = { - 64, 64, 0xff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_DSTBE) }, { F (F_OP_MODE) }, { F (F_OP_SIZE) }, { F (F_SRCBE) }, { F (F_OP_CLASS) }, { 0 } } + 64, 64, 0xfffff0ff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_DSTBE) }, { F (F_OP_MODE) }, { F (F_OP_SIZE) }, { F (F_SRCBE) }, { F (F_OP_CLASS) }, { 0 } } }; static const CGEN_IFMT ifmt_ldxwle ATTRIBUTE_UNUSED = { - 64, 64, 0xff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_SRCLE) }, { F (F_OP_MODE) }, { F (F_OP_SIZE) }, { F (F_DSTLE) }, { F (F_OP_CLASS) }, { 0 } } + 64, 64, 0xffffffff000000ff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_SRCLE) }, { F (F_OP_MODE) }, { F (F_OP_SIZE) }, { F (F_DSTLE) }, { F (F_OP_CLASS) }, { 0 } } }; static const CGEN_IFMT ifmt_ldxwbe ATTRIBUTE_UNUSED = { - 64, 64, 0xff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_DSTBE) }, { F (F_OP_MODE) }, { F (F_OP_SIZE) }, { F (F_SRCBE) }, { F (F_OP_CLASS) }, { 0 } } + 64, 64, 0xffffffff000000ff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_DSTBE) }, { F (F_OP_MODE) }, { F (F_OP_SIZE) }, { F (F_SRCBE) }, { F (F_OP_CLASS) }, { 0 } } }; static const CGEN_IFMT ifmt_stble ATTRIBUTE_UNUSED = { - 64, 64, 0xff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_SRCLE) }, { F (F_OP_MODE) }, { F (F_OP_SIZE) }, { F (F_DSTLE) }, { F (F_OP_CLASS) }, { 0 } } + 64, 64, 0xf0ff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_SRCLE) }, { F (F_OP_MODE) }, { F (F_OP_SIZE) }, { F (F_DSTLE) }, { F (F_OP_CLASS) }, { 0 } } }; static const CGEN_IFMT ifmt_stbbe ATTRIBUTE_UNUSED = { - 64, 64, 0xff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_DSTBE) }, { F (F_OP_MODE) }, { F (F_OP_SIZE) }, { F (F_SRCBE) }, { F (F_OP_CLASS) }, { 0 } } + 64, 64, 0xfff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_DSTBE) }, { F (F_OP_MODE) }, { F (F_OP_SIZE) }, { F (F_SRCBE) }, { F (F_OP_CLASS) }, { 0 } } }; static const CGEN_IFMT ifmt_jeqile ATTRIBUTE_UNUSED = { - 64, 64, 0xff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_SRCLE) }, { F (F_OP_CODE) }, { F (F_DSTLE) }, { F (F_OP_SRC) }, { F (F_OP_CLASS) }, { 0 } } + 64, 64, 0xf0ff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_SRCLE) }, { F (F_OP_CODE) }, { F (F_DSTLE) }, { F (F_OP_SRC) }, { F (F_OP_CLASS) }, { 0 } } }; static const CGEN_IFMT ifmt_jeqrle ATTRIBUTE_UNUSED = { - 64, 64, 0xff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_SRCLE) }, { F (F_OP_CODE) }, { F (F_DSTLE) }, { F (F_OP_SRC) }, { F (F_OP_CLASS) }, { 0 } } + 64, 64, 0xffffffff000000ff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_SRCLE) }, { F (F_OP_CODE) }, { F (F_DSTLE) }, { F (F_OP_SRC) }, { F (F_OP_CLASS) }, { 0 } } }; static const CGEN_IFMT ifmt_jeqibe ATTRIBUTE_UNUSED = { - 64, 64, 0xff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_DSTBE) }, { F (F_OP_CODE) }, { F (F_SRCBE) }, { F (F_OP_SRC) }, { F (F_OP_CLASS) }, { 0 } } + 64, 64, 0xfff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_DSTBE) }, { F (F_OP_CODE) }, { F (F_SRCBE) }, { F (F_OP_SRC) }, { F (F_OP_CLASS) }, { 0 } } }; static const CGEN_IFMT ifmt_jeqrbe ATTRIBUTE_UNUSED = { - 64, 64, 0xff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_DSTBE) }, { F (F_OP_CODE) }, { F (F_SRCBE) }, { F (F_OP_SRC) }, { F (F_OP_CLASS) }, { 0 } } + 64, 64, 0xffffffff000000ff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_DSTBE) }, { F (F_OP_CODE) }, { F (F_SRCBE) }, { F (F_OP_SRC) }, { F (F_OP_CLASS) }, { 0 } } }; static const CGEN_IFMT ifmt_callle ATTRIBUTE_UNUSED = { - 64, 64, 0xff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_REGS) }, { F (F_OP_CODE) }, { F (F_OP_SRC) }, { F (F_OP_CLASS) }, { 0 } } + 64, 64, 0xffff0fff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_SRCLE) }, { F (F_OP_CODE) }, { F (F_DSTLE) }, { F (F_OP_SRC) }, { F (F_OP_CLASS) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_callbe ATTRIBUTE_UNUSED = { + 64, 64, 0xfffff0ff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_DSTBE) }, { F (F_OP_CODE) }, { F (F_SRCBE) }, { F (F_OP_SRC) }, { F (F_OP_CLASS) }, { 0 } } }; static const CGEN_IFMT ifmt_ja ATTRIBUTE_UNUSED = { - 64, 64, 0xff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_REGS) }, { F (F_OP_CODE) }, { F (F_OP_SRC) }, { F (F_OP_CLASS) }, { 0 } } + 64, 64, 0xffffffff0000ffff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_REGS) }, { F (F_OP_CODE) }, { F (F_OP_SRC) }, { F (F_OP_CLASS) }, { 0 } } }; static const CGEN_IFMT ifmt_exit ATTRIBUTE_UNUSED = { - 64, 64, 0xff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_REGS) }, { F (F_OP_CODE) }, { F (F_OP_SRC) }, { F (F_OP_CLASS) }, { 0 } } + 64, 64, 0xffffffffffffffff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_REGS) }, { F (F_OP_CODE) }, { F (F_OP_SRC) }, { F (F_OP_CLASS) }, { 0 } } }; #undef F @@ -1646,7 +1650,7 @@ static const CGEN_OPCODE bpf_cgen_insn_opcode_table[MAX_INSNS] = { { 0, 0, 0, 0 }, { { MNEM, ' ', OP (DISP32), 0 } }, - & ifmt_callle, { 0x85 } + & ifmt_callbe, { 0x85 } }, /* call $dstle */ { diff --git a/opcodes/cgen-dis.c b/opcodes/cgen-dis.c index de315d90cfc..90746a845ed 100644 --- a/opcodes/cgen-dis.c +++ b/opcodes/cgen-dis.c @@ -39,7 +39,7 @@ static void add_insn_to_hash_chain (CGEN_INSN_LIST *, static int count_decodable_bits (const CGEN_INSN *insn) { - unsigned mask = CGEN_INSN_BASE_MASK (insn); + CGEN_INSN_LGUINT mask = CGEN_INSN_BASE_MASK (insn); #if GCC_VERSION >= 3004 return __builtin_popcount (mask); #else -- 2.39.0