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[62.178.148.172]) by smtp.gmail.com with ESMTPSA id m9-20020a7bca49000000b003c65c9a36dfsm3050553wml.48.2023.01.20.11.55.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 20 Jan 2023 11:55:37 -0800 (PST) From: Christoph Muellner To: binutils@sourceware.org, Nelson Chu , Andrew Waterman , Palmer Dabbelt , Jim Wilson , Philipp Tomsich , Elda Kuka , Aaron Durbin , Andrew de los Reyes , Eric Gouriou , Barna Ibrahim , Jeff Law Cc: =?UTF-8?q?Christoph=20M=C3=BCllner?= Subject: [RFC PATCH v2 2/6] RISC-V: Add Zvkg ISA extension support Date: Fri, 20 Jan 2023 20:55:28 +0100 Message-Id: <20230120195532.917113-3-christoph.muellner@vrull.eu> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20230120195532.917113-1-christoph.muellner@vrull.eu> References: <20230120195532.917113-1-christoph.muellner@vrull.eu> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-12.6 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,GIT_PATCH_0,JMQ_SPF_NEUTRAL,KAM_MANYTO,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: From: Christoph Müllner This commit adds the Zvkg ISA extension instruction, which is part of the vector crypto extensions. Signed-off-by: Christoph Müllner --- bfd/elfxx-riscv.c | 5 +++++ gas/testsuite/gas/riscv/zvkg.d | 9 +++++++++ gas/testsuite/gas/riscv/zvkg.s | 1 + include/opcode/riscv-opc.h | 5 +++++ include/opcode/riscv.h | 1 + opcodes/riscv-opc.c | 3 +++ 6 files changed, 24 insertions(+) create mode 100644 gas/testsuite/gas/riscv/zvkg.d create mode 100644 gas/testsuite/gas/riscv/zvkg.s diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c index c9952a51c3c..9e0dee9cc72 100644 --- a/bfd/elfxx-riscv.c +++ b/bfd/elfxx-riscv.c @@ -1206,6 +1206,7 @@ static struct riscv_supported_ext riscv_supported_std_z_ext[] = {"zve64f", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"zve64d", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"zvkb", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"zvkg", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"zvl32b", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"zvl64b", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"zvl128b", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, @@ -2358,6 +2359,8 @@ riscv_multi_subset_supports (riscv_parse_subset_t *rps, || riscv_subset_supports (rps, "zve32f")); case INSN_CLASS_ZVKB: return riscv_subset_supports (rps, "zvkb"); + case INSN_CLASS_ZVKG: + return riscv_subset_supports (rps, "zvkg"); case INSN_CLASS_SVINVAL: return riscv_subset_supports (rps, "svinval"); case INSN_CLASS_H: @@ -2518,6 +2521,8 @@ riscv_multi_subset_supports_ext (riscv_parse_subset_t *rps, return _("v' or `zve64d' or `zve64f' or `zve32f"); case INSN_CLASS_ZVKB: return _("zvkb"); + case INSN_CLASS_ZVKG: + return _("zvkg"); case INSN_CLASS_SVINVAL: return "svinval"; case INSN_CLASS_H: diff --git a/gas/testsuite/gas/riscv/zvkg.d b/gas/testsuite/gas/riscv/zvkg.d new file mode 100644 index 00000000000..abca83ea3a8 --- /dev/null +++ b/gas/testsuite/gas/riscv/zvkg.d @@ -0,0 +1,9 @@ +#as: -march=rv64gc_zvkg +#objdump: -dr + +.*:[ ]+file format .* + + +Disassembly of section .text: +0+000 <.text>: +[ ]+[0-9a-f]+:[ ]+b2862277[ ]+vghmac.vv[ ]+v4,v8,v12 diff --git a/gas/testsuite/gas/riscv/zvkg.s b/gas/testsuite/gas/riscv/zvkg.s new file mode 100644 index 00000000000..7c97108a396 --- /dev/null +++ b/gas/testsuite/gas/riscv/zvkg.s @@ -0,0 +1 @@ + vghmac.vv v4, v8, v12 diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h index bdcb3e442f8..cfe4f12d7e4 100644 --- a/include/opcode/riscv-opc.h +++ b/include/opcode/riscv-opc.h @@ -2084,6 +2084,9 @@ #define MASK_VANDNVX 0xfc00707f #define MATCH_VANDNVI 0x04003057 #define MASK_VANDNVI 0xfc00707f +/* Zvkg instructions. */ +#define MATCH_VGHMACVV 0xb2002077 +#define MASK_VGHMACVV 0xfe00707f /* Svinval instruction. */ #define MATCH_SINVAL_VMA 0x16000073 #define MASK_SINVAL_VMA 0xfe007fff @@ -3162,6 +3165,8 @@ DECLARE_INSN(vrev8v, MATCH_VREV8V, MASK_VREV8V) DECLARE_INSN(vandnvv, MATCH_VANDNVV, MASK_VANDNVV) DECLARE_INSN(vandnvx, MATCH_VANDNVX, MASK_VANDNVX) DECLARE_INSN(vandnvi, MATCH_VANDNVI, MASK_VANDNVI) +/* Zvkg instructions. */ +DECLARE_INSN(vghmacvv, MATCH_VGHMACVV, MASK_VGHMACVV) /* Vendor-specific (T-Head) XTheadBa instructions. */ DECLARE_INSN(th_addsl, MATCH_TH_ADDSL, MASK_TH_ADDSL) /* Vendor-specific (T-Head) XTheadBb instructions. */ diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h index cc3950f56b8..9e883f030d6 100644 --- a/include/opcode/riscv.h +++ b/include/opcode/riscv.h @@ -410,6 +410,7 @@ enum riscv_insn_class INSN_CLASS_V, INSN_CLASS_ZVEF, INSN_CLASS_ZVKB, + INSN_CLASS_ZVKG, INSN_CLASS_SVINVAL, INSN_CLASS_ZICBOM, INSN_CLASS_ZICBOP, diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c index 0b76bff2617..9992b11f94c 100644 --- a/opcodes/riscv-opc.c +++ b/opcodes/riscv-opc.c @@ -1831,6 +1831,9 @@ const struct riscv_opcode riscv_opcodes[] = {"vandn.vx", 0, INSN_CLASS_ZVKB, "Vd,Vt,sVm", MATCH_VANDNVX, MASK_VANDNVX, match_opcode, 0}, {"vandn.vi", 0, INSN_CLASS_ZVKB, "Vd,Vt,ViVm", MATCH_VANDNVI, MASK_VANDNVI, match_opcode, 0}, +/* Zvkg instructions. */ +{"vghmac.vv", 0, INSN_CLASS_ZVKG, "Vd,Vt,Vs", MATCH_VGHMACVV, MASK_VGHMACVV, match_opcode, 0}, + /* Supervisor instructions. */ {"csrr", 0, INSN_CLASS_ZICSR, "d,E", MATCH_CSRRS, MASK_CSRRS|MASK_RS1, match_opcode, INSN_ALIAS }, {"csrw", 0, INSN_CLASS_ZICSR, "E,s", MATCH_CSRRW, MASK_CSRRW|MASK_RD, match_opcode, INSN_ALIAS }, -- 2.39.0