From: Christoph Muellner <christoph.muellner@vrull.eu>
To: binutils@sourceware.org, Nelson Chu <nelson@rivosinc.com>,
Andrew Waterman <andrew@sifive.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Jim Wilson <jim.wilson.gcc@gmail.com>,
Philipp Tomsich <philipp.tomsich@vrull.eu>,
Elda Kuka <elda.kuka@vrull.eu>,
Aaron Durbin <adurbin@rivosinc.com>,
Andrew de los Reyes <adlr@rivosinc.com>,
Eric Gouriou <ego@rivosinc.com>,
Barna Ibrahim <barna@rivosinc.com>,
Jeff Law <jeffreyalaw@gmail.com>
Cc: "Christoph Müllner" <christoph.muellner@vrull.eu>
Subject: [RFC PATCH v2 4/6] RISC-V: Add Zvkns ISA extension support
Date: Fri, 20 Jan 2023 20:55:30 +0100 [thread overview]
Message-ID: <20230120195532.917113-5-christoph.muellner@vrull.eu> (raw)
In-Reply-To: <20230120195532.917113-1-christoph.muellner@vrull.eu>
From: Christoph Müllner <christoph.muellner@vrull.eu>
This commit adds the Zvkns ISA extension instructions, which are
part of the vector crypto extensions.
Changes in v2:
- Rename Zvkn -> Zvkns
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
---
bfd/elfxx-riscv.c | 5 +++++
gas/testsuite/gas/riscv/zvkns.d | 21 ++++++++++++++++++++
gas/testsuite/gas/riscv/zvkns.s | 13 ++++++++++++
include/opcode/riscv-opc.h | 35 +++++++++++++++++++++++++++++++++
include/opcode/riscv.h | 1 +
opcodes/riscv-opc.c | 13 ++++++++++++
6 files changed, 88 insertions(+)
create mode 100644 gas/testsuite/gas/riscv/zvkns.d
create mode 100644 gas/testsuite/gas/riscv/zvkns.s
diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
index b61c73569d3..790585ccdd9 100644
--- a/bfd/elfxx-riscv.c
+++ b/bfd/elfxx-riscv.c
@@ -1209,6 +1209,7 @@ static struct riscv_supported_ext riscv_supported_std_z_ext[] =
{"zvkg", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"zvknha", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"zvknhb", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
+ {"zvkns", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"zvl32b", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"zvl64b", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"zvl128b", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
@@ -2370,6 +2371,8 @@ riscv_multi_subset_supports (riscv_parse_subset_t *rps,
case INSN_CLASS_ZVKNHA_OR_ZVKNHB:
return (riscv_subset_supports (rps, "zvknha")
|| riscv_subset_supports (rps, "zvknhb"));
+ case INSN_CLASS_ZVKNS:
+ return riscv_subset_supports (rps, "zvkns");
case INSN_CLASS_SVINVAL:
return riscv_subset_supports (rps, "svinval");
case INSN_CLASS_H:
@@ -2536,6 +2539,8 @@ riscv_multi_subset_supports_ext (riscv_parse_subset_t *rps,
return _("zvknha");
case INSN_CLASS_ZVKNHB:
return _("zvknhb");
+ case INSN_CLASS_ZVKNS:
+ return _("zvkns");
case INSN_CLASS_SVINVAL:
return "svinval";
case INSN_CLASS_H:
diff --git a/gas/testsuite/gas/riscv/zvkns.d b/gas/testsuite/gas/riscv/zvkns.d
new file mode 100644
index 00000000000..3d4687c2140
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zvkns.d
@@ -0,0 +1,21 @@
+#as: -march=rv64gc_zvkns
+#objdump: -dr
+
+.*:[ ]+file format .*
+
+
+Disassembly of section .text:
+0+000 <.text>:
+[ ]+[0-9a-f]+:[ ]+a280a277[ ]+vaesdf.vv[ ]+v4,v8
+[ ]+[0-9a-f]+:[ ]+a680a277[ ]+vaesdf.vs[ ]+v4,v8
+[ ]+[0-9a-f]+:[ ]+a2802277[ ]+vaesdm.vv[ ]+v4,v8
+[ ]+[0-9a-f]+:[ ]+a6802277[ ]+vaesdm.vs[ ]+v4,v8
+[ ]+[0-9a-f]+:[ ]+a281a277[ ]+vaesef.vv[ ]+v4,v8
+[ ]+[0-9a-f]+:[ ]+a681a277[ ]+vaesef.vs[ ]+v4,v8
+[ ]+[0-9a-f]+:[ ]+a2812277[ ]+vaesem.vv[ ]+v4,v8
+[ ]+[0-9a-f]+:[ ]+a6812277[ ]+vaesem.vs[ ]+v4,v8
+[ ]+[0-9a-f]+:[ ]+8a812277[ ]+vaeskf1.vi[ ]+v4,v8,2
+[ ]+[0-9a-f]+:[ ]+8a872277[ ]+vaeskf1.vi[ ]+v4,v8,14
+[ ]+[0-9a-f]+:[ ]+aa812277[ ]+vaeskf2.vi[ ]+v4,v8,2
+[ ]+[0-9a-f]+:[ ]+aa872277[ ]+vaeskf2.vi[ ]+v4,v8,14
+[ ]+[0-9a-f]+:[ ]+a683a277[ ]+vaesz.vs[ ]+v4,v8
diff --git a/gas/testsuite/gas/riscv/zvkns.s b/gas/testsuite/gas/riscv/zvkns.s
new file mode 100644
index 00000000000..f0f3811eaec
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zvkns.s
@@ -0,0 +1,13 @@
+ vaesdf.vv v4, v8
+ vaesdf.vs v4, v8
+ vaesdm.vv v4, v8
+ vaesdm.vs v4, v8
+ vaesef.vv v4, v8
+ vaesef.vs v4, v8
+ vaesem.vv v4, v8
+ vaesem.vs v4, v8
+ vaeskf1.vi v4, v8, 2
+ vaeskf1.vi v4, v8, 14
+ vaeskf2.vi v4, v8, 2
+ vaeskf2.vi v4, v8, 14
+ vaesz.vs v4, v8
diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h
index 29b45adb010..e04169b5343 100644
--- a/include/opcode/riscv-opc.h
+++ b/include/opcode/riscv-opc.h
@@ -2094,6 +2094,29 @@
#define MASK_VSHA2CLVV 0xfe00707f
#define MATCH_VSHA2MSVV 0xb6002077
#define MASK_VSHA2MSVV 0xfe00707f
+/* Zvkns instructions. */
+#define MATCH_VAESDFVV 0xa200a077
+#define MASK_VAESDFVV 0xfe0ff07f
+#define MATCH_VAESDFVS 0xa600a077
+#define MASK_VAESDFVS 0xfe0ff07f
+#define MATCH_VAESDMVV 0xa2002077
+#define MASK_VAESDMVV 0xfe0ff07f
+#define MATCH_VAESDMVS 0xa6002077
+#define MASK_VAESDMVS 0xfe0ff07f
+#define MATCH_VAESEFVV 0xa201a077
+#define MASK_VAESEFVV 0xfe0ff07f
+#define MATCH_VAESEFVS 0xa601a077
+#define MASK_VAESEFVS 0xfe0ff07f
+#define MATCH_VAESEMVV 0xa2012077
+#define MASK_VAESEMVV 0xfe0ff07f
+#define MATCH_VAESEMVS 0xa6012077
+#define MASK_VAESEMVS 0xfe0ff07f
+#define MATCH_VAESKF1VI 0x8a002077
+#define MASK_VAESKF1VI 0xfe00707f
+#define MATCH_VAESKF2VI 0xaa002077
+#define MASK_VAESKF2VI 0xfe00707f
+#define MATCH_VAESZVS 0xa603a077
+#define MASK_VAESZVS 0xfe0ff07f
/* Svinval instruction. */
#define MATCH_SINVAL_VMA 0x16000073
#define MASK_SINVAL_VMA 0xfe007fff
@@ -3178,6 +3201,18 @@ DECLARE_INSN(vghmacvv, MATCH_VGHMACVV, MASK_VGHMACVV)
DECLARE_INSN(vsha2chvv, MATCH_VSHA2CHVV, MASK_VSHA2CHVV)
DECLARE_INSN(vsha2clvv, MATCH_VSHA2CLVV, MASK_VSHA2CLVV)
DECLARE_INSN(vsha2msvv, MATCH_VSHA2MSVV, MASK_VSHA2MSVV)
+/* Zvkns instructions. */
+DECLARE_INSN(vaesdfvv, MATCH_VAESDFVV, MASK_VAESDFVV)
+DECLARE_INSN(vaesdfvs, MATCH_VAESDFVS, MASK_VAESDFVS)
+DECLARE_INSN(vaesdmvv, MATCH_VAESDMVV, MASK_VAESDMVV)
+DECLARE_INSN(vaesdmvs, MATCH_VAESDMVS, MASK_VAESDMVS)
+DECLARE_INSN(vaesefvv, MATCH_VAESEFVV, MASK_VAESEFVV)
+DECLARE_INSN(vaesefvs, MATCH_VAESEFVS, MASK_VAESEFVS)
+DECLARE_INSN(vaesemvv, MATCH_VAESEMVV, MASK_VAESEMVV)
+DECLARE_INSN(vaesemvs, MATCH_VAESEMVS, MASK_VAESEMVS)
+DECLARE_INSN(vaeskf1vi, MATCH_VAESKF1VI, MASK_VAESKF1VI)
+DECLARE_INSN(vaeskf2vi, MATCH_VAESKF2VI, MASK_VAESKF2VI)
+DECLARE_INSN(vaeszvs, MATCH_VAESZVS, MASK_VAESZVS)
/* Vendor-specific (T-Head) XTheadBa instructions. */
DECLARE_INSN(th_addsl, MATCH_TH_ADDSL, MASK_TH_ADDSL)
/* Vendor-specific (T-Head) XTheadBb instructions. */
diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h
index 55fefa40ae2..48db408f303 100644
--- a/include/opcode/riscv.h
+++ b/include/opcode/riscv.h
@@ -414,6 +414,7 @@ enum riscv_insn_class
INSN_CLASS_ZVKNHA,
INSN_CLASS_ZVKNHB,
INSN_CLASS_ZVKNHA_OR_ZVKNHB,
+ INSN_CLASS_ZVKNS,
INSN_CLASS_SVINVAL,
INSN_CLASS_ZICBOM,
INSN_CLASS_ZICBOP,
diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
index 8de7610573e..a7f79f8fe68 100644
--- a/opcodes/riscv-opc.c
+++ b/opcodes/riscv-opc.c
@@ -1839,6 +1839,19 @@ const struct riscv_opcode riscv_opcodes[] =
{"vsha2cl.vv", 0, INSN_CLASS_ZVKNHA_OR_ZVKNHB, "Vd,Vt,Vs", MATCH_VSHA2CLVV, MASK_VSHA2CLVV, match_opcode, 0},
{"vsha2ms.vv", 0, INSN_CLASS_ZVKNHA_OR_ZVKNHB, "Vd,Vt,Vs", MATCH_VSHA2MSVV, MASK_VSHA2MSVV, match_opcode, 0},
+/* Zvkns instructions. */
+{"vaesdf.vv", 0, INSN_CLASS_ZVKNS, "Vd,Vt", MATCH_VAESDFVV, MASK_VAESDFVV, match_opcode, 0},
+{"vaesdf.vs", 0, INSN_CLASS_ZVKNS, "Vd,Vt", MATCH_VAESDFVS, MASK_VAESDFVV, match_opcode, 0},
+{"vaesdm.vv", 0, INSN_CLASS_ZVKNS, "Vd,Vt", MATCH_VAESDMVV, MASK_VAESDMVV, match_opcode, 0},
+{"vaesdm.vs", 0, INSN_CLASS_ZVKNS, "Vd,Vt", MATCH_VAESDMVS, MASK_VAESDMVV, match_opcode, 0},
+{"vaesef.vv", 0, INSN_CLASS_ZVKNS, "Vd,Vt", MATCH_VAESEFVV, MASK_VAESEFVV, match_opcode, 0},
+{"vaesef.vs", 0, INSN_CLASS_ZVKNS, "Vd,Vt", MATCH_VAESEFVS, MASK_VAESEFVV, match_opcode, 0},
+{"vaesem.vv", 0, INSN_CLASS_ZVKNS, "Vd,Vt", MATCH_VAESEMVV, MASK_VAESEMVV, match_opcode, 0},
+{"vaesem.vs", 0, INSN_CLASS_ZVKNS, "Vd,Vt", MATCH_VAESEMVS, MASK_VAESEMVV, match_opcode, 0},
+{"vaeskf1.vi", 0, INSN_CLASS_ZVKNS, "Vd,Vt,Vj", MATCH_VAESKF1VI, MASK_VAESKF1VI, match_opcode, 0},
+{"vaeskf2.vi", 0, INSN_CLASS_ZVKNS, "Vd,Vt,Vj", MATCH_VAESKF2VI, MASK_VAESKF2VI, match_opcode, 0},
+{"vaesz.vs", 0, INSN_CLASS_ZVKNS, "Vd,Vt", MATCH_VAESZVS, MASK_VAESZVS, match_opcode, 0},
+
/* Supervisor instructions. */
{"csrr", 0, INSN_CLASS_ZICSR, "d,E", MATCH_CSRRS, MASK_CSRRS|MASK_RS1, match_opcode, INSN_ALIAS },
{"csrw", 0, INSN_CLASS_ZICSR, "E,s", MATCH_CSRRW, MASK_CSRRW|MASK_RD, match_opcode, INSN_ALIAS },
--
2.39.0
next prev parent reply other threads:[~2023-01-20 19:55 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-01-20 19:55 [RFC PATCH v2 0/6] RISC-V: Add support for vector crypto extensions Christoph Muellner
2023-01-20 19:55 ` [RFC PATCH v2 1/6] RISC-V: Add Zvkb ISA extension support Christoph Muellner
2023-01-20 19:55 ` [RFC PATCH v2 2/6] RISC-V: Add Zvkg " Christoph Muellner
2023-01-20 19:55 ` [RFC PATCH v2 3/6] RISC-V: Add Zvknh[a,b] " Christoph Muellner
2023-01-20 19:55 ` Christoph Muellner [this message]
2023-01-20 19:55 ` [RFC PATCH v2 5/6] RISC-V: Add Zvksed " Christoph Muellner
2023-01-20 19:55 ` [RFC PATCH v2 6/6] RISC-V: Add Zvksh " Christoph Muellner
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