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[62.178.148.172]) by smtp.gmail.com with ESMTPSA id m9-20020a7bca49000000b003c65c9a36dfsm3050553wml.48.2023.01.20.11.55.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 20 Jan 2023 11:55:41 -0800 (PST) From: Christoph Muellner To: binutils@sourceware.org, Nelson Chu , Andrew Waterman , Palmer Dabbelt , Jim Wilson , Philipp Tomsich , Elda Kuka , Aaron Durbin , Andrew de los Reyes , Eric Gouriou , Barna Ibrahim , Jeff Law Cc: =?UTF-8?q?Christoph=20M=C3=BCllner?= Subject: [RFC PATCH v2 5/6] RISC-V: Add Zvksed ISA extension support Date: Fri, 20 Jan 2023 20:55:31 +0100 Message-Id: <20230120195532.917113-6-christoph.muellner@vrull.eu> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20230120195532.917113-1-christoph.muellner@vrull.eu> References: <20230120195532.917113-1-christoph.muellner@vrull.eu> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-12.6 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,GIT_PATCH_0,JMQ_SPF_NEUTRAL,KAM_MANYTO,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: From: Christoph Müllner This commit adds the Zvksed ISA extension instructions, which are part of the vector crypto extensions. Signed-off-by: Christoph Müllner --- bfd/elfxx-riscv.c | 5 +++++ gas/testsuite/gas/riscv/zvksed.d | 12 ++++++++++++ gas/testsuite/gas/riscv/zvksed.s | 4 ++++ include/opcode/riscv-opc.h | 11 +++++++++++ include/opcode/riscv.h | 1 + opcodes/riscv-opc.c | 5 +++++ 6 files changed, 38 insertions(+) create mode 100644 gas/testsuite/gas/riscv/zvksed.d create mode 100644 gas/testsuite/gas/riscv/zvksed.s diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c index 790585ccdd9..08f892ed987 100644 --- a/bfd/elfxx-riscv.c +++ b/bfd/elfxx-riscv.c @@ -1210,6 +1210,7 @@ static struct riscv_supported_ext riscv_supported_std_z_ext[] = {"zvknha", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"zvknhb", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"zvkns", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"zvksed", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"zvl32b", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"zvl64b", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"zvl128b", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, @@ -2373,6 +2374,8 @@ riscv_multi_subset_supports (riscv_parse_subset_t *rps, || riscv_subset_supports (rps, "zvknhb")); case INSN_CLASS_ZVKNS: return riscv_subset_supports (rps, "zvkns"); + case INSN_CLASS_ZVKSED: + return riscv_subset_supports (rps, "zvksed"); case INSN_CLASS_SVINVAL: return riscv_subset_supports (rps, "svinval"); case INSN_CLASS_H: @@ -2541,6 +2544,8 @@ riscv_multi_subset_supports_ext (riscv_parse_subset_t *rps, return _("zvknhb"); case INSN_CLASS_ZVKNS: return _("zvkns"); + case INSN_CLASS_ZVKSED: + return _("zvksed"); case INSN_CLASS_SVINVAL: return "svinval"; case INSN_CLASS_H: diff --git a/gas/testsuite/gas/riscv/zvksed.d b/gas/testsuite/gas/riscv/zvksed.d new file mode 100644 index 00000000000..48b4aafdbb1 --- /dev/null +++ b/gas/testsuite/gas/riscv/zvksed.d @@ -0,0 +1,12 @@ +#as: -march=rv64gc_zvksed +#objdump: -dr + +.*:[ ]+file format .* + + +Disassembly of section .text: +0+000 <.text>: +[ ]+[0-9a-f]+:[ ]+86802277[ ]+vsm4k.vi[ ]+v4,v8,0 +[ ]+[0-9a-f]+:[ ]+8683a277[ ]+vsm4k.vi[ ]+v4,v8,7 +[ ]+[0-9a-f]+:[ ]+a2882277[ ]+vsm4r.vv[ ]+v4,v8 +[ ]+[0-9a-f]+:[ ]+a6882277[ ]+vsm4r.vs[ ]+v4,v8 diff --git a/gas/testsuite/gas/riscv/zvksed.s b/gas/testsuite/gas/riscv/zvksed.s new file mode 100644 index 00000000000..754b4646adf --- /dev/null +++ b/gas/testsuite/gas/riscv/zvksed.s @@ -0,0 +1,4 @@ + vsm4k.vi v4, v8, 0 + vsm4k.vi v4, v8, 7 + vsm4r.vv v4, v8 + vsm4r.vs v4, v8 diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h index e04169b5343..0a1fd0b69e8 100644 --- a/include/opcode/riscv-opc.h +++ b/include/opcode/riscv-opc.h @@ -2117,6 +2117,13 @@ #define MASK_VAESKF2VI 0xfe00707f #define MATCH_VAESZVS 0xa603a077 #define MASK_VAESZVS 0xfe0ff07f +/* Zvksed instructions. */ +#define MATCH_VSM4KVI 0x86002077 +#define MASK_VSM4KVI 0xfe00707f +#define MATCH_VSM4RVV 0xa2082077 +#define MASK_VSM4RVV 0xfe0ff07f +#define MATCH_VSM4RVS 0xa6082077 +#define MASK_VSM4RVS 0xfe0ff07f /* Svinval instruction. */ #define MATCH_SINVAL_VMA 0x16000073 #define MASK_SINVAL_VMA 0xfe007fff @@ -3213,6 +3220,10 @@ DECLARE_INSN(vaesemvs, MATCH_VAESEMVS, MASK_VAESEMVS) DECLARE_INSN(vaeskf1vi, MATCH_VAESKF1VI, MASK_VAESKF1VI) DECLARE_INSN(vaeskf2vi, MATCH_VAESKF2VI, MASK_VAESKF2VI) DECLARE_INSN(vaeszvs, MATCH_VAESZVS, MASK_VAESZVS) +/* Zvksed instructions. */ +DECLARE_INSN(vsm4kvi, MATCH_VSM4KVI, MASK_VSM4KVI) +DECLARE_INSN(vsm4rvv, MATCH_VSM4RVV, MASK_VSM4RVV) +DECLARE_INSN(vsm4rvs, MATCH_VSM4RVS, MASK_VSM4RVS) /* Vendor-specific (T-Head) XTheadBa instructions. */ DECLARE_INSN(th_addsl, MATCH_TH_ADDSL, MASK_TH_ADDSL) /* Vendor-specific (T-Head) XTheadBb instructions. */ diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h index 48db408f303..c2d70728749 100644 --- a/include/opcode/riscv.h +++ b/include/opcode/riscv.h @@ -415,6 +415,7 @@ enum riscv_insn_class INSN_CLASS_ZVKNHB, INSN_CLASS_ZVKNHA_OR_ZVKNHB, INSN_CLASS_ZVKNS, + INSN_CLASS_ZVKSED, INSN_CLASS_SVINVAL, INSN_CLASS_ZICBOM, INSN_CLASS_ZICBOP, diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c index a7f79f8fe68..1a4b3738744 100644 --- a/opcodes/riscv-opc.c +++ b/opcodes/riscv-opc.c @@ -1852,6 +1852,11 @@ const struct riscv_opcode riscv_opcodes[] = {"vaeskf2.vi", 0, INSN_CLASS_ZVKNS, "Vd,Vt,Vj", MATCH_VAESKF2VI, MASK_VAESKF2VI, match_opcode, 0}, {"vaesz.vs", 0, INSN_CLASS_ZVKNS, "Vd,Vt", MATCH_VAESZVS, MASK_VAESZVS, match_opcode, 0}, +/* Zvksed instructions. */ +{"vsm4k.vi", 0, INSN_CLASS_ZVKSED, "Vd,Vt,Vj", MATCH_VSM4KVI, MASK_VSM4KVI, match_opcode, 0}, +{"vsm4r.vv", 0, INSN_CLASS_ZVKSED, "Vd,Vt", MATCH_VSM4RVV, MASK_VSM4RVV, match_opcode, 0}, +{"vsm4r.vs", 0, INSN_CLASS_ZVKSED, "Vd,Vt", MATCH_VSM4RVS, MASK_VSM4RVS, match_opcode, 0}, + /* Supervisor instructions. */ {"csrr", 0, INSN_CLASS_ZICSR, "d,E", MATCH_CSRRS, MASK_CSRRS|MASK_RS1, match_opcode, INSN_ALIAS }, {"csrw", 0, INSN_CLASS_ZICSR, "E,s", MATCH_CSRRW, MASK_CSRRW|MASK_RD, match_opcode, INSN_ALIAS }, -- 2.39.0