From: Christoph Muellner <christoph.muellner@vrull.eu>
To: binutils@sourceware.org, Nelson Chu <nelson@rivosinc.com>,
Andrew Waterman <andrew@sifive.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Jim Wilson <jim.wilson.gcc@gmail.com>,
Philipp Tomsich <philipp.tomsich@vrull.eu>,
Elda Kuka <elda.kuka@vrull.eu>,
Aaron Durbin <adurbin@rivosinc.com>,
Andrew de los Reyes <adlr@rivosinc.com>,
Eric Gouriou <ego@rivosinc.com>,
Barna Ibrahim <barna@rivosinc.com>,
Jeff Law <jeffreyalaw@gmail.com>
Cc: "Christoph Müllner" <christoph.muellner@vrull.eu>
Subject: [RFC PATCH v3 2/8] RISC-V: Add Zvkg ISA extension support
Date: Mon, 13 Feb 2023 14:39:43 +0100 [thread overview]
Message-ID: <20230213133949.3773320-3-christoph.muellner@vrull.eu> (raw)
In-Reply-To: <20230213133949.3773320-1-christoph.muellner@vrull.eu>
From: Christoph Müllner <christoph.muellner@vrull.eu>
This commit adds the Zvkg ISA extension instruction, which is part
of the vector crypto extensions.
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
---
Changes in v3:
- Updated to spec v0.3.0 (2023-02-06)
- Removed vghmac.vv
- Added vghsh.vv and vgmul.vv
bfd/elfxx-riscv.c | 5 +++++
gas/testsuite/gas/riscv/zvkg.d | 10 ++++++++++
gas/testsuite/gas/riscv/zvkg.s | 2 ++
include/opcode/riscv-opc.h | 8 ++++++++
include/opcode/riscv.h | 1 +
opcodes/riscv-opc.c | 4 ++++
6 files changed, 30 insertions(+)
create mode 100644 gas/testsuite/gas/riscv/zvkg.d
create mode 100644 gas/testsuite/gas/riscv/zvkg.s
diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
index c9952a51c3c..9e0dee9cc72 100644
--- a/bfd/elfxx-riscv.c
+++ b/bfd/elfxx-riscv.c
@@ -1206,6 +1206,7 @@ static struct riscv_supported_ext riscv_supported_std_z_ext[] =
{"zve64f", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"zve64d", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"zvkb", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
+ {"zvkg", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"zvl32b", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"zvl64b", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"zvl128b", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
@@ -2358,6 +2359,8 @@ riscv_multi_subset_supports (riscv_parse_subset_t *rps,
|| riscv_subset_supports (rps, "zve32f"));
case INSN_CLASS_ZVKB:
return riscv_subset_supports (rps, "zvkb");
+ case INSN_CLASS_ZVKG:
+ return riscv_subset_supports (rps, "zvkg");
case INSN_CLASS_SVINVAL:
return riscv_subset_supports (rps, "svinval");
case INSN_CLASS_H:
@@ -2518,6 +2521,8 @@ riscv_multi_subset_supports_ext (riscv_parse_subset_t *rps,
return _("v' or `zve64d' or `zve64f' or `zve32f");
case INSN_CLASS_ZVKB:
return _("zvkb");
+ case INSN_CLASS_ZVKG:
+ return _("zvkg");
case INSN_CLASS_SVINVAL:
return "svinval";
case INSN_CLASS_H:
diff --git a/gas/testsuite/gas/riscv/zvkg.d b/gas/testsuite/gas/riscv/zvkg.d
new file mode 100644
index 00000000000..7f898d377b2
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zvkg.d
@@ -0,0 +1,10 @@
+#as: -march=rv64gc_zvkg
+#objdump: -dr
+
+.*:[ ]+file format .*
+
+
+Disassembly of section .text:
+0+000 <.text>:
+[ ]+[0-9a-f]+:[ ]+b2862277[ ]+vghsh.vv[ ]+v4,v8,v12
+[ ]+[0-9a-f]+:[ ]+a2c8a277[ ]+vgmul.vv[ ]+v4,v12
diff --git a/gas/testsuite/gas/riscv/zvkg.s b/gas/testsuite/gas/riscv/zvkg.s
new file mode 100644
index 00000000000..b802d6add39
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zvkg.s
@@ -0,0 +1,2 @@
+ vghsh.vv v4, v8, v12
+ vgmul.vv v4, v12
diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h
index bdcb3e442f8..03eda5a9e49 100644
--- a/include/opcode/riscv-opc.h
+++ b/include/opcode/riscv-opc.h
@@ -2084,6 +2084,11 @@
#define MASK_VANDNVX 0xfc00707f
#define MATCH_VANDNVI 0x04003057
#define MASK_VANDNVI 0xfc00707f
+/* Zvkg instructions. */
+#define MATCH_VGHSHVV 0xb2002077
+#define MASK_VGHSHVV 0xfe00707f
+#define MATCH_VGMULVV 0xa208a077
+#define MASK_VGMULVV 0xfe0ff07f
/* Svinval instruction. */
#define MATCH_SINVAL_VMA 0x16000073
#define MASK_SINVAL_VMA 0xfe007fff
@@ -3162,6 +3167,9 @@ DECLARE_INSN(vrev8v, MATCH_VREV8V, MASK_VREV8V)
DECLARE_INSN(vandnvv, MATCH_VANDNVV, MASK_VANDNVV)
DECLARE_INSN(vandnvx, MATCH_VANDNVX, MASK_VANDNVX)
DECLARE_INSN(vandnvi, MATCH_VANDNVI, MASK_VANDNVI)
+/* Zvkg instructions. */
+DECLARE_INSN(vghshvv, MATCH_VGHASHVV, MASK_VGHASHVV)
+DECLARE_INSN(vgmulvv, MATCH_VGMULTVV, MASK_VGMULTVV)
/* Vendor-specific (T-Head) XTheadBa instructions. */
DECLARE_INSN(th_addsl, MATCH_TH_ADDSL, MASK_TH_ADDSL)
/* Vendor-specific (T-Head) XTheadBb instructions. */
diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h
index cc3950f56b8..9e883f030d6 100644
--- a/include/opcode/riscv.h
+++ b/include/opcode/riscv.h
@@ -410,6 +410,7 @@ enum riscv_insn_class
INSN_CLASS_V,
INSN_CLASS_ZVEF,
INSN_CLASS_ZVKB,
+ INSN_CLASS_ZVKG,
INSN_CLASS_SVINVAL,
INSN_CLASS_ZICBOM,
INSN_CLASS_ZICBOP,
diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
index 4d0c5a4ec37..0bb0bb4cce7 100644
--- a/opcodes/riscv-opc.c
+++ b/opcodes/riscv-opc.c
@@ -1831,6 +1831,10 @@ const struct riscv_opcode riscv_opcodes[] =
{"vandn.vx", 0, INSN_CLASS_ZVKB, "Vd,Vt,sVm", MATCH_VANDNVX, MASK_VANDNVX, match_opcode, 0},
{"vandn.vi", 0, INSN_CLASS_ZVKB, "Vd,Vt,ViVm", MATCH_VANDNVI, MASK_VANDNVI, match_opcode, 0},
+/* Zvkg instructions. */
+{"vghsh.vv", 0, INSN_CLASS_ZVKG, "Vd,Vt,Vs", MATCH_VGHSHVV, MASK_VGHSHVV, match_opcode, 0},
+{"vgmul.vv", 0, INSN_CLASS_ZVKG, "Vd,Vt", MATCH_VGMULVV, MASK_VGMULVV, match_opcode, 0},
+
/* Supervisor instructions. */
{"csrr", 0, INSN_CLASS_ZICSR, "d,E", MATCH_CSRRS, MASK_CSRRS|MASK_RS1, match_opcode, INSN_ALIAS },
{"csrw", 0, INSN_CLASS_ZICSR, "E,s", MATCH_CSRRW, MASK_CSRRW|MASK_RD, match_opcode, INSN_ALIAS },
--
2.39.1
next prev parent reply other threads:[~2023-02-13 13:39 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-02-13 13:39 [RFC PATCH v3 0/8] RISC-V: Add support for vector crypto extensions Christoph Muellner
2023-02-13 13:39 ` [RFC PATCH v3 1/8] RISC-V: Add Zvkb ISA extension support Christoph Muellner
2023-02-13 13:39 ` Christoph Muellner [this message]
2023-02-13 13:39 ` [RFC PATCH v3 3/8] RISC-V: Add Zvkned " Christoph Muellner
2023-02-13 13:39 ` [RFC PATCH v3 4/8] RISC-V: Add Zvknh[a,b] " Christoph Muellner
2023-02-13 13:39 ` [RFC PATCH v3 5/8] RISC-V: Add Zvkn " Christoph Muellner
2023-02-13 13:39 ` [RFC PATCH v3 6/8] RISC-V: Add Zvksed " Christoph Muellner
2023-02-13 13:39 ` [RFC PATCH v3 7/8] RISC-V: Add Zvksh " Christoph Muellner
2023-02-13 13:39 ` [RFC PATCH v3 8/8] RISC-V: Add Zvks " Christoph Muellner
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