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[62.178.148.172]) by smtp.gmail.com with ESMTPSA id qh7-20020a170906eca700b0092bea699124sm13797144ejb.106.2023.03.27.01.01.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 Mar 2023 01:01:09 -0700 (PDT) From: Christoph Muellner To: binutils@sourceware.org, Nelson Chu , Andrew Waterman , Palmer Dabbelt , Jim Wilson , Philipp Tomsich , Jeff Law , Tsukasa OI Cc: =?UTF-8?q?Christoph=20M=C3=BCllner?= Subject: [RFC PATCH v2 0/2] RISC-V: Add support for the Zfa extension Date: Mon, 27 Mar 2023 10:01:05 +0200 Message-Id: <20230327080107.3266866-1-christoph.muellner@vrull.eu> X-Mailer: git-send-email 2.39.2 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-6.7 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,JMQ_SPF_NEUTRAL,KAM_MANYTO,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: From: Christoph Müllner This series adds support for the RISC-V Zfa extension. It consists of two patches: 1) A clean-up patch from Tsukasa that improves the way we structure format string directives. 2) A patch that introduces support for the Zfa extension. The first patch does not have any dependencies and is suggested to get merged as early as possible. The second patch can land once the Zfa specification gets frozen. Some additional bits to get the full context: * Tsukasa wrote a first version, which can be found here: https://sourceware.org/pipermail/binutils/2022-September/122939.html * I took over the patch as agreed here: https://sourceware.org/pipermail/binutils/2023-March/126753.html There is also a discussion how to represent the constants in the assembly notation. I've decided to use C-like constants, as I consider this as the most user-friedly form for assembly programmers (for examples see gas/testsuite/gas/riscv/zfa.s). I prefer to not support the RS1-constants or the hex-encoded register values that will land in the floating-point registers, as I want to avoid misinterpretation because of multiple allowed notations. If another notation is preferred, then please let me know. Christoph Müllner (1): RISC-V: Add support for the Zfa extension Tsukasa OI (1): RISC-V: Allocate "various" operand type bfd/elfxx-riscv.c | 39 ++++++++++++ gas/config/tc-riscv.c | 89 ++++++++++++++++++++++----- gas/testsuite/gas/riscv/zfa-32.d | 10 +++ gas/testsuite/gas/riscv/zfa-32.s | 3 + gas/testsuite/gas/riscv/zfa-64.d | 10 +++ gas/testsuite/gas/riscv/zfa-64.s | 3 + gas/testsuite/gas/riscv/zfa-fail.d | 2 + gas/testsuite/gas/riscv/zfa-fail.l | 33 ++++++++++ gas/testsuite/gas/riscv/zfa-fail.s | 26 ++++++++ gas/testsuite/gas/riscv/zfa.d | 89 +++++++++++++++++++++++++++ gas/testsuite/gas/riscv/zfa.s | 87 ++++++++++++++++++++++++++ include/opcode/riscv-opc.h | 99 ++++++++++++++++++++++++++++++ include/opcode/riscv.h | 5 ++ opcodes/riscv-dis.c | 38 ++++++++++-- opcodes/riscv-opc.c | 59 +++++++++++++++++- 15 files changed, 567 insertions(+), 25 deletions(-) create mode 100644 gas/testsuite/gas/riscv/zfa-32.d create mode 100644 gas/testsuite/gas/riscv/zfa-32.s create mode 100644 gas/testsuite/gas/riscv/zfa-64.d create mode 100644 gas/testsuite/gas/riscv/zfa-64.s create mode 100644 gas/testsuite/gas/riscv/zfa-fail.d create mode 100644 gas/testsuite/gas/riscv/zfa-fail.l create mode 100644 gas/testsuite/gas/riscv/zfa-fail.s create mode 100644 gas/testsuite/gas/riscv/zfa.d create mode 100644 gas/testsuite/gas/riscv/zfa.s -- 2.39.2