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From: Richard Sandiford <richard.sandiford@arm.com>
To: binutils@sourceware.org
Cc: Richard Sandiford <richard.sandiford@arm.com>
Subject: [PATCH 10/43] aarch64: Reuse parse_typed_reg for ZA tiles
Date: Thu, 30 Mar 2023 11:23:26 +0100	[thread overview]
Message-ID: <20230330102359.3327695-11-richard.sandiford@arm.com> (raw)
In-Reply-To: <20230330102359.3327695-1-richard.sandiford@arm.com>

This patch reuses the general parse_typed_reg for ZA tiles.
This involves adding a way of suppressing the usual treatment
of register indices, since ZA indices look very different from
Advanced SIMD and SVE vector indices.
---
 gas/config/tc-aarch64.c | 98 ++++++++++++++++++++---------------------
 1 file changed, 47 insertions(+), 51 deletions(-)

diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c
index 8c3d627a08b..f9e85b3d803 100644
--- a/gas/config/tc-aarch64.c
+++ b/gas/config/tc-aarch64.c
@@ -906,7 +906,7 @@ parse_vector_type_for_operand (aarch64_reg_type reg_type,
   gas_assert (*ptr == '.');
   ptr++;
 
-  if (reg_type == REG_TYPE_ZN || reg_type == REG_TYPE_PN || !ISDIGIT (*ptr))
+  if (reg_type != REG_TYPE_VN || !ISDIGIT (*ptr))
     {
       width = 0;
       goto elt_size;
@@ -938,7 +938,7 @@ parse_vector_type_for_operand (aarch64_reg_type reg_type,
       element_size = 64;
       break;
     case 'q':
-      if (reg_type == REG_TYPE_ZN || width == 1)
+      if (reg_type != REG_TYPE_VN || width == 1)
 	{
 	  type = NT_q;
 	  element_size = 128;
@@ -1004,6 +1004,29 @@ parse_predication_for_operand (struct vector_type_el *parsed_type, char **str)
   return true;
 }
 
+/* Return true if CH is a valid suffix character for registers of
+   type TYPE.  */
+
+static bool
+aarch64_valid_suffix_char_p (aarch64_reg_type type, char ch)
+{
+  switch (type)
+    {
+    case REG_TYPE_VN:
+    case REG_TYPE_ZN:
+    case REG_TYPE_ZAT:
+    case REG_TYPE_ZATH:
+    case REG_TYPE_ZATV:
+      return ch == '.';
+
+    case REG_TYPE_PN:
+      return ch == '.' || ch == '/';
+
+    default:
+      return false;
+    }
+}
+
 /* Parse a register of the type TYPE.
 
    Return null if the string pointed to by *CCP is not a valid register
@@ -1012,9 +1035,13 @@ parse_predication_for_operand (struct vector_type_el *parsed_type, char **str)
    Otherwise return the register, and optionally return the register
    shape and element index information in *TYPEINFO.
 
-   FLAGS includes PTR_IN_REGLIST if the caller is parsing a register list.  */
+   FLAGS includes PTR_IN_REGLIST if the caller is parsing a register list.
+
+   FLAGS includes PTR_FULL_REG if the function should ignore any potential
+   register index.  */
 
 #define PTR_IN_REGLIST (1U << 0)
+#define PTR_FULL_REG (1U << 1)
 
 static const reg_entry *
 parse_typed_reg (char **ccp, aarch64_reg_type type,
@@ -1047,8 +1074,7 @@ parse_typed_reg (char **ccp, aarch64_reg_type type,
     }
   type = reg->type;
 
-  if ((type == REG_TYPE_VN || type == REG_TYPE_ZN || type == REG_TYPE_PN)
-      && (*str == '.' || (type == REG_TYPE_PN && *str == '/')))
+  if (aarch64_valid_suffix_char_p (reg->type, *str))
     {
       if (*str == '.')
 	{
@@ -1064,7 +1090,7 @@ parse_typed_reg (char **ccp, aarch64_reg_type type,
       /* Register if of the form Vn.[bhsdq].  */
       is_typed_vecreg = true;
 
-      if (type == REG_TYPE_ZN || type == REG_TYPE_PN)
+      if (type != REG_TYPE_VN)
 	{
 	  /* The width is always variable; we don't allow an integer width
 	     to be specified.  */
@@ -1084,7 +1110,7 @@ parse_typed_reg (char **ccp, aarch64_reg_type type,
       atype.width = parsetype.width;
     }
 
-  if (skip_past_char (&str, '['))
+  if (!(flags & PTR_FULL_REG) && skip_past_char (&str, '['))
     {
       expressionS exp;
 
@@ -4304,45 +4330,17 @@ static const reg_entry *
 parse_reg_with_qual (char **str, aarch64_reg_type reg_type,
                      aarch64_opnd_qualifier_t *qualifier)
 {
-  char *q;
-
-  reg_entry *reg = parse_reg (str);
-  if (reg != NULL && aarch64_check_reg_type (reg, reg_type))
-    {
-      if (!skip_past_char (str, '.'))
-        {
-          set_syntax_error (_("missing ZA tile element size separator"));
-          return NULL;
-        }
-
-      q = *str;
-      switch (TOLOWER (*q))
-        {
-        case 'b':
-          *qualifier = AARCH64_OPND_QLF_S_B;
-          break;
-        case 'h':
-          *qualifier = AARCH64_OPND_QLF_S_H;
-          break;
-        case 's':
-          *qualifier = AARCH64_OPND_QLF_S_S;
-          break;
-        case 'd':
-          *qualifier = AARCH64_OPND_QLF_S_D;
-          break;
-        case 'q':
-          *qualifier = AARCH64_OPND_QLF_S_Q;
-          break;
-        default:
-          return NULL;
-        }
-      q++;
+  struct vector_type_el vectype;
+  const reg_entry *reg = parse_typed_reg (str, reg_type, &vectype,
+					  PTR_FULL_REG);
+  if (!reg)
+    return NULL;
 
-      *str = q;
-      return reg;
-    }
+  *qualifier = vectype_to_qualifier (&vectype);
+  if (*qualifier == AARCH64_OPND_QLF_NIL)
+    return NULL;
 
-  return NULL;
+  return reg;
 }
 
 /* Parse SME ZA tile encoded in <ZAda> assembler symbol.
@@ -4641,19 +4639,17 @@ parse_sme_zero_mask(char **str)
             }
           continue;
         }
-      else if (strncasecmp (q, "za", 2) == 0
-               && !ISALNUM (q[2]))
+      clear_error ();
+      if (strncasecmp (q, "za", 2) == 0 && !ISALNUM (q[2]))
         {
           /* { ZA } is assembled as all-ones immediate.  */
           mask = 0xff;
           q += 2;
           continue;
         }
-      else
-        {
-          set_syntax_error (_("wrong ZA tile element format"));
-          return PARSE_FAIL;
-        }
+
+      set_syntax_error (_("wrong ZA tile element format"));
+      return PARSE_FAIL;
     }
   while (skip_past_char (&q, ','));
 
-- 
2.25.1


  parent reply	other threads:[~2023-03-30 10:24 UTC|newest]

Thread overview: 46+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-03-30 10:23 [PATCH 00/43] aarch64: Groundwork for SME2 support Richard Sandiford
2023-03-30 10:23 ` [PATCH 01/43] aarch64: Fix PSEL opcode mask Richard Sandiford
2023-03-30 10:23 ` [PATCH 02/43] aarch64: Restrict range of PRFM opcodes Richard Sandiford
2023-03-30 10:23 ` [PATCH 03/43] aarch64: Fix SVE2 register/immediate distinction Richard Sandiford
2023-03-30 10:23 ` [PATCH 04/43] aarch64: Make SME instructions use F_STRICT Richard Sandiford
2023-03-30 10:23 ` [PATCH 05/43] aarch64: Use aarch64_operand_error more widely Richard Sandiford
2023-03-30 10:23 ` [PATCH 06/43] aarch64: Rename REG_TYPE_ZA* to REG_TYPE_ZAT* Richard Sandiford
2023-03-30 10:23 ` [PATCH 07/43] aarch64: Add REG_TYPE_ZATHV Richard Sandiford
2023-03-30 10:23 ` [PATCH 08/43] aarch64: Move vectype_to_qualifier further up Richard Sandiford
2023-03-30 10:23 ` [PATCH 09/43] aarch64: Rework parse_typed_reg interface Richard Sandiford
2023-03-30 10:23 ` Richard Sandiford [this message]
2023-03-30 10:23 ` [PATCH 11/43] aarch64: Consolidate ZA tile range checks Richard Sandiford
2023-03-30 10:23 ` [PATCH 12/43] aarch64: Treat ZA as a register Richard Sandiford
2023-03-30 10:23 ` [PATCH 13/43] aarch64: Rename za_tile_vector to za_index Richard Sandiford
2023-03-30 10:23 ` [PATCH 14/43] aarch64: Make indexed_za use 64-bit immediates Richard Sandiford
2023-03-30 10:23 ` [PATCH 15/43] aarch64: Pass aarch64_indexed_za to parsers Richard Sandiford
2023-03-30 10:23 ` [PATCH 16/43] aarch64: Move ZA range checks to aarch64-opc.c Richard Sandiford
2023-03-30 10:23 ` [PATCH 17/43] aarch64: Consolidate ZA slice parsing Richard Sandiford
2023-03-30 10:23 ` [PATCH 18/43] aarch64: Commonise index parsing Richard Sandiford
2023-03-30 10:23 ` [PATCH 19/43] aarch64: Move w12-w15 range check to libopcodes Richard Sandiford
2023-03-30 10:23 ` [PATCH 20/43] aarch64: Tweak error for missing immediate offset Richard Sandiford
2023-03-30 10:23 ` [PATCH 21/43] aarch64: Tweak errors for base & offset registers Richard Sandiford
2023-03-30 10:23 ` [PATCH 22/43] aarch64: Tweak parsing of integer & FP registers Richard Sandiford
2023-03-30 10:23 ` [PATCH 23/43] aarch64: Improve errors for malformed register lists Richard Sandiford
2023-03-30 10:23 ` [PATCH 24/43] aarch64: Try to avoid inappropriate default errors Richard Sandiford
2023-03-30 10:23 ` [PATCH 25/43] aarch64: Rework reporting of failed register checks Richard Sandiford
2023-03-30 10:23 ` [PATCH 26/43] aarch64: Update operand_mismatch_kind_names Richard Sandiford
2023-03-30 10:23 ` [PATCH 27/43] aarch64: Deprioritise AARCH64_OPDE_REG_LIST Richard Sandiford
2023-03-30 10:23 ` [PATCH 28/43] aarch64: Add an error code for out-of-range registers Richard Sandiford
2023-03-30 10:23 ` [PATCH 29/43] aarch64: Commonise checks for index operands Richard Sandiford
2023-03-30 10:23 ` [PATCH 30/43] aarch64: Add an operand class for SVE register lists Richard Sandiford
2023-03-30 10:23 ` [PATCH 31/43] aarch64: Make AARCH64_OPDE_REG_LIST take a bitfield Richard Sandiford
2023-03-30 10:23 ` [PATCH 32/43] aarch64: Tweak register list errors Richard Sandiford
2023-03-30 10:23 ` [PATCH 33/43] aarch64: Try to report invalid variants against the closest match Richard Sandiford
2023-03-30 10:23 ` [PATCH 34/43] aarch64: Tweak priorities of parsing-related errors Richard Sandiford
2023-03-30 10:23 ` [PATCH 35/43] aarch64: Rename aarch64-tbl.h OP_SME_* macros Richard Sandiford
2023-03-30 10:23 ` [PATCH 36/43] aarch64: Reorder some OP_SVE_* macros Richard Sandiford
2023-03-30 10:23 ` [PATCH 37/43] aarch64: Add a aarch64_cpu_supports_inst_p helper Richard Sandiford
2023-03-30 10:23 ` [PATCH 38/43] aarch64: Rename some of GAS's REG_TYPE_* macros Richard Sandiford
2023-03-30 10:23 ` [PATCH 39/43] aarch64: Regularise FLD_* suffixes Richard Sandiford
2023-03-30 10:23 ` [PATCH 40/43] aarch64: Resync field names Richard Sandiford
2023-03-30 10:23 ` [PATCH 41/43] aarch64: Sort fields alphanumerically Richard Sandiford
2023-03-30 10:23 ` [PATCH 42/43] aarch64: Add support for strided register lists Richard Sandiford
2023-03-30 15:50   ` Simon Marchi
2023-03-30 16:06     ` Richard Sandiford
2023-03-30 10:23 ` [PATCH 43/43] aarch64: Prefer register ranges & support wrapping Richard Sandiford

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