From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by sourceware.org (Postfix) with ESMTP id 9EAA43858CDB for ; Thu, 30 Mar 2023 10:24:15 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 9EAA43858CDB Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id B371A12FC; Thu, 30 Mar 2023 03:24:59 -0700 (PDT) Received: from e121540-lin.manchester.arm.com (e121540-lin.manchester.arm.com [10.32.110.72]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id EA9D63F663; Thu, 30 Mar 2023 03:24:14 -0700 (PDT) From: Richard Sandiford To: binutils@sourceware.org Cc: Richard Sandiford Subject: [PATCH 01/43] aarch64: Fix PSEL opcode mask Date: Thu, 30 Mar 2023 11:23:17 +0100 Message-Id: <20230330102359.3327695-2-richard.sandiford@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230330102359.3327695-1-richard.sandiford@arm.com> References: <20230330102359.3327695-1-richard.sandiford@arm.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-33.4 required=5.0 tests=BAYES_00,GIT_PATCH_0,KAM_DMARC_NONE,KAM_DMARC_STATUS,KAM_LAZY_DOMAIN_SECURITY,SPF_HELO_NONE,SPF_NONE,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: The opcode mask for PSEL was missing some bits, which meant that some upcoming SME2 opcodes would be misinterpreted as PSELs. --- gas/testsuite/gas/aarch64/sme-9.d | 3 +++ gas/testsuite/gas/aarch64/sme-9.s | 5 +++++ opcodes/aarch64-tbl.h | 2 +- 3 files changed, 9 insertions(+), 1 deletion(-) diff --git a/gas/testsuite/gas/aarch64/sme-9.d b/gas/testsuite/gas/aarch64/sme-9.d index ef314c61451..9a6175c3906 100644 --- a/gas/testsuite/gas/aarch64/sme-9.d +++ b/gas/testsuite/gas/aarch64/sme-9.d @@ -71,3 +71,6 @@ Disassembly of section \.text: f4: 44cbc544 uclamp z4.d, z10.d, z11.d f8: 25277c61 psel p1, p15, p3.b\[w15, 0\] fc: 252778a2 psel p2, p14, p5.b\[w15, 0\] + 100: 25244200 \.inst 0x25244200 ; undefined + 104: 25244010 \.inst 0x25244010 ; undefined + 108: 25244210 \.inst 0x25244210 ; undefined diff --git a/gas/testsuite/gas/aarch64/sme-9.s b/gas/testsuite/gas/aarch64/sme-9.s index be8511fe3df..495a7f9fbf0 100644 --- a/gas/testsuite/gas/aarch64/sme-9.s +++ b/gas/testsuite/gas/aarch64/sme-9.s @@ -84,3 +84,8 @@ foo .req p1 bar .req w15 psel foo, p15, p3.b[w15, 0] psel p2, p14, p5.b[bar, 0] + +// These were previously incorrectly decoded as PSELs. +.inst 0x25244200 +.inst 0x25244010 +.inst 0x25244210 diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h index 69703650471..96e6c136282 100644 --- a/opcodes/aarch64-tbl.h +++ b/opcodes/aarch64-tbl.h @@ -5275,7 +5275,7 @@ const struct aarch64_opcode aarch64_opcode_table[] = SME_INSNC ("revd", 0x52e8000, 0xffffe000, sme_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_QMQ, 0, C_SCAN_MOVPRFX, 0), SME_INSNC ("sclamp", 0x4400c000, 0xff20fc00, sve_size_bhsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_BHSD, 0, C_SCAN_MOVPRFX, 0), SME_INSNC ("uclamp", 0x4400c400, 0xff20fc00, sve_size_bhsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_BHSD, 0, C_SCAN_MOVPRFX, 0), - SME_INSN ("psel", 0x25204000, 0xff20c000, sme_misc, 0, OP3 (SVE_Pd, SVE_Pg4_10, SME_PnT_Wm_imm), OP_SVE_NN_BHSD, 0, 0), + SME_INSN ("psel", 0x25204000, 0xff20c210, sme_misc, 0, OP3 (SVE_Pd, SVE_Pg4_10, SME_PnT_Wm_imm), OP_SVE_NN_BHSD, 0, 0), /* SIMD Dot Product (optional in v8.2-A). */ DOT_INSN ("udot", 0x2e009400, 0xbf20fc00, dotproduct, OP3 (Vd, Vn, Vm), QL_V3DOT, F_SIZEQ), -- 2.25.1