From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by sourceware.org (Postfix) with ESMTP id B5720385841D for ; Thu, 30 Mar 2023 10:24:31 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org B5720385841D Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id E25811596; Thu, 30 Mar 2023 03:25:15 -0700 (PDT) Received: from e121540-lin.manchester.arm.com (e121540-lin.manchester.arm.com [10.32.110.72]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 256213F663; Thu, 30 Mar 2023 03:24:31 -0700 (PDT) From: Richard Sandiford To: binutils@sourceware.org Cc: Richard Sandiford Subject: [PATCH 24/43] aarch64: Try to avoid inappropriate default errors Date: Thu, 30 Mar 2023 11:23:40 +0100 Message-Id: <20230330102359.3327695-25-richard.sandiford@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230330102359.3327695-1-richard.sandiford@arm.com> References: <20230330102359.3327695-1-richard.sandiford@arm.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-33.0 required=5.0 tests=BAYES_00,GIT_PATCH_0,KAM_DMARC_NONE,KAM_DMARC_STATUS,KAM_LAZY_DOMAIN_SECURITY,SPF_HELO_NONE,SPF_NONE,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: After parsing a '{' and the first register, parse_typed_reg would report errors in subsequent registers in the same way as for the first register. It used set_default_error, which reports errors of the form "operand N must be X". The problem is that if there are multiple opcode entries for the same mnemonic, there could be several matches that lead to a default error. There's no guarantee that the default error for the register list is the one that will be chosen. To take an example from the testsuite: ext z0.b,{z31.b,z32.b},#0 gave: operand 2 must be an SVE vector register with the error being reported against the single-vector version of ext, even though the operand is clearly a list. This patch uses set_fatal_syntax_error to bump the priority of the error once we're sure that the operand is a list of the right type. --- gas/config/tc-aarch64.c | 21 +++++++++++++++++---- gas/testsuite/gas/aarch64/illegal-sve2.l | 2 +- gas/testsuite/gas/aarch64/sme-4-illegal.l | 2 ++ gas/testsuite/gas/aarch64/sme-4-illegal.s | 2 ++ gas/testsuite/gas/aarch64/sve-invalid.l | 2 ++ gas/testsuite/gas/aarch64/sve-invalid.s | 2 ++ 6 files changed, 26 insertions(+), 5 deletions(-) diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c index 596cc0f0813..616454b584e 100644 --- a/gas/config/tc-aarch64.c +++ b/gas/config/tc-aarch64.c @@ -1073,10 +1073,14 @@ parse_index_expression (char **str, int64_t *imm) FLAGS includes PTR_IN_REGLIST if the caller is parsing a register list. FLAGS includes PTR_FULL_REG if the function should ignore any potential - register index. */ + register index. + + FLAGS includes PTR_GOOD_MATCH if we are sufficiently far into parsing + an operand that we can be confident that it is a good match. */ #define PTR_IN_REGLIST (1U << 0) #define PTR_FULL_REG (1U << 1) +#define PTR_GOOD_MATCH (1U << 2) static const reg_entry * parse_typed_reg (char **ccp, aarch64_reg_type type, @@ -1101,6 +1105,8 @@ parse_typed_reg (char **ccp, aarch64_reg_type type, *typeinfo = atype; if (!isalpha && (flags & PTR_IN_REGLIST)) set_fatal_syntax_error (_("syntax error in register list")); + else if (flags & PTR_GOOD_MATCH) + set_fatal_syntax_error (NULL); else set_default_error (); return NULL; @@ -1109,7 +1115,10 @@ parse_typed_reg (char **ccp, aarch64_reg_type type, if (! aarch64_check_reg_type (reg, type)) { DEBUG_TRACE ("reg type check failed"); - set_default_error (); + if (flags & PTR_GOOD_MATCH) + set_fatal_syntax_error (NULL); + else + set_default_error (); return NULL; } type = reg->type; @@ -1262,6 +1271,7 @@ parse_vector_reg_list (char **ccp, aarch64_reg_type type, int i; bool error = false; bool expect_index = false; + unsigned int ptr_flags = PTR_IN_REGLIST; if (*str != '{') { @@ -1288,7 +1298,7 @@ parse_vector_reg_list (char **ccp, aarch64_reg_type type, val_range = val; } const reg_entry *reg = parse_typed_reg (&str, type, &typeinfo, - PTR_IN_REGLIST); + ptr_flags); if (!reg) { set_first_syntax_error (_("invalid vector register in list")); @@ -1336,6 +1346,7 @@ parse_vector_reg_list (char **ccp, aarch64_reg_type type, nb_regs++; } in_range = 0; + ptr_flags |= PTR_GOOD_MATCH; } while (skip_past_comma (&str) || (in_range = 1, *str == '-')); @@ -4530,13 +4541,14 @@ parse_sme_zero_mask(char **str) char *q; int mask; aarch64_opnd_qualifier_t qualifier; + unsigned int ptr_flags = PTR_IN_REGLIST; mask = 0x00; q = *str; do { const reg_entry *reg = parse_reg_with_qual (&q, REG_TYPE_ZA_ZAT, - &qualifier, PTR_IN_REGLIST); + &qualifier, ptr_flags); if (!reg) return PARSE_FAIL; @@ -4581,6 +4593,7 @@ parse_sme_zero_mask(char **str) return PARSE_FAIL; } } + ptr_flags |= PTR_GOOD_MATCH; } while (skip_past_char (&q, ',')); diff --git a/gas/testsuite/gas/aarch64/illegal-sve2.l b/gas/testsuite/gas/aarch64/illegal-sve2.l index 2eab4120331..13df21b4a4e 100644 --- a/gas/testsuite/gas/aarch64/illegal-sve2.l +++ b/gas/testsuite/gas/aarch64/illegal-sve2.l @@ -255,7 +255,7 @@ [^ :]+:[0-9]+: Error: invalid register list at operand 2 -- `ext z0\.b,{z0\.b,z31\.b},#0' [^ :]+:[0-9]+: Error: immediate value out of range 0 to 255 at operand 3 -- `ext z0\.b,{z0\.b,z1\.b},#256' [^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `ext z32\.b,{z0\.b,z1\.b},#0' -[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `ext z0\.b,{z31\.b,z32\.b},#0' +[^ :]+:[0-9]+: Error: operand 2 must be a list of SVE vector registers -- `ext z0\.b,{z31\.b,z32\.b},#0' [^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `ext z0\.b,{z32\.b,z33\.b},#0' [^ :]+:[0-9]+: Error: operand 1 must be a SIMD vector register -- `faddp z32\.h,p0/m,z32\.h,z0\.h' [^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `faddp z0\.h,p8/m,z0\.h,z0\.h' diff --git a/gas/testsuite/gas/aarch64/sme-4-illegal.l b/gas/testsuite/gas/aarch64/sme-4-illegal.l index 72f62667768..57d7d65c08c 100644 --- a/gas/testsuite/gas/aarch64/sme-4-illegal.l +++ b/gas/testsuite/gas/aarch64/sme-4-illegal.l @@ -16,6 +16,8 @@ [^:]*:[0-9]+: Error: missing ZA tile size at operand 1 -- `zero {za0}' [^:]*:[0-9]+: Error: syntax error in register list at operand 1 -- `zero {,za0.d}' [^:]*:[0-9]+: Error: syntax error in register list at operand 1 -- `zero {za0.d,}' +[^:]*:[0-9]+: Error: operand 1 must be a list of 64-bit ZA element tiles -- `zero {za0.d,z1.d}' +[^:]*:[0-9]+: Error: operand 1 must be a list of 64-bit ZA element tiles -- `zero {za0.d,za32.d}' [^:]*:[0-9]+: Error: syntax error in register list at operand 1 -- `zero {za0.d,za1.d,}' [^:]*:[0-9]+: Error: syntax error in register list at operand 1 -- `zero {za,}' [^:]*:[0-9]+: Error: unexpected character `}' in element size at operand 1 -- `zero {za.}' diff --git a/gas/testsuite/gas/aarch64/sme-4-illegal.s b/gas/testsuite/gas/aarch64/sme-4-illegal.s index 3d81942f724..da4aa3da266 100644 --- a/gas/testsuite/gas/aarch64/sme-4-illegal.s +++ b/gas/testsuite/gas/aarch64/sme-4-illegal.s @@ -19,6 +19,8 @@ zero { , , } zero { za0 } zero { , za0.d } zero { za0.d , } +zero { za0.d, z1.d } +zero { za0.d, za32.d } zero { za0.d , za1.d , } zero { za, } zero { za. } diff --git a/gas/testsuite/gas/aarch64/sve-invalid.l b/gas/testsuite/gas/aarch64/sve-invalid.l index 930d67328e6..b0750933612 100644 --- a/gas/testsuite/gas/aarch64/sve-invalid.l +++ b/gas/testsuite/gas/aarch64/sve-invalid.l @@ -1208,3 +1208,5 @@ .*: Error: syntax error in register list at operand 1 -- `ld2b {.b},p0/z,\[x0\]' .*: Error: syntax error in register list at operand 1 -- `ld2b {z0.b-},p0/z,\[x0\]' .*: Error: syntax error in register list at operand 1 -- `ld2b {z0.b,},p0/z,\[x0\]' +.*: Error: operand 1 must be a list of SVE vector registers -- `ld2b {z0\.b-z32\.b},p0/z,\[x0\]' +.*: Error: operand 1 must be a list of SVE vector registers -- `ld2b {z0\.b-v1\.16b},p0/z,\[x0\]' diff --git a/gas/testsuite/gas/aarch64/sve-invalid.s b/gas/testsuite/gas/aarch64/sve-invalid.s index ece2142b072..b56a08dc15c 100644 --- a/gas/testsuite/gas/aarch64/sve-invalid.s +++ b/gas/testsuite/gas/aarch64/sve-invalid.s @@ -1329,3 +1329,5 @@ ld2b {.b}, p0/z, [x0] ld2b {z0.b-}, p0/z, [x0] ld2b {z0.b,}, p0/z, [x0] + ld2b {z0.b-z32.b}, p0/z, [x0] + ld2b {z0.b-v1.16b}, p0/z, [x0] -- 2.25.1