From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by sourceware.org (Postfix) with ESMTP id 1BC793858430 for ; Thu, 30 Mar 2023 10:24:34 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 1BC793858430 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 3B1141650; Thu, 30 Mar 2023 03:25:18 -0700 (PDT) Received: from e121540-lin.manchester.arm.com (e121540-lin.manchester.arm.com [10.32.110.72]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 722D93F663; Thu, 30 Mar 2023 03:24:33 -0700 (PDT) From: Richard Sandiford To: binutils@sourceware.org Cc: Richard Sandiford Subject: [PATCH 27/43] aarch64: Deprioritise AARCH64_OPDE_REG_LIST Date: Thu, 30 Mar 2023 11:23:43 +0100 Message-Id: <20230330102359.3327695-28-richard.sandiford@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230330102359.3327695-1-richard.sandiford@arm.com> References: <20230330102359.3327695-1-richard.sandiford@arm.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-33.0 required=5.0 tests=BAYES_00,GIT_PATCH_0,KAM_DMARC_NONE,KAM_DMARC_STATUS,KAM_LAZY_DOMAIN_SECURITY,SPF_HELO_NONE,SPF_NONE,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: SME2 has many instructions that take a list of SVE registers. There are often multiple forms, with different forms taking different numbers of registers. This means that if, after a successful parse and qualifier match, we find that the number of registers does not match the opcode entry, the associated error should have a lower priority/severity than other errors reported at the same stage. For example, if there are 2-register and 4-register forms of an instruction, and if the assembly code uses the 2-register form with an out-of-range value, the out-of-range value error against the 2-register instruction should have a higher priority than the "wrong number of registers" error against the 4-register instruction. This is tested by the main SME2 patches, but seemed worth splitting out. --- gas/config/tc-aarch64.c | 6 +++--- include/opcode/aarch64.h | 14 +++++++++----- 2 files changed, 12 insertions(+), 8 deletions(-) diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c index 8910872dbe4..86d5ba992ff 100644 --- a/gas/config/tc-aarch64.c +++ b/gas/config/tc-aarch64.c @@ -5051,11 +5051,11 @@ const char* operand_mismatch_kind_names[] = "AARCH64_OPDE_SYNTAX_ERROR", "AARCH64_OPDE_FATAL_SYNTAX_ERROR", "AARCH64_OPDE_INVALID_VARIANT", + "AARCH64_OPDE_REG_LIST", "AARCH64_OPDE_UNTIED_IMMS", "AARCH64_OPDE_UNTIED_OPERAND", "AARCH64_OPDE_OUT_OF_RANGE", "AARCH64_OPDE_UNALIGNED", - "AARCH64_OPDE_REG_LIST", "AARCH64_OPDE_OTHER_ERROR", }; #endif /* DEBUG_AARCH64 */ @@ -5077,9 +5077,9 @@ operand_error_higher_severity_p (enum aarch64_operand_error_kind lhs, gas_assert (AARCH64_OPDE_SYNTAX_ERROR > AARCH64_OPDE_EXPECTED_A_AFTER_B); gas_assert (AARCH64_OPDE_FATAL_SYNTAX_ERROR > AARCH64_OPDE_SYNTAX_ERROR); gas_assert (AARCH64_OPDE_INVALID_VARIANT > AARCH64_OPDE_FATAL_SYNTAX_ERROR); - gas_assert (AARCH64_OPDE_OUT_OF_RANGE > AARCH64_OPDE_INVALID_VARIANT); + gas_assert (AARCH64_OPDE_REG_LIST > AARCH64_OPDE_INVALID_VARIANT); + gas_assert (AARCH64_OPDE_OUT_OF_RANGE > AARCH64_OPDE_REG_LIST); gas_assert (AARCH64_OPDE_UNALIGNED > AARCH64_OPDE_OUT_OF_RANGE); - gas_assert (AARCH64_OPDE_REG_LIST > AARCH64_OPDE_UNALIGNED); gas_assert (AARCH64_OPDE_OTHER_ERROR > AARCH64_OPDE_REG_LIST); return lhs > rhs; } diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h index 60c77cab2a8..10c7983aa2d 100644 --- a/include/opcode/aarch64.h +++ b/include/opcode/aarch64.h @@ -1284,6 +1284,14 @@ struct aarch64_inst No syntax error, but the operands are not a valid combination, e.g. FMOV D0,S0 + The following errors are only reported against an asm string that is + syntactically valid and that has valid operand qualifiers. + + AARCH64_OPDE_REG_LIST + Error about the register list operand having an unexpected number of + registers. This error is low severity because there might be another + opcode entry that supports the given number of registers. + AARCH64_OPDE_UNTIED_IMMS The asm failed to use the same immediate for a destination operand and a tied source operand. @@ -1299,10 +1307,6 @@ struct aarch64_inst Error about some immediate value not properly aligned (i.e. not being a multiple times of a certain value). - AARCH64_OPDE_REG_LIST - Error about the register list operand having unexpected number of - registers. - AARCH64_OPDE_OTHER_ERROR Error of the highest severity and used for any severe issue that does not fall into any of the above categories. @@ -1330,11 +1334,11 @@ enum aarch64_operand_error_kind AARCH64_OPDE_SYNTAX_ERROR, AARCH64_OPDE_FATAL_SYNTAX_ERROR, AARCH64_OPDE_INVALID_VARIANT, + AARCH64_OPDE_REG_LIST, AARCH64_OPDE_UNTIED_IMMS, AARCH64_OPDE_UNTIED_OPERAND, AARCH64_OPDE_OUT_OF_RANGE, AARCH64_OPDE_UNALIGNED, - AARCH64_OPDE_REG_LIST, AARCH64_OPDE_OTHER_ERROR }; -- 2.25.1