From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by sourceware.org (Postfix) with ESMTP id DC62C3854803 for ; Thu, 30 Mar 2023 10:24:42 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org DC62C3854803 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 203C32F4; Thu, 30 Mar 2023 03:25:27 -0700 (PDT) Received: from e121540-lin.manchester.arm.com (e121540-lin.manchester.arm.com [10.32.110.72]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 576D23F663; Thu, 30 Mar 2023 03:24:42 -0700 (PDT) From: Richard Sandiford To: binutils@sourceware.org Cc: Richard Sandiford Subject: [PATCH 40/43] aarch64: Resync field names Date: Thu, 30 Mar 2023 11:23:56 +0100 Message-Id: <20230330102359.3327695-41-richard.sandiford@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230330102359.3327695-1-richard.sandiford@arm.com> References: <20230330102359.3327695-1-richard.sandiford@arm.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-32.7 required=5.0 tests=BAYES_00,GIT_PATCH_0,KAM_DMARC_NONE,KAM_DMARC_STATUS,KAM_LAZY_DOMAIN_SECURITY,SPF_HELO_NONE,SPF_NONE,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: This patch just makes the comments in aarch64-opc.c:fields match the names of the associated FLD_* enum. --- opcodes/aarch64-opc.c | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/opcodes/aarch64-opc.c b/opcodes/aarch64-opc.c index 46c49dd95f8..dc4df2ff20c 100644 --- a/opcodes/aarch64-opc.c +++ b/opcodes/aarch64-opc.c @@ -258,12 +258,12 @@ const aarch64_field fields[] = { 16, 6 }, /* immr: in bitfield and logical immediate instructions. */ { 16, 3 }, /* immb: in advsimd shift by immediate instructions. */ { 19, 4 }, /* immh: in advsimd shift by immediate instructions. */ - { 22, 1 }, /* S: in LDRAA and LDRAB instructions. */ + { 22, 1 }, /* S_imm10: in LDRAA and LDRAB instructions. */ { 22, 1 }, /* N: in logical (immediate) instructions. */ { 11, 1 }, /* index: in ld/st inst deciding the pre/post-index. */ { 24, 1 }, /* index2: in ld/st pair inst deciding the pre/post-index. */ { 31, 1 }, /* sf: in integer data processing instructions. */ - { 30, 1 }, /* lse_size: in LSE extension atomic instructions. */ + { 30, 1 }, /* lse_sz: in LSE extension atomic instructions. */ { 11, 1 }, /* H: in advsimd scalar x indexed element instructions. */ { 21, 1 }, /* L: in advsimd scalar x indexed element instructions. */ { 20, 1 }, /* M: in advsimd scalar x indexed element instructions. */ @@ -324,22 +324,22 @@ const aarch64_field fields[] = { 19, 2 }, /* SVE_tszl_19: triangular size select low, bits [20,19]. */ { 14, 1 }, /* SVE_xs_14: UXTW/SXTW select (bit 14). */ { 22, 1 }, /* SVE_xs_22: UXTW/SXTW select (bit 22). */ - { 0, 2 }, /* SME ZAda tile ZA0-ZA3. */ - { 0, 3 }, /* SME ZAda tile ZA0-ZA7. */ + { 0, 2 }, /* SME_ZAda_2b: tile ZA0-ZA3. */ + { 0, 3 }, /* SME_ZAda_3b: tile ZA0-ZA7. */ { 22, 2 }, /* SME_size_22: size<1>, size<0> class field, [23:22]. */ { 16, 1 }, /* SME_Q: Q class bit, bit 16. */ { 15, 1 }, /* SME_V: (horizontal / vertical tiles), bit 15. */ { 13, 2 }, /* SME_Rv: vector select register W12-W15, bits [14:13]. */ - { 13, 3 }, /* SME Pm second source scalable predicate register P0-P7. */ + { 13, 3 }, /* SME_Pm: second source scalable predicate register P0-P7. */ { 0, 8 }, /* SME_zero_mask: list of up to 8 tile names separated by commas [7:0]. */ { 16, 2 }, /* SME_Rm: index base register W12-W15 [17:16]. */ { 23, 1 }, /* SME_i1: immediate field, bit 23. */ { 22, 1 }, /* SME_tszh: immediate and qualifier field, bit 22. */ - { 18, 3 }, /* SME_tshl: immediate and qualifier field, bits [20:18]. */ + { 18, 3 }, /* SME_tszl: immediate and qualifier field, bits [20:18]. */ { 11, 2 }, /* rotate1: FCMLA immediate rotate. */ { 13, 2 }, /* rotate2: Indexed element FCMLA immediate rotate. */ { 12, 1 }, /* rotate3: FCADD immediate rotate. */ - { 12, 2 }, /* SM3: Indexed element SM3 2 bits index immediate. */ + { 12, 2 }, /* SM3_imm2: Indexed element SM3 2 bits index immediate. */ { 22, 1 }, /* sz: 1-bit element size select. */ { 10, 2 }, /* CRm_dsb_nxs: 2-bit imm. encoded in CRm<3:2>. */ { 10, 8 }, /* CSSC_imm8. */ -- 2.25.1