From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by sourceware.org (Postfix) with ESMTP id 46B9F3895FCD for ; Thu, 30 Mar 2023 10:26:54 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 46B9F3895FCD Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 6644E12FC; Thu, 30 Mar 2023 03:27:38 -0700 (PDT) Received: from e121540-lin.manchester.arm.com (e121540-lin.manchester.arm.com [10.32.110.72]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 9D3DE3F663; Thu, 30 Mar 2023 03:26:53 -0700 (PDT) From: Richard Sandiford To: binutils@sourceware.org Cc: Richard Sandiford Subject: [PATCH 01/31] aarch64: Add +sme2 Date: Thu, 30 Mar 2023 11:26:16 +0100 Message-Id: <20230330102646.3327818-2-richard.sandiford@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230330102646.3327818-1-richard.sandiford@arm.com> References: <20230330102646.3327818-1-richard.sandiford@arm.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-32.3 required=5.0 tests=BAYES_00,GIT_PATCH_0,KAM_DMARC_NONE,KAM_DMARC_STATUS,KAM_LAZY_DOMAIN_SECURITY,KAM_NUMSUBJECT,SPF_HELO_NONE,SPF_NONE,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: This patch adds bare-bones support for +sme2. Later patches fill in the rest. --- gas/NEWS | 2 ++ gas/config/tc-aarch64.c | 2 ++ gas/doc/c-aarch64.texi | 2 ++ include/opcode/aarch64.h | 1 + 4 files changed, 7 insertions(+) diff --git a/gas/NEWS b/gas/NEWS index 4ae2089901c..05fbed113c2 100644 --- a/gas/NEWS +++ b/gas/NEWS @@ -1,5 +1,7 @@ -*- text -*- +* Add SME2 support to the AArch64 port. + Changes in 2.40: * Add support for Intel RAO-INT instructions. diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c index 2d4c6106506..6ebfcda7dff 100644 --- a/gas/config/tc-aarch64.c +++ b/gas/config/tc-aarch64.c @@ -10183,6 +10183,8 @@ static const struct aarch64_option_cpu_value_table aarch64_features[] = { AARCH64_FEATURE (AARCH64_FEATURE_SME, 0)}, {"sme-i16i64", AARCH64_FEATURE (AARCH64_FEATURE_SME_I16I64, 0), AARCH64_FEATURE (AARCH64_FEATURE_SME, 0)}, + {"sme2", AARCH64_FEATURE (AARCH64_FEATURE_SME2, 0), + AARCH64_FEATURE (AARCH64_FEATURE_SME, 0)}, {"bf16", AARCH64_FEATURE (AARCH64_FEATURE_BFLOAT16, 0), AARCH64_FEATURE (AARCH64_FEATURE_FP, 0)}, {"i8mm", AARCH64_FEATURE (AARCH64_FEATURE_I8MM, 0), diff --git a/gas/doc/c-aarch64.texi b/gas/doc/c-aarch64.texi index 3921c0d368e..acde4a77dd2 100644 --- a/gas/doc/c-aarch64.texi +++ b/gas/doc/c-aarch64.texi @@ -235,6 +235,8 @@ automatically cause those extensions to be disabled. @tab Enable SME F64F64 Extension. @item @code{sme-i16i64} @tab Armv9-A @tab No @tab Enable SME I16I64 Extension. +@item @code{sme2} @tab Armv9-A @tab No + @tab Enable SME2. This implies @code{sme}. @item @code{ssbs} @tab ARMv8-A @tab ARMv8.5-A or later @tab Enable Speculative Store Bypassing Safe state read and write. @item @code{sve} @tab ARMv8.2-A @tab Armv9-A or later diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h index ef59d531d17..5c9b5e5dac1 100644 --- a/include/opcode/aarch64.h +++ b/include/opcode/aarch64.h @@ -100,6 +100,7 @@ typedef uint32_t aarch64_insn; #define AARCH64_FEATURE_SME_I16I64 (1ULL << 58) /* SME I16I64. */ #define AARCH64_FEATURE_V8_8 (1ULL << 59) /* Armv8.8 processors. */ #define AARCH64_FEATURE_CSSC (1ULL << 60) /* Common Short Sequence Compression instructions. */ +#define AARCH64_FEATURE_SME2 (1ULL << 61) /* SME2. */ /* Crypto instructions are the combination of AES and SHA2. */ #define AARCH64_FEATURE_CRYPTO (AARCH64_FEATURE_SHA2 | AARCH64_FEATURE_AES) -- 2.25.1