From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from azure-sdnproxy.icoremail.net (azure-sdnproxy.icoremail.net [207.46.229.174]) by sourceware.org (Postfix) with ESMTP id 2F2493858D38 for ; Thu, 18 May 2023 06:59:56 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 2F2493858D38 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=eswincomputing.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=eswincomputing.com Received: from host014-ubuntu-1804.lxd (unknown [10.12.130.31]) by app1 (Coremail) with SMTP id EwgMCgBnBcXozGVkD8gXAA--.25116S4; Thu, 18 May 2023 14:59:53 +0800 (CST) From: Li Xu To: binutils@sourceware.org Cc: kito.cheng@gmail.com, palmer@dabbelt.com, Li Xu Subject: [PATCH] RISC-V: Warn in AS if vsew/vlmul/vtype is reserved. Date: Thu, 18 May 2023 06:59:50 +0000 Message-Id: <20230518065950.6166-1-xuli1@eswincomputing.com> X-Mailer: git-send-email 2.17.1 X-CM-TRANSID:EwgMCgBnBcXozGVkD8gXAA--.25116S4 X-Coremail-Antispam: 1UD129KBjvJXoW3GrW3CFy8GF1fCFW3Gr45ZFb_yoWfCw1fpF 4UGw4SvFWrCF9xZ3y3tr15Aa1jvan7Kr98Kw1Y93W8Cay8ArsYy3s8GrsrZrn2qrW2kFyr ua1UAr4ru3Z8JrJanT9S1TB71UUUUUUqnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnRJUUUk214x267AKxVWUJVW8JwAFc2x0x2IEx4CE42xK8VAvwI8IcIk0 rVWrJVCq3wAFIxvE14AKwVWUJVWUGwA2ocxC64kIII0Yj41l84x0c7CEw4AK67xGY2AK02 1l84ACjcxK6xIIjxv20xvE14v26w1j6s0DM28EF7xvwVC0I7IYx2IY6xkF7I0E14v26r4U JVWxJr1l84ACjcxK6I8E87Iv67AKxVW0oVCq3wA2z4x0Y4vEx4A2jsIEc7CjxVAFwI0_Gc CE3s1le2I262IYc4CY6c8Ij28IcVAaY2xG8wAqx4xG64xvF2IEw4CE5I8CrVC2j2WlYx0E 2Ix0cI8IcVAFwI0_Jr0_Jr4lYx0Ex4A2jsIE14v26r1j6r4UMcvjeVCFs4IE7xkEbVWUJV W8JwACjcxG0xvY0x0EwIxGrwACjI8F5VA0II8E6IAqYI8I648v4I1lc2xSY4AK6svPMxAI w28IcxkI7VAKI48JMxC20s026xCaFVCjc4AY6r1j6r4UMI8I3I0E5I8CrVAFwI0_Jr0_Jr 4lx2IqxVCjr7xvwVAFwI0_JrI_JrWlx4CE17CEb7AF67AKxVWUAVWUtwCIc40Y0x0EwIxG rwCI42IY6xIIjxv20xvE14v26r1j6r1xMIIF0xvE2Ix0cI8IcVCY1x0267AKxVWUJVW8Jw CI42IY6xAIw20EY4v20xvaj40_Jr0_JF4lIxAIcVC2z280aVAFwI0_Jr0_Gr1lIxAIcVC2 z280aVCY1x0267AKxVWUJVW8JbIYCTnIWIevJa73UjIFyTuYvjfU5WlkUUUUU X-CM-SenderInfo: 50xoxi46hv4xpqfrz1xxwl0woofrz/ X-Spam-Status: No, score=-13.4 required=5.0 tests=BAYES_00,GIT_PATCH_0,KAM_DMARC_STATUS,RCVD_IN_DNSWL_LOW,RCVD_IN_MSPIKE_H2,SPF_HELO_NONE,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: Consider the following case: vsetvli a0, a1, 0x4 # unrecognized vlmul vsetvli a0, a1, 0x20 # unrecognized vsew vsetvli a0, a1, 0x700 # unrecognized vtype The current AS doesn't have any hints, so I think it's better to give a warning. After this patch: test.s: Assembler messages: test.s:1: Warning: The vtype encoding of vlmul = 0x4 is reserved. test.s:2: Warning: The vtype encoding of vsew = 0x4 is reserved. test.s:3: Warning: The vtype encoding of 0x700 is reserved. gas/ChangeLog: * config/tc-riscv.c (my_getVsetvliExpression): Warn if vsew/vlmul/vtype is reserved. * testsuite/gas/riscv/vector-insns.d: move vsetvl to new file. * testsuite/gas/riscv/vector-insns.s: Ditto. * testsuite/gas/riscv/vector-insns-vsetvl.d: New test. * testsuite/gas/riscv/vector-insns-vsetvl.s: New test. * testsuite/gas/riscv/vector-insns-warning.l: New test. --- gas/config/tc-riscv.c | 10 ++++++ gas/testsuite/gas/riscv/vector-insns-vsetvl.d | 33 +++++++++++++++++++ gas/testsuite/gas/riscv/vector-insns-vsetvl.s | 24 ++++++++++++++ .../gas/riscv/vector-insns-warning.l | 15 +++++++++ gas/testsuite/gas/riscv/vector-insns.d | 23 ------------- gas/testsuite/gas/riscv/vector-insns.s | 25 -------------- 6 files changed, 82 insertions(+), 48 deletions(-) create mode 100644 gas/testsuite/gas/riscv/vector-insns-vsetvl.d create mode 100644 gas/testsuite/gas/riscv/vector-insns-vsetvl.s create mode 100644 gas/testsuite/gas/riscv/vector-insns-warning.l diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c index 0cc2484b049..521850f5191 100644 --- a/gas/config/tc-riscv.c +++ b/gas/config/tc-riscv.c @@ -2381,6 +2381,16 @@ my_getVsetvliExpression (expressionS *ep, char *str) { my_getExpression (ep, str); str = expr_parse_end; + unsigned int imm_vlmul = EXTRACT_OPERAND (VLMUL, ep->X_add_number); + if (!riscv_vlmul[imm_vlmul]) + as_warn (_("The vtype encoding of vlmul = %#x is reserved."), imm_vlmul); + unsigned int imm_vsew = EXTRACT_OPERAND (VSEW, ep->X_add_number); + if (!riscv_vsew[imm_vsew]) + as_warn (_("The vtype encoding of vsew = %#x is reserved."), imm_vsew); + unsigned int imm_vtype_res = ep->X_add_number >> 8; + if (imm_vtype_res) + as_warn (_("The vtype encoding of %#lx is reserved."), + (unsigned long) ep->X_add_number); } } diff --git a/gas/testsuite/gas/riscv/vector-insns-vsetvl.d b/gas/testsuite/gas/riscv/vector-insns-vsetvl.d new file mode 100644 index 00000000000..549737ad936 --- /dev/null +++ b/gas/testsuite/gas/riscv/vector-insns-vsetvl.d @@ -0,0 +1,33 @@ +#as: -march=rv32ifv +#warning_output: vector-insns-warning.l +#objdump: -dr + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 <.text>: +[ ]+[0-9a-f]+:[ ]+80c5f557[ ]+vsetvl[ ]+a0,a1,a2 +[ ]+[0-9a-f]+:[ ]+0005f557[ ]+vsetvli[ ]+a0,a1,e8,m1,tu,mu +[ ]+[0-9a-f]+:[ ]+7ff5f557[ ]+vsetvli[ ]+a0,a1,2047 +[ ]+[0-9a-f]+:[ ]+0045f557[ ]+vsetvli[ ]+a0,a1,4 +[ ]+[0-9a-f]+:[ ]+0205f557[ ]+vsetvli[ ]+a0,a1,32 +[ ]+[0-9a-f]+:[ ]+0015f557[ ]+vsetvli[ ]+a0,a1,e8,m2,tu,mu +[ ]+[0-9a-f]+:[ ]+04a5f557[ ]+vsetvli[ ]+a0,a1,e16,m4,ta,mu +[ ]+[0-9a-f]+:[ ]+0165f557[ ]+vsetvli[ ]+a0,a1,e32,mf4,tu,mu +[ ]+[0-9a-f]+:[ ]+09d5f557[ ]+vsetvli[ ]+a0,a1,e64,mf8,tu,ma +[ ]+[0-9a-f]+:[ ]+c005f557[ ]+vsetivli[ ]+a0,11,e8,m1,tu,mu +[ ]+[0-9a-f]+:[ ]+fff5f557[ ]+vsetivli[ ]+a0,11,1023 +[ ]+[0-9a-f]+:[ ]+c045f557[ ]+vsetivli[ ]+a0,11,4 +[ ]+[0-9a-f]+:[ ]+c205f557[ ]+vsetivli[ ]+a0,11,32 +[ ]+[0-9a-f]+:[ ]+c015f557[ ]+vsetivli[ ]+a0,11,e8,m2,tu,mu +[ ]+[0-9a-f]+:[ ]+c4a5f557[ ]+vsetivli[ ]+a0,11,e16,m4,ta,mu +[ ]+[0-9a-f]+:[ ]+c165f557[ ]+vsetivli[ ]+a0,11,e32,mf4,tu,mu +[ ]+[0-9a-f]+:[ ]+c9d5f557[ ]+vsetivli[ ]+a0,11,e64,mf8,tu,ma +[ ]+[0-9a-f]+:[ ]+7005f557[ ]+vsetvli[ ]+a0,a1,1792 +[ ]+[0-9a-f]+:[ ]+4005f557[ ]+vsetvli[ ]+a0,a1,1024 +[ ]+[0-9a-f]+:[ ]+3005f557[ ]+vsetvli[ ]+a0,a1,768 +[ ]+[0-9a-f]+:[ ]+1005f557[ ]+vsetvli[ ]+a0,a1,256 +[ ]+[0-9a-f]+:[ ]+f005f557[ ]+vsetivli[ ]+a0,11,768 +[ ]+[0-9a-f]+:[ ]+d005f557[ ]+vsetivli[ ]+a0,11,256 diff --git a/gas/testsuite/gas/riscv/vector-insns-vsetvl.s b/gas/testsuite/gas/riscv/vector-insns-vsetvl.s new file mode 100644 index 00000000000..b42dc503d93 --- /dev/null +++ b/gas/testsuite/gas/riscv/vector-insns-vsetvl.s @@ -0,0 +1,24 @@ + vsetvl a0, a1, a2 + vsetvli a0, a1, 0 + vsetvli a0, a1, 0x7ff + vsetvli a0, a1, 0x4 # unrecognized vlmul + vsetvli a0, a1, 0x20 # unrecognized vsew + vsetvli a0, a1, e8, m2 + vsetvli a0, a1, e16, m4, ta + vsetvli a0, a1, e32, mf4, mu + vsetvli a0, a1, e64, mf8, tu, ma + vsetivli a0, 0xb, 0 + vsetivli a0, 0xb, 0x3ff + vsetivli a0, 0xb, 0x4 # unrecognized vlmul + vsetivli a0, 0xb, 0x20 # unrecognized vsew + vsetivli a0, 0xb, e8, m2 + vsetivli a0, 0xb, e16, m4, ta + vsetivli a0, 0xb, e32, mf4, mu + vsetivli a0, 0xb, e64, mf8, tu, ma + + vsetvli a0, a1, 0x700 + vsetvli a0, a1, 0x400 + vsetvli a0, a1, 0x300 + vsetvli a0, a1, 0x100 + vsetivli a0, 0xb, 0x300 + vsetivli a0, 0xb, 0x100 diff --git a/gas/testsuite/gas/riscv/vector-insns-warning.l b/gas/testsuite/gas/riscv/vector-insns-warning.l new file mode 100644 index 00000000000..73d15eb8f21 --- /dev/null +++ b/gas/testsuite/gas/riscv/vector-insns-warning.l @@ -0,0 +1,15 @@ +.*Assembler messages: +.*Warning: The vtype encoding of vsew = 0x7 is reserved. +.*Warning: The vtype encoding of 0x7ff is reserved. +.*Warning: The vtype encoding of vlmul = 0x4 is reserved. +.*Warning: The vtype encoding of vsew = 0x4 is reserved. +.*Warning: The vtype encoding of vsew = 0x7 is reserved. +.*Warning: The vtype encoding of 0x3ff is reserved. +.*Warning: The vtype encoding of vlmul = 0x4 is reserved. +.*Warning: The vtype encoding of vsew = 0x4 is reserved. +.*Warning: The vtype encoding of 0x700 is reserved. +.*Warning: The vtype encoding of 0x400 is reserved. +.*Warning: The vtype encoding of 0x300 is reserved. +.*Warning: The vtype encoding of 0x100 is reserved. +.*Warning: The vtype encoding of 0x300 is reserved. +.*Warning: The vtype encoding of 0x100 is reserved. diff --git a/gas/testsuite/gas/riscv/vector-insns.d b/gas/testsuite/gas/riscv/vector-insns.d index 71764aa1f34..ae4f36ca885 100644 --- a/gas/testsuite/gas/riscv/vector-insns.d +++ b/gas/testsuite/gas/riscv/vector-insns.d @@ -7,29 +7,6 @@ Disassembly of section .text: 0+000 <.text>: -[ ]+[0-9a-f]+:[ ]+80c5f557[ ]+vsetvl[ ]+a0,a1,a2 -[ ]+[0-9a-f]+:[ ]+0005f557[ ]+vsetvli[ ]+a0,a1,e8,m1,tu,mu -[ ]+[0-9a-f]+:[ ]+7ff5f557[ ]+vsetvli[ ]+a0,a1,2047 -[ ]+[0-9a-f]+:[ ]+0045f557[ ]+vsetvli[ ]+a0,a1,4 -[ ]+[0-9a-f]+:[ ]+0205f557[ ]+vsetvli[ ]+a0,a1,32 -[ ]+[0-9a-f]+:[ ]+0015f557[ ]+vsetvli[ ]+a0,a1,e8,m2,tu,mu -[ ]+[0-9a-f]+:[ ]+04a5f557[ ]+vsetvli[ ]+a0,a1,e16,m4,ta,mu -[ ]+[0-9a-f]+:[ ]+0165f557[ ]+vsetvli[ ]+a0,a1,e32,mf4,tu,mu -[ ]+[0-9a-f]+:[ ]+09d5f557[ ]+vsetvli[ ]+a0,a1,e64,mf8,tu,ma -[ ]+[0-9a-f]+:[ ]+c005f557[ ]+vsetivli[ ]+a0,11,e8,m1,tu,mu -[ ]+[0-9a-f]+:[ ]+fff5f557[ ]+vsetivli[ ]+a0,11,1023 -[ ]+[0-9a-f]+:[ ]+c045f557[ ]+vsetivli[ ]+a0,11,4 -[ ]+[0-9a-f]+:[ ]+c205f557[ ]+vsetivli[ ]+a0,11,32 -[ ]+[0-9a-f]+:[ ]+c015f557[ ]+vsetivli[ ]+a0,11,e8,m2,tu,mu -[ ]+[0-9a-f]+:[ ]+c4a5f557[ ]+vsetivli[ ]+a0,11,e16,m4,ta,mu -[ ]+[0-9a-f]+:[ ]+c165f557[ ]+vsetivli[ ]+a0,11,e32,mf4,tu,mu -[ ]+[0-9a-f]+:[ ]+c9d5f557[ ]+vsetivli[ ]+a0,11,e64,mf8,tu,ma -[ ]+[0-9a-f]+:[ ]+7005f557[ ]+vsetvli[ ]+a0,a1,1792 -[ ]+[0-9a-f]+:[ ]+4005f557[ ]+vsetvli[ ]+a0,a1,1024 -[ ]+[0-9a-f]+:[ ]+3005f557[ ]+vsetvli[ ]+a0,a1,768 -[ ]+[0-9a-f]+:[ ]+1005f557[ ]+vsetvli[ ]+a0,a1,256 -[ ]+[0-9a-f]+:[ ]+f005f557[ ]+vsetivli[ ]+a0,11,768 -[ ]+[0-9a-f]+:[ ]+d005f557[ ]+vsetivli[ ]+a0,11,256 [ ]+[0-9a-f]+:[ ]+02b50207[ ]+vlm.v[ ]+v4,\(a0\) [ ]+[0-9a-f]+:[ ]+02b50207[ ]+vlm.v[ ]+v4,\(a0\) [ ]+[0-9a-f]+:[ ]+02b50207[ ]+vlm.v[ ]+v4,\(a0\) diff --git a/gas/testsuite/gas/riscv/vector-insns.s b/gas/testsuite/gas/riscv/vector-insns.s index a4b98d81026..76f0f179021 100644 --- a/gas/testsuite/gas/riscv/vector-insns.s +++ b/gas/testsuite/gas/riscv/vector-insns.s @@ -1,28 +1,3 @@ - vsetvl a0, a1, a2 - vsetvli a0, a1, 0 - vsetvli a0, a1, 0x7ff - vsetvli a0, a1, 0x4 # unrecognized vlmul - vsetvli a0, a1, 0x20 # unrecognized vsew - vsetvli a0, a1, e8, m2 - vsetvli a0, a1, e16, m4, ta - vsetvli a0, a1, e32, mf4, mu - vsetvli a0, a1, e64, mf8, tu, ma - vsetivli a0, 0xb, 0 - vsetivli a0, 0xb, 0x3ff - vsetivli a0, 0xb, 0x4 # unrecognized vlmul - vsetivli a0, 0xb, 0x20 # unrecognized vsew - vsetivli a0, 0xb, e8, m2 - vsetivli a0, 0xb, e16, m4, ta - vsetivli a0, 0xb, e32, mf4, mu - vsetivli a0, 0xb, e64, mf8, tu, ma - - vsetvli a0, a1, 0x700 - vsetvli a0, a1, 0x400 - vsetvli a0, a1, 0x300 - vsetvli a0, a1, 0x100 - vsetivli a0, 0xb, 0x300 - vsetivli a0, 0xb, 0x100 - vlm.v v4, (a0) vlm.v v4, 0(a0) vle1.v v4, (a0) # Alias of vlm.v -- 2.17.1