From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from s01.bc.larksuite.com (s01.bc.larksuite.com [209.127.230.14]) by sourceware.org (Postfix) with UTF8SMTPS id 488243857344 for ; Thu, 18 May 2023 08:57:55 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 488243857344 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=oss.cipunited.com Authentication-Results: sourceware.org; spf=none smtp.mailfrom=oss.cipunited.com DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; s=s1; d=oss-cipunited-com.20200927.dkim.feishu.cn; t=1684400270; h=from:subject:mime-version:from:date:message-id:subject:to:cc: reply-to:content-type:mime-version:in-reply-to:message-id; bh=AoGc1ooK00UCanzSKrfvs2rer1OVGCqXxH5ZW43TkRc=; b=fLF8Had/QB7ELpgir/iiqmEqHtbLJeKBvdeWfVB1ts7QDmSscEoBvw+awAjWR3iuw2Ae82 3yibyRzHIEs32Y4HIDQzHudyJMlwpKCS8WguooYr92X2Kofsp91brVKgkfBYCXg1ciYosL dyonyKrkY4q03a91m6WyOXa0QBIWWE1kZe/v81vwy9OSPw9p5F4osEA5R0HRAmtSZ3C6An xhA+0jCT+iDNtYkfSEtbDWORBUArCqakL0GOszennVR5Pk4J7Byr9p8ZjsHR9JQQx7D5jn vPBleLTtOfYF3OM/IldWIvbA9JKb72EeJWWic2pDBMvkjOecJtUVRqL1esNJgg== Subject: [PATCH] Add GINV(+VIRT) ASE for MIPSr6 Message-Id: <20230518085739.2195035-1-lei.wang@oss.cipunited.com> Mime-Version: 1.0 X-Mailer: git-send-email 2.40.1 Content-Transfer-Encoding: 8bit To: From: "Tsing" Date: Thu, 18 May 2023 16:57:50 +0800 X-Lms-Return-Path: Content-Type: multipart/alternative; boundary=a8f464fc0dfc9853385572bf7e8f2483fccb0a906422d4f0c2c3d2a305bf X-Spam-Status: No, score=-11.7 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,GIT_PATCH_0,HTML_MESSAGE,KAM_NUMSUBJECT,SPF_HELO_NONE,SPF_NONE,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: --a8f464fc0dfc9853385572bf7e8f2483fccb0a906422d4f0c2c3d2a305bf Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset=UTF-8 This patch adds the VZ extension to MIPSr6 as part of the GINV ASE. gas/ChangeLog * config/tc-mips.c (mips_ases): Add microMIPS ASE. (mips_set_ase): Set combination VZ+GINV ASE flag. gas/testsuite/ChangeLog * gas/mips/ginv.s: Add test case. * gas/mips/ginv-virt.d: New test. * gas/mips/mips.exp: Run the new tests. include/Changelog * opcode/mips.h: Add note for micromips +\ format descriptor. (ASE_GINV_VIRT): New macro. opcodes/ChangeLog * mips-dis.c (mips_calculate_combination_ases): Set ASE_GINV_VIRT. * mips-opc.c (GINVVZ): New macro. (mips_opcode): Add instructions GINVGT. --- gas/config/tc-mips.c | 11 ++++++++++- gas/testsuite/gas/mips/ginv-virt.d | 22 ++++++++++++++++++++++ gas/testsuite/gas/mips/ginv.s | 5 +++++ gas/testsuite/gas/mips/mips.exp | 1 + include/opcode/mips.h | 6 ++++++ opcodes/mips-dis.c | 2 ++ opcodes/mips-opc.c | 2 ++ 7 files changed, 48 insertions(+), 1 deletion(-) create mode 100644 gas/testsuite/gas/mips/ginv-virt.d diff --git a/gas/config/tc-mips.c b/gas/config/tc-mips.c index 077993cf..de8ea1dd 100644 --- a/gas/config/tc-mips.c +++ b/gas/config/tc-mips.c @@ -2227,7 +2227,7 @@ mips_set_ase (const struct mips_ase *ase, struct mips= _set_options *opts, =20 /* Clear combination ASE flags, which need to be recalculated based on updated regular ASE settings. */ - opts->ase &=3D ~(ASE_MIPS16E2_MT | ASE_XPA_VIRT | ASE_EVA_R6); + opts->ase &=3D ~(ASE_MIPS16E2_MT | ASE_XPA_VIRT | ASE_EVA_R6 | ASE_GINV_= VIRT); =20 if (enabled_p) opts->ase |=3D ase->flags; @@ -2255,6 +2255,15 @@ mips_set_ase (const struct mips_ase *ase, struct mip= s_set_options *opts, mask |=3D ASE_EVA_R6; } =20 + /* The Virtualization ASE has Global INValidate (GINV) instructions + which are only valid when both ASEs are enabled. This sets the + ASE_GINV_VIRT flag when both ASEs are present. */ + if ((opts->ase & (ASE_GINV | ASE_VIRT)) =3D=3D (ASE_GINV | ASE_VIRT)) + { + opts->ase |=3D ASE_GINV_VIRT; + mask |=3D ASE_GINV_VIRT; + } + return mask; } =20 diff --git a/gas/testsuite/gas/mips/ginv-virt.d b/gas/testsuite/gas/mips/gi= nv-virt.d new file mode 100644 index 00000000..50fa6d54 --- /dev/null +++ b/gas/testsuite/gas/mips/ginv-virt.d @@ -0,0 +1,22 @@ +#objdump: -pdr --prefix-addresses --show-raw-insn +#name: MIPS GINV Virtualization +#as: --defsym VX=3D -mginv -mvirt -32 +#source: ginv.s + +# Test GINV+VZ instructions. + +.*: +file format .*mips.* +#... +ASEs: +#... + VZ ASE + GINV ASE +#... + +Disassembly of section \.text: +[0-9a-f]+ <[^>]*> 7c40003d ginvi v0 +[0-9a-f]+ <[^>]*> 7c6000bd ginvt v1,0x0 +[0-9a-f]+ <[^>]*> 7c8001bd ginvt a0,0x1 +[0-9a-f]+ <[^>]*> 7c8002fd ginvgt a0,0x2 +[0-9a-f]+ <[^>]*> 7ca003fd ginvgt a1,0x3 + \.\.\. diff --git a/gas/testsuite/gas/mips/ginv.s b/gas/testsuite/gas/mips/ginv.s index 63cfb150..80159948 100644 --- a/gas/testsuite/gas/mips/ginv.s +++ b/gas/testsuite/gas/mips/ginv.s @@ -4,6 +4,11 @@ test: ginvt $3,0 ginvt $4,1 =20 + .ifdef VX + ginvgt $4,2 + ginvgt $5,3 + .endif + # Force at least 8 (non-delay-slot) zero bytes, to make 'objdump' print ... .align 2 .space 8 diff --git a/gas/testsuite/gas/mips/mips.exp b/gas/testsuite/gas/mips/mips.= exp index fafed2dc..4e3e226f 100644 --- a/gas/testsuite/gas/mips/mips.exp +++ b/gas/testsuite/gas/mips/mips.exp @@ -2131,6 +2131,7 @@ if { [istarget mips*-*-vxworks*] } { =20 run_dump_test_arches "ginv" [mips_arch_list_matching mips32r6] run_dump_test_arches "ginv-err" [mips_arch_list_matching mips32r6] + run_dump_test_arches "ginv-virt" [mips_arch_list_matching mips32r6] =20 run_dump_test_arches "llpscp-32" [mips_arch_list_matching mips32r6] run_dump_test_arch "llpscp-64" "" mips64r6 diff --git a/include/opcode/mips.h b/include/opcode/mips.h index 75d3fc25..b26a8ffd 100644 --- a/include/opcode/mips.h +++ b/include/opcode/mips.h @@ -1316,6 +1316,9 @@ static const unsigned int mips_isa_table[] =3D { /* The Enhanced VA Scheme (EVA) extension has instructions which are only valid for the R6 ISA. */ #define ASE_EVA_R6 0x02000000 +/* The Virtualization ASE has Global INValidate (GINV) + instructions which are only valid when both ASEs are enabled. */ +#define ASE_GINV_VIRT 0x08000000 =20 /* MIPS ISA defines, use instead of hardcoding ISA level. */ =20 @@ -2351,6 +2354,9 @@ extern const int bfd_mips16_num_opcodes; "+*" 5-bit register vector element index at bit 16 "+|" 8-bit mask at bit 16 =20 + GINV ASE usage: + "+\" 2 bit Global TLB invalidate type at bit 8 + Other: "()" parens surrounding optional value "," separates operands diff --git a/opcodes/mips-dis.c b/opcodes/mips-dis.c index 6a513cd8..77b35b60 100644 --- a/opcodes/mips-dis.c +++ b/opcodes/mips-dis.c @@ -866,6 +866,8 @@ mips_calculate_combination_ases (int opcode_isa, unsign= ed long opcode_ases) && ((opcode_isa & INSN_ISA_MASK) =3D=3D ISA_MIPS64R6 || (opcode_isa & INSN_ISA_MASK) =3D=3D ISA_MIPS32R6)) combination_ases |=3D ASE_EVA_R6; + if ((opcode_ases & (ASE_GINV | ASE_VIRT)) =3D=3D (ASE_GINV | ASE_VIRT)) + combination_ases |=3D ASE_GINV_VIRT; return combination_ases; } =20 diff --git a/opcodes/mips-opc.c b/opcodes/mips-opc.c index 2a1a6cbb..80a5124b 100644 --- a/opcodes/mips-opc.c +++ b/opcodes/mips-opc.c @@ -412,6 +412,7 @@ decode_mips_operand (const char *p) =20 /* Global INValidate (GINV) support. */ #define GINV ASE_GINV +#define GINVVZ ASE_GINV_VIRT =20 /* Loongson MultiMedia extensions Instructions (MMI) support. */ #define LMMI ASE_LOONGSON_MMI @@ -3329,6 +3330,7 @@ const struct mips_opcode mips_builtin_opcodes[] =3D /* MIPS Global INValidate (GINV) ASE. */ {"ginvi", "s", 0x7c00003d, 0xfc1fffff, RD_1, 0, 0, GINV, 0 }, {"ginvt", "s,+\\", 0x7c0000bd, 0xfc1ffcff, RD_1, 0, 0, GINV, 0 }, +{"ginvgt", "s,+\\", 0x7c0000fd, 0xfc1ffcff, RD_1, 0, 0, GINVVZ, 0 }, =20 /* Move bc0* after mftr and mttr to avoid opcode collision. */ {"bc0f", "p", 0x41000000, 0xffff0000, RD_CC|CBD, 0, I1, 0, I4_32 }, --=20 2.40.1= --a8f464fc0dfc9853385572bf7e8f2483fccb0a906422d4f0c2c3d2a305bf--