From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-wm1-x333.google.com (mail-wm1-x333.google.com [IPv6:2a00:1450:4864:20::333]) by sourceware.org (Postfix) with ESMTPS id 1D88D3858C52 for ; Wed, 14 Jun 2023 00:01:54 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 1D88D3858C52 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=davidgf.es Authentication-Results: sourceware.org; spf=fail smtp.mailfrom=davidgf.es Received: by mail-wm1-x333.google.com with SMTP id 5b1f17b1804b1-3f736e0c9b1so1349615e9.3 for ; Tue, 13 Jun 2023 17:01:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=davidgf-es.20221208.gappssmtp.com; s=20221208; t=1686700913; x=1689292913; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=1Ku7Z/qnp8AOtndvRTkMXDZowwP0QIpA7RvHbTOA3jY=; b=tVX0yj7YaDy97AcA1qh6XWJ7Xf+7qaM82Zh5A3FaxDq3fnHgEOWINUvMkSHTCoT5j8 TfL4YETR9yluAbesQQ3OLislxxDIOmTjGl1mI5uWkQTxvhf3kySyCoxnAw7KeDWdhoDK F9WEfloRj+jV+cvHnx/9K36JwYDH2UnZfpPED2mboV6s656TbvT3ubSzotymy2yWTKYv uJFtcnsD5UhhA6Jawt3EufZ4OwY0FLhjw4v/rrzkfA/jBjmNlqVKW8dF7z3v7+IY1zlo fbQUQOl9/8FWrYkm8RaX4caAsHmb3myZZboSQHWLfnyr+RjPoTpiR9hezpPrF8fe3rE6 88aA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1686700913; x=1689292913; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=1Ku7Z/qnp8AOtndvRTkMXDZowwP0QIpA7RvHbTOA3jY=; b=W0UH3s9HqX56BaPGjnGy1VVYbjqPu+e9JbzKr7Oz3JhEizlMSr+IAOn01dEE5GQvWn GJfpdqzSNj/nJMkm/E7lgCt/oEcpWi9CY947IG2cz/fjob1i9fPFqb9MFh0mO9wXTQmf u1D9PS4kV+Ua1nAsFT9UMHX9t9hh17eisdEtcPgm64wgTPRp8O8FCVcPJopALs1bUjb8 irb9i2yOp9mRHnz8naABADO8NFcGVF58WLyNcgLl6GGlfrkSP8ri9SbgfbqwTwvr6HYo dsqXJoRV3Pj1wbEEReqL6bH0/VdDnbzHUF/WcGLlGqunXX0LqcmQhmiBI8B7qMRFyH+v Vm5A== X-Gm-Message-State: AC+VfDyaUVnamoeDBt9EXoEx9+0N81dKYi6nl6bnkwMeb9lcKSbHaaTg VfsHCvIEwwhs2CX0uQWnwocJTp/9Vigc6fs6dw== X-Google-Smtp-Source: ACHHUZ5aIfIi16VLNsnRD7TAKJAjwQ0kRTVpc92znC13FakDVDfGOjBwHMtgXo/hmq8dI8cQamaF3g== X-Received: by 2002:a5d:684a:0:b0:30f:befc:d864 with SMTP id o10-20020a5d684a000000b0030fbefcd864mr6514751wrw.62.1686700912814; Tue, 13 Jun 2023 17:01:52 -0700 (PDT) Received: from localhost.localdomain ([37.17.237.79]) by smtp.gmail.com with ESMTPSA id p17-20020a1c7411000000b003f7e4639aabsm15726702wmc.10.2023.06.13.17.01.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 13 Jun 2023 17:01:52 -0700 (PDT) From: david@davidgf.es To: binutils@sourceware.org Cc: David Guillen Fandos Subject: [PATCH v2 2/3] Add rotation instructions to MIPS Allegrex CPU Date: Wed, 14 Jun 2023 02:01:47 +0200 Message-Id: <20230614000148.10989-3-david@davidgf.es> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230614000148.10989-1-david@davidgf.es> References: <20230614000148.10989-1-david@davidgf.es> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-10.5 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,GIT_PATCH_0,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_SOFTFAIL,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: From: David Guillen Fandos The Allegrex CPU supports bit rotation instructions as described in the MIPS32 release 2 CPU (even though it is a MIPS-2 based CPU). Signed-off-by: David Guillen Fandos --- gas/config/tc-mips.c | 2 +- opcodes/mips-opc.c | 14 +++++++------- gas/testsuite/gas/mips/mips.exp | 2 +- 3 files changed, 9 insertions(+), 9 deletions(-) diff --git a/gas/config/tc-mips.c b/gas/config/tc-mips.c index 3c42d59e5b..d46a427503 100644 --- a/gas/config/tc-mips.c +++ b/gas/config/tc-mips.c @@ -526,7 +526,7 @@ static int mips_32bitmode = 0; #define CPU_HAS_DROR(CPU) ((CPU) == CPU_VR5400 || (CPU) == CPU_VR5500) /* True if CPU has a ror instruction. */ -#define CPU_HAS_ROR(CPU) CPU_HAS_DROR (CPU) +#define CPU_HAS_ROR(CPU) (CPU_HAS_DROR (CPU) || (CPU) == CPU_ALLEGREX) /* True if CPU is in the Octeon family. */ #define CPU_IS_OCTEON(CPU) ((CPU) == CPU_OCTEON || (CPU) == CPU_OCTEONP \ diff --git a/opcodes/mips-opc.c b/opcodes/mips-opc.c index ec897029af..9375ba3318 100644 --- a/opcodes/mips-opc.c +++ b/opcodes/mips-opc.c @@ -1810,13 +1810,13 @@ const struct mips_opcode mips_builtin_opcodes[] = {"rol", "d,v,I", 0, (int) M_ROL_I, INSN_MACRO, 0, I1, 0, 0 }, {"ror", "d,v,t", 0, (int) M_ROR, INSN_MACRO, 0, I1, 0, 0 }, {"ror", "d,v,I", 0, (int) M_ROR_I, INSN_MACRO, 0, I1, 0, 0 }, -{"ror", "d,w,<", 0x00200002, 0xffe0003f, WR_1|RD_2, 0, N5|I33, SMT, 0 }, -{"rorv", "d,t,s", 0x00000046, 0xfc0007ff, WR_1|RD_2|RD_3, 0, N5|I33, SMT, 0 }, -{"rotl", "d,v,t", 0, (int) M_ROL, INSN_MACRO, 0, I33, SMT, 0 }, -{"rotl", "d,v,I", 0, (int) M_ROL_I, INSN_MACRO, 0, I33, SMT, 0 }, -{"rotr", "d,v,t", 0, (int) M_ROR, INSN_MACRO, 0, I33, SMT, 0 }, -{"rotr", "d,v,I", 0, (int) M_ROR_I, INSN_MACRO, 0, I33, SMT, 0 }, -{"rotrv", "d,t,s", 0x00000046, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I33, SMT, 0 }, +{"ror", "d,w,<", 0x00200002, 0xffe0003f, WR_1|RD_2, 0, N5|I33|AL, SMT, 0 }, +{"rorv", "d,t,s", 0x00000046, 0xfc0007ff, WR_1|RD_2|RD_3, 0, N5|I33|AL, SMT, 0 }, +{"rotl", "d,v,t", 0, (int) M_ROL, INSN_MACRO, 0, I33|AL, SMT, 0 }, +{"rotl", "d,v,I", 0, (int) M_ROL_I, INSN_MACRO, 0, I33|AL, SMT, 0 }, +{"rotr", "d,v,t", 0, (int) M_ROR, INSN_MACRO, 0, I33|AL, SMT, 0 }, +{"rotr", "d,v,I", 0, (int) M_ROR_I, INSN_MACRO, 0, I33|AL, SMT, 0 }, +{"rotrv", "d,t,s", 0x00000046, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I33|AL, SMT, 0 }, {"round.l.d", "D,S", 0x46200008, 0xffff003f, WR_1|RD_2|FP_D, 0, I3_33, 0, 0 }, {"round.l.s", "D,S", 0x46000008, 0xffff003f, WR_1|RD_2|FP_S|FP_D, 0, I3_33, 0, 0 }, {"round.w.d", "D,S", 0x4620000c, 0xffff003f, WR_1|RD_2|FP_S|FP_D, 0, I2, 0, SF }, diff --git a/gas/testsuite/gas/mips/mips.exp b/gas/testsuite/gas/mips/mips.exp index 6dbf2e3746..f4137c5640 100644 --- a/gas/testsuite/gas/mips/mips.exp +++ b/gas/testsuite/gas/mips/mips.exp @@ -517,7 +517,7 @@ mips_arch_create r3000 32 mips1 {} \ mips_arch_create r3900 32 mips1 { gpr_ilocks } \ { -march=r3900 -mtune=r3900 } { -mmips:3900 } \ { mipstx39-*-* mipstx39el-*-* } -mips_arch_create allegrex 32 mips2 { oddspreg singlefloat } \ +mips_arch_create allegrex 32 mips2 { oddspreg ror singlefloat } \ { -march=allegrex -mtune=allegrex } \ { -mmips:allegrex } mips_arch_create r4000 64 mips3 {} \ -- 2.40.1