From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-yw1-x114a.google.com (mail-yw1-x114a.google.com [IPv6:2607:f8b0:4864:20::114a]) by sourceware.org (Postfix) with ESMTPS id 3DBC4385841A for ; Thu, 29 Jun 2023 17:18:50 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 3DBC4385841A Authentication-Results: sourceware.org; dmarc=pass (p=reject dis=none) header.from=google.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=flex--nhuck.bounces.google.com Received: by mail-yw1-x114a.google.com with SMTP id 00721157ae682-565d1b86a64so7219457b3.3 for ; Thu, 29 Jun 2023 10:18:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20221208; t=1688059129; x=1690651129; h=content-transfer-encoding:cc:to:from:subject:message-id:references :mime-version:in-reply-to:date:from:to:cc:subject:date:message-id :reply-to; bh=OirzkJeHnH7C44+hF8yCgYhlLE30eQ+S3fRwVw/fOPQ=; b=VKDOYLRFDe52EX4TZUBWmAiFiUUtGAvLZBKPDPcDJvZ58paW7AXoIlnCly+eoMHMh0 6VED34ifKE7TmZ1Bi2Ita7J4iHyDm9BdF6LkW21yvTRUE666QWPjKOUYmSGcL54MH8uv e5+Z1qEfISaJAKdgfqE5+PV5qe3QQoQZjxgKxTsuXrVHWApqTufoIV9jgo+7dxUQ03ff CB10+BzCgfVtr96oDX2FwMqG81Jm2zVfo1BkxZFljM4hi0Dk88StfzALGg4cLCx0Se8M rFHVI56PAd10lrcQFdgzJFue41aUXPxvtIBUTgMiydpk6qMEmomx99YhXQt8yopr9Or/ rGPA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1688059129; x=1690651129; h=content-transfer-encoding:cc:to:from:subject:message-id:references :mime-version:in-reply-to:date:x-gm-message-state:from:to:cc:subject :date:message-id:reply-to; bh=OirzkJeHnH7C44+hF8yCgYhlLE30eQ+S3fRwVw/fOPQ=; b=I2MWDP+v6Xqm2jBnrxYEM4mAN6atU5H+ADUUEeoBOcFJnkElaGPQDu+6A1Bw/juO65 2KI/gE6bRA0MctpwySpu5w83VvNgJKrdKGU4aKHxbQ4/UdV/g5jRX0OMQZWcq92LqhE9 gWbgG9r5iAseRRZWxINN+4ogvuk7Kop/pxsMoJ1Mo/UVUZ5WxDugO1/3isFsRcr2L7nd 6hdfRaHl+1ysI85+oEgSIv47gaIR0fyR61DP2lkF0swZs4HNmlhvGBiDb9XIzvQZiNTg uQ1zaSCk4pUW1rtaAIk4Jb1qB/aWr3mUhSdh5nS6wrWSDBVvldNLjP5MTUsac3bsYGrF eDmg== X-Gm-Message-State: ABy/qLbQkiI5d2TGr8GA94xlZfZ3jgK/aCcwN5kYjfOFt1wix8QpJ24u ZdBMaQEmaxzp3jwzMb8RvHnMKOI+7bytZKJaZVkxOI8qC/r6QA7pb0Wj4Wc+i6a+3yojIfQ3wyi VGQvjhp7l4JSuNx0zPbYs7CmuHLLhCz4M5p6yqIs1oNa4dhgyXVenDr5lHCnP X-Google-Smtp-Source: APBJJlEDIetoTI24/HN53KMSaxTn1WsdnrlmSPTlskKskTfSWDiEZoBcvNFLmpXlQ5FOGula9xcVrdbjWg== X-Received: from nhuck.c.googlers.com ([fda3:e722:ac3:cc00:14:4d90:c0a8:39cc]) (user=nhuck job=sendgmr) by 2002:a81:6d8e:0:b0:56d:3c2b:2471 with SMTP id i136-20020a816d8e000000b0056d3c2b2471mr171ywc.3.1688059129696; Thu, 29 Jun 2023 10:18:49 -0700 (PDT) Date: Thu, 29 Jun 2023 10:18:29 -0700 In-Reply-To: <20230629171839.573187-1-nhuck@google.com> Mime-Version: 1.0 References: <20230629171839.573187-1-nhuck@google.com> X-Mailer: git-send-email 2.41.0.255.g8b1d071c50-goog Message-ID: <20230629171839.573187-5-nhuck@google.com> Subject: [PATCH 04/14] Add support for the Zvkned ISA extension. From: Nathan Huckleberry To: binutils@sourceware.org Cc: nhuck@pmull.org, "=?UTF-8?q?Christoph=20M=C3=BCllner?=" , Nathan Huckleberry Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Spam-Status: No, score=-20.5 required=5.0 tests=BAYES_00,DKIMWL_WL_MED,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,GIT_PATCH_0,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE,USER_IN_DEF_DKIM_WL autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: From: Christoph M=C3=BCllner Zvkned is part of the vector crypto extensions. This extension adds the following instructions: - vaesef.[vv,vs] - vaesem.[vv,vs] - vaesdf.[vv,vs] - vaesdm.[vv,vs] - vaeskf1.vi - vaeskf2.vi - vaesz.vs Signed-off-by: Christoph M=C3=BCllner [Updated to newest version of RISC-V spec] Signed-off-by: Nathan Huckleberry --- bfd/elfxx-riscv.c | 5 +++++ gas/testsuite/gas/riscv/zvkned.d | 21 +++++++++++++++++++ gas/testsuite/gas/riscv/zvkned.s | 13 ++++++++++++ include/opcode/riscv-opc.h | 35 ++++++++++++++++++++++++++++++++ include/opcode/riscv.h | 1 + opcodes/riscv-opc.c | 13 ++++++++++++ 6 files changed, 88 insertions(+) create mode 100644 gas/testsuite/gas/riscv/zvkned.d create mode 100644 gas/testsuite/gas/riscv/zvkned.s diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c index b51d4f4438f..cb3420540e9 100644 --- a/bfd/elfxx-riscv.c +++ b/bfd/elfxx-riscv.c @@ -1262,6 +1262,7 @@ static struct riscv_supported_ext riscv_supported_std= _z_ext[] =3D {"zvbb", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"zvbc", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"zvkg", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"zvkned", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"zvl32b", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"zvl64b", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"zvl128b", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, @@ -2420,6 +2421,8 @@ riscv_multi_subset_supports (riscv_parse_subset_t *rp= s, return riscv_subset_supports (rps, "zvbc"); case INSN_CLASS_ZVKG: return riscv_subset_supports (rps, "zvkg"); + case INSN_CLASS_ZVKNED: + return riscv_subset_supports (rps, "zvkned"); case INSN_CLASS_SVINVAL: return riscv_subset_supports (rps, "svinval"); case INSN_CLASS_H: @@ -2586,6 +2589,8 @@ riscv_multi_subset_supports_ext (riscv_parse_subset_t= *rps, return _("zvbc"); case INSN_CLASS_ZVKG: return _("zvkg"); + case INSN_CLASS_ZVKNED: + return _("zvkned"); case INSN_CLASS_SVINVAL: return "svinval"; case INSN_CLASS_H: diff --git a/gas/testsuite/gas/riscv/zvkned.d b/gas/testsuite/gas/riscv/zvk= ned.d new file mode 100644 index 00000000000..0b09da9dbc2 --- /dev/null +++ b/gas/testsuite/gas/riscv/zvkned.d @@ -0,0 +1,21 @@ +#as: -march=3Drv64gc_zvkned +#objdump: -dr + +.*:[ ]+file format .* + + +Disassembly of section .text: +0+000 <.text>: +[ ]+[0-9a-f]+:[ ]+a280a277[ ]+vaesdf.vv[ ]+v4,v8 +[ ]+[0-9a-f]+:[ ]+a680a277[ ]+vaesdf.vs[ ]+v4,v8 +[ ]+[0-9a-f]+:[ ]+a2802277[ ]+vaesdm.vv[ ]+v4,v8 +[ ]+[0-9a-f]+:[ ]+a6802277[ ]+vaesdm.vs[ ]+v4,v8 +[ ]+[0-9a-f]+:[ ]+a281a277[ ]+vaesef.vv[ ]+v4,v8 +[ ]+[0-9a-f]+:[ ]+a681a277[ ]+vaesef.vs[ ]+v4,v8 +[ ]+[0-9a-f]+:[ ]+a2812277[ ]+vaesem.vv[ ]+v4,v8 +[ ]+[0-9a-f]+:[ ]+a6812277[ ]+vaesem.vs[ ]+v4,v8 +[ ]+[0-9a-f]+:[ ]+8a812277[ ]+vaeskf1.vi[ ]+v4,v8,2 +[ ]+[0-9a-f]+:[ ]+8a872277[ ]+vaeskf1.vi[ ]+v4,v8,14 +[ ]+[0-9a-f]+:[ ]+aa812277[ ]+vaeskf2.vi[ ]+v4,v8,2 +[ ]+[0-9a-f]+:[ ]+aa872277[ ]+vaeskf2.vi[ ]+v4,v8,14 +[ ]+[0-9a-f]+:[ ]+a683a277[ ]+vaesz.vs[ ]+v4,v8 diff --git a/gas/testsuite/gas/riscv/zvkned.s b/gas/testsuite/gas/riscv/zvk= ned.s new file mode 100644 index 00000000000..f0f3811eaec --- /dev/null +++ b/gas/testsuite/gas/riscv/zvkned.s @@ -0,0 +1,13 @@ + vaesdf.vv v4, v8 + vaesdf.vs v4, v8 + vaesdm.vv v4, v8 + vaesdm.vs v4, v8 + vaesef.vv v4, v8 + vaesef.vs v4, v8 + vaesem.vv v4, v8 + vaesem.vs v4, v8 + vaeskf1.vi v4, v8, 2 + vaeskf1.vi v4, v8, 14 + vaeskf2.vi v4, v8, 2 + vaeskf2.vi v4, v8, 14 + vaesz.vs v4, v8 diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h index 9bc75fd0e59..48ba80cda63 100644 --- a/include/opcode/riscv-opc.h +++ b/include/opcode/riscv-opc.h @@ -2102,6 +2102,29 @@ #define MASK_VGHSH_VV 0xfe00707f #define MATCH_VGMUL_VV 0xa208a077 #define MASK_VGMUL_VV 0xfe0ff07f +/* Zvkned instructions. */ +#define MATCH_VAESDF_VS 0xa600a077 +#define MASK_VAESDF_VS 0xfe0ff07f +#define MATCH_VAESDF_VV 0xa200a077 +#define MASK_VAESDF_VV 0xfe0ff07f +#define MATCH_VAESDM_VS 0xa6002077 +#define MASK_VAESDM_VS 0xfe0ff07f +#define MATCH_VAESDM_VV 0xa2002077 +#define MASK_VAESDM_VV 0xfe0ff07f +#define MATCH_VAESEF_VS 0xa601a077 +#define MASK_VAESEF_VS 0xfe0ff07f +#define MATCH_VAESEF_VV 0xa201a077 +#define MASK_VAESEF_VV 0xfe0ff07f +#define MATCH_VAESEM_VS 0xa6012077 +#define MASK_VAESEM_VS 0xfe0ff07f +#define MATCH_VAESEM_VV 0xa2012077 +#define MASK_VAESEM_VV 0xfe0ff07f +#define MATCH_VAESKF1_VI 0x8a002077 +#define MASK_VAESKF1_VI 0xfe00707f +#define MATCH_VAESKF2_VI 0xaa002077 +#define MASK_VAESKF2_VI 0xfe00707f +#define MATCH_VAESZ_VS 0xa603a077 +#define MASK_VAESZ_VS 0xfe0ff07f /* Svinval instruction. */ #define MATCH_SINVAL_VMA 0x16000073 #define MASK_SINVAL_VMA 0xfe007fff @@ -3195,6 +3218,18 @@ DECLARE_INSN(vclmulh_vx, MATCH_VCLMULH_VX, MASK_VCLM= ULH_VX) /* Zvkg instructions. */ DECLARE_INSN(vghsh_vv, MATCH_VGHSH_VV, MASK_VGHSH_VV) DECLARE_INSN(vgmul_vv, MATCH_VGMUL_VV, MASK_VGMUL_VV) +/* Zvkned instructions. */ +DECLARE_INSN(vaesdf_vs, MATCH_VAESDF_VS, MASK_VAESDF_VS) +DECLARE_INSN(vaesdf_vv, MATCH_VAESDF_VV, MASK_VAESDF_VV) +DECLARE_INSN(vaesdm_vs, MATCH_VAESDM_VS, MASK_VAESDM_VS) +DECLARE_INSN(vaesdm_vv, MATCH_VAESDM_VV, MASK_VAESDM_VV) +DECLARE_INSN(vaesef_vs, MATCH_VAESEF_VS, MASK_VAESEF_VS) +DECLARE_INSN(vaesef_vv, MATCH_VAESEF_VV, MASK_VAESEF_VV) +DECLARE_INSN(vaesem_vs, MATCH_VAESEM_VS, MASK_VAESEM_VS) +DECLARE_INSN(vaesem_vv, MATCH_VAESEM_VV, MASK_VAESEM_VV) +DECLARE_INSN(vaeskf1_vi, MATCH_VAESKF1_VI, MASK_VAESKF1_VI) +DECLARE_INSN(vaeskf2_vi, MATCH_VAESKF2_VI, MASK_VAESKF2_VI) +DECLARE_INSN(vaesz_vs, MATCH_VAESZ_VS, MASK_VAESZ_VS) /* Vendor-specific (T-Head) XTheadBa instructions. */ DECLARE_INSN(th_addsl, MATCH_TH_ADDSL, MASK_TH_ADDSL) /* Vendor-specific (T-Head) XTheadBb instructions. */ diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h index ae13dc17022..e921e1b8a2a 100644 --- a/include/opcode/riscv.h +++ b/include/opcode/riscv.h @@ -412,6 +412,7 @@ enum riscv_insn_class INSN_CLASS_ZVBB, INSN_CLASS_ZVBC, INSN_CLASS_ZVKG, + INSN_CLASS_ZVKNED, INSN_CLASS_SVINVAL, INSN_CLASS_ZICBOM, INSN_CLASS_ZICBOP, diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c index 09c8444ee74..7e73c1a739d 100644 --- a/opcodes/riscv-opc.c +++ b/opcodes/riscv-opc.c @@ -1843,6 +1843,19 @@ const struct riscv_opcode riscv_opcodes[] =3D {"vghsh.vv", 0, INSN_CLASS_ZVKG, "Vd,Vt,Vs", MATCH_VGHSH_VV, MASK_VGHSH_= VV, match_opcode, 0}, {"vgmul.vv", 0, INSN_CLASS_ZVKG, "Vd,Vt", MATCH_VGMUL_VV, MASK_VGMUL_VV,= match_opcode, 0}, =20 +/* Zvkned instructions. */ +{"vaesdf.vv", 0, INSN_CLASS_ZVKNED, "Vd,Vt", MATCH_VAESDF_VV, MASK_VAESD= F_VV, match_opcode, 0}, +{"vaesdf.vs", 0, INSN_CLASS_ZVKNED, "Vd,Vt", MATCH_VAESDF_VS, MASK_VAESD= F_VV, match_opcode, 0}, +{"vaesdm.vv", 0, INSN_CLASS_ZVKNED, "Vd,Vt", MATCH_VAESDM_VV, MASK_VAESD= M_VV, match_opcode, 0}, +{"vaesdm.vs", 0, INSN_CLASS_ZVKNED, "Vd,Vt", MATCH_VAESDM_VS, MASK_VAESD= M_VV, match_opcode, 0}, +{"vaesef.vv", 0, INSN_CLASS_ZVKNED, "Vd,Vt", MATCH_VAESEF_VV, MASK_VAESE= F_VV, match_opcode, 0}, +{"vaesef.vs", 0, INSN_CLASS_ZVKNED, "Vd,Vt", MATCH_VAESEF_VS, MASK_VAESE= F_VV, match_opcode, 0}, +{"vaesem.vv", 0, INSN_CLASS_ZVKNED, "Vd,Vt", MATCH_VAESEM_VV, MASK_VAESE= M_VV, match_opcode, 0}, +{"vaesem.vs", 0, INSN_CLASS_ZVKNED, "Vd,Vt", MATCH_VAESEM_VS, MASK_VAESE= M_VV, match_opcode, 0}, +{"vaeskf1.vi", 0, INSN_CLASS_ZVKNED, "Vd,Vt,Vj", MATCH_VAESKF1_VI, MASK_= VAESKF1_VI, match_opcode, 0}, +{"vaeskf2.vi", 0, INSN_CLASS_ZVKNED, "Vd,Vt,Vj", MATCH_VAESKF2_VI, MASK_= VAESKF2_VI, match_opcode, 0}, +{"vaesz.vs", 0, INSN_CLASS_ZVKNED, "Vd,Vt", MATCH_VAESZ_VS, MASK_VAESZ= _VS, match_opcode, 0}, + /* Supervisor instructions. */ {"csrr", 0, INSN_CLASS_ZICSR, "d,E", MATCH_CSRRS, MASK_CSRRS|MASK_= RS1, match_opcode, INSN_ALIAS }, {"csrw", 0, INSN_CLASS_ZICSR, "E,s", MATCH_CSRRW, MASK_CSRRW|MASK_= RD, match_opcode, INSN_ALIAS }, --=20 2.41.0.255.g8b1d071c50-goog