From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-yw1-x114a.google.com (mail-yw1-x114a.google.com [IPv6:2607:f8b0:4864:20::114a]) by sourceware.org (Postfix) with ESMTPS id 296BE3858425 for ; Thu, 29 Jun 2023 17:18:52 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 296BE3858425 Authentication-Results: sourceware.org; dmarc=pass (p=reject dis=none) header.from=google.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=flex--nhuck.bounces.google.com Received: by mail-yw1-x114a.google.com with SMTP id 00721157ae682-573cacf4804so7608437b3.1 for ; Thu, 29 Jun 2023 10:18:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20221208; t=1688059131; x=1690651131; h=content-transfer-encoding:cc:to:from:subject:message-id:references :mime-version:in-reply-to:date:from:to:cc:subject:date:message-id :reply-to; bh=AIdKWwuTyS5aAcle4JdhFuT3sMrEn41H5UThiyrDHhc=; b=6W2y0rWYpawBu16/astHJHNcSZatEG6wD3zqJYUmJ1wh7tV7tNhZMkxtS+UsDy8Q8L G6qVKyNVMvh9fJaFTLpU/nAmIbSl/7Zn0ucvAvy03cfKxovMpvUAI7FI48WUmj+N7S+i nt7Hn1WzlIiWk1y4FgQ1VSaLKD76ZrHxOAtVwCYpqPTFkpzoCKC9Q5hhs3lXozP7JQ7a bf5qwt+DX8vxHu+5KMuw37m4BAwQK7OsnNmVvrlCdam23QMtrQ8rcQhWAzcDforL8bIH smRKtElMsPMktIdn2eWSi99y1+MAM6tboX4YNn6lr4gL2NVs8K+x2YUM0XRp7AVFC8wN k6uA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1688059131; x=1690651131; h=content-transfer-encoding:cc:to:from:subject:message-id:references :mime-version:in-reply-to:date:x-gm-message-state:from:to:cc:subject :date:message-id:reply-to; bh=AIdKWwuTyS5aAcle4JdhFuT3sMrEn41H5UThiyrDHhc=; b=GiviWMoD6eBcBBhPG4vHbWcwJ46+v8yDLSNcVB6x3hVDkWKPlpb3kOOvznfH8utEfA 8orlPRkS+Jd4lb0AeCCj58lKd1kNn/RMOksZW1n+b3v6mIxoOlGre01/oLh1xp++frX4 ckG0Wc0z6vxIukbeGFura5fAbQnkbrETktAwPhvhQ2+bMeBF4nCvNFyPtgkckaWUES9r sidYHZzmWm6DexhsyT4GB5X9ixgDItLxHZjSRr2F3SgvdXkLj9wA9SoZBbms0BsX/VH2 KY+V1c9+JP3C876N1lN0njngyFvjNDtROwkW+NfnUMaSCdHsa+trRpRGhylX61QoxQkW KRDA== X-Gm-Message-State: ABy/qLZLYvH1h0U2E8YQmipCmUZR4nstluhTuYGtsdpmorwnUjMV+Gsf jJvlzTi1m7ti3L/+pNN84mZLkK9Q+RvOBtWXKb3SZk3nnBBzkf9m1V1FmyuNQ4A5ok0hyIHw9xH DMP4xflqgPeHFqlaRC1JD02tkZEq2owZlzFoR9veiSvFovkGmUdJi3sWWmPu2 X-Google-Smtp-Source: APBJJlGnPGmk13KlvOKt5fzg2KwJE61gzWL2uLPb5aPFOFvLIPS674CwpXDBnVjdDyLD/soCyPaC2EnVyA== X-Received: from nhuck.c.googlers.com ([fda3:e722:ac3:cc00:14:4d90:c0a8:39cc]) (user=nhuck job=sendgmr) by 2002:a81:8d52:0:b0:577:2d24:4217 with SMTP id w18-20020a818d52000000b005772d244217mr158ywj.7.1688059131517; Thu, 29 Jun 2023 10:18:51 -0700 (PDT) Date: Thu, 29 Jun 2023 10:18:30 -0700 In-Reply-To: <20230629171839.573187-1-nhuck@google.com> Mime-Version: 1.0 References: <20230629171839.573187-1-nhuck@google.com> X-Mailer: git-send-email 2.41.0.255.g8b1d071c50-goog Message-ID: <20230629171839.573187-6-nhuck@google.com> Subject: [PATCH 05/14] Add support for the Zvknh[a,b] ISA extensions. From: Nathan Huckleberry To: binutils@sourceware.org Cc: nhuck@pmull.org, "=?UTF-8?q?Christoph=20M=C3=BCllner?=" , Nathan Huckleberry Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Spam-Status: No, score=-20.6 required=5.0 tests=BAYES_00,DKIMWL_WL_MED,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,GIT_PATCH_0,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE,USER_IN_DEF_DKIM_WL autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: From: Christoph M=C3=BCllner Zvknh[a,b] are parts of the vector crypto extensions. This extension adds the following instructions: - vsha2ms.vv - vsha2c[hl].vv Signed-off-by: Christoph M=C3=BCllner [Updated to newest version of RISC-V spec] Signed-off-by: Nathan Huckleberry --- bfd/elfxx-riscv.c | 13 +++++++++++++ gas/testsuite/gas/riscv/zvknha.d | 12 ++++++++++++ gas/testsuite/gas/riscv/zvknha_zvknhb.s | 3 +++ gas/testsuite/gas/riscv/zvknhb.d | 12 ++++++++++++ include/opcode/riscv-opc.h | 11 +++++++++++ include/opcode/riscv.h | 3 +++ opcodes/riscv-opc.c | 5 +++++ 7 files changed, 59 insertions(+) create mode 100644 gas/testsuite/gas/riscv/zvknha.d create mode 100644 gas/testsuite/gas/riscv/zvknha_zvknhb.s create mode 100644 gas/testsuite/gas/riscv/zvknhb.d diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c index cb3420540e9..adcc606fe7e 100644 --- a/bfd/elfxx-riscv.c +++ b/bfd/elfxx-riscv.c @@ -1263,6 +1263,8 @@ static struct riscv_supported_ext riscv_supported_std= _z_ext[] =3D {"zvbc", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"zvkg", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"zvkned", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"zvknha", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"zvknhb", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"zvl32b", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"zvl64b", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"zvl128b", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, @@ -2423,6 +2425,13 @@ riscv_multi_subset_supports (riscv_parse_subset_t *r= ps, return riscv_subset_supports (rps, "zvkg"); case INSN_CLASS_ZVKNED: return riscv_subset_supports (rps, "zvkned"); + case INSN_CLASS_ZVKNHA: + return riscv_subset_supports (rps, "zvknha"); + case INSN_CLASS_ZVKNHB: + return riscv_subset_supports (rps, "zvknhb"); + case INSN_CLASS_ZVKNHA_OR_ZVKNHB: + return (riscv_subset_supports (rps, "zvknha") + || riscv_subset_supports (rps, "zvknhb")); case INSN_CLASS_SVINVAL: return riscv_subset_supports (rps, "svinval"); case INSN_CLASS_H: @@ -2591,6 +2600,10 @@ riscv_multi_subset_supports_ext (riscv_parse_subset_= t *rps, return _("zvkg"); case INSN_CLASS_ZVKNED: return _("zvkned"); + case INSN_CLASS_ZVKNHA: + return _("zvknha"); + case INSN_CLASS_ZVKNHB: + return _("zvknhb"); case INSN_CLASS_SVINVAL: return "svinval"; case INSN_CLASS_H: diff --git a/gas/testsuite/gas/riscv/zvknha.d b/gas/testsuite/gas/riscv/zvk= nha.d new file mode 100644 index 00000000000..36d660f634f --- /dev/null +++ b/gas/testsuite/gas/riscv/zvknha.d @@ -0,0 +1,12 @@ +#as: -march=3Drv64gc_zvknha +#source: zvknha_zvknhb.s +#objdump: -dr + +.*:[ ]+file format .* + + +Disassembly of section .text: +0+000 <.text>: +[ ]+[0-9a-f]+:[ ]+ba862277[ ]+vsha2ch.vv[ ]+v4,v8,v12 +[ ]+[0-9a-f]+:[ ]+be862277[ ]+vsha2cl.vv[ ]+v4,v8,v12 +[ ]+[0-9a-f]+:[ ]+b6862277[ ]+vsha2ms.vv[ ]+v4,v8,v12 diff --git a/gas/testsuite/gas/riscv/zvknha_zvknhb.s b/gas/testsuite/gas/ri= scv/zvknha_zvknhb.s new file mode 100644 index 00000000000..d20e6310531 --- /dev/null +++ b/gas/testsuite/gas/riscv/zvknha_zvknhb.s @@ -0,0 +1,3 @@ + vsha2ch.vv v4, v8, v12 + vsha2cl.vv v4, v8, v12 + vsha2ms.vv v4, v8, v12 diff --git a/gas/testsuite/gas/riscv/zvknhb.d b/gas/testsuite/gas/riscv/zvk= nhb.d new file mode 100644 index 00000000000..ab0f035889e --- /dev/null +++ b/gas/testsuite/gas/riscv/zvknhb.d @@ -0,0 +1,12 @@ +#as: -march=3Drv64gc_zvknhb +#source: zvknha_zvknhb.s +#objdump: -dr + +.*:[ ]+file format .* + + +Disassembly of section .text: +0+000 <.text>: +[ ]+[0-9a-f]+:[ ]+ba862277[ ]+vsha2ch.vv[ ]+v4,v8,v12 +[ ]+[0-9a-f]+:[ ]+be862277[ ]+vsha2cl.vv[ ]+v4,v8,v12 +[ ]+[0-9a-f]+:[ ]+b6862277[ ]+vsha2ms.vv[ ]+v4,v8,v12 diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h index 48ba80cda63..5590dc3b014 100644 --- a/include/opcode/riscv-opc.h +++ b/include/opcode/riscv-opc.h @@ -2125,6 +2125,13 @@ #define MASK_VAESKF2_VI 0xfe00707f #define MATCH_VAESZ_VS 0xa603a077 #define MASK_VAESZ_VS 0xfe0ff07f +/* Zvknh[a,b] instructions. */ +#define MATCH_VSHA2CH_VV 0xba002077 +#define MASK_VSHA2CH_VV 0xfe00707f +#define MATCH_VSHA2CL_VV 0xbe002077 +#define MASK_VSHA2CL_VV 0xfe00707f +#define MATCH_VSHA2MS_VV 0xb6002077 +#define MASK_VSHA2MS_VV 0xfe00707f /* Svinval instruction. */ #define MATCH_SINVAL_VMA 0x16000073 #define MASK_SINVAL_VMA 0xfe007fff @@ -3230,6 +3237,10 @@ DECLARE_INSN(vaesem_vv, MATCH_VAESEM_VV, MASK_VAESEM= _VV) DECLARE_INSN(vaeskf1_vi, MATCH_VAESKF1_VI, MASK_VAESKF1_VI) DECLARE_INSN(vaeskf2_vi, MATCH_VAESKF2_VI, MASK_VAESKF2_VI) DECLARE_INSN(vaesz_vs, MATCH_VAESZ_VS, MASK_VAESZ_VS) +/* Zvknh[a,b] instructions. */ +DECLARE_INSN(vsha2ch_vv, MATCH_VSHA2CH_VV, MASK_VSHA2CH_VV) +DECLARE_INSN(vsha2cl_vv, MATCH_VSHA2CL_VV, MASK_VSHA2CL_VV) +DECLARE_INSN(vsha2ms_vv, MATCH_VSHA2MS_VV, MASK_VSHA2MS_VV) /* Vendor-specific (T-Head) XTheadBa instructions. */ DECLARE_INSN(th_addsl, MATCH_TH_ADDSL, MASK_TH_ADDSL) /* Vendor-specific (T-Head) XTheadBb instructions. */ diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h index e921e1b8a2a..4ceb191ab07 100644 --- a/include/opcode/riscv.h +++ b/include/opcode/riscv.h @@ -413,6 +413,9 @@ enum riscv_insn_class INSN_CLASS_ZVBC, INSN_CLASS_ZVKG, INSN_CLASS_ZVKNED, + INSN_CLASS_ZVKNHA, + INSN_CLASS_ZVKNHB, + INSN_CLASS_ZVKNHA_OR_ZVKNHB, INSN_CLASS_SVINVAL, INSN_CLASS_ZICBOM, INSN_CLASS_ZICBOP, diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c index 7e73c1a739d..d7d3f1c1cd2 100644 --- a/opcodes/riscv-opc.c +++ b/opcodes/riscv-opc.c @@ -1856,6 +1856,11 @@ const struct riscv_opcode riscv_opcodes[] =3D {"vaeskf2.vi", 0, INSN_CLASS_ZVKNED, "Vd,Vt,Vj", MATCH_VAESKF2_VI, MASK_= VAESKF2_VI, match_opcode, 0}, {"vaesz.vs", 0, INSN_CLASS_ZVKNED, "Vd,Vt", MATCH_VAESZ_VS, MASK_VAESZ= _VS, match_opcode, 0}, =20 +/* Zvknh[a,b] instructions. */ +{"vsha2ch.vv", 0, INSN_CLASS_ZVKNHA_OR_ZVKNHB, "Vd,Vt,Vs", MATCH_VSHA2CH_= VV, MASK_VSHA2CH_VV, match_opcode, 0}, +{"vsha2cl.vv", 0, INSN_CLASS_ZVKNHA_OR_ZVKNHB, "Vd,Vt,Vs", MATCH_VSHA2CL_= VV, MASK_VSHA2CL_VV, match_opcode, 0}, +{"vsha2ms.vv", 0, INSN_CLASS_ZVKNHA_OR_ZVKNHB, "Vd,Vt,Vs", MATCH_VSHA2MS_= VV, MASK_VSHA2MS_VV, match_opcode, 0}, + /* Supervisor instructions. */ {"csrr", 0, INSN_CLASS_ZICSR, "d,E", MATCH_CSRRS, MASK_CSRRS|MASK_= RS1, match_opcode, INSN_ALIAS }, {"csrw", 0, INSN_CLASS_ZICSR, "E,s", MATCH_CSRRW, MASK_CSRRW|MASK_= RD, match_opcode, INSN_ALIAS }, --=20 2.41.0.255.g8b1d071c50-goog