From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-yw1-x1149.google.com (mail-yw1-x1149.google.com [IPv6:2607:f8b0:4864:20::1149]) by sourceware.org (Postfix) with ESMTPS id 9F2533858426 for ; Thu, 29 Jun 2023 17:18:54 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 9F2533858426 Authentication-Results: sourceware.org; dmarc=pass (p=reject dis=none) header.from=google.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=flex--nhuck.bounces.google.com Received: by mail-yw1-x1149.google.com with SMTP id 00721157ae682-5704991ea05so7594537b3.1 for ; Thu, 29 Jun 2023 10:18:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20221208; t=1688059134; x=1690651134; h=content-transfer-encoding:cc:to:from:subject:message-id:references :mime-version:in-reply-to:date:from:to:cc:subject:date:message-id :reply-to; bh=ovJfR2S/IFSjQRn8meJtK0YC11WZ7vnNjFpy98gt2gw=; b=k6mDxXniWik5wRLu5YmPr68yHWxXw4ujPKnAAgHPmd5h3JgIpo/OBrCf1Kv2xQEa4g IMxZHCFc5uLeOgF+U2yAZhPgxoyHI9iTVX4ZIl8tQmzk6AwdmgQDoLOo2xL/4y6JvBF3 8Yag8fCxmbcYmAnk1nqYlAdWF6Lq8VEOG6+RURcW3gyEmyjsfec0KVvY1lv8GKodBOPN xYokYJTRIwmOdAoMKTiMLyH1YLNYuZDVww+8bBvpQUysVFg6xr5oOuX05AkGHXCHgP2p tqxdOXTAnacEUby2R9PSZiSG7MrJ0DKpCF3Hh8HYJmJ+g1NxirrO/m5k5zLHniOI3hmW vKUA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1688059134; x=1690651134; h=content-transfer-encoding:cc:to:from:subject:message-id:references :mime-version:in-reply-to:date:x-gm-message-state:from:to:cc:subject :date:message-id:reply-to; bh=ovJfR2S/IFSjQRn8meJtK0YC11WZ7vnNjFpy98gt2gw=; b=Vp6vY4C8c6F/SFltWBuVZ2TNO0MqU9OrazKFkivpoCmRSqtQHrYPR6je7lNhBRLwDb LcnS8WfJz6dSFpHmonw2TBEBc9SGDgfV3/YC2xP4+rxMCqVBlrHohGLuWVdJY3lu3HvG xdJe0x8BsJGxoz69CwU2MY5TU1HxPTPf+XacMaUxi5hWJsx6KeYT5MrntVFy+uIz6RZ6 J5PbcC10hOBbLpRI3P0MkjGLfOHzGqNVc0GUonIPWVffTwEfWohL6KKR1IowbEMJ9sfx dgloDEGyvrc8llIvHx7tum3P9hbqx8TGC4dk9vBjwSv2eaAmiKI6OZ/CQBwWiT2A/UEc qcsw== X-Gm-Message-State: ABy/qLY6An2Ql6pFlXzK1FZEV6Ae0k4OJMiH1KXEb3dhexYO7ivtU2+j VyaG/WCA/OgbnKkEZn+gRyTd6Cwy3Ap3CAlUyFxWbawL3WlgLvWXTMaX3FDzC0ASJlWHchucDWg gQ8ty5vh5fgBgASKcV5nJ/2obDDoLR8EWphTJ35lXpbWe1LW3MJy2os6rkp4M X-Google-Smtp-Source: APBJJlGXQHwdr3a039sFxDjn9K+qHDiEUrni786Ua7j/DyYZ1P+x4XwMHBR5tbXXaNYEdL48WAXfUyt7cQ== X-Received: from nhuck.c.googlers.com ([fda3:e722:ac3:cc00:14:4d90:c0a8:39cc]) (user=nhuck job=sendgmr) by 2002:a05:690c:703:b0:573:8316:8d04 with SMTP id bs3-20020a05690c070300b0057383168d04mr162ywb.4.1688059134099; Thu, 29 Jun 2023 10:18:54 -0700 (PDT) Date: Thu, 29 Jun 2023 10:18:31 -0700 In-Reply-To: <20230629171839.573187-1-nhuck@google.com> Mime-Version: 1.0 References: <20230629171839.573187-1-nhuck@google.com> X-Mailer: git-send-email 2.41.0.255.g8b1d071c50-goog Message-ID: <20230629171839.573187-7-nhuck@google.com> Subject: [PATCH 06/14] Add support for the Zvksed ISA extension. From: Nathan Huckleberry To: binutils@sourceware.org Cc: nhuck@pmull.org, "=?UTF-8?q?Christoph=20M=C3=BCllner?=" , Nathan Huckleberry Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Spam-Status: No, score=-20.8 required=5.0 tests=BAYES_00,DKIMWL_WL_MED,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,GIT_PATCH_0,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE,USER_IN_DEF_DKIM_WL autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: From: Christoph M=C3=BCllner Zvksed is part of the vector crypto extensions. This extension adds the following instructions: - vsm4k.vi - vsm4r.[vv,vs] Signed-off-by: Christoph M=C3=BCllner [Updated to newest version of RISC-V spec] Signed-off-by: Nathan Huckleberry --- bfd/elfxx-riscv.c | 5 +++++ gas/testsuite/gas/riscv/zvksed.d | 12 ++++++++++++ gas/testsuite/gas/riscv/zvksed.s | 4 ++++ include/opcode/riscv-opc.h | 11 +++++++++++ include/opcode/riscv.h | 1 + opcodes/riscv-opc.c | 5 +++++ 6 files changed, 38 insertions(+) create mode 100644 gas/testsuite/gas/riscv/zvksed.d create mode 100644 gas/testsuite/gas/riscv/zvksed.s diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c index adcc606fe7e..0ec2552bfb9 100644 --- a/bfd/elfxx-riscv.c +++ b/bfd/elfxx-riscv.c @@ -1265,6 +1265,7 @@ static struct riscv_supported_ext riscv_supported_std= _z_ext[] =3D {"zvkned", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"zvknha", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"zvknhb", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"zvksed", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"zvl32b", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"zvl64b", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"zvl128b", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, @@ -2432,6 +2433,8 @@ riscv_multi_subset_supports (riscv_parse_subset_t *rp= s, case INSN_CLASS_ZVKNHA_OR_ZVKNHB: return (riscv_subset_supports (rps, "zvknha") || riscv_subset_supports (rps, "zvknhb")); + case INSN_CLASS_ZVKSED: + return riscv_subset_supports (rps, "zvksed"); case INSN_CLASS_SVINVAL: return riscv_subset_supports (rps, "svinval"); case INSN_CLASS_H: @@ -2604,6 +2607,8 @@ riscv_multi_subset_supports_ext (riscv_parse_subset_t= *rps, return _("zvknha"); case INSN_CLASS_ZVKNHB: return _("zvknhb"); + case INSN_CLASS_ZVKSED: + return _("zvksed"); case INSN_CLASS_SVINVAL: return "svinval"; case INSN_CLASS_H: diff --git a/gas/testsuite/gas/riscv/zvksed.d b/gas/testsuite/gas/riscv/zvk= sed.d new file mode 100644 index 00000000000..48b4aafdbb1 --- /dev/null +++ b/gas/testsuite/gas/riscv/zvksed.d @@ -0,0 +1,12 @@ +#as: -march=3Drv64gc_zvksed +#objdump: -dr + +.*:[ ]+file format .* + + +Disassembly of section .text: +0+000 <.text>: +[ ]+[0-9a-f]+:[ ]+86802277[ ]+vsm4k.vi[ ]+v4,v8,0 +[ ]+[0-9a-f]+:[ ]+8683a277[ ]+vsm4k.vi[ ]+v4,v8,7 +[ ]+[0-9a-f]+:[ ]+a2882277[ ]+vsm4r.vv[ ]+v4,v8 +[ ]+[0-9a-f]+:[ ]+a6882277[ ]+vsm4r.vs[ ]+v4,v8 diff --git a/gas/testsuite/gas/riscv/zvksed.s b/gas/testsuite/gas/riscv/zvk= sed.s new file mode 100644 index 00000000000..754b4646adf --- /dev/null +++ b/gas/testsuite/gas/riscv/zvksed.s @@ -0,0 +1,4 @@ + vsm4k.vi v4, v8, 0 + vsm4k.vi v4, v8, 7 + vsm4r.vv v4, v8 + vsm4r.vs v4, v8 diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h index 5590dc3b014..415930d0e3e 100644 --- a/include/opcode/riscv-opc.h +++ b/include/opcode/riscv-opc.h @@ -2132,6 +2132,13 @@ #define MASK_VSHA2CL_VV 0xfe00707f #define MATCH_VSHA2MS_VV 0xb6002077 #define MASK_VSHA2MS_VV 0xfe00707f +/* Zvksed instructions. */ +#define MATCH_VSM4K_VI 0x86002077 +#define MASK_VSM4K_VI 0xfe00707f +#define MATCH_VSM4R_VS 0xa6082077 +#define MASK_VSM4R_VS 0xfe0ff07f +#define MATCH_VSM4R_VV 0xa2082077 +#define MASK_VSM4R_VV 0xfe0ff07f /* Svinval instruction. */ #define MATCH_SINVAL_VMA 0x16000073 #define MASK_SINVAL_VMA 0xfe007fff @@ -3241,6 +3248,10 @@ DECLARE_INSN(vaesz_vs, MATCH_VAESZ_VS, MASK_VAESZ_VS= ) DECLARE_INSN(vsha2ch_vv, MATCH_VSHA2CH_VV, MASK_VSHA2CH_VV) DECLARE_INSN(vsha2cl_vv, MATCH_VSHA2CL_VV, MASK_VSHA2CL_VV) DECLARE_INSN(vsha2ms_vv, MATCH_VSHA2MS_VV, MASK_VSHA2MS_VV) +/* Zvksed instructions. */ +DECLARE_INSN(vsm4k_vi, MATCH_VSM4K_VI, MASK_VSM4K_VI) +DECLARE_INSN(vsm4r_vs, MATCH_VSM4R_VS, MASK_VSM4R_VS) +DECLARE_INSN(vsm4r_vv, MATCH_VSM4R_VV, MASK_VSM4R_VV) /* Vendor-specific (T-Head) XTheadBa instructions. */ DECLARE_INSN(th_addsl, MATCH_TH_ADDSL, MASK_TH_ADDSL) /* Vendor-specific (T-Head) XTheadBb instructions. */ diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h index 4ceb191ab07..df807fe8f79 100644 --- a/include/opcode/riscv.h +++ b/include/opcode/riscv.h @@ -416,6 +416,7 @@ enum riscv_insn_class INSN_CLASS_ZVKNHA, INSN_CLASS_ZVKNHB, INSN_CLASS_ZVKNHA_OR_ZVKNHB, + INSN_CLASS_ZVKSED, INSN_CLASS_SVINVAL, INSN_CLASS_ZICBOM, INSN_CLASS_ZICBOP, diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c index d7d3f1c1cd2..cb164169f92 100644 --- a/opcodes/riscv-opc.c +++ b/opcodes/riscv-opc.c @@ -1861,6 +1861,11 @@ const struct riscv_opcode riscv_opcodes[] =3D {"vsha2cl.vv", 0, INSN_CLASS_ZVKNHA_OR_ZVKNHB, "Vd,Vt,Vs", MATCH_VSHA2CL_= VV, MASK_VSHA2CL_VV, match_opcode, 0}, {"vsha2ms.vv", 0, INSN_CLASS_ZVKNHA_OR_ZVKNHB, "Vd,Vt,Vs", MATCH_VSHA2MS_= VV, MASK_VSHA2MS_VV, match_opcode, 0}, =20 +/* Zvksed instructions. */ +{"vsm4k.vi", 0, INSN_CLASS_ZVKSED, "Vd,Vt,Vj", MATCH_VSM4K_VI, MASK_VS= M4K_VI, match_opcode, 0}, +{"vsm4r.vv", 0, INSN_CLASS_ZVKSED, "Vd,Vt", MATCH_VSM4R_VV, MASK_VSM4R= _VV, match_opcode, 0}, +{"vsm4r.vs", 0, INSN_CLASS_ZVKSED, "Vd,Vt", MATCH_VSM4R_VS, MASK_VSM4R= _VS, match_opcode, 0}, + /* Supervisor instructions. */ {"csrr", 0, INSN_CLASS_ZICSR, "d,E", MATCH_CSRRS, MASK_CSRRS|MASK_= RS1, match_opcode, INSN_ALIAS }, {"csrw", 0, INSN_CLASS_ZICSR, "E,s", MATCH_CSRRW, MASK_CSRRW|MASK_= RD, match_opcode, INSN_ALIAS }, --=20 2.41.0.255.g8b1d071c50-goog