From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-yw1-x1149.google.com (mail-yw1-x1149.google.com [IPv6:2607:f8b0:4864:20::1149]) by sourceware.org (Postfix) with ESMTPS id 7977A3858017 for ; Thu, 29 Jun 2023 17:18:56 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 7977A3858017 Authentication-Results: sourceware.org; dmarc=pass (p=reject dis=none) header.from=google.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=flex--nhuck.bounces.google.com Received: by mail-yw1-x1149.google.com with SMTP id 00721157ae682-577323ba3d5so7729057b3.0 for ; Thu, 29 Jun 2023 10:18:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20221208; t=1688059136; x=1690651136; h=content-transfer-encoding:cc:to:from:subject:message-id:references :mime-version:in-reply-to:date:from:to:cc:subject:date:message-id :reply-to; bh=KXIjdKjfkQ/yjiNPX40ud1AqNH67L9jA1Bty9nig7jc=; b=jJxrrvcfyZA1KBoNyDlPVr5arsQGfbNkDQ4n0/cF5EeQ8DWMMdTErcOdmWL7kOBpgv OQoBO0xh6GSJOwvO+Q7VDzElUaZep6tl5xwDtstfd6oY5rqOEx4YG8/M+q9AMAqtq4y3 ORj3lQunn7BytmRA3a/wXYgiyuIl9iu/y5/YvK5jVNPeFa1HlcpybFApVrq2IgQ2FM73 b9Sh8W1E1pZvjYhe+CPgDlBCJJbWkovdEoF2+8DwY69pn2xPW4UDgSM/tjZnHIQJbkHL Etp+jaBiMnfUi01xO6ovSnFFPEC03u4ZTmjRNDrBbB++1TVGD3OnqMxPUq+HQlnC+m4Q wYoQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1688059136; x=1690651136; h=content-transfer-encoding:cc:to:from:subject:message-id:references :mime-version:in-reply-to:date:x-gm-message-state:from:to:cc:subject :date:message-id:reply-to; bh=KXIjdKjfkQ/yjiNPX40ud1AqNH67L9jA1Bty9nig7jc=; b=QnklYvVUlcIAeP3e8xKNCS/Y0npgAqLpBRPlfwstM2fTK9dZCKfhIVEWYbrZuzLNU8 +4YoF9fF0R9A6MyPiUvsxzBkFmJExlr7jvH72Uv9KC7XTQQGxE1eJtIF3HyRNP1WjWfU 6GIeIqEnsiTH+Ri3Nup6qBlepaqNYBwPW2ZntASem4HVmlJQKpti0Rt0ofzuBqx9CsNY Yx8Lq93scxXi0+32LBIkocDiPVxBSZTF4QEokA0S5qaVQ2njRxLBwLTZukbwBIXqeO4F 6FUtdevoSCDE0GhSPcAykWb63/8bSM2w30HoDJyIjSqCD942nluDqa0OiyW6es+pSx0j 1kfg== X-Gm-Message-State: ABy/qLaAYf9RBV78MPuy0cq/Z5F1wl21tNCS3S5wG8Auv/mP7wBCNyQB QNZ9UnOLqAWTDZtXquFm14U2yK+te2BpfFrm2cUyX5gNtz/888w6ab5qHEuTaCq2a6MGkcWqbYg 5k0KgOgeM8vHJ47k7jerVGDf9zH0ozThYCQIjulrIBUted3QgwUhiQGu9n8/2 X-Google-Smtp-Source: APBJJlHj0UvuwpZmAViTYQfEid9KtYCWeB/xvXEbQKlnjv6s4yK95W13LE2o+X37HFivdwrNpvgu5Z/aHQ== X-Received: from nhuck.c.googlers.com ([fda3:e722:ac3:cc00:14:4d90:c0a8:39cc]) (user=nhuck job=sendgmr) by 2002:a0d:d5ca:0:b0:573:54d8:e5be with SMTP id x193-20020a0dd5ca000000b0057354d8e5bemr7726ywd.3.1688059135940; Thu, 29 Jun 2023 10:18:55 -0700 (PDT) Date: Thu, 29 Jun 2023 10:18:32 -0700 In-Reply-To: <20230629171839.573187-1-nhuck@google.com> Mime-Version: 1.0 References: <20230629171839.573187-1-nhuck@google.com> X-Mailer: git-send-email 2.41.0.255.g8b1d071c50-goog Message-ID: <20230629171839.573187-8-nhuck@google.com> Subject: [PATCH 07/14] Adds support for the Zvksh ISA extension. From: Nathan Huckleberry To: binutils@sourceware.org Cc: nhuck@pmull.org, "=?UTF-8?q?Christoph=20M=C3=BCllner?=" , Nathan Huckleberry Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Spam-Status: No, score=-20.8 required=5.0 tests=BAYES_00,DKIMWL_WL_MED,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,GIT_PATCH_0,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE,USER_IN_DEF_DKIM_WL autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: From: Christoph M=C3=BCllner Zvksh is part of the vector crypto extensions. This extension adds the following instructions: - vsm3me.vv - vsm3c.vi Signed-off-by: Christoph M=C3=BCllner [Updated to newest version of RISC-V spec] Signed-off-by: Nathan Huckleberry --- bfd/elfxx-riscv.c | 5 +++++ gas/testsuite/gas/riscv/zvksh.d | 11 +++++++++++ gas/testsuite/gas/riscv/zvksh.s | 3 +++ include/opcode/riscv-opc.h | 8 ++++++++ include/opcode/riscv.h | 1 + opcodes/riscv-opc.c | 4 ++++ 6 files changed, 32 insertions(+) create mode 100644 gas/testsuite/gas/riscv/zvksh.d create mode 100644 gas/testsuite/gas/riscv/zvksh.s diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c index 0ec2552bfb9..77ef99d02cf 100644 --- a/bfd/elfxx-riscv.c +++ b/bfd/elfxx-riscv.c @@ -1266,6 +1266,7 @@ static struct riscv_supported_ext riscv_supported_std= _z_ext[] =3D {"zvknha", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"zvknhb", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"zvksed", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"zvksh", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"zvl32b", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"zvl64b", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"zvl128b", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, @@ -2435,6 +2436,8 @@ riscv_multi_subset_supports (riscv_parse_subset_t *rp= s, || riscv_subset_supports (rps, "zvknhb")); case INSN_CLASS_ZVKSED: return riscv_subset_supports (rps, "zvksed"); + case INSN_CLASS_ZVKSH: + return riscv_subset_supports (rps, "zvksh"); case INSN_CLASS_SVINVAL: return riscv_subset_supports (rps, "svinval"); case INSN_CLASS_H: @@ -2609,6 +2612,8 @@ riscv_multi_subset_supports_ext (riscv_parse_subset_t= *rps, return _("zvknhb"); case INSN_CLASS_ZVKSED: return _("zvksed"); + case INSN_CLASS_ZVKSH: + return _("zvksh"); case INSN_CLASS_SVINVAL: return "svinval"; case INSN_CLASS_H: diff --git a/gas/testsuite/gas/riscv/zvksh.d b/gas/testsuite/gas/riscv/zvks= h.d new file mode 100644 index 00000000000..b24d126ed7b --- /dev/null +++ b/gas/testsuite/gas/riscv/zvksh.d @@ -0,0 +1,11 @@ +#as: -march=3Drv64gc_zvksh +#objdump: -dr + +.*:[ ]+file format .* + + +Disassembly of section .text: +0+000 <.text>: +[ ]+[0-9a-f]+:[ ]+ae802277[ ]+vsm3c.vi[ ]+v4,v8,0 +[ ]+[0-9a-f]+:[ ]+ae8fa277[ ]+vsm3c.vi[ ]+v4,v8,31 +[ ]+[0-9a-f]+:[ ]+82862277[ ]+vsm3me.vv[ ]+v4,v8,v12 diff --git a/gas/testsuite/gas/riscv/zvksh.s b/gas/testsuite/gas/riscv/zvks= h.s new file mode 100644 index 00000000000..bde705c5e33 --- /dev/null +++ b/gas/testsuite/gas/riscv/zvksh.s @@ -0,0 +1,3 @@ + vsm3c.vi v4, v8, 0 + vsm3c.vi v4, v8, 31 + vsm3me.vv v4, v8, v12 diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h index 415930d0e3e..142fa0f2660 100644 --- a/include/opcode/riscv-opc.h +++ b/include/opcode/riscv-opc.h @@ -2139,6 +2139,11 @@ #define MASK_VSM4R_VS 0xfe0ff07f #define MATCH_VSM4R_VV 0xa2082077 #define MASK_VSM4R_VV 0xfe0ff07f +/* Zvksh instructions. */ +#define MATCH_VSM3C_VI 0xae002077 +#define MASK_VSM3C_VI 0xfe00707f +#define MATCH_VSM3ME_VV 0x82002077 +#define MASK_VSM3ME_VV 0xfe00707f /* Svinval instruction. */ #define MATCH_SINVAL_VMA 0x16000073 #define MASK_SINVAL_VMA 0xfe007fff @@ -3252,6 +3257,9 @@ DECLARE_INSN(vsha2ms_vv, MATCH_VSHA2MS_VV, MASK_VSHA2= MS_VV) DECLARE_INSN(vsm4k_vi, MATCH_VSM4K_VI, MASK_VSM4K_VI) DECLARE_INSN(vsm4r_vs, MATCH_VSM4R_VS, MASK_VSM4R_VS) DECLARE_INSN(vsm4r_vv, MATCH_VSM4R_VV, MASK_VSM4R_VV) +/* Zvksh instructions. */ +DECLARE_INSN(vsm3c_vi, MATCH_VSM3C_VI, MASK_VSM3C_VI) +DECLARE_INSN(vsm3me_vv, MATCH_VSM3ME_VV, MASK_VSM3ME_VV) /* Vendor-specific (T-Head) XTheadBa instructions. */ DECLARE_INSN(th_addsl, MATCH_TH_ADDSL, MASK_TH_ADDSL) /* Vendor-specific (T-Head) XTheadBb instructions. */ diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h index df807fe8f79..338f58b4fae 100644 --- a/include/opcode/riscv.h +++ b/include/opcode/riscv.h @@ -417,6 +417,7 @@ enum riscv_insn_class INSN_CLASS_ZVKNHB, INSN_CLASS_ZVKNHA_OR_ZVKNHB, INSN_CLASS_ZVKSED, + INSN_CLASS_ZVKSH, INSN_CLASS_SVINVAL, INSN_CLASS_ZICBOM, INSN_CLASS_ZICBOP, diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c index cb164169f92..e3235393e98 100644 --- a/opcodes/riscv-opc.c +++ b/opcodes/riscv-opc.c @@ -1866,6 +1866,10 @@ const struct riscv_opcode riscv_opcodes[] =3D {"vsm4r.vv", 0, INSN_CLASS_ZVKSED, "Vd,Vt", MATCH_VSM4R_VV, MASK_VSM4R= _VV, match_opcode, 0}, {"vsm4r.vs", 0, INSN_CLASS_ZVKSED, "Vd,Vt", MATCH_VSM4R_VS, MASK_VSM4R= _VS, match_opcode, 0}, =20 +/* Zvksh instructions. */ +{"vsm3c.vi", 0, INSN_CLASS_ZVKSH, "Vd,Vt,Vj", MATCH_VSM3C_VI, MASK_VSM= 3C_VI, match_opcode, 0}, +{"vsm3me.vv", 0, INSN_CLASS_ZVKSH, "Vd,Vt,Vs", MATCH_VSM3ME_VV, MASK_VS= M3ME_VV, match_opcode, 0}, + /* Supervisor instructions. */ {"csrr", 0, INSN_CLASS_ZICSR, "d,E", MATCH_CSRRS, MASK_CSRRS|MASK_= RS1, match_opcode, INSN_ALIAS }, {"csrw", 0, INSN_CLASS_ZICSR, "E,s", MATCH_CSRRW, MASK_CSRRW|MASK_= RD, match_opcode, INSN_ALIAS }, --=20 2.41.0.255.g8b1d071c50-goog