From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mailbox.box.xen0n.name (mail.xen0n.name [115.28.160.31]) by sourceware.org (Postfix) with ESMTPS id 012C53864877 for ; Fri, 30 Jun 2023 12:33:06 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 012C53864877 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=xen0n.name Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=xen0n.name DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=xen0n.name; s=mail; t=1688128384; bh=h2Nx4GmN9LRJ3m1sZ4BomnEV0AM3Hio4972WVtgJmc8=; h=From:To:Cc:Subject:Date:From; b=F/7MAQug2Okee5j01SU90Ce6UPn/+nHHZjLtghgZhVaP8ksoj8/5lkkumXblYuk+i 5LpFiVcxfFFJR10pHAn+hjWoQRgx8iKw8bze9TshX6dpuRO9O7j214JGKVI1S0Kijz vwWMB9Ac6YcoeAK51N+YCKFXhQQF3qgXQbebEHY0= Received: from ld50.lan (unknown [101.88.25.181]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by mailbox.box.xen0n.name (Postfix) with ESMTPSA id C1097600A6; Fri, 30 Jun 2023 20:33:02 +0800 (CST) From: WANG Xuerui To: binutils@sourceware.org Cc: Chenghua Xu , Zhensong Liu , Qinggang Meng , Xi Ruoyao , WANG Xuerui Subject: [PATCH] opcodes/loongarch: Mark address offset operands of LVZ/LBT insns as such Date: Fri, 30 Jun 2023 20:32:59 +0800 Message-Id: <20230630123259.1900571-1-i.swmail@xen0n.name> X-Mailer: git-send-email 2.40.0 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-12.3 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,GIT_PATCH_0,SPF_HELO_NONE,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: From: WANG Xuerui opcodes/ChangeLog: * loongarch-opc.c: Mark the offset operands as "so" for {,x}v{ld,st}, {,x}v{ldrepl,stelm}.[bhwd], and {ld,st}[lr].[wd]. Signed-off-by: WANG Xuerui --- opcodes/loongarch-opc.c | 56 ++++++++++++++++++++--------------------- 1 file changed, 28 insertions(+), 28 deletions(-) diff --git a/opcodes/loongarch-opc.c b/opcodes/loongarch-opc.c index 336be3fb8f8..c83e4810db1 100644 --- a/opcodes/loongarch-opc.c +++ b/opcodes/loongarch-opc.c @@ -906,30 +906,30 @@ static struct loongarch_opcode loongarch_load_store_opcodes[] = { 0x387e8000, 0xffff8000, "stle.h", "r0:5,r5:5,r10:5", 0, 0, 0, 0 }, { 0x387f0000, 0xffff8000, "stle.w", "r0:5,r5:5,r10:5", 0, 0, 0, 0 }, { 0x387f8000, 0xffff8000, "stle.d", "r0:5,r5:5,r10:5", 0, 0, 0, 0 }, - { 0x2c000000, 0xffc00000, "vld", "v0:5,r5:5,s10:12", 0, 0, 0, 0 }, - { 0x2c400000, 0xffc00000, "vst", "v0:5,r5:5,s10:12", 0, 0, 0, 0 }, - { 0x2c800000, 0xffc00000, "xvld", "x0:5,r5:5,s10:12", 0, 0, 0, 0 }, - { 0x2cc00000, 0xffc00000, "xvst", "x0:5,r5:5,s10:12", 0, 0, 0, 0 }, + { 0x2c000000, 0xffc00000, "vld", "v0:5,r5:5,so10:12", 0, 0, 0, 0 }, + { 0x2c400000, 0xffc00000, "vst", "v0:5,r5:5,so10:12", 0, 0, 0, 0 }, + { 0x2c800000, 0xffc00000, "xvld", "x0:5,r5:5,so10:12", 0, 0, 0, 0 }, + { 0x2cc00000, 0xffc00000, "xvst", "x0:5,r5:5,so10:12", 0, 0, 0, 0 }, { 0x38400000, 0xffff8000, "vldx", "v0:5,r5:5,r10:5", 0, 0, 0, 0 }, { 0x38440000, 0xffff8000, "vstx", "v0:5,r5:5,r10:5", 0, 0, 0, 0 }, { 0x38480000, 0xffff8000, "xvldx", "x0:5,r5:5,r10:5", 0, 0, 0, 0 }, { 0x384c0000, 0xffff8000, "xvstx", "x0:5,r5:5,r10:5", 0, 0, 0, 0 }, - { 0x30100000, 0xfff80000, "vldrepl.d", "v0:5,r5:5,s10:9<<3", 0, 0, 0, 0 }, - { 0x30200000, 0xfff00000, "vldrepl.w", "v0:5,r5:5,s10:10<<2", 0, 0, 0, 0 }, - { 0x30400000, 0xffe00000, "vldrepl.h", "v0:5,r5:5,s10:11<<1", 0, 0, 0, 0 }, - { 0x30800000, 0xffc00000, "vldrepl.b", "v0:5,r5:5,s10:12", 0, 0, 0, 0 }, - { 0x31100000, 0xfff80000, "vstelm.d", "v0:5,r5:5,s10:8<<3,u18:1", 0, 0, 0, 0 }, - { 0x31200000, 0xfff00000, "vstelm.w", "v0:5,r5:5,s10:8<<2,u18:2", 0, 0, 0, 0 }, - { 0x31400000, 0xffe00000, "vstelm.h", "v0:5,r5:5,s10:8<<1,u18:3", 0, 0, 0, 0 }, - { 0x31800000, 0xffc00000, "vstelm.b", "v0:5,r5:5,s10:8,u18:4", 0, 0, 0, 0 }, - { 0x32100000, 0xfff80000, "xvldrepl.d", "x0:5,r5:5,s10:9<<3", 0, 0, 0, 0 }, - { 0x32200000, 0xfff00000, "xvldrepl.w", "x0:5,r5:5,s10:10<<2", 0, 0, 0, 0 }, - { 0x32400000, 0xffe00000, "xvldrepl.h", "x0:5,r5:5,s10:11<<1", 0, 0, 0, 0 }, - { 0x32800000, 0xffc00000, "xvldrepl.b", "x0:5,r5:5,s10:12", 0, 0, 0, 0 }, - { 0x33100000, 0xfff00000, "xvstelm.d", "x0:5,r5:5,s10:8<<3,u18:2", 0, 0, 0, 0 }, - { 0x33200000, 0xffe00000, "xvstelm.w", "x0:5,r5:5,s10:8<<2,u18:3", 0, 0, 0, 0 }, - { 0x33400000, 0xffc00000, "xvstelm.h", "x0:5,r5:5,s10:8<<1,u18:4", 0, 0, 0, 0 }, - { 0x33800000, 0xff800000, "xvstelm.b", "x0:5,r5:5,s10:8,u18:5", 0, 0, 0, 0 }, + { 0x30100000, 0xfff80000, "vldrepl.d", "v0:5,r5:5,so10:9<<3", 0, 0, 0, 0 }, + { 0x30200000, 0xfff00000, "vldrepl.w", "v0:5,r5:5,so10:10<<2", 0, 0, 0, 0 }, + { 0x30400000, 0xffe00000, "vldrepl.h", "v0:5,r5:5,so10:11<<1", 0, 0, 0, 0 }, + { 0x30800000, 0xffc00000, "vldrepl.b", "v0:5,r5:5,so10:12", 0, 0, 0, 0 }, + { 0x31100000, 0xfff80000, "vstelm.d", "v0:5,r5:5,so10:8<<3,u18:1", 0, 0, 0, 0 }, + { 0x31200000, 0xfff00000, "vstelm.w", "v0:5,r5:5,so10:8<<2,u18:2", 0, 0, 0, 0 }, + { 0x31400000, 0xffe00000, "vstelm.h", "v0:5,r5:5,so10:8<<1,u18:3", 0, 0, 0, 0 }, + { 0x31800000, 0xffc00000, "vstelm.b", "v0:5,r5:5,so10:8,u18:4", 0, 0, 0, 0 }, + { 0x32100000, 0xfff80000, "xvldrepl.d", "x0:5,r5:5,so10:9<<3", 0, 0, 0, 0 }, + { 0x32200000, 0xfff00000, "xvldrepl.w", "x0:5,r5:5,so10:10<<2", 0, 0, 0, 0 }, + { 0x32400000, 0xffe00000, "xvldrepl.h", "x0:5,r5:5,so10:11<<1", 0, 0, 0, 0 }, + { 0x32800000, 0xffc00000, "xvldrepl.b", "x0:5,r5:5,so10:12", 0, 0, 0, 0 }, + { 0x33100000, 0xfff00000, "xvstelm.d", "x0:5,r5:5,so10:8<<3,u18:2", 0, 0, 0, 0 }, + { 0x33200000, 0xffe00000, "xvstelm.w", "x0:5,r5:5,so10:8<<2,u18:3", 0, 0, 0, 0 }, + { 0x33400000, 0xffc00000, "xvstelm.h", "x0:5,r5:5,so10:8<<1,u18:4", 0, 0, 0, 0 }, + { 0x33800000, 0xff800000, "xvstelm.b", "x0:5,r5:5,so10:8,u18:5", 0, 0, 0, 0 }, { 0, 0, 0, 0, 0, 0, 0, 0 } /* Terminate the list. */ }; @@ -2382,14 +2382,14 @@ static struct loongarch_opcode loongarch_lbt_opcodes[] = {0x0114e400, 0xfffffc00, "fcvt.ud.d", "f0:5,f5:5", 0, 0, 0, 0}, {0x0114e000, 0xfffffc00, "fcvt.ld.d", "f0:5,f5:5", 0, 0, 0, 0}, {0x01150000, 0xffff8000, "fcvt.d.ld", "f0:5,f5:5,f10:5", 0, 0, 0, 0}, - {0x2e800000, 0xffc00000, "ldl.d", "r0:5,r5:5,s10:12", 0, 0, 0, 0}, - {0x2e000000, 0xffc00000, "ldl.w", "r0:5,r5:5,s10:12", 0, 0, 0, 0}, - {0x2e400000, 0xffc00000, "ldr.w", "r0:5,r5:5,s10:12", 0, 0, 0, 0}, - {0x2ec00000, 0xffc00000, "ldr.d", "r0:5,r5:5,s10:12", 0, 0, 0, 0}, - {0x2f000000, 0xffc00000, "stl.w", "r0:5,r5:5,s10:12", 0, 0, 0, 0}, - {0x2f800000, 0xffc00000, "stl.d", "r0:5,r5:5,s10:12", 0, 0, 0, 0}, - {0x2f400000, 0xffc00000, "str.w", "r0:5,r5:5,s10:12", 0, 0, 0, 0}, - {0x2fc00000, 0xffc00000, "str.d", "r0:5,r5:5,s10:12", 0, 0, 0, 0}, + {0x2e800000, 0xffc00000, "ldl.d", "r0:5,r5:5,so10:12", 0, 0, 0, 0}, + {0x2e000000, 0xffc00000, "ldl.w", "r0:5,r5:5,so10:12", 0, 0, 0, 0}, + {0x2e400000, 0xffc00000, "ldr.w", "r0:5,r5:5,so10:12", 0, 0, 0, 0}, + {0x2ec00000, 0xffc00000, "ldr.d", "r0:5,r5:5,so10:12", 0, 0, 0, 0}, + {0x2f000000, 0xffc00000, "stl.w", "r0:5,r5:5,so10:12", 0, 0, 0, 0}, + {0x2f800000, 0xffc00000, "stl.d", "r0:5,r5:5,so10:12", 0, 0, 0, 0}, + {0x2f400000, 0xffc00000, "str.w", "r0:5,r5:5,so10:12", 0, 0, 0, 0}, + {0x2fc00000, 0xffc00000, "str.d", "r0:5,r5:5,so10:12", 0, 0, 0, 0}, {0x003f000c, 0xffff801f, "x86adc.b", "r5:5,r10:5", 0, 0, 0, 0}, {0x003f000d, 0xffff801f, "x86adc.h", "r5:5,r10:5", 0, 0, 0, 0}, {0x003f000e, 0xffff801f, "x86adc.w", "r5:5,r10:5", 0, 0, 0, 0}, -- 2.40.0