From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga07.intel.com (mga07.intel.com [134.134.136.100]) by sourceware.org (Postfix) with ESMTPS id 0ECCE385AF8F for ; Thu, 13 Jul 2023 06:33:11 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 0ECCE385AF8F Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=intel.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1689229992; x=1720765992; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=cwvddikiURm8GPZoqctjA7uv4llgivv9198ZvpiknDI=; b=ImIB/up2wDoArpLY5/7abDcpygXY0toCtYjp7WU+BCulpY8h99tmONKT yY88X4jhambthKkjNfMx2RYsSHKExn96+Ebk5niUvOZCv6jJjsNxDsRA0 gSedRHd/Wc7xXUnNN5T1oXaoAakQ/alALBVarMVdH/Ex5ZQXlTVwzCLaf LAQlWlK4F0X2Oxahpz65XJJ/aoqMPRMg8fyJLv4QgLFe+H/n4m3KzOOUg n8Z+GcXD+Ajd0s0umj4v0KJK98XHXlBRk1X3D/EmzUd6edLH45qSbIEYm ZaV5PIV331g0YBm9hXbIZkI6kTjiUbSTAaohP+eFy9mEBC/N0emlxCNvb Q==; X-IronPort-AV: E=McAfee;i="6600,9927,10769"; a="431253773" X-IronPort-AV: E=Sophos;i="6.01,201,1684825200"; d="scan'208";a="431253773" Received: from fmsmga004.fm.intel.com ([10.253.24.48]) by orsmga105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Jul 2023 23:33:10 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10769"; a="791914382" X-IronPort-AV: E=Sophos;i="6.01,201,1684825200"; d="scan'208";a="791914382" Received: from shvmail03.sh.intel.com ([10.239.245.20]) by fmsmga004.fm.intel.com with ESMTP; 12 Jul 2023 23:33:06 -0700 Received: from shliclel4217.sh.intel.com (shliclel4217.sh.intel.com [10.239.240.127]) by shvmail03.sh.intel.com (Postfix) with ESMTP id 7444D1005698; Thu, 13 Jul 2023 14:33:05 +0800 (CST) From: Haochen Jiang To: binutils@sourceware.org Cc: jbeulich@suse.com, hjl.tools@gmail.com, amodra@gmail.com Subject: [PATCH 2/5] Support Intel SHA512 Date: Thu, 13 Jul 2023 14:33:00 +0800 Message-Id: <20230713063303.205862-3-haochen.jiang@intel.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20230713063303.205862-1-haochen.jiang@intel.com> References: <20230713063303.205862-1-haochen.jiang@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-10.7 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,GIT_PATCH_0,KAM_NUMSUBJECT,SPF_HELO_NONE,SPF_NONE,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: Hi Jan, In SHA512 patch, I have considered to eliminate the ModR/M table pass for vsha512msg1 and vsha512rnds2 since you just introduced OP_R with Uxmm. However, xmm_mode in OP_R requires VEX128 or less. But unfortunately, for both instructions, they are VEX256. Therefore, I still keep the ModR/M table pass in the patch. BRs, Haochen gas/ChangeLog: * NEWS: Support Intel SHA512. * config/tc-i386.c: Add sha512. * doc/c-i386.texi: Document .sha512. * testsuite/gas/i386/i386.exp: Run SHA512 tests. * testsuite/gas/i386/x86-64.exp: Ditto. * testsuite/gas/i386/sha512-intel.d: New test. * testsuite/gas/i386/sha512-inval.l: Ditto. * testsuite/gas/i386/sha512-inval.s: Ditto. * testsuite/gas/i386/sha512.d: Ditto. * testsuite/gas/i386/sha512.s: Ditto. * testsuite/gas/i386/x86-64-sha512-intel.d: Ditto. * testsuite/gas/i386/x86-64-sha512-inval.l: Ditto. * testsuite/gas/i386/x86-64-sha512-inval.s: Ditto. * testsuite/gas/i386/x86-64-sha512.d: Ditto. * testsuite/gas/i386/x86-64-sha512.s: Ditto. opcodes/ChangeLog: * i386-dis.c (Uymm): New. (MOD_VEX_0F38CB_P_3_W_0_L_1): Ditto. (MOD_VEX_0F38CC_P_3_W_0_L_1): Ditto. (PREFIX_VEX_0F38CB): Ditto. (PREFIX_VEX_0F38CC): Ditto. (PREFIX_VEX_0F38CD): Ditto. (VEX_LEN_0F38CB_P_3_W_0): Ditto. (VEX_LEN_0F38CC_P_3_W_0): Ditto. (VEX_LEN_0F38CD_P_3_W_0): Ditto. (VEX_W_0F38CB_P_3): Ditto. (VEX_W_0F38CC_P_3): Ditto. (VEX_W_0F38CD_P_3): Ditto. (mod_table): Add MOD_VEX_0F38CB_P_3_W_0_L_1, MOD_VEX_0F38CC_P_3_W_0_L_1, (prefix_table): Add PREFIX_VEX_0F38CB, PREFIX_VEX_0F38CC, PREFIX_VEX_0F38CD. (vex_len_table): Add VEX_LEN_0F38CB_P_3_W_0, VEX_LEN_0F38CC_P_3_W_0, VEX_LEN_0F38CD_P_3_W_0. (vex_w_table): Add VEX_W_0F38CB_P_3, VEX_W_0F38CC_P_3, VEX_W_0F38CD_P_3. * i386-gen.c (isa_dependencies): Add SHA512. (cpu_flags): Ditto. * i386-init.h: Regenerated. * i386-mnem.h: Ditto. * i386-opc.h (CpuSHA512): New. (i386_cpu_flags): Add cpusha512. * i386-opc.tbl: Add SHA512 instructions. * i386-tbl.h: Regenerated. --- gas/NEWS | 2 + gas/config/tc-i386.c | 1 + gas/doc/c-i386.texi | 3 +- gas/testsuite/gas/i386/i386.exp | 2 + gas/testsuite/gas/i386/sha512-intel.d | 16 + gas/testsuite/gas/i386/sha512.d | 16 + gas/testsuite/gas/i386/sha512.s | 13 + gas/testsuite/gas/i386/x86-64-sha512-intel.d | 16 + gas/testsuite/gas/i386/x86-64-sha512.d | 16 + gas/testsuite/gas/i386/x86-64-sha512.s | 13 + gas/testsuite/gas/i386/x86-64.exp | 2 + opcodes/i386-dis.c | 82 +- opcodes/i386-gen.c | 3 + opcodes/i386-init.h | 648 +- opcodes/i386-mnem.h | 3949 ++++---- opcodes/i386-opc.h | 3 + opcodes/i386-opc.tbl | 8 + opcodes/i386-tbl.h | 8555 +++++++++--------- 18 files changed, 6806 insertions(+), 6542 deletions(-) create mode 100644 gas/testsuite/gas/i386/sha512-intel.d create mode 100644 gas/testsuite/gas/i386/sha512.d create mode 100644 gas/testsuite/gas/i386/sha512.s create mode 100644 gas/testsuite/gas/i386/x86-64-sha512-intel.d create mode 100644 gas/testsuite/gas/i386/x86-64-sha512.d create mode 100644 gas/testsuite/gas/i386/x86-64-sha512.s diff --git a/gas/NEWS b/gas/NEWS index 5e9ed5ab4bc..fe2c055fa7f 100644 --- a/gas/NEWS +++ b/gas/NEWS @@ -1,5 +1,7 @@ -*- text -*- +* Add support for Intel SHA512 instructions. + * Add support for Intel AVX-VNNI-INT16 instructions. Changes in 2.41: diff --git a/gas/config/tc-i386.c b/gas/config/tc-i386.c index 0d3d7560efe..836640d9123 100644 --- a/gas/config/tc-i386.c +++ b/gas/config/tc-i386.c @@ -1152,6 +1152,7 @@ static const arch_entry cpu_arch[] = SUBARCH (fred, FRED, ANY_FRED, false), SUBARCH (lkgs, LKGS, ANY_LKGS, false), SUBARCH (avx_vnni_int16, AVX_VNNI_INT16, ANY_AVX_VNNI_INT16, false), + SUBARCH (sha512, SHA512, ANY_SHA512, false), }; #undef SUBARCH diff --git a/gas/doc/c-i386.texi b/gas/doc/c-i386.texi index 40ba942d9cb..21fb71e54ab 100644 --- a/gas/doc/c-i386.texi +++ b/gas/doc/c-i386.texi @@ -208,6 +208,7 @@ accept various extension mnemonics. For example, @code{fred}, @code{lkgs}, @code{avx_vnni_int16}, +@code{sha512}, @code{amx_int8}, @code{amx_bf16}, @code{amx_fp16}, @@ -1637,7 +1638,7 @@ supported on the CPU specified. The choices for @var{cpu_type} are: @item @samp{.prefetchi} @tab @samp{.avx_ifma} @tab @samp{.avx_vnni_int8} @item @samp{.cmpccxadd} @tab @samp{.wrmsrns} @tab @samp{.msrlist} @item @samp{.avx_ne_convert} @tab @samp{.rao_int} @tab @samp{.fred} @tab @samp{.lkgs} -@item @samp{.avx_vnni_int16} +@item @samp{.avx_vnni_int16} @tab @samp{.sha512} @item @samp{.wbnoinvd} @tab @samp{.pconfig} @tab @samp{.waitpkg} @tab @samp{.cldemote} @item @samp{.shstk} @tab @samp{.gfni} @tab @samp{.vaes} @tab @samp{.vpclmulqdq} @item @samp{.movdiri} @tab @samp{.movdir64b} @tab @samp{.enqcmd} @tab @samp{.tsxldtrk} diff --git a/gas/testsuite/gas/i386/i386.exp b/gas/testsuite/gas/i386/i386.exp index b69c692cd16..487811ad988 100644 --- a/gas/testsuite/gas/i386/i386.exp +++ b/gas/testsuite/gas/i386/i386.exp @@ -498,6 +498,8 @@ if [gas_32_check] then { run_list_test "amx-complex-inval" run_dump_test "avx-vnni-int16" run_dump_test "avx-vnni-int16-intel" + run_dump_test "sha512" + run_dump_test "sha512-intel" run_list_test "sg" run_dump_test "clzero" run_dump_test "invlpgb" diff --git a/gas/testsuite/gas/i386/sha512-intel.d b/gas/testsuite/gas/i386/sha512-intel.d new file mode 100644 index 00000000000..c1cc85b9f26 --- /dev/null +++ b/gas/testsuite/gas/i386/sha512-intel.d @@ -0,0 +1,16 @@ +#as: +#objdump: -dw -Mintel +#name: i386 SHA512 insns (Intel disassembly) +#source: sha512.s + +.*: +file format .* + +Disassembly of section \.text: + +0+ <_start>: +\s*[a-f0-9]+:\s*c4 e2 7f cc f5\s+vsha512msg1 ymm6,xmm5 +\s*[a-f0-9]+:\s*c4 e2 7f cd f5\s+vsha512msg2 ymm6,ymm5 +\s*[a-f0-9]+:\s*c4 e2 57 cb f4\s+vsha512rnds2 ymm6,ymm5,xmm4 +\s*[a-f0-9]+:\s*c4 e2 7f cc f5\s+vsha512msg1 ymm6,xmm5 +\s*[a-f0-9]+:\s*c4 e2 7f cd f5\s+vsha512msg2 ymm6,ymm5 +\s*[a-f0-9]+:\s*c4 e2 57 cb f4\s+vsha512rnds2 ymm6,ymm5,xmm4 diff --git a/gas/testsuite/gas/i386/sha512.d b/gas/testsuite/gas/i386/sha512.d new file mode 100644 index 00000000000..b90019954ea --- /dev/null +++ b/gas/testsuite/gas/i386/sha512.d @@ -0,0 +1,16 @@ +#as: +#objdump: -dw +#name: i386 SHA512 insns +#source: sha512.s + +.*: +file format .* + +Disassembly of section \.text: + +0+ <_start>: +\s*[a-f0-9]+:\s*c4 e2 7f cc f5\s+vsha512msg1 %xmm5,%ymm6 +\s*[a-f0-9]+:\s*c4 e2 7f cd f5\s+vsha512msg2 %ymm5,%ymm6 +\s*[a-f0-9]+:\s*c4 e2 57 cb f4\s+vsha512rnds2 %xmm4,%ymm5,%ymm6 +\s*[a-f0-9]+:\s*c4 e2 7f cc f5\s+vsha512msg1 %xmm5,%ymm6 +\s*[a-f0-9]+:\s*c4 e2 7f cd f5\s+vsha512msg2 %ymm5,%ymm6 +\s*[a-f0-9]+:\s*c4 e2 57 cb f4\s+vsha512rnds2 %xmm4,%ymm5,%ymm6 diff --git a/gas/testsuite/gas/i386/sha512.s b/gas/testsuite/gas/i386/sha512.s new file mode 100644 index 00000000000..e238c272970 --- /dev/null +++ b/gas/testsuite/gas/i386/sha512.s @@ -0,0 +1,13 @@ +# Check 32bit SHA512 instructions + + .allow_index_reg + .text +_start: + vsha512msg1 %xmm5, %ymm6 #SHA512 + vsha512msg2 %ymm5, %ymm6 #SHA512 + vsha512rnds2 %xmm4, %ymm5, %ymm6 #SHA512 + +.intel_syntax noprefix + vsha512msg1 ymm6, xmm5 #SHA512 + vsha512msg2 ymm6, ymm5 #SHA512 + vsha512rnds2 ymm6, ymm5, xmm4 #SHA512 diff --git a/gas/testsuite/gas/i386/x86-64-sha512-intel.d b/gas/testsuite/gas/i386/x86-64-sha512-intel.d new file mode 100644 index 00000000000..e644168e311 --- /dev/null +++ b/gas/testsuite/gas/i386/x86-64-sha512-intel.d @@ -0,0 +1,16 @@ +#as: +#objdump: -dw -Mintel +#name: x86_64 SHA512 insns (Intel disassembly) +#source: x86-64-sha512.s + +.*: +file format .* + +Disassembly of section \.text: + +0+ <_start>: +\s*[a-f0-9]+:\s*c4 e2 7f cc f5\s+vsha512msg1 ymm6,xmm5 +\s*[a-f0-9]+:\s*c4 e2 7f cd f5\s+vsha512msg2 ymm6,ymm5 +\s*[a-f0-9]+:\s*c4 e2 57 cb f4\s+vsha512rnds2 ymm6,ymm5,xmm4 +\s*[a-f0-9]+:\s*c4 e2 7f cc f5\s+vsha512msg1 ymm6,xmm5 +\s*[a-f0-9]+:\s*c4 e2 7f cd f5\s+vsha512msg2 ymm6,ymm5 +\s*[a-f0-9]+:\s*c4 e2 57 cb f4\s+vsha512rnds2 ymm6,ymm5,xmm4 diff --git a/gas/testsuite/gas/i386/x86-64-sha512.d b/gas/testsuite/gas/i386/x86-64-sha512.d new file mode 100644 index 00000000000..fcb8ae61fee --- /dev/null +++ b/gas/testsuite/gas/i386/x86-64-sha512.d @@ -0,0 +1,16 @@ +#as: +#objdump: -dw +#name: x86_64 SHA512 insns +#source: x86-64-sha512.s + +.*: +file format .* + +Disassembly of section \.text: + +0+ <_start>: +\s*[a-f0-9]+:\s*c4 e2 7f cc f5\s+vsha512msg1 %xmm5,%ymm6 +\s*[a-f0-9]+:\s*c4 e2 7f cd f5\s+vsha512msg2 %ymm5,%ymm6 +\s*[a-f0-9]+:\s*c4 e2 57 cb f4\s+vsha512rnds2 %xmm4,%ymm5,%ymm6 +\s*[a-f0-9]+:\s*c4 e2 7f cc f5\s+vsha512msg1 %xmm5,%ymm6 +\s*[a-f0-9]+:\s*c4 e2 7f cd f5\s+vsha512msg2 %ymm5,%ymm6 +\s*[a-f0-9]+:\s*c4 e2 57 cb f4\s+vsha512rnds2 %xmm4,%ymm5,%ymm6 diff --git a/gas/testsuite/gas/i386/x86-64-sha512.s b/gas/testsuite/gas/i386/x86-64-sha512.s new file mode 100644 index 00000000000..5eaadb3bade --- /dev/null +++ b/gas/testsuite/gas/i386/x86-64-sha512.s @@ -0,0 +1,13 @@ +# Check 64bit SHA512 instructions + + .allow_index_reg + .text +_start: + vsha512msg1 %xmm5, %ymm6 #SHA512 + vsha512msg2 %ymm5, %ymm6 #SHA512 + vsha512rnds2 %xmm4, %ymm5, %ymm6 #SHA512 + +.intel_syntax noprefix + vsha512msg1 ymm6, xmm5 #SHA512 + vsha512msg2 ymm6, ymm5 #SHA512 + vsha512rnds2 ymm6, ymm5, xmm4 #SHA512 diff --git a/gas/testsuite/gas/i386/x86-64.exp b/gas/testsuite/gas/i386/x86-64.exp index 0f2903c6185..64d8c3726d4 100644 --- a/gas/testsuite/gas/i386/x86-64.exp +++ b/gas/testsuite/gas/i386/x86-64.exp @@ -440,6 +440,8 @@ run_dump_test "x86-64-lkgs" run_list_test "x86-64-lkgs-inval" run_dump_test "x86-64-avx-vnni-int16" run_dump_test "x86-64-avx-vnni-int16-intel" +run_dump_test "x86-64-sha512" +run_dump_test "x86-64-sha512-intel" run_dump_test "x86-64-clzero" run_dump_test "x86-64-mwaitx-bdver4" run_list_test "x86-64-mwaitx-reg" diff --git a/opcodes/i386-dis.c b/opcodes/i386-dis.c index 9311d832342..430238c3e4e 100644 --- a/opcodes/i386-dis.c +++ b/opcodes/i386-dis.c @@ -530,6 +530,7 @@ fetch_error (const instr_info *ins) #define Nq { OP_R, q_mode } #define Ux { OP_R, x_mode } #define Uxmm { OP_R, xmm_mode } +#define Uymm { OP_R, ymm_mode } #define Rtmm { OP_R, tmm_mode } #define EMCq { OP_EMC, q_mode } #define MXC { OP_MXC, 0 } @@ -895,6 +896,8 @@ enum MOD_0F38DC_PREFIX_1, MOD_VEX_0F3849_X86_64_L_0_W_0, + MOD_VEX_0F38CB_P_3_W_0_L_1, + MOD_VEX_0F38CC_P_3_W_0_L_1, }; enum @@ -1064,6 +1067,9 @@ enum PREFIX_VEX_0F38B1_W_0, PREFIX_VEX_0F38D2_W_0, PREFIX_VEX_0F38D3_W_0, + PREFIX_VEX_0F38CB, + PREFIX_VEX_0F38CC, + PREFIX_VEX_0F38CD, PREFIX_VEX_0F38F5_L_0, PREFIX_VEX_0F38F6_L_0, PREFIX_VEX_0F38F7_L_0, @@ -1306,6 +1312,9 @@ enum VEX_LEN_0F385C_X86_64, VEX_LEN_0F385E_X86_64, VEX_LEN_0F386C_X86_64, + VEX_LEN_0F38CB_P_3_W_0, + VEX_LEN_0F38CC_P_3_W_0, + VEX_LEN_0F38CD_P_3_W_0, VEX_LEN_0F38DB, VEX_LEN_0F38F2, VEX_LEN_0F38F3, @@ -1473,6 +1482,9 @@ enum VEX_W_0F38B1, VEX_W_0F38B4, VEX_W_0F38B5, + VEX_W_0F38CB_P_3, + VEX_W_0F38CC_P_3, + VEX_W_0F38CD_P_3, VEX_W_0F38CF, VEX_W_0F38D2, VEX_W_0F38D3, @@ -3928,6 +3940,30 @@ static const struct dis386 prefix_table[][4] = { { "vpdpwusds", { XM, Vex, EXx }, 0 }, }, + /* PREFIX_VEX_0F38CB */ + { + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { VEX_W_TABLE (VEX_W_0F38CB_P_3) }, + }, + + /* PREFIX_VEX_0F38CC */ + { + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { VEX_W_TABLE (VEX_W_0F38CC_P_3) }, + }, + + /* PREFIX_VEX_0F38CD */ + { + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { VEX_W_TABLE (VEX_W_0F38CD_P_3) }, + }, + /* PREFIX_VEX_0F38F5_L_0 */ { { "bzhiS", { Gdq, Edq, VexGdq }, 0 }, @@ -6380,9 +6416,9 @@ static const struct dis386 vex_table[][256] = { { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, + { PREFIX_TABLE (PREFIX_VEX_0F38CB) }, + { PREFIX_TABLE (PREFIX_VEX_0F38CC) }, + { PREFIX_TABLE (PREFIX_VEX_0F38CD) }, { Bad_Opcode }, { VEX_W_TABLE (VEX_W_0F38CF) }, /* d0 */ @@ -6944,6 +6980,24 @@ static const struct dis386 vex_len_table[][2] = { { VEX_W_TABLE (VEX_W_0F386C_X86_64_L_0) }, }, + /* VEX_LEN_0F38CB_P_3_W_0 */ + { + { Bad_Opcode }, + { MOD_TABLE (MOD_VEX_0F38CB_P_3_W_0_L_1) }, + }, + + /* VEX_LEN_0F38CC_P_3_W_0 */ + { + { Bad_Opcode }, + { MOD_TABLE (MOD_VEX_0F38CC_P_3_W_0_L_1) }, + }, + + /* VEX_LEN_0F38CD_P_3_W_0 */ + { + { Bad_Opcode }, + { "vsha512msg2", { XM, Uymm }, 0 }, + }, + /* VEX_LEN_0F38DB */ { { "vaesimc", { XM, EXx }, PREFIX_DATA }, @@ -7614,6 +7668,18 @@ static const struct dis386 vex_w_table[][2] = { { Bad_Opcode }, { "%XVvpmadd52huq", { XM, Vex, EXx }, PREFIX_DATA }, }, + { + /* VEX_W_0F38CB_P_3 */ + { VEX_LEN_TABLE (VEX_LEN_0F38CB_P_3_W_0) }, + }, + { + /* VEX_W_0F38CC_P_3 */ + { VEX_LEN_TABLE (VEX_LEN_0F38CC_P_3_W_0) }, + }, + { + /* VEX_W_0F38CD_P_3 */ + { VEX_LEN_TABLE (VEX_LEN_0F38CD_P_3_W_0) }, + }, { /* VEX_W_0F38CF */ { "%XEvgf2p8mulb", { XM, Vex, EXx }, PREFIX_DATA }, @@ -8055,6 +8121,16 @@ static const struct dis386 mod_table[][2] = { { PREFIX_TABLE (PREFIX_VEX_0F3849_X86_64_L_0_W_0_M_0) }, { PREFIX_TABLE (PREFIX_VEX_0F3849_X86_64_L_0_W_0_M_1) }, }, + { + /* MOD_VEX_0F38CB_P_3_W_0_L_1 */ + { Bad_Opcode }, + { "vsha512rnds2", { XM, Vex, EXxmm }, 0 }, + }, + { + /* MOD_VEX_0F38CC_P_3_W_0_L_1 */ + { Bad_Opcode }, + { "vsha512msg1", { XM, EXxmm }, 0 }, + }, #include "i386-dis-evex-mod.h" }; diff --git a/opcodes/i386-gen.c b/opcodes/i386-gen.c index 9796977a2aa..8a163533eeb 100644 --- a/opcodes/i386-gen.c +++ b/opcodes/i386-gen.c @@ -168,6 +168,8 @@ static const dependency isa_dependencies[] = "LKGS" }, { "AVX_VNNI_INT16", "AVX2" }, + { "SHA512", + "AVX" }, { "AVX512F", "AVX2" }, { "AVX512CD", @@ -369,6 +371,7 @@ static bitfield cpu_flags[] = BITFIELD (FRED), BITFIELD (LKGS), BITFIELD (AVX_VNNI_INT16), + BITFIELD (SHA512), BITFIELD (MWAITX), BITFIELD (CLZERO), BITFIELD (OSPKE), diff --git a/opcodes/i386-opc.h b/opcodes/i386-opc.h index 4a225202e64..224ca04661e 100644 --- a/opcodes/i386-opc.h +++ b/opcodes/i386-opc.h @@ -235,6 +235,8 @@ enum CpuLKGS, /* Intel AVX VNNI-INT16 Instructions support required. */ CpuAVX_VNNI_INT16, + /* Intel SHA512 Instructions support required. */ + CpuSHA512, /* mwaitx instruction required */ CpuMWAITX, /* Clzero instruction required */ @@ -433,6 +435,7 @@ typedef union i386_cpu_flags unsigned int cpufred:1; unsigned int cpulkgs:1; unsigned int cpuavx_vnni_int16:1; + unsigned int cpusha512:1; unsigned int cpumwaitx:1; unsigned int cpuclzero:1; unsigned int cpuospke:1; diff --git a/opcodes/i386-opc.tbl b/opcodes/i386-opc.tbl index 4903d3b2361..18ea2f1500e 100644 --- a/opcodes/i386-opc.tbl +++ b/opcodes/i386-opc.tbl @@ -3375,3 +3375,11 @@ vpdpwsud, 0xf3d2, AVX_VNNI_INT16, Modrm|Vex|Space0F38|VexVVVV|VexW0|CheckOperand vpdpwsuds, 0xf3d3, AVX_VNNI_INT16, Modrm|Vex|Space0F38|VexVVVV|VexW0|CheckOperandSize|NoSuf, { RegXMM|RegYMM|Unspecified|BaseIndex, RegXMM|RegYMM, RegXMM|RegYMM } // AVX_VNNI_INT16 instructions end. + +// SHA512 instructions. + +vsha512rnds2, 0xf2cb, SHA512, Vex256|Space0F38|Modrm|VexVVVV|VexW0|NoSuf, { RegXMM, RegYMM, RegYMM } +vsha512msg1, 0xf2cc, SHA512, Vex256|Space0F38|Modrm|VexW0|NoSuf, { RegXMM, RegYMM } +vsha512msg2, 0xf2cd, SHA512, Vex256|Space0F38|Modrm|VexW0|NoSuf, { RegYMM, RegYMM } + +// SHA512 instructions end. -- 2.31.1