From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga07.intel.com (mga07.intel.com [134.134.136.100]) by sourceware.org (Postfix) with ESMTPS id 17C4C3858421 for ; Thu, 13 Jul 2023 06:33:12 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 17C4C3858421 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=intel.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1689229993; x=1720765993; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=epjqJpAx/xSpWnpUPnfKr+D1QRq1ZuXGableIrXKK9w=; b=h8mT79cuAYmtK18dibVhEsXk3qr+D7uKL8jETjtRC2wdi8F3lfFOyeXZ yBJo0uewJRhepUbyTfic49xdRgv8ZYPUlluFiByMFRaVzDUKQ2kKn57Yw 0Ka5PNrOTJ0Z/X6SxrIGjqHpWA2Kt0hAEC8YebXWeIPREE6aCQBmXHDTr +LotBVNRspSSvqIEPL3JwFgaA+BVLbka8nwot0Xc5BYzfMs2LIJC1/3rW GtYEESoOpVnLot2jSmcWdNLfGoApNYxRmFcyxZnTPWuhaLPO2njYUREvA 8Bcjc1ADcuQVSKXjXdVf6Wp4c0+K/PSBFDMqPRtkzIuLq9DsZ+ZmIaCO5 Q==; X-IronPort-AV: E=McAfee;i="6600,9927,10769"; a="431253779" X-IronPort-AV: E=Sophos;i="6.01,201,1684825200"; d="scan'208";a="431253779" Received: from fmsmga004.fm.intel.com ([10.253.24.48]) by orsmga105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Jul 2023 23:33:10 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10769"; a="791914406" X-IronPort-AV: E=Sophos;i="6.01,201,1684825200"; d="scan'208";a="791914406" Received: from shvmail03.sh.intel.com ([10.239.245.20]) by fmsmga004.fm.intel.com with ESMTP; 12 Jul 2023 23:33:08 -0700 Received: from shliclel4217.sh.intel.com (shliclel4217.sh.intel.com [10.239.240.127]) by shvmail03.sh.intel.com (Postfix) with ESMTP id 811B310079B6; Thu, 13 Jul 2023 14:33:05 +0800 (CST) From: Haochen Jiang To: binutils@sourceware.org Cc: jbeulich@suse.com, hjl.tools@gmail.com, amodra@gmail.com, "Hu, Lin1" Subject: [PATCH 5/5] Support Intel PBNDKB Date: Thu, 13 Jul 2023 14:33:03 +0800 Message-Id: <20230713063303.205862-6-haochen.jiang@intel.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20230713063303.205862-1-haochen.jiang@intel.com> References: <20230713063303.205862-1-haochen.jiang@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-10.9 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,GIT_PATCH_0,SPF_HELO_NONE,SPF_NONE,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: From: "Hu, Lin1" gas/ChangeLog: * NEWS: Support Intel PBNDKB. * config/tc-i386.c: Add pbndkb. * doc/c-i386.texi: Document .pbndkb. * testsuite/gas/i386/i386.exp: Add PBNDKB tests. * testsuite/gas/i386/x86-64.exp: Ditto. * testsuite/gas/i386/pbndkb-inval.l: New test. * testsuite/gas/i386/pbndkb-inval.s: Ditto. * testsuite/gas/i386/x86-64-pbndkb-intel.d: Ditto. * testsuite/gas/i386/x86-64-pbndkb.d: Ditto. * testsuite/gas/i386/x86-64-pbndkb.s: Ditto. opcodes/ChangeLog: * i386-dis.c (X86_64_0F01_REG_0_MOD_3_RM_7): New. (X86_64_0F01_REG_0_MOD_3_RM_7_P_0): Ditto. (prefix_table): Add PREFIX_0F01_REG_0_MOD_3_RM_7. (x86_64_table): Add X86_64_0F01_REG_0_MOD_3_RM_7_P_0. (rm_table): New entry for pbndkb. * i386-gen.c (cpu_flag): Add PBNDKB. * i386-init.h: Regenerated. * i386-mnem.h: Ditto. * i386-opc.h (CpuPBNDKB): New. (i386_cpu_flags): Add cpupbndkb. * i386-opc.tbl: Add PBNDKB instructions. * i386-tbl.h: Regenerated. --- gas/NEWS | 2 + gas/config/tc-i386.c | 1 + gas/doc/c-i386.texi | 2 + gas/testsuite/gas/i386/i386.exp | 1 + gas/testsuite/gas/i386/pbndkb-inval.l | 2 + gas/testsuite/gas/i386/pbndkb-inval.s | 6 + gas/testsuite/gas/i386/x86-64-pbndkb-intel.d | 12 + gas/testsuite/gas/i386/x86-64-pbndkb.d | 12 + gas/testsuite/gas/i386/x86-64-pbndkb.s | 9 + gas/testsuite/gas/i386/x86-64.exp | 2 + opcodes/i386-dis.c | 14 + opcodes/i386-gen.c | 1 + opcodes/i386-init.h | 652 +- opcodes/i386-mnem.h | 3673 ++++---- opcodes/i386-opc.h | 3 + opcodes/i386-opc.tbl | 6 + opcodes/i386-tbl.h | 7949 +++++++++--------- 17 files changed, 6223 insertions(+), 6124 deletions(-) create mode 100644 gas/testsuite/gas/i386/pbndkb-inval.l create mode 100644 gas/testsuite/gas/i386/pbndkb-inval.s create mode 100644 gas/testsuite/gas/i386/x86-64-pbndkb-intel.d create mode 100644 gas/testsuite/gas/i386/x86-64-pbndkb.d create mode 100644 gas/testsuite/gas/i386/x86-64-pbndkb.s diff --git a/gas/NEWS b/gas/NEWS index 26e75bde391..1ed043511eb 100644 --- a/gas/NEWS +++ b/gas/NEWS @@ -1,5 +1,7 @@ -*- text -*- +* Add support for Intel PBNDKB instructions. + * Add support for Intel SM4 instructions. * Add support for Intel SM3 instructions. diff --git a/gas/config/tc-i386.c b/gas/config/tc-i386.c index 686dd4c70f4..e35e2660ed5 100644 --- a/gas/config/tc-i386.c +++ b/gas/config/tc-i386.c @@ -1155,6 +1155,7 @@ static const arch_entry cpu_arch[] = SUBARCH (sha512, SHA512, ANY_SHA512, false), SUBARCH (sm3, SM3, ANY_SM3, false), SUBARCH (sm4, SM4, ANY_SM4, false), + SUBARCH (pbndkb, PBNDKB, PBNDKB, false), }; #undef SUBARCH diff --git a/gas/doc/c-i386.texi b/gas/doc/c-i386.texi index 54b0d7d738c..dd06282a5a3 100644 --- a/gas/doc/c-i386.texi +++ b/gas/doc/c-i386.texi @@ -211,6 +211,7 @@ accept various extension mnemonics. For example, @code{sha512}, @code{sm3}, @code{sm4}, +@code{pbndkb}, @code{amx_int8}, @code{amx_bf16}, @code{amx_fp16}, @@ -1641,6 +1642,7 @@ supported on the CPU specified. The choices for @var{cpu_type} are: @item @samp{.cmpccxadd} @tab @samp{.wrmsrns} @tab @samp{.msrlist} @item @samp{.avx_ne_convert} @tab @samp{.rao_int} @tab @samp{.fred} @tab @samp{.lkgs} @item @samp{.avx_vnni_int16} @tab @samp{.sha512} @tab @samp{.sm3} @tab @samp{.sm4} +@item @samp{.pbndkb} @item @samp{.wbnoinvd} @tab @samp{.pconfig} @tab @samp{.waitpkg} @tab @samp{.cldemote} @item @samp{.shstk} @tab @samp{.gfni} @tab @samp{.vaes} @tab @samp{.vpclmulqdq} @item @samp{.movdiri} @tab @samp{.movdir64b} @tab @samp{.enqcmd} @tab @samp{.tsxldtrk} diff --git a/gas/testsuite/gas/i386/i386.exp b/gas/testsuite/gas/i386/i386.exp index 5e575660d7c..90f6e20bf5a 100644 --- a/gas/testsuite/gas/i386/i386.exp +++ b/gas/testsuite/gas/i386/i386.exp @@ -504,6 +504,7 @@ if [gas_32_check] then { run_dump_test "sm3-intel" run_dump_test "sm4" run_dump_test "sm4-intel" + run_list_test "pbndkb-inval" run_list_test "sg" run_dump_test "clzero" run_dump_test "invlpgb" diff --git a/gas/testsuite/gas/i386/pbndkb-inval.l b/gas/testsuite/gas/i386/pbndkb-inval.l new file mode 100644 index 00000000000..673bfff67e7 --- /dev/null +++ b/gas/testsuite/gas/i386/pbndkb-inval.l @@ -0,0 +1,2 @@ +.* Assembler messages: +.*:6: Error: `pbndkb' is only supported in 64-bit mode diff --git a/gas/testsuite/gas/i386/pbndkb-inval.s b/gas/testsuite/gas/i386/pbndkb-inval.s new file mode 100644 index 00000000000..ac8aa00f8d1 --- /dev/null +++ b/gas/testsuite/gas/i386/pbndkb-inval.s @@ -0,0 +1,6 @@ +# Check Illegal PBNDKB instructions + + .allow_index_reg + .text +_start: + pbndkb #PBNDKB diff --git a/gas/testsuite/gas/i386/x86-64-pbndkb-intel.d b/gas/testsuite/gas/i386/x86-64-pbndkb-intel.d new file mode 100644 index 00000000000..0ac10b2d1ba --- /dev/null +++ b/gas/testsuite/gas/i386/x86-64-pbndkb-intel.d @@ -0,0 +1,12 @@ +#as: +#objdump: -dw -Mintel +#name: x86_64 PBNDKB insns (Intel disassembly) +#source: x86-64-pbndkb.s + +.*: +file format .* + +Disassembly of section \.text: + +0+ <_start>: +\s*[a-f0-9]+:\s*0f 01 c7\s+pbndkb +\s*[a-f0-9]+:\s*0f 01 c7\s+pbndkb diff --git a/gas/testsuite/gas/i386/x86-64-pbndkb.d b/gas/testsuite/gas/i386/x86-64-pbndkb.d new file mode 100644 index 00000000000..cff4f509194 --- /dev/null +++ b/gas/testsuite/gas/i386/x86-64-pbndkb.d @@ -0,0 +1,12 @@ +#as: +#objdump: -dw +#name: x86_64 PBNDKB insns +#source: x86-64-pbndkb.s + +.*: +file format .* + +Disassembly of section \.text: + +0+ <_start>: +\s*[a-f0-9]+:\s*0f 01 c7\s+pbndkb +\s*[a-f0-9]+:\s*0f 01 c7\s+pbndkb diff --git a/gas/testsuite/gas/i386/x86-64-pbndkb.s b/gas/testsuite/gas/i386/x86-64-pbndkb.s new file mode 100644 index 00000000000..defcce9cb08 --- /dev/null +++ b/gas/testsuite/gas/i386/x86-64-pbndkb.s @@ -0,0 +1,9 @@ +# Check 64bit PBNDKB instructions + + .allow_index_reg + .text +_start: + pbndkb #PBNDKB + +.intel_syntax noprefix + pbndkb #PBNDKB diff --git a/gas/testsuite/gas/i386/x86-64.exp b/gas/testsuite/gas/i386/x86-64.exp index 36bde0ac372..5e329147ffd 100644 --- a/gas/testsuite/gas/i386/x86-64.exp +++ b/gas/testsuite/gas/i386/x86-64.exp @@ -446,6 +446,8 @@ run_dump_test "x86-64-sm3" run_dump_test "x86-64-sm3-intel" run_dump_test "x86-64-sm4" run_dump_test "x86-64-sm4-intel" +run_dump_test "x86-64-pbndkb" +run_dump_test "x86-64-pbndkb-intel" run_dump_test "x86-64-clzero" run_dump_test "x86-64-mwaitx-bdver4" run_list_test "x86-64-mwaitx-reg" diff --git a/opcodes/i386-dis.c b/opcodes/i386-dis.c index e21ad7ae005..c28522d4bcc 100644 --- a/opcodes/i386-dis.c +++ b/opcodes/i386-dis.c @@ -924,6 +924,7 @@ enum PREFIX_90 = 0, PREFIX_0F00_REG_6_X86_64, PREFIX_0F01_REG_0_MOD_3_RM_6, + PREFIX_0F01_REG_0_MOD_3_RM_7, PREFIX_0F01_REG_1_RM_2, PREFIX_0F01_REG_1_RM_4, PREFIX_0F01_REG_1_RM_5, @@ -1198,6 +1199,7 @@ enum X86_64_0F01_REG_0, X86_64_0F01_REG_0_MOD_3_RM_6_P_1, X86_64_0F01_REG_0_MOD_3_RM_6_P_3, + X86_64_0F01_REG_0_MOD_3_RM_7_P_0, X86_64_0F01_REG_1, X86_64_0F01_REG_1_RM_2_PREFIX_1, X86_64_0F01_REG_1_RM_2_PREFIX_3, @@ -2910,6 +2912,11 @@ static const struct dis386 prefix_table[][4] = { { X86_64_TABLE (X86_64_0F01_REG_0_MOD_3_RM_6_P_3) }, }, + /* PREFIX_0F01_REG_0_MOD_3_RM_7 */ + { + { X86_64_TABLE (X86_64_0F01_REG_0_MOD_3_RM_7_P_0) }, + }, + /* PREFIX_0F01_REG_1_RM_2 */ { { "clac", { Skip_MODRM }, 0 }, @@ -4194,6 +4201,12 @@ static const struct dis386 x86_64_table[][2] = { { "rdmsrlist", { Skip_MODRM }, 0 }, }, + /* X86_64_0F01_REG_0_MOD_3_RM_7_P_0 */ + { + { Bad_Opcode }, + { "pbndkb", { Skip_MODRM }, 0 }, + }, + /* X86_64_0F01_REG_1 */ { { "sidt{Q|Q}", { M }, 0 }, @@ -8190,6 +8203,7 @@ static const struct dis386 rm_table[][8] = { { "vmxoff", { Skip_MODRM }, 0 }, { "pconfig", { Skip_MODRM }, 0 }, { PREFIX_TABLE (PREFIX_0F01_REG_0_MOD_3_RM_6) }, + { PREFIX_TABLE (PREFIX_0F01_REG_0_MOD_3_RM_7) }, }, { /* RM_0F01_REG_1 */ diff --git a/opcodes/i386-gen.c b/opcodes/i386-gen.c index 24a9943da47..17f17d38d35 100644 --- a/opcodes/i386-gen.c +++ b/opcodes/i386-gen.c @@ -378,6 +378,7 @@ static bitfield cpu_flags[] = BITFIELD (SHA512), BITFIELD (SM3), BITFIELD (SM4), + BITFIELD (PBNDKB), BITFIELD (MWAITX), BITFIELD (CLZERO), BITFIELD (OSPKE), diff --git a/opcodes/i386-opc.h b/opcodes/i386-opc.h index fcbdb4c5f8d..62067dde5a6 100644 --- a/opcodes/i386-opc.h +++ b/opcodes/i386-opc.h @@ -241,6 +241,8 @@ enum CpuSM3, /* Intel SM4 Instructions support required. */ CpuSM4, + /* Intel PBNDKB Instructions support required. */ + CpuPBNDKB, /* mwaitx instruction required */ CpuMWAITX, /* Clzero instruction required */ @@ -442,6 +444,7 @@ typedef union i386_cpu_flags unsigned int cpusha512:1; unsigned int cpusm3:1; unsigned int cpusm4:1; + unsigned int cpupbndkb:1; unsigned int cpumwaitx:1; unsigned int cpuclzero:1; unsigned int cpuospke:1; diff --git a/opcodes/i386-opc.tbl b/opcodes/i386-opc.tbl index eca60b467f2..6bd0f505118 100644 --- a/opcodes/i386-opc.tbl +++ b/opcodes/i386-opc.tbl @@ -3397,3 +3397,9 @@ vsm4key4, 0xf3da, SM4, Modrm|Space0F38|Vex|VexVVVV|VexW0|CheckOperandSize|NoSuf, vsm4rnds4, 0xf2da, SM4, Modrm|Space0F38|Vex|VexVVVV|VexW0|CheckOperandSize|NoSuf, { RegXMM|RegYMM|Unspecified|BaseIndex, RegXMM|RegYMM, RegXMM|RegYMM } // SM4 instructions end. + +// PBNDKB instruction. + +pbndkb, 0x0f01c7, PBNDKB|x64, NoSuf, {} + +// PBNDKB instruction end. -- 2.31.1