From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from cstnet.cn (smtp21.cstnet.cn [159.226.251.21]) by sourceware.org (Postfix) with ESMTPS id 994A73858C41 for ; Mon, 24 Jul 2023 07:50:01 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 994A73858C41 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=iscas.ac.cn Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=iscas.ac.cn Received: from localhost.localdomain (unknown [47.113.87.88]) by APP-01 (Coremail) with SMTP id qwCowAB3fRn+LL5k8M9iDQ--.25321S2; Mon, 24 Jul 2023 15:49:19 +0800 (CST) From: Jiawei To: binutils@sourceware.org Cc: nelson@rivosinc.com, kito.cheng@sifive.com, palmer@dabbelt.com, jbeulich@suse.com, christoph.muellner@vrull.eu, wuwei2016@iscas.ac.cn, shihua@iscas.ac.cn, shiyulong@iscas.ac.cn, chenyixuan@iscas.ac.cn, Jiawei Subject: [PATCH] RISC-V: Add 'Zacas' extension instructions Date: Mon, 24 Jul 2023 15:49:04 +0800 Message-Id: <20230724074904.637833-1-jiawei@iscas.ac.cn> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-CM-TRANSID:qwCowAB3fRn+LL5k8M9iDQ--.25321S2 X-Coremail-Antispam: 1UD129KBjvJXoW3XryUKF18Gry3uFWDJw1rtFb_yoWfJr15pF s5WF4avF95tF97Jr93uF4jka1fXr9akF17Cw4Igw1av3yj9r4UJFnYyw1DJr18JFs09rnx ua4rZry5uFyUCF7anT9S1TB71UUUUUUqnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnRJUUUvm14x267AKxVW8JVW5JwAFc2x0x2IEx4CE42xK8VAvwI8IcIk0 rVWrJVCq3wAFIxvE14AKwVWUJVWUGwA2ocxC64kIII0Yj41l84x0c7CEw4AK67xGY2AK02 1l84ACjcxK6xIIjxv20xvE14v26F1j6w1UM28EF7xvwVC0I7IYx2IY6xkF7I0E14v26r4U JVWxJr1l84ACjcxK6I8E87Iv67AKxVW0oVCq3wA2z4x0Y4vEx4A2jsIEc7CjxVAFwI0_Gc CE3s1le2I262IYc4CY6c8Ij28IcVAaY2xG8wAqx4xG64xvF2IEw4CE5I8CrVC2j2WlYx0E 2Ix0cI8IcVAFwI0_Jr0_Jr4lYx0Ex4A2jsIE14v26r1j6r4UMcvjeVCFs4IE7xkEbVWUJV W8JwACjcxG0xvY0x0EwIxGrwACjI8F5VA0II8E6IAqYI8I648v4I1lFIxGxcIEc7CjxVA2 Y2ka0xkIwI1lc2xSY4AK67A8MxAIw28IcxkI7VAKI48JMxC20s026xCaFVCjc4AY6r1j6r 4UMI8I3I0E5I8CrVAFwI0_Jr0_Jr4lx2IqxVCjr7xvwVAFwI0_JrI_JrWlx4CE17CEb7AF 67AKxVWUtVW8ZwCIc40Y0x0EwIxGrwCI42IY6xIIjxv20xvE14v26r1j6r1xMIIF0xvE2I x0cI8IcVCY1x0267AKxVW8JVWxJwCI42IY6xAIw20EY4v20xvaj40_Jr0_JF4lIxAIcVC2 z280aVAFwI0_Jr0_Gr1lIxAIcVC2z280aVCY1x0267AKxVW8JVW8JrUvcSsGvfC2KfnxnU UI43ZEXa7VUU7GYJUUUUU== X-Originating-IP: [47.113.87.88] X-CM-SenderInfo: 5mld4v3l6l2u1dvotugofq/1tbiCggCAGS+Hao3CgAAsQ X-Spam-Status: No, score=-11.8 required=5.0 tests=BAYES_00,GIT_PATCH_0,KAM_DMARC_STATUS,RCVD_IN_DNSWL_LOW,SPF_HELO_PASS,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: This patch supports RISC-V Atomic compare-and-swap(CAS) extension instructions(Zacas)[1]. It contains word/doubleword/quadword CAS instructions amocas.w/d/q.And optionally provides release consistency semantics, using the 'aq' and 'rl' bits, to help implement multiprocessor synchronization. [1] https://github.com/riscv/riscv-zacas bfd/ChangeLog: * elfxx-riscv.c (riscv_multi_subset_supports): New depends. (riscv_multi_subset_supports_ext): New extension. gas/ChangeLog: * testsuite/gas/riscv/zacas.d: New test. * testsuite/gas/riscv/zacas.s: New test. include/ChangeLog: * opcode/riscv-opc.h (MATCH_AMOCAS_W): New match opcode. (MASK_AMOCAS_W): New mask opcode. (MATCH_AMOCAS_D): New match opcode. (MASK_AMOCAS_D): New mask opcode. (MATCH_AMOCAS_Q): New match opcode. (MASK_AMOCAS_Q): New mask opcode. * opcode/riscv.h (enum riscv_insn_class): New extension class. opcodes/ChangeLog: * riscv-opc.c: New instructions. --- bfd/elfxx-riscv.c | 6 ++++++ gas/testsuite/gas/riscv/zacas.d | 20 ++++++++++++++++++++ gas/testsuite/gas/riscv/zacas.s | 13 +++++++++++++ include/opcode/riscv-opc.h | 7 +++++++ include/opcode/riscv.h | 1 + opcodes/riscv-opc.c | 14 ++++++++++++++ 6 files changed, 61 insertions(+) create mode 100644 gas/testsuite/gas/riscv/zacas.d create mode 100644 gas/testsuite/gas/riscv/zacas.s diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c index ee96608358e..46b91087fc6 100644 --- a/bfd/elfxx-riscv.c +++ b/bfd/elfxx-riscv.c @@ -1171,6 +1171,7 @@ static struct riscv_implicit_subset riscv_implicit_subsets[] = {"zvksg", "zvkg", check_implicit_always}, {"zvksc", "zvks", check_implicit_always}, {"zvksc", "zvbc", check_implicit_always}, + {"zacas", "a", check_implicit_always}, {"zcf", "zca", check_implicit_always}, {"zcd", "zca", check_implicit_always}, {"zcb", "zca", check_implicit_always}, @@ -1248,6 +1249,7 @@ static struct riscv_supported_ext riscv_supported_std_z_ext[] = {"zifencei", ISA_SPEC_CLASS_20190608, 2, 0, 0 }, {"zihintpause", ISA_SPEC_CLASS_DRAFT, 2, 0, 0 }, {"zmmul", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"zacas", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"zawrs", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"zfa", ISA_SPEC_CLASS_DRAFT, 0, 1, 0 }, {"zfh", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, @@ -2382,6 +2384,8 @@ riscv_multi_subset_supports (riscv_parse_subset_t *rps, return riscv_subset_supports (rps, "zmmul"); case INSN_CLASS_A: return riscv_subset_supports (rps, "a"); + case INSN_CLASS_ZACAS: + return riscv_subset_supports (rps, "zacas"); case INSN_CLASS_ZAWRS: return riscv_subset_supports (rps, "zawrs"); case INSN_CLASS_F: @@ -2575,6 +2579,8 @@ riscv_multi_subset_supports_ext (riscv_parse_subset_t *rps, return _ ("m' or `zmmul"); case INSN_CLASS_A: return "a"; + case INSN_CLASS_ZACAS: + return "zacas"; case INSN_CLASS_ZAWRS: return "zawrs"; case INSN_CLASS_F: diff --git a/gas/testsuite/gas/riscv/zacas.d b/gas/testsuite/gas/riscv/zacas.d new file mode 100644 index 00000000000..2f65a9bcbe4 --- /dev/null +++ b/gas/testsuite/gas/riscv/zacas.d @@ -0,0 +1,20 @@ +#as: -march=rv64i_zacas +#objdump: -d + +.*:[ ]+file format .* + +Disassembly of section .text: + +0+000 : +[ ]+[0-9a-f]+:[ ]+28e5262f[ ]+amocas.w[ ]+a2,a4,\(a0\) +[ ]+[0-9a-f]+:[ ]+2ce5262f[ ]+amocas.w.aq[ ]+a2,a4,\(a0\) +[ ]+[0-9a-f]+:[ ]+2ae5262f[ ]+amocas.w.rl[ ]+a2,a4,\(a0\) +[ ]+[0-9a-f]+:[ ]+2ee5262f[ ]+amocas.w.aqrl[ ]+a2,a4,\(a0\) +[ ]+[0-9a-f]+:[ ]+28e5372f[ ]+amocas.d[ ]+a4,a4,\(a0\) +[ ]+[0-9a-f]+:[ ]+2ce5372f[ ]+amocas.d.aq[ ]+a4,a4,\(a0\) +[ ]+[0-9a-f]+:[ ]+2ae5372f[ ]+amocas.d.rl[ ]+a4,a4,\(a0\) +[ ]+[0-9a-f]+:[ ]+2ee5372f[ ]+amocas.d.aqrl[ ]+a4,a4,\(a0\) +[ ]+[0-9a-f]+:[ ]+28e5482f[ ]+amocas.q[ ]+a6,a4,\(a0\) +[ ]+[0-9a-f]+:[ ]+2ce5482f[ ]+amocas.q.aq[ ]+a6,a4,\(a0\) +[ ]+[0-9a-f]+:[ ]+2ae5482f[ ]+amocas.q.rl[ ]+a6,a4,\(a0\) +[ ]+[0-9a-f]+:[ ]+2ee5482f[ ]+amocas.q.aqrl[ ]+a6,a4,\(a0\) diff --git a/gas/testsuite/gas/riscv/zacas.s b/gas/testsuite/gas/riscv/zacas.s new file mode 100644 index 00000000000..441284455a2 --- /dev/null +++ b/gas/testsuite/gas/riscv/zacas.s @@ -0,0 +1,13 @@ +target: + amocas.w a2, a4, (a0) + amocas.w.aq a2, a4, (a0) + amocas.w.rl a2, a4, (a0) + amocas.w.aqrl a2, a4, (a0) + amocas.d a4, a4, (a0) + amocas.d.aq a4, a4, (a0) + amocas.d.rl a4, a4, (a0) + amocas.d.aqrl a4, a4, (a0) + amocas.q a6, a4, (a0) + amocas.q.aq a6, a4, (a0) + amocas.q.rl a6, a4, (a0) + amocas.q.aqrl a6, a4, (a0) diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h index 53f5f200508..750e31a337d 100644 --- a/include/opcode/riscv-opc.h +++ b/include/opcode/riscv-opc.h @@ -2298,6 +2298,13 @@ #define MASK_CZERO_EQZ 0xfe00707f #define MATCH_CZERO_NEZ 0xe007033 #define MASK_CZERO_NEZ 0xfe00707f +/* Zacas intructions. */ +#define MATCH_AMOCAS_W 0x2800202f +#define MASK_AMOCAS_W 0xf800707f +#define MATCH_AMOCAS_D 0x2800302f +#define MASK_AMOCAS_D 0xf800707f +#define MATCH_AMOCAS_Q 0x2800402f +#define MASK_AMOCAS_Q 0xf800707f /* Zawrs intructions. */ #define MATCH_WRS_NTO 0x00d00073 #define MASK_WRS_NTO 0xffffffff diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h index 808f3657303..e06f9819d6e 100644 --- a/include/opcode/riscv.h +++ b/include/opcode/riscv.h @@ -394,6 +394,7 @@ enum riscv_insn_class INSN_CLASS_ZIFENCEI, INSN_CLASS_ZIHINTPAUSE, INSN_CLASS_ZMMUL, + INSN_CLASS_ZACAS, INSN_CLASS_ZAWRS, INSN_CLASS_F_INX, INSN_CLASS_D_INX, diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c index 6a854736fec..ef57850d4e6 100644 --- a/opcodes/riscv-opc.c +++ b/opcodes/riscv-opc.c @@ -633,6 +633,20 @@ const struct riscv_opcode riscv_opcodes[] = {"amomin.d.aqrl", 64, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOMIN_D|MASK_AQRL, MASK_AMOMIN_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE }, {"amominu.d.aqrl", 64, INSN_CLASS_A, "d,t,0(s)", MATCH_AMOMINU_D|MASK_AQRL, MASK_AMOMINU_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE }, +/* Atomic compare-and-swap instruction subset. */ +{"amocas.w", 0, INSN_CLASS_ZACAS, "d,t,0(s)", MATCH_AMOCAS_W, MASK_AMOCAS_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE }, +{"amocas.w.aq", 0, INSN_CLASS_ZACAS, "d,t,0(s)", MATCH_AMOCAS_W|MASK_AQ, MASK_AMOCAS_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE }, +{"amocas.w.rl", 0, INSN_CLASS_ZACAS, "d,t,0(s)", MATCH_AMOCAS_W|MASK_RL, MASK_AMOCAS_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE }, +{"amocas.w.aqrl", 0, INSN_CLASS_ZACAS, "d,t,0(s)", MATCH_AMOCAS_W|MASK_AQRL, MASK_AMOCAS_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE }, +{"amocas.d", 0, INSN_CLASS_ZACAS, "d,t,0(s)", MATCH_AMOCAS_D, MASK_AMOCAS_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE }, +{"amocas.d.aq", 0, INSN_CLASS_ZACAS, "d,t,0(s)", MATCH_AMOCAS_D|MASK_AQ, MASK_AMOCAS_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE }, +{"amocas.d.rl", 0, INSN_CLASS_ZACAS, "d,t,0(s)", MATCH_AMOCAS_D|MASK_RL, MASK_AMOCAS_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE }, +{"amocas.d.aqrl", 0, INSN_CLASS_ZACAS, "d,t,0(s)", MATCH_AMOCAS_D|MASK_AQRL, MASK_AMOCAS_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE }, +{"amocas.q", 64, INSN_CLASS_ZACAS, "d,t,0(s)", MATCH_AMOCAS_Q, MASK_AMOCAS_Q|MASK_AQRL, match_opcode, INSN_DREF|INSN_16_BYTE }, +{"amocas.q.aq", 64, INSN_CLASS_ZACAS, "d,t,0(s)", MATCH_AMOCAS_Q|MASK_AQ, MASK_AMOCAS_Q|MASK_AQRL, match_opcode, INSN_DREF|INSN_16_BYTE }, +{"amocas.q.rl", 64, INSN_CLASS_ZACAS, "d,t,0(s)", MATCH_AMOCAS_Q|MASK_RL, MASK_AMOCAS_Q|MASK_AQRL, match_opcode, INSN_DREF|INSN_16_BYTE }, +{"amocas.q.aqrl", 64, INSN_CLASS_ZACAS, "d,t,0(s)", MATCH_AMOCAS_Q|MASK_AQRL, MASK_AMOCAS_Q|MASK_AQRL, match_opcode, INSN_DREF|INSN_16_BYTE }, + /* Multiply/Divide instruction subset. */ {"mul", 0, INSN_CLASS_ZCB_AND_ZMMUL, "Cs,Cw,Ct", MATCH_C_MUL, MASK_C_MUL, match_opcode, INSN_ALIAS }, {"mul", 0, INSN_CLASS_ZMMUL, "d,s,t", MATCH_MUL, MASK_MUL, match_opcode, 0 }, -- 2.25.1