From: "Ying Huang" <ying.huang@oss.cipunited.com>
To: <binutils@sourceware.org>
Cc: <yunqiang.su@oss.cipunited.com>,
"Ying Huang" <huangyin@oss.cipunited.com>
Subject: [PATCH] MIPS: Change all E_MIPS_* to EF_MIPS_*
Date: Fri, 18 Aug 2023 17:50:53 +0800 [thread overview]
Message-ID: <20230818095053.2340246-1-ying.huang@oss.cipunited.com> (raw)
[-- Attachment #1: Type: text/plain, Size: 48943 bytes --]
From: Ying Huang <huangyin@oss.cipunited.com>
The purpose is to keep same with glibc elf.h
---
bfd/elf32-mips.c | 4 +-
bfd/elfxx-mips.c | 224 +++++++++++++++++++++----------------------
binutils/readelf.c | 76 +++++++--------
elfcpp/mips.h | 74 +++++++-------
gas/config.in | 4 +-
gas/config/tc-mips.c | 10 +-
gas/configure | 8 +-
gas/configure.ac | 10 +-
gdb/mips-tdep.c | 16 ++--
gold/mips.cc | 168 ++++++++++++++++----------------
include/elf/mips.h | 74 +++++++-------
sim/mips/interp.c | 4 +-
12 files changed, 336 insertions(+), 336 deletions(-)
diff --git a/bfd/elf32-mips.c b/bfd/elf32-mips.c
index 03be42e845c..460b6064f7f 100644
--- a/bfd/elf32-mips.c
+++ b/bfd/elf32-mips.c
@@ -2135,8 +2135,8 @@ bfd_elf32_bfd_reloc_type_lookup (bfd *abfd, bfd_reloc_code_real_type code)
/* We need to handle BFD_RELOC_CTOR specially.
Select the right relocation (R_MIPS_32 or R_MIPS_64) based on the
size of addresses of the ABI. */
- if ((elf_elfheader (abfd)->e_flags & (E_MIPS_ABI_O64
- | E_MIPS_ABI_EABI64)) != 0)
+ if ((elf_elfheader (abfd)->e_flags & (EF_MIPS_ABI_O64
+ | EF_MIPS_ABI_EABI64)) != 0)
return &elf_mips_ctor64_howto;
else
return &howto_table[(int) R_MIPS_32];
diff --git a/bfd/elfxx-mips.c b/bfd/elfxx-mips.c
index 92dd4c20a7d..4b1ec670dc0 100644
--- a/bfd/elfxx-mips.c
+++ b/bfd/elfxx-mips.c
@@ -787,14 +787,14 @@ static bfd *reldyn_sorting_bfd;
/* True if ABFD is for CPUs with load interlocking that include
non-MIPS1 CPUs and R3900. */
#define LOAD_INTERLOCKS_P(abfd) \
- ( ((elf_elfheader (abfd)->e_flags & EF_MIPS_ARCH) != E_MIPS_ARCH_1) \
- || ((elf_elfheader (abfd)->e_flags & EF_MIPS_MACH) == E_MIPS_MACH_3900))
+ ( ((elf_elfheader (abfd)->e_flags & EF_MIPS_ARCH) != EF_MIPS_ARCH_1) \
+ || ((elf_elfheader (abfd)->e_flags & EF_MIPS_MACH) == EF_MIPS_MACH_3900))
/* True if ABFD is for CPUs that are faster if JAL is converted to BAL.
This should be safe for all architectures. We enable this predicate
for RM9000 for now. */
#define JAL_TO_BAL_P(abfd) \
- ((elf_elfheader (abfd)->e_flags & EF_MIPS_MACH) == E_MIPS_MACH_9000)
+ ((elf_elfheader (abfd)->e_flags & EF_MIPS_MACH) == EF_MIPS_MACH_9000)
/* True if ABFD is for CPUs that are faster if JALR is converted to BAL.
This should be safe for all architectures. We enable this predicate for
@@ -812,7 +812,7 @@ static bfd *reldyn_sorting_bfd;
/* Nonzero if ABFD is using the O32 ABI. */
#define ABI_O32_P(abfd) \
- ((elf_elfheader (abfd)->e_flags & EF_MIPS_ABI) == E_MIPS_ABI_O32)
+ ((elf_elfheader (abfd)->e_flags & EF_MIPS_ABI) == EF_MIPS_ABI_O32)
/* Nonzero if ABFD is using the N32 ABI. */
#define ABI_N32_P(abfd) \
@@ -831,8 +831,8 @@ static bfd *reldyn_sorting_bfd;
/* Nonzero if ABFD is MIPS R6. */
#define MIPSR6_P(abfd) \
- ((elf_elfheader (abfd)->e_flags & EF_MIPS_ARCH) == E_MIPS_ARCH_32R6 \
- || (elf_elfheader (abfd)->e_flags & EF_MIPS_ARCH) == E_MIPS_ARCH_64R6)
+ ((elf_elfheader (abfd)->e_flags & EF_MIPS_ARCH) == EF_MIPS_ARCH_32R6 \
+ || (elf_elfheader (abfd)->e_flags & EF_MIPS_ARCH) == EF_MIPS_ARCH_64R6)
/* The IRIX compatibility level we are striving for. */
#define IRIX_COMPAT(abfd) \
@@ -6994,107 +6994,107 @@ _bfd_elf_mips_mach (flagword flags)
{
switch (flags & EF_MIPS_MACH)
{
- case E_MIPS_MACH_3900:
+ case EF_MIPS_MACH_3900:
return bfd_mach_mips3900;
- case E_MIPS_MACH_4010:
+ case EF_MIPS_MACH_4010:
return bfd_mach_mips4010;
- case E_MIPS_MACH_ALLEGREX:
+ case EF_MIPS_MACH_ALLEGREX:
return bfd_mach_mips_allegrex;
- case E_MIPS_MACH_4100:
+ case EF_MIPS_MACH_4100:
return bfd_mach_mips4100;
- case E_MIPS_MACH_4111:
+ case EF_MIPS_MACH_4111:
return bfd_mach_mips4111;
- case E_MIPS_MACH_4120:
+ case EF_MIPS_MACH_4120:
return bfd_mach_mips4120;
- case E_MIPS_MACH_4650:
+ case EF_MIPS_MACH_4650:
return bfd_mach_mips4650;
- case E_MIPS_MACH_5400:
+ case EF_MIPS_MACH_5400:
return bfd_mach_mips5400;
- case E_MIPS_MACH_5500:
+ case EF_MIPS_MACH_5500:
return bfd_mach_mips5500;
- case E_MIPS_MACH_5900:
+ case EF_MIPS_MACH_5900:
return bfd_mach_mips5900;
- case E_MIPS_MACH_9000:
+ case EF_MIPS_MACH_9000:
return bfd_mach_mips9000;
- case E_MIPS_MACH_SB1:
+ case EF_MIPS_MACH_SB1:
return bfd_mach_mips_sb1;
- case E_MIPS_MACH_LS2E:
+ case EF_MIPS_MACH_LS2E:
return bfd_mach_mips_loongson_2e;
- case E_MIPS_MACH_LS2F:
+ case EF_MIPS_MACH_LS2F:
return bfd_mach_mips_loongson_2f;
- case E_MIPS_MACH_GS464:
+ case EF_MIPS_MACH_GS464:
return bfd_mach_mips_gs464;
- case E_MIPS_MACH_GS464E:
+ case EF_MIPS_MACH_GS464E:
return bfd_mach_mips_gs464e;
- case E_MIPS_MACH_GS264E:
+ case EF_MIPS_MACH_GS264E:
return bfd_mach_mips_gs264e;
- case E_MIPS_MACH_OCTEON3:
+ case EF_MIPS_MACH_OCTEON3:
return bfd_mach_mips_octeon3;
- case E_MIPS_MACH_OCTEON2:
+ case EF_MIPS_MACH_OCTEON2:
return bfd_mach_mips_octeon2;
- case E_MIPS_MACH_OCTEON:
+ case EF_MIPS_MACH_OCTEON:
return bfd_mach_mips_octeon;
- case E_MIPS_MACH_XLR:
+ case EF_MIPS_MACH_XLR:
return bfd_mach_mips_xlr;
- case E_MIPS_MACH_IAMR2:
+ case EF_MIPS_MACH_IAMR2:
return bfd_mach_mips_interaptiv_mr2;
default:
switch (flags & EF_MIPS_ARCH)
{
default:
- case E_MIPS_ARCH_1:
+ case EF_MIPS_ARCH_1:
return bfd_mach_mips3000;
- case E_MIPS_ARCH_2:
+ case EF_MIPS_ARCH_2:
return bfd_mach_mips6000;
- case E_MIPS_ARCH_3:
+ case EF_MIPS_ARCH_3:
return bfd_mach_mips4000;
- case E_MIPS_ARCH_4:
+ case EF_MIPS_ARCH_4:
return bfd_mach_mips8000;
- case E_MIPS_ARCH_5:
+ case EF_MIPS_ARCH_5:
return bfd_mach_mips5;
- case E_MIPS_ARCH_32:
+ case EF_MIPS_ARCH_32:
return bfd_mach_mipsisa32;
- case E_MIPS_ARCH_64:
+ case EF_MIPS_ARCH_64:
return bfd_mach_mipsisa64;
- case E_MIPS_ARCH_32R2:
+ case EF_MIPS_ARCH_32R2:
return bfd_mach_mipsisa32r2;
- case E_MIPS_ARCH_64R2:
+ case EF_MIPS_ARCH_64R2:
return bfd_mach_mipsisa64r2;
- case E_MIPS_ARCH_32R6:
+ case EF_MIPS_ARCH_32R6:
return bfd_mach_mipsisa32r6;
- case E_MIPS_ARCH_64R6:
+ case EF_MIPS_ARCH_64R6:
return bfd_mach_mipsisa64r6;
}
}
@@ -7119,13 +7119,13 @@ elf_mips_abi_name (bfd *abfd)
return "64";
else
return "none";
- case E_MIPS_ABI_O32:
+ case EF_MIPS_ABI_O32:
return "O32";
- case E_MIPS_ABI_O64:
+ case EF_MIPS_ABI_O64:
return "O64";
- case E_MIPS_ABI_EABI32:
+ case EF_MIPS_ABI_EABI32:
return "EABI32";
- case E_MIPS_ABI_EABI64:
+ case EF_MIPS_ABI_EABI64:
return "EABI64";
default:
return "unknown abi";
@@ -7280,7 +7280,7 @@ _bfd_mips_elf_eh_frame_address_size (bfd *abfd, const asection *sec)
{
if (elf_elfheader (abfd)->e_ident[EI_CLASS] == ELFCLASS64)
return 8;
- if ((elf_elfheader (abfd)->e_flags & EF_MIPS_ABI) == E_MIPS_ABI_EABI64)
+ if ((elf_elfheader (abfd)->e_flags & EF_MIPS_ABI) == EF_MIPS_ABI_EABI64)
{
bool long32_p, long64_p;
@@ -12319,68 +12319,68 @@ mips_set_isa_flags (bfd *abfd)
{
default:
if (ABI_N32_P (abfd) || ABI_64_P (abfd))
- val = MIPS_DEFAULT_R6 ? E_MIPS_ARCH_64R6 : E_MIPS_ARCH_3;
+ val = MIPS_DEFAULT_R6 ? EF_MIPS_ARCH_64R6 : EF_MIPS_ARCH_3;
else
- val = MIPS_DEFAULT_R6 ? E_MIPS_ARCH_32R6 : E_MIPS_ARCH_1;
+ val = MIPS_DEFAULT_R6 ? EF_MIPS_ARCH_32R6 : EF_MIPS_ARCH_1;
break;
case bfd_mach_mips3000:
- val = E_MIPS_ARCH_1;
+ val = EF_MIPS_ARCH_1;
break;
case bfd_mach_mips3900:
- val = E_MIPS_ARCH_1 | E_MIPS_MACH_3900;
+ val = EF_MIPS_ARCH_1 | EF_MIPS_MACH_3900;
break;
case bfd_mach_mips6000:
- val = E_MIPS_ARCH_2;
+ val = EF_MIPS_ARCH_2;
break;
case bfd_mach_mips4010:
- val = E_MIPS_ARCH_2 | E_MIPS_MACH_4010;
+ val = EF_MIPS_ARCH_2 | EF_MIPS_MACH_4010;
break;
case bfd_mach_mips_allegrex:
- val = E_MIPS_ARCH_2 | E_MIPS_MACH_ALLEGREX;
+ val = EF_MIPS_ARCH_2 | EF_MIPS_MACH_ALLEGREX;
break;
case bfd_mach_mips4000:
case bfd_mach_mips4300:
case bfd_mach_mips4400:
case bfd_mach_mips4600:
- val = E_MIPS_ARCH_3;
+ val = EF_MIPS_ARCH_3;
break;
case bfd_mach_mips4100:
- val = E_MIPS_ARCH_3 | E_MIPS_MACH_4100;
+ val = EF_MIPS_ARCH_3 | EF_MIPS_MACH_4100;
break;
case bfd_mach_mips4111:
- val = E_MIPS_ARCH_3 | E_MIPS_MACH_4111;
+ val = EF_MIPS_ARCH_3 | EF_MIPS_MACH_4111;
break;
case bfd_mach_mips4120:
- val = E_MIPS_ARCH_3 | E_MIPS_MACH_4120;
+ val = EF_MIPS_ARCH_3 | EF_MIPS_MACH_4120;
break;
case bfd_mach_mips4650:
- val = E_MIPS_ARCH_3 | E_MIPS_MACH_4650;
+ val = EF_MIPS_ARCH_3 | EF_MIPS_MACH_4650;
break;
case bfd_mach_mips5400:
- val = E_MIPS_ARCH_4 | E_MIPS_MACH_5400;
+ val = EF_MIPS_ARCH_4 | EF_MIPS_MACH_5400;
break;
case bfd_mach_mips5500:
- val = E_MIPS_ARCH_4 | E_MIPS_MACH_5500;
+ val = EF_MIPS_ARCH_4 | EF_MIPS_MACH_5500;
break;
case bfd_mach_mips5900:
- val = E_MIPS_ARCH_3 | E_MIPS_MACH_5900;
+ val = EF_MIPS_ARCH_3 | EF_MIPS_MACH_5900;
break;
case bfd_mach_mips9000:
- val = E_MIPS_ARCH_4 | E_MIPS_MACH_9000;
+ val = EF_MIPS_ARCH_4 | EF_MIPS_MACH_9000;
break;
case bfd_mach_mips5000:
@@ -12390,84 +12390,84 @@ mips_set_isa_flags (bfd *abfd)
case bfd_mach_mips12000:
case bfd_mach_mips14000:
case bfd_mach_mips16000:
- val = E_MIPS_ARCH_4;
+ val = EF_MIPS_ARCH_4;
break;
case bfd_mach_mips5:
- val = E_MIPS_ARCH_5;
+ val = EF_MIPS_ARCH_5;
break;
case bfd_mach_mips_loongson_2e:
- val = E_MIPS_ARCH_3 | E_MIPS_MACH_LS2E;
+ val = EF_MIPS_ARCH_3 | EF_MIPS_MACH_LS2E;
break;
case bfd_mach_mips_loongson_2f:
- val = E_MIPS_ARCH_3 | E_MIPS_MACH_LS2F;
+ val = EF_MIPS_ARCH_3 | EF_MIPS_MACH_LS2F;
break;
case bfd_mach_mips_sb1:
- val = E_MIPS_ARCH_64 | E_MIPS_MACH_SB1;
+ val = EF_MIPS_ARCH_64 | EF_MIPS_MACH_SB1;
break;
case bfd_mach_mips_gs464:
- val = E_MIPS_ARCH_64R2 | E_MIPS_MACH_GS464;
+ val = EF_MIPS_ARCH_64R2 | EF_MIPS_MACH_GS464;
break;
case bfd_mach_mips_gs464e:
- val = E_MIPS_ARCH_64R2 | E_MIPS_MACH_GS464E;
+ val = EF_MIPS_ARCH_64R2 | EF_MIPS_MACH_GS464E;
break;
case bfd_mach_mips_gs264e:
- val = E_MIPS_ARCH_64R2 | E_MIPS_MACH_GS264E;
+ val = EF_MIPS_ARCH_64R2 | EF_MIPS_MACH_GS264E;
break;
case bfd_mach_mips_octeon:
case bfd_mach_mips_octeonp:
- val = E_MIPS_ARCH_64R2 | E_MIPS_MACH_OCTEON;
+ val = EF_MIPS_ARCH_64R2 | EF_MIPS_MACH_OCTEON;
break;
case bfd_mach_mips_octeon3:
- val = E_MIPS_ARCH_64R2 | E_MIPS_MACH_OCTEON3;
+ val = EF_MIPS_ARCH_64R2 | EF_MIPS_MACH_OCTEON3;
break;
case bfd_mach_mips_xlr:
- val = E_MIPS_ARCH_64 | E_MIPS_MACH_XLR;
+ val = EF_MIPS_ARCH_64 | EF_MIPS_MACH_XLR;
break;
case bfd_mach_mips_octeon2:
- val = E_MIPS_ARCH_64R2 | E_MIPS_MACH_OCTEON2;
+ val = EF_MIPS_ARCH_64R2 | EF_MIPS_MACH_OCTEON2;
break;
case bfd_mach_mipsisa32:
- val = E_MIPS_ARCH_32;
+ val = EF_MIPS_ARCH_32;
break;
case bfd_mach_mipsisa64:
- val = E_MIPS_ARCH_64;
+ val = EF_MIPS_ARCH_64;
break;
case bfd_mach_mipsisa32r2:
case bfd_mach_mipsisa32r3:
case bfd_mach_mipsisa32r5:
- val = E_MIPS_ARCH_32R2;
+ val = EF_MIPS_ARCH_32R2;
break;
case bfd_mach_mips_interaptiv_mr2:
- val = E_MIPS_ARCH_32R2 | E_MIPS_MACH_IAMR2;
+ val = EF_MIPS_ARCH_32R2 | EF_MIPS_MACH_IAMR2;
break;
case bfd_mach_mipsisa64r2:
case bfd_mach_mipsisa64r3:
case bfd_mach_mipsisa64r5:
- val = E_MIPS_ARCH_64R2;
+ val = EF_MIPS_ARCH_64R2;
break;
case bfd_mach_mipsisa32r6:
- val = E_MIPS_ARCH_32R6;
+ val = EF_MIPS_ARCH_32R6;
break;
case bfd_mach_mipsisa64r6:
- val = E_MIPS_ARCH_64R6;
+ val = EF_MIPS_ARCH_64R6;
break;
}
elf_elfheader (abfd)->e_flags &= ~(EF_MIPS_ARCH | EF_MIPS_MACH);
@@ -14719,17 +14719,17 @@ update_mips_abiflags_isa (bfd *abfd, Elf_Internal_ABIFlags_v0 *abiflags)
int new_isa = 0;
switch (elf_elfheader (abfd)->e_flags & EF_MIPS_ARCH)
{
- case E_MIPS_ARCH_1: new_isa = LEVEL_REV (1, 0); break;
- case E_MIPS_ARCH_2: new_isa = LEVEL_REV (2, 0); break;
- case E_MIPS_ARCH_3: new_isa = LEVEL_REV (3, 0); break;
- case E_MIPS_ARCH_4: new_isa = LEVEL_REV (4, 0); break;
- case E_MIPS_ARCH_5: new_isa = LEVEL_REV (5, 0); break;
- case E_MIPS_ARCH_32: new_isa = LEVEL_REV (32, 1); break;
- case E_MIPS_ARCH_32R2: new_isa = LEVEL_REV (32, 2); break;
- case E_MIPS_ARCH_32R6: new_isa = LEVEL_REV (32, 6); break;
- case E_MIPS_ARCH_64: new_isa = LEVEL_REV (64, 1); break;
- case E_MIPS_ARCH_64R2: new_isa = LEVEL_REV (64, 2); break;
- case E_MIPS_ARCH_64R6: new_isa = LEVEL_REV (64, 6); break;
+ case EF_MIPS_ARCH_1: new_isa = LEVEL_REV (1, 0); break;
+ case EF_MIPS_ARCH_2: new_isa = LEVEL_REV (2, 0); break;
+ case EF_MIPS_ARCH_3: new_isa = LEVEL_REV (3, 0); break;
+ case EF_MIPS_ARCH_4: new_isa = LEVEL_REV (4, 0); break;
+ case EF_MIPS_ARCH_5: new_isa = LEVEL_REV (5, 0); break;
+ case EF_MIPS_ARCH_32: new_isa = LEVEL_REV (32, 1); break;
+ case EF_MIPS_ARCH_32R2: new_isa = LEVEL_REV (32, 2); break;
+ case EF_MIPS_ARCH_32R6: new_isa = LEVEL_REV (32, 6); break;
+ case EF_MIPS_ARCH_64: new_isa = LEVEL_REV (64, 1); break;
+ case EF_MIPS_ARCH_64R2: new_isa = LEVEL_REV (64, 2); break;
+ case EF_MIPS_ARCH_64R6: new_isa = LEVEL_REV (64, 6); break;
default:
_bfd_error_handler
/* xgettext:c-format */
@@ -14755,13 +14755,13 @@ static bool
mips_32bit_flags_p (flagword flags)
{
return ((flags & EF_MIPS_32BITMODE) != 0
- || (flags & EF_MIPS_ABI) == E_MIPS_ABI_O32
- || (flags & EF_MIPS_ABI) == E_MIPS_ABI_EABI32
- || (flags & EF_MIPS_ARCH) == E_MIPS_ARCH_1
- || (flags & EF_MIPS_ARCH) == E_MIPS_ARCH_2
- || (flags & EF_MIPS_ARCH) == E_MIPS_ARCH_32
- || (flags & EF_MIPS_ARCH) == E_MIPS_ARCH_32R2
- || (flags & EF_MIPS_ARCH) == E_MIPS_ARCH_32R6);
+ || (flags & EF_MIPS_ABI) == EF_MIPS_ABI_O32
+ || (flags & EF_MIPS_ABI) == EF_MIPS_ABI_EABI32
+ || (flags & EF_MIPS_ARCH) == EF_MIPS_ARCH_1
+ || (flags & EF_MIPS_ARCH) == EF_MIPS_ARCH_2
+ || (flags & EF_MIPS_ARCH) == EF_MIPS_ARCH_32
+ || (flags & EF_MIPS_ARCH) == EF_MIPS_ARCH_32R2
+ || (flags & EF_MIPS_ARCH) == EF_MIPS_ARCH_32R6);
}
/* Infer the content of the ABI flags based on the elf header. */
@@ -16372,13 +16372,13 @@ _bfd_mips_elf_print_private_bfd_data (bfd *abfd, void *ptr)
/* xgettext:c-format */
fprintf (file, _("private flags = %lx:"), elf_elfheader (abfd)->e_flags);
- if ((elf_elfheader (abfd)->e_flags & EF_MIPS_ABI) == E_MIPS_ABI_O32)
+ if ((elf_elfheader (abfd)->e_flags & EF_MIPS_ABI) == EF_MIPS_ABI_O32)
fprintf (file, _(" [abi=O32]"));
- else if ((elf_elfheader (abfd)->e_flags & EF_MIPS_ABI) == E_MIPS_ABI_O64)
+ else if ((elf_elfheader (abfd)->e_flags & EF_MIPS_ABI) == EF_MIPS_ABI_O64)
fprintf (file, _(" [abi=O64]"));
- else if ((elf_elfheader (abfd)->e_flags & EF_MIPS_ABI) == E_MIPS_ABI_EABI32)
+ else if ((elf_elfheader (abfd)->e_flags & EF_MIPS_ABI) == EF_MIPS_ABI_EABI32)
fprintf (file, _(" [abi=EABI32]"));
- else if ((elf_elfheader (abfd)->e_flags & EF_MIPS_ABI) == E_MIPS_ABI_EABI64)
+ else if ((elf_elfheader (abfd)->e_flags & EF_MIPS_ABI) == EF_MIPS_ABI_EABI64)
fprintf (file, _(" [abi=EABI64]"));
else if ((elf_elfheader (abfd)->e_flags & EF_MIPS_ABI))
fprintf (file, _(" [abi unknown]"));
@@ -16389,27 +16389,27 @@ _bfd_mips_elf_print_private_bfd_data (bfd *abfd, void *ptr)
else
fprintf (file, _(" [no abi set]"));
- if ((elf_elfheader (abfd)->e_flags & EF_MIPS_ARCH) == E_MIPS_ARCH_1)
+ if ((elf_elfheader (abfd)->e_flags & EF_MIPS_ARCH) == EF_MIPS_ARCH_1)
fprintf (file, " [mips1]");
- else if ((elf_elfheader (abfd)->e_flags & EF_MIPS_ARCH) == E_MIPS_ARCH_2)
+ else if ((elf_elfheader (abfd)->e_flags & EF_MIPS_ARCH) == EF_MIPS_ARCH_2)
fprintf (file, " [mips2]");
- else if ((elf_elfheader (abfd)->e_flags & EF_MIPS_ARCH) == E_MIPS_ARCH_3)
+ else if ((elf_elfheader (abfd)->e_flags & EF_MIPS_ARCH) == EF_MIPS_ARCH_3)
fprintf (file, " [mips3]");
- else if ((elf_elfheader (abfd)->e_flags & EF_MIPS_ARCH) == E_MIPS_ARCH_4)
+ else if ((elf_elfheader (abfd)->e_flags & EF_MIPS_ARCH) == EF_MIPS_ARCH_4)
fprintf (file, " [mips4]");
- else if ((elf_elfheader (abfd)->e_flags & EF_MIPS_ARCH) == E_MIPS_ARCH_5)
+ else if ((elf_elfheader (abfd)->e_flags & EF_MIPS_ARCH) == EF_MIPS_ARCH_5)
fprintf (file, " [mips5]");
- else if ((elf_elfheader (abfd)->e_flags & EF_MIPS_ARCH) == E_MIPS_ARCH_32)
+ else if ((elf_elfheader (abfd)->e_flags & EF_MIPS_ARCH) == EF_MIPS_ARCH_32)
fprintf (file, " [mips32]");
- else if ((elf_elfheader (abfd)->e_flags & EF_MIPS_ARCH) == E_MIPS_ARCH_64)
+ else if ((elf_elfheader (abfd)->e_flags & EF_MIPS_ARCH) == EF_MIPS_ARCH_64)
fprintf (file, " [mips64]");
- else if ((elf_elfheader (abfd)->e_flags & EF_MIPS_ARCH) == E_MIPS_ARCH_32R2)
+ else if ((elf_elfheader (abfd)->e_flags & EF_MIPS_ARCH) == EF_MIPS_ARCH_32R2)
fprintf (file, " [mips32r2]");
- else if ((elf_elfheader (abfd)->e_flags & EF_MIPS_ARCH) == E_MIPS_ARCH_64R2)
+ else if ((elf_elfheader (abfd)->e_flags & EF_MIPS_ARCH) == EF_MIPS_ARCH_64R2)
fprintf (file, " [mips64r2]");
- else if ((elf_elfheader (abfd)->e_flags & EF_MIPS_ARCH) == E_MIPS_ARCH_32R6)
+ else if ((elf_elfheader (abfd)->e_flags & EF_MIPS_ARCH) == EF_MIPS_ARCH_32R6)
fprintf (file, " [mips32r6]");
- else if ((elf_elfheader (abfd)->e_flags & EF_MIPS_ARCH) == E_MIPS_ARCH_64R6)
+ else if ((elf_elfheader (abfd)->e_flags & EF_MIPS_ARCH) == EF_MIPS_ARCH_64R6)
fprintf (file, " [mips64r6]");
else
fprintf (file, _(" [unknown ISA]"));
diff --git a/binutils/readelf.c b/binutils/readelf.c
index a06ec79db77..cfc239e592a 100644
--- a/binutils/readelf.c
+++ b/binutils/readelf.c
@@ -3647,70 +3647,70 @@ decode_MIPS_machine_flags (char *out, unsigned int e_flags)
switch ((e_flags & EF_MIPS_MACH))
{
- case E_MIPS_MACH_3900:
+ case EF_MIPS_MACH_3900:
out = stpcpy (out, ", 3900");
break;
- case E_MIPS_MACH_4010:
+ case EF_MIPS_MACH_4010:
out = stpcpy (out, ", 4010");
break;
- case E_MIPS_MACH_4100:
+ case EF_MIPS_MACH_4100:
out = stpcpy (out, ", 4100");
break;
- case E_MIPS_MACH_4111:
+ case EF_MIPS_MACH_4111:
out = stpcpy (out, ", 4111");
break;
- case E_MIPS_MACH_4120:
+ case EF_MIPS_MACH_4120:
out = stpcpy (out, ", 4120");
break;
- case E_MIPS_MACH_4650:
+ case EF_MIPS_MACH_4650:
out = stpcpy (out, ", 4650");
break;
- case E_MIPS_MACH_5400:
+ case EF_MIPS_MACH_5400:
out = stpcpy (out, ", 5400");
break;
- case E_MIPS_MACH_5500:
+ case EF_MIPS_MACH_5500:
out = stpcpy (out, ", 5500");
break;
- case E_MIPS_MACH_5900:
+ case EF_MIPS_MACH_5900:
out = stpcpy (out, ", 5900");
break;
- case E_MIPS_MACH_SB1:
+ case EF_MIPS_MACH_SB1:
out = stpcpy (out, ", sb1");
break;
- case E_MIPS_MACH_9000:
+ case EF_MIPS_MACH_9000:
out = stpcpy (out, ", 9000");
break;
- case E_MIPS_MACH_LS2E:
+ case EF_MIPS_MACH_LS2E:
out = stpcpy (out, ", loongson-2e");
break;
- case E_MIPS_MACH_LS2F:
+ case EF_MIPS_MACH_LS2F:
out = stpcpy (out, ", loongson-2f");
break;
- case E_MIPS_MACH_GS464:
+ case EF_MIPS_MACH_GS464:
out = stpcpy (out, ", gs464");
break;
- case E_MIPS_MACH_GS464E:
+ case EF_MIPS_MACH_GS464E:
out = stpcpy (out, ", gs464e");
break;
- case E_MIPS_MACH_GS264E:
+ case EF_MIPS_MACH_GS264E:
out = stpcpy (out, ", gs264e");
break;
- case E_MIPS_MACH_OCTEON:
+ case EF_MIPS_MACH_OCTEON:
out = stpcpy (out, ", octeon");
break;
- case E_MIPS_MACH_OCTEON2:
+ case EF_MIPS_MACH_OCTEON2:
out = stpcpy (out, ", octeon2");
break;
- case E_MIPS_MACH_OCTEON3:
+ case EF_MIPS_MACH_OCTEON3:
out = stpcpy (out, ", octeon3");
break;
- case E_MIPS_MACH_XLR:
+ case EF_MIPS_MACH_XLR:
out = stpcpy (out, ", xlr");
break;
- case E_MIPS_MACH_IAMR2:
+ case EF_MIPS_MACH_IAMR2:
out = stpcpy (out, ", interaptiv-mr2");
break;
- case E_MIPS_MACH_ALLEGREX:
+ case EF_MIPS_MACH_ALLEGREX:
out = stpcpy (out, ", allegrex");
break;
case 0:
@@ -3725,16 +3725,16 @@ decode_MIPS_machine_flags (char *out, unsigned int e_flags)
switch ((e_flags & EF_MIPS_ABI))
{
- case E_MIPS_ABI_O32:
+ case EF_MIPS_ABI_O32:
out = stpcpy (out, ", o32");
break;
- case E_MIPS_ABI_O64:
+ case EF_MIPS_ABI_O64:
out = stpcpy (out, ", o64");
break;
- case E_MIPS_ABI_EABI32:
+ case EF_MIPS_ABI_EABI32:
out = stpcpy (out, ", eabi32");
break;
- case E_MIPS_ABI_EABI64:
+ case EF_MIPS_ABI_EABI64:
out = stpcpy (out, ", eabi64");
break;
case 0:
@@ -3759,37 +3759,37 @@ decode_MIPS_machine_flags (char *out, unsigned int e_flags)
switch ((e_flags & EF_MIPS_ARCH))
{
- case E_MIPS_ARCH_1:
+ case EF_MIPS_ARCH_1:
out = stpcpy (out, ", mips1");
break;
- case E_MIPS_ARCH_2:
+ case EF_MIPS_ARCH_2:
out = stpcpy (out, ", mips2");
break;
- case E_MIPS_ARCH_3:
+ case EF_MIPS_ARCH_3:
out = stpcpy (out, ", mips3");
break;
- case E_MIPS_ARCH_4:
+ case EF_MIPS_ARCH_4:
out = stpcpy (out, ", mips4");
break;
- case E_MIPS_ARCH_5:
+ case EF_MIPS_ARCH_5:
out = stpcpy (out, ", mips5");
break;
- case E_MIPS_ARCH_32:
+ case EF_MIPS_ARCH_32:
out = stpcpy (out, ", mips32");
break;
- case E_MIPS_ARCH_32R2:
+ case EF_MIPS_ARCH_32R2:
out = stpcpy (out, ", mips32r2");
break;
- case E_MIPS_ARCH_32R6:
+ case EF_MIPS_ARCH_32R6:
out = stpcpy (out, ", mips32r6");
break;
- case E_MIPS_ARCH_64:
+ case EF_MIPS_ARCH_64:
out = stpcpy (out, ", mips64");
break;
- case E_MIPS_ARCH_64R2:
+ case EF_MIPS_ARCH_64R2:
out = stpcpy (out, ", mips64r2");
break;
- case E_MIPS_ARCH_64R6:
+ case EF_MIPS_ARCH_64R6:
out = stpcpy (out, ", mips64r6");
break;
default:
@@ -7595,7 +7595,7 @@ process_section_headers (Filedata * filedata)
earlier compilers provided no way of distinguishing ILP32 objects
from LP64 objects, so if there's any doubt, we should assume that
the official LP64 form is being used. */
- if ((filedata->file_header.e_flags & EF_MIPS_ABI) == E_MIPS_ABI_EABI64
+ if ((filedata->file_header.e_flags & EF_MIPS_ABI) == EF_MIPS_ABI_EABI64
&& find_section (filedata, ".gcc_compiled_long32") == NULL)
eh_addr_size = 8;
break;
diff --git a/elfcpp/mips.h b/elfcpp/mips.h
index daf3f5472f4..bc95277df50 100644
--- a/elfcpp/mips.h
+++ b/elfcpp/mips.h
@@ -218,26 +218,26 @@ enum
// 00 - 7F should be left for a future standard;
// the rest are open.
- E_MIPS_MACH_3900 = 0x00810000,
- E_MIPS_MACH_4010 = 0x00820000,
- E_MIPS_MACH_4100 = 0x00830000,
- E_MIPS_MACH_4650 = 0x00850000,
- E_MIPS_MACH_4120 = 0x00870000,
- E_MIPS_MACH_4111 = 0x00880000,
- E_MIPS_MACH_SB1 = 0x008a0000,
- E_MIPS_MACH_OCTEON = 0x008b0000,
- E_MIPS_MACH_XLR = 0x008c0000,
- E_MIPS_MACH_OCTEON2 = 0x008d0000,
- E_MIPS_MACH_OCTEON3 = 0x008e0000,
- E_MIPS_MACH_5400 = 0x00910000,
- E_MIPS_MACH_5900 = 0x00920000,
- E_MIPS_MACH_5500 = 0x00980000,
- E_MIPS_MACH_9000 = 0x00990000,
- E_MIPS_MACH_LS2E = 0x00A00000,
- E_MIPS_MACH_LS2F = 0x00A10000,
- E_MIPS_MACH_GS464 = 0x00A20000,
- E_MIPS_MACH_GS464E = 0x00A30000,
- E_MIPS_MACH_GS264E = 0x00A40000,
+ EF_MIPS_MACH_3900 = 0x00810000,
+ EF_MIPS_MACH_4010 = 0x00820000,
+ EF_MIPS_MACH_4100 = 0x00830000,
+ EF_MIPS_MACH_4650 = 0x00850000,
+ EF_MIPS_MACH_4120 = 0x00870000,
+ EF_MIPS_MACH_4111 = 0x00880000,
+ EF_MIPS_MACH_SB1 = 0x008a0000,
+ EF_MIPS_MACH_OCTEON = 0x008b0000,
+ EF_MIPS_MACH_XLR = 0x008c0000,
+ EF_MIPS_MACH_OCTEON2 = 0x008d0000,
+ EF_MIPS_MACH_OCTEON3 = 0x008e0000,
+ EF_MIPS_MACH_5400 = 0x00910000,
+ EF_MIPS_MACH_5900 = 0x00920000,
+ EF_MIPS_MACH_5500 = 0x00980000,
+ EF_MIPS_MACH_9000 = 0x00990000,
+ EF_MIPS_MACH_LS2E = 0x00A00000,
+ EF_MIPS_MACH_LS2F = 0x00A10000,
+ EF_MIPS_MACH_GS464 = 0x00A20000,
+ EF_MIPS_MACH_GS464E = 0x00A30000,
+ EF_MIPS_MACH_GS264E = 0x00A40000,
};
// MIPS architecture
@@ -246,27 +246,27 @@ enum
// Four bit MIPS architecture field.
EF_MIPS_ARCH = 0xf0000000,
// -mips1 code.
- E_MIPS_ARCH_1 = 0x00000000,
+ EF_MIPS_ARCH_1 = 0x00000000,
// -mips2 code.
- E_MIPS_ARCH_2 = 0x10000000,
+ EF_MIPS_ARCH_2 = 0x10000000,
// -mips3 code.
- E_MIPS_ARCH_3 = 0x20000000,
+ EF_MIPS_ARCH_3 = 0x20000000,
// -mips4 code.
- E_MIPS_ARCH_4 = 0x30000000,
+ EF_MIPS_ARCH_4 = 0x30000000,
// -mips5 code.
- E_MIPS_ARCH_5 = 0x40000000,
+ EF_MIPS_ARCH_5 = 0x40000000,
// -mips32 code.
- E_MIPS_ARCH_32 = 0x50000000,
+ EF_MIPS_ARCH_32 = 0x50000000,
// -mips64 code.
- E_MIPS_ARCH_64 = 0x60000000,
+ EF_MIPS_ARCH_64 = 0x60000000,
// -mips32r2 code.
- E_MIPS_ARCH_32R2 = 0x70000000,
+ EF_MIPS_ARCH_32R2 = 0x70000000,
// -mips64r2 code.
- E_MIPS_ARCH_64R2 = 0x80000000,
+ EF_MIPS_ARCH_64R2 = 0x80000000,
// -mips32r6 code.
- E_MIPS_ARCH_32R6 = 0x90000000,
+ EF_MIPS_ARCH_32R6 = 0x90000000,
// -mips64r6 code.
- E_MIPS_ARCH_64R6 = 0xa0000000,
+ EF_MIPS_ARCH_64R6 = 0xa0000000,
};
// Values for the xxx_size bytes of an ABI flags structure.
@@ -412,13 +412,13 @@ enum
EF_MIPS_ABI = 0x0000F000,
// The original o32 abi.
- E_MIPS_ABI_O32 = 0x00001000,
+ EF_MIPS_ABI_O32 = 0x00001000,
// O32 extended to work on 64 bit architectures
- E_MIPS_ABI_O64 = 0x00002000,
+ EF_MIPS_ABI_O64 = 0x00002000,
// EABI in 32 bit mode
- E_MIPS_ABI_EABI32 = 0x00003000,
+ EF_MIPS_ABI_EABI32 = 0x00003000,
// EABI in 64 bit mode
- E_MIPS_ABI_EABI64 = 0x00004000,
+ EF_MIPS_ABI_EABI64 = 0x00004000,
};
// Dynamic section MIPS flags
@@ -493,8 +493,8 @@ abi_n32(elfcpp::Elf_Word e_flags)
bool
r6_isa(elfcpp::Elf_Word e_flags)
{
- return ((e_flags & elfcpp::EF_MIPS_ARCH) == elfcpp::E_MIPS_ARCH_32R6)
- || ((e_flags & elfcpp::EF_MIPS_ARCH) == elfcpp::E_MIPS_ARCH_64R6);
+ return ((e_flags & elfcpp::EF_MIPS_ARCH) == elfcpp::EF_MIPS_ARCH_32R6)
+ || ((e_flags & elfcpp::EF_MIPS_ARCH) == elfcpp::EF_MIPS_ARCH_64R6);
}
// Whether the file has microMIPS code.
diff --git a/gas/config.in b/gas/config.in
index 232bc350759..ea21757f6a7 100644
--- a/gas/config.in
+++ b/gas/config.in
@@ -264,8 +264,8 @@
/* Use emulation support? */
#undef USE_EMULATIONS
-/* Allow use of E_MIPS_ABI_O32 on MIPS targets. */
-#undef USE_E_MIPS_ABI_O32
+/* Allow use of EF_MIPS_ABI_O32 on MIPS targets. */
+#undef USE_EF_MIPS_ABI_O32
/* Enable extensions on AIX 3, Interix. */
#ifndef _ALL_SOURCE
diff --git a/gas/config/tc-mips.c b/gas/config/tc-mips.c
index d6aae660abf..f3fe294a85b 100644
--- a/gas/config/tc-mips.c
+++ b/gas/config/tc-mips.c
@@ -19534,16 +19534,16 @@ mips_elf_final_processing (void)
elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_MDMX;
/* Set the MIPS ELF ABI flags. */
- if (mips_abi == O32_ABI && USE_E_MIPS_ABI_O32)
- elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O32;
+ if (mips_abi == O32_ABI && USE_EF_MIPS_ABI_O32)
+ elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ABI_O32;
else if (mips_abi == O64_ABI)
- elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O64;
+ elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ABI_O64;
else if (mips_abi == EABI_ABI)
{
if (file_mips_opts.gp == 64)
- elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI64;
+ elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ABI_EABI64;
else
- elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI32;
+ elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ABI_EABI32;
}
/* Nothing to do for N32_ABI or N64_ABI. */
diff --git a/gas/configure b/gas/configure
index 3c80fe5741a..a012b71c1c8 100755
--- a/gas/configure
+++ b/gas/configure
@@ -12234,14 +12234,14 @@ _ACEOF
as_fn_error $? "$target_cpu isn't a supported MIPS CPU name" "$LINENO" 5
;;
esac
- # See whether it's appropriate to set E_MIPS_ABI_O32 for o32
+ # See whether it's appropriate to set EF_MIPS_ABI_O32 for o32
# binaries. It's a GNU extension that some OSes don't understand.
case ${target} in
*-*-irix*)
- use_e_mips_abi_o32=0
+ use_ef_mips_abi_o32=0
;;
*)
- use_e_mips_abi_o32=1
+ use_ef_mips_abi_o32=1
;;
esac
# Decide whether to generate 32-bit or 64-bit code by default.
@@ -12277,7 +12277,7 @@ _ACEOF
cat >>confdefs.h <<_ACEOF
-#define USE_E_MIPS_ABI_O32 $use_e_mips_abi_o32
+#define USE_EF_MIPS_ABI_O32 $use_ef_mips_abi_o32
_ACEOF
diff --git a/gas/configure.ac b/gas/configure.ac
index 3a04c39d344..d0b4cfb0310 100644
--- a/gas/configure.ac
+++ b/gas/configure.ac
@@ -372,14 +372,14 @@ changequote([,])dnl
AC_MSG_ERROR($target_cpu isn't a supported MIPS CPU name)
;;
esac
- # See whether it's appropriate to set E_MIPS_ABI_O32 for o32
+ # See whether it's appropriate to set EF_MIPS_ABI_O32 for o32
# binaries. It's a GNU extension that some OSes don't understand.
case ${target} in
*-*-irix*)
- use_e_mips_abi_o32=0
+ use_ef_mips_abi_o32=0
;;
*)
- use_e_mips_abi_o32=1
+ use_ef_mips_abi_o32=1
;;
esac
# Decide whether to generate 32-bit or 64-bit code by default.
@@ -410,8 +410,8 @@ changequote([,])dnl
esac
AC_DEFINE_UNQUOTED(MIPS_CPU_STRING_DEFAULT, "$mips_cpu",
[Default CPU for MIPS targets. ])
- AC_DEFINE_UNQUOTED(USE_E_MIPS_ABI_O32, $use_e_mips_abi_o32,
- [Allow use of E_MIPS_ABI_O32 on MIPS targets. ])
+ AC_DEFINE_UNQUOTED(USE_EF_MIPS_ABI_O32, $use_ef_mips_abi_o32,
+ [Allow use of EF_MIPS_ABI_O32 on MIPS targets. ])
AC_DEFINE_UNQUOTED(MIPS_DEFAULT_64BIT, $mips_default_64bit,
[Generate 64-bit code by default on MIPS targets. ])
AC_DEFINE_UNQUOTED(MIPS_DEFAULT_ABI, $mips_default_abi,
diff --git a/gdb/mips-tdep.c b/gdb/mips-tdep.c
index 4044daa2413..809e6007870 100644
--- a/gdb/mips-tdep.c
+++ b/gdb/mips-tdep.c
@@ -8107,16 +8107,16 @@ mips_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
/* Check ELF_FLAGS to see if it specifies the ABI being used. */
switch ((elf_flags & EF_MIPS_ABI))
{
- case E_MIPS_ABI_O32:
+ case EF_MIPS_ABI_O32:
found_abi = MIPS_ABI_O32;
break;
- case E_MIPS_ABI_O64:
+ case EF_MIPS_ABI_O64:
found_abi = MIPS_ABI_O64;
break;
- case E_MIPS_ABI_EABI32:
+ case EF_MIPS_ABI_EABI32:
found_abi = MIPS_ABI_EABI32;
break;
- case E_MIPS_ABI_EABI64:
+ case EF_MIPS_ABI_EABI64:
found_abi = MIPS_ABI_EABI64;
break;
default:
@@ -8921,16 +8921,16 @@ mips_dump_tdep (struct gdbarch *gdbarch, struct ui_file *file)
/* Determine the ISA. */
switch (tdep->elf_flags & EF_MIPS_ARCH)
{
- case E_MIPS_ARCH_1:
+ case EF_MIPS_ARCH_1:
ef_mips_arch = 1;
break;
- case E_MIPS_ARCH_2:
+ case EF_MIPS_ARCH_2:
ef_mips_arch = 2;
break;
- case E_MIPS_ARCH_3:
+ case EF_MIPS_ARCH_3:
ef_mips_arch = 3;
break;
- case E_MIPS_ARCH_4:
+ case EF_MIPS_ARCH_4:
ef_mips_arch = 4;
break;
default:
diff --git a/gold/mips.cc b/gold/mips.cc
index a6a41d7a5e4..121cecdf487 100644
--- a/gold/mips.cc
+++ b/gold/mips.cc
@@ -8807,13 +8807,13 @@ bool
Target_mips<size, big_endian>::mips_32bit_flags(elfcpp::Elf_Word flags)
{
return ((flags & elfcpp::EF_MIPS_32BITMODE) != 0
- || (flags & elfcpp::EF_MIPS_ABI) == elfcpp::E_MIPS_ABI_O32
- || (flags & elfcpp::EF_MIPS_ABI) == elfcpp::E_MIPS_ABI_EABI32
- || (flags & elfcpp::EF_MIPS_ARCH) == elfcpp::E_MIPS_ARCH_1
- || (flags & elfcpp::EF_MIPS_ARCH) == elfcpp::E_MIPS_ARCH_2
- || (flags & elfcpp::EF_MIPS_ARCH) == elfcpp::E_MIPS_ARCH_32
- || (flags & elfcpp::EF_MIPS_ARCH) == elfcpp::E_MIPS_ARCH_32R2
- || (flags & elfcpp::EF_MIPS_ARCH) == elfcpp::E_MIPS_ARCH_32R6);
+ || (flags & elfcpp::EF_MIPS_ABI) == elfcpp::EF_MIPS_ABI_O32
+ || (flags & elfcpp::EF_MIPS_ABI) == elfcpp::EF_MIPS_ABI_EABI32
+ || (flags & elfcpp::EF_MIPS_ARCH) == elfcpp::EF_MIPS_ARCH_1
+ || (flags & elfcpp::EF_MIPS_ARCH) == elfcpp::EF_MIPS_ARCH_2
+ || (flags & elfcpp::EF_MIPS_ARCH) == elfcpp::EF_MIPS_ARCH_32
+ || (flags & elfcpp::EF_MIPS_ARCH) == elfcpp::EF_MIPS_ARCH_32R2
+ || (flags & elfcpp::EF_MIPS_ARCH) == elfcpp::EF_MIPS_ARCH_32R6);
}
// Return the MACH for a MIPS e_flags value.
@@ -8823,101 +8823,101 @@ Target_mips<size, big_endian>::elf_mips_mach(elfcpp::Elf_Word flags)
{
switch (flags & elfcpp::EF_MIPS_MACH)
{
- case elfcpp::E_MIPS_MACH_3900:
+ case elfcpp::EF_MIPS_MACH_3900:
return mach_mips3900;
- case elfcpp::E_MIPS_MACH_4010:
+ case elfcpp::EF_MIPS_MACH_4010:
return mach_mips4010;
- case elfcpp::E_MIPS_MACH_4100:
+ case elfcpp::EF_MIPS_MACH_4100:
return mach_mips4100;
- case elfcpp::E_MIPS_MACH_4111:
+ case elfcpp::EF_MIPS_MACH_4111:
return mach_mips4111;
- case elfcpp::E_MIPS_MACH_4120:
+ case elfcpp::EF_MIPS_MACH_4120:
return mach_mips4120;
- case elfcpp::E_MIPS_MACH_4650:
+ case elfcpp::EF_MIPS_MACH_4650:
return mach_mips4650;
- case elfcpp::E_MIPS_MACH_5400:
+ case elfcpp::EF_MIPS_MACH_5400:
return mach_mips5400;
- case elfcpp::E_MIPS_MACH_5500:
+ case elfcpp::EF_MIPS_MACH_5500:
return mach_mips5500;
- case elfcpp::E_MIPS_MACH_5900:
+ case elfcpp::EF_MIPS_MACH_5900:
return mach_mips5900;
- case elfcpp::E_MIPS_MACH_9000:
+ case elfcpp::EF_MIPS_MACH_9000:
return mach_mips9000;
- case elfcpp::E_MIPS_MACH_SB1:
+ case elfcpp::EF_MIPS_MACH_SB1:
return mach_mips_sb1;
- case elfcpp::E_MIPS_MACH_LS2E:
+ case elfcpp::EF_MIPS_MACH_LS2E:
return mach_mips_loongson_2e;
- case elfcpp::E_MIPS_MACH_LS2F:
+ case elfcpp::EF_MIPS_MACH_LS2F:
return mach_mips_loongson_2f;
- case elfcpp::E_MIPS_MACH_GS464:
+ case elfcpp::EF_MIPS_MACH_GS464:
return mach_mips_gs464;
- case elfcpp::E_MIPS_MACH_GS464E:
+ case elfcpp::EF_MIPS_MACH_GS464E:
return mach_mips_gs464e;
- case elfcpp::E_MIPS_MACH_GS264E:
+ case elfcpp::EF_MIPS_MACH_GS264E:
return mach_mips_gs264e;
- case elfcpp::E_MIPS_MACH_OCTEON3:
+ case elfcpp::EF_MIPS_MACH_OCTEON3:
return mach_mips_octeon3;
- case elfcpp::E_MIPS_MACH_OCTEON2:
+ case elfcpp::EF_MIPS_MACH_OCTEON2:
return mach_mips_octeon2;
- case elfcpp::E_MIPS_MACH_OCTEON:
+ case elfcpp::EF_MIPS_MACH_OCTEON:
return mach_mips_octeon;
- case elfcpp::E_MIPS_MACH_XLR:
+ case elfcpp::EF_MIPS_MACH_XLR:
return mach_mips_xlr;
default:
switch (flags & elfcpp::EF_MIPS_ARCH)
{
default:
- case elfcpp::E_MIPS_ARCH_1:
+ case elfcpp::EF_MIPS_ARCH_1:
return mach_mips3000;
- case elfcpp::E_MIPS_ARCH_2:
+ case elfcpp::EF_MIPS_ARCH_2:
return mach_mips6000;
- case elfcpp::E_MIPS_ARCH_3:
+ case elfcpp::EF_MIPS_ARCH_3:
return mach_mips4000;
- case elfcpp::E_MIPS_ARCH_4:
+ case elfcpp::EF_MIPS_ARCH_4:
return mach_mips8000;
- case elfcpp::E_MIPS_ARCH_5:
+ case elfcpp::EF_MIPS_ARCH_5:
return mach_mips5;
- case elfcpp::E_MIPS_ARCH_32:
+ case elfcpp::EF_MIPS_ARCH_32:
return mach_mipsisa32;
- case elfcpp::E_MIPS_ARCH_64:
+ case elfcpp::EF_MIPS_ARCH_64:
return mach_mipsisa64;
- case elfcpp::E_MIPS_ARCH_32R2:
+ case elfcpp::EF_MIPS_ARCH_32R2:
return mach_mipsisa32r2;
- case elfcpp::E_MIPS_ARCH_32R6:
+ case elfcpp::EF_MIPS_ARCH_32R6:
return mach_mipsisa32r6;
- case elfcpp::E_MIPS_ARCH_64R2:
+ case elfcpp::EF_MIPS_ARCH_64R2:
return mach_mipsisa64r2;
- case elfcpp::E_MIPS_ARCH_64R6:
+ case elfcpp::EF_MIPS_ARCH_64R6:
return mach_mipsisa64r6;
}
}
@@ -9066,37 +9066,37 @@ Target_mips<size, big_endian>::update_abiflags_isa(const std::string& name,
int new_isa = 0;
switch (e_flags & elfcpp::EF_MIPS_ARCH)
{
- case elfcpp::E_MIPS_ARCH_1:
+ case elfcpp::EF_MIPS_ARCH_1:
new_isa = this->level_rev(1, 0);
break;
- case elfcpp::E_MIPS_ARCH_2:
+ case elfcpp::EF_MIPS_ARCH_2:
new_isa = this->level_rev(2, 0);
break;
- case elfcpp::E_MIPS_ARCH_3:
+ case elfcpp::EF_MIPS_ARCH_3:
new_isa = this->level_rev(3, 0);
break;
- case elfcpp::E_MIPS_ARCH_4:
+ case elfcpp::EF_MIPS_ARCH_4:
new_isa = this->level_rev(4, 0);
break;
- case elfcpp::E_MIPS_ARCH_5:
+ case elfcpp::EF_MIPS_ARCH_5:
new_isa = this->level_rev(5, 0);
break;
- case elfcpp::E_MIPS_ARCH_32:
+ case elfcpp::EF_MIPS_ARCH_32:
new_isa = this->level_rev(32, 1);
break;
- case elfcpp::E_MIPS_ARCH_32R2:
+ case elfcpp::EF_MIPS_ARCH_32R2:
new_isa = this->level_rev(32, 2);
break;
- case elfcpp::E_MIPS_ARCH_32R6:
+ case elfcpp::EF_MIPS_ARCH_32R6:
new_isa = this->level_rev(32, 6);
break;
- case elfcpp::E_MIPS_ARCH_64:
+ case elfcpp::EF_MIPS_ARCH_64:
new_isa = this->level_rev(64, 1);
break;
- case elfcpp::E_MIPS_ARCH_64R2:
+ case elfcpp::EF_MIPS_ARCH_64R2:
new_isa = this->level_rev(64, 2);
break;
- case elfcpp::E_MIPS_ARCH_64R6:
+ case elfcpp::EF_MIPS_ARCH_64R6:
new_isa = this->level_rev(64, 6);
break;
default:
@@ -12489,13 +12489,13 @@ Target_mips<size, big_endian>::elf_mips_abi_name(elfcpp::Elf_Word e_flags)
return "64";
else
return "none";
- case elfcpp::E_MIPS_ABI_O32:
+ case elfcpp::EF_MIPS_ABI_O32:
return "O32";
- case elfcpp::E_MIPS_ABI_O64:
+ case elfcpp::EF_MIPS_ABI_O64:
return "O64";
- case elfcpp::E_MIPS_ABI_EABI32:
+ case elfcpp::EF_MIPS_ABI_EABI32:
return "EABI32";
- case elfcpp::E_MIPS_ABI_EABI64:
+ case elfcpp::EF_MIPS_ABI_EABI64:
return "EABI64";
default:
return "unknown abi";
@@ -12508,81 +12508,81 @@ Target_mips<size, big_endian>::elf_mips_mach_name(elfcpp::Elf_Word e_flags)
{
switch (e_flags & elfcpp::EF_MIPS_MACH)
{
- case elfcpp::E_MIPS_MACH_3900:
+ case elfcpp::EF_MIPS_MACH_3900:
return "mips:3900";
- case elfcpp::E_MIPS_MACH_4010:
+ case elfcpp::EF_MIPS_MACH_4010:
return "mips:4010";
- case elfcpp::E_MIPS_MACH_4100:
+ case elfcpp::EF_MIPS_MACH_4100:
return "mips:4100";
- case elfcpp::E_MIPS_MACH_4111:
+ case elfcpp::EF_MIPS_MACH_4111:
return "mips:4111";
- case elfcpp::E_MIPS_MACH_4120:
+ case elfcpp::EF_MIPS_MACH_4120:
return "mips:4120";
- case elfcpp::E_MIPS_MACH_4650:
+ case elfcpp::EF_MIPS_MACH_4650:
return "mips:4650";
- case elfcpp::E_MIPS_MACH_5400:
+ case elfcpp::EF_MIPS_MACH_5400:
return "mips:5400";
- case elfcpp::E_MIPS_MACH_5500:
+ case elfcpp::EF_MIPS_MACH_5500:
return "mips:5500";
- case elfcpp::E_MIPS_MACH_5900:
+ case elfcpp::EF_MIPS_MACH_5900:
return "mips:5900";
- case elfcpp::E_MIPS_MACH_SB1:
+ case elfcpp::EF_MIPS_MACH_SB1:
return "mips:sb1";
- case elfcpp::E_MIPS_MACH_9000:
+ case elfcpp::EF_MIPS_MACH_9000:
return "mips:9000";
- case elfcpp::E_MIPS_MACH_LS2E:
+ case elfcpp::EF_MIPS_MACH_LS2E:
return "mips:loongson_2e";
- case elfcpp::E_MIPS_MACH_LS2F:
+ case elfcpp::EF_MIPS_MACH_LS2F:
return "mips:loongson_2f";
- case elfcpp::E_MIPS_MACH_GS464:
+ case elfcpp::EF_MIPS_MACH_GS464:
return "mips:gs464";
- case elfcpp::E_MIPS_MACH_GS464E:
+ case elfcpp::EF_MIPS_MACH_GS464E:
return "mips:gs464e";
- case elfcpp::E_MIPS_MACH_GS264E:
+ case elfcpp::EF_MIPS_MACH_GS264E:
return "mips:gs264e";
- case elfcpp::E_MIPS_MACH_OCTEON:
+ case elfcpp::EF_MIPS_MACH_OCTEON:
return "mips:octeon";
- case elfcpp::E_MIPS_MACH_OCTEON2:
+ case elfcpp::EF_MIPS_MACH_OCTEON2:
return "mips:octeon2";
- case elfcpp::E_MIPS_MACH_OCTEON3:
+ case elfcpp::EF_MIPS_MACH_OCTEON3:
return "mips:octeon3";
- case elfcpp::E_MIPS_MACH_XLR:
+ case elfcpp::EF_MIPS_MACH_XLR:
return "mips:xlr";
default:
switch (e_flags & elfcpp::EF_MIPS_ARCH)
{
default:
- case elfcpp::E_MIPS_ARCH_1:
+ case elfcpp::EF_MIPS_ARCH_1:
return "mips:3000";
- case elfcpp::E_MIPS_ARCH_2:
+ case elfcpp::EF_MIPS_ARCH_2:
return "mips:6000";
- case elfcpp::E_MIPS_ARCH_3:
+ case elfcpp::EF_MIPS_ARCH_3:
return "mips:4000";
- case elfcpp::E_MIPS_ARCH_4:
+ case elfcpp::EF_MIPS_ARCH_4:
return "mips:8000";
- case elfcpp::E_MIPS_ARCH_5:
+ case elfcpp::EF_MIPS_ARCH_5:
return "mips:mips5";
- case elfcpp::E_MIPS_ARCH_32:
+ case elfcpp::EF_MIPS_ARCH_32:
return "mips:isa32";
- case elfcpp::E_MIPS_ARCH_64:
+ case elfcpp::EF_MIPS_ARCH_64:
return "mips:isa64";
- case elfcpp::E_MIPS_ARCH_32R2:
+ case elfcpp::EF_MIPS_ARCH_32R2:
return "mips:isa32r2";
- case elfcpp::E_MIPS_ARCH_32R6:
+ case elfcpp::EF_MIPS_ARCH_32R6:
return "mips:isa32r6";
- case elfcpp::E_MIPS_ARCH_64R2:
+ case elfcpp::EF_MIPS_ARCH_64R2:
return "mips:isa64r2";
- case elfcpp::E_MIPS_ARCH_64R6:
+ case elfcpp::EF_MIPS_ARCH_64R6:
return "mips:isa64r6";
}
}
diff --git a/include/elf/mips.h b/include/elf/mips.h
index 2c13cc88b40..48d54a1808f 100644
--- a/include/elf/mips.h
+++ b/include/elf/mips.h
@@ -223,52 +223,52 @@ END_RELOC_NUMBERS (R_MIPS_maxext)
#define EF_MIPS_ARCH 0xf0000000
/* -mips1 code. */
-#define E_MIPS_ARCH_1 0x00000000
+#define EF_MIPS_ARCH_1 0x00000000
/* -mips2 code. */
-#define E_MIPS_ARCH_2 0x10000000
+#define EF_MIPS_ARCH_2 0x10000000
/* -mips3 code. */
-#define E_MIPS_ARCH_3 0x20000000
+#define EF_MIPS_ARCH_3 0x20000000
/* -mips4 code. */
-#define E_MIPS_ARCH_4 0x30000000
+#define EF_MIPS_ARCH_4 0x30000000
/* -mips5 code. */
-#define E_MIPS_ARCH_5 0x40000000
+#define EF_MIPS_ARCH_5 0x40000000
/* -mips32 code. */
-#define E_MIPS_ARCH_32 0x50000000
+#define EF_MIPS_ARCH_32 0x50000000
/* -mips64 code. */
-#define E_MIPS_ARCH_64 0x60000000
+#define EF_MIPS_ARCH_64 0x60000000
/* -mips32r2 code. */
-#define E_MIPS_ARCH_32R2 0x70000000
+#define EF_MIPS_ARCH_32R2 0x70000000
/* -mips64r2 code. */
-#define E_MIPS_ARCH_64R2 0x80000000
+#define EF_MIPS_ARCH_64R2 0x80000000
/* -mips32r6 code. */
-#define E_MIPS_ARCH_32R6 0x90000000
+#define EF_MIPS_ARCH_32R6 0x90000000
/* -mips64r6 code. */
-#define E_MIPS_ARCH_64R6 0xa0000000
+#define EF_MIPS_ARCH_64R6 0xa0000000
/* The ABI of the file. Also see EF_MIPS_ABI2 above. */
#define EF_MIPS_ABI 0x0000F000
/* The original o32 abi. */
-#define E_MIPS_ABI_O32 0x00001000
+#define EF_MIPS_ABI_O32 0x00001000
/* O32 extended to work on 64 bit architectures */
-#define E_MIPS_ABI_O64 0x00002000
+#define EF_MIPS_ABI_O64 0x00002000
/* EABI in 32 bit mode */
-#define E_MIPS_ABI_EABI32 0x00003000
+#define EF_MIPS_ABI_EABI32 0x00003000
/* EABI in 64 bit mode */
-#define E_MIPS_ABI_EABI64 0x00004000
+#define EF_MIPS_ABI_EABI64 0x00004000
/* Machine variant if we know it. This field was invented at Cygnus,
@@ -281,28 +281,28 @@ END_RELOC_NUMBERS (R_MIPS_maxext)
00 - 7F should be left for a future standard;
the rest are open. */
-#define E_MIPS_MACH_3900 0x00810000
-#define E_MIPS_MACH_4010 0x00820000
-#define E_MIPS_MACH_4100 0x00830000
-#define E_MIPS_MACH_ALLEGREX 0x00840000
-#define E_MIPS_MACH_4650 0x00850000
-#define E_MIPS_MACH_4120 0x00870000
-#define E_MIPS_MACH_4111 0x00880000
-#define E_MIPS_MACH_SB1 0x008a0000
-#define E_MIPS_MACH_OCTEON 0x008b0000
-#define E_MIPS_MACH_XLR 0x008c0000
-#define E_MIPS_MACH_OCTEON2 0x008d0000
-#define E_MIPS_MACH_OCTEON3 0x008e0000
-#define E_MIPS_MACH_5400 0x00910000
-#define E_MIPS_MACH_5900 0x00920000
-#define E_MIPS_MACH_IAMR2 0x00930000
-#define E_MIPS_MACH_5500 0x00980000
-#define E_MIPS_MACH_9000 0x00990000
-#define E_MIPS_MACH_LS2E 0x00A00000
-#define E_MIPS_MACH_LS2F 0x00A10000
-#define E_MIPS_MACH_GS464 0x00A20000
-#define E_MIPS_MACH_GS464E 0x00A30000
-#define E_MIPS_MACH_GS264E 0x00A40000
+#define EF_MIPS_MACH_3900 0x00810000
+#define EF_MIPS_MACH_4010 0x00820000
+#define EF_MIPS_MACH_4100 0x00830000
+#define EF_MIPS_MACH_ALLEGREX 0x00840000
+#define EF_MIPS_MACH_4650 0x00850000
+#define EF_MIPS_MACH_4120 0x00870000
+#define EF_MIPS_MACH_4111 0x00880000
+#define EF_MIPS_MACH_SB1 0x008a0000
+#define EF_MIPS_MACH_OCTEON 0x008b0000
+#define EF_MIPS_MACH_XLR 0x008c0000
+#define EF_MIPS_MACH_OCTEON2 0x008d0000
+#define EF_MIPS_MACH_OCTEON3 0x008e0000
+#define EF_MIPS_MACH_5400 0x00910000
+#define EF_MIPS_MACH_5900 0x00920000
+#define EF_MIPS_MACH_IAMR2 0x00930000
+#define EF_MIPS_MACH_5500 0x00980000
+#define EF_MIPS_MACH_9000 0x00990000
+#define EF_MIPS_MACH_LS2E 0x00A00000
+#define EF_MIPS_MACH_LS2F 0x00A10000
+#define EF_MIPS_MACH_GS464 0x00A20000
+#define EF_MIPS_MACH_GS464E 0x00A30000
+#define EF_MIPS_MACH_GS264E 0x00A40000
\f
/* Processor specific section indices. These sections do not actually
exist. Symbols with a st_shndx field corresponding to one of these
diff --git a/sim/mips/interp.c b/sim/mips/interp.c
index e521963a902..f0c509021a4 100644
--- a/sim/mips/interp.c
+++ b/sim/mips/interp.c
@@ -1557,8 +1557,8 @@ store_word (SIM_DESC sd,
}
#define MIPSR6_P(abfd) \
- ((elf_elfheader (abfd)->e_flags & EF_MIPS_ARCH) == E_MIPS_ARCH_32R6 \
- || (elf_elfheader (abfd)->e_flags & EF_MIPS_ARCH) == E_MIPS_ARCH_64R6)
+ ((elf_elfheader (abfd)->e_flags & EF_MIPS_ARCH) == EF_MIPS_ARCH_32R6 \
+ || (elf_elfheader (abfd)->e_flags & EF_MIPS_ARCH) == EF_MIPS_ARCH_64R6)
/* Load a word from memory. */
--
2.34.1
next reply other threads:[~2023-08-18 9:51 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-08-18 9:50 Ying Huang [this message]
2023-10-07 3:27 ` YunQiang Su
2023-10-07 14:57 ` Maciej W. Rozycki
2023-10-07 15:08 ` Maciej W. Rozycki
2023-10-08 6:13 ` Ying Huang
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