From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-pf1-x432.google.com (mail-pf1-x432.google.com [IPv6:2607:f8b0:4864:20::432]) by sourceware.org (Postfix) with ESMTPS id AA05D3858D32 for ; Tue, 19 Sep 2023 07:02:22 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org AA05D3858D32 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=gmail.com Received: by mail-pf1-x432.google.com with SMTP id d2e1a72fcca58-68fb2e9ebcdso3970904b3a.2 for ; Tue, 19 Sep 2023 00:02:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1695106941; x=1695711741; darn=sourceware.org; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:from:to:cc:subject:date:message-id:reply-to; bh=5rz0JxUc7vipoOicEkSlECmozYkjx/ggJ+vQymmz0Z8=; b=TuZn4iZLC7IzvVldaNuRghE3dYpNl50+ksIQUcDbYXw23WmR5Qh4/KMbYofF/d6e1x Ee8LHlzylyQKgmKKuHXy2lnLbY4Gbykx/7aGlRmRj5uycmKWNw9wyWIxZjroW1JlO+vz I+OjHUb5HM3V8k5i54Y3Te/zFfGtau0X6Ahf8ApKJwylwolECUYb4B4JSTWWm8V4rpH4 ws/buUADsFvvNdJFUwgtEB504mjXuJuoa5vNBXDjORVN1nI+NLShuL7dfkNngcl+wTKw b7fsBQujp3KaH83LCf27RJw+ovoGP+Pe4ZuHyrBQLOjyj/9UrsUeTgM9IXg8EOZe4GLu qeJQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1695106941; x=1695711741; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=5rz0JxUc7vipoOicEkSlECmozYkjx/ggJ+vQymmz0Z8=; b=BnH1tySL6BNEs/sGATEXFI5sHWFP0JNDiQpsET5fmteVcDl9lEyGqvq3Yc6IHZznsJ /Z3iBv+d7kZzzYD5u0YpegtiT2yUHDpN/26MrFtMJQrc/W9+pjHmlFeS6IcXOaqOEbxb kOSAOP1/Xo/g/BclaZ1yw+NQ505V/YexG60o7TGwnlTC2/K+h/hNvEUKJ71A6IiRUxh2 4hou/xn71ub6edgqdzT/hRlu3cM5drf8UdMwmgGKcazvq2lde/6uU9c0icmip8+hYmCv /sg9rXyIcNgxF4+Psyd90LkDpi8JyE6C9wYC21f7cqtX7EQRCm34Tn/gk/Mdmin3IbzV orFg== X-Gm-Message-State: AOJu0YxCz9C1+5eejHsCMSiyOt7txG8XeCFaf/AofJ3P4PF2RzbrQ1Jn e4D5bD0nR2Sa6uuca/KZwOk6UWkVirI= X-Google-Smtp-Source: AGHT+IGafPkhsVMc038gaVFksdraf1bTa+G7cn5clWn5q6R7ryQITmzLX4XF5BcT05zPbP3wuBihJQ== X-Received: by 2002:a05:6a00:23c4:b0:68e:29a6:e247 with SMTP id g4-20020a056a0023c400b0068e29a6e247mr12094845pfc.10.1695106940594; Tue, 19 Sep 2023 00:02:20 -0700 (PDT) Received: from blue.flets-east.jp ([2405:6580:8dc0:3c00:8694:ace3:6efb:65a2]) by smtp.gmail.com with ESMTPSA id s12-20020a62e70c000000b0068fda1db80bsm8030488pfh.75.2023.09.19.00.02.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 19 Sep 2023 00:02:20 -0700 (PDT) From: Rui Ueyama X-Google-Original-From: Rui Ueyama To: binutils@sourceware.org Cc: Rui Ueyama Subject: [PATCH] RISC-V: emit R_RISCV_RELAX for the la pseudo instruction Date: Tue, 19 Sep 2023 16:01:21 +0900 Message-Id: <20230919070121.1489019-1-ruiu@bluewhale.systems> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-9.3 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_ENVFROM_END_DIGIT,FREEMAIL_FROM,GIT_PATCH_0,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: Some psABIs define a relaxation to turn a GOT load into a PC-relative address materialization. For example, the AArch64's psABI allows adrp+ldr to be rewritten to nop+adr to eliminate the memory load. This patch is part of the effort to make such optimization possible for RISC-V. For RISC-V, we use the la assembly pseudo instruction to load a symbol address from the GOT. The pseudo instruction is expanded to auipc+ld. If the address loaded by the instruction pair is actually a PC-relative link-time constant, we want the linker to rewrite the instruction pair with auipc+addi. We can't rewrite all existing auipc+ld pairs with auipc+addi in the linker because there might be code that jumps to the middle of the instruction pair. That should be extremely rare, if ever exists, but you can at least in theory write a program in assembly that jumps to the ld instruction of the instruction pair. We need a marker to identify that an auipc+ld can be safely relaxed (i.e. they are emitted for la). This patch is to annotate R_RISCV_GOT_HI20 with R_RISCV_RELAX only when the relocation is emitted for the la pseudo instruction. The linker will use it as a signal that the instruction pair can be safely relaxed. Proposal to the RISC-V psABI: https://github.com/riscv-non-isa/riscv-elf-psabi-doc/pull/397 --- bfd/bfd-in2.h | 1 + bfd/elfxx-riscv.c | 1 + gas/config/tc-riscv.c | 3 ++- gas/testsuite/gas/riscv/la-variants.d | 3 +++ 4 files changed, 7 insertions(+), 1 deletion(-) diff --git a/bfd/bfd-in2.h b/bfd/bfd-in2.h index 1c4f75ae244..e15641a1d00 100644 --- a/bfd/bfd-in2.h +++ b/bfd/bfd-in2.h @@ -5413,6 +5413,7 @@ number for the SBIC, SBIS, SBI and CBI instructions */ BFD_RELOC_RISCV_SUB32, BFD_RELOC_RISCV_SUB64, BFD_RELOC_RISCV_GOT_HI20, + BFD_RELOC_RISCV_GOT_HI20_RELAX, BFD_RELOC_RISCV_TLS_GOT_HI20, BFD_RELOC_RISCV_TLS_GD_HI20, BFD_RELOC_RISCV_JMP, diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c index 6ed657171f0..71e63e7b789 100644 --- a/bfd/elfxx-riscv.c +++ b/bfd/elfxx-riscv.c @@ -913,6 +913,7 @@ static const struct elf_reloc_map riscv_reloc_map[] = { BFD_RELOC_RISCV_PCREL_HI20, R_RISCV_PCREL_HI20 }, { BFD_RELOC_RISCV_JMP, R_RISCV_JAL }, { BFD_RELOC_RISCV_GOT_HI20, R_RISCV_GOT_HI20 }, + { BFD_RELOC_RISCV_GOT_HI20_RELAX, R_RISCV_GOT_HI20 }, { BFD_RELOC_RISCV_TLS_DTPMOD32, R_RISCV_TLS_DTPMOD32 }, { BFD_RELOC_RISCV_TLS_DTPREL32, R_RISCV_TLS_DTPREL32 }, { BFD_RELOC_RISCV_TLS_DTPMOD64, R_RISCV_TLS_DTPMOD64 }, diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c index 3b520ad208b..303ae18436c 100644 --- a/gas/config/tc-riscv.c +++ b/gas/config/tc-riscv.c @@ -2039,7 +2039,7 @@ macro (struct riscv_cl_insn *ip, expressionS *imm_expr, else if ((riscv_opts.pic && mask == M_LA) || mask == M_LGA) pcrel_load (rd, rd, imm_expr, LOAD_ADDRESS_INSN, - BFD_RELOC_RISCV_GOT_HI20, BFD_RELOC_RISCV_PCREL_LO12_I); + BFD_RELOC_RISCV_GOT_HI20_RELAX, BFD_RELOC_RISCV_PCREL_LO12_I); /* Local PIC symbol, or any non-PIC symbol. */ else pcrel_load (rd, rd, imm_expr, "addi", @@ -4244,6 +4244,7 @@ md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED) relaxable = true; break; + case BFD_RELOC_RISCV_GOT_HI20_RELAX: case BFD_RELOC_RISCV_PCREL_HI20: case BFD_RELOC_RISCV_PCREL_LO12_S: case BFD_RELOC_RISCV_PCREL_LO12_I: diff --git a/gas/testsuite/gas/riscv/la-variants.d b/gas/testsuite/gas/riscv/la-variants.d index b1d316983b7..e8ac09c2af2 100644 --- a/gas/testsuite/gas/riscv/la-variants.d +++ b/gas/testsuite/gas/riscv/la-variants.d @@ -21,11 +21,13 @@ Disassembly of section .text: [ ]+[0-9a-f]+:[ ]+R_RISCV_RELAX[ ]+\*ABS\* [ ]+[0-9a-f]+:[ ]+00000617[ ]+auipc[ ]+a2,0x0 [ ]+[0-9a-f]+:[ ]+R_RISCV_GOT_HI20[ ]+a +[ ]+[0-9a-f]+:[ ]+R_RISCV_RELAX[ ]+\*ABS\* [ ]+[0-9a-f]+:[ ]+(00062603|00063603)[ ]+(lw|ld)[ ]+a2,0\(a2\).* [ ]+[0-9a-f]+:[ ]+R_RISCV_PCREL_LO12_I[ ]+\.L0[ ]+ [ ]+[0-9a-f]+:[ ]+R_RISCV_RELAX[ ]+\*ABS\* [ ]+[0-9a-f]+:[ ]+00000697[ ]+auipc[ ]+a3,0x0 [ ]+[0-9a-f]+:[ ]+R_RISCV_GOT_HI20[ ]+a +[ ]+[0-9a-f]+:[ ]+R_RISCV_RELAX[ ]+\*ABS\* [ ]+[0-9a-f]+:[ ]+(0006a683|0006b683)[ ]+(lw|ld)[ ]+a3,0\(a3\).* [ ]+[0-9a-f]+:[ ]+R_RISCV_PCREL_LO12_I[ ]+\.L0[ ]+ [ ]+[0-9a-f]+:[ ]+R_RISCV_RELAX[ ]+\*ABS\* @@ -37,6 +39,7 @@ Disassembly of section .text: [ ]+[0-9a-f]+:[ ]+R_RISCV_RELAX[ ]+\*ABS\* [ ]+[0-9a-f]+:[ ]+00000797[ ]+auipc[ ]+a5,0x0 [ ]+[0-9a-f]+:[ ]+R_RISCV_GOT_HI20[ ]+a +[ ]+[0-9a-f]+:[ ]+R_RISCV_RELAX[ ]+\*ABS\* [ ]+[0-9a-f]+:[ ]+(0007a783|0007b783)[ ]+(lw|ld)[ ]+a5,0\(a5\).* [ ]+[0-9a-f]+:[ ]+R_RISCV_PCREL_LO12_I[ ]+\.L0[ ]+ [ ]+[0-9a-f]+:[ ]+R_RISCV_RELAX[ ]+\*ABS\* -- 2.34.1