From: Victor Do Nascimento <victor.donascimento@arm.com>
To: <binutils@sourceware.org>
Cc: <richard.earnshaw@arm.com>, <nickc@redhat.com>,
Victor Do Nascimento <victor.donascimento@arm.com>
Subject: [PATCH 2/3] aarch64: Add arch support for LSE128 extension
Date: Mon, 6 Nov 2023 13:12:47 +0000 [thread overview]
Message-ID: <20231106131301.2576862-3-victor.donascimento@arm.com> (raw)
In-Reply-To: <20231106131301.2576862-1-victor.donascimento@arm.com>
Enable the `+lse128' feature modifier which, together with new
internal feature flags, enables LSE128 instructions, which are
represented via the new `_LSE128_INSN' macro.
gas/ChangeLog:
* config/tc-aarch64.c (aarch64_features): Add new "lse128"
entry.
include/ChangeLog:
* include/opcode/aarch64.h (enum aarch64_feature_bit): New
AARCH64_FEATURE_LSE128 feature bit.
(enum aarch64_insn_class): New lse128_atomic instruction class.
opcodes/ChangeLog:
* opcodes/aarch64-tbl.h (aarch64_feature_lse128): New.
(LSE128): Likewise.
(_LSE128_INSN): Likewise.
---
gas/config/tc-aarch64.c | 1 +
gas/doc/c-aarch64.texi | 2 ++
include/opcode/aarch64.h | 3 +++
opcodes/aarch64-tbl.h | 5 +++++
4 files changed, 11 insertions(+)
diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c
index 7e76c1b0733..325ea2f99d8 100644
--- a/gas/config/tc-aarch64.c
+++ b/gas/config/tc-aarch64.c
@@ -10239,6 +10239,7 @@ static const struct aarch64_option_cpu_value_table aarch64_features[] = {
AARCH64_FEATURE (SIMD)},
{"fp", AARCH64_FEATURE (FP), AARCH64_NO_FEATURES},
{"lse", AARCH64_FEATURE (LSE), AARCH64_NO_FEATURES},
+ {"lse128", AARCH64_FEATURES (2, LSE, LSE128), AARCH64_NO_FEATURES},
{"simd", AARCH64_FEATURE (SIMD), AARCH64_FEATURE (FP)},
{"pan", AARCH64_FEATURE (PAN), AARCH64_NO_FEATURES},
{"lor", AARCH64_FEATURE (LOR), AARCH64_NO_FEATURES},
diff --git a/gas/doc/c-aarch64.texi b/gas/doc/c-aarch64.texi
index a3ca714c299..b9fddd6a7f9 100644
--- a/gas/doc/c-aarch64.texi
+++ b/gas/doc/c-aarch64.texi
@@ -263,6 +263,8 @@ automatically cause those extensions to be disabled.
@tab Enable Check Feature Status Extension.
@item @code{gcs} @tab N/A @tab No
@tab Enable Guarded Control Stack Extension.
+@item @code{lse128} @Armv9.4-A @tab No
+ @tab Enable the 128-bit Atomic Instructions extension. This implies @code{lse}.
@end multitable
@node AArch64 Syntax
diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h
index 2b7e633fae2..3dd55f1438e 100644
--- a/include/opcode/aarch64.h
+++ b/include/opcode/aarch64.h
@@ -165,6 +165,8 @@ enum aarch64_feature_bit {
AARCH64_FEATURE_GCS,
/* SME2. */
AARCH64_FEATURE_SME2,
+ /* LSE128. */
+ AARCH64_FEATURE_LSE128,
AARCH64_NUM_FEATURES
};
@@ -855,6 +857,7 @@ enum aarch64_insn_class
log_imm,
log_shift,
lse_atomic,
+ lse128_atomic,
movewide,
pcreladdr,
ic_system,
diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h
index 150b042d7ee..58787fbc4a9 100644
--- a/opcodes/aarch64-tbl.h
+++ b/opcodes/aarch64-tbl.h
@@ -2470,6 +2470,8 @@ static const aarch64_feature_set aarch64_feature_crc =
AARCH64_FEATURE (CRC);
static const aarch64_feature_set aarch64_feature_lse =
AARCH64_FEATURE (LSE);
+static const aarch64_feature_set aarch64_feature_lse128 =
+ AARCH64_FEATURES (2, LSE, LSE128);
static const aarch64_feature_set aarch64_feature_lor =
AARCH64_FEATURE (LOR);
static const aarch64_feature_set aarch64_feature_rdma =
@@ -2582,6 +2584,7 @@ static const aarch64_feature_set aarch64_feature_gcs =
#define SIMD &aarch64_feature_simd
#define CRC &aarch64_feature_crc
#define LSE &aarch64_feature_lse
+#define LSE128 &aarch64_feature_lse128
#define LOR &aarch64_feature_lor
#define RDMA &aarch64_feature_rdma
#define FP_F16 &aarch64_feature_fp_f16
@@ -2649,6 +2652,8 @@ static const aarch64_feature_set aarch64_feature_gcs =
{ NAME, OPCODE, MASK, CLASS, 0, CRC, OPS, QUALS, FLAGS, 0, 0, NULL }
#define _LSE_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \
{ NAME, OPCODE, MASK, CLASS, 0, LSE, OPS, QUALS, FLAGS, 0, 0, NULL }
+#define _LSE128_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \
+ { NAME, OPCODE, MASK, CLASS, 0, LSE128, OPS, QUALS, FLAGS, 0, 0, NULL }
#define _LOR_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \
{ NAME, OPCODE, MASK, CLASS, 0, LOR, OPS, QUALS, FLAGS, 0, 0, NULL }
#define RDMA_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \
--
2.41.0
next prev parent reply other threads:[~2023-11-06 13:13 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-11-06 13:12 [PATCH 0/3] aarch64: Add support for the Armv9.4-a " Victor Do Nascimento
2023-11-06 13:12 ` [PATCH 1/3] aarch64: Add LSE128 instruction operand support Victor Do Nascimento
2023-11-06 13:12 ` Victor Do Nascimento [this message]
2023-11-06 13:12 ` [PATCH 3/3] aarch64: Add LSE128 instructions Victor Do Nascimento
2023-11-07 11:08 ` [PATCH 0/3] aarch64: Add support for the Armv9.4-a LSE128 extension Nick Clifton
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20231106131301.2576862-3-victor.donascimento@arm.com \
--to=victor.donascimento@arm.com \
--cc=binutils@sourceware.org \
--cc=nickc@redhat.com \
--cc=richard.earnshaw@arm.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for read-only IMAP folder(s) and NNTP newsgroup(s).