[PATCH 3/3] aarch64: Add FEAT_ITE support

[Andrea Corallo <andrea.corallo@arm.com>]

This patch add support for FEAT_ITE "Instrumentation Extension" adding
the "trcit" instruction.

This is enabled by the +ite march flag.
---
 gas/config/tc-aarch64.c                    | 1 +
 gas/doc/c-aarch64.texi                     | 2 ++
 gas/testsuite/gas/aarch64/illegal-ite1-1.d | 3 +++
 gas/testsuite/gas/aarch64/illegal-ite1-1.l | 2 ++
 gas/testsuite/gas/aarch64/ite1.d           | 9 +++++++++
 gas/testsuite/gas/aarch64/ite1.s           | 4 ++++
 include/opcode/aarch64.h                   | 2 ++
 opcodes/aarch64-tbl.h                      | 8 ++++++++
 8 files changed, 31 insertions(+)
 create mode 100644 gas/testsuite/gas/aarch64/illegal-ite1-1.d
 create mode 100644 gas/testsuite/gas/aarch64/illegal-ite1-1.l
 create mode 100644 gas/testsuite/gas/aarch64/ite1.d
 create mode 100644 gas/testsuite/gas/aarch64/ite1.s

diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c
index 827e0436136..84c69a8eedf 100644
--- a/gas/config/tc-aarch64.c
+++ b/gas/config/tc-aarch64.c
@@ -10305,6 +10305,7 @@ static const struct aarch64_option_cpu_value_table aarch64_features[] = {
   {"gcs",		AARCH64_FEATURE (GCS), AARCH64_NO_FEATURES},
   {"prfmslc",		AARCH64_FEATURE (PRFMSLC), AARCH64_NO_FEATURES},
   {"rasv2",		AARCH64_FEATURE (RASv2), AARCH64_NO_FEATURES},
+  {"ite",		AARCH64_FEATURE (ITE), AARCH64_NO_FEATURES},
   {NULL,		AARCH64_NO_FEATURES, AARCH64_NO_FEATURES},
 };
 
diff --git a/gas/doc/c-aarch64.texi b/gas/doc/c-aarch64.texi
index 0624c4f0bb8..3c0aeeb6720 100644
--- a/gas/doc/c-aarch64.texi
+++ b/gas/doc/c-aarch64.texi
@@ -267,6 +267,8 @@ automatically cause those extensions to be disabled.
  @tab Enable the Reliability, Availability and Serviceability extension v2.
 @item @code{predres2} @tab ARMv8-A/Armv9-A @tab ARMv8.9-A/Armv9.4-A or later
  @tab Enable Prediction instructions.
+@item @code{ite} @tab N/A @tab no
+ @tab Enable TRCIT instruction.
 @end multitable
 
 @node AArch64 Syntax
diff --git a/gas/testsuite/gas/aarch64/illegal-ite1-1.d b/gas/testsuite/gas/aarch64/illegal-ite1-1.d
new file mode 100644
index 00000000000..99ef4d47d7b
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/illegal-ite1-1.d
@@ -0,0 +1,3 @@
+#as: -march=armv8-a
+#source: ite1.s
+#error_output: illegal-ite1-1.l
\ No newline at end of file
diff --git a/gas/testsuite/gas/aarch64/illegal-ite1-1.l b/gas/testsuite/gas/aarch64/illegal-ite1-1.l
new file mode 100644
index 00000000000..1e97c9147ee
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/illegal-ite1-1.l
@@ -0,0 +1,2 @@
+[^:]*: Assembler messages:
+[^:]*:[0-9]+: Error: selected processor does not support `trcit x1'
diff --git a/gas/testsuite/gas/aarch64/ite1.d b/gas/testsuite/gas/aarch64/ite1.d
new file mode 100644
index 00000000000..7c4b486ced8
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/ite1.d
@@ -0,0 +1,9 @@
+#as: -march=armv9.4-a+ite
+#objdump: -dr
+
+.*:     file format .*
+
+Disassembly of section \.text:
+
+0+ <.*>:
+.*:	d50b72e1 	trcit	x1
diff --git a/gas/testsuite/gas/aarch64/ite1.s b/gas/testsuite/gas/aarch64/ite1.s
new file mode 100644
index 00000000000..595ecf897f2
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/ite1.s
@@ -0,0 +1,4 @@
+/* File to test the +ite option.  */
+func:
+	trcit x1
+	
diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h
index ae6457597e5..fe046b9adfb 100644
--- a/include/opcode/aarch64.h
+++ b/include/opcode/aarch64.h
@@ -173,6 +173,8 @@ enum aarch64_feature_bit {
   AARCH64_FEATURE_RASv2,
   /* Speculation Prediction Restriction instructions.  */
   AARCH64_FEATURE_PREDRES2,
+  /* Instrumentation Extension.  */
+  AARCH64_FEATURE_ITE,
   DUMMY1,
   DUMMY2,
   DUMMY3,
diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h
index b64d94ab70f..ac21a563b3b 100644
--- a/opcodes/aarch64-tbl.h
+++ b/opcodes/aarch64-tbl.h
@@ -2582,6 +2582,8 @@ static const aarch64_feature_set aarch64_feature_prfmslc =
   AARCH64_FEATURE (PRFMSLC);
 static const aarch64_feature_set aarch64_feature_rasv2 =
   AARCH64_FEATURE (RASv2);
+static const aarch64_feature_set aarch64_feature_ite =
+  AARCH64_FEATURE (ITE);
 
 #define CORE		&aarch64_feature_v8
 #define FP		&aarch64_feature_fp
@@ -2645,6 +2647,7 @@ static const aarch64_feature_set aarch64_feature_rasv2 =
 #define GCS	  &aarch64_feature_gcs
 #define PRFMSLC  &aarch64_feature_prfmslc
 #define RASv2  &aarch64_feature_rasv2
+#define ITE	  &aarch64_feature_ite
 
 #define CORE_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS) \
   { NAME, OPCODE, MASK, CLASS, OP, CORE, OPS, QUALS, FLAGS, 0, 0, NULL }
@@ -2848,6 +2851,9 @@ static const aarch64_feature_set aarch64_feature_rasv2 =
 #define PREDRES2_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \
   { NAME, OPCODE, MASK, CLASS, 0, PREDRES2, OPS, QUALS, FLAGS, 0, 0, NULL }
 
+#define ITE_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \
+  { NAME, OPCODE, MASK, CLASS, 0, ITE, OPS, QUALS, FLAGS, 0, 0, NULL }
+
 const struct aarch64_opcode aarch64_opcode_table[] =
 {
   /* Add/subtract (with carry).  */
@@ -6105,6 +6111,8 @@ const struct aarch64_opcode aarch64_opcode_table[] =
      command-line flags.  */
   CORE_INSN ("clrbhb", 0xd50322df, 0xffffffff, ic_system, 0, OP0 (), {}, F_ALIAS),
 
+  ITE_INSN ("trcit", 0xd50b72e0, 0xffffffe0, ic_system, OP1 (Rt), QL_I1X, F_ALIAS),
+
   {0, 0, 0, 0, 0, 0, {}, {}, 0, 0, 0, NULL},
 };
 
-- 
2.25.1