From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from out30-113.freemail.mail.aliyun.com (out30-113.freemail.mail.aliyun.com [115.124.30.113]) by sourceware.org (Postfix) with ESMTPS id 10CB53858D38 for ; Fri, 10 Nov 2023 07:22:38 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 10CB53858D38 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=linux.alibaba.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=linux.alibaba.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 10CB53858D38 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=115.124.30.113 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1699600961; cv=none; b=hIqR1HEvFqzTmmiw8+O7vKkCylY4ZB/MgK9inDhBhCVcJExu8YI3mi87gpFj4OkUatN25rLmvnOlfXrKNN3Ls5p/C9XLWgST2jFOxA22uW2BNMcjO9S/DerdOYM03vM9gA0L/wk7StuKCSo+TWCCoplAnt4m24leT3oqpRYSmW0= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1699600961; c=relaxed/simple; bh=jta21Pnf/SAY9kRP1S4u4Tz4rSPwHpQF5BBtLJFjmPo=; h=From:To:Subject:Date:Message-Id:MIME-Version; b=r5xg4QUCRDpLONcvWaS5B+CFhO370/67SJVDvggXq9EOeLoZkObMlYQEQaQQMpN/zUk/abB0IqaHT+Z08iD+ok8Nr5atRQIF375eSgN19l9HA7eZwEPP/DpDqW2ErkK5kQeS2ZMr3lDUkrLnpeDSFQ1vvw6vz5z81aj+mUZiMJM= ARC-Authentication-Results: i=1; server2.sourceware.org X-Alimail-AntiSpam:AC=PASS;BC=-1|-1;BR=01201311R941e4;CH=green;DM=||false|;DS=||;FP=0|-1|-1|-1|0|-1|-1|-1;HT=ay29a033018046056;MF=jinma@linux.alibaba.com;NM=1;PH=DS;RN=6;SR=0;TI=SMTPD_---0Vw3jXbb_1699600954; Received: from localhost.localdomain(mailfrom:jinma@linux.alibaba.com fp:SMTPD_---0Vw3jXbb_1699600954) by smtp.aliyun-inc.com; Fri, 10 Nov 2023 15:22:35 +0800 From: Jin Ma To: binutils@sourceware.org, nelson@rivosinc.com Cc: christoph.muellner@vrull.eu, lifang_xia@linux.alibaba.com, jinma.contrib@gmail.com, Jin Ma Subject: [PATCH 03/12] RISC-V: Add configuration-setting instructions for T-Head VECTOR vendor extension Date: Fri, 10 Nov 2023 15:22:24 +0800 Message-Id: <20231110072224.1735-1-jinma@linux.alibaba.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20231110071759.1640-1-jinma@linux.alibaba.com> References: <20231110071759.1640-1-jinma@linux.alibaba.com> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-20.3 required=5.0 tests=BAYES_00,ENV_AND_HDR_SPF_MATCH,GIT_PATCH_0,KAM_DMARC_STATUS,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE,UNPARSEABLE_RELAY,USER_IN_DEF_SPF_WL autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: T-Head has a range of vendor-specific instructions. Therefore it makes sense to group them into smaller chunks in form of vendor extensions. This patch adds configuration-setting instructions for the "XTheadVector" extension. The 'th' prefix and the "XTheadVector" extension are documented in a PR for the RISC-V toolchain conventions ([1]). [1] https://github.com/riscv-non-isa/riscv-toolchain-conventions/pull/19 Co-developed-by: Lifang Xia Co-developed-by: Christoph Müllner gas/ChangeLog: * testsuite/gas/riscv/x-thead-vector.d: New test. * testsuite/gas/riscv/x-thead-vector.s: New test. include/ChangeLog: * opcode/riscv-opc.h (MATCH_TH_VSETVL): New. opcodes/ChangeLog: * riscv-opc.c: Likewise.. --- gas/testsuite/gas/riscv/x-thead-vector.d | 12 ++++++++++++ gas/testsuite/gas/riscv/x-thead-vector.s | 3 +++ include/opcode/riscv-opc.h | 5 +++++ opcodes/riscv-opc.c | 4 ++++ 4 files changed, 24 insertions(+) create mode 100644 gas/testsuite/gas/riscv/x-thead-vector.d diff --git a/gas/testsuite/gas/riscv/x-thead-vector.d b/gas/testsuite/gas/riscv/x-thead-vector.d new file mode 100644 index 00000000000..e509ed0971b --- /dev/null +++ b/gas/testsuite/gas/riscv/x-thead-vector.d @@ -0,0 +1,12 @@ +#as: -march=rv32if_xtheadvector +#objdump: -dr + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 <.text>: +[ ]+[0-9a-f]+:[ ]+80c5f557[ ]+th.vsetvl[ ]+a0,a1,a2 +[ ]+[0-9a-f]+:[ ]+0005f557[ ]+th.vsetvli[ ]+a0,a1,e8,m1,tu,mu +[ ]+[0-9a-f]+:[ ]+7ff5f557[ ]+th.vsetvli[ ]+a0,a1,2047 diff --git a/gas/testsuite/gas/riscv/x-thead-vector.s b/gas/testsuite/gas/riscv/x-thead-vector.s index e69de29bb2d..ffea0a6f9f9 100644 --- a/gas/testsuite/gas/riscv/x-thead-vector.s +++ b/gas/testsuite/gas/riscv/x-thead-vector.s @@ -0,0 +1,3 @@ + th.vsetvl a0, a1, a2 + th.vsetvli a0, a1, 0 + th.vsetvli a0, a1, 0x7ff diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h index ed29384e825..dc18dd9f04c 100644 --- a/include/opcode/riscv-opc.h +++ b/include/opcode/riscv-opc.h @@ -2648,6 +2648,11 @@ #define MASK_TH_SYNC_IS 0xffffffff #define MATCH_TH_SYNC_S 0x0190000b #define MASK_TH_SYNC_S 0xffffffff +/* Vendor-specific (T-Head) XTheadVector instructions. */ +#define MATCH_TH_VSETVL 0x80007057 +#define MASK_TH_VSETVL 0xfe00707f +#define MATCH_TH_VSETVLI 0x00007057 +#define MASK_TH_VSETVLI 0x8000707f /* Vendor-specific (Ventana Microsystems) XVentanaCondOps instructions */ #define MATCH_VT_MASKC 0x607b #define MASK_VT_MASKC 0xfe00707f diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c index 72d727cd77e..2fb7cf1e14a 100644 --- a/opcodes/riscv-opc.c +++ b/opcodes/riscv-opc.c @@ -2234,6 +2234,10 @@ const struct riscv_opcode riscv_opcodes[] = {"th.sync.is", 0, INSN_CLASS_XTHEADSYNC, "", MATCH_TH_SYNC_IS, MASK_TH_SYNC_IS, match_opcode, 0}, {"th.sync.s", 0, INSN_CLASS_XTHEADSYNC, "", MATCH_TH_SYNC_S, MASK_TH_SYNC_S, match_opcode, 0}, +/* Vendor-specific (T-Head) XTheadVector instructions. */ +{"th.vsetvl", 0, INSN_CLASS_XTHEADVECTOR, "d,s,t", MATCH_TH_VSETVL, MASK_TH_VSETVL, match_opcode, 0}, +{"th.vsetvli", 0, INSN_CLASS_XTHEADVECTOR, "d,s,Vc", MATCH_TH_VSETVLI, MASK_TH_VSETVLI, match_opcode, 0}, + /* Vendor-specific (Ventana Microsystems) XVentanaCondOps instructions */ {"vt.maskc", 64, INSN_CLASS_XVENTANACONDOPS, "d,s,t", MATCH_VT_MASKC, MASK_VT_MASKC, match_opcode, 0 }, {"vt.maskcn", 64, INSN_CLASS_XVENTANACONDOPS, "d,s,t", MATCH_VT_MASKCN, MASK_VT_MASKCN, match_opcode, 0 }, -- 2.17.1