From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from out30-100.freemail.mail.aliyun.com (out30-100.freemail.mail.aliyun.com [115.124.30.100]) by sourceware.org (Postfix) with ESMTPS id A32D43857017 for ; Fri, 10 Nov 2023 07:25:18 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org A32D43857017 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=linux.alibaba.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=linux.alibaba.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org A32D43857017 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=115.124.30.100 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1699601127; cv=none; b=mdWIj0Ila7MjEzkkTZ5mSzAMkQIwtFOorPwRlIlw8iw1X3sy1ptyjktqTNAntGCj06455lJGZMhHBmEZjnumzUXzK5gmEdpvH5tXzwo0GwSra2WnU6IqFjYrFK508RoTqXPzkpsgdHxBn/RXeRzeVKOzipWTWmb6nKOXNlppTg0= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1699601127; c=relaxed/simple; bh=S3XA5et8khOV6G1RJloRzpiGG4Wuz/LLZg+81uXfYJ4=; h=From:To:Subject:Date:Message-Id:MIME-Version; b=c5ftrBFaPhEZQ3nVZwP63pRGiX3RKnC2Gm4pzczT+P7FNblExggVWK74hyoGj6svaN3oMahn1Slwnsa/ujo2n1/tQ0pJ8DgvJFgvFdV9DO5fA/G+TMiP1GWVzYukRlCdN3QVA8mgmk8mqIQ0gmiI3BHTmwF9Jai/I3u1ip4ZjIA= ARC-Authentication-Results: i=1; server2.sourceware.org X-Alimail-AntiSpam:AC=PASS;BC=-1|-1;BR=01201311R201e4;CH=green;DM=||false|;DS=||;FP=0|-1|-1|-1|0|-1|-1|-1;HT=ay29a033018046060;MF=jinma@linux.alibaba.com;NM=1;PH=DS;RN=6;SR=0;TI=SMTPD_---0Vw3jBTV_1699601112; Received: from localhost.localdomain(mailfrom:jinma@linux.alibaba.com fp:SMTPD_---0Vw3jBTV_1699601112) by smtp.aliyun-inc.com; Fri, 10 Nov 2023 15:25:15 +0800 From: Jin Ma To: binutils@sourceware.org, nelson@rivosinc.com Cc: christoph.muellner@vrull.eu, lifang_xia@linux.alibaba.com, jinma.contrib@gmail.com, Jin Ma Subject: [PATCH 05/12] RISC-V: Add the sub-extension "XTheadZvlsseg" for T-Head VECTOR vendor extension Date: Fri, 10 Nov 2023 15:24:59 +0800 Message-Id: <20231110072459.1826-1-jinma@linux.alibaba.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20231110071759.1640-1-jinma@linux.alibaba.com> References: <20231110071759.1640-1-jinma@linux.alibaba.com> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-20.5 required=5.0 tests=BAYES_00,ENV_AND_HDR_SPF_MATCH,GIT_PATCH_0,KAM_DMARC_STATUS,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE,UNPARSEABLE_RELAY,USER_IN_DEF_SPF_WL autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: T-Head has a range of vendor-specific instructions. Therefore it makes sense to group them into smaller chunks in form of vendor extensions. This patch adds the sub-extension "XTheadZvlsseg" for the "XTheadVector" extension, and it provides load/store segment instructions for T-Head VECTOR vendor extension. The 'th' prefix and the "XTheadVector" extension are documented in a PR for the RISC-V toolchain conventions ([1]). [1] https://github.com/riscv-non-isa/riscv-toolchain-conventions/pull/19 Co-developed-by: Lifang Xia Co-developed-by: Christoph Müllner bfd/ChangeLog: * elfxx-riscv.c (riscv_multi_subset_supports): Add support for "XTheadZvlsseg" extensions. (riscv_multi_subset_supports_ext): Likewise. gas/ChangeLog: * testsuite/gas/riscv/x-thead-vector-zvlsseg.d: New test. * testsuite/gas/riscv/x-thead-vector-zvlsseg.s: New test. include/ChangeLog: * opcode/riscv-opc.h (MATCH_TH_VLSEG2BV): New. * opcode/riscv.h (enum riscv_insn_class): Add insn class. opcodes/ChangeLog: * riscv-opc.c: Likewise. --- bfd/elfxx-riscv.c | 6 + gas/doc/c-riscv.texi | 6 + .../gas/riscv/x-thead-vector-zvlsseg.d | 849 +++++++++++++++++ .../gas/riscv/x-thead-vector-zvlsseg.s | 867 ++++++++++++++++++ include/opcode/riscv-opc.h | 560 +++++++++++ include/opcode/riscv.h | 1 + opcodes/riscv-opc.c | 280 ++++++ 7 files changed, 2569 insertions(+) create mode 100644 gas/testsuite/gas/riscv/x-thead-vector-zvlsseg.d create mode 100644 gas/testsuite/gas/riscv/x-thead-vector-zvlsseg.s diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c index e2c3ffe4b4f..2d2ab040674 100644 --- a/bfd/elfxx-riscv.c +++ b/bfd/elfxx-riscv.c @@ -1199,6 +1199,7 @@ static struct riscv_implicit_subset riscv_implicit_subsets[] = {"ssstateen", "zicsr", check_implicit_always}, {"sstc", "zicsr", check_implicit_always}, {"svadu", "zicsr", check_implicit_always}, + {"xtheadvector", "xtheadzvlsseg", check_implicit_always}, {NULL, NULL, NULL} }; @@ -1374,6 +1375,7 @@ static struct riscv_supported_ext riscv_supported_vendor_x_ext[] = {"xtheadmempair", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"xtheadsync", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"xtheadvector", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"xtheadzvlsseg", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"xventanacondops", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {NULL, 0, 0, 0, 0} }; @@ -2590,6 +2592,8 @@ riscv_multi_subset_supports (riscv_parse_subset_t *rps, return riscv_subset_supports (rps, "xtheadsync"); case INSN_CLASS_XTHEADVECTOR: return riscv_subset_supports (rps, "xtheadvector"); + case INSN_CLASS_XTHEADZVLSSEG: + return riscv_subset_supports (rps, "xtheadzvlsseg"); case INSN_CLASS_XVENTANACONDOPS: return riscv_subset_supports (rps, "xventanacondops"); default: @@ -2836,6 +2840,8 @@ riscv_multi_subset_supports_ext (riscv_parse_subset_t *rps, return "xtheadsync"; case INSN_CLASS_XTHEADVECTOR: return "xtheadvector"; + case INSN_CLASS_XTHEADZVLSSEG: + return "xtheadzvlsseg"; default: rps->error_handler (_("internal: unreachable INSN_CLASS_*")); diff --git a/gas/doc/c-riscv.texi b/gas/doc/c-riscv.texi index a7c9420bd86..e47200faaf6 100644 --- a/gas/doc/c-riscv.texi +++ b/gas/doc/c-riscv.texi @@ -819,6 +819,12 @@ The XTheadVector extension provides instructions for thead vector. It is documented in @url{https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.3.0/xthead-2023-11-10-2.3.0.pdf}. +@item XTheadZvlsseg +The XTheadZvlsseg extension is a subextension of the XTheadVector extension, +and it provides load/store segment instructions for thead vector. + +It is documented in @url{https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.3.0/xthead-2023-11-10-2.3.0.pdf}. + @item XVentanaCondOps XVentanaCondOps extension provides instructions for branchless sequences that perform conditional arithmetic, conditional diff --git a/gas/testsuite/gas/riscv/x-thead-vector-zvlsseg.d b/gas/testsuite/gas/riscv/x-thead-vector-zvlsseg.d new file mode 100644 index 00000000000..0821b040a94 --- /dev/null +++ b/gas/testsuite/gas/riscv/x-thead-vector-zvlsseg.d @@ -0,0 +1,849 @@ +#as: -march=rv32if_xtheadvector_xtheadzvlsseg +#objdump: -dr + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 <.text>: +[ ]+[0-9a-f]+:[ ]+32050207[ ]+th.vlseg2b.v[ ]+v4,\(a0\) +[ ]+[0-9a-f]+:[ ]+32050207[ ]+th.vlseg2b.v[ ]+v4,\(a0\) +[ ]+[0-9a-f]+:[ ]+30050207[ ]+th.vlseg2b.v[ ]+v4,\(a0\),v0.t +[ ]+[0-9a-f]+:[ ]+32055207[ ]+th.vlseg2h.v[ ]+v4,\(a0\) +[ ]+[0-9a-f]+:[ ]+32055207[ ]+th.vlseg2h.v[ ]+v4,\(a0\) +[ ]+[0-9a-f]+:[ ]+30055207[ ]+th.vlseg2h.v[ ]+v4,\(a0\),v0.t +[ ]+[0-9a-f]+:[ ]+32056207[ ]+th.vlseg2w.v[ ]+v4,\(a0\) +[ ]+[0-9a-f]+:[ ]+32056207[ ]+th.vlseg2w.v[ ]+v4,\(a0\) +[ ]+[0-9a-f]+:[ ]+30056207[ ]+th.vlseg2w.v[ ]+v4,\(a0\),v0.t +[ ]+[0-9a-f]+:[ ]+22050207[ ]+th.vlseg2bu.v[ ]+v4,\(a0\) +[ ]+[0-9a-f]+:[ ]+22050207[ ]+th.vlseg2bu.v[ ]+v4,\(a0\) +[ ]+[0-9a-f]+:[ ]+20050207[ ]+th.vlseg2bu.v[ ]+v4,\(a0\),v0.t +[ ]+[0-9a-f]+:[ ]+22055207[ ]+th.vlseg2hu.v[ ]+v4,\(a0\) +[ ]+[0-9a-f]+:[ ]+22055207[ ]+th.vlseg2hu.v[ ]+v4,\(a0\) +[ ]+[0-9a-f]+:[ ]+20055207[ ]+th.vlseg2hu.v[ ]+v4,\(a0\),v0.t +[ ]+[0-9a-f]+:[ ]+22056207[ ]+th.vlseg2wu.v[ ]+v4,\(a0\) +[ ]+[0-9a-f]+:[ ]+22056207[ ]+th.vlseg2wu.v[ ]+v4,\(a0\) +[ ]+[0-9a-f]+:[ ]+20056207[ ]+th.vlseg2wu.v[ ]+v4,\(a0\),v0.t +[ ]+[0-9a-f]+:[ ]+22057207[ ]+th.vlseg2e.v[ ]+v4,\(a0\) +[ ]+[0-9a-f]+:[ ]+22057207[ ]+th.vlseg2e.v[ ]+v4,\(a0\) +[ ]+[0-9a-f]+:[ ]+20057207[ ]+th.vlseg2e.v[ ]+v4,\(a0\),v0.t +[ ]+[0-9a-f]+:[ ]+22050227[ ]+th.vsseg2b.v[ ]+v4,\(a0\) +[ ]+[0-9a-f]+:[ ]+22050227[ ]+th.vsseg2b.v[ ]+v4,\(a0\) +[ ]+[0-9a-f]+:[ ]+20050227[ ]+th.vsseg2b.v[ ]+v4,\(a0\),v0.t +[ ]+[0-9a-f]+:[ ]+22055227[ ]+th.vsseg2h.v[ ]+v4,\(a0\) +[ ]+[0-9a-f]+:[ ]+22055227[ ]+th.vsseg2h.v[ ]+v4,\(a0\) +[ ]+[0-9a-f]+:[ ]+20055227[ ]+th.vsseg2h.v[ ]+v4,\(a0\),v0.t +[ ]+[0-9a-f]+:[ ]+22056227[ ]+th.vsseg2w.v[ ]+v4,\(a0\) +[ ]+[0-9a-f]+:[ ]+22056227[ ]+th.vsseg2w.v[ ]+v4,\(a0\) +[ ]+[0-9a-f]+:[ ]+20056227[ ]+th.vsseg2w.v[ ]+v4,\(a0\),v0.t +[ ]+[0-9a-f]+:[ ]+22057227[ ]+th.vsseg2e.v[ ]+v4,\(a0\) +[ ]+[0-9a-f]+:[ ]+22057227[ ]+th.vsseg2e.v[ ]+v4,\(a0\) +[ ]+[0-9a-f]+:[ ]+20057227[ ]+th.vsseg2e.v[ ]+v4,\(a0\),v0.t +[ ]+[0-9a-f]+:[ ]+52050207[ ]+th.vlseg3b.v[ ]+v4,\(a0\) +[ ]+[0-9a-f]+:[ ]+52050207[ ]+th.vlseg3b.v[ ]+v4,\(a0\) +[ ]+[0-9a-f]+:[ ]+50050207[ ]+th.vlseg3b.v[ ]+v4,\(a0\),v0.t +[ ]+[0-9a-f]+:[ ]+52055207[ ]+th.vlseg3h.v[ ]+v4,\(a0\) +[ ]+[0-9a-f]+:[ ]+52055207[ ]+th.vlseg3h.v[ ]+v4,\(a0\) +[ ]+[0-9a-f]+:[ ]+50055207[ ]+th.vlseg3h.v[ ]+v4,\(a0\),v0.t +[ ]+[0-9a-f]+:[ ]+52056207[ ]+th.vlseg3w.v[ ]+v4,\(a0\) +[ ]+[0-9a-f]+:[ ]+52056207[ ]+th.vlseg3w.v[ ]+v4,\(a0\) +[ ]+[0-9a-f]+:[ ]+50056207[ ]+th.vlseg3w.v[ ]+v4,\(a0\),v0.t +[ ]+[0-9a-f]+:[ ]+42050207[ ]+th.vlseg3bu.v[ ]+v4,\(a0\) +[ ]+[0-9a-f]+:[ ]+42050207[ ]+th.vlseg3bu.v[ ]+v4,\(a0\) +[ ]+[0-9a-f]+:[ ]+40050207[ ]+th.vlseg3bu.v[ ]+v4,\(a0\),v0.t +[ ]+[0-9a-f]+:[ ]+42055207[ ]+th.vlseg3hu.v[ ]+v4,\(a0\) +[ ]+[0-9a-f]+:[ ]+42055207[ ]+th.vlseg3hu.v[ ]+v4,\(a0\) +[ ]+[0-9a-f]+:[ ]+40055207[ ]+th.vlseg3hu.v[ ]+v4,\(a0\),v0.t +[ ]+[0-9a-f]+:[ ]+42056207[ ]+th.vlseg3wu.v[ ]+v4,\(a0\) +[ ]+[0-9a-f]+:[ ]+42056207[ ]+th.vlseg3wu.v[ ]+v4,\(a0\) +[ ]+[0-9a-f]+:[ ]+40056207[ ]+th.vlseg3wu.v[ ]+v4,\(a0\),v0.t +[ ]+[0-9a-f]+:[ ]+42057207[ ]+th.vlseg3e.v[ ]+v4,\(a0\) +[ ]+[0-9a-f]+:[ ]+42057207[ ]+th.vlseg3e.v[ ]+v4,\(a0\) +[ ]+[0-9a-f]+:[ ]+40057207[ ]+th.vlseg3e.v[ ]+v4,\(a0\),v0.t +[ ]+[0-9a-f]+:[ ]+42050227[ ]+th.vsseg3b.v[ ]+v4,\(a0\) +[ ]+[0-9a-f]+:[ ]+42050227[ ]+th.vsseg3b.v[ ]+v4,\(a0\) +[ ]+[0-9a-f]+:[ ]+40050227[ ]+th.vsseg3b.v[ ]+v4,\(a0\),v0.t +[ ]+[0-9a-f]+:[ ]+42055227[ ]+th.vsseg3h.v[ ]+v4,\(a0\) +[ ]+[0-9a-f]+:[ ]+42055227[ ]+th.vsseg3h.v[ ]+v4,\(a0\) +[ ]+[0-9a-f]+:[ ]+40055227[ ]+th.vsseg3h.v[ ]+v4,\(a0\),v0.t +[ ]+[0-9a-f]+:[ ]+42056227[ ]+th.vsseg3w.v[ ]+v4,\(a0\) +[ ]+[0-9a-f]+:[ ]+42056227[ ]+th.vsseg3w.v[ ]+v4,\(a0\) +[ ]+[0-9a-f]+:[ ]+40056227[ ]+th.vsseg3w.v[ ]+v4,\(a0\),v0.t +[ ]+[0-9a-f]+:[ ]+42057227[ ]+th.vsseg3e.v[ ]+v4,\(a0\) +[ ]+[0-9a-f]+:[ ]+42057227[ ]+th.vsseg3e.v[ ]+v4,\(a0\) +[ ]+[0-9a-f]+:[ ]+40057227[ ]+th.vsseg3e.v[ ]+v4,\(a0\),v0.t +[ ]+[0-9a-f]+:[ ]+72050207[ ]+th.vlseg4b.v[ ]+v4,\(a0\) +[ ]+[0-9a-f]+:[ ]+72050207[ ]+th.vlseg4b.v[ ]+v4,\(a0\) +[ ]+[0-9a-f]+:[ ]+70050207[ ]+th.vlseg4b.v[ ]+v4,\(a0\),v0.t +[ ]+[0-9a-f]+:[ ]+72055207[ ]+th.vlseg4h.v[ ]+v4,\(a0\) +[ ]+[0-9a-f]+:[ ]+72055207[ ]+th.vlseg4h.v[ ]+v4,\(a0\) +[ ]+[0-9a-f]+:[ ]+70055207[ ]+th.vlseg4h.v[ ]+v4,\(a0\),v0.t +[ ]+[0-9a-f]+:[ ]+72056207[ ]+th.vlseg4w.v[ ]+v4,\(a0\) +[ ]+[0-9a-f]+:[ ]+72056207[ ]+th.vlseg4w.v[ ]+v4,\(a0\) +[ ]+[0-9a-f]+:[ ]+70056207[ ]+th.vlseg4w.v[ ]+v4,\(a0\),v0.t +[ ]+[0-9a-f]+:[ ]+62050207[ ]+th.vlseg4bu.v[ ]+v4,\(a0\) +[ ]+[0-9a-f]+:[ ]+62050207[ ]+th.vlseg4bu.v[ ]+v4,\(a0\) +[ ]+[0-9a-f]+:[ ]+60050207[ ]+th.vlseg4bu.v[ ]+v4,\(a0\),v0.t +[ ]+[0-9a-f]+:[ ]+62055207[ ]+th.vlseg4hu.v[ ]+v4,\(a0\) +[ ]+[0-9a-f]+:[ ]+62055207[ ]+th.vlseg4hu.v[ ]+v4,\(a0\) +[ ]+[0-9a-f]+:[ ]+60055207[ ]+th.vlseg4hu.v[ ]+v4,\(a0\),v0.t +[ ]+[0-9a-f]+:[ ]+62056207[ ]+th.vlseg4wu.v[ ]+v4,\(a0\) +[ ]+[0-9a-f]+:[ ]+62056207[ ]+th.vlseg4wu.v[ ]+v4,\(a0\) +[ ]+[0-9a-f]+:[ ]+60056207[ ]+th.vlseg4wu.v[ ]+v4,\(a0\),v0.t +[ ]+[0-9a-f]+:[ ]+62057207[ ]+th.vlseg4e.v[ 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th.vlseg2e.v v4, 0(a0) + th.vlseg2e.v v4, (a0), v0.t + th.vsseg2b.v v4, (a0) + th.vsseg2b.v v4, 0(a0) + th.vsseg2b.v v4, (a0), v0.t + th.vsseg2h.v v4, (a0) + th.vsseg2h.v v4, 0(a0) + th.vsseg2h.v v4, (a0), v0.t + th.vsseg2w.v v4, (a0) + th.vsseg2w.v v4, 0(a0) + th.vsseg2w.v v4, (a0), v0.t + th.vsseg2e.v v4, (a0) + th.vsseg2e.v v4, 0(a0) + th.vsseg2e.v v4, (a0), v0.t + + th.vlseg3b.v v4, (a0) + th.vlseg3b.v v4, 0(a0) + th.vlseg3b.v v4, (a0), v0.t + th.vlseg3h.v v4, (a0) + th.vlseg3h.v v4, 0(a0) + th.vlseg3h.v v4, (a0), v0.t + th.vlseg3w.v v4, (a0) + th.vlseg3w.v v4, 0(a0) + th.vlseg3w.v v4, (a0), v0.t + th.vlseg3bu.v v4, (a0) + th.vlseg3bu.v v4, 0(a0) + th.vlseg3bu.v v4, (a0), v0.t + th.vlseg3hu.v v4, (a0) + th.vlseg3hu.v v4, 0(a0) + th.vlseg3hu.v v4, (a0), v0.t + th.vlseg3wu.v v4, (a0) + th.vlseg3wu.v v4, 0(a0) + th.vlseg3wu.v v4, (a0), v0.t + th.vlseg3e.v v4, (a0) + th.vlseg3e.v v4, 0(a0) + th.vlseg3e.v v4, (a0), v0.t + th.vsseg3b.v v4, (a0) + th.vsseg3b.v v4, 0(a0) + th.vsseg3b.v v4, (a0), v0.t + th.vsseg3h.v v4, (a0) + th.vsseg3h.v v4, 0(a0) + th.vsseg3h.v v4, (a0), v0.t + th.vsseg3w.v v4, (a0) + th.vsseg3w.v v4, 0(a0) + th.vsseg3w.v v4, (a0), v0.t + th.vsseg3e.v v4, (a0) + th.vsseg3e.v v4, 0(a0) + th.vsseg3e.v v4, (a0), v0.t + + th.vlseg4b.v v4, (a0) + th.vlseg4b.v v4, 0(a0) + th.vlseg4b.v v4, (a0), v0.t + th.vlseg4h.v v4, (a0) + th.vlseg4h.v v4, 0(a0) + th.vlseg4h.v v4, (a0), v0.t + th.vlseg4w.v v4, (a0) + th.vlseg4w.v v4, 0(a0) + th.vlseg4w.v v4, (a0), v0.t + th.vlseg4bu.v v4, (a0) + th.vlseg4bu.v v4, 0(a0) + th.vlseg4bu.v v4, (a0), v0.t + th.vlseg4hu.v v4, (a0) + th.vlseg4hu.v v4, 0(a0) + th.vlseg4hu.v v4, (a0), v0.t + th.vlseg4wu.v v4, (a0) + th.vlseg4wu.v v4, 0(a0) + th.vlseg4wu.v v4, (a0), v0.t + th.vlseg4e.v v4, (a0) + th.vlseg4e.v v4, 0(a0) + th.vlseg4e.v v4, (a0), v0.t + th.vsseg4b.v v4, (a0) + th.vsseg4b.v v4, 0(a0) + th.vsseg4b.v v4, (a0), v0.t + th.vsseg4h.v v4, (a0) + th.vsseg4h.v v4, 0(a0) + th.vsseg4h.v v4, (a0), v0.t + th.vsseg4w.v v4, (a0) + th.vsseg4w.v v4, 0(a0) + th.vsseg4w.v v4, (a0), v0.t + th.vsseg4e.v v4, (a0) + th.vsseg4e.v v4, 0(a0) + th.vsseg4e.v v4, (a0), v0.t + + th.vlseg5b.v v4, (a0) + th.vlseg5b.v v4, 0(a0) + th.vlseg5b.v v4, (a0), v0.t + th.vlseg5h.v v4, (a0) + th.vlseg5h.v v4, 0(a0) + th.vlseg5h.v v4, (a0), v0.t + th.vlseg5w.v v4, (a0) + th.vlseg5w.v v4, 0(a0) + th.vlseg5w.v v4, (a0), v0.t + th.vlseg5bu.v v4, (a0) + th.vlseg5bu.v v4, 0(a0) + th.vlseg5bu.v v4, (a0), v0.t + th.vlseg5hu.v v4, (a0) + th.vlseg5hu.v v4, 0(a0) + th.vlseg5hu.v v4, (a0), v0.t + th.vlseg5wu.v v4, (a0) + th.vlseg5wu.v v4, 0(a0) + th.vlseg5wu.v v4, (a0), v0.t + th.vlseg5e.v v4, (a0) + th.vlseg5e.v v4, 0(a0) + th.vlseg5e.v v4, (a0), v0.t + th.vsseg5b.v v4, (a0) + th.vsseg5b.v v4, 0(a0) + th.vsseg5b.v v4, (a0), v0.t + th.vsseg5h.v v4, (a0) + th.vsseg5h.v v4, 0(a0) + th.vsseg5h.v v4, (a0), v0.t + th.vsseg5w.v v4, (a0) + th.vsseg5w.v v4, 0(a0) + th.vsseg5w.v v4, (a0), v0.t + th.vsseg5e.v v4, (a0) + th.vsseg5e.v v4, 0(a0) + th.vsseg5e.v v4, (a0), v0.t + + th.vlseg6b.v v4, (a0) + th.vlseg6b.v v4, 0(a0) + th.vlseg6b.v v4, (a0), v0.t + th.vlseg6h.v v4, (a0) + th.vlseg6h.v v4, 0(a0) + th.vlseg6h.v v4, (a0), v0.t + th.vlseg6w.v v4, (a0) + th.vlseg6w.v v4, 0(a0) + th.vlseg6w.v v4, (a0), v0.t + th.vlseg6bu.v v4, (a0) + th.vlseg6bu.v v4, 0(a0) + th.vlseg6bu.v v4, (a0), v0.t + th.vlseg6hu.v v4, (a0) + th.vlseg6hu.v v4, 0(a0) + th.vlseg6hu.v v4, (a0), v0.t + th.vlseg6wu.v v4, (a0) + th.vlseg6wu.v v4, 0(a0) + th.vlseg6wu.v v4, (a0), v0.t + th.vlseg6e.v v4, (a0) + th.vlseg6e.v v4, 0(a0) + th.vlseg6e.v v4, (a0), v0.t + th.vsseg6b.v v4, (a0) + th.vsseg6b.v v4, 0(a0) + th.vsseg6b.v v4, (a0), v0.t + th.vsseg6h.v v4, (a0) + th.vsseg6h.v v4, 0(a0) + th.vsseg6h.v v4, (a0), v0.t + th.vsseg6w.v v4, (a0) + th.vsseg6w.v v4, 0(a0) + th.vsseg6w.v v4, (a0), v0.t + th.vsseg6e.v v4, (a0) + th.vsseg6e.v v4, 0(a0) + th.vsseg6e.v v4, (a0), v0.t + + th.vlseg7b.v v4, (a0) + th.vlseg7b.v v4, 0(a0) + th.vlseg7b.v v4, (a0), v0.t + th.vlseg7h.v v4, (a0) + th.vlseg7h.v v4, 0(a0) + th.vlseg7h.v v4, (a0), v0.t + th.vlseg7w.v v4, (a0) + th.vlseg7w.v v4, 0(a0) + th.vlseg7w.v v4, (a0), v0.t + th.vlseg7bu.v v4, (a0) + th.vlseg7bu.v v4, 0(a0) + th.vlseg7bu.v v4, (a0), v0.t + th.vlseg7hu.v v4, (a0) + th.vlseg7hu.v v4, 0(a0) + th.vlseg7hu.v v4, (a0), v0.t + th.vlseg7wu.v v4, (a0) + th.vlseg7wu.v v4, 0(a0) + th.vlseg7wu.v v4, (a0), v0.t + th.vlseg7e.v v4, (a0) + th.vlseg7e.v v4, 0(a0) + th.vlseg7e.v v4, (a0), v0.t + th.vsseg7b.v v4, (a0) + th.vsseg7b.v v4, 0(a0) + th.vsseg7b.v v4, (a0), v0.t + th.vsseg7h.v v4, (a0) + th.vsseg7h.v v4, 0(a0) + th.vsseg7h.v v4, (a0), v0.t + th.vsseg7w.v v4, (a0) + th.vsseg7w.v v4, 0(a0) + th.vsseg7w.v v4, (a0), v0.t + th.vsseg7e.v v4, (a0) + th.vsseg7e.v v4, 0(a0) + th.vsseg7e.v v4, (a0), v0.t + + th.vlseg8b.v v4, (a0) + th.vlseg8b.v v4, 0(a0) + th.vlseg8b.v v4, (a0), v0.t + th.vlseg8h.v v4, (a0) + th.vlseg8h.v v4, 0(a0) + th.vlseg8h.v v4, (a0), v0.t + th.vlseg8w.v v4, (a0) + th.vlseg8w.v v4, 0(a0) + th.vlseg8w.v v4, (a0), v0.t + th.vlseg8bu.v v4, (a0) + th.vlseg8bu.v v4, 0(a0) + th.vlseg8bu.v v4, (a0), v0.t + th.vlseg8hu.v v4, (a0) + th.vlseg8hu.v v4, 0(a0) + th.vlseg8hu.v v4, (a0), v0.t + th.vlseg8wu.v v4, (a0) + th.vlseg8wu.v v4, 0(a0) + th.vlseg8wu.v v4, (a0), v0.t + th.vlseg8e.v v4, (a0) + th.vlseg8e.v v4, 0(a0) + th.vlseg8e.v v4, (a0), v0.t + th.vsseg8b.v v4, (a0) + th.vsseg8b.v v4, 0(a0) + th.vsseg8b.v v4, (a0), v0.t + th.vsseg8h.v v4, (a0) + th.vsseg8h.v v4, 0(a0) + th.vsseg8h.v v4, (a0), v0.t + th.vsseg8w.v v4, (a0) + th.vsseg8w.v v4, 0(a0) + th.vsseg8w.v v4, (a0), v0.t + th.vsseg8e.v v4, (a0) + th.vsseg8e.v v4, 0(a0) + th.vsseg8e.v v4, (a0), v0.t + + th.vlsseg2b.v v4, (a0), a1 + th.vlsseg2b.v v4, 0(a0), a1 + th.vlsseg2b.v v4, (a0), a1, v0.t + th.vlsseg2h.v v4, (a0), a1 + th.vlsseg2h.v v4, 0(a0), a1 + th.vlsseg2h.v v4, (a0), a1, v0.t + th.vlsseg2w.v v4, (a0), a1 + th.vlsseg2w.v v4, 0(a0), a1 + th.vlsseg2w.v v4, (a0), a1, v0.t + th.vlsseg2bu.v v4, (a0), a1 + th.vlsseg2bu.v v4, 0(a0), a1 + th.vlsseg2bu.v v4, (a0), a1, v0.t + th.vlsseg2hu.v v4, (a0), a1 + th.vlsseg2hu.v v4, 0(a0), a1 + th.vlsseg2hu.v v4, (a0), a1, v0.t + th.vlsseg2wu.v v4, (a0), a1 + th.vlsseg2wu.v v4, 0(a0), a1 + th.vlsseg2wu.v v4, (a0), a1, v0.t + th.vlsseg2e.v v4, (a0), a1 + th.vlsseg2e.v v4, 0(a0), a1 + th.vlsseg2e.v v4, (a0), a1, v0.t + th.vssseg2b.v v4, (a0), a1 + th.vssseg2b.v v4, 0(a0), a1 + th.vssseg2b.v v4, (a0), a1, v0.t + th.vssseg2h.v v4, (a0), a1 + th.vssseg2h.v v4, 0(a0), a1 + th.vssseg2h.v v4, (a0), a1, v0.t + th.vssseg2w.v v4, (a0), a1 + th.vssseg2w.v v4, 0(a0), a1 + th.vssseg2w.v v4, (a0), a1, v0.t + th.vssseg2e.v v4, (a0), a1 + th.vssseg2e.v v4, 0(a0), a1 + th.vssseg2e.v v4, (a0), a1, v0.t + + th.vlsseg3b.v v4, (a0), a1 + th.vlsseg3b.v v4, 0(a0), a1 + th.vlsseg3b.v v4, (a0), a1, v0.t + th.vlsseg3h.v v4, (a0), a1 + th.vlsseg3h.v v4, 0(a0), a1 + th.vlsseg3h.v v4, (a0), a1, v0.t + th.vlsseg3w.v v4, (a0), a1 + th.vlsseg3w.v v4, 0(a0), a1 + th.vlsseg3w.v v4, (a0), a1, v0.t + th.vlsseg3bu.v v4, (a0), a1 + th.vlsseg3bu.v v4, 0(a0), a1 + th.vlsseg3bu.v v4, (a0), a1, v0.t + th.vlsseg3hu.v v4, (a0), a1 + th.vlsseg3hu.v v4, 0(a0), a1 + th.vlsseg3hu.v v4, (a0), a1, v0.t + th.vlsseg3wu.v v4, (a0), a1 + th.vlsseg3wu.v v4, 0(a0), a1 + th.vlsseg3wu.v v4, (a0), a1, v0.t + th.vlsseg3e.v v4, (a0), a1 + th.vlsseg3e.v v4, 0(a0), a1 + th.vlsseg3e.v v4, (a0), a1, v0.t + th.vssseg3b.v v4, (a0), a1 + th.vssseg3b.v v4, 0(a0), a1 + th.vssseg3b.v v4, (a0), a1, v0.t + th.vssseg3h.v v4, (a0), a1 + th.vssseg3h.v v4, 0(a0), a1 + th.vssseg3h.v v4, (a0), a1, v0.t + th.vssseg3w.v v4, (a0), a1 + th.vssseg3w.v v4, 0(a0), a1 + th.vssseg3w.v v4, (a0), a1, v0.t + th.vssseg3e.v v4, (a0), a1 + th.vssseg3e.v v4, 0(a0), a1 + th.vssseg3e.v v4, (a0), a1, v0.t + + th.vlsseg4b.v v4, (a0), a1 + th.vlsseg4b.v v4, 0(a0), a1 + th.vlsseg4b.v v4, (a0), a1, v0.t + th.vlsseg4h.v v4, (a0), a1 + th.vlsseg4h.v v4, 0(a0), a1 + th.vlsseg4h.v v4, (a0), a1, v0.t + th.vlsseg4w.v v4, (a0), a1 + th.vlsseg4w.v v4, 0(a0), a1 + th.vlsseg4w.v v4, (a0), a1, v0.t + th.vlsseg4bu.v v4, (a0), a1 + th.vlsseg4bu.v v4, 0(a0), a1 + th.vlsseg4bu.v v4, (a0), a1, v0.t + th.vlsseg4hu.v v4, (a0), a1 + th.vlsseg4hu.v v4, 0(a0), a1 + th.vlsseg4hu.v v4, (a0), a1, v0.t + th.vlsseg4wu.v v4, (a0), a1 + th.vlsseg4wu.v v4, 0(a0), a1 + th.vlsseg4wu.v v4, (a0), a1, v0.t + th.vlsseg4e.v v4, (a0), a1 + th.vlsseg4e.v v4, 0(a0), a1 + th.vlsseg4e.v v4, (a0), a1, v0.t + th.vssseg4b.v v4, (a0), a1 + th.vssseg4b.v v4, 0(a0), a1 + th.vssseg4b.v v4, (a0), a1, v0.t + th.vssseg4h.v v4, (a0), a1 + th.vssseg4h.v v4, 0(a0), a1 + th.vssseg4h.v v4, (a0), a1, v0.t + th.vssseg4w.v v4, (a0), a1 + th.vssseg4w.v v4, 0(a0), a1 + th.vssseg4w.v v4, (a0), a1, v0.t + th.vssseg4e.v v4, (a0), a1 + th.vssseg4e.v v4, 0(a0), a1 + th.vssseg4e.v v4, (a0), a1, v0.t + + th.vlsseg5b.v v4, (a0), a1 + th.vlsseg5b.v v4, 0(a0), a1 + th.vlsseg5b.v v4, (a0), a1, v0.t + th.vlsseg5h.v v4, (a0), a1 + th.vlsseg5h.v v4, 0(a0), a1 + th.vlsseg5h.v v4, (a0), a1, v0.t + th.vlsseg5w.v v4, (a0), a1 + th.vlsseg5w.v v4, 0(a0), a1 + th.vlsseg5w.v v4, (a0), a1, v0.t + th.vlsseg5bu.v v4, (a0), a1 + th.vlsseg5bu.v v4, 0(a0), a1 + th.vlsseg5bu.v v4, (a0), a1, v0.t + th.vlsseg5hu.v v4, (a0), a1 + th.vlsseg5hu.v v4, 0(a0), a1 + th.vlsseg5hu.v v4, (a0), a1, v0.t + th.vlsseg5wu.v v4, (a0), a1 + th.vlsseg5wu.v v4, 0(a0), a1 + th.vlsseg5wu.v v4, (a0), a1, v0.t + th.vlsseg5e.v v4, (a0), a1 + th.vlsseg5e.v v4, 0(a0), a1 + th.vlsseg5e.v v4, (a0), a1, v0.t + th.vssseg5b.v v4, (a0), a1 + th.vssseg5b.v v4, 0(a0), a1 + th.vssseg5b.v v4, (a0), a1, v0.t + th.vssseg5h.v v4, (a0), a1 + th.vssseg5h.v v4, 0(a0), a1 + th.vssseg5h.v v4, (a0), a1, v0.t + th.vssseg5w.v v4, (a0), a1 + th.vssseg5w.v v4, 0(a0), a1 + th.vssseg5w.v v4, (a0), a1, v0.t + th.vssseg5e.v v4, (a0), a1 + th.vssseg5e.v v4, 0(a0), a1 + th.vssseg5e.v v4, (a0), a1, v0.t + + th.vlsseg6b.v v4, (a0), a1 + th.vlsseg6b.v v4, 0(a0), a1 + th.vlsseg6b.v v4, (a0), a1, v0.t + th.vlsseg6h.v v4, (a0), a1 + th.vlsseg6h.v v4, 0(a0), a1 + th.vlsseg6h.v v4, (a0), a1, v0.t + th.vlsseg6w.v v4, (a0), a1 + th.vlsseg6w.v v4, 0(a0), a1 + th.vlsseg6w.v v4, (a0), a1, v0.t + th.vlsseg6bu.v v4, (a0), a1 + th.vlsseg6bu.v v4, 0(a0), a1 + th.vlsseg6bu.v v4, (a0), a1, v0.t + th.vlsseg6hu.v v4, (a0), a1 + th.vlsseg6hu.v v4, 0(a0), a1 + th.vlsseg6hu.v v4, (a0), a1, v0.t + th.vlsseg6wu.v v4, (a0), a1 + th.vlsseg6wu.v v4, 0(a0), a1 + th.vlsseg6wu.v v4, (a0), a1, v0.t + th.vlsseg6e.v v4, (a0), a1 + th.vlsseg6e.v v4, 0(a0), a1 + th.vlsseg6e.v v4, (a0), a1, v0.t + th.vssseg6b.v v4, (a0), a1 + th.vssseg6b.v v4, 0(a0), a1 + th.vssseg6b.v v4, (a0), a1, v0.t + th.vssseg6h.v v4, (a0), a1 + th.vssseg6h.v v4, 0(a0), a1 + th.vssseg6h.v v4, (a0), a1, v0.t + th.vssseg6w.v v4, (a0), a1 + th.vssseg6w.v v4, 0(a0), a1 + th.vssseg6w.v v4, (a0), a1, v0.t + th.vssseg6e.v v4, (a0), a1 + th.vssseg6e.v v4, 0(a0), a1 + th.vssseg6e.v v4, (a0), a1, v0.t + + th.vlsseg7b.v v4, (a0), a1 + th.vlsseg7b.v v4, 0(a0), a1 + th.vlsseg7b.v v4, (a0), a1, v0.t + th.vlsseg7h.v v4, (a0), a1 + th.vlsseg7h.v v4, 0(a0), a1 + th.vlsseg7h.v v4, (a0), a1, v0.t + th.vlsseg7w.v v4, (a0), a1 + th.vlsseg7w.v v4, 0(a0), a1 + th.vlsseg7w.v v4, (a0), a1, v0.t + th.vlsseg7bu.v v4, (a0), a1 + th.vlsseg7bu.v v4, 0(a0), a1 + th.vlsseg7bu.v v4, (a0), a1, v0.t + th.vlsseg7hu.v v4, (a0), a1 + th.vlsseg7hu.v v4, 0(a0), a1 + th.vlsseg7hu.v v4, (a0), a1, v0.t + th.vlsseg7wu.v v4, (a0), a1 + th.vlsseg7wu.v v4, 0(a0), a1 + th.vlsseg7wu.v v4, (a0), a1, v0.t + th.vlsseg7e.v v4, (a0), a1 + th.vlsseg7e.v v4, 0(a0), a1 + th.vlsseg7e.v v4, (a0), a1, v0.t + th.vssseg7b.v v4, (a0), a1 + th.vssseg7b.v v4, 0(a0), a1 + th.vssseg7b.v v4, (a0), a1, v0.t + th.vssseg7h.v v4, (a0), a1 + th.vssseg7h.v v4, 0(a0), a1 + th.vssseg7h.v v4, (a0), a1, v0.t + th.vssseg7w.v v4, (a0), a1 + th.vssseg7w.v v4, 0(a0), a1 + th.vssseg7w.v v4, (a0), a1, v0.t + th.vssseg7e.v v4, (a0), a1 + th.vssseg7e.v v4, 0(a0), a1 + th.vssseg7e.v v4, (a0), a1, v0.t + + th.vlsseg8b.v v4, (a0), a1 + th.vlsseg8b.v v4, 0(a0), a1 + th.vlsseg8b.v v4, (a0), a1, v0.t + th.vlsseg8h.v v4, (a0), a1 + th.vlsseg8h.v v4, 0(a0), a1 + th.vlsseg8h.v v4, (a0), a1, v0.t + th.vlsseg8w.v v4, (a0), a1 + th.vlsseg8w.v v4, 0(a0), a1 + th.vlsseg8w.v v4, (a0), a1, v0.t + th.vlsseg8bu.v v4, (a0), a1 + th.vlsseg8bu.v v4, 0(a0), a1 + th.vlsseg8bu.v v4, (a0), a1, v0.t + th.vlsseg8hu.v v4, (a0), a1 + th.vlsseg8hu.v v4, 0(a0), a1 + th.vlsseg8hu.v v4, (a0), a1, v0.t + th.vlsseg8wu.v v4, (a0), a1 + th.vlsseg8wu.v v4, 0(a0), a1 + th.vlsseg8wu.v v4, (a0), a1, v0.t + th.vlsseg8e.v v4, (a0), a1 + th.vlsseg8e.v v4, 0(a0), a1 + th.vlsseg8e.v v4, (a0), a1, v0.t + th.vssseg8b.v v4, (a0), a1 + th.vssseg8b.v v4, 0(a0), a1 + th.vssseg8b.v v4, (a0), a1, v0.t + th.vssseg8h.v v4, (a0), a1 + th.vssseg8h.v v4, 0(a0), a1 + th.vssseg8h.v v4, (a0), a1, v0.t + th.vssseg8w.v v4, (a0), a1 + th.vssseg8w.v v4, 0(a0), a1 + th.vssseg8w.v v4, (a0), a1, v0.t + th.vssseg8e.v v4, (a0), a1 + th.vssseg8e.v v4, 0(a0), a1 + th.vssseg8e.v v4, (a0), a1, v0.t + + th.vlxseg2b.v v4, (a0), v12 + th.vlxseg2b.v v4, 0(a0), v12 + th.vlxseg2b.v v4, (a0), v12, v0.t + th.vlxseg2h.v v4, (a0), v12 + th.vlxseg2h.v v4, 0(a0), v12 + th.vlxseg2h.v v4, (a0), v12, v0.t + th.vlxseg2w.v v4, (a0), v12 + th.vlxseg2w.v v4, 0(a0), v12 + th.vlxseg2w.v v4, (a0), v12, v0.t + th.vlxseg2bu.v v4, (a0), v12 + th.vlxseg2bu.v v4, 0(a0), v12 + th.vlxseg2bu.v v4, (a0), v12, v0.t + th.vlxseg2hu.v v4, (a0), v12 + th.vlxseg2hu.v v4, 0(a0), v12 + th.vlxseg2hu.v v4, (a0), v12, v0.t + th.vlxseg2wu.v v4, (a0), v12 + th.vlxseg2wu.v v4, 0(a0), v12 + th.vlxseg2wu.v v4, (a0), v12, v0.t + th.vlxseg2e.v v4, (a0), v12 + th.vlxseg2e.v v4, 0(a0), v12 + th.vlxseg2e.v v4, (a0), v12, v0.t + th.vsxseg2b.v v4, (a0), v12 + th.vsxseg2b.v v4, 0(a0), v12 + th.vsxseg2b.v v4, (a0), v12, v0.t + th.vsxseg2h.v v4, (a0), v12 + th.vsxseg2h.v v4, 0(a0), v12 + th.vsxseg2h.v v4, (a0), v12, v0.t + th.vsxseg2w.v v4, (a0), v12 + th.vsxseg2w.v v4, 0(a0), v12 + th.vsxseg2w.v v4, (a0), v12, v0.t + th.vsxseg2e.v v4, (a0), v12 + th.vsxseg2e.v v4, 0(a0), v12 + th.vsxseg2e.v v4, (a0), v12, v0.t + + th.vlxseg3b.v v4, (a0), v12 + th.vlxseg3b.v v4, 0(a0), v12 + th.vlxseg3b.v v4, (a0), v12, v0.t + th.vlxseg3h.v v4, (a0), v12 + th.vlxseg3h.v v4, 0(a0), v12 + th.vlxseg3h.v v4, (a0), v12, v0.t + th.vlxseg3w.v v4, (a0), v12 + th.vlxseg3w.v v4, 0(a0), v12 + th.vlxseg3w.v v4, (a0), v12, v0.t + th.vlxseg3bu.v v4, (a0), v12 + th.vlxseg3bu.v v4, 0(a0), v12 + th.vlxseg3bu.v v4, (a0), v12, v0.t + th.vlxseg3hu.v v4, (a0), v12 + th.vlxseg3hu.v v4, 0(a0), v12 + th.vlxseg3hu.v v4, (a0), v12, v0.t + th.vlxseg3wu.v v4, (a0), v12 + th.vlxseg3wu.v v4, 0(a0), v12 + th.vlxseg3wu.v v4, (a0), v12, v0.t + th.vlxseg3e.v v4, (a0), v12 + th.vlxseg3e.v v4, 0(a0), v12 + th.vlxseg3e.v v4, (a0), v12, v0.t + th.vsxseg3b.v v4, (a0), v12 + th.vsxseg3b.v v4, 0(a0), v12 + th.vsxseg3b.v v4, (a0), v12, v0.t + th.vsxseg3h.v v4, (a0), v12 + th.vsxseg3h.v v4, 0(a0), v12 + th.vsxseg3h.v v4, (a0), v12, v0.t + th.vsxseg3w.v v4, (a0), v12 + th.vsxseg3w.v v4, 0(a0), v12 + th.vsxseg3w.v v4, (a0), v12, v0.t + th.vsxseg3e.v v4, (a0), v12 + th.vsxseg3e.v v4, 0(a0), v12 + th.vsxseg3e.v v4, (a0), v12, v0.t + + th.vlxseg4b.v v4, (a0), v12 + th.vlxseg4b.v v4, 0(a0), v12 + th.vlxseg4b.v v4, (a0), v12, v0.t + th.vlxseg4h.v v4, (a0), v12 + th.vlxseg4h.v v4, 0(a0), v12 + th.vlxseg4h.v v4, (a0), v12, v0.t + th.vlxseg4w.v v4, (a0), v12 + th.vlxseg4w.v v4, 0(a0), v12 + th.vlxseg4w.v v4, (a0), v12, v0.t + th.vlxseg4bu.v v4, (a0), v12 + th.vlxseg4bu.v v4, 0(a0), v12 + th.vlxseg4bu.v v4, (a0), v12, v0.t + th.vlxseg4hu.v v4, (a0), v12 + th.vlxseg4hu.v v4, 0(a0), v12 + th.vlxseg4hu.v v4, (a0), v12, v0.t + th.vlxseg4wu.v v4, (a0), v12 + th.vlxseg4wu.v v4, 0(a0), v12 + th.vlxseg4wu.v v4, (a0), v12, v0.t + th.vlxseg4e.v v4, (a0), v12 + th.vlxseg4e.v v4, 0(a0), v12 + th.vlxseg4e.v v4, (a0), v12, v0.t + th.vsxseg4b.v v4, (a0), v12 + th.vsxseg4b.v v4, 0(a0), v12 + th.vsxseg4b.v v4, (a0), v12, v0.t + th.vsxseg4h.v v4, (a0), v12 + th.vsxseg4h.v v4, 0(a0), v12 + th.vsxseg4h.v v4, (a0), v12, v0.t + th.vsxseg4w.v v4, (a0), v12 + th.vsxseg4w.v v4, 0(a0), v12 + th.vsxseg4w.v v4, (a0), v12, v0.t + th.vsxseg4e.v v4, (a0), v12 + th.vsxseg4e.v v4, 0(a0), v12 + th.vsxseg4e.v v4, (a0), v12, v0.t + + th.vlxseg5b.v v4, (a0), v12 + th.vlxseg5b.v v4, 0(a0), v12 + th.vlxseg5b.v v4, (a0), v12, v0.t + th.vlxseg5h.v v4, (a0), v12 + th.vlxseg5h.v v4, 0(a0), v12 + th.vlxseg5h.v v4, (a0), v12, v0.t + th.vlxseg5w.v v4, (a0), v12 + th.vlxseg5w.v v4, 0(a0), v12 + th.vlxseg5w.v v4, (a0), v12, v0.t + th.vlxseg5bu.v v4, (a0), v12 + th.vlxseg5bu.v v4, 0(a0), v12 + th.vlxseg5bu.v v4, (a0), v12, v0.t + th.vlxseg5hu.v v4, (a0), v12 + th.vlxseg5hu.v v4, 0(a0), v12 + th.vlxseg5hu.v v4, (a0), v12, v0.t + th.vlxseg5wu.v v4, (a0), v12 + th.vlxseg5wu.v v4, 0(a0), v12 + th.vlxseg5wu.v v4, (a0), v12, v0.t + th.vlxseg5e.v v4, (a0), v12 + th.vlxseg5e.v v4, 0(a0), v12 + th.vlxseg5e.v v4, (a0), v12, v0.t + th.vsxseg5b.v v4, (a0), v12 + th.vsxseg5b.v v4, 0(a0), v12 + th.vsxseg5b.v v4, (a0), v12, v0.t + th.vsxseg5h.v v4, (a0), v12 + th.vsxseg5h.v v4, 0(a0), v12 + th.vsxseg5h.v v4, (a0), v12, v0.t + th.vsxseg5w.v v4, (a0), v12 + th.vsxseg5w.v v4, 0(a0), v12 + th.vsxseg5w.v v4, (a0), v12, v0.t + th.vsxseg5e.v v4, (a0), v12 + th.vsxseg5e.v v4, 0(a0), v12 + th.vsxseg5e.v v4, (a0), v12, v0.t + + th.vlxseg6b.v v4, (a0), v12 + th.vlxseg6b.v v4, 0(a0), v12 + th.vlxseg6b.v v4, (a0), v12, v0.t + th.vlxseg6h.v v4, (a0), v12 + th.vlxseg6h.v v4, 0(a0), v12 + th.vlxseg6h.v v4, (a0), v12, v0.t + th.vlxseg6w.v v4, (a0), v12 + th.vlxseg6w.v v4, 0(a0), v12 + th.vlxseg6w.v v4, (a0), v12, v0.t + th.vlxseg6bu.v v4, (a0), v12 + th.vlxseg6bu.v v4, 0(a0), v12 + th.vlxseg6bu.v v4, (a0), v12, v0.t + th.vlxseg6hu.v v4, (a0), v12 + th.vlxseg6hu.v v4, 0(a0), v12 + th.vlxseg6hu.v v4, (a0), v12, v0.t + th.vlxseg6wu.v v4, (a0), v12 + th.vlxseg6wu.v v4, 0(a0), v12 + th.vlxseg6wu.v v4, (a0), v12, v0.t + th.vlxseg6e.v v4, (a0), v12 + th.vlxseg6e.v v4, 0(a0), v12 + th.vlxseg6e.v v4, (a0), v12, v0.t + th.vsxseg6b.v v4, (a0), v12 + th.vsxseg6b.v v4, 0(a0), v12 + th.vsxseg6b.v v4, (a0), v12, v0.t + th.vsxseg6h.v v4, (a0), v12 + th.vsxseg6h.v v4, 0(a0), v12 + th.vsxseg6h.v v4, (a0), v12, v0.t + th.vsxseg6w.v v4, (a0), v12 + th.vsxseg6w.v v4, 0(a0), v12 + th.vsxseg6w.v v4, (a0), v12, v0.t + th.vsxseg6e.v v4, (a0), v12 + th.vsxseg6e.v v4, 0(a0), v12 + th.vsxseg6e.v v4, (a0), v12, v0.t + + th.vlxseg7b.v v4, (a0), v12 + th.vlxseg7b.v v4, 0(a0), v12 + th.vlxseg7b.v v4, (a0), v12, v0.t + th.vlxseg7h.v v4, (a0), v12 + th.vlxseg7h.v v4, 0(a0), v12 + th.vlxseg7h.v v4, (a0), v12, v0.t + th.vlxseg7w.v v4, (a0), v12 + th.vlxseg7w.v v4, 0(a0), v12 + th.vlxseg7w.v v4, (a0), v12, v0.t + th.vlxseg7bu.v v4, (a0), v12 + th.vlxseg7bu.v v4, 0(a0), v12 + th.vlxseg7bu.v v4, (a0), v12, v0.t + th.vlxseg7hu.v v4, (a0), v12 + th.vlxseg7hu.v v4, 0(a0), v12 + th.vlxseg7hu.v v4, (a0), v12, v0.t + th.vlxseg7wu.v v4, (a0), v12 + th.vlxseg7wu.v v4, 0(a0), v12 + th.vlxseg7wu.v v4, (a0), v12, v0.t + th.vlxseg7e.v v4, (a0), v12 + th.vlxseg7e.v v4, 0(a0), v12 + th.vlxseg7e.v v4, (a0), v12, v0.t + th.vsxseg7b.v v4, (a0), v12 + th.vsxseg7b.v v4, 0(a0), v12 + th.vsxseg7b.v v4, (a0), v12, v0.t + th.vsxseg7h.v v4, (a0), v12 + th.vsxseg7h.v v4, 0(a0), v12 + th.vsxseg7h.v v4, (a0), v12, v0.t + th.vsxseg7w.v v4, (a0), v12 + th.vsxseg7w.v v4, 0(a0), v12 + th.vsxseg7w.v v4, (a0), v12, v0.t + th.vsxseg7e.v v4, (a0), v12 + th.vsxseg7e.v v4, 0(a0), v12 + th.vsxseg7e.v v4, (a0), v12, v0.t + + th.vlxseg8b.v v4, (a0), v12 + th.vlxseg8b.v v4, 0(a0), v12 + th.vlxseg8b.v v4, (a0), v12, v0.t + th.vlxseg8h.v v4, (a0), v12 + th.vlxseg8h.v v4, 0(a0), v12 + th.vlxseg8h.v v4, (a0), v12, v0.t + th.vlxseg8w.v v4, (a0), v12 + th.vlxseg8w.v v4, 0(a0), v12 + th.vlxseg8w.v v4, (a0), v12, v0.t + th.vlxseg8bu.v v4, (a0), v12 + th.vlxseg8bu.v v4, 0(a0), v12 + th.vlxseg8bu.v v4, (a0), v12, v0.t + th.vlxseg8hu.v v4, (a0), v12 + th.vlxseg8hu.v v4, 0(a0), v12 + th.vlxseg8hu.v v4, (a0), v12, v0.t + th.vlxseg8wu.v v4, (a0), v12 + th.vlxseg8wu.v v4, 0(a0), v12 + th.vlxseg8wu.v v4, (a0), v12, v0.t + th.vlxseg8e.v v4, (a0), v12 + th.vlxseg8e.v v4, 0(a0), v12 + th.vlxseg8e.v v4, (a0), v12, v0.t + th.vsxseg8b.v v4, (a0), v12 + th.vsxseg8b.v v4, 0(a0), v12 + th.vsxseg8b.v v4, (a0), v12, v0.t + th.vsxseg8h.v v4, (a0), v12 + th.vsxseg8h.v v4, 0(a0), v12 + th.vsxseg8h.v v4, (a0), v12, v0.t + th.vsxseg8w.v v4, (a0), v12 + th.vsxseg8w.v v4, 0(a0), v12 + th.vsxseg8w.v v4, (a0), v12, v0.t + th.vsxseg8e.v v4, (a0), v12 + th.vsxseg8e.v v4, 0(a0), v12 + th.vsxseg8e.v v4, (a0), v12, v0.t + + th.vlseg2bff.v v4, (a0) + th.vlseg2bff.v v4, 0(a0) + th.vlseg2bff.v v4, (a0), v0.t + th.vlseg2hff.v v4, (a0) + th.vlseg2hff.v v4, 0(a0) + th.vlseg2hff.v v4, (a0), v0.t + th.vlseg2wff.v v4, (a0) + th.vlseg2wff.v v4, 0(a0) + th.vlseg2wff.v v4, (a0), v0.t + th.vlseg2buff.v v4, (a0) + th.vlseg2buff.v v4, 0(a0) + th.vlseg2buff.v v4, (a0), v0.t + th.vlseg2huff.v v4, (a0) + th.vlseg2huff.v v4, 0(a0) + th.vlseg2huff.v v4, (a0), v0.t + th.vlseg2wuff.v v4, (a0) + th.vlseg2wuff.v v4, 0(a0) + th.vlseg2wuff.v v4, (a0), v0.t + th.vlseg2eff.v v4, (a0) + th.vlseg2eff.v v4, 0(a0) + th.vlseg2eff.v v4, (a0), v0.t + + th.vlseg3bff.v v4, (a0) + th.vlseg3bff.v v4, 0(a0) + th.vlseg3bff.v v4, (a0), v0.t + th.vlseg3hff.v v4, (a0) + th.vlseg3hff.v v4, 0(a0) + th.vlseg3hff.v v4, (a0), v0.t + th.vlseg3wff.v v4, (a0) + th.vlseg3wff.v v4, 0(a0) + th.vlseg3wff.v v4, (a0), v0.t + th.vlseg3buff.v v4, (a0) + th.vlseg3buff.v v4, 0(a0) + th.vlseg3buff.v v4, (a0), v0.t + th.vlseg3huff.v v4, (a0) + th.vlseg3huff.v v4, 0(a0) + th.vlseg3huff.v v4, (a0), v0.t + th.vlseg3wuff.v v4, (a0) + th.vlseg3wuff.v v4, 0(a0) + th.vlseg3wuff.v v4, (a0), v0.t + th.vlseg3eff.v v4, (a0) + th.vlseg3eff.v v4, 0(a0) + th.vlseg3eff.v v4, (a0), v0.t + + th.vlseg4bff.v v4, (a0) + th.vlseg4bff.v v4, 0(a0) + th.vlseg4bff.v v4, (a0), v0.t + th.vlseg4hff.v v4, (a0) + th.vlseg4hff.v v4, 0(a0) + th.vlseg4hff.v v4, (a0), v0.t + th.vlseg4wff.v v4, (a0) + th.vlseg4wff.v v4, 0(a0) + th.vlseg4wff.v v4, (a0), v0.t + th.vlseg4buff.v v4, (a0) + th.vlseg4buff.v v4, 0(a0) + th.vlseg4buff.v v4, (a0), v0.t + th.vlseg4huff.v v4, (a0) + th.vlseg4huff.v v4, 0(a0) + th.vlseg4huff.v v4, (a0), v0.t + th.vlseg4wuff.v v4, (a0) + th.vlseg4wuff.v v4, 0(a0) + th.vlseg4wuff.v v4, (a0), v0.t + th.vlseg4eff.v v4, (a0) + th.vlseg4eff.v v4, 0(a0) + th.vlseg4eff.v v4, (a0), v0.t + + th.vlseg5bff.v v4, (a0) + th.vlseg5bff.v v4, 0(a0) + th.vlseg5bff.v v4, (a0), v0.t + th.vlseg5hff.v v4, (a0) + th.vlseg5hff.v v4, 0(a0) + th.vlseg5hff.v v4, (a0), v0.t + th.vlseg5wff.v v4, (a0) + th.vlseg5wff.v v4, 0(a0) + th.vlseg5wff.v v4, (a0), v0.t + th.vlseg5buff.v v4, (a0) + th.vlseg5buff.v v4, 0(a0) + th.vlseg5buff.v v4, (a0), v0.t + th.vlseg5huff.v v4, (a0) + th.vlseg5huff.v v4, 0(a0) + th.vlseg5huff.v v4, (a0), v0.t + th.vlseg5wuff.v v4, (a0) + th.vlseg5wuff.v v4, 0(a0) + th.vlseg5wuff.v v4, (a0), v0.t + th.vlseg5eff.v v4, (a0) + th.vlseg5eff.v v4, 0(a0) + th.vlseg5eff.v v4, (a0), v0.t + + th.vlseg6bff.v v4, (a0) + th.vlseg6bff.v v4, 0(a0) + th.vlseg6bff.v v4, (a0), v0.t + th.vlseg6hff.v v4, (a0) + th.vlseg6hff.v v4, 0(a0) + th.vlseg6hff.v v4, (a0), v0.t + th.vlseg6wff.v v4, (a0) + th.vlseg6wff.v v4, 0(a0) + th.vlseg6wff.v v4, (a0), v0.t + th.vlseg6buff.v v4, (a0) + th.vlseg6buff.v v4, 0(a0) + th.vlseg6buff.v v4, (a0), v0.t + th.vlseg6huff.v v4, (a0) + th.vlseg6huff.v v4, 0(a0) + th.vlseg6huff.v v4, (a0), v0.t + th.vlseg6wuff.v v4, (a0) + th.vlseg6wuff.v v4, 0(a0) + th.vlseg6wuff.v v4, (a0), v0.t + th.vlseg6eff.v v4, (a0) + th.vlseg6eff.v v4, 0(a0) + th.vlseg6eff.v v4, (a0), v0.t + + th.vlseg7bff.v v4, (a0) + th.vlseg7bff.v v4, 0(a0) + th.vlseg7bff.v v4, (a0), v0.t + th.vlseg7hff.v v4, (a0) + th.vlseg7hff.v v4, 0(a0) + th.vlseg7hff.v v4, (a0), v0.t + th.vlseg7wff.v v4, (a0) + th.vlseg7wff.v v4, 0(a0) + th.vlseg7wff.v v4, (a0), v0.t + th.vlseg7buff.v v4, (a0) + th.vlseg7buff.v v4, 0(a0) + th.vlseg7buff.v v4, (a0), v0.t + th.vlseg7huff.v v4, (a0) + th.vlseg7huff.v v4, 0(a0) + th.vlseg7huff.v v4, (a0), v0.t + th.vlseg7wuff.v v4, (a0) + th.vlseg7wuff.v v4, 0(a0) + th.vlseg7wuff.v v4, (a0), v0.t + th.vlseg7eff.v v4, (a0) + th.vlseg7eff.v v4, 0(a0) + th.vlseg7eff.v v4, (a0), v0.t + + th.vlseg8bff.v v4, (a0) + th.vlseg8bff.v v4, 0(a0) + th.vlseg8bff.v v4, (a0), v0.t + th.vlseg8hff.v v4, (a0) + th.vlseg8hff.v v4, 0(a0) + th.vlseg8hff.v v4, (a0), v0.t + th.vlseg8wff.v v4, (a0) + th.vlseg8wff.v v4, 0(a0) + th.vlseg8wff.v v4, (a0), v0.t + th.vlseg8buff.v v4, (a0) + th.vlseg8buff.v v4, 0(a0) + th.vlseg8buff.v v4, (a0), v0.t + th.vlseg8huff.v v4, (a0) + th.vlseg8huff.v v4, 0(a0) + th.vlseg8huff.v v4, (a0), v0.t + th.vlseg8wuff.v v4, (a0) + th.vlseg8wuff.v v4, 0(a0) + th.vlseg8wuff.v v4, (a0), v0.t + th.vlseg8eff.v v4, (a0) + th.vlseg8eff.v v4, 0(a0) + th.vlseg8eff.v v4, (a0), v0.t diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h index a0de7a59676..c1f94f484d8 100644 --- a/include/opcode/riscv-opc.h +++ b/include/opcode/riscv-opc.h @@ -2741,6 +2741,566 @@ #define MASK_TH_VLWUFFV 0xfdf0707f #define MATCH_TH_VLEFFV 0x01007007 #define MASK_TH_VLEFFV 0xfdf0707f +#define MATCH_TH_VLSEG2BV 0x30000007 +#define MASK_TH_VLSEG2BV 0xfdf0707f +#define MATCH_TH_VLSEG2HV 0x30005007 +#define MASK_TH_VLSEG2HV 0xfdf0707f +#define MATCH_TH_VLSEG2WV 0x30006007 +#define MASK_TH_VLSEG2WV 0xfdf0707f +#define MATCH_TH_VLSEG2BUV 0x20000007 +#define MASK_TH_VLSEG2BUV 0xfdf0707f +#define MATCH_TH_VLSEG2HUV 0x20005007 +#define MASK_TH_VLSEG2HUV 0xfdf0707f +#define MATCH_TH_VLSEG2WUV 0x20006007 +#define MASK_TH_VLSEG2WUV 0xfdf0707f +#define MATCH_TH_VLSEG2EV 0x20007007 +#define MASK_TH_VLSEG2EV 0xfdf0707f +#define MATCH_TH_VSSEG2BV 0x20000027 +#define MASK_TH_VSSEG2BV 0xfdf0707f +#define MATCH_TH_VSSEG2HV 0x20005027 +#define MASK_TH_VSSEG2HV 0xfdf0707f +#define MATCH_TH_VSSEG2WV 0x20006027 +#define MASK_TH_VSSEG2WV 0xfdf0707f +#define MATCH_TH_VSSEG2EV 0x20007027 +#define MASK_TH_VSSEG2EV 0xfdf0707f +#define MATCH_TH_VLSEG3BV 0x50000007 +#define MASK_TH_VLSEG3BV 0xfdf0707f +#define MATCH_TH_VLSEG3HV 0x50005007 +#define MASK_TH_VLSEG3HV 0xfdf0707f +#define MATCH_TH_VLSEG3WV 0x50006007 +#define MASK_TH_VLSEG3WV 0xfdf0707f +#define MATCH_TH_VLSEG3BUV 0x40000007 +#define MASK_TH_VLSEG3BUV 0xfdf0707f +#define MATCH_TH_VLSEG3HUV 0x40005007 +#define MASK_TH_VLSEG3HUV 0xfdf0707f +#define MATCH_TH_VLSEG3WUV 0x40006007 +#define MASK_TH_VLSEG3WUV 0xfdf0707f +#define MATCH_TH_VLSEG3EV 0x40007007 +#define MASK_TH_VLSEG3EV 0xfdf0707f +#define MATCH_TH_VSSEG3BV 0x40000027 +#define MASK_TH_VSSEG3BV 0xfdf0707f +#define MATCH_TH_VSSEG3HV 0x40005027 +#define MASK_TH_VSSEG3HV 0xfdf0707f +#define MATCH_TH_VSSEG3WV 0x40006027 +#define MASK_TH_VSSEG3WV 0xfdf0707f +#define MATCH_TH_VSSEG3EV 0x40007027 +#define MASK_TH_VSSEG3EV 0xfdf0707f +#define MATCH_TH_VLSEG4BV 0x70000007 +#define MASK_TH_VLSEG4BV 0xfdf0707f +#define MATCH_TH_VLSEG4HV 0x70005007 +#define MASK_TH_VLSEG4HV 0xfdf0707f +#define MATCH_TH_VLSEG4WV 0x70006007 +#define MASK_TH_VLSEG4WV 0xfdf0707f +#define MATCH_TH_VLSEG4BUV 0x60000007 +#define MASK_TH_VLSEG4BUV 0xfdf0707f +#define MATCH_TH_VLSEG4HUV 0x60005007 +#define MASK_TH_VLSEG4HUV 0xfdf0707f +#define MATCH_TH_VLSEG4WUV 0x60006007 +#define MASK_TH_VLSEG4WUV 0xfdf0707f +#define MATCH_TH_VLSEG4EV 0x60007007 +#define MASK_TH_VLSEG4EV 0xfdf0707f +#define MATCH_TH_VSSEG4BV 0x60000027 +#define MASK_TH_VSSEG4BV 0xfdf0707f +#define MATCH_TH_VSSEG4HV 0x60005027 +#define MASK_TH_VSSEG4HV 0xfdf0707f +#define MATCH_TH_VSSEG4WV 0x60006027 +#define MASK_TH_VSSEG4WV 0xfdf0707f +#define MATCH_TH_VSSEG4EV 0x60007027 +#define MASK_TH_VSSEG4EV 0xfdf0707f +#define MATCH_TH_VLSEG5BV 0x90000007 +#define MASK_TH_VLSEG5BV 0xfdf0707f +#define MATCH_TH_VLSEG5HV 0x90005007 +#define MASK_TH_VLSEG5HV 0xfdf0707f +#define MATCH_TH_VLSEG5WV 0x90006007 +#define MASK_TH_VLSEG5WV 0xfdf0707f +#define MATCH_TH_VLSEG5BUV 0x80000007 +#define MASK_TH_VLSEG5BUV 0xfdf0707f +#define MATCH_TH_VLSEG5HUV 0x80005007 +#define MASK_TH_VLSEG5HUV 0xfdf0707f +#define MATCH_TH_VLSEG5WUV 0x80006007 +#define MASK_TH_VLSEG5WUV 0xfdf0707f +#define MATCH_TH_VLSEG5EV 0x80007007 +#define MASK_TH_VLSEG5EV 0xfdf0707f +#define MATCH_TH_VSSEG5BV 0x80000027 +#define MASK_TH_VSSEG5BV 0xfdf0707f +#define MATCH_TH_VSSEG5HV 0x80005027 +#define MASK_TH_VSSEG5HV 0xfdf0707f +#define MATCH_TH_VSSEG5WV 0x80006027 +#define MASK_TH_VSSEG5WV 0xfdf0707f +#define MATCH_TH_VSSEG5EV 0x80007027 +#define MASK_TH_VSSEG5EV 0xfdf0707f +#define MATCH_TH_VLSEG6BV 0xb0000007 +#define MASK_TH_VLSEG6BV 0xfdf0707f +#define MATCH_TH_VLSEG6HV 0xb0005007 +#define MASK_TH_VLSEG6HV 0xfdf0707f +#define MATCH_TH_VLSEG6WV 0xb0006007 +#define MASK_TH_VLSEG6WV 0xfdf0707f +#define MATCH_TH_VLSEG6BUV 0xa0000007 +#define MASK_TH_VLSEG6BUV 0xfdf0707f +#define MATCH_TH_VLSEG6HUV 0xa0005007 +#define MASK_TH_VLSEG6HUV 0xfdf0707f +#define MATCH_TH_VLSEG6WUV 0xa0006007 +#define MASK_TH_VLSEG6WUV 0xfdf0707f +#define MATCH_TH_VLSEG6EV 0xa0007007 +#define MASK_TH_VLSEG6EV 0xfdf0707f +#define MATCH_TH_VSSEG6BV 0xa0000027 +#define MASK_TH_VSSEG6BV 0xfdf0707f +#define MATCH_TH_VSSEG6HV 0xa0005027 +#define MASK_TH_VSSEG6HV 0xfdf0707f +#define MATCH_TH_VSSEG6WV 0xa0006027 +#define MASK_TH_VSSEG6WV 0xfdf0707f +#define MATCH_TH_VSSEG6EV 0xa0007027 +#define MASK_TH_VSSEG6EV 0xfdf0707f +#define MATCH_TH_VLSEG7BV 0xd0000007 +#define MASK_TH_VLSEG7BV 0xfdf0707f +#define MATCH_TH_VLSEG7HV 0xd0005007 +#define MASK_TH_VLSEG7HV 0xfdf0707f +#define MATCH_TH_VLSEG7WV 0xd0006007 +#define MASK_TH_VLSEG7WV 0xfdf0707f +#define MATCH_TH_VLSEG7BUV 0xc0000007 +#define MASK_TH_VLSEG7BUV 0xfdf0707f +#define MATCH_TH_VLSEG7HUV 0xc0005007 +#define MASK_TH_VLSEG7HUV 0xfdf0707f +#define MATCH_TH_VLSEG7WUV 0xc0006007 +#define MASK_TH_VLSEG7WUV 0xfdf0707f +#define MATCH_TH_VLSEG7EV 0xc0007007 +#define MASK_TH_VLSEG7EV 0xfdf0707f +#define MATCH_TH_VSSEG7BV 0xc0000027 +#define MASK_TH_VSSEG7BV 0xfdf0707f +#define MATCH_TH_VSSEG7HV 0xc0005027 +#define MASK_TH_VSSEG7HV 0xfdf0707f +#define MATCH_TH_VSSEG7WV 0xc0006027 +#define MASK_TH_VSSEG7WV 0xfdf0707f +#define MATCH_TH_VSSEG7EV 0xc0007027 +#define MASK_TH_VSSEG7EV 0xfdf0707f +#define MATCH_TH_VLSEG8BV 0xf0000007 +#define MASK_TH_VLSEG8BV 0xfdf0707f +#define MATCH_TH_VLSEG8HV 0xf0005007 +#define MASK_TH_VLSEG8HV 0xfdf0707f +#define MATCH_TH_VLSEG8WV 0xf0006007 +#define MASK_TH_VLSEG8WV 0xfdf0707f +#define MATCH_TH_VLSEG8BUV 0xe0000007 +#define MASK_TH_VLSEG8BUV 0xfdf0707f +#define MATCH_TH_VLSEG8HUV 0xe0005007 +#define MASK_TH_VLSEG8HUV 0xfdf0707f +#define MATCH_TH_VLSEG8WUV 0xe0006007 +#define MASK_TH_VLSEG8WUV 0xfdf0707f +#define MATCH_TH_VLSEG8EV 0xe0007007 +#define MASK_TH_VLSEG8EV 0xfdf0707f +#define MATCH_TH_VSSEG8BV 0xe0000027 +#define MASK_TH_VSSEG8BV 0xfdf0707f +#define MATCH_TH_VSSEG8HV 0xe0005027 +#define MASK_TH_VSSEG8HV 0xfdf0707f +#define MATCH_TH_VSSEG8WV 0xe0006027 +#define MASK_TH_VSSEG8WV 0xfdf0707f +#define MATCH_TH_VSSEG8EV 0xe0007027 +#define MASK_TH_VSSEG8EV 0xfdf0707f +#define MATCH_TH_VLSSEG2BV 0x38000007 +#define MASK_TH_VLSSEG2BV 0xfc00707f +#define MATCH_TH_VLSSEG2HV 0x38005007 +#define MASK_TH_VLSSEG2HV 0xfc00707f +#define MATCH_TH_VLSSEG2WV 0x38006007 +#define MASK_TH_VLSSEG2WV 0xfc00707f +#define MATCH_TH_VLSSEG2BUV 0x28000007 +#define MASK_TH_VLSSEG2BUV 0xfc00707f +#define MATCH_TH_VLSSEG2HUV 0x28005007 +#define MASK_TH_VLSSEG2HUV 0xfc00707f +#define MATCH_TH_VLSSEG2WUV 0x28006007 +#define MASK_TH_VLSSEG2WUV 0xfc00707f +#define MATCH_TH_VLSSEG2EV 0x28007007 +#define MASK_TH_VLSSEG2EV 0xfc00707f +#define MATCH_TH_VSSSEG2BV 0x28000027 +#define MASK_TH_VSSSEG2BV 0xfc00707f +#define MATCH_TH_VSSSEG2HV 0x28005027 +#define MASK_TH_VSSSEG2HV 0xfc00707f +#define MATCH_TH_VSSSEG2WV 0x28006027 +#define MASK_TH_VSSSEG2WV 0xfc00707f +#define MATCH_TH_VSSSEG2EV 0x28007027 +#define MASK_TH_VSSSEG2EV 0xfc00707f +#define MATCH_TH_VLSSEG3BV 0x58000007 +#define MASK_TH_VLSSEG3BV 0xfc00707f +#define MATCH_TH_VLSSEG3HV 0x58005007 +#define MASK_TH_VLSSEG3HV 0xfc00707f +#define MATCH_TH_VLSSEG3WV 0x58006007 +#define MASK_TH_VLSSEG3WV 0xfc00707f +#define MATCH_TH_VLSSEG3BUV 0x48000007 +#define MASK_TH_VLSSEG3BUV 0xfc00707f +#define MATCH_TH_VLSSEG3HUV 0x48005007 +#define MASK_TH_VLSSEG3HUV 0xfc00707f +#define MATCH_TH_VLSSEG3WUV 0x48006007 +#define MASK_TH_VLSSEG3WUV 0xfc00707f +#define MATCH_TH_VLSSEG3EV 0x48007007 +#define MASK_TH_VLSSEG3EV 0xfc00707f +#define MATCH_TH_VSSSEG3BV 0x48000027 +#define MASK_TH_VSSSEG3BV 0xfc00707f +#define MATCH_TH_VSSSEG3HV 0x48005027 +#define MASK_TH_VSSSEG3HV 0xfc00707f +#define MATCH_TH_VSSSEG3WV 0x48006027 +#define MASK_TH_VSSSEG3WV 0xfc00707f +#define MATCH_TH_VSSSEG3EV 0x48007027 +#define MASK_TH_VSSSEG3EV 0xfc00707f +#define MATCH_TH_VLSSEG4BV 0x78000007 +#define MASK_TH_VLSSEG4BV 0xfc00707f +#define MATCH_TH_VLSSEG4HV 0x78005007 +#define MASK_TH_VLSSEG4HV 0xfc00707f +#define MATCH_TH_VLSSEG4WV 0x78006007 +#define MASK_TH_VLSSEG4WV 0xfc00707f +#define MATCH_TH_VLSSEG4BUV 0x68000007 +#define MASK_TH_VLSSEG4BUV 0xfc00707f +#define MATCH_TH_VLSSEG4HUV 0x68005007 +#define MASK_TH_VLSSEG4HUV 0xfc00707f +#define MATCH_TH_VLSSEG4WUV 0x68006007 +#define MASK_TH_VLSSEG4WUV 0xfc00707f +#define MATCH_TH_VLSSEG4EV 0x68007007 +#define MASK_TH_VLSSEG4EV 0xfc00707f +#define MATCH_TH_VSSSEG4BV 0x68000027 +#define MASK_TH_VSSSEG4BV 0xfc00707f +#define MATCH_TH_VSSSEG4HV 0x68005027 +#define MASK_TH_VSSSEG4HV 0xfc00707f +#define MATCH_TH_VSSSEG4WV 0x68006027 +#define MASK_TH_VSSSEG4WV 0xfc00707f +#define MATCH_TH_VSSSEG4EV 0x68007027 +#define MASK_TH_VSSSEG4EV 0xfc00707f +#define MATCH_TH_VLSSEG5BV 0x98000007 +#define MASK_TH_VLSSEG5BV 0xfc00707f +#define MATCH_TH_VLSSEG5HV 0x98005007 +#define MASK_TH_VLSSEG5HV 0xfc00707f +#define MATCH_TH_VLSSEG5WV 0x98006007 +#define MASK_TH_VLSSEG5WV 0xfc00707f +#define MATCH_TH_VLSSEG5BUV 0x88000007 +#define MASK_TH_VLSSEG5BUV 0xfc00707f +#define MATCH_TH_VLSSEG5HUV 0x88005007 +#define MASK_TH_VLSSEG5HUV 0xfc00707f +#define MATCH_TH_VLSSEG5WUV 0x88006007 +#define MASK_TH_VLSSEG5WUV 0xfc00707f +#define MATCH_TH_VLSSEG5EV 0x88007007 +#define MASK_TH_VLSSEG5EV 0xfc00707f +#define MATCH_TH_VSSSEG5BV 0x88000027 +#define MASK_TH_VSSSEG5BV 0xfc00707f +#define MATCH_TH_VSSSEG5HV 0x88005027 +#define MASK_TH_VSSSEG5HV 0xfc00707f +#define MATCH_TH_VSSSEG5WV 0x88006027 +#define MASK_TH_VSSSEG5WV 0xfc00707f +#define MATCH_TH_VSSSEG5EV 0x88007027 +#define MASK_TH_VSSSEG5EV 0xfc00707f +#define MATCH_TH_VLSSEG6BV 0xb8000007 +#define MASK_TH_VLSSEG6BV 0xfc00707f +#define MATCH_TH_VLSSEG6HV 0xb8005007 +#define MASK_TH_VLSSEG6HV 0xfc00707f +#define MATCH_TH_VLSSEG6WV 0xb8006007 +#define MASK_TH_VLSSEG6WV 0xfc00707f +#define MATCH_TH_VLSSEG6BUV 0xa8000007 +#define MASK_TH_VLSSEG6BUV 0xfc00707f +#define MATCH_TH_VLSSEG6HUV 0xa8005007 +#define MASK_TH_VLSSEG6HUV 0xfc00707f +#define MATCH_TH_VLSSEG6WUV 0xa8006007 +#define MASK_TH_VLSSEG6WUV 0xfc00707f +#define MATCH_TH_VLSSEG6EV 0xa8007007 +#define MASK_TH_VLSSEG6EV 0xfc00707f +#define MATCH_TH_VSSSEG6BV 0xa8000027 +#define MASK_TH_VSSSEG6BV 0xfc00707f +#define MATCH_TH_VSSSEG6HV 0xa8005027 +#define MASK_TH_VSSSEG6HV 0xfc00707f +#define MATCH_TH_VSSSEG6WV 0xa8006027 +#define MASK_TH_VSSSEG6WV 0xfc00707f +#define MATCH_TH_VSSSEG6EV 0xa8007027 +#define MASK_TH_VSSSEG6EV 0xfc00707f +#define MATCH_TH_VLSSEG7BV 0xd8000007 +#define MASK_TH_VLSSEG7BV 0xfc00707f +#define MATCH_TH_VLSSEG7HV 0xd8005007 +#define MASK_TH_VLSSEG7HV 0xfc00707f +#define MATCH_TH_VLSSEG7WV 0xd8006007 +#define MASK_TH_VLSSEG7WV 0xfc00707f +#define MATCH_TH_VLSSEG7BUV 0xc8000007 +#define MASK_TH_VLSSEG7BUV 0xfc00707f +#define MATCH_TH_VLSSEG7HUV 0xc8005007 +#define MASK_TH_VLSSEG7HUV 0xfc00707f +#define MATCH_TH_VLSSEG7WUV 0xc8006007 +#define MASK_TH_VLSSEG7WUV 0xfc00707f +#define MATCH_TH_VLSSEG7EV 0xc8007007 +#define MASK_TH_VLSSEG7EV 0xfc00707f +#define MATCH_TH_VSSSEG7BV 0xc8000027 +#define MASK_TH_VSSSEG7BV 0xfc00707f +#define MATCH_TH_VSSSEG7HV 0xc8005027 +#define MASK_TH_VSSSEG7HV 0xfc00707f +#define MATCH_TH_VSSSEG7WV 0xc8006027 +#define MASK_TH_VSSSEG7WV 0xfc00707f +#define MATCH_TH_VSSSEG7EV 0xc8007027 +#define MASK_TH_VSSSEG7EV 0xfc00707f +#define MATCH_TH_VLSSEG8BV 0xf8000007 +#define MASK_TH_VLSSEG8BV 0xfc00707f +#define MATCH_TH_VLSSEG8HV 0xf8005007 +#define MASK_TH_VLSSEG8HV 0xfc00707f +#define MATCH_TH_VLSSEG8WV 0xf8006007 +#define MASK_TH_VLSSEG8WV 0xfc00707f +#define MATCH_TH_VLSSEG8BUV 0xe8000007 +#define MASK_TH_VLSSEG8BUV 0xfc00707f +#define MATCH_TH_VLSSEG8HUV 0xe8005007 +#define MASK_TH_VLSSEG8HUV 0xfc00707f +#define MATCH_TH_VLSSEG8WUV 0xe8006007 +#define MASK_TH_VLSSEG8WUV 0xfc00707f +#define MATCH_TH_VLSSEG8EV 0xe8007007 +#define MASK_TH_VLSSEG8EV 0xfc00707f +#define MATCH_TH_VSSSEG8BV 0xe8000027 +#define MASK_TH_VSSSEG8BV 0xfc00707f +#define MATCH_TH_VSSSEG8HV 0xe8005027 +#define MASK_TH_VSSSEG8HV 0xfc00707f +#define MATCH_TH_VSSSEG8WV 0xe8006027 +#define MASK_TH_VSSSEG8WV 0xfc00707f +#define MATCH_TH_VSSSEG8EV 0xe8007027 +#define MASK_TH_VSSSEG8EV 0xfc00707f +#define MATCH_TH_VLXSEG2BV 0x3c000007 +#define MASK_TH_VLXSEG2BV 0xfc00707f +#define MATCH_TH_VLXSEG2HV 0x3c005007 +#define MASK_TH_VLXSEG2HV 0xfc00707f +#define MATCH_TH_VLXSEG2WV 0x3c006007 +#define MASK_TH_VLXSEG2WV 0xfc00707f +#define MATCH_TH_VLXSEG2BUV 0x2c000007 +#define MASK_TH_VLXSEG2BUV 0xfc00707f +#define MATCH_TH_VLXSEG2HUV 0x2c005007 +#define MASK_TH_VLXSEG2HUV 0xfc00707f +#define MATCH_TH_VLXSEG2WUV 0x2c006007 +#define MASK_TH_VLXSEG2WUV 0xfc00707f +#define MATCH_TH_VLXSEG2EV 0x2c007007 +#define MASK_TH_VLXSEG2EV 0xfc00707f +#define MATCH_TH_VSXSEG2BV 0x2c000027 +#define MASK_TH_VSXSEG2BV 0xfc00707f +#define MATCH_TH_VSXSEG2HV 0x2c005027 +#define MASK_TH_VSXSEG2HV 0xfc00707f +#define MATCH_TH_VSXSEG2WV 0x2c006027 +#define MASK_TH_VSXSEG2WV 0xfc00707f +#define MATCH_TH_VSXSEG2EV 0x2c007027 +#define MASK_TH_VSXSEG2EV 0xfc00707f +#define MATCH_TH_VLXSEG3BV 0x5c000007 +#define MASK_TH_VLXSEG3BV 0xfc00707f +#define MATCH_TH_VLXSEG3HV 0x5c005007 +#define MASK_TH_VLXSEG3HV 0xfc00707f +#define MATCH_TH_VLXSEG3WV 0x5c006007 +#define MASK_TH_VLXSEG3WV 0xfc00707f +#define MATCH_TH_VLXSEG3BUV 0x4c000007 +#define MASK_TH_VLXSEG3BUV 0xfc00707f +#define MATCH_TH_VLXSEG3HUV 0x4c005007 +#define MASK_TH_VLXSEG3HUV 0xfc00707f +#define MATCH_TH_VLXSEG3WUV 0x4c006007 +#define MASK_TH_VLXSEG3WUV 0xfc00707f +#define MATCH_TH_VLXSEG3EV 0x4c007007 +#define MASK_TH_VLXSEG3EV 0xfc00707f +#define MATCH_TH_VSXSEG3BV 0x4c000027 +#define MASK_TH_VSXSEG3BV 0xfc00707f +#define MATCH_TH_VSXSEG3HV 0x4c005027 +#define MASK_TH_VSXSEG3HV 0xfc00707f +#define MATCH_TH_VSXSEG3WV 0x4c006027 +#define MASK_TH_VSXSEG3WV 0xfc00707f +#define MATCH_TH_VSXSEG3EV 0x4c007027 +#define MASK_TH_VSXSEG3EV 0xfc00707f +#define MATCH_TH_VLXSEG4BV 0x7c000007 +#define MASK_TH_VLXSEG4BV 0xfc00707f +#define MATCH_TH_VLXSEG4HV 0x7c005007 +#define MASK_TH_VLXSEG4HV 0xfc00707f +#define MATCH_TH_VLXSEG4WV 0x7c006007 +#define MASK_TH_VLXSEG4WV 0xfc00707f +#define MATCH_TH_VLXSEG4BUV 0x6c000007 +#define MASK_TH_VLXSEG4BUV 0xfc00707f +#define MATCH_TH_VLXSEG4HUV 0x6c005007 +#define MASK_TH_VLXSEG4HUV 0xfc00707f +#define MATCH_TH_VLXSEG4WUV 0x6c006007 +#define MASK_TH_VLXSEG4WUV 0xfc00707f +#define MATCH_TH_VLXSEG4EV 0x6c007007 +#define MASK_TH_VLXSEG4EV 0xfc00707f +#define MATCH_TH_VSXSEG4BV 0x6c000027 +#define MASK_TH_VSXSEG4BV 0xfc00707f +#define MATCH_TH_VSXSEG4HV 0x6c005027 +#define MASK_TH_VSXSEG4HV 0xfc00707f +#define MATCH_TH_VSXSEG4WV 0x6c006027 +#define MASK_TH_VSXSEG4WV 0xfc00707f +#define MATCH_TH_VSXSEG4EV 0x6c007027 +#define MASK_TH_VSXSEG4EV 0xfc00707f +#define MATCH_TH_VLXSEG5BV 0x9c000007 +#define MASK_TH_VLXSEG5BV 0xfc00707f +#define MATCH_TH_VLXSEG5HV 0x9c005007 +#define MASK_TH_VLXSEG5HV 0xfc00707f +#define MATCH_TH_VLXSEG5WV 0x9c006007 +#define MASK_TH_VLXSEG5WV 0xfc00707f +#define MATCH_TH_VLXSEG5BUV 0x8c000007 +#define MASK_TH_VLXSEG5BUV 0xfc00707f +#define MATCH_TH_VLXSEG5HUV 0x8c005007 +#define MASK_TH_VLXSEG5HUV 0xfc00707f +#define MATCH_TH_VLXSEG5WUV 0x8c006007 +#define MASK_TH_VLXSEG5WUV 0xfc00707f +#define MATCH_TH_VLXSEG5EV 0x8c007007 +#define MASK_TH_VLXSEG5EV 0xfc00707f +#define MATCH_TH_VSXSEG5BV 0x8c000027 +#define MASK_TH_VSXSEG5BV 0xfc00707f +#define MATCH_TH_VSXSEG5HV 0x8c005027 +#define MASK_TH_VSXSEG5HV 0xfc00707f +#define MATCH_TH_VSXSEG5WV 0x8c006027 +#define MASK_TH_VSXSEG5WV 0xfc00707f +#define MATCH_TH_VSXSEG5EV 0x8c007027 +#define MASK_TH_VSXSEG5EV 0xfc00707f +#define MATCH_TH_VLXSEG6BV 0xbc000007 +#define MASK_TH_VLXSEG6BV 0xfc00707f +#define MATCH_TH_VLXSEG6HV 0xbc005007 +#define MASK_TH_VLXSEG6HV 0xfc00707f +#define MATCH_TH_VLXSEG6WV 0xbc006007 +#define MASK_TH_VLXSEG6WV 0xfc00707f +#define MATCH_TH_VLXSEG6BUV 0xac000007 +#define MASK_TH_VLXSEG6BUV 0xfc00707f +#define MATCH_TH_VLXSEG6HUV 0xac005007 +#define MASK_TH_VLXSEG6HUV 0xfc00707f +#define MATCH_TH_VLXSEG6WUV 0xac006007 +#define MASK_TH_VLXSEG6WUV 0xfc00707f +#define MATCH_TH_VLXSEG6EV 0xac007007 +#define MASK_TH_VLXSEG6EV 0xfc00707f +#define MATCH_TH_VSXSEG6BV 0xac000027 +#define MASK_TH_VSXSEG6BV 0xfc00707f +#define MATCH_TH_VSXSEG6HV 0xac005027 +#define MASK_TH_VSXSEG6HV 0xfc00707f +#define MATCH_TH_VSXSEG6WV 0xac006027 +#define MASK_TH_VSXSEG6WV 0xfc00707f +#define MATCH_TH_VSXSEG6EV 0xac007027 +#define MASK_TH_VSXSEG6EV 0xfc00707f +#define MATCH_TH_VLXSEG7BV 0xdc000007 +#define MASK_TH_VLXSEG7BV 0xfc00707f +#define MATCH_TH_VLXSEG7HV 0xdc005007 +#define MASK_TH_VLXSEG7HV 0xfc00707f +#define MATCH_TH_VLXSEG7WV 0xdc006007 +#define MASK_TH_VLXSEG7WV 0xfc00707f +#define MATCH_TH_VLXSEG7BUV 0xcc000007 +#define MASK_TH_VLXSEG7BUV 0xfc00707f +#define MATCH_TH_VLXSEG7HUV 0xcc005007 +#define MASK_TH_VLXSEG7HUV 0xfc00707f +#define MATCH_TH_VLXSEG7WUV 0xcc006007 +#define MASK_TH_VLXSEG7WUV 0xfc00707f +#define MATCH_TH_VLXSEG7EV 0xcc007007 +#define MASK_TH_VLXSEG7EV 0xfc00707f +#define MATCH_TH_VSXSEG7BV 0xcc000027 +#define MASK_TH_VSXSEG7BV 0xfc00707f +#define MATCH_TH_VSXSEG7HV 0xcc005027 +#define MASK_TH_VSXSEG7HV 0xfc00707f +#define MATCH_TH_VSXSEG7WV 0xcc006027 +#define MASK_TH_VSXSEG7WV 0xfc00707f +#define MATCH_TH_VSXSEG7EV 0xcc007027 +#define MASK_TH_VSXSEG7EV 0xfc00707f +#define MATCH_TH_VLXSEG8BV 0xfc000007 +#define MASK_TH_VLXSEG8BV 0xfc00707f +#define MATCH_TH_VLXSEG8HV 0xfc005007 +#define MASK_TH_VLXSEG8HV 0xfc00707f +#define MATCH_TH_VLXSEG8WV 0xfc006007 +#define MASK_TH_VLXSEG8WV 0xfc00707f +#define MATCH_TH_VLXSEG8BUV 0xec000007 +#define MASK_TH_VLXSEG8BUV 0xfc00707f +#define MATCH_TH_VLXSEG8HUV 0xec005007 +#define MASK_TH_VLXSEG8HUV 0xfc00707f +#define MATCH_TH_VLXSEG8WUV 0xec006007 +#define MASK_TH_VLXSEG8WUV 0xfc00707f +#define MATCH_TH_VLXSEG8EV 0xec007007 +#define MASK_TH_VLXSEG8EV 0xfc00707f +#define MATCH_TH_VSXSEG8BV 0xec000027 +#define MASK_TH_VSXSEG8BV 0xfc00707f +#define MATCH_TH_VSXSEG8HV 0xec005027 +#define MASK_TH_VSXSEG8HV 0xfc00707f +#define MATCH_TH_VSXSEG8WV 0xec006027 +#define MASK_TH_VSXSEG8WV 0xfc00707f +#define MATCH_TH_VSXSEG8EV 0xec007027 +#define MASK_TH_VSXSEG8EV 0xfc00707f +#define MATCH_TH_VLSEG2BFFV 0x31000007 +#define MASK_TH_VLSEG2BFFV 0xfdf0707f +#define MATCH_TH_VLSEG2HFFV 0x31005007 +#define MASK_TH_VLSEG2HFFV 0xfdf0707f +#define MATCH_TH_VLSEG2WFFV 0x31006007 +#define MASK_TH_VLSEG2WFFV 0xfdf0707f +#define MATCH_TH_VLSEG2BUFFV 0x21000007 +#define MASK_TH_VLSEG2BUFFV 0xfdf0707f +#define MATCH_TH_VLSEG2HUFFV 0x21005007 +#define MASK_TH_VLSEG2HUFFV 0xfdf0707f +#define MATCH_TH_VLSEG2WUFFV 0x21006007 +#define MASK_TH_VLSEG2WUFFV 0xfdf0707f +#define MATCH_TH_VLSEG2EFFV 0x21007007 +#define MASK_TH_VLSEG2EFFV 0xfdf0707f +#define MATCH_TH_VLSEG3BFFV 0x51000007 +#define MASK_TH_VLSEG3BFFV 0xfdf0707f +#define MATCH_TH_VLSEG3HFFV 0x51005007 +#define MASK_TH_VLSEG3HFFV 0xfdf0707f +#define MATCH_TH_VLSEG3WFFV 0x51006007 +#define MASK_TH_VLSEG3WFFV 0xfdf0707f +#define MATCH_TH_VLSEG3BUFFV 0x41000007 +#define MASK_TH_VLSEG3BUFFV 0xfdf0707f +#define MATCH_TH_VLSEG3HUFFV 0x41005007 +#define MASK_TH_VLSEG3HUFFV 0xfdf0707f +#define MATCH_TH_VLSEG3WUFFV 0x41006007 +#define MASK_TH_VLSEG3WUFFV 0xfdf0707f +#define MATCH_TH_VLSEG3EFFV 0x41007007 +#define MASK_TH_VLSEG3EFFV 0xfdf0707f +#define MATCH_TH_VLSEG4BFFV 0x71000007 +#define MASK_TH_VLSEG4BFFV 0xfdf0707f +#define MATCH_TH_VLSEG4HFFV 0x71005007 +#define MASK_TH_VLSEG4HFFV 0xfdf0707f +#define MATCH_TH_VLSEG4WFFV 0x71006007 +#define MASK_TH_VLSEG4WFFV 0xfdf0707f +#define MATCH_TH_VLSEG4BUFFV 0x61000007 +#define MASK_TH_VLSEG4BUFFV 0xfdf0707f +#define MATCH_TH_VLSEG4HUFFV 0x61005007 +#define MASK_TH_VLSEG4HUFFV 0xfdf0707f +#define MATCH_TH_VLSEG4WUFFV 0x61006007 +#define MASK_TH_VLSEG4WUFFV 0xfdf0707f +#define MATCH_TH_VLSEG4EFFV 0x61007007 +#define MASK_TH_VLSEG4EFFV 0xfdf0707f +#define MATCH_TH_VLSEG5BFFV 0x91000007 +#define MASK_TH_VLSEG5BFFV 0xfdf0707f +#define MATCH_TH_VLSEG5HFFV 0x91005007 +#define MASK_TH_VLSEG5HFFV 0xfdf0707f +#define MATCH_TH_VLSEG5WFFV 0x91006007 +#define MASK_TH_VLSEG5WFFV 0xfdf0707f +#define MATCH_TH_VLSEG5BUFFV 0x81000007 +#define MASK_TH_VLSEG5BUFFV 0xfdf0707f +#define MATCH_TH_VLSEG5HUFFV 0x81005007 +#define MASK_TH_VLSEG5HUFFV 0xfdf0707f +#define MATCH_TH_VLSEG5WUFFV 0x81006007 +#define MASK_TH_VLSEG5WUFFV 0xfdf0707f +#define MATCH_TH_VLSEG5EFFV 0x81007007 +#define MASK_TH_VLSEG5EFFV 0xfdf0707f +#define MATCH_TH_VLSEG6BFFV 0xb1000007 +#define MASK_TH_VLSEG6BFFV 0xfdf0707f +#define MATCH_TH_VLSEG6HFFV 0xb1005007 +#define MASK_TH_VLSEG6HFFV 0xfdf0707f +#define MATCH_TH_VLSEG6WFFV 0xb1006007 +#define MASK_TH_VLSEG6WFFV 0xfdf0707f +#define MATCH_TH_VLSEG6BUFFV 0xa1000007 +#define MASK_TH_VLSEG6BUFFV 0xfdf0707f +#define MATCH_TH_VLSEG6HUFFV 0xa1005007 +#define MASK_TH_VLSEG6HUFFV 0xfdf0707f +#define MATCH_TH_VLSEG6WUFFV 0xa1006007 +#define MASK_TH_VLSEG6WUFFV 0xfdf0707f +#define MATCH_TH_VLSEG6EFFV 0xa1007007 +#define MASK_TH_VLSEG6EFFV 0xfdf0707f +#define MATCH_TH_VLSEG7BFFV 0xd1000007 +#define MASK_TH_VLSEG7BFFV 0xfdf0707f +#define MATCH_TH_VLSEG7HFFV 0xd1005007 +#define MASK_TH_VLSEG7HFFV 0xfdf0707f +#define MATCH_TH_VLSEG7WFFV 0xd1006007 +#define MASK_TH_VLSEG7WFFV 0xfdf0707f +#define MATCH_TH_VLSEG7BUFFV 0xc1000007 +#define MASK_TH_VLSEG7BUFFV 0xfdf0707f +#define MATCH_TH_VLSEG7HUFFV 0xc1005007 +#define MASK_TH_VLSEG7HUFFV 0xfdf0707f +#define MATCH_TH_VLSEG7WUFFV 0xc1006007 +#define MASK_TH_VLSEG7WUFFV 0xfdf0707f +#define MATCH_TH_VLSEG7EFFV 0xc1007007 +#define MASK_TH_VLSEG7EFFV 0xfdf0707f +#define MATCH_TH_VLSEG8BFFV 0xf1000007 +#define MASK_TH_VLSEG8BFFV 0xfdf0707f +#define MATCH_TH_VLSEG8HFFV 0xf1005007 +#define MASK_TH_VLSEG8HFFV 0xfdf0707f +#define MATCH_TH_VLSEG8WFFV 0xf1006007 +#define MASK_TH_VLSEG8WFFV 0xfdf0707f +#define MATCH_TH_VLSEG8BUFFV 0xe1000007 +#define MASK_TH_VLSEG8BUFFV 0xfdf0707f +#define MATCH_TH_VLSEG8HUFFV 0xe1005007 +#define MASK_TH_VLSEG8HUFFV 0xfdf0707f +#define MATCH_TH_VLSEG8WUFFV 0xe1006007 +#define MASK_TH_VLSEG8WUFFV 0xfdf0707f +#define MATCH_TH_VLSEG8EFFV 0xe1007007 +#define MASK_TH_VLSEG8EFFV 0xfdf0707f /* Vendor-specific (Ventana Microsystems) XVentanaCondOps instructions */ #define MATCH_VT_MASKC 0x607b #define MASK_VT_MASKC 0xfe00707f diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h index a26ef8abf12..f9c3293b29b 100644 --- a/include/opcode/riscv.h +++ b/include/opcode/riscv.h @@ -468,6 +468,7 @@ enum riscv_insn_class INSN_CLASS_XTHEADMEMPAIR, INSN_CLASS_XTHEADSYNC, INSN_CLASS_XTHEADVECTOR, + INSN_CLASS_XTHEADZVLSSEG, INSN_CLASS_XVENTANACONDOPS, }; diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c index 05bdce449f4..d089aa4958d 100644 --- a/opcodes/riscv-opc.c +++ b/opcodes/riscv-opc.c @@ -2281,6 +2281,286 @@ const struct riscv_opcode riscv_opcodes[] = {"th.vlhuff.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s)Vm", MATCH_TH_VLHUFFV, MASK_TH_VLHUFFV, match_opcode, INSN_DREF }, {"th.vlwuff.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s)Vm", MATCH_TH_VLWUFFV, MASK_TH_VLWUFFV, match_opcode, INSN_DREF }, {"th.vleff.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s)Vm", MATCH_TH_VLEFFV, MASK_TH_VLEFFV, match_opcode, INSN_DREF }, +{"th.vlseg2b.v", 0, INSN_CLASS_XTHEADZVLSSEG, "Vd,0(s)Vm", MATCH_TH_VLSEG2BV, MASK_TH_VLSEG2BV, match_opcode, INSN_DREF }, +{"th.vlseg2h.v", 0, INSN_CLASS_XTHEADZVLSSEG, "Vd,0(s)Vm", MATCH_TH_VLSEG2HV, MASK_TH_VLSEG2HV, match_opcode, INSN_DREF }, +{"th.vlseg2w.v", 0, INSN_CLASS_XTHEADZVLSSEG, "Vd,0(s)Vm", MATCH_TH_VLSEG2WV, MASK_TH_VLSEG2WV, match_opcode, INSN_DREF }, +{"th.vlseg2bu.v", 0, INSN_CLASS_XTHEADZVLSSEG, "Vd,0(s)Vm", MATCH_TH_VLSEG2BUV, MASK_TH_VLSEG2BUV, match_opcode, INSN_DREF }, +{"th.vlseg2hu.v", 0, INSN_CLASS_XTHEADZVLSSEG, "Vd,0(s)Vm", MATCH_TH_VLSEG2HUV, MASK_TH_VLSEG2HUV, match_opcode, INSN_DREF }, +{"th.vlseg2wu.v", 0, INSN_CLASS_XTHEADZVLSSEG, "Vd,0(s)Vm", MATCH_TH_VLSEG2WUV, MASK_TH_VLSEG2WUV, match_opcode, INSN_DREF }, +{"th.vlseg2e.v", 0, INSN_CLASS_XTHEADZVLSSEG, "Vd,0(s)Vm", MATCH_TH_VLSEG2EV, MASK_TH_VLSEG2EV, match_opcode, INSN_DREF }, +{"th.vsseg2b.v", 0, INSN_CLASS_XTHEADZVLSSEG, "Vd,0(s)Vm", MATCH_TH_VSSEG2BV, MASK_TH_VSSEG2BV, match_opcode, INSN_DREF }, +{"th.vsseg2h.v", 0, INSN_CLASS_XTHEADZVLSSEG, "Vd,0(s)Vm", MATCH_TH_VSSEG2HV, MASK_TH_VSSEG2HV, match_opcode, INSN_DREF }, +{"th.vsseg2w.v", 0, INSN_CLASS_XTHEADZVLSSEG, "Vd,0(s)Vm", MATCH_TH_VSSEG2WV, MASK_TH_VSSEG2WV, match_opcode, INSN_DREF }, +{"th.vsseg2e.v", 0, INSN_CLASS_XTHEADZVLSSEG, "Vd,0(s)Vm", MATCH_TH_VSSEG2EV, MASK_TH_VSSEG2EV, match_opcode, INSN_DREF }, +{"th.vlseg3b.v", 0, INSN_CLASS_XTHEADZVLSSEG, "Vd,0(s)Vm", MATCH_TH_VLSEG3BV, MASK_TH_VLSEG3BV, match_opcode, INSN_DREF }, +{"th.vlseg3h.v", 0, INSN_CLASS_XTHEADZVLSSEG, "Vd,0(s)Vm", MATCH_TH_VLSEG3HV, MASK_TH_VLSEG3HV, match_opcode, INSN_DREF }, +{"th.vlseg3w.v", 0, INSN_CLASS_XTHEADZVLSSEG, "Vd,0(s)Vm", MATCH_TH_VLSEG3WV, MASK_TH_VLSEG3WV, match_opcode, INSN_DREF }, +{"th.vlseg3bu.v", 0, INSN_CLASS_XTHEADZVLSSEG, "Vd,0(s)Vm", MATCH_TH_VLSEG3BUV, MASK_TH_VLSEG3BUV, match_opcode, INSN_DREF }, +{"th.vlseg3hu.v", 0, INSN_CLASS_XTHEADZVLSSEG, "Vd,0(s)Vm", MATCH_TH_VLSEG3HUV, MASK_TH_VLSEG3HUV, match_opcode, INSN_DREF }, +{"th.vlseg3wu.v", 0, INSN_CLASS_XTHEADZVLSSEG, "Vd,0(s)Vm", MATCH_TH_VLSEG3WUV, MASK_TH_VLSEG3WUV, match_opcode, INSN_DREF }, +{"th.vlseg3e.v", 0, INSN_CLASS_XTHEADZVLSSEG, "Vd,0(s)Vm", MATCH_TH_VLSEG3EV, MASK_TH_VLSEG3EV, match_opcode, INSN_DREF }, +{"th.vsseg3b.v", 0, INSN_CLASS_XTHEADZVLSSEG, "Vd,0(s)Vm", MATCH_TH_VSSEG3BV, MASK_TH_VSSEG3BV, match_opcode, INSN_DREF }, +{"th.vsseg3h.v", 0, INSN_CLASS_XTHEADZVLSSEG, "Vd,0(s)Vm", MATCH_TH_VSSEG3HV, MASK_TH_VSSEG3HV, match_opcode, INSN_DREF }, +{"th.vsseg3w.v", 0, INSN_CLASS_XTHEADZVLSSEG, "Vd,0(s)Vm", MATCH_TH_VSSEG3WV, MASK_TH_VSSEG3WV, match_opcode, INSN_DREF }, +{"th.vsseg3e.v", 0, INSN_CLASS_XTHEADZVLSSEG, "Vd,0(s)Vm", MATCH_TH_VSSEG3EV, MASK_TH_VSSEG3EV, match_opcode, INSN_DREF }, +{"th.vlseg4b.v", 0, INSN_CLASS_XTHEADZVLSSEG, "Vd,0(s)Vm", MATCH_TH_VLSEG4BV, MASK_TH_VLSEG4BV, match_opcode, INSN_DREF }, +{"th.vlseg4h.v", 0, INSN_CLASS_XTHEADZVLSSEG, "Vd,0(s)Vm", MATCH_TH_VLSEG4HV, MASK_TH_VLSEG4HV, match_opcode, INSN_DREF }, +{"th.vlseg4w.v", 0, INSN_CLASS_XTHEADZVLSSEG, "Vd,0(s)Vm", MATCH_TH_VLSEG4WV, MASK_TH_VLSEG4WV, match_opcode, INSN_DREF }, +{"th.vlseg4bu.v", 0, INSN_CLASS_XTHEADZVLSSEG, "Vd,0(s)Vm", MATCH_TH_VLSEG4BUV, MASK_TH_VLSEG4BUV, match_opcode, INSN_DREF }, +{"th.vlseg4hu.v", 0, INSN_CLASS_XTHEADZVLSSEG, "Vd,0(s)Vm", MATCH_TH_VLSEG4HUV, MASK_TH_VLSEG4HUV, match_opcode, INSN_DREF }, +{"th.vlseg4wu.v", 0, INSN_CLASS_XTHEADZVLSSEG, "Vd,0(s)Vm", MATCH_TH_VLSEG4WUV, MASK_TH_VLSEG4WUV, match_opcode, INSN_DREF }, +{"th.vlseg4e.v", 0, INSN_CLASS_XTHEADZVLSSEG, "Vd,0(s)Vm", MATCH_TH_VLSEG4EV, MASK_TH_VLSEG4EV, match_opcode, INSN_DREF }, +{"th.vsseg4b.v", 0, INSN_CLASS_XTHEADZVLSSEG, "Vd,0(s)Vm", MATCH_TH_VSSEG4BV, MASK_TH_VSSEG4BV, match_opcode, INSN_DREF }, +{"th.vsseg4h.v", 0, INSN_CLASS_XTHEADZVLSSEG, "Vd,0(s)Vm", MATCH_TH_VSSEG4HV, MASK_TH_VSSEG4HV, match_opcode, INSN_DREF }, +{"th.vsseg4w.v", 0, INSN_CLASS_XTHEADZVLSSEG, "Vd,0(s)Vm", MATCH_TH_VSSEG4WV, MASK_TH_VSSEG4WV, match_opcode, INSN_DREF }, +{"th.vsseg4e.v", 0, INSN_CLASS_XTHEADZVLSSEG, "Vd,0(s)Vm", MATCH_TH_VSSEG4EV, MASK_TH_VSSEG4EV, match_opcode, INSN_DREF }, +{"th.vlseg5b.v", 0, INSN_CLASS_XTHEADZVLSSEG, "Vd,0(s)Vm", MATCH_TH_VLSEG5BV, MASK_TH_VLSEG5BV, match_opcode, INSN_DREF }, +{"th.vlseg5h.v", 0, INSN_CLASS_XTHEADZVLSSEG, "Vd,0(s)Vm", MATCH_TH_VLSEG5HV, MASK_TH_VLSEG5HV, match_opcode, INSN_DREF }, +{"th.vlseg5w.v", 0, INSN_CLASS_XTHEADZVLSSEG, "Vd,0(s)Vm", MATCH_TH_VLSEG5WV, MASK_TH_VLSEG5WV, match_opcode, INSN_DREF }, +{"th.vlseg5bu.v", 0, INSN_CLASS_XTHEADZVLSSEG, "Vd,0(s)Vm", MATCH_TH_VLSEG5BUV, MASK_TH_VLSEG5BUV, match_opcode, INSN_DREF }, +{"th.vlseg5hu.v", 0, INSN_CLASS_XTHEADZVLSSEG, "Vd,0(s)Vm", MATCH_TH_VLSEG5HUV, MASK_TH_VLSEG5HUV, match_opcode, INSN_DREF }, +{"th.vlseg5wu.v", 0, INSN_CLASS_XTHEADZVLSSEG, "Vd,0(s)Vm", MATCH_TH_VLSEG5WUV, MASK_TH_VLSEG5WUV, match_opcode, INSN_DREF }, +{"th.vlseg5e.v", 0, INSN_CLASS_XTHEADZVLSSEG, "Vd,0(s)Vm", MATCH_TH_VLSEG5EV, MASK_TH_VLSEG5EV, match_opcode, INSN_DREF }, +{"th.vsseg5b.v", 0, INSN_CLASS_XTHEADZVLSSEG, "Vd,0(s)Vm", MATCH_TH_VSSEG5BV, MASK_TH_VSSEG5BV, match_opcode, INSN_DREF }, +{"th.vsseg5h.v", 0, INSN_CLASS_XTHEADZVLSSEG, "Vd,0(s)Vm", MATCH_TH_VSSEG5HV, MASK_TH_VSSEG5HV, match_opcode, INSN_DREF }, +{"th.vsseg5w.v", 0, INSN_CLASS_XTHEADZVLSSEG, "Vd,0(s)Vm", MATCH_TH_VSSEG5WV, MASK_TH_VSSEG5WV, match_opcode, INSN_DREF }, +{"th.vsseg5e.v", 0, INSN_CLASS_XTHEADZVLSSEG, "Vd,0(s)Vm", MATCH_TH_VSSEG5EV, MASK_TH_VSSEG5EV, match_opcode, INSN_DREF }, +{"th.vlseg6b.v", 0, INSN_CLASS_XTHEADZVLSSEG, "Vd,0(s)Vm", MATCH_TH_VLSEG6BV, MASK_TH_VLSEG6BV, match_opcode, INSN_DREF }, +{"th.vlseg6h.v", 0, INSN_CLASS_XTHEADZVLSSEG, "Vd,0(s)Vm", MATCH_TH_VLSEG6HV, MASK_TH_VLSEG6HV, match_opcode, INSN_DREF }, +{"th.vlseg6w.v", 0, INSN_CLASS_XTHEADZVLSSEG, "Vd,0(s)Vm", MATCH_TH_VLSEG6WV, MASK_TH_VLSEG6WV, match_opcode, INSN_DREF }, +{"th.vlseg6bu.v", 0, INSN_CLASS_XTHEADZVLSSEG, "Vd,0(s)Vm", MATCH_TH_VLSEG6BUV, MASK_TH_VLSEG6BUV, match_opcode, INSN_DREF }, +{"th.vlseg6hu.v", 0, INSN_CLASS_XTHEADZVLSSEG, "Vd,0(s)Vm", MATCH_TH_VLSEG6HUV, MASK_TH_VLSEG6HUV, match_opcode, INSN_DREF }, +{"th.vlseg6wu.v", 0, INSN_CLASS_XTHEADZVLSSEG, "Vd,0(s)Vm", MATCH_TH_VLSEG6WUV, MASK_TH_VLSEG6WUV, match_opcode, INSN_DREF }, +{"th.vlseg6e.v", 0, INSN_CLASS_XTHEADZVLSSEG, "Vd,0(s)Vm", MATCH_TH_VLSEG6EV, MASK_TH_VLSEG6EV, match_opcode, INSN_DREF }, +{"th.vsseg6b.v", 0, INSN_CLASS_XTHEADZVLSSEG, "Vd,0(s)Vm", MATCH_TH_VSSEG6BV, MASK_TH_VSSEG6BV, match_opcode, INSN_DREF }, +{"th.vsseg6h.v", 0, INSN_CLASS_XTHEADZVLSSEG, "Vd,0(s)Vm", MATCH_TH_VSSEG6HV, MASK_TH_VSSEG6HV, match_opcode, INSN_DREF }, +{"th.vsseg6w.v", 0, INSN_CLASS_XTHEADZVLSSEG, "Vd,0(s)Vm", MATCH_TH_VSSEG6WV, MASK_TH_VSSEG6WV, match_opcode, INSN_DREF }, +{"th.vsseg6e.v", 0, INSN_CLASS_XTHEADZVLSSEG, "Vd,0(s)Vm", MATCH_TH_VSSEG6EV, MASK_TH_VSSEG6EV, match_opcode, INSN_DREF }, +{"th.vlseg7b.v", 0, INSN_CLASS_XTHEADZVLSSEG, "Vd,0(s)Vm", MATCH_TH_VLSEG7BV, MASK_TH_VLSEG7BV, match_opcode, INSN_DREF }, +{"th.vlseg7h.v", 0, INSN_CLASS_XTHEADZVLSSEG, "Vd,0(s)Vm", MATCH_TH_VLSEG7HV, MASK_TH_VLSEG7HV, match_opcode, INSN_DREF }, +{"th.vlseg7w.v", 0, INSN_CLASS_XTHEADZVLSSEG, "Vd,0(s)Vm", MATCH_TH_VLSEG7WV, MASK_TH_VLSEG7WV, match_opcode, INSN_DREF }, +{"th.vlseg7bu.v", 0, INSN_CLASS_XTHEADZVLSSEG, "Vd,0(s)Vm", MATCH_TH_VLSEG7BUV, MASK_TH_VLSEG7BUV, match_opcode, INSN_DREF }, +{"th.vlseg7hu.v", 0, INSN_CLASS_XTHEADZVLSSEG, "Vd,0(s)Vm", MATCH_TH_VLSEG7HUV, MASK_TH_VLSEG7HUV, match_opcode, INSN_DREF }, +{"th.vlseg7wu.v", 0, INSN_CLASS_XTHEADZVLSSEG, "Vd,0(s)Vm", MATCH_TH_VLSEG7WUV, MASK_TH_VLSEG7WUV, match_opcode, INSN_DREF }, +{"th.vlseg7e.v", 0, INSN_CLASS_XTHEADZVLSSEG, "Vd,0(s)Vm", MATCH_TH_VLSEG7EV, MASK_TH_VLSEG7EV, match_opcode, INSN_DREF }, +{"th.vsseg7b.v", 0, INSN_CLASS_XTHEADZVLSSEG, "Vd,0(s)Vm", MATCH_TH_VSSEG7BV, MASK_TH_VSSEG7BV, match_opcode, INSN_DREF }, +{"th.vsseg7h.v", 0, INSN_CLASS_XTHEADZVLSSEG, "Vd,0(s)Vm", MATCH_TH_VSSEG7HV, MASK_TH_VSSEG7HV, match_opcode, INSN_DREF }, +{"th.vsseg7w.v", 0, INSN_CLASS_XTHEADZVLSSEG, "Vd,0(s)Vm", MATCH_TH_VSSEG7WV, MASK_TH_VSSEG7WV, match_opcode, INSN_DREF }, +{"th.vsseg7e.v", 0, INSN_CLASS_XTHEADZVLSSEG, "Vd,0(s)Vm", MATCH_TH_VSSEG7EV, MASK_TH_VSSEG7EV, match_opcode, INSN_DREF }, +{"th.vlseg8b.v", 0, INSN_CLASS_XTHEADZVLSSEG, "Vd,0(s)Vm", MATCH_TH_VLSEG8BV, MASK_TH_VLSEG8BV, match_opcode, INSN_DREF }, +{"th.vlseg8h.v", 0, INSN_CLASS_XTHEADZVLSSEG, "Vd,0(s)Vm", MATCH_TH_VLSEG8HV, MASK_TH_VLSEG8HV, match_opcode, INSN_DREF }, +{"th.vlseg8w.v", 0, INSN_CLASS_XTHEADZVLSSEG, "Vd,0(s)Vm", MATCH_TH_VLSEG8WV, MASK_TH_VLSEG8WV, match_opcode, INSN_DREF }, +{"th.vlseg8bu.v", 0, INSN_CLASS_XTHEADZVLSSEG, "Vd,0(s)Vm", MATCH_TH_VLSEG8BUV, MASK_TH_VLSEG8BUV, match_opcode, INSN_DREF }, +{"th.vlseg8hu.v", 0, INSN_CLASS_XTHEADZVLSSEG, "Vd,0(s)Vm", MATCH_TH_VLSEG8HUV, MASK_TH_VLSEG8HUV, match_opcode, INSN_DREF }, +{"th.vlseg8wu.v", 0, INSN_CLASS_XTHEADZVLSSEG, "Vd,0(s)Vm", MATCH_TH_VLSEG8WUV, MASK_TH_VLSEG8WUV, match_opcode, INSN_DREF }, +{"th.vlseg8e.v", 0, INSN_CLASS_XTHEADZVLSSEG, "Vd,0(s)Vm", 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"Vd,0(s)Vm", MATCH_TH_VLSEG5BUFFV, MASK_TH_VLSEG5BUFFV, match_opcode, INSN_DREF }, +{"th.vlseg5huff.v", 0, INSN_CLASS_XTHEADZVLSSEG, "Vd,0(s)Vm", MATCH_TH_VLSEG5HUFFV, MASK_TH_VLSEG5HUFFV, match_opcode, INSN_DREF }, +{"th.vlseg5wuff.v", 0, INSN_CLASS_XTHEADZVLSSEG, "Vd,0(s)Vm", MATCH_TH_VLSEG5WUFFV, MASK_TH_VLSEG5WUFFV, match_opcode, INSN_DREF }, +{"th.vlseg5eff.v", 0, INSN_CLASS_XTHEADZVLSSEG, "Vd,0(s)Vm", MATCH_TH_VLSEG5EFFV, MASK_TH_VLSEG5EFFV, match_opcode, INSN_DREF }, +{"th.vlseg6bff.v", 0, INSN_CLASS_XTHEADZVLSSEG, "Vd,0(s)Vm", MATCH_TH_VLSEG6BFFV, MASK_TH_VLSEG6BFFV, match_opcode, INSN_DREF }, +{"th.vlseg6hff.v", 0, INSN_CLASS_XTHEADZVLSSEG, "Vd,0(s)Vm", MATCH_TH_VLSEG6HFFV, MASK_TH_VLSEG6HFFV, match_opcode, INSN_DREF }, +{"th.vlseg6wff.v", 0, INSN_CLASS_XTHEADZVLSSEG, "Vd,0(s)Vm", MATCH_TH_VLSEG6WFFV, MASK_TH_VLSEG6WFFV, match_opcode, INSN_DREF }, +{"th.vlseg6buff.v", 0, INSN_CLASS_XTHEADZVLSSEG, "Vd,0(s)Vm", MATCH_TH_VLSEG6BUFFV, MASK_TH_VLSEG6BUFFV, match_opcode, INSN_DREF }, +{"th.vlseg6huff.v", 0, INSN_CLASS_XTHEADZVLSSEG, "Vd,0(s)Vm", MATCH_TH_VLSEG6HUFFV, MASK_TH_VLSEG6HUFFV, match_opcode, INSN_DREF }, +{"th.vlseg6wuff.v", 0, INSN_CLASS_XTHEADZVLSSEG, "Vd,0(s)Vm", MATCH_TH_VLSEG6WUFFV, MASK_TH_VLSEG6WUFFV, match_opcode, INSN_DREF }, +{"th.vlseg6eff.v", 0, INSN_CLASS_XTHEADZVLSSEG, "Vd,0(s)Vm", MATCH_TH_VLSEG6EFFV, MASK_TH_VLSEG6EFFV, match_opcode, INSN_DREF }, +{"th.vlseg7bff.v", 0, INSN_CLASS_XTHEADZVLSSEG, "Vd,0(s)Vm", MATCH_TH_VLSEG7BFFV, MASK_TH_VLSEG7BFFV, match_opcode, INSN_DREF }, +{"th.vlseg7hff.v", 0, INSN_CLASS_XTHEADZVLSSEG, "Vd,0(s)Vm", MATCH_TH_VLSEG7HFFV, MASK_TH_VLSEG7HFFV, match_opcode, INSN_DREF }, +{"th.vlseg7wff.v", 0, INSN_CLASS_XTHEADZVLSSEG, "Vd,0(s)Vm", MATCH_TH_VLSEG7WFFV, MASK_TH_VLSEG7WFFV, match_opcode, INSN_DREF }, +{"th.vlseg7buff.v", 0, INSN_CLASS_XTHEADZVLSSEG, "Vd,0(s)Vm", MATCH_TH_VLSEG7BUFFV, MASK_TH_VLSEG7BUFFV, match_opcode, INSN_DREF }, +{"th.vlseg7huff.v", 0, INSN_CLASS_XTHEADZVLSSEG, "Vd,0(s)Vm", MATCH_TH_VLSEG7HUFFV, MASK_TH_VLSEG7HUFFV, match_opcode, INSN_DREF }, +{"th.vlseg7wuff.v", 0, INSN_CLASS_XTHEADZVLSSEG, "Vd,0(s)Vm", MATCH_TH_VLSEG7WUFFV, MASK_TH_VLSEG7WUFFV, match_opcode, INSN_DREF }, +{"th.vlseg7eff.v", 0, INSN_CLASS_XTHEADZVLSSEG, "Vd,0(s)Vm", MATCH_TH_VLSEG7EFFV, MASK_TH_VLSEG7EFFV, match_opcode, INSN_DREF }, +{"th.vlseg8bff.v", 0, INSN_CLASS_XTHEADZVLSSEG, "Vd,0(s)Vm", MATCH_TH_VLSEG8BFFV, MASK_TH_VLSEG8BFFV, match_opcode, INSN_DREF }, +{"th.vlseg8hff.v", 0, INSN_CLASS_XTHEADZVLSSEG, "Vd,0(s)Vm", MATCH_TH_VLSEG8HFFV, MASK_TH_VLSEG8HFFV, match_opcode, INSN_DREF }, +{"th.vlseg8wff.v", 0, INSN_CLASS_XTHEADZVLSSEG, "Vd,0(s)Vm", MATCH_TH_VLSEG8WFFV, MASK_TH_VLSEG8WFFV, match_opcode, INSN_DREF }, +{"th.vlseg8buff.v", 0, INSN_CLASS_XTHEADZVLSSEG, "Vd,0(s)Vm", MATCH_TH_VLSEG8BUFFV, MASK_TH_VLSEG8BUFFV, match_opcode, INSN_DREF }, +{"th.vlseg8huff.v", 0, INSN_CLASS_XTHEADZVLSSEG, "Vd,0(s)Vm", MATCH_TH_VLSEG8HUFFV, MASK_TH_VLSEG8HUFFV, match_opcode, INSN_DREF }, +{"th.vlseg8wuff.v", 0, INSN_CLASS_XTHEADZVLSSEG, "Vd,0(s)Vm", MATCH_TH_VLSEG8WUFFV, MASK_TH_VLSEG8WUFFV, match_opcode, INSN_DREF }, +{"th.vlseg8eff.v", 0, INSN_CLASS_XTHEADZVLSSEG, "Vd,0(s)Vm", MATCH_TH_VLSEG8EFFV, MASK_TH_VLSEG8EFFV, match_opcode, INSN_DREF }, /* Vendor-specific (Ventana Microsystems) XVentanaCondOps instructions */ {"vt.maskc", 64, INSN_CLASS_XVENTANACONDOPS, "d,s,t", MATCH_VT_MASKC, MASK_VT_MASKC, match_opcode, 0 }, -- 2.17.1