From: Jin Ma <jinma@linux.alibaba.com>
To: binutils@sourceware.org, nelson@rivosinc.com
Cc: christoph.muellner@vrull.eu, lifang_xia@linux.alibaba.com,
jinma.contrib@gmail.com, Jin Ma <jinma@linux.alibaba.com>
Subject: [PATCH 09/12] RISC-V: Add floating-point arithmetic instructions for T-Head VECTOR vendor extension
Date: Fri, 10 Nov 2023 15:32:47 +0800 [thread overview]
Message-ID: <20231110073247.2005-1-jinma@linux.alibaba.com> (raw)
In-Reply-To: <20231110071759.1640-1-jinma@linux.alibaba.com>
T-Head has a range of vendor-specific instructions. Therefore
it makes sense to group them into smaller chunks in form of
vendor extensions.
This patch adds floating-point arithmetic instructions for the
"XTheadVector" extension. The 'th' prefix and the
"XTheadVector" extension are documented in a PR for the
RISC-V toolchain conventions ([1]).
[1] https://github.com/riscv-non-isa/riscv-toolchain-conventions/pull/19
Co-developed-by: Lifang Xia <lifang_xia@linux.alibaba.com>
Co-developed-by: Christoph Müllner <christoph.muellner@vrull.eu>
gas/ChangeLog:
* testsuite/gas/riscv/x-thead-vector.d: Add tests for
floating-point arithmetic instructions.
* testsuite/gas/riscv/x-thead-vector.s: Likewise.
include/ChangeLog:
* opcode/riscv-opc.h (MATCH_TH_VFADDVV): New.
opcodes/ChangeLog:
* riscv-opc.c: Likewise.
---
gas/testsuite/gas/riscv/x-thead-vector.d | 170 ++++++++++++++++++++
gas/testsuite/gas/riscv/x-thead-vector.s | 188 +++++++++++++++++++++++
include/opcode/riscv-opc.h | 168 ++++++++++++++++++++
opcodes/riscv-opc.c | 86 +++++++++++
4 files changed, 612 insertions(+)
diff --git a/gas/testsuite/gas/riscv/x-thead-vector.d b/gas/testsuite/gas/riscv/x-thead-vector.d
index 9a199177f37..09e4a9c2f73 100644
--- a/gas/testsuite/gas/riscv/x-thead-vector.d
+++ b/gas/testsuite/gas/riscv/x-thead-vector.d
@@ -550,3 +550,173 @@ Disassembly of section .text:
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+[ ]+[0-9a-f]+:[ ]+8a889257[ ]+th.vfncvt.x.f.v[ ]+v4,v8
+[ ]+[0-9a-f]+:[ ]+8a891257[ ]+th.vfncvt.f.xu.v[ ]+v4,v8
+[ ]+[0-9a-f]+:[ ]+8a899257[ ]+th.vfncvt.f.x.v[ ]+v4,v8
+[ ]+[0-9a-f]+:[ ]+8a8a1257[ ]+th.vfncvt.f.f.v[ ]+v4,v8
+[ ]+[0-9a-f]+:[ ]+88881257[ ]+th.vfncvt.xu.f.v[ ]+v4,v8,v0.t
+[ ]+[0-9a-f]+:[ ]+88889257[ ]+th.vfncvt.x.f.v[ ]+v4,v8,v0.t
+[ ]+[0-9a-f]+:[ ]+88891257[ ]+th.vfncvt.f.xu.v[ ]+v4,v8,v0.t
+[ ]+[0-9a-f]+:[ ]+88899257[ ]+th.vfncvt.f.x.v[ ]+v4,v8,v0.t
+[ ]+[0-9a-f]+:[ ]+888a1257[ ]+th.vfncvt.f.f.v[ ]+v4,v8,v0.t
diff --git a/gas/testsuite/gas/riscv/x-thead-vector.s b/gas/testsuite/gas/riscv/x-thead-vector.s
index b2fbb0c343f..f7de24fdd63 100644
--- a/gas/testsuite/gas/riscv/x-thead-vector.s
+++ b/gas/testsuite/gas/riscv/x-thead-vector.s
@@ -564,3 +564,191 @@
th.vnclip.vx v4, v8, a1, v0.t
th.vnclip.vi v4, v8, 1, v0.t
th.vnclip.vi v4, v8, 31, v0.t
+
+ th.vfadd.vv v4, v8, v12
+ th.vfadd.vf v4, v8, fa2
+ th.vfadd.vv v4, v8, v12, v0.t
+ th.vfadd.vf v4, v8, fa2, v0.t
+ th.vfsub.vv v4, v8, v12
+ th.vfsub.vf v4, v8, fa2
+ th.vfsub.vv v4, v8, v12, v0.t
+ th.vfsub.vf v4, v8, fa2, v0.t
+ th.vfrsub.vf v4, v8, fa2
+ th.vfrsub.vf v4, v8, fa2, v0.t
+
+ th.vfwadd.vv v4, v8, v12
+ th.vfwadd.vf v4, v8, fa2
+ th.vfwadd.vv v4, v8, v12, v0.t
+ th.vfwadd.vf v4, v8, fa2, v0.t
+ th.vfwsub.vv v4, v8, v12
+ th.vfwsub.vf v4, v8, fa2
+ th.vfwsub.vv v4, v8, v12, v0.t
+ th.vfwsub.vf v4, v8, fa2, v0.t
+ th.vfwadd.wv v4, v8, v12
+ th.vfwadd.wf v4, v8, fa2
+ th.vfwadd.wv v4, v8, v12, v0.t
+ th.vfwadd.wf v4, v8, fa2, v0.t
+ th.vfwsub.wv v4, v8, v12
+ th.vfwsub.wf v4, v8, fa2
+ th.vfwsub.wv v4, v8, v12, v0.t
+ th.vfwsub.wf v4, v8, fa2, v0.t
+
+ th.vfmul.vv v4, v8, v12
+ th.vfmul.vf v4, v8, fa2
+ th.vfmul.vv v4, v8, v12, v0.t
+ th.vfmul.vf v4, v8, fa2, v0.t
+ th.vfdiv.vv v4, v8, v12
+ th.vfdiv.vf v4, v8, fa2
+ th.vfdiv.vv v4, v8, v12, v0.t
+ th.vfdiv.vf v4, v8, fa2, v0.t
+ th.vfrdiv.vf v4, v8, fa2
+ th.vfrdiv.vf v4, v8, fa2, v0.t
+
+ th.vfwmul.vv v4, v8, v12
+ th.vfwmul.vf v4, v8, fa2
+ th.vfwmul.vv v4, v8, v12, v0.t
+ th.vfwmul.vf v4, v8, fa2, v0.t
+
+ th.vfmadd.vv v4, v12, v8
+ th.vfmadd.vf v4, fa2, v8
+ th.vfnmadd.vv v4, v12, v8
+ th.vfnmadd.vf v4, fa2, v8
+ th.vfmsub.vv v4, v12, v8
+ th.vfmsub.vf v4, fa2, v8
+ th.vfnmsub.vv v4, v12, v8
+ th.vfnmsub.vf v4, fa2, v8
+ th.vfmadd.vv v4, v12, v8, v0.t
+ th.vfmadd.vf v4, fa2, v8, v0.t
+ th.vfnmadd.vv v4, v12, v8, v0.t
+ th.vfnmadd.vf v4, fa2, v8, v0.t
+ th.vfmsub.vv v4, v12, v8, v0.t
+ th.vfmsub.vf v4, fa2, v8, v0.t
+ th.vfnmsub.vv v4, v12, v8, v0.t
+ th.vfnmsub.vf v4, fa2, v8, v0.t
+ th.vfmacc.vv v4, v12, v8
+ th.vfmacc.vf v4, fa2, v8
+ th.vfnmacc.vv v4, v12, v8
+ th.vfnmacc.vf v4, fa2, v8
+ th.vfmsac.vv v4, v12, v8
+ th.vfmsac.vf v4, fa2, v8
+ th.vfnmsac.vv v4, v12, v8
+ th.vfnmsac.vf v4, fa2, v8
+ th.vfmacc.vv v4, v12, v8, v0.t
+ th.vfmacc.vf v4, fa2, v8, v0.t
+ th.vfnmacc.vv v4, v12, v8, v0.t
+ th.vfnmacc.vf v4, fa2, v8, v0.t
+ th.vfmsac.vv v4, v12, v8, v0.t
+ th.vfmsac.vf v4, fa2, v8, v0.t
+ th.vfnmsac.vv v4, v12, v8, v0.t
+ th.vfnmsac.vf v4, fa2, v8, v0.t
+
+ th.vfwmacc.vv v4, v12, v8
+ th.vfwmacc.vf v4, fa2, v8
+ th.vfwnmacc.vv v4, v12, v8
+ th.vfwnmacc.vf v4, fa2, v8
+ th.vfwmsac.vv v4, v12, v8
+ th.vfwmsac.vf v4, fa2, v8
+ th.vfwnmsac.vv v4, v12, v8
+ th.vfwnmsac.vf v4, fa2, v8
+ th.vfwmacc.vv v4, v12, v8, v0.t
+ th.vfwmacc.vf v4, fa2, v8, v0.t
+ th.vfwnmacc.vv v4, v12, v8, v0.t
+ th.vfwnmacc.vf v4, fa2, v8, v0.t
+ th.vfwmsac.vv v4, v12, v8, v0.t
+ th.vfwmsac.vf v4, fa2, v8, v0.t
+ th.vfwnmsac.vv v4, v12, v8, v0.t
+ th.vfwnmsac.vf v4, fa2, v8, v0.t
+
+ th.vfsqrt.v v4, v8
+ th.vfsqrt.v v4, v8, v0.t
+
+ th.vfmin.vv v4, v8, v12
+ th.vfmin.vf v4, v8, fa2
+ th.vfmax.vv v4, v8, v12
+ th.vfmax.vf v4, v8, fa2
+ th.vfmin.vv v4, v8, v12, v0.t
+ th.vfmin.vf v4, v8, fa2, v0.t
+ th.vfmax.vv v4, v8, v12, v0.t
+ th.vfmax.vf v4, v8, fa2, v0.t
+
+ th.vfsgnj.vv v4, v8, v12
+ th.vfsgnj.vf v4, v8, fa2
+ th.vfsgnjn.vv v4, v8, v12
+ th.vfsgnjn.vf v4, v8, fa2
+ th.vfsgnjx.vv v4, v8, v12
+ th.vfsgnjx.vf v4, v8, fa2
+ th.vfsgnj.vv v4, v8, v12, v0.t
+ th.vfsgnj.vf v4, v8, fa2, v0.t
+ th.vfsgnjn.vv v4, v8, v12, v0.t
+ th.vfsgnjn.vf v4, v8, fa2, v0.t
+ th.vfsgnjx.vv v4, v8, v12, v0.t
+ th.vfsgnjx.vf v4, v8, fa2, v0.t
+
+ # Aliases
+ th.vmfgt.vv v4, v8, v12
+ th.vmfge.vv v4, v8, v12
+ th.vmfgt.vv v4, v8, v12, v0.t
+ th.vmfge.vv v4, v8, v12, v0.t
+
+ th.vmfeq.vv v4, v8, v12
+ th.vmfeq.vf v4, v8, fa2
+ th.vmfne.vv v4, v8, v12
+ th.vmfne.vf v4, v8, fa2
+ th.vmflt.vv v4, v8, v12
+ th.vmflt.vf v4, v8, fa2
+ th.vmfle.vv v4, v8, v12
+ th.vmfle.vf v4, v8, fa2
+ th.vmfgt.vf v4, v8, fa2
+ th.vmfge.vf v4, v8, fa2
+ th.vmfeq.vv v4, v8, v12, v0.t
+ th.vmfeq.vf v4, v8, fa2, v0.t
+ th.vmfne.vv v4, v8, v12, v0.t
+ th.vmfne.vf v4, v8, fa2, v0.t
+ th.vmflt.vv v4, v8, v12, v0.t
+ th.vmflt.vf v4, v8, fa2, v0.t
+ th.vmfle.vv v4, v8, v12, v0.t
+ th.vmfle.vf v4, v8, fa2, v0.t
+ th.vmfgt.vf v4, v8, fa2, v0.t
+ th.vmfge.vf v4, v8, fa2, v0.t
+
+ th.vmford.vv v4, v8, v12
+ th.vmford.vf v4, v8, fa2
+ th.vmford.vv v4, v8, v12, v0.t
+ th.vmford.vf v4, v8, fa2, v0.t
+
+ th.vfclass.v v4, v8
+ th.vfclass.v v4, v8, v0.t
+
+ th.vfmerge.vfm v4, v8, fa2, v0
+ th.vfmv.v.f v4, fa1
+
+ th.vfcvt.xu.f.v v4, v8
+ th.vfcvt.x.f.v v4, v8
+ th.vfcvt.f.xu.v v4, v8
+ th.vfcvt.f.x.v v4, v8
+ th.vfcvt.xu.f.v v4, v8, v0.t
+ th.vfcvt.x.f.v v4, v8, v0.t
+ th.vfcvt.f.xu.v v4, v8, v0.t
+ th.vfcvt.f.x.v v4, v8, v0.t
+
+ th.vfwcvt.xu.f.v v4, v8
+ th.vfwcvt.x.f.v v4, v8
+ th.vfwcvt.f.xu.v v4, v8
+ th.vfwcvt.f.x.v v4, v8
+ th.vfwcvt.f.f.v v4, v8
+ th.vfwcvt.xu.f.v v4, v8, v0.t
+ th.vfwcvt.x.f.v v4, v8, v0.t
+ th.vfwcvt.f.xu.v v4, v8, v0.t
+ th.vfwcvt.f.x.v v4, v8, v0.t
+ th.vfwcvt.f.f.v v4, v8, v0.t
+
+ th.vfncvt.xu.f.v v4, v8
+ th.vfncvt.x.f.v v4, v8
+ th.vfncvt.f.xu.v v4, v8
+ th.vfncvt.f.x.v v4, v8
+ th.vfncvt.f.f.v v4, v8
+ th.vfncvt.xu.f.v v4, v8, v0.t
+ th.vfncvt.x.f.v v4, v8, v0.t
+ th.vfncvt.f.xu.v v4, v8, v0.t
+ th.vfncvt.f.x.v v4, v8, v0.t
+ th.vfncvt.f.f.v v4, v8, v0.t
diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h
index 059b2fa68bb..2ec07a0b2a5 100644
--- a/include/opcode/riscv-opc.h
+++ b/include/opcode/riscv-opc.h
@@ -3671,6 +3671,174 @@
#define MASK_TH_VNCLIPVX 0xfc00707f
#define MATCH_TH_VNCLIPVI 0xbc003057
#define MASK_TH_VNCLIPVI 0xfc00707f
+#define MATCH_TH_VFADDVV 0x00001057
+#define MASK_TH_VFADDVV 0xfc00707f
+#define MATCH_TH_VFADDVF 0x00005057
+#define MASK_TH_VFADDVF 0xfc00707f
+#define MATCH_TH_VFSUBVV 0x08001057
+#define MASK_TH_VFSUBVV 0xfc00707f
+#define MATCH_TH_VFSUBVF 0x08005057
+#define MASK_TH_VFSUBVF 0xfc00707f
+#define MATCH_TH_VFRSUBVF 0x9c005057
+#define MASK_TH_VFRSUBVF 0xfc00707f
+#define MATCH_TH_VFWADDVV 0xc0001057
+#define MASK_TH_VFWADDVV 0xfc00707f
+#define MATCH_TH_VFWADDVF 0xc0005057
+#define MASK_TH_VFWADDVF 0xfc00707f
+#define MATCH_TH_VFWSUBVV 0xc8001057
+#define MASK_TH_VFWSUBVV 0xfc00707f
+#define MATCH_TH_VFWSUBVF 0xc8005057
+#define MASK_TH_VFWSUBVF 0xfc00707f
+#define MATCH_TH_VFWADDWV 0xd0001057
+#define MASK_TH_VFWADDWV 0xfc00707f
+#define MATCH_TH_VFWADDWF 0xd0005057
+#define MASK_TH_VFWADDWF 0xfc00707f
+#define MATCH_TH_VFWSUBWV 0xd8001057
+#define MASK_TH_VFWSUBWV 0xfc00707f
+#define MATCH_TH_VFWSUBWF 0xd8005057
+#define MASK_TH_VFWSUBWF 0xfc00707f
+#define MATCH_TH_VFMULVV 0x90001057
+#define MASK_TH_VFMULVV 0xfc00707f
+#define MATCH_TH_VFMULVF 0x90005057
+#define MASK_TH_VFMULVF 0xfc00707f
+#define MATCH_TH_VFDIVVV 0x80001057
+#define MASK_TH_VFDIVVV 0xfc00707f
+#define MATCH_TH_VFDIVVF 0x80005057
+#define MASK_TH_VFDIVVF 0xfc00707f
+#define MATCH_TH_VFRDIVVF 0x84005057
+#define MASK_TH_VFRDIVVF 0xfc00707f
+#define MATCH_TH_VFWMULVV 0xe0001057
+#define MASK_TH_VFWMULVV 0xfc00707f
+#define MATCH_TH_VFWMULVF 0xe0005057
+#define MASK_TH_VFWMULVF 0xfc00707f
+#define MATCH_TH_VFMADDVV 0xa0001057
+#define MASK_TH_VFMADDVV 0xfc00707f
+#define MATCH_TH_VFMADDVF 0xa0005057
+#define MASK_TH_VFMADDVF 0xfc00707f
+#define MATCH_TH_VFNMADDVV 0xa4001057
+#define MASK_TH_VFNMADDVV 0xfc00707f
+#define MATCH_TH_VFNMADDVF 0xa4005057
+#define MASK_TH_VFNMADDVF 0xfc00707f
+#define MATCH_TH_VFMSUBVV 0xa8001057
+#define MASK_TH_VFMSUBVV 0xfc00707f
+#define MATCH_TH_VFMSUBVF 0xa8005057
+#define MASK_TH_VFMSUBVF 0xfc00707f
+#define MATCH_TH_VFNMSUBVV 0xac001057
+#define MASK_TH_VFNMSUBVV 0xfc00707f
+#define MATCH_TH_VFNMSUBVF 0xac005057
+#define MASK_TH_VFNMSUBVF 0xfc00707f
+#define MATCH_TH_VFMACCVV 0xb0001057
+#define MASK_TH_VFMACCVV 0xfc00707f
+#define MATCH_TH_VFMACCVF 0xb0005057
+#define MASK_TH_VFMACCVF 0xfc00707f
+#define MATCH_TH_VFNMACCVV 0xb4001057
+#define MASK_TH_VFNMACCVV 0xfc00707f
+#define MATCH_TH_VFNMACCVF 0xb4005057
+#define MASK_TH_VFNMACCVF 0xfc00707f
+#define MATCH_TH_VFMSACVV 0xb8001057
+#define MASK_TH_VFMSACVV 0xfc00707f
+#define MATCH_TH_VFMSACVF 0xb8005057
+#define MASK_TH_VFMSACVF 0xfc00707f
+#define MATCH_TH_VFNMSACVV 0xbc001057
+#define MASK_TH_VFNMSACVV 0xfc00707f
+#define MATCH_TH_VFNMSACVF 0xbc005057
+#define MASK_TH_VFNMSACVF 0xfc00707f
+#define MATCH_TH_VFWMACCVV 0xf0001057
+#define MASK_TH_VFWMACCVV 0xfc00707f
+#define MATCH_TH_VFWMACCVF 0xf0005057
+#define MASK_TH_VFWMACCVF 0xfc00707f
+#define MATCH_TH_VFWNMACCVV 0xf4001057
+#define MASK_TH_VFWNMACCVV 0xfc00707f
+#define MATCH_TH_VFWNMACCVF 0xf4005057
+#define MASK_TH_VFWNMACCVF 0xfc00707f
+#define MATCH_TH_VFWMSACVV 0xf8001057
+#define MASK_TH_VFWMSACVV 0xfc00707f
+#define MATCH_TH_VFWMSACVF 0xf8005057
+#define MASK_TH_VFWMSACVF 0xfc00707f
+#define MATCH_TH_VFWNMSACVV 0xfc001057
+#define MASK_TH_VFWNMSACVV 0xfc00707f
+#define MATCH_TH_VFWNMSACVF 0xfc005057
+#define MASK_TH_VFWNMSACVF 0xfc00707f
+#define MATCH_TH_VFSQRTV 0x8c001057
+#define MASK_TH_VFSQRTV 0xfc0ff07f
+#define MATCH_TH_VFMINVV 0x10001057
+#define MASK_TH_VFMINVV 0xfc00707f
+#define MATCH_TH_VFMINVF 0x10005057
+#define MASK_TH_VFMINVF 0xfc00707f
+#define MATCH_TH_VFMAXVV 0x18001057
+#define MASK_TH_VFMAXVV 0xfc00707f
+#define MATCH_TH_VFMAXVF 0x18005057
+#define MASK_TH_VFMAXVF 0xfc00707f
+#define MATCH_TH_VFSGNJVV 0x20001057
+#define MASK_TH_VFSGNJVV 0xfc00707f
+#define MATCH_TH_VFSGNJVF 0x20005057
+#define MASK_TH_VFSGNJVF 0xfc00707f
+#define MATCH_TH_VFSGNJNVV 0x24001057
+#define MASK_TH_VFSGNJNVV 0xfc00707f
+#define MATCH_TH_VFSGNJNVF 0x24005057
+#define MASK_TH_VFSGNJNVF 0xfc00707f
+#define MATCH_TH_VFSGNJXVV 0x28001057
+#define MASK_TH_VFSGNJXVV 0xfc00707f
+#define MATCH_TH_VFSGNJXVF 0x28005057
+#define MASK_TH_VFSGNJXVF 0xfc00707f
+#define MATCH_TH_VMFEQVV 0x60001057
+#define MASK_TH_VMFEQVV 0xfc00707f
+#define MATCH_TH_VMFEQVF 0x60005057
+#define MASK_TH_VMFEQVF 0xfc00707f
+#define MATCH_TH_VMFNEVV 0x70001057
+#define MASK_TH_VMFNEVV 0xfc00707f
+#define MATCH_TH_VMFNEVF 0x70005057
+#define MASK_TH_VMFNEVF 0xfc00707f
+#define MATCH_TH_VMFLTVV 0x6c001057
+#define MASK_TH_VMFLTVV 0xfc00707f
+#define MATCH_TH_VMFLTVF 0x6c005057
+#define MASK_TH_VMFLTVF 0xfc00707f
+#define MATCH_TH_VMFLEVV 0x64001057
+#define MASK_TH_VMFLEVV 0xfc00707f
+#define MATCH_TH_VMFLEVF 0x64005057
+#define MASK_TH_VMFLEVF 0xfc00707f
+#define MATCH_TH_VMFGTVF 0x74005057
+#define MASK_TH_VMFGTVF 0xfc00707f
+#define MATCH_TH_VMFGEVF 0x7c005057
+#define MASK_TH_VMFGEVF 0xfc00707f
+#define MATCH_TH_VMFORDVV 0x68001057
+#define MASK_TH_VMFORDVV 0xfc00707f
+#define MATCH_TH_VMFORDVF 0x68005057
+#define MASK_TH_VMFORDVF 0xfc00707f
+#define MATCH_TH_VFCLASSV 0x8c081057
+#define MASK_TH_VFCLASSV 0xfc0ff07f
+#define MATCH_TH_VFMERGEVFM 0x5c005057
+#define MASK_TH_VFMERGEVFM 0xfe00707f
+#define MATCH_TH_VFMVVF 0x5e005057
+#define MASK_TH_VFMVVF 0xfff0707f
+#define MATCH_TH_VFCVTXUFV 0x88001057
+#define MASK_TH_VFCVTXUFV 0xfc0ff07f
+#define MATCH_TH_VFCVTXFV 0x88009057
+#define MASK_TH_VFCVTXFV 0xfc0ff07f
+#define MATCH_TH_VFCVTFXUV 0x88011057
+#define MASK_TH_VFCVTFXUV 0xfc0ff07f
+#define MATCH_TH_VFCVTFXV 0x88019057
+#define MASK_TH_VFCVTFXV 0xfc0ff07f
+#define MATCH_TH_VFWCVTXUFV 0x88041057
+#define MASK_TH_VFWCVTXUFV 0xfc0ff07f
+#define MATCH_TH_VFWCVTXFV 0x88049057
+#define MASK_TH_VFWCVTXFV 0xfc0ff07f
+#define MATCH_TH_VFWCVTFXUV 0x88051057
+#define MASK_TH_VFWCVTFXUV 0xfc0ff07f
+#define MATCH_TH_VFWCVTFXV 0x88059057
+#define MASK_TH_VFWCVTFXV 0xfc0ff07f
+#define MATCH_TH_VFWCVTFFV 0x88061057
+#define MASK_TH_VFWCVTFFV 0xfc0ff07f
+#define MATCH_TH_VFNCVTXUFV 0x88081057
+#define MASK_TH_VFNCVTXUFV 0xfc0ff07f
+#define MATCH_TH_VFNCVTXFV 0x88089057
+#define MASK_TH_VFNCVTXFV 0xfc0ff07f
+#define MATCH_TH_VFNCVTFXUV 0x88091057
+#define MASK_TH_VFNCVTFXUV 0xfc0ff07f
+#define MATCH_TH_VFNCVTFXV 0x88099057
+#define MASK_TH_VFNCVTFXV 0xfc0ff07f
+#define MATCH_TH_VFNCVTFFV 0x880a1057
+#define MASK_TH_VFNCVTFFV 0xfc0ff07f
/* Vendor-specific (Ventana Microsystems) XVentanaCondOps instructions */
#define MATCH_VT_MASKC 0x607b
#define MASK_VT_MASKC 0xfe00707f
diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
index c7d6d171902..a556f44d99d 100644
--- a/opcodes/riscv-opc.c
+++ b/opcodes/riscv-opc.c
@@ -2758,6 +2758,92 @@ const struct riscv_opcode riscv_opcodes[] =
{"th.vnclip.vv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_TH_VNCLIPVV, MASK_TH_VNCLIPVV, match_opcode, 0 },
{"th.vnclip.vx", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,sVm", MATCH_TH_VNCLIPVX, MASK_TH_VNCLIPVX, match_opcode, 0 },
{"th.vnclip.vi", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VjVm", MATCH_TH_VNCLIPVI, MASK_TH_VNCLIPVI, match_opcode, 0 },
+{"th.vfadd.vv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_TH_VFADDVV, MASK_TH_VFADDVV, match_opcode, 0},
+{"th.vfadd.vf", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,SVm", MATCH_TH_VFADDVF, MASK_TH_VFADDVF, match_opcode, 0},
+{"th.vfsub.vv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_TH_VFSUBVV, MASK_TH_VFSUBVV, match_opcode, 0},
+{"th.vfsub.vf", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,SVm", MATCH_TH_VFSUBVF, MASK_TH_VFSUBVF, match_opcode, 0},
+{"th.vfrsub.vf", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,SVm", MATCH_TH_VFRSUBVF, MASK_TH_VFRSUBVF, match_opcode, 0},
+{"th.vfwadd.vv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_TH_VFWADDVV, MASK_TH_VFWADDVV, match_opcode, 0},
+{"th.vfwadd.vf", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,SVm", MATCH_TH_VFWADDVF, MASK_TH_VFWADDVF, match_opcode, 0},
+{"th.vfwsub.vv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_TH_VFWSUBVV, MASK_TH_VFWSUBVV, match_opcode, 0},
+{"th.vfwsub.vf", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,SVm", MATCH_TH_VFWSUBVF, MASK_TH_VFWSUBVF, match_opcode, 0},
+{"th.vfwadd.wv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_TH_VFWADDWV, MASK_TH_VFWADDWV, match_opcode, 0},
+{"th.vfwsub.wv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_TH_VFWSUBWV, MASK_TH_VFWSUBWV, match_opcode, 0},
+{"th.vfwadd.wf", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,SVm", MATCH_TH_VFWADDWF, MASK_TH_VFWADDWF, match_opcode, 0},
+{"th.vfwsub.wf", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,SVm", MATCH_TH_VFWSUBWF, MASK_TH_VFWSUBWF, match_opcode, 0},
+{"th.vfmul.vv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_TH_VFMULVV, MASK_TH_VFMULVV, match_opcode, 0},
+{"th.vfmul.vf", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,SVm", MATCH_TH_VFMULVF, MASK_TH_VFMULVF, match_opcode, 0},
+{"th.vfdiv.vv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_TH_VFDIVVV, MASK_TH_VFDIVVV, match_opcode, 0},
+{"th.vfdiv.vf", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,SVm", MATCH_TH_VFDIVVF, MASK_TH_VFDIVVF, match_opcode, 0},
+{"th.vfrdiv.vf", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,SVm", MATCH_TH_VFRDIVVF, MASK_TH_VFRDIVVF, match_opcode, 0},
+{"th.vfwmul.vv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_TH_VFWMULVV, MASK_TH_VFWMULVV, match_opcode, 0},
+{"th.vfwmul.vf", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,SVm", MATCH_TH_VFWMULVF, MASK_TH_VFWMULVF, match_opcode, 0},
+{"th.vfmadd.vv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vs,VtVm", MATCH_TH_VFMADDVV, MASK_TH_VFMADDVV, match_opcode, 0},
+{"th.vfmadd.vf", 0, INSN_CLASS_XTHEADVECTOR, "Vd,S,VtVm", MATCH_TH_VFMADDVF, MASK_TH_VFMADDVF, match_opcode, 0},
+{"th.vfnmadd.vv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vs,VtVm", MATCH_TH_VFNMADDVV, MASK_TH_VFNMADDVV, match_opcode, 0},
+{"th.vfnmadd.vf", 0, INSN_CLASS_XTHEADVECTOR, "Vd,S,VtVm", MATCH_TH_VFNMADDVF, MASK_TH_VFNMADDVF, match_opcode, 0},
+{"th.vfmsub.vv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vs,VtVm", MATCH_TH_VFMSUBVV, MASK_TH_VFMSUBVV, match_opcode, 0},
+{"th.vfmsub.vf", 0, INSN_CLASS_XTHEADVECTOR, "Vd,S,VtVm", MATCH_TH_VFMSUBVF, MASK_TH_VFMSUBVF, match_opcode, 0},
+{"th.vfnmsub.vv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vs,VtVm", MATCH_TH_VFNMSUBVV, MASK_TH_VFNMSUBVV, match_opcode, 0},
+{"th.vfnmsub.vf", 0, INSN_CLASS_XTHEADVECTOR, "Vd,S,VtVm", MATCH_TH_VFNMSUBVF, MASK_TH_VFNMSUBVF, match_opcode, 0},
+{"th.vfmacc.vv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vs,VtVm", MATCH_TH_VFMACCVV, MASK_TH_VFMACCVV, match_opcode, 0},
+{"th.vfmacc.vf", 0, INSN_CLASS_XTHEADVECTOR, "Vd,S,VtVm", MATCH_TH_VFMACCVF, MASK_TH_VFMACCVF, match_opcode, 0},
+{"th.vfnmacc.vv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vs,VtVm", MATCH_TH_VFNMACCVV, MASK_TH_VFNMACCVV, match_opcode, 0},
+{"th.vfnmacc.vf", 0, INSN_CLASS_XTHEADVECTOR, "Vd,S,VtVm", MATCH_TH_VFNMACCVF, MASK_TH_VFNMACCVF, match_opcode, 0},
+{"th.vfmsac.vv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vs,VtVm", MATCH_TH_VFMSACVV, MASK_TH_VFMSACVV, match_opcode, 0},
+{"th.vfmsac.vf", 0, INSN_CLASS_XTHEADVECTOR, "Vd,S,VtVm", MATCH_TH_VFMSACVF, MASK_TH_VFMSACVF, match_opcode, 0},
+{"th.vfnmsac.vv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vs,VtVm", MATCH_TH_VFNMSACVV, MASK_TH_VFNMSACVV, match_opcode, 0},
+{"th.vfnmsac.vf", 0, INSN_CLASS_XTHEADVECTOR, "Vd,S,VtVm", MATCH_TH_VFNMSACVF, MASK_TH_VFNMSACVF, match_opcode, 0},
+{"th.vfwmacc.vv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vs,VtVm", MATCH_TH_VFWMACCVV, MASK_TH_VFWMACCVV, match_opcode, 0},
+{"th.vfwmacc.vf", 0, INSN_CLASS_XTHEADVECTOR, "Vd,S,VtVm", MATCH_TH_VFWMACCVF, MASK_TH_VFWMACCVF, match_opcode, 0},
+{"th.vfwnmacc.vv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vs,VtVm", MATCH_TH_VFWNMACCVV, MASK_TH_VFWNMACCVV, match_opcode, 0},
+{"th.vfwnmacc.vf", 0, INSN_CLASS_XTHEADVECTOR, "Vd,S,VtVm", MATCH_TH_VFWNMACCVF, MASK_TH_VFWNMACCVF, match_opcode, 0},
+{"th.vfwmsac.vv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vs,VtVm", MATCH_TH_VFWMSACVV, MASK_TH_VFWMSACVV, match_opcode, 0},
+{"th.vfwmsac.vf", 0, INSN_CLASS_XTHEADVECTOR, "Vd,S,VtVm", MATCH_TH_VFWMSACVF, MASK_TH_VFWMSACVF, match_opcode, 0},
+{"th.vfwnmsac.vv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vs,VtVm", MATCH_TH_VFWNMSACVV, MASK_TH_VFWNMSACVV, match_opcode, 0},
+{"th.vfwnmsac.vf", 0, INSN_CLASS_XTHEADVECTOR, "Vd,S,VtVm", MATCH_TH_VFWNMSACVF, MASK_TH_VFWNMSACVF, match_opcode, 0},
+{"th.vfsqrt.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,VtVm", MATCH_TH_VFSQRTV, MASK_TH_VFSQRTV, match_opcode, 0},
+{"th.vfmin.vv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_TH_VFMINVV, MASK_TH_VFMINVV, match_opcode, 0},
+{"th.vfmin.vf", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,SVm", MATCH_TH_VFMINVF, MASK_TH_VFMINVF, match_opcode, 0},
+{"th.vfmax.vv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_TH_VFMAXVV, MASK_TH_VFMAXVV, match_opcode, 0},
+{"th.vfmax.vf", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,SVm", MATCH_TH_VFMAXVF, MASK_TH_VFMAXVF, match_opcode, 0},
+{"th.vfsgnj.vv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_TH_VFSGNJVV, MASK_TH_VFSGNJVV, match_opcode, 0},
+{"th.vfsgnj.vf", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,SVm", MATCH_TH_VFSGNJVF, MASK_TH_VFSGNJVF, match_opcode, 0},
+{"th.vfsgnjn.vv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_TH_VFSGNJNVV, MASK_TH_VFSGNJNVV, match_opcode, 0},
+{"th.vfsgnjn.vf", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,SVm", MATCH_TH_VFSGNJNVF, MASK_TH_VFSGNJNVF, match_opcode, 0},
+{"th.vfsgnjx.vv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_TH_VFSGNJXVV, MASK_TH_VFSGNJXVV, match_opcode, 0},
+{"th.vfsgnjx.vf", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,SVm", MATCH_TH_VFSGNJXVF, MASK_TH_VFSGNJXVF, match_opcode, 0},
+{"th.vmfeq.vv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_TH_VMFEQVV, MASK_TH_VMFEQVV, match_opcode, 0},
+{"th.vmfeq.vf", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,SVm", MATCH_TH_VMFEQVF, MASK_TH_VMFEQVF, match_opcode, 0},
+{"th.vmfne.vv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_TH_VMFNEVV, MASK_TH_VMFNEVV, match_opcode, 0},
+{"th.vmfne.vf", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,SVm", MATCH_TH_VMFNEVF, MASK_TH_VMFNEVF, match_opcode, 0},
+{"th.vmflt.vv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_TH_VMFLTVV, MASK_TH_VMFLTVV, match_opcode, 0},
+{"th.vmflt.vf", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,SVm", MATCH_TH_VMFLTVF, MASK_TH_VMFLTVF, match_opcode, 0},
+{"th.vmfle.vv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_TH_VMFLEVV, MASK_TH_VMFLEVV, match_opcode, 0},
+{"th.vmfle.vf", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,SVm", MATCH_TH_VMFLEVF, MASK_TH_VMFLEVF, match_opcode, 0},
+{"th.vmfgt.vf", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,SVm", MATCH_TH_VMFGTVF, MASK_TH_VMFGTVF, match_opcode, 0},
+{"th.vmfge.vf", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,SVm", MATCH_TH_VMFGEVF, MASK_TH_VMFGEVF, match_opcode, 0},
+{"th.vmfgt.vv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vs,VtVm", MATCH_TH_VMFLTVV, MASK_TH_VMFLTVV, match_opcode, INSN_ALIAS},
+{"th.vmfge.vv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vs,VtVm", MATCH_TH_VMFLEVV, MASK_TH_VMFLEVV, match_opcode, INSN_ALIAS},
+{"th.vmford.vv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_TH_VMFORDVV, MASK_TH_VMFORDVV, match_opcode, 0},
+{"th.vmford.vf", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,SVm", MATCH_TH_VMFORDVF, MASK_TH_VMFORDVF, match_opcode, 0},
+{"th.vfclass.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,VtVm", MATCH_TH_VFCLASSV, MASK_TH_VFCLASSV, match_opcode, 0},
+{"th.vfmerge.vfm",0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,S,V0", MATCH_TH_VFMERGEVFM, MASK_TH_VFMERGEVFM, match_opcode, 0},
+{"th.vfmv.v.f", 0, INSN_CLASS_XTHEADVECTOR, "Vd,S", MATCH_TH_VFMVVF, MASK_TH_VFMVVF, match_opcode, 0 },
+{"th.vfcvt.xu.f.v",0, INSN_CLASS_XTHEADVECTOR, "Vd,VtVm", MATCH_TH_VFCVTXUFV, MASK_TH_VFCVTXUFV, match_opcode, 0},
+{"th.vfcvt.x.f.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,VtVm", MATCH_TH_VFCVTXFV, MASK_TH_VFCVTXFV, match_opcode, 0},
+{"th.vfcvt.f.xu.v",0, INSN_CLASS_XTHEADVECTOR, "Vd,VtVm", MATCH_TH_VFCVTFXUV, MASK_TH_VFCVTFXUV, match_opcode, 0},
+{"th.vfcvt.f.x.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,VtVm", MATCH_TH_VFCVTFXV, MASK_TH_VFCVTFXV, match_opcode, 0},
+{"th.vfwcvt.xu.f.v",0,INSN_CLASS_XTHEADVECTOR, "Vd,VtVm", MATCH_TH_VFWCVTXUFV, MASK_TH_VFWCVTXUFV, match_opcode, 0},
+{"th.vfwcvt.x.f.v",0, INSN_CLASS_XTHEADVECTOR, "Vd,VtVm", MATCH_TH_VFWCVTXFV, MASK_TH_VFWCVTXFV, match_opcode, 0},
+{"th.vfwcvt.f.xu.v",0,INSN_CLASS_XTHEADVECTOR, "Vd,VtVm", MATCH_TH_VFWCVTFXUV, MASK_TH_VFWCVTFXUV, match_opcode, 0},
+{"th.vfwcvt.f.x.v",0, INSN_CLASS_XTHEADVECTOR, "Vd,VtVm", MATCH_TH_VFWCVTFXV, MASK_TH_VFWCVTFXV, match_opcode, 0},
+{"th.vfwcvt.f.f.v",0, INSN_CLASS_XTHEADVECTOR, "Vd,VtVm", MATCH_TH_VFWCVTFFV, MASK_TH_VFWCVTFFV, match_opcode, 0},
+{"th.vfncvt.xu.f.v",0,INSN_CLASS_XTHEADVECTOR, "Vd,VtVm", MATCH_TH_VFNCVTXUFV, MASK_TH_VFNCVTXUFV, match_opcode, 0},
+{"th.vfncvt.x.f.v",0, INSN_CLASS_XTHEADVECTOR, "Vd,VtVm", MATCH_TH_VFNCVTXFV, MASK_TH_VFNCVTXFV, match_opcode, 0},
+{"th.vfncvt.f.xu.v",0,INSN_CLASS_XTHEADVECTOR, "Vd,VtVm", MATCH_TH_VFNCVTFXUV, MASK_TH_VFNCVTFXUV, match_opcode, 0},
+{"th.vfncvt.f.x.v",0, INSN_CLASS_XTHEADVECTOR, "Vd,VtVm", MATCH_TH_VFNCVTFXV, MASK_TH_VFNCVTFXV, match_opcode, 0},
+{"th.vfncvt.f.f.v",0, INSN_CLASS_XTHEADVECTOR, "Vd,VtVm", MATCH_TH_VFNCVTFFV, MASK_TH_VFNCVTFFV, match_opcode, 0},
/* Vendor-specific (Ventana Microsystems) XVentanaCondOps instructions */
{"vt.maskc", 64, INSN_CLASS_XVENTANACONDOPS, "d,s,t", MATCH_VT_MASKC, MASK_VT_MASKC, match_opcode, 0 },
--
2.17.1
next prev parent reply other threads:[~2023-11-10 7:33 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-11-10 7:17 [PATCH 01/12] RISC-V: Add " Jin Ma
2023-11-10 7:20 ` [PATCH 02/12] RISC-V: Add CSRs for " Jin Ma
2023-11-10 7:22 ` [PATCH 03/12] RISC-V: Add configuration-setting instructions " Jin Ma
2023-11-17 3:18 ` Nelson Chu
2023-11-17 9:53 ` Jin Ma
2023-11-10 7:23 ` [PATCH 04/12] RISC-V: Add load/store " Jin Ma
2023-11-10 7:24 ` [PATCH 05/12] RISC-V: Add the sub-extension "XTheadZvlsseg" " Jin Ma
2023-11-10 7:25 ` [PATCH 06/12] RISC-V: Add sub-extension XTheadZvamo " Jin Ma
2023-11-10 7:31 ` [PATCH 07/12] RISC-V: Add integer arithmetic instructions " Jin Ma
2023-11-10 7:31 ` [PATCH 08/12] RISC-V: Add fixed-point " Jin Ma
2023-11-10 7:32 ` Jin Ma [this message]
2023-11-10 7:33 ` [PATCH 10/12] RISC-V: Add reductions " Jin Ma
2023-11-10 7:34 ` [PATCH 11/12] RISC-V: Add vector mask " Jin Ma
2023-11-10 7:35 ` [PATCH 12/12] RISC-V: Add vector permutation " Jin Ma
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