From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.8]) by sourceware.org (Postfix) with ESMTPS id D93393858D20 for ; Wed, 15 Nov 2023 03:01:31 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org D93393858D20 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=intel.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org D93393858D20 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=192.198.163.8 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1700017294; cv=none; b=WVMlfTJ4Zx/KVOs7GdxmjSk8xOqZ+OZO8k1sn7oN0Pknghf2fNNpyVFxT8dacRHpxjgkW0qICZFsxXopv5V3LHp9m0KhdjbCjh26vuOLgUsjDKW326NiZ/rzKazwVxpNR6DPCvJliaG6bjN6P01FEMaEkYVkG5SCc05CkXUGDLg= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1700017294; c=relaxed/simple; bh=D/9MjvFocR1oi8NeZ6U6mIuWfgnKFi7k2wg+umiMOuY=; h=DKIM-Signature:From:To:Subject:Date:Message-Id:MIME-Version; b=IxcOU/qsrqKsl7RTYAoIdok4kCFPyc/aK2InRfyMl2eH0kH4t59eDqW/LAGc6vfFcGbSeg81wxI2S+6jG4Yrn28XWhPmZv38C8IeptP5JGLSsmJwNTApl4Cqkh2keZ5j2kTqPdDKsch8A0zKYiMOHCv+SEVRqdzM+UseXlaQ9FQ= ARC-Authentication-Results: i=1; server2.sourceware.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1700017292; x=1731553292; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=D/9MjvFocR1oi8NeZ6U6mIuWfgnKFi7k2wg+umiMOuY=; b=DJZD4gJ8yRIJ7mnj/kwfMQJZmcqjCEAAeQ0tzudEdZjrwQmRBU0XLmTR cG/tsq8a6MMv599G7/GSkU/g8ggbcHUKGf9AITVO7ANR7jp7YbpPHGGMx 3zYTpw6vl2vJlG0tCuOLugbMYIbHqBuk9v0WhIAIASBgAJTriYfabFHGB z4dsnFSDTCv5aZsgQR8b6rPNCjBialzNNVuzZ7tWtPhBTpNVr6367W7e4 RTVuTjbJYuhOBX2w7mXX9h+t5mk9Y/o2/vZWX/tePCNhkqQA5t0IdfHRn yyCI8W57rlWt2cvl2O0+Ljold1WKb872roPPZ+GALcVSt0xZXHI7PBiXy Q==; X-IronPort-AV: E=McAfee;i="6600,9927,10894"; a="3874028" X-IronPort-AV: E=Sophos;i="6.03,303,1694761200"; d="scan'208";a="3874028" Received: from orsmga003.jf.intel.com ([10.7.209.27]) by fmvoesa102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 Nov 2023 19:01:31 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10894"; a="714752264" X-IronPort-AV: E=Sophos;i="6.03,303,1694761200"; d="scan'208";a="714752264" Received: from shvmail03.sh.intel.com ([10.239.245.20]) by orsmga003.jf.intel.com with ESMTP; 14 Nov 2023 19:01:26 -0800 Received: from shliclel4217.sh.intel.com (shliclel4217.sh.intel.com [10.239.240.127]) by shvmail03.sh.intel.com (Postfix) with ESMTP id 71C3A1005670; Wed, 15 Nov 2023 11:01:25 +0800 (CST) From: "Hu, Lin1" To: binutils@sourceware.org Cc: JBeulich@suse.com, hongjiu.lu@intel.com Subject: [PATCH][v3] Support APX NDD optimized encoding. Date: Wed, 15 Nov 2023 10:59:25 +0800 Message-Id: <20231115025925.2891038-1-lin1.hu@intel.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <8ed3b7a2-8cba-6428-1c01-5b6c28ca4a89@suse.com> References: <8ed3b7a2-8cba-6428-1c01-5b6c28ca4a89@suse.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-9.3 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,GIT_PATCH_0,SCC_10_SHORT_WORD_LINES,SCC_20_SHORT_WORD_LINES,SCC_5_SHORT_WORD_LINES,SPF_HELO_NONE,SPF_NONE,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: Hi, This patch is based on a possible version of what we discussed earlier, which was developed based on the fact that I had reorder the i386.tbl. And it only optimize some insns in opcode_space legacy-map0 or legacy-map1. Like adcx/adox, I don't reorder them as you expectation, so I can use the condition !t[1].opcode_modifier.evex to exclude them. The other version in the previous email was made to optimize adcx and adox for legacy. BRs, Lin This patch aims to optimize: add %r16, %r15, %r15 -> add %r16, %r15 gas/ChangeLog: * config/tc-i386.c (optimize_NDD_to_nonNDD): New function. (match_template): If we can optimzie APX NDD insns, so rematch template. * testsuite/gas/i386/x86-64.exp: Add test. * testsuite/gas/i386/x86-64-apx-ndd-optimize.d: New test. * testsuite/gas/i386/x86-64-apx-ndd-optimize.s: Ditto. opcodes/ChangeLog: * i386-init.h: Regenerated. * i386-mnem.h: Ditto. * i386-tbl.h: Ditto. * i386-opc.tbl: Add C to some instructions for support optimization. --- gas/config/tc-i386.c | 52 ++++++++ .../gas/i386/x86-64-apx-ndd-optimize.d | 126 ++++++++++++++++++ .../gas/i386/x86-64-apx-ndd-optimize.s | 119 +++++++++++++++++ gas/testsuite/gas/i386/x86-64.exp | 1 + 4 files changed, 298 insertions(+) create mode 100644 gas/testsuite/gas/i386/x86-64-apx-ndd-optimize.d create mode 100644 gas/testsuite/gas/i386/x86-64-apx-ndd-optimize.s diff --git a/gas/config/tc-i386.c b/gas/config/tc-i386.c index d98950c7dfd..6d6fc65383e 100644 --- a/gas/config/tc-i386.c +++ b/gas/config/tc-i386.c @@ -7208,6 +7208,43 @@ check_EgprOperands (const insn_template *t) return 0; } +/* Optimize APX NDD insns to legacy insns. */ +static bool +convert_NDD_to_REX2 (const insn_template *t) +{ + if (t->opcode_modifier.vexvvvv == VexVVVV_DST + && t->opcode_space == SPACE_EVEXMAP4 + && !i.has_nf + && i.reg_operands >= 2) + { + unsigned int readonly_var = ~0; + unsigned int dest = i.operands - 1; + unsigned int src1 = i.operands - 2; + unsigned int src2 = (i.operands > 3) ? i.operands - 3 : 0; + + if (i.types[src1].bitfield.class == Reg + && i.op[src1].regs == i.op[dest].regs) + readonly_var = src2; + /* adcx, adox and imul can't support to swap the source operands. */ + else if (i.types[src2].bitfield.class == Reg + && i.op[src2].regs == i.op[dest].regs + && optimize > 1 + && t->opcode_modifier.commutative) + readonly_var = src1; + if (readonly_var != (unsigned int) ~0) + { + if (readonly_var != src2) + swap_2_operands (readonly_var, src2); + + --i.operands; + --i.reg_operands; + + return true; + } + } + return false; +} + /* Helper function for the progress() macro in match_template(). */ static INLINE enum i386_error progress (enum i386_error new, enum i386_error last, @@ -7728,6 +7765,21 @@ match_template (char mnem_suffix) i.memshift = memshift; } + /* If we can optimize a NDD insn to non-NDD insn, like + add %r16, %r8, %r8 -> add %r16, %r8, + add %r8, %r16, %r8 -> add %r16, %r8, then rematch template. + Note that the semantics have not been changed. */ + if (optimize + && !i.no_optimize + && i.vec_encoding != vex_encoding_evex + && t + 1 < current_templates->end + && !t[1].opcode_modifier.evex + && convert_NDD_to_REX2 (t)) + { + specific_error = progress (internal_error); + continue; + } + /* We've found a match; break out of loop. */ break; } diff --git a/gas/testsuite/gas/i386/x86-64-apx-ndd-optimize.d b/gas/testsuite/gas/i386/x86-64-apx-ndd-optimize.d new file mode 100644 index 00000000000..d13daed38b5 --- /dev/null +++ b/gas/testsuite/gas/i386/x86-64-apx-ndd-optimize.d @@ -0,0 +1,126 @@ +#as: -Os +#objdump: -drw +#name: x86-64 APX NDD optimized encoding +#source: x86-64-apx-ndd-optimize.s + +.*: +file format .* + + +Disassembly of section .text: + +0+ <_start>: +\s*[a-f0-9]+:\s*d5 19 ff c7 inc %r31 +\s*[a-f0-9]+:\s*d5 11 fe c7 inc %r31b +\s*[a-f0-9]+:\s*d5 4d 01 f8 add %r31,%r8 +\s*[a-f0-9]+:\s*d5 45 00 f8 add %r31b,%r8b +\s*[a-f0-9]+:\s*d5 4d 01 f8 add %r31,%r8 +\s*[a-f0-9]+:\s*d5 1d 03 c7 add %r31,%r8 +\s*[a-f0-9]+:\s*d5 4d 03 38 add \(%r8\),%r31 +\s*[a-f0-9]+:\s*d5 1d 03 07 add \(%r31\),%r8 +\s*[a-f0-9]+:\s*49 81 c7 33 44 34 12 add \$0x12344433,%r15 +\s*[a-f0-9]+:\s*49 81 c0 11 22 33 f4 add \$0xfffffffff4332211,%r8 +\s*[a-f0-9]+:\s*d5 18 ff c9 dec %r17 +\s*[a-f0-9]+:\s*d5 10 fe c9 dec %r17b +\s*[a-f0-9]+:\s*d5 18 f7 d1 not %r17 +\s*[a-f0-9]+:\s*d5 10 f6 d1 not %r17b +\s*[a-f0-9]+:\s*d5 18 f7 d9 neg %r17 +\s*[a-f0-9]+:\s*d5 10 f6 d9 neg %r17b +\s*[a-f0-9]+:\s*d5 1c 29 f9 sub %r15,%r17 +\s*[a-f0-9]+:\s*d5 14 28 f9 sub %r15b,%r17b +\s*[a-f0-9]+:\s*62 54 84 18 29 38 sub %r15,\(%r8\),%r15 +\s*[a-f0-9]+:\s*d5 49 2b 04 07 sub \(%r15,%rax,1\),%r16 +\s*[a-f0-9]+:\s*d5 19 81 ee 34 12 00 00 sub \$0x1234,%r30 +\s*[a-f0-9]+:\s*d5 1c 19 f9 sbb %r15,%r17 +\s*[a-f0-9]+:\s*d5 14 18 f9 sbb %r15b,%r17b +\s*[a-f0-9]+:\s*62 54 84 18 19 38 sbb %r15,\(%r8\),%r15 +\s*[a-f0-9]+:\s*d5 49 1b 04 07 sbb \(%r15,%rax,1\),%r16 +\s*[a-f0-9]+:\s*d5 19 81 de 34 12 00 00 sbb \$0x1234,%r30 +\s*[a-f0-9]+:\s*d5 1c 11 f9 adc %r15,%r17 +\s*[a-f0-9]+:\s*d5 14 10 f9 adc %r15b,%r17b +\s*[a-f0-9]+:\s*4d 13 38 adc \(%r8\),%r15 +\s*[a-f0-9]+:\s*d5 49 13 04 07 adc \(%r15,%rax,1\),%r16 +\s*[a-f0-9]+:\s*d5 19 81 d6 34 12 00 00 adc \$0x1234,%r30 +\s*[a-f0-9]+:\s*d5 1c 09 f9 or %r15,%r17 +\s*[a-f0-9]+:\s*d5 14 08 f9 or %r15b,%r17b +\s*[a-f0-9]+:\s*4d 0b 38 or \(%r8\),%r15 +\s*[a-f0-9]+:\s*d5 49 0b 04 07 or \(%r15,%rax,1\),%r16 +\s*[a-f0-9]+:\s*d5 19 81 ce 34 12 00 00 or \$0x1234,%r30 +\s*[a-f0-9]+:\s*d5 1c 31 f9 xor %r15,%r17 +\s*[a-f0-9]+:\s*d5 14 30 f9 xor %r15b,%r17b +\s*[a-f0-9]+:\s*4d 33 38 xor \(%r8\),%r15 +\s*[a-f0-9]+:\s*d5 49 33 04 07 xor \(%r15,%rax,1\),%r16 +\s*[a-f0-9]+:\s*d5 19 81 f6 34 12 00 00 xor \$0x1234,%r30 +\s*[a-f0-9]+:\s*d5 1c 21 f9 and %r15,%r17 +\s*[a-f0-9]+:\s*d5 14 20 f9 and %r15b,%r17b +\s*[a-f0-9]+:\s*4d 23 38 and \(%r8\),%r15 +\s*[a-f0-9]+:\s*d5 49 23 04 07 and \(%r15,%rax,1\),%r16 +\s*[a-f0-9]+:\s*d5 11 81 e6 34 12 00 00 and \$0x1234,%r30d +\s*[a-f0-9]+:\s*d5 19 d1 cf ror %r31 +\s*[a-f0-9]+:\s*d5 11 d0 cf ror %r31b +\s*[a-f0-9]+:\s*49 c1 cc 02 ror \$0x2,%r12 +\s*[a-f0-9]+:\s*41 c0 cc 02 ror \$0x2,%r12b +\s*[a-f0-9]+:\s*d5 19 d1 c7 rol %r31 +\s*[a-f0-9]+:\s*d5 11 d0 c7 rol %r31b +\s*[a-f0-9]+:\s*49 c1 c4 02 rol \$0x2,%r12 +\s*[a-f0-9]+:\s*41 c0 c4 02 rol \$0x2,%r12b +\s*[a-f0-9]+:\s*d5 19 d1 df rcr %r31 +\s*[a-f0-9]+:\s*d5 11 d0 df rcr %r31b +\s*[a-f0-9]+:\s*49 c1 dc 02 rcr \$0x2,%r12 +\s*[a-f0-9]+:\s*41 c0 dc 02 rcr \$0x2,%r12b +\s*[a-f0-9]+:\s*d5 19 d1 d7 rcl %r31 +\s*[a-f0-9]+:\s*d5 11 d0 d7 rcl %r31b +\s*[a-f0-9]+:\s*49 c1 d4 02 rcl \$0x2,%r12 +\s*[a-f0-9]+:\s*41 c0 d4 02 rcl \$0x2,%r12b +\s*[a-f0-9]+:\s*d5 19 d1 e7 shl %r31 +\s*[a-f0-9]+:\s*d5 11 d0 e7 shl %r31b +\s*[a-f0-9]+:\s*49 c1 e4 02 shl \$0x2,%r12 +\s*[a-f0-9]+:\s*41 c0 e4 02 shl \$0x2,%r12b +\s*[a-f0-9]+:\s*d5 19 d1 ff sar %r31 +\s*[a-f0-9]+:\s*d5 11 d0 ff sar %r31b +\s*[a-f0-9]+:\s*49 c1 fc 02 sar \$0x2,%r12 +\s*[a-f0-9]+:\s*41 c0 fc 02 sar \$0x2,%r12b +\s*[a-f0-9]+:\s*d5 19 d1 e7 shl %r31 +\s*[a-f0-9]+:\s*d5 11 d0 e7 shl %r31b +\s*[a-f0-9]+:\s*49 c1 e4 02 shl \$0x2,%r12 +\s*[a-f0-9]+:\s*41 c0 e4 02 shl \$0x2,%r12b +\s*[a-f0-9]+:\s*d5 19 d1 ef shr %r31 +\s*[a-f0-9]+:\s*d5 11 d0 ef shr %r31b +\s*[a-f0-9]+:\s*49 c1 ec 02 shr \$0x2,%r12 +\s*[a-f0-9]+:\s*41 c0 ec 02 shr \$0x2,%r12b +\s*[a-f0-9]+:\s*62 74 9c 18 24 20 01 shld \$0x1,%r12,\(%rax\),%r12 +\s*[a-f0-9]+:\s*4d 0f a4 c4 02 shld \$0x2,%r8,%r12 +\s*[a-f0-9]+:\s*62 54 bc 18 24 c4 02 shld \$0x2,%r8,%r12,%r8 +\s*[a-f0-9]+:\s*62 74 b4 18 a5 08 shld %cl,%r9,\(%rax\),%r9 +\s*[a-f0-9]+:\s*d5 9c a5 e0 shld %cl,%r12,%r16 +\s*[a-f0-9]+:\s*62 7c 9c 18 a5 e0 shld %cl,%r12,%r16,%r12 +\s*[a-f0-9]+:\s*62 74 9c 18 2c 20 01 shrd \$0x1,%r12,\(%rax\),%r12 +\s*[a-f0-9]+:\s*4d 0f ac ec 01 shrd \$0x1,%r13,%r12 +\s*[a-f0-9]+:\s*62 54 94 18 2c ec 01 shrd \$0x1,%r13,%r12,%r13 +\s*[a-f0-9]+:\s*62 74 b4 18 ad 08 shrd %cl,%r9,\(%rax\),%r9 +\s*[a-f0-9]+:\s*d5 9c ad e0 shrd %cl,%r12,%r16 +\s*[a-f0-9]+:\s*62 7c 9c 18 ad e0 shrd %cl,%r12,%r16,%r12 +\s*[a-f0-9]+:\s*62 54 bd 18 66 c7 adcx %r15,%r8,%r8 +\s*[a-f0-9]+:\s*62 14 b9 18 66 04 3f adcx \(%r15,%r31,1\),%r8,%r8 +\s*[a-f0-9]+:\s*62 54 bd 18 66 c8 adcx %r8,%r9,%r8 +\s*[a-f0-9]+:\s*62 54 be 18 66 c7 adox %r15,%r8,%r8 +\s*[a-f0-9]+:\s*62 14 ba 18 66 04 3f adox \(%r15,%r31,1\),%r8,%r8 +\s*[a-f0-9]+:\s*62 54 be 18 66 c8 adox %r8,%r9,%r8 +\s*[a-f0-9]+:\s*67 0f 40 90 90 90 90 90 cmovo -0x6f6f6f70\(%eax\),%edx +\s*[a-f0-9]+:\s*67 0f 41 90 90 90 90 90 cmovno -0x6f6f6f70\(%eax\),%edx +\s*[a-f0-9]+:\s*67 0f 42 90 90 90 90 90 cmovb -0x6f6f6f70\(%eax\),%edx +\s*[a-f0-9]+:\s*67 0f 43 90 90 90 90 90 cmovae -0x6f6f6f70\(%eax\),%edx +\s*[a-f0-9]+:\s*67 0f 44 90 90 90 90 90 cmove -0x6f6f6f70\(%eax\),%edx +\s*[a-f0-9]+:\s*67 0f 45 90 90 90 90 90 cmovne -0x6f6f6f70\(%eax\),%edx +\s*[a-f0-9]+:\s*67 0f 46 90 90 90 90 90 cmovbe -0x6f6f6f70\(%eax\),%edx +\s*[a-f0-9]+:\s*67 0f 47 90 90 90 90 90 cmova -0x6f6f6f70\(%eax\),%edx +\s*[a-f0-9]+:\s*67 0f 48 90 90 90 90 90 cmovs -0x6f6f6f70\(%eax\),%edx +\s*[a-f0-9]+:\s*67 0f 49 90 90 90 90 90 cmovns -0x6f6f6f70\(%eax\),%edx +\s*[a-f0-9]+:\s*67 0f 4a 90 90 90 90 90 cmovp -0x6f6f6f70\(%eax\),%edx +\s*[a-f0-9]+:\s*67 0f 4b 90 90 90 90 90 cmovnp -0x6f6f6f70\(%eax\),%edx +\s*[a-f0-9]+:\s*67 0f 4c 90 90 90 90 90 cmovl -0x6f6f6f70\(%eax\),%edx +\s*[a-f0-9]+:\s*67 0f 4d 90 90 90 90 90 cmovge -0x6f6f6f70\(%eax\),%edx +\s*[a-f0-9]+:\s*67 0f 4e 90 90 90 90 90 cmovle -0x6f6f6f70\(%eax\),%edx +\s*[a-f0-9]+:\s*67 0f 4f 90 90 90 90 90 cmovg -0x6f6f6f70\(%eax\),%edx +\s*[a-f0-9]+:\s*67 0f af 90 09 09 09 00 imul 0x90909\(%eax\),%edx +\s*[a-f0-9]+:\s*d5 aa af 94 f8 09 09 00 00 imul 0x909\(%rax,%r31,8\),%rdx +\s*[a-f0-9]+:\s*48 0f af d0 imul %rax,%rdx diff --git a/gas/testsuite/gas/i386/x86-64-apx-ndd-optimize.s b/gas/testsuite/gas/i386/x86-64-apx-ndd-optimize.s new file mode 100644 index 00000000000..80c39059143 --- /dev/null +++ b/gas/testsuite/gas/i386/x86-64-apx-ndd-optimize.s @@ -0,0 +1,119 @@ +# Check 64bit APX NDD instructions with optimized encoding + + .text +_start: +inc %r31,%r31 +incb %r31b,%r31b +add %r31,%r8,%r8 +addb %r31b,%r8b,%r8b +{store} add %r31,%r8,%r8 +{load} add %r31,%r8,%r8 +add %r31,(%r8),%r31 +add (%r31),%r8,%r8 +add $0x12344433,%r15,%r15 +add $0xfffffffff4332211,%r8,%r8 +dec %r17,%r17 +decb %r17b,%r17b +not %r17,%r17 +notb %r17b,%r17b +neg %r17,%r17 +negb %r17b,%r17b +sub %r15,%r17,%r17 +subb %r15b,%r17b,%r17b +sub %r15,(%r8),%r15 +sub (%r15,%rax,1),%r16,%r16 +sub $0x1234,%r30,%r30 +sbb %r15,%r17,%r17 +sbbb %r15b,%r17b,%r17b +sbb %r15,(%r8),%r15 +sbb (%r15,%rax,1),%r16,%r16 +sbb $0x1234,%r30,%r30 +adc %r15,%r17,%r17 +adcb %r15b,%r17b,%r17b +adc %r15,(%r8),%r15 +adc (%r15,%rax,1),%r16,%r16 +adc $0x1234,%r30,%r30 +or %r15,%r17,%r17 +orb %r15b,%r17b,%r17b +or %r15,(%r8),%r15 +or (%r15,%rax,1),%r16,%r16 +or $0x1234,%r30,%r30 +xor %r15,%r17,%r17 +xorb %r15b,%r17b,%r17b +xor %r15,(%r8),%r15 +xor (%r15,%rax,1),%r16,%r16 +xor $0x1234,%r30,%r30 +and %r15,%r17,%r17 +andb %r15b,%r17b,%r17b +and %r15,(%r8),%r15 +and (%r15,%rax,1),%r16,%r16 +and $0x1234,%r30,%r30 +ror %r31,%r31 +rorb %r31b,%r31b +ror $0x2,%r12,%r12 +rorb $0x2,%r12b,%r12b +rol %r31,%r31 +rolb %r31b,%r31b +rol $0x2,%r12,%r12 +rolb $0x2,%r12b,%r12b +rcr %r31,%r31 +rcrb %r31b,%r31b +rcr $0x2,%r12,%r12 +rcrb $0x2,%r12b,%r12b +rcl %r31,%r31 +rclb %r31b,%r31b +rcl $0x2,%r12,%r12 +rclb $0x2,%r12b,%r12b +sal %r31,%r31 +salb %r31b,%r31b +sal $0x2,%r12,%r12 +salb $0x2,%r12b,%r12b +sar %r31,%r31 +sarb %r31b,%r31b +sar $0x2,%r12,%r12 +sarb $0x2,%r12b,%r12b +shl %r31,%r31 +shlb %r31b,%r31b +shl $0x2,%r12,%r12 +shlb $0x2,%r12b,%r12b +shr %r31,%r31 +shrb %r31b,%r31b +shr $0x2,%r12,%r12 +shrb $0x2,%r12b,%r12b +shld $0x1,%r12,(%rax),%r12 +shld $0x2,%r8,%r12,%r12 +shld $0x2,%r8,%r12,%r8 +shld %cl,%r9,(%rax),%r9 +shld %cl,%r12,%r16,%r16 +shld %cl,%r12,%r16,%r12 +shrd $0x1,%r12,(%rax),%r12 +shrd $0x1,%r13,%r12,%r12 +shrd $0x1,%r13,%r12,%r13 +shrd %cl,%r9,(%rax),%r9 +shrd %cl,%r12,%r16,%r16 +shrd %cl,%r12,%r16,%r12 +adcx %r15,%r8,%r8 +adcx (%r15,%r31,1),%r8,%r8 +adcx %r8,%r9,%r8 +adox %r15,%r8,%r8 +adox (%r15,%r31,1),%r8,%r8 +adox %r8,%r9,%r8 +cmovo 0x90909090(%eax),%edx,%edx +cmovno 0x90909090(%eax),%edx,%edx +cmovb 0x90909090(%eax),%edx,%edx +cmovae 0x90909090(%eax),%edx,%edx +cmove 0x90909090(%eax),%edx,%edx +cmovne 0x90909090(%eax),%edx,%edx +cmovbe 0x90909090(%eax),%edx,%edx +cmova 0x90909090(%eax),%edx,%edx +cmovs 0x90909090(%eax),%edx,%edx +cmovns 0x90909090(%eax),%edx,%edx +cmovp 0x90909090(%eax),%edx,%edx +cmovnp 0x90909090(%eax),%edx,%edx +cmovl 0x90909090(%eax),%edx,%edx +cmovge 0x90909090(%eax),%edx,%edx +cmovle 0x90909090(%eax),%edx,%edx +cmovg 0x90909090(%eax),%edx,%edx +imul 0x90909(%eax),%edx,%edx +imul 0x909(%rax,%r31,8),%rdx,%rdx +imul %rdx,%rax,%rdx diff --git a/gas/testsuite/gas/i386/x86-64.exp b/gas/testsuite/gas/i386/x86-64.exp index 668b366a212..eab99f9e52b 100644 --- a/gas/testsuite/gas/i386/x86-64.exp +++ b/gas/testsuite/gas/i386/x86-64.exp @@ -552,6 +552,7 @@ run_dump_test "x86-64-optimize-6" run_list_test "x86-64-optimize-7a" "-I${srcdir}/$subdir -march=+noavx -al" run_dump_test "x86-64-optimize-7b" run_list_test "x86-64-optimize-8" "-I${srcdir}/$subdir -march=+noavx2 -al" +run_dump_test "x86-64-apx-ndd-optimize" run_dump_test "x86-64-align-branch-1a" run_dump_test "x86-64-align-branch-1b" run_dump_test "x86-64-align-branch-1c" -- 2.31.1