From: Jin Ma <jinma@linux.alibaba.com>
To: binutils@sourceware.org, nelson@rivosinc.com
Cc: christoph.muellner@vrull.eu, lifang_xia@linux.alibaba.com,
jinma.contrib@gmail.com, Jin Ma <jinma@linux.alibaba.com>
Subject: [PATCH] RISC-V: Fix the wrong encoding and operand of the XTheadFmv extension.
Date: Fri, 17 Nov 2023 14:20:53 +0800 [thread overview]
Message-ID: <20231117062053.1873-1-jinma@linux.alibaba.com> (raw)
The description of instructions 'th.fmv.hw.x' and 'th.fmv.x.hw' of the
XTheadFmv extension in T-Head specific is incorrect, and it also has
some impact on the implementation of the binutils, so this patch
corrects this.
For details see:
https://github.com/T-head-Semi/thead-extension-spec/pull/34
gas/ChangeLog:
* testsuite/gas/riscv/x-thead-fmv.d: Correct test.
* testsuite/gas/riscv/x-thead-fmv.s: Likewise.
include/ChangeLog:
* opcode/riscv-opc.h (MATCH_TH_FMV_HW_X): Correct coding.
(MASK_TH_FMV_HW_X): Likewise.
(MATCH_TH_FMV_X_HW): Likewise.
(MASK_TH_FMV_X_HW): Likewise.
opcodes/ChangeLog:
* riscv-opc.c: Correct operands.
---
gas/testsuite/gas/riscv/x-thead-fmv.d | 4 ++--
gas/testsuite/gas/riscv/x-thead-fmv.s | 2 +-
include/opcode/riscv-opc.h | 8 ++++----
opcodes/riscv-opc.c | 2 +-
4 files changed, 8 insertions(+), 8 deletions(-)
diff --git a/gas/testsuite/gas/riscv/x-thead-fmv.d b/gas/testsuite/gas/riscv/x-thead-fmv.d
index af8ce0c8ee0..50ccc62413f 100644
--- a/gas/testsuite/gas/riscv/x-thead-fmv.d
+++ b/gas/testsuite/gas/riscv/x-thead-fmv.d
@@ -7,5 +7,5 @@
Disassembly of section .text:
0+000 <target>:
-[ ]+[0-9a-f]+:[ ]+5005950b[ ]+th.fmv.hw.x[ ]+a0,fa1
-[ ]+[0-9a-f]+:[ ]+6005158b[ ]+th.fmv.x.hw[ ]+a1,fa0
+[ ]+[0-9a-f]+:[ ]+a005158b[ ]+th.fmv.hw.x[ ]+fa1,a0
+[ ]+[0-9a-f]+:[ ]+c005158b[ ]+th.fmv.x.hw[ ]+a1,fa0
diff --git a/gas/testsuite/gas/riscv/x-thead-fmv.s b/gas/testsuite/gas/riscv/x-thead-fmv.s
index 250ba8358ae..8ca2ec2f093 100644
--- a/gas/testsuite/gas/riscv/x-thead-fmv.s
+++ b/gas/testsuite/gas/riscv/x-thead-fmv.s
@@ -1,3 +1,3 @@
target:
- th.fmv.hw.x a0, fa1
+ th.fmv.hw.x fa1, a0
th.fmv.x.hw a1, fa0
diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h
index 24217062edc..061e35d8603 100644
--- a/include/opcode/riscv-opc.h
+++ b/include/opcode/riscv-opc.h
@@ -2515,10 +2515,10 @@
#define MATCH_TH_FSURW 0x5000700b
#define MASK_TH_FSURW 0xf800707f
/* Vendor-specific (T-Head) XTheadFmv instructions. */
-#define MATCH_TH_FMV_HW_X 0x5000100b
-#define MASK_TH_FMV_HW_X 0xfff0707f
-#define MATCH_TH_FMV_X_HW 0x6000100b
-#define MASK_TH_FMV_X_HW 0xfff0707f
+#define MATCH_TH_FMV_X_HW 0xc000100b
+#define MASK_TH_FMV_X_HW 0xfff0707f
+#define MATCH_TH_FMV_HW_X 0xa000100b
+#define MASK_TH_FMV_HW_X 0xfff0707f
/* Vendor-specific (T-Head) XTheadInt instructions. */
#define MATCH_TH_IPOP 0x0050000b
#define MASK_TH_IPOP 0xffffffff
diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
index 72d727cd77e..3a4ab62d274 100644
--- a/opcodes/riscv-opc.c
+++ b/opcodes/riscv-opc.c
@@ -2157,7 +2157,7 @@ const struct riscv_opcode riscv_opcodes[] =
{"th.fsurw", 0, INSN_CLASS_XTHEADFMEMIDX, "D,s,t,Xtu2@25", MATCH_TH_FSURW, MASK_TH_FSURW, match_opcode, 0},
/* Vendor-specific (T-Head) XTheadFmv instructions. */
-{"th.fmv.hw.x", 32, INSN_CLASS_XTHEADFMV, "d,S", MATCH_TH_FMV_HW_X, MASK_TH_FMV_HW_X, match_opcode, 0},
+{"th.fmv.hw.x", 32, INSN_CLASS_XTHEADFMV, "D,s", MATCH_TH_FMV_HW_X, MASK_TH_FMV_HW_X, match_opcode, 0},
{"th.fmv.x.hw", 32, INSN_CLASS_XTHEADFMV, "d,S", MATCH_TH_FMV_X_HW, MASK_TH_FMV_X_HW, match_opcode, 0},
/* Vendor-specific (T-Head) XTheadInt instructions. */
base-commit: 0da4f405f8d9d15b9381075debce788251e31815
--
2.17.1
next reply other threads:[~2023-11-17 6:21 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-11-17 6:20 Jin Ma [this message]
2023-12-13 7:00 ` Christoph Müllner
2023-12-14 3:05 ` Nelson Chu
2023-12-14 8:57 ` Christoph Müllner
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