From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from out30-133.freemail.mail.aliyun.com (out30-133.freemail.mail.aliyun.com [115.124.30.133]) by sourceware.org (Postfix) with ESMTPS id 50B333858D20 for ; Sat, 18 Nov 2023 06:49:47 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 50B333858D20 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=linux.alibaba.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=linux.alibaba.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 50B333858D20 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=115.124.30.133 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1700290189; cv=none; b=WvDd6oIukwzx+0kL8uZjWetjXDnSV0KAyNHezIARARM0t59WYv1ESiGGiwbE1YzvzcfewoG08l/8+NYead8coHRTxrlsRM/YXjBPip9uJEvdB+usMxvsmFVUzezdwpsYLT3jUk2kPdPRRNtPBqdxqldzk3q8mvYXEXDxb1O2j7c= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1700290189; c=relaxed/simple; bh=JaGjXgdYiOoLFLyfQMauNySMxbAoSi1tsh3negggNB4=; h=From:To:Subject:Date:Message-Id:MIME-Version; b=kUbLNz3dBpbw5ol3KsQDHi7ckFXFZ8OHWiKG90NV+yRoII1ILpTPcMPtZfF/b/fLgK/rRo5EDw5Z9X9o9QiyFLGkWhbSlgBWyDySE7ZpPHCSp9wJUf0zV52mzV8YQe4sWt+yZPFI+r47dBZGUmttpszps7EQ3q+e2cIdRyoahF8= ARC-Authentication-Results: i=1; server2.sourceware.org X-Alimail-AntiSpam:AC=PASS;BC=-1|-1;BR=01201311R961e4;CH=green;DM=||false|;DS=||;FP=0|-1|-1|-1|0|-1|-1|-1;HT=ay29a033018046050;MF=jinma@linux.alibaba.com;NM=1;PH=DS;RN=6;SR=0;TI=SMTPD_---0VwbcQkO_1700290180; Received: from localhost.localdomain(mailfrom:jinma@linux.alibaba.com fp:SMTPD_---0VwbcQkO_1700290180) by smtp.aliyun-inc.com; Sat, 18 Nov 2023 14:49:43 +0800 From: Jin Ma To: binutils@sourceware.org, nelson@rivosinc.com Cc: christoph.muellner@vrull.eu, lifang_xia@linux.alibaba.com, jinma.contrib@gmail.com, Jin Ma Subject: [PATCH v2 00/12] RISC-V: Add T-Head VECTOR vendor extension. Date: Sat, 18 Nov 2023 14:49:28 +0800 Message-Id: <20231118064928.849-1-jinma@linux.alibaba.com> X-Mailer: git-send-email 2.21.0 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-14.5 required=5.0 tests=BAYES_00,ENV_AND_HDR_SPF_MATCH,KAM_DMARC_STATUS,RCVD_IN_DNSWL_NONE,RCVD_IN_MSPIKE_H2,SPF_HELO_NONE,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE,UNPARSEABLE_RELAY,USER_IN_DEF_SPF_WL autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: V1 -> V2: V2 adopted the review comments of Nelson and modified the instructions encoding of vendor: Reuse the instruction encoding of the "V" extension as much as possible and remove redundant instructions encoding. V1: T-Head has a range of vendor-specific instructions ([2]). Therefore it makes sense to group them into smaller chunks in form of vendor extensions. This patch adds the "XTheadVector" extension, a collection of T-Head-specific vector instructions. The 'th' prefix and the "XTheadVector" extension are documented in a PR for the RISC-V toolchain conventions ([1]). Here are some things that need to be explained: The "XTheadVector" extension is not a custom-extension, but a non-standard non-conforming extension. The encoding space of the "TheadVector" instructions overlaps with those of the 'V' extension. This encoding space conflict is not on purpose, but the result of issues in the past that have been resolved since. Therefore, the "XTheadVector" extension and the 'V' extension are in conflict. [1] https://github.com/riscv-non-isa/riscv-toolchain-conventions/pull/19 [2] https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.3.0/xthead-2023-11-10-2.3.0.pdf Co-developed-by: Lifang Xia Co-developed-by: Christoph Müllner --- bfd/elfxx-riscv.c | 17 + gas/NEWS | 3 + gas/config/tc-riscv.c | 4 + gas/doc/c-riscv.texi | 11 + .../gas/riscv/x-thead-vector-csr-warn.d | 3 + .../gas/riscv/x-thead-vector-csr-warn.l | 16 + gas/testsuite/gas/riscv/x-thead-vector-csr.d | 21 + gas/testsuite/gas/riscv/x-thead-vector-csr.s | 13 + gas/testsuite/gas/riscv/x-thead-vector-fail.d | 3 + gas/testsuite/gas/riscv/x-thead-vector-fail.l | 2 + .../gas/riscv/x-thead-vector-zvamo.d | 81 + .../gas/riscv/x-thead-vector-zvamo.s | 74 + gas/testsuite/gas/riscv/x-thead-vector.d | 1650 ++++++++++++++++ gas/testsuite/gas/riscv/x-thead-vector.s | 1726 +++++++++++++++++ include/opcode/riscv-opc.h | 328 ++++ include/opcode/riscv.h | 2 + opcodes/riscv-dis.c | 14 +- opcodes/riscv-opc.c | 661 +++++++ 18 files changed, 4627 insertions(+), 2 deletions(-) create mode 100644 gas/testsuite/gas/riscv/x-thead-vector-csr-warn.d create mode 100644 gas/testsuite/gas/riscv/x-thead-vector-csr-warn.l create mode 100644 gas/testsuite/gas/riscv/x-thead-vector-csr.d create mode 100644 gas/testsuite/gas/riscv/x-thead-vector-csr.s create mode 100644 gas/testsuite/gas/riscv/x-thead-vector-fail.d create mode 100644 gas/testsuite/gas/riscv/x-thead-vector-fail.l create mode 100644 gas/testsuite/gas/riscv/x-thead-vector-zvamo.d create mode 100644 gas/testsuite/gas/riscv/x-thead-vector-zvamo.s create mode 100644 gas/testsuite/gas/riscv/x-thead-vector.d create mode 100644 gas/testsuite/gas/riscv/x-thead-vector.s -- 2.17.1