From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from out30-124.freemail.mail.aliyun.com (out30-124.freemail.mail.aliyun.com [115.124.30.124]) by sourceware.org (Postfix) with ESMTPS id F2B973858D1E for ; Sat, 18 Nov 2023 07:09:22 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org F2B973858D1E Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=linux.alibaba.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=linux.alibaba.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org F2B973858D1E Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=115.124.30.124 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1700291365; cv=none; b=Fw72jh6IoU6eUTTQn/w7tWVvSvUFmzJl7lk7TuGYt6RQW8PtZukKjkxZpPpE1K6dWE4aGck7rENZyL+zLr4FYiblMWeSoKF62L1F/eRXz0usqVuhQmnvmo9awV6sTnZTPKT3sV79MSxLIkqsAQppxZl8J11pNkHkWa+YV1iBEOc= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1700291365; c=relaxed/simple; bh=gxPi13VTgnLeWiXodJSHirSZbOMpmSbdFl3yMpfEMgo=; h=From:To:Subject:Date:Message-Id:MIME-Version; b=fnEtO0f1Oi55sXW8Fcd5HB/axA3e0IXifZIcwZhkT1wzHuwlXJ/W5ppksSUdWaB+J3Wgzsq2FIKdxOJ3b+zQ2Au3RoNFV5KgF+lLkCrQIFiM9GYO4JqzXI1/hmIL1/v4AkD5xUYLpOej5cpw3xig+e1v9l+uOBkXyxKDVd9zIrA= ARC-Authentication-Results: i=1; server2.sourceware.org X-Alimail-AntiSpam:AC=PASS;BC=-1|-1;BR=01201311R211e4;CH=green;DM=||false|;DS=||;FP=0|-1|-1|-1|0|-1|-1|-1;HT=ay29a033018045170;MF=jinma@linux.alibaba.com;NM=1;PH=DS;RN=6;SR=0;TI=SMTPD_---0Vwbjbgv_1700291358; Received: from localhost.localdomain(mailfrom:jinma@linux.alibaba.com fp:SMTPD_---0Vwbjbgv_1700291358) by smtp.aliyun-inc.com; Sat, 18 Nov 2023 15:09:20 +0800 From: Jin Ma To: binutils@sourceware.org, nelson@rivosinc.com Cc: christoph.muellner@vrull.eu, lifang_xia@linux.alibaba.com, jinma.contrib@gmail.com, Jin Ma Subject: [PATCH v2 12/12] RISC-V: Add vector permutation instructions for T-Head VECTOR vendor extension Date: Sat, 18 Nov 2023 15:08:59 +0800 Message-Id: <20231118070859.1601-1-jinma@linux.alibaba.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20231118064928.849-1-jinma@linux.alibaba.com> References: <20231118064928.849-1-jinma@linux.alibaba.com> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-20.4 required=5.0 tests=BAYES_00,ENV_AND_HDR_SPF_MATCH,GIT_PATCH_0,KAM_DMARC_STATUS,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE,UNPARSEABLE_RELAY,USER_IN_DEF_SPF_WL autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: T-Head has a range of vendor-specific instructions. Therefore it makes sense to group them into smaller chunks in form of vendor extensions. This patch adds permutation instructions for the "XTheadVector" extension. The 'th' prefix and the "XTheadVector" extension are documented in a PR for the RISC-V toolchain conventions ([1]). [1] https://github.com/riscv-non-isa/riscv-toolchain-conventions/pull/19 Co-developed-by: Lifang Xia Co-developed-by: Christoph Müllner gas/ChangeLog: * testsuite/gas/riscv/x-thead-vector.d: Add tests for permutation instructions. * testsuite/gas/riscv/x-thead-vector.s: Likewise. include/ChangeLog: * opcode/riscv-opc.h (MATCH_TH_VMVXS): New. opcodes/ChangeLog: * riscv-opc.c: Likewise. --- gas/testsuite/gas/riscv/x-thead-vector.d | 30 +++++++++++++++++++ gas/testsuite/gas/riscv/x-thead-vector.s | 38 ++++++++++++++++++++++++ include/opcode/riscv-opc.h | 10 +++++++ opcodes/riscv-opc.c | 15 ++++++++++ 4 files changed, 93 insertions(+) diff --git a/gas/testsuite/gas/riscv/x-thead-vector.d b/gas/testsuite/gas/riscv/x-thead-vector.d index 03d8ede7c77..014c2fdb80d 100644 --- a/gas/testsuite/gas/riscv/x-thead-vector.d +++ b/gas/testsuite/gas/riscv/x-thead-vector.d @@ -1618,3 +1618,33 @@ Disassembly of section .text: [ ]+[0-9a-f]+:[ ]+58812257[ ]+th.vmsof.m[ ]+v4,v8,v0.t [ ]+[0-9a-f]+:[ ]+58882257[ ]+th.viota.m[ ]+v4,v8,v0.t [ ]+[0-9a-f]+:[ ]+5808a257[ ]+th.vid.v[ ]+v4,v0.t +[ ]+[0-9a-f]+:[ ]+32c02557[ ]+th.vmv.x.s[ ]+a0,v12 +[ ]+[0-9a-f]+:[ ]+32c62557[ ]+th.vext.x.v[ ]+a0,v12,a2 +[ ]+[0-9a-f]+:[ ]+36056257[ ]+th.vmv.s.x[ ]+v4,a0 +[ ]+[0-9a-f]+:[ ]+32801557[ ]+th.vfmv.f.s[ ]+fa0,v8 +[ ]+[0-9a-f]+:[ ]+3605d257[ ]+th.vfmv.s.f[ ]+v4,fa1 +[ ]+[0-9a-f]+:[ ]+3a85c257[ ]+th.vslideup.vx[ ]+v4,v8,a1 +[ ]+[0-9a-f]+:[ ]+3a803257[ ]+th.vslideup.vi[ ]+v4,v8,0 +[ ]+[0-9a-f]+:[ ]+3a8fb257[ ]+th.vslideup.vi[ ]+v4,v8,31 +[ ]+[0-9a-f]+:[ ]+3e85c257[ ]+th.vslidedown.vx[ ]+v4,v8,a1 +[ ]+[0-9a-f]+:[ ]+3e803257[ ]+th.vslidedown.vi[ ]+v4,v8,0 +[ ]+[0-9a-f]+:[ ]+3e8fb257[ ]+th.vslidedown.vi[ ]+v4,v8,31 +[ ]+[0-9a-f]+:[ ]+3885c257[ ]+th.vslideup.vx[ ]+v4,v8,a1,v0.t +[ ]+[0-9a-f]+:[ ]+38803257[ ]+th.vslideup.vi[ ]+v4,v8,0,v0.t +[ ]+[0-9a-f]+:[ ]+388fb257[ ]+th.vslideup.vi[ ]+v4,v8,31,v0.t +[ ]+[0-9a-f]+:[ ]+3c85c257[ ]+th.vslidedown.vx[ ]+v4,v8,a1,v0.t +[ ]+[0-9a-f]+:[ ]+3c803257[ ]+th.vslidedown.vi[ ]+v4,v8,0,v0.t +[ ]+[0-9a-f]+:[ ]+3c8fb257[ ]+th.vslidedown.vi[ ]+v4,v8,31,v0.t +[ ]+[0-9a-f]+:[ ]+3a85e257[ ]+th.vslide1up.vx[ ]+v4,v8,a1 +[ ]+[0-9a-f]+:[ ]+3e85e257[ ]+th.vslide1down.vx[ ]+v4,v8,a1 +[ ]+[0-9a-f]+:[ ]+3885e257[ ]+th.vslide1up.vx[ ]+v4,v8,a1,v0.t +[ ]+[0-9a-f]+:[ ]+3c85e257[ ]+th.vslide1down.vx[ ]+v4,v8,a1,v0.t +[ ]+[0-9a-f]+:[ ]+32860257[ ]+th.vrgather.vv[ ]+v4,v8,v12 +[ ]+[0-9a-f]+:[ ]+3285c257[ ]+th.vrgather.vx[ ]+v4,v8,a1 +[ ]+[0-9a-f]+:[ ]+32803257[ ]+th.vrgather.vi[ ]+v4,v8,0 +[ ]+[0-9a-f]+:[ ]+328fb257[ ]+th.vrgather.vi[ ]+v4,v8,31 +[ ]+[0-9a-f]+:[ ]+30860257[ ]+th.vrgather.vv[ ]+v4,v8,v12,v0.t +[ ]+[0-9a-f]+:[ ]+3085c257[ ]+th.vrgather.vx[ ]+v4,v8,a1,v0.t +[ ]+[0-9a-f]+:[ ]+30803257[ ]+th.vrgather.vi[ ]+v4,v8,0,v0.t +[ ]+[0-9a-f]+:[ ]+308fb257[ ]+th.vrgather.vi[ ]+v4,v8,31,v0.t +[ ]+[0-9a-f]+:[ ]+5e862257[ ]+th.vcompress.vm[ ]+v4,v8,v12 diff --git a/gas/testsuite/gas/riscv/x-thead-vector.s b/gas/testsuite/gas/riscv/x-thead-vector.s index 1c1c27cb6d8..3a4dea38c8b 100644 --- a/gas/testsuite/gas/riscv/x-thead-vector.s +++ b/gas/testsuite/gas/riscv/x-thead-vector.s @@ -1686,3 +1686,41 @@ th.vmsof.m v4, v8, v0.t th.viota.m v4, v8, v0.t th.vid.v v4, v0.t + + # Alias + th.vmv.x.s a0, v12 + + th.vext.x.v a0, v12, a2 + th.vmv.s.x v4, a0 + + th.vfmv.f.s fa0, v8 + th.vfmv.s.f v4, fa1 + + th.vslideup.vx v4, v8, a1 + th.vslideup.vi v4, v8, 0 + th.vslideup.vi v4, v8, 31 + th.vslidedown.vx v4, v8, a1 + th.vslidedown.vi v4, v8, 0 + th.vslidedown.vi v4, v8, 31 + th.vslideup.vx v4, v8, a1, v0.t + th.vslideup.vi v4, v8, 0, v0.t + th.vslideup.vi v4, v8, 31, v0.t + th.vslidedown.vx v4, v8, a1, v0.t + th.vslidedown.vi v4, v8, 0, v0.t + th.vslidedown.vi v4, v8, 31, v0.t + + th.vslide1up.vx v4, v8, a1 + th.vslide1down.vx v4, v8, a1 + th.vslide1up.vx v4, v8, a1, v0.t + th.vslide1down.vx v4, v8, a1, v0.t + + th.vrgather.vv v4, v8, v12 + th.vrgather.vx v4, v8, a1 + th.vrgather.vi v4, v8, 0 + th.vrgather.vi v4, v8, 31 + th.vrgather.vv v4, v8, v12, v0.t + th.vrgather.vx v4, v8, a1, v0.t + th.vrgather.vi v4, v8, 0, v0.t + th.vrgather.vi v4, v8, 31, v0.t + + th.vcompress.vm v4, v8, v12 diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h index 9b4288c8ee2..1e417217b7d 100644 --- a/include/opcode/riscv-opc.h +++ b/include/opcode/riscv-opc.h @@ -2959,6 +2959,16 @@ #define MASK_TH_VIOTAM 0xfc0ff07f #define MATCH_TH_VIDV 0x5808a057 #define MASK_TH_VIDV 0xfdfff07f +#define MATCH_TH_VMVXS 0x32002057 +#define MASK_TH_VMVXS 0xfe0ff07f +#define MATCH_TH_VEXTXV 0x32002057 +#define MASK_TH_VEXTXV 0xfe00707f +#define MATCH_TH_VMVSX 0x36006057 +#define MASK_TH_VMVSX 0xfff0707f +#define MATCH_TH_VFMVFS 0x32001057 +#define MASK_TH_VFMVFS 0xfe0ff07f +#define MATCH_TH_VFMVSF 0x36005057 +#define MASK_TH_VFMVSF 0xfff0707f /* Vendor-specific (Ventana Microsystems) XVentanaCondOps instructions */ #define MATCH_VT_MASKC 0x607b #define MASK_VT_MASKC 0xfe00707f diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c index b9b47cf849e..fcba49972f0 100644 --- a/opcodes/riscv-opc.c +++ b/opcodes/riscv-opc.c @@ -2879,6 +2879,21 @@ const struct riscv_opcode riscv_opcodes[] = {"th.vmsof.m", 0, INSN_CLASS_XTHEADVECTOR, "Vd,VtVm", MATCH_TH_VMSOFM, MASK_TH_VMSOFM, match_opcode, 0}, {"th.viota.m", 0, INSN_CLASS_XTHEADVECTOR, "Vd,VtVm", MATCH_TH_VIOTAM, MASK_TH_VIOTAM, match_opcode, 0}, {"th.vid.v", 0, INSN_CLASS_XTHEADVECTOR, "VdVm", MATCH_TH_VIDV, MASK_TH_VIDV, match_opcode, 0}, +{"th.vmv.x.s", 0, INSN_CLASS_XTHEADVECTOR, "d,Vt", MATCH_TH_VMVXS, MASK_TH_VMVXS, match_opcode, INSN_ALIAS}, +{"th.vext.x.v", 0, INSN_CLASS_XTHEADVECTOR, "d,Vt,s", MATCH_TH_VEXTXV, MASK_TH_VEXTXV, match_opcode, 0}, +{"th.vmv.s.x", 0, INSN_CLASS_XTHEADVECTOR, "Vd,s", MATCH_TH_VMVSX, MASK_TH_VMVSX, match_opcode, 0}, +{"th.vfmv.f.s", 0, INSN_CLASS_XTHEADVECTOR, "D,Vt", MATCH_TH_VFMVFS, MASK_TH_VFMVFS, match_opcode, 0}, +{"th.vfmv.s.f", 0, INSN_CLASS_XTHEADVECTOR, "Vd,S", MATCH_TH_VFMVSF, MASK_TH_VFMVSF, match_opcode, 0}, +{"th.vslideup.vx",0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,sVm", MATCH_VSLIDEUPVX, MASK_VSLIDEUPVX, match_opcode, 0}, +{"th.vslideup.vi",0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VjVm", MATCH_VSLIDEUPVI, MASK_VSLIDEUPVI, match_opcode, 0}, +{"th.vslidedown.vx",0,INSN_CLASS_XTHEADVECTOR, "Vd,Vt,sVm", MATCH_VSLIDEDOWNVX, MASK_VSLIDEDOWNVX, match_opcode, 0}, +{"th.vslidedown.vi",0,INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VjVm", MATCH_VSLIDEDOWNVI, MASK_VSLIDEDOWNVI, match_opcode, 0}, +{"th.vslide1up.vx",0 ,INSN_CLASS_XTHEADVECTOR, "Vd,Vt,sVm", MATCH_VSLIDE1UPVX, MASK_VSLIDE1UPVX, match_opcode, 0}, +{"th.vslide1down.vx",0,INSN_CLASS_XTHEADVECTOR, "Vd,Vt,sVm", MATCH_VSLIDE1DOWNVX, MASK_VSLIDE1DOWNVX, match_opcode, 0}, +{"th.vrgather.vv",0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_VRGATHERVV, MASK_VRGATHERVV, match_opcode, 0}, +{"th.vrgather.vx",0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,sVm", MATCH_VRGATHERVX, MASK_VRGATHERVX, match_opcode, 0}, +{"th.vrgather.vi",0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VjVm", MATCH_VRGATHERVI, MASK_VRGATHERVI, match_opcode, 0}, +{"th.vcompress.vm",0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,Vs", MATCH_VCOMPRESSVM, MASK_VCOMPRESSVM, match_opcode, 0}, /* Vendor-specific (Ventana Microsystems) XVentanaCondOps instructions */ {"vt.maskc", 64, INSN_CLASS_XVENTANACONDOPS, "d,s,t", MATCH_VT_MASKC, MASK_VT_MASKC, match_opcode, 0 }, -- 2.17.1