From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mgamail.intel.com (mgamail.intel.com [192.55.52.88]) by sourceware.org (Postfix) with ESMTPS id F23D83858431 for ; Fri, 24 Nov 2023 07:02:31 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org F23D83858431 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=intel.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org F23D83858431 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=192.55.52.88 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1700809355; cv=none; b=p2pTkbNHkOMt3NkU14gf16DJReEmJkm7iWYB9Q/wijFr0ULx7oUaaI0wOe5uh+zyzqtYHSwsvFUIsLDEyo64Lx5h4bYK9LjPEeklEyagH5Flukxg4+tlq6R3RqokHAJh4t+Ey/A++WoAsjJzpTjVYuU2ivXs/AThioQ0zquadMc= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1700809355; c=relaxed/simple; bh=RegPUzyg4B6eJSV1l51W+NSTcVYN6MS09ziIUn+Nusc=; h=DKIM-Signature:From:To:Subject:Date:Message-Id:MIME-Version; b=ZWKJxFBJUW0t37yJVavR6eEd1g1YAHx1bCZkPx5kK/K9OvT4zfr11hqwDjMAZzmNNJrttnpIZhWRjqVISIu0K4lPXEnanBhZuWg3++3yoVLxuHNXCmsY/m5nBtqJW6HGvt1N/DTKjnOt1ghPgumNFV7ktdr2/eZLgytV8JvBidY= ARC-Authentication-Results: i=1; server2.sourceware.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1700809352; x=1732345352; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=RegPUzyg4B6eJSV1l51W+NSTcVYN6MS09ziIUn+Nusc=; b=kcVlnyPE1Y0hnf+JlPZ6I5qw+4YzjIK0P3wNKsOEYOqtyVlwA8xdi8JS pzOYg1UiT3hLka+bp8FdjPHus2s4ZcjAMdfI12W+E8Y0n6HYoRzWqOW5l eRL7ceZzW8g6HYh/pyQWD8/UDmPTbTHs9df0P+Cg1RsLAMze62N5wKwY0 XFDu12GT5/yD53FSuT6WXiiExu24EtMTxoX/d6GE4OFseRABkZbde/R5Z 4voogc6PcOdy311DDQgNHeiUXBVqXJSEOkkkdI88m5pzZwB6DNAFZ6SWf CgboynY5U7XOOSGlfaZu/CBi0QjoJVzDpPmS+96rq1RkvRIWZ/s9m279I Q==; X-IronPort-AV: E=McAfee;i="6600,9927,10902"; a="423513738" X-IronPort-AV: E=Sophos;i="6.04,223,1695711600"; d="scan'208";a="423513738" Received: from fmviesa001.fm.intel.com ([10.60.135.141]) by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Nov 2023 23:02:30 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.04,223,1695711600"; d="scan'208";a="15880721" Received: from scymds04.sc.intel.com ([10.82.73.238]) by fmviesa001.fm.intel.com with ESMTP; 23 Nov 2023 23:02:30 -0800 Received: from shgcc101.sh.intel.com (shgcc101.sh.intel.com [10.239.85.97]) by scymds04.sc.intel.com (Postfix) with ESMTP id 2F3D2200311D; Thu, 23 Nov 2023 23:02:29 -0800 (PST) From: "Cui, Lili" To: binutils@sourceware.org Cc: jbeulich@suse.com, hongjiu.lu@intel.com, "Mo, Zewei" Subject: [PATCH v3 7/9] Support APX Push2/Pop2 Date: Fri, 24 Nov 2023 07:02:11 +0000 Message-Id: <20231124070213.3886483-7-lili.cui@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20231124070213.3886483-1-lili.cui@intel.com> References: <20231124070213.3886483-1-lili.cui@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-10.0 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,GIT_PATCH_0,KAM_NUMSUBJECT,RCVD_IN_MSPIKE_H3,RCVD_IN_MSPIKE_WL,SPF_HELO_NONE,SPF_NONE,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: From: "Mo, Zewei" PPX functionality for PUSH/POP is not implemented in this patch and will be implemented separately. gas/ChangeLog: 2023-11-21 Zewei Mo H.J. Lu Lili Cui * config/tc-i386.c: (enum i386_error): New unsupported_rsp_register and invalid_src_register_set. (md_assemble): Add handler for unsupported_rsp_register and invalid_src_register_set. (check_APX_operands): Add invalid check for push2/pop2. (match_template): Handle check_APX_operands. * testsuite/gas/i386/i386.exp: Add apx-push2pop2 tests. * testsuite/gas/i386/x86-64.exp: Ditto. * testsuite/gas/i386/x86-64-apx-push2pop2.d: New test. * testsuite/gas/i386/x86-64-apx-push2pop2.s: Ditto. * testsuite/gas/i386/x86-64-apx-push2pop2-intel.d: Ditto. * testsuite/gas/i386/x86-64-apx-push2pop2-inval.l: Ditto. * testsuite/gas/i386/x86-64-apx-push2pop2-inval.s: Ditto. * testsuite/gas/i386/apx-push2pop2-inval.s: Ditto. * testsuite/gas/i386/apx-push2pop2-inval.d: Ditto. * testsuite/gas/i386/x86-64-apx-evex-promoted-bad.d: Added bad testcases for POP2. * testsuite/gas/i386/x86-64-apx-evex-promoted-bad.s: Ditto. opcodes/ChangeLog: * i386-dis-evex-reg.h: Add REG_EVEX_MAP4_8F. * i386-dis-evex-w.h: Add EVEX_W_MAP4_8F_R_0 and EVEX_W_MAP4_FF_R_6 * i386-dis-evex.h: Add REG_EVEX_MAP4_8F. * i386-dis.c (PUSH2_POP2_Fixup): Add special handling for PUSH2/POP2. (get_valid_dis386): Add handler for vector length and address_mode for APX-Push2/Pop2 insn. (nd): define nd as b for EVEX-promoted instrutions. (OP_VEX): Add handler of 64-bit vvvv register for APX-Push2/Pop2 insn. * i386-gen.c: Add Push2Pop2 bitfield. * i386-opc.h: Regenerated. * i386-opc.tbl: Regenerated. --- gas/config/tc-i386.c | 42 +++++++++++++++++++ gas/testsuite/gas/i386/apx-push2pop2-inval.l | 5 +++ gas/testsuite/gas/i386/apx-push2pop2-inval.s | 9 ++++ gas/testsuite/gas/i386/i386.exp | 1 + .../gas/i386/x86-64-apx-evex-promoted-bad.d | 6 ++- .../gas/i386/x86-64-apx-evex-promoted-bad.s | 6 +++ .../gas/i386/x86-64-apx-push2pop2-intel.d | 42 +++++++++++++++++++ .../gas/i386/x86-64-apx-push2pop2-inval.l | 13 ++++++ .../gas/i386/x86-64-apx-push2pop2-inval.s | 17 ++++++++ gas/testsuite/gas/i386/x86-64-apx-push2pop2.d | 42 +++++++++++++++++++ gas/testsuite/gas/i386/x86-64-apx-push2pop2.s | 39 +++++++++++++++++ gas/testsuite/gas/i386/x86-64.exp | 3 ++ opcodes/i386-dis-evex-reg.h | 9 ++++ opcodes/i386-dis-evex-w.h | 10 +++++ opcodes/i386-dis-evex.h | 2 +- opcodes/i386-dis.c | 39 +++++++++++++++-- opcodes/i386-opc.h | 1 + opcodes/i386-opc.tbl | 9 ++++ 18 files changed, 289 insertions(+), 6 deletions(-) create mode 100644 gas/testsuite/gas/i386/apx-push2pop2-inval.l create mode 100644 gas/testsuite/gas/i386/apx-push2pop2-inval.s create mode 100644 gas/testsuite/gas/i386/x86-64-apx-push2pop2-intel.d create mode 100644 gas/testsuite/gas/i386/x86-64-apx-push2pop2-inval.l create mode 100644 gas/testsuite/gas/i386/x86-64-apx-push2pop2-inval.s create mode 100644 gas/testsuite/gas/i386/x86-64-apx-push2pop2.d create mode 100644 gas/testsuite/gas/i386/x86-64-apx-push2pop2.s diff --git a/gas/config/tc-i386.c b/gas/config/tc-i386.c index 1efda914150..e7e104dba07 100644 --- a/gas/config/tc-i386.c +++ b/gas/config/tc-i386.c @@ -248,6 +248,7 @@ enum i386_error invalid_vector_register_set, invalid_tmm_register_set, invalid_dest_and_src_register_set, + invalid_src_register_set, invalid_pseudo_prefix, unsupported_vector_index_register, unsupported_broadcast, @@ -256,6 +257,7 @@ enum i386_error mask_not_on_destination, no_default_mask, unsupported_rc_sae, + unsupported_rsp_register, invalid_register_operand, internal_error, }; @@ -5398,6 +5400,9 @@ md_assemble (char *line) case invalid_dest_and_src_register_set: err_msg = _("destination and source registers must be distinct"); break; + case invalid_src_register_set: + err_msg = _("two source registers must be distinct"); + break; case invalid_pseudo_prefix: err_msg = _("rex2 pseudo prefix cannot be used here"); break; @@ -5422,6 +5427,9 @@ md_assemble (char *line) case unsupported_rc_sae: err_msg = _("unsupported static rounding/sae"); break; + case unsupported_rsp_register: + err_msg = _("cannot be used with %rsp register"); + break; case invalid_register_operand: err_msg = _("invalid register operand"); break; @@ -7113,6 +7121,33 @@ check_EgprOperands (const insn_template *t) return 0; } +/* Check if APX operands are valid for the instruction. */ +static int +check_APX_operands (const insn_template *t) +{ + /* Push2* and Pop2* cannot use RSP and Pop2* cannot pop two same registers. + */ + if (t->mnem_off == MN_push2 || t->mnem_off == MN_push2p + || t->mnem_off == MN_pop2 || t->mnem_off == MN_pop2p) + { + unsigned int reg1 = register_number (i.op[0].regs); + unsigned int reg2 = register_number (i.op[1].regs); + + if (reg1 == 0x4 || reg2 == 0x4) + { + i.error = unsupported_rsp_register; + return 1; + } + if (t->base_opcode == 0x8f && reg1 == reg2) + { + i.error = invalid_src_register_set; + return 1; + } + } + + return 0; +} + /* Helper function for the progress() macro in match_template(). */ static INLINE enum i386_error progress (enum i386_error new, enum i386_error last, @@ -7606,6 +7641,13 @@ match_template (char mnem_suffix) continue; } + /* Check if APX operands are valid. */ + if (check_APX_operands (t)) + { + specific_error = progress (i.error); + continue; + } + /* Check whether to use the shorter VEX encoding for certain insns where the EVEX enconding comes first in the table. This requires the respective AVX-* feature to be explicitly enabled. */ diff --git a/gas/testsuite/gas/i386/apx-push2pop2-inval.l b/gas/testsuite/gas/i386/apx-push2pop2-inval.l new file mode 100644 index 00000000000..a55a71520c8 --- /dev/null +++ b/gas/testsuite/gas/i386/apx-push2pop2-inval.l @@ -0,0 +1,5 @@ +.* Assembler messages: +.*:6: Error: `push2' is only supported in 64-bit mode +.*:7: Error: `push2p' is only supported in 64-bit mode +.*:8: Error: `pop2' is only supported in 64-bit mode +.*:9: Error: `pop2p' is only supported in 64-bit mode diff --git a/gas/testsuite/gas/i386/apx-push2pop2-inval.s b/gas/testsuite/gas/i386/apx-push2pop2-inval.s new file mode 100644 index 00000000000..77166327ed1 --- /dev/null +++ b/gas/testsuite/gas/i386/apx-push2pop2-inval.s @@ -0,0 +1,9 @@ +# Check 32bit APX-PUSH2/POP2 instructions + + .allow_index_reg + .text +_start: + push2 %rax, %rbx + push2p %rax, %rbx + pop2 %rax, %rbx + pop2p %rax, %rbx diff --git a/gas/testsuite/gas/i386/i386.exp b/gas/testsuite/gas/i386/i386.exp index 6ab197089ee..835cc3ecdff 100644 --- a/gas/testsuite/gas/i386/i386.exp +++ b/gas/testsuite/gas/i386/i386.exp @@ -511,6 +511,7 @@ if [gas_32_check] then { run_dump_test "sm4-intel" run_list_test "pbndkb-inval" run_list_test "user_msr-inval" + run_list_test "apx-push2pop2-inval" run_list_test "sg" run_dump_test "clzero" run_dump_test "invlpgb" diff --git a/gas/testsuite/gas/i386/x86-64-apx-evex-promoted-bad.d b/gas/testsuite/gas/i386/x86-64-apx-evex-promoted-bad.d index 2ae0f1a358f..b6ba39a5a25 100644 --- a/gas/testsuite/gas/i386/x86-64-apx-evex-promoted-bad.d +++ b/gas/testsuite/gas/i386/x86-64-apx-evex-promoted-bad.d @@ -28,5 +28,7 @@ Disassembly of section .text: [ ]*[a-f0-9]+:[ ]+67 62 f2 7c 18 f5[ ]+addr32 \(bad\) [ ]*[a-f0-9]+:[ ]+0b ff[ ]+or %edi,%edi [ ]*[a-f0-9]+:[ ]+62 f4 fc 08 ff[ ]+\(bad\) -[ ]*[a-f0-9]+:[ ]+d8[ ]+.byte 0xd8 -#pass +[ ]*[a-f0-9]+:[ ]+d8 ff[ ]+fdivr %st\(7\),%st +[ ]*[a-f0-9]+:[ ]+62 f4 64[ ]+\(bad\) +[ ]*[a-f0-9]+:[ ]+08 8f c0 ff ff ff[ ]+or %cl,-0x40\(%rdi\) +[ ]*[a-f0-9]+:[ ]+62 f4 7c 18 8f c0[ ]+pop2 %rax,\(bad\) diff --git a/gas/testsuite/gas/i386/x86-64-apx-evex-promoted-bad.s b/gas/testsuite/gas/i386/x86-64-apx-evex-promoted-bad.s index c4646dcadb4..2339349bd99 100644 --- a/gas/testsuite/gas/i386/x86-64-apx-evex-promoted-bad.s +++ b/gas/testsuite/gas/i386/x86-64-apx-evex-promoted-bad.s @@ -28,3 +28,9 @@ _start: .byte 0xff #{evex} inc %rax %rbx EVEX.vvvv' != 1111 && EVEX.ND = 0. .insn EVEX.L0.NP.M4.W1 0xff, %rax, %rbx + .byte 0xff + # pop2 %rax, %rbx set EVEX.ND=0. + .byte 0x62,0xf4,0x64,0x08,0x8f,0xc0 + .byte 0xff, 0xff, 0xff + # pop2 %rax set EVEX.vvvv' = 1111. + .byte 0x62,0xf4,0x7c,0x18,0x8f,0xc0 diff --git a/gas/testsuite/gas/i386/x86-64-apx-push2pop2-intel.d b/gas/testsuite/gas/i386/x86-64-apx-push2pop2-intel.d new file mode 100644 index 00000000000..46b21219582 --- /dev/null +++ b/gas/testsuite/gas/i386/x86-64-apx-push2pop2-intel.d @@ -0,0 +1,42 @@ +#as: --64 +#objdump: -dw -Mintel +#name: i386 APX-push2pop2 insns (Intel disassembly) +#source: x86-64-apx-push2pop2.s + +.*: +file format .* + +Disassembly of section \.text: + +0+ <_start>: +\s*[a-f0-9]+:\s*62 f4 7c 18 ff f3\s+push2\s+rax,rbx +\s*[a-f0-9]+:\s*62 fc 3c 18 ff f1\s+push2\s+r8,r17 +\s*[a-f0-9]+:\s*62 d4 04 10 ff f1\s+push2\s+r31,r9 +\s*[a-f0-9]+:\s*62 dc 3c 10 ff f7\s+push2\s+r24,r31 +\s*[a-f0-9]+:\s*62 f4 fc 18 ff f3\s+push2p\s+rax,rbx +\s*[a-f0-9]+:\s*62 fc bc 18 ff f1\s+push2p\s+r8,r17 +\s*[a-f0-9]+:\s*62 d4 84 10 ff f1\s+push2p\s+r31,r9 +\s*[a-f0-9]+:\s*62 dc bc 10 ff f7\s+push2p\s+r24,r31 +\s*[a-f0-9]+:\s*62 f4 64 18 8f c0\s+pop2\s+rbx,rax +\s*[a-f0-9]+:\s*62 d4 74 10 8f c0\s+pop2\s+r17,r8 +\s*[a-f0-9]+:\s*62 dc 34 18 8f c7\s+pop2\s+r9,r31 +\s*[a-f0-9]+:\s*62 dc 04 10 8f c0\s+pop2\s+r31,r24 +\s*[a-f0-9]+:\s*62 f4 e4 18 8f c0\s+pop2p\s+rbx,rax +\s*[a-f0-9]+:\s*62 d4 f4 10 8f c0\s+pop2p\s+r17,r8 +\s*[a-f0-9]+:\s*62 dc b4 18 8f c7\s+pop2p\s+r9,r31 +\s*[a-f0-9]+:\s*62 dc 84 10 8f c0\s+pop2p\s+r31,r24 +\s*[a-f0-9]+:\s*62 f4 7c 18 ff f3\s+push2\s+rax,rbx +\s*[a-f0-9]+:\s*62 fc 3c 18 ff f1\s+push2\s+r8,r17 +\s*[a-f0-9]+:\s*62 d4 04 10 ff f1\s+push2\s+r31,r9 +\s*[a-f0-9]+:\s*62 dc 3c 10 ff f7\s+push2\s+r24,r31 +\s*[a-f0-9]+:\s*62 f4 fc 18 ff f3\s+push2p\s+rax,rbx +\s*[a-f0-9]+:\s*62 fc bc 18 ff f1\s+push2p\s+r8,r17 +\s*[a-f0-9]+:\s*62 d4 84 10 ff f1\s+push2p\s+r31,r9 +\s*[a-f0-9]+:\s*62 dc bc 10 ff f7\s+push2p\s+r24,r31 +\s*[a-f0-9]+:\s*62 f4 64 18 8f c0\s+pop2\s+rbx,rax +\s*[a-f0-9]+:\s*62 d4 74 10 8f c0\s+pop2\s+r17,r8 +\s*[a-f0-9]+:\s*62 dc 34 18 8f c7\s+pop2\s+r9,r31 +\s*[a-f0-9]+:\s*62 dc 04 10 8f c0\s+pop2\s+r31,r24 +\s*[a-f0-9]+:\s*62 f4 e4 18 8f c0\s+pop2p\s+rbx,rax +\s*[a-f0-9]+:\s*62 d4 f4 10 8f c0\s+pop2p\s+r17,r8 +\s*[a-f0-9]+:\s*62 dc b4 18 8f c7\s+pop2p\s+r9,r31 +\s*[a-f0-9]+:\s*62 dc 84 10 8f c0\s+pop2p\s+r31,r24 diff --git a/gas/testsuite/gas/i386/x86-64-apx-push2pop2-inval.l b/gas/testsuite/gas/i386/x86-64-apx-push2pop2-inval.l new file mode 100644 index 00000000000..a23011ea15d --- /dev/null +++ b/gas/testsuite/gas/i386/x86-64-apx-push2pop2-inval.l @@ -0,0 +1,13 @@ +.* Assembler messages: +.*:6: Error: operand size mismatch for `push2' +.*:7: Error: operand size mismatch for `push2' +.*:8: Error: cannot be used with %rsp register for `push2' +.*:9: Error: cannot be used with %rsp register for `push2' +.*:10: Error: operand size mismatch for `push2p' +.*:11: Error: cannot be used with %rsp register for `push2p' +.*:12: Error: operand size mismatch for `pop2' +.*:13: Error: cannot be used with %rsp register for `pop2' +.*:14: Error: cannot be used with %rsp register for `pop2' +.*:15: Error: two source registers must be distinct for `pop2' +.*:16: Error: cannot be used with %rsp register for `pop2p' +.*:17: Error: two source registers must be distinct for `pop2p' diff --git a/gas/testsuite/gas/i386/x86-64-apx-push2pop2-inval.s b/gas/testsuite/gas/i386/x86-64-apx-push2pop2-inval.s new file mode 100644 index 00000000000..83cef97d57e --- /dev/null +++ b/gas/testsuite/gas/i386/x86-64-apx-push2pop2-inval.s @@ -0,0 +1,17 @@ +# Check illegal APX-Push2Pop2 instructions + + .allow_index_reg + .text +_start: + push2 %ax, %bx + push2 %eax, %ebx + push2 %rsp, %r17 + push2 %r17, %rsp + push2p %eax, %ebx + push2p %rsp, %r17 + pop2 %ax, %bx + pop2 %rax, %rsp + pop2 %rsp, %rax + pop2 %r12, %r12 + pop2p %rax, %rsp + pop2p %r12, %r12 diff --git a/gas/testsuite/gas/i386/x86-64-apx-push2pop2.d b/gas/testsuite/gas/i386/x86-64-apx-push2pop2.d new file mode 100644 index 00000000000..54f22a7f94e --- /dev/null +++ b/gas/testsuite/gas/i386/x86-64-apx-push2pop2.d @@ -0,0 +1,42 @@ +#as: --64 +#objdump: -dw +#name: x86_64 APX-push2pop2 insns +#source: x86-64-apx-push2pop2.s + +.*: +file format .* + +Disassembly of section \.text: + +0+ <_start>: +\s*[a-f0-9]+:\s*62 f4 7c 18 ff f3\s+push2\s+%rbx,%rax +\s*[a-f0-9]+:\s*62 fc 3c 18 ff f1\s+push2\s+%r17,%r8 +\s*[a-f0-9]+:\s*62 d4 04 10 ff f1\s+push2\s+%r9,%r31 +\s*[a-f0-9]+:\s*62 dc 3c 10 ff f7\s+push2\s+%r31,%r24 +\s*[a-f0-9]+:\s*62 f4 fc 18 ff f3\s+push2p\s+%rbx,%rax +\s*[a-f0-9]+:\s*62 fc bc 18 ff f1\s+push2p\s+%r17,%r8 +\s*[a-f0-9]+:\s*62 d4 84 10 ff f1\s+push2p\s+%r9,%r31 +\s*[a-f0-9]+:\s*62 dc bc 10 ff f7\s+push2p\s+%r31,%r24 +\s*[a-f0-9]+:\s*62 f4 64 18 8f c0\s+pop2\s+%rax,%rbx +\s*[a-f0-9]+:\s*62 d4 74 10 8f c0\s+pop2\s+%r8,%r17 +\s*[a-f0-9]+:\s*62 dc 34 18 8f c7\s+pop2\s+%r31,%r9 +\s*[a-f0-9]+:\s*62 dc 04 10 8f c0\s+pop2\s+%r24,%r31 +\s*[a-f0-9]+:\s*62 f4 e4 18 8f c0\s+pop2p\s+%rax,%rbx +\s*[a-f0-9]+:\s*62 d4 f4 10 8f c0\s+pop2p\s+%r8,%r17 +\s*[a-f0-9]+:\s*62 dc b4 18 8f c7\s+pop2p\s+%r31,%r9 +\s*[a-f0-9]+:\s*62 dc 84 10 8f c0\s+pop2p\s+%r24,%r31 +\s*[a-f0-9]+:\s*62 f4 7c 18 ff f3\s+push2\s+%rbx,%rax +\s*[a-f0-9]+:\s*62 fc 3c 18 ff f1\s+push2\s+%r17,%r8 +\s*[a-f0-9]+:\s*62 d4 04 10 ff f1\s+push2\s+%r9,%r31 +\s*[a-f0-9]+:\s*62 dc 3c 10 ff f7\s+push2\s+%r31,%r24 +\s*[a-f0-9]+:\s*62 f4 fc 18 ff f3\s+push2p\s+%rbx,%rax +\s*[a-f0-9]+:\s*62 fc bc 18 ff f1\s+push2p\s+%r17,%r8 +\s*[a-f0-9]+:\s*62 d4 84 10 ff f1\s+push2p\s+%r9,%r31 +\s*[a-f0-9]+:\s*62 dc bc 10 ff f7\s+push2p\s+%r31,%r24 +\s*[a-f0-9]+:\s*62 f4 64 18 8f c0\s+pop2\s+%rax,%rbx +\s*[a-f0-9]+:\s*62 d4 74 10 8f c0\s+pop2\s+%r8,%r17 +\s*[a-f0-9]+:\s*62 dc 34 18 8f c7\s+pop2\s+%r31,%r9 +\s*[a-f0-9]+:\s*62 dc 04 10 8f c0\s+pop2\s+%r24,%r31 +\s*[a-f0-9]+:\s*62 f4 e4 18 8f c0\s+pop2p\s+%rax,%rbx +\s*[a-f0-9]+:\s*62 d4 f4 10 8f c0\s+pop2p\s+%r8,%r17 +\s*[a-f0-9]+:\s*62 dc b4 18 8f c7\s+pop2p\s+%r31,%r9 +\s*[a-f0-9]+:\s*62 dc 84 10 8f c0\s+pop2p\s+%r24,%r31 diff --git a/gas/testsuite/gas/i386/x86-64-apx-push2pop2.s b/gas/testsuite/gas/i386/x86-64-apx-push2pop2.s new file mode 100644 index 00000000000..4cfc0a2185f --- /dev/null +++ b/gas/testsuite/gas/i386/x86-64-apx-push2pop2.s @@ -0,0 +1,39 @@ +# Check 64bit APX-Push2Pop2 instructions + + .allow_index_reg + .text +_start: + push2 %rbx, %rax + push2 %r17, %r8 + push2 %r9, %r31 + push2 %r31, %r24 + push2p %rbx, %rax + push2p %r17, %r8 + push2p %r9, %r31 + push2p %r31, %r24 + pop2 %rax, %rbx + pop2 %r8, %r17 + pop2 %r31, %r9 + pop2 %r24, %r31 + pop2p %rax, %rbx + pop2p %r8, %r17 + pop2p %r31, %r9 + pop2p %r24, %r31 + +.intel_syntax noprefix + push2 rax, rbx + push2 r8, r17 + push2 r31, r9 + push2 r24, r31 + push2p rax, rbx + push2p r8, r17 + push2p r31, r9 + push2p r24, r31 + pop2 rbx, rax + pop2 r17, r8 + pop2 r9, r31 + pop2 r31, r24 + pop2p rbx, rax + pop2p r17, r8 + pop2p r9, r31 + pop2p r31, r24 diff --git a/gas/testsuite/gas/i386/x86-64.exp b/gas/testsuite/gas/i386/x86-64.exp index c28e4e7e333..b834379a491 100644 --- a/gas/testsuite/gas/i386/x86-64.exp +++ b/gas/testsuite/gas/i386/x86-64.exp @@ -345,6 +345,9 @@ run_dump_test "x86-64-avx512dq-rcigrd-intel" run_dump_test "x86-64-avx512dq-rcigrd" run_dump_test "x86-64-avx512dq-rcigrne-intel" run_dump_test "x86-64-avx512dq-rcigrne" +run_dump_test "x86-64-apx-push2pop2" +run_dump_test "x86-64-apx-push2pop2-intel" +run_list_test "x86-64-apx-push2pop2-inval" run_dump_test "x86-64-avx512dq-rcigru-intel" run_dump_test "x86-64-avx512dq-rcigru" run_dump_test "x86-64-avx512dq-rcigrz-intel" diff --git a/opcodes/i386-dis-evex-reg.h b/opcodes/i386-dis-evex-reg.h index b7f87c2fa39..bf33f5425da 100644 --- a/opcodes/i386-dis-evex-reg.h +++ b/opcodes/i386-dis-evex-reg.h @@ -86,6 +86,10 @@ { "subQ", { VexGv, Ev, sIb }, PREFIX_NP_OR_DATA }, { "xorQ", { VexGv, Ev, sIb }, PREFIX_NP_OR_DATA }, }, + /* REG_EVEX_MAP4_8F */ + { + { VEX_W_TABLE (EVEX_W_MAP4_8F_R_0) }, + }, /* REG_EVEX_MAP4_F6 */ { { Bad_Opcode }, @@ -109,5 +113,10 @@ { { "incQ", { VexGv, Ev }, PREFIX_NP_OR_DATA }, { "decQ", { VexGv, Ev }, PREFIX_NP_OR_DATA }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { VEX_W_TABLE (EVEX_W_MAP4_FF_R_6) }, }, diff --git a/opcodes/i386-dis-evex-w.h b/opcodes/i386-dis-evex-w.h index b828277d413..12ab29544bb 100644 --- a/opcodes/i386-dis-evex-w.h +++ b/opcodes/i386-dis-evex-w.h @@ -442,6 +442,16 @@ { Bad_Opcode }, { "vpshrdw", { XM, Vex, EXx, Ib }, 0 }, }, + /* EVEX_W_MAP4_8F_R_0 */ + { + { "pop2", { { PUSH2_POP2_Fixup, q_mode}, Eq }, NO_PREFIX }, + { "pop2p", { { PUSH2_POP2_Fixup, q_mode}, Eq }, NO_PREFIX }, + }, + /* EVEX_W_MAP4_FF_R_6 */ + { + { "push2", { { PUSH2_POP2_Fixup, q_mode}, Eq }, 0 }, + { "push2p", { { PUSH2_POP2_Fixup, q_mode}, Eq }, 0 }, + }, /* EVEX_W_MAP5_5B_P_0 */ { { "vcvtdq2ph%XY", { XMxmmq, EXx, EXxEVexR }, 0 }, diff --git a/opcodes/i386-dis-evex.h b/opcodes/i386-dis-evex.h index a6e1eb3250f..e7ee868cf1f 100644 --- a/opcodes/i386-dis-evex.h +++ b/opcodes/i386-dis-evex.h @@ -1035,7 +1035,7 @@ static const struct dis386 evex_table[][256] = { { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, - { Bad_Opcode }, + { REG_TABLE (REG_EVEX_MAP4_8F) }, /* 90 */ { Bad_Opcode }, { Bad_Opcode }, diff --git a/opcodes/i386-dis.c b/opcodes/i386-dis.c index 50b2734108b..0612b0cd4b4 100644 --- a/opcodes/i386-dis.c +++ b/opcodes/i386-dis.c @@ -105,6 +105,7 @@ static bool FXSAVE_Fixup (instr_info *, int, int); static bool MOVSXD_Fixup (instr_info *, int, int); static bool DistinctDest_Fixup (instr_info *, int, int); static bool PREFETCHI_Fixup (instr_info *, int, int); +static bool PUSH2_POP2_Fixup (instr_info *, int, int); static void ATTRIBUTE_PRINTF_3 i386_dis_printf (const disassemble_info *, enum disassembler_style, @@ -225,6 +226,9 @@ struct instr_info } vex; +/* For APX EVEX-promoted prefix, EVEX.ND shares the same bit as vex.b. */ +#define nd b + enum evex_type evex_type; /* Remember if the current op is a jump instruction. */ @@ -899,6 +903,7 @@ enum REG_EVEX_MAP4_80, REG_EVEX_MAP4_81, REG_EVEX_MAP4_83, + REG_EVEX_MAP4_8F, REG_EVEX_MAP4_F6, REG_EVEX_MAP4_F7, REG_EVEX_MAP4_FE, @@ -1742,6 +1747,9 @@ enum EVEX_W_0F3A70, EVEX_W_0F3A72, + EVEX_W_MAP4_8F_R_0, + EVEX_W_MAP4_FF_R_6, + EVEX_W_MAP5_5B_P_0, EVEX_W_MAP5_7A_P_3, }; @@ -9125,7 +9133,7 @@ get_valid_dis386 (const struct dis386 *dp, instr_info *ins) /* EVEX from legacy instructions, when the EVEX.ND bit is 0, all bits of EVEX.vvvv and EVEX.V' must be 1. */ - if (ins->evex_type == evex_from_legacy && !ins->vex.b + if (ins->evex_type == evex_from_legacy && !ins->vex.nd && (ins->vex.register_specifier || !ins->vex.v)) return &bad_opcode; @@ -13388,11 +13396,10 @@ OP_VEX (instr_info *ins, int bytemode, int sizeflag ATTRIBUTE_UNUSED) if (!ins->need_vex) return true; - /* Here vex.b is treated as "EVEX.ND". */ if (ins->evex_type == evex_from_legacy) { ins->evex_used |= EVEX_b_used; - if (!ins->vex.b) + if (!ins->vex.nd) return true; } @@ -13500,6 +13507,9 @@ OP_VEX (instr_info *ins, int bytemode, int sizeflag ATTRIBUTE_UNUSED) case b_mode: names = att_names8rex; break; + case q_mode: + names = att_names64; + break; case mask_bd_mode: case mask_mode: if (reg > 0x7) @@ -13884,3 +13894,26 @@ PREFETCHI_Fixup (instr_info *ins, int bytemode, int sizeflag) return OP_M (ins, bytemode, sizeflag); } + +static bool +PUSH2_POP2_Fixup (instr_info *ins, int bytemode, int sizeflag) +{ + if (ins->modrm.mod != 3 || !ins->vex.b) + return true; + + unsigned int vvvv_reg = ins->vex.register_specifier + | (!ins->vex.v << 4); + unsigned int rm_reg = ins->modrm.rm + (ins->rex & REX_B ? 8 : 0) + + (ins->rex2 & REX_B ? 16 : 0); + + /* Push2/Pop2 cannot use RSP and Pop2 cannot pop two same registers. */ + if (!ins->vex.nd || vvvv_reg == 0x4 || rm_reg == 0x4 + || (!ins->modrm.reg + && vvvv_reg == rm_reg)) + { + oappend (ins, "(bad)"); + return true; + } + + return OP_VEX (ins, bytemode, sizeflag); +} diff --git a/opcodes/i386-opc.h b/opcodes/i386-opc.h index 256f5a3865e..edd59dd67ea 100644 --- a/opcodes/i386-opc.h +++ b/opcodes/i386-opc.h @@ -807,6 +807,7 @@ typedef struct i386_opcode_modifier unsigned int isa64:2; unsigned int noegpr:1; unsigned int nf:1; + unsigned int push2pop2:1; } i386_opcode_modifier; /* Operand classes. */ diff --git a/opcodes/i386-opc.tbl b/opcodes/i386-opc.tbl index 5aa00cb93ef..642e519fe3a 100644 --- a/opcodes/i386-opc.tbl +++ b/opcodes/i386-opc.tbl @@ -3486,3 +3486,12 @@ uwrmsr, 0xf30f38f8, USER_MSR, Modrm|NoSuf|NoRex64, { Reg64, Reg64 } uwrmsr, 0xf3f8/0, USER_MSR, Modrm|Vex128|VexMap7|VexW0|NoSuf, { Imm32, Reg64 } // USER_MSR instructions end. + +// APX Push2/Pop2 instructions. + +push2, 0xff/6, APX_F, Modrm|VexW0|EVex128|EVexMap4|VexVVVV|No_bSuf|No_wSuf|No_lSuf|No_sSuf, { Reg64, Reg64 } +push2p, 0xff/6, APX_F, Modrm|VexW1|EVex128|EVexMap4|VexVVVV|No_bSuf|No_wSuf|No_lSuf|No_sSuf, { Reg64, Reg64 } +pop2, 0x8f/0, APX_F, Modrm|VexW0|EVex128|EVexMap4|VexVVVV|No_bSuf|No_wSuf|No_lSuf|No_sSuf, { Reg64, Reg64 } +pop2p, 0x8f/0, APX_F, Modrm|VexW1|EVex128|EVexMap4|VexVVVV|No_bSuf|No_wSuf|No_lSuf|No_sSuf, { Reg64, Reg64 } + +// APX Push2/Pop2 instructions end. -- 2.25.1