From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail.loongson.cn (mail.loongson.cn [114.242.206.163]) by sourceware.org (Postfix) with ESMTP id 38603385841F for ; Thu, 14 Dec 2023 06:39:26 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 38603385841F Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=loongson.cn Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=loongson.cn ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 38603385841F Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=114.242.206.163 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1702535970; cv=none; b=f2uBhlie/2OggGPxlMxtwXYb2dp7xokLMdIywJGsETFea3XOmarqGV2U5oYIuMywdYvg8kZlLsGel4qzNKDMscsVIhWSZrfgZ2sXVuLTTJVB6oiIof8MYgt7hZgc+5NSE+dbLjo83HFgS6Xg+SkmTqifMgHnIMO2HyndkJVmQ4U= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1702535970; c=relaxed/simple; bh=R3r9CNzJQl8QyUOUt1cZb0OyQp1HG2LScRwz1kJqRZQ=; h=From:To:Subject:Date:Message-Id:MIME-Version; b=ce0k83pEHi9KvmJfkGo0IxkkDJbsIPkTivjB8xTSlYv9c2D7MSvlyte+5kwWtwjYVtR/ulIiXL26dqBOELyczlfyhQRufKnfCbE6HxErfnFfFfcajyq19f1ihai6VpbbUtjzlHgBVrBWmP6oYBe92xllywng8IGIyn11JTpJWug= ARC-Authentication-Results: i=1; server2.sourceware.org Received: from loongson.cn (unknown [10.2.6.5]) by gateway (Coremail) with SMTP id _____8CxRPAco3plUu8AAA--.5352S3; Thu, 14 Dec 2023 14:39:24 +0800 (CST) Received: from 5.5.5 (unknown [10.2.6.5]) by localhost.localdomain (Coremail) with SMTP id AQAAf8Cx3+EWo3pl6cUDAA--.21837S3; Thu, 14 Dec 2023 14:39:23 +0800 (CST) From: mengqinggang To: binutils@sourceware.org Cc: xuchenghua@loongson.cn, chenglulu@loongson.cn, liuzhensong@loongson.cn, cailulu@loongson.cn, xry111@xry111.site, i.swmail@xen0n.name, maskray@google.com, luweining@loongson.cn, wanglei@loongson.cn, hejinyang@loongson.cn, mengqinggang Subject: [PATCH v2 1/2] LoongArch: Add new relocation R_LARCH_CALL36 Date: Thu, 14 Dec 2023 14:39:15 +0800 Message-Id: <20231214063916.2340161-2-mengqinggang@loongson.cn> X-Mailer: git-send-email 2.39.3 In-Reply-To: <20231214063916.2340161-1-mengqinggang@loongson.cn> References: <20231214063916.2340161-1-mengqinggang@loongson.cn> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-CM-TRANSID:AQAAf8Cx3+EWo3pl6cUDAA--.21837S3 X-CM-SenderInfo: 5phqw15lqjwttqj6z05rqj20fqof0/ X-Coremail-Antispam: 1Uk129KBj93XoWxtF4xtFW5Kr47tF4kXr18JFc_yoWfCw4rpw nxZw1YkF48CFnrWF9xKry5ZFs8Ww4xGrW2vaySq3WS9r4DJryUXF4ktrW3ZF45Jw4jqr4I qF1Fqw1UZF48J3cCm3ZEXasCq-sJn29KB7ZKAUJUUUU8529EdanIXcx71UUUUU7KY7ZEXa sCq-sGcSsGvfJ3Ic02F40EFcxC0VAKzVAqx4xG6I80ebIjqfuFe4nvWSU5nxnvy29KBjDU 0xBIdaVrnRJUUUk2b4IE77IF4wAFF20E14v26r1j6r4UM7CY07I20VC2zVCF04k26cxKx2 IYs7xG6rWj6s0DM7CIcVAFz4kK6r106r15M28lY4IEw2IIxxk0rwA2F7IY1VAKz4vEj48v e4kI8wA2z4x0Y4vE2Ix0cI8IcVAFwI0_Gr0_Xr1l84ACjcxK6xIIjxv20xvEc7CjxVAFwI 0_Gr0_Cr1l84ACjcxK6I8E87Iv67AKxVW8Jr0_Cr1UM28EF7xvwVC2z280aVCY1x0267AK xVW8Jr0_Cr1UM2AIxVAIcxkEcVAq07x20xvEncxIr21l57IF6xkI12xvs2x26I8E6xACxx 1l5I8CrVACY4xI64kE6c02F40Ex7xfMcIj6xIIjxv20xvE14v26r126r1DMcIj6I8E87Iv 67AKxVWxJVW8Jr1lOx8S6xCaFVCjc4AY6r1j6r4UM4x0Y48IcxkI7VAKI48JMxAIw28Icx kI7VAKI48JMxC20s026xCaFVCjc4AY6r1j6r4UMI8I3I0E5I8CrVAFwI0_Jr0_Jr4lx2Iq xVCjr7xvwVAFwI0_JrI_JrWlx4CE17CEb7AF67AKxVWUtVW8ZwCIc40Y0x0EwIxGrwCI42 IY6xIIjxv20xvE14v26r1j6r1xMIIF0xvE2Ix0cI8IcVCY1x0267AKxVWUJVW8JwCI42IY 6xAIw20EY4v20xvaj40_Jr0_JF4lIxAIcVC2z280aVAFwI0_Jr0_Gr1lIxAIcVC2z280aV CY1x0267AKxVWUJVW8JbIYCTnIWIevJa73UjIFyTuYvjxUzzuAUUUUU X-Spam-Status: No, score=-12.3 required=5.0 tests=BAYES_00,GIT_PATCH_0,KAM_DMARC_STATUS,KAM_NUMSUBJECT,SPF_HELO_NONE,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: R_LARCH_CALL36 is used for medium code model function call pcaddu18i+jirl, and these two instructions must adjacent. The LoongArch ABI v2.20 at here: https://github.com/loongson/la-abi-specs. --- bfd/bfd-in2.h | 1 + bfd/elfnn-loongarch.c | 19 ++++++++++----- bfd/elfxx-loongarch.c | 24 +++++++++++++++++++ bfd/libbfd.h | 1 + bfd/reloc.c | 3 +++ gas/config/tc-loongarch.c | 6 ++++- gas/testsuite/gas/loongarch/medium-call.d | 15 ++++++++++++ gas/testsuite/gas/loongarch/medium-call.s | 6 +++++ include/elf/loongarch.h | 2 ++ .../ld-loongarch-elf/ld-loongarch-elf.exp | 12 ++++++++++ ld/testsuite/ld-loongarch-elf/medium-call.s | 7 ++++++ 11 files changed, 89 insertions(+), 7 deletions(-) create mode 100644 gas/testsuite/gas/loongarch/medium-call.d create mode 100644 gas/testsuite/gas/loongarch/medium-call.s create mode 100644 ld/testsuite/ld-loongarch-elf/medium-call.s diff --git a/bfd/bfd-in2.h b/bfd/bfd-in2.h index 040d5560cdf..73459a689ae 100644 --- a/bfd/bfd-in2.h +++ b/bfd/bfd-in2.h @@ -7460,6 +7460,7 @@ enum bfd_reloc_code_real BFD_RELOC_LARCH_ADD_ULEB128, BFD_RELOC_LARCH_SUB_ULEB128, BFD_RELOC_LARCH_64_PCREL, + BFD_RELOC_LARCH_CALL36, BFD_RELOC_UNUSED }; typedef enum bfd_reloc_code_real bfd_reloc_code_real_type; diff --git a/bfd/elfnn-loongarch.c b/bfd/elfnn-loongarch.c index 024c5d4cd96..aa88ee8f928 100644 --- a/bfd/elfnn-loongarch.c +++ b/bfd/elfnn-loongarch.c @@ -780,6 +780,7 @@ loongarch_elf_check_relocs (bfd *abfd, struct bfd_link_info *info, case R_LARCH_B16: case R_LARCH_B21: case R_LARCH_B26: + case R_LARCH_CALL36: if (h != NULL) { h->needs_plt = 1; @@ -1884,20 +1885,24 @@ loongarch_check_offset (const Elf_Internal_Rela *rel, ret; \ }) +/* Write immediate to instructions. */ + static bfd_reloc_status_type loongarch_reloc_rewrite_imm_insn (const Elf_Internal_Rela *rel, const asection *input_section ATTRIBUTE_UNUSED, reloc_howto_type *howto, bfd *input_bfd, bfd_byte *contents, bfd_vma reloc_val) { - int bits = bfd_get_reloc_size (howto) * 8; - uint32_t insn = bfd_get (bits, input_bfd, contents + rel->r_offset); - + /* Adjust the immediate based on alignment and + its position in the instruction. */ if (!loongarch_adjust_reloc_bitsfield (input_bfd, howto, &reloc_val)) return bfd_reloc_overflow; - insn = (insn & (uint32_t)howto->src_mask) - | ((insn & (~(uint32_t)howto->dst_mask)) | reloc_val); + int bits = bfd_get_reloc_size (howto) * 8; + uint64_t insn = bfd_get (bits, input_bfd, contents + rel->r_offset); + + /* Write immediate to instruction. */ + insn = (insn & ~howto->dst_mask) | (reloc_val & howto->dst_mask); bfd_put (bits, input_bfd, insn, contents + rel->r_offset); @@ -2120,6 +2125,7 @@ perform_relocation (const Elf_Internal_Rela *rel, asection *input_section, case R_LARCH_TLS_GD_PC_HI20: case R_LARCH_TLS_GD_HI20: case R_LARCH_PCREL20_S2: + case R_LARCH_CALL36: r = loongarch_check_offset (rel, input_section); if (r != bfd_reloc_ok) break; @@ -3127,9 +3133,10 @@ loongarch_elf_relocate_section (bfd *output_bfd, struct bfd_link_info *info, break; /* New reloc types. */ + case R_LARCH_B16: case R_LARCH_B21: case R_LARCH_B26: - case R_LARCH_B16: + case R_LARCH_CALL36: unresolved_reloc = false; if (is_undefweak) { diff --git a/bfd/elfxx-loongarch.c b/bfd/elfxx-loongarch.c index 7f298c08fd3..d93b79043ce 100644 --- a/bfd/elfxx-loongarch.c +++ b/bfd/elfxx-loongarch.c @@ -1547,6 +1547,24 @@ static loongarch_reloc_howto_type loongarch_howto_table[] = NULL, /* adjust_reloc_bits */ NULL), /* larch_reloc_type_name */ + /* Used for medium code model function call pcaddu18i+jirl, + these two instructions must adjacent. */ + LOONGARCH_HOWTO (R_LARCH_CALL36, /* type (110). */ + 2, /* rightshift. */ + 8, /* size. */ + 36, /* bitsize. */ + true, /* pc_relative. */ + 0, /* bitpos. */ + complain_overflow_signed, /* complain_on_overflow. */ + bfd_elf_generic_reloc, /* special_function. */ + "R_LARCH_CALL36", /* name. */ + false, /* partial_inplace. */ + 0, /* src_mask. */ + 0x03fffc0001ffffe0, /* dst_mask. */ + false, /* pcrel_offset. */ + BFD_RELOC_LARCH_CALL36, /* bfd_reloc_code_real_type. */ + reloc_sign_bits, /* adjust_reloc_bits. */ + "call36"), /* larch_reloc_type_name. */ }; reloc_howto_type * @@ -1726,6 +1744,12 @@ reloc_sign_bits (bfd *abfd, reloc_howto_type *howto, bfd_vma *fix_val) /* Perform insn bits field. 15:0<<10, 20:16>>16. */ val = ((val & 0xffff) << 10) | ((val >> 16) & 0x1f); break; + case R_LARCH_CALL36: + /* 0x8000: If low 16-bit immediate greater than 0x7fff, + it become to a negative number due to sign-extended, + so the high part need to add 0x8000. */ + val = (((val + 0x8000) >> 16) << 5) | (((val & 0xffff) << 10) << 32); + break; default: val <<= howto->bitpos; break; diff --git a/bfd/libbfd.h b/bfd/libbfd.h index cc432677a81..399b1f688bb 100644 --- a/bfd/libbfd.h +++ b/bfd/libbfd.h @@ -3599,6 +3599,7 @@ static const char *const bfd_reloc_code_real_names[] = { "@@uninitialized@@", "BFD_RELOC_LARCH_ADD_ULEB128", "BFD_RELOC_LARCH_SUB_ULEB128", "BFD_RELOC_LARCH_64_PCREL", + "BFD_RELOC_LARCH_CALL36", "@@overflow: BFD_RELOC_UNUSED@@", }; #endif diff --git a/bfd/reloc.c b/bfd/reloc.c index 93ebad879e0..4d3ac4c1096 100644 --- a/bfd/reloc.c +++ b/bfd/reloc.c @@ -8292,6 +8292,9 @@ ENUMX ENUMX BFD_RELOC_LARCH_64_PCREL +ENUMX + BFD_RELOC_LARCH_CALL36 + ENUMDOC LARCH relocations. diff --git a/gas/config/tc-loongarch.c b/gas/config/tc-loongarch.c index 59232832cf7..367a0b6c5a4 100644 --- a/gas/config/tc-loongarch.c +++ b/gas/config/tc-loongarch.c @@ -682,7 +682,7 @@ loongarch_args_parser_can_match_arg_helper (char esc_ch1, char esc_ch2, esc_ch1, esc_ch2, bit_field, arg); if (ip->reloc_info[0].type >= BFD_RELOC_LARCH_B16 - && ip->reloc_info[0].type < BFD_RELOC_LARCH_64_PCREL) + && ip->reloc_info[0].type < BFD_RELOC_UNUSED) { /* As we compact stack-relocs, it is no need for pop operation. But break out until here in order to check the imm field. @@ -956,6 +956,10 @@ move_insn (struct loongarch_cl_insn *insn, fragS *frag, long where) static void append_fixed_insn (struct loongarch_cl_insn *insn) { + /* Ensure the jirl is emitted to the same frag as the pcaddu18i. */ + if (BFD_RELOC_LARCH_CALL36 == insn->reloc_info[0].type) + frag_grow (8); + char *f = frag_more (insn->insn_length); move_insn (insn, frag_now, f - frag_now->fr_literal); } diff --git a/gas/testsuite/gas/loongarch/medium-call.d b/gas/testsuite/gas/loongarch/medium-call.d new file mode 100644 index 00000000000..4183818cb4f --- /dev/null +++ b/gas/testsuite/gas/loongarch/medium-call.d @@ -0,0 +1,15 @@ +#as: +#objdump: -dr + +.*:[ ]+file format .* + + +Disassembly of section .text: + +.* <.text>: +[ ]+0:[ ]+1e000001[ ]+pcaddu18i[ ]+\$ra, 0 +[ ]+0: R_LARCH_CALL36[ ]+a +[ ]+4:[ ]+4c000021[ ]+jirl[ ]+\$ra, \$ra, 0 +[ ]+8:[ ]+1e00000c[ ]+pcaddu18i[ ]+\$t0, 0 +[ ]+8: R_LARCH_CALL36[ ]+a +[ ]+c:[ ]+4c000180[ ]+jr[ ]+\$t0 diff --git a/gas/testsuite/gas/loongarch/medium-call.s b/gas/testsuite/gas/loongarch/medium-call.s new file mode 100644 index 00000000000..f2977d1c6d7 --- /dev/null +++ b/gas/testsuite/gas/loongarch/medium-call.s @@ -0,0 +1,6 @@ + # call .L1, r1(ra) temp register, r1(ra) return register. + pcaddu18i $r1, %call36(a) + jirl $r1, $r1, 0 + # tail .L1, r12(t0) temp register, r0(zero) return register. + pcaddu18i $r12, %call36(a) + jirl $r0, $r12, 0 diff --git a/include/elf/loongarch.h b/include/elf/loongarch.h index e31395e13d5..34719ee8b8c 100644 --- a/include/elf/loongarch.h +++ b/include/elf/loongarch.h @@ -251,6 +251,8 @@ RELOC_NUMBER (R_LARCH_SUB_ULEB128, 108) RELOC_NUMBER (R_LARCH_64_PCREL, 109) +RELOC_NUMBER (R_LARCH_CALL36, 110) + END_RELOC_NUMBERS (R_LARCH_count) /* Processor specific flags for the ELF header e_flags field. */ diff --git a/ld/testsuite/ld-loongarch-elf/ld-loongarch-elf.exp b/ld/testsuite/ld-loongarch-elf/ld-loongarch-elf.exp index b95cc53e597..1fc70d0a61e 100644 --- a/ld/testsuite/ld-loongarch-elf/ld-loongarch-elf.exp +++ b/ld/testsuite/ld-loongarch-elf/ld-loongarch-elf.exp @@ -55,4 +55,16 @@ if [istarget "loongarch64-*-*"] { "64_pcrel" \ ] \ ] + + run_ld_link_tests \ + [list \ + [list \ + "medium code model call" \ + "-e 0x0" "" \ + "" \ + {medium-call.s} \ + {} \ + "medium-call" \ + ] \ + ] } diff --git a/ld/testsuite/ld-loongarch-elf/medium-call.s b/ld/testsuite/ld-loongarch-elf/medium-call.s new file mode 100644 index 00000000000..4d1888b76a0 --- /dev/null +++ b/ld/testsuite/ld-loongarch-elf/medium-call.s @@ -0,0 +1,7 @@ +.L1: + # call .L1, r1(ra) temp register, r1(ra) return register. + pcaddu18i $r1, %call36(.L1) + jirl $r1, $r1, 0 + # tail .L1, r12(t0) temp register, r0(zero) return register. + pcaddu18i $r12, %call36(.L1) + jirl $r0, $r12, 0 -- 2.36.0