From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mgamail.intel.com (mgamail.intel.com [134.134.136.126]) by sourceware.org (Postfix) with ESMTPS id B63E13861800 for ; Tue, 19 Dec 2023 12:13:16 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org B63E13861800 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=intel.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org B63E13861800 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=134.134.136.126 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1702988000; cv=none; b=ezK3u1ue2p45rYsid9/6QnGIF3+q8oQFQ0MuDMK+Xup6WcuUZGizUCQxGPEWeLgy6jO/rwZqL3v1pJN/NeDsGrMab1ETM3aEyzw1Z9GzUpICUAkD987hmCvlehKN/zndrsf6HaOprRFPP7LJXxoKGFmwG6VguSZxLRgjtcN5ZBI= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1702988000; c=relaxed/simple; bh=Y0IYr6VwPl4baaPA2Ol3E4LEmIczjIktCycJa5/Wc7E=; h=DKIM-Signature:From:To:Subject:Date:Message-Id:MIME-Version; b=fTrzzEvWwSyz2A0ip2yPzSv5By/F/NdCHVSIT0QVlreuSBhO1F1kdml6FOUMN7+UvjFEDhAYO8RWTqiBRPIYaeGMzjx5J0dLrf3j5oMeo55z0bM/Gn9ov/27vhr8Pm6FaqXwAjWua6GqYaLUiW/oFdjquwzriQwcT/4Bjpxs5Ew= ARC-Authentication-Results: i=1; server2.sourceware.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1702987997; x=1734523997; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=Y0IYr6VwPl4baaPA2Ol3E4LEmIczjIktCycJa5/Wc7E=; b=lWqNLb+ncQ3E/MxJMuZJ7EHyKAffmAQnpoAikC/fRxDnuW2GtIPTM2A2 1fwAyAPO76VxTWKbNRTKG1/FXExNgw2MZdkMPzFpDI623k+1ih+tekdeS Vtwl0ToY7OMlPdYFSlCq2ZR/tvUmiGU0bNRGMHBFm+Mz/RhSGnfuyn3/G LHIwbFQJiHmXDZnIWorI2GeHG9ojcumjg+liOFh18FgFIOlkeZ/dAu02/ hV9p4N/fjpwEK1vmf8490qFrwe9odDEIG4WGbzg3RpgIEeh/o8LvbB1e9 gbk9hWkgpIvYqIXJ9hHWAdceGRlgno0Qkr38ZxXqGD7rhrMNpnFeAIHLE w==; X-IronPort-AV: E=McAfee;i="6600,9927,10928"; a="380633967" X-IronPort-AV: E=Sophos;i="6.04,288,1695711600"; d="scan'208";a="380633967" Received: from orsmga003.jf.intel.com ([10.7.209.27]) by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 19 Dec 2023 04:12:34 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10928"; a="725712594" X-IronPort-AV: E=Sophos;i="6.04,288,1695711600"; d="scan'208";a="725712594" Received: from scymds04.sc.intel.com ([10.82.73.238]) by orsmga003.jf.intel.com with ESMTP; 19 Dec 2023 04:12:33 -0800 Received: from shgcc101.sh.intel.com (shgcc101.sh.intel.com [10.239.85.97]) by scymds04.sc.intel.com (Postfix) with ESMTP id 44AA72002D88; Tue, 19 Dec 2023 04:12:32 -0800 (PST) From: "Cui, Lili" To: binutils@sourceware.org Cc: hongjiu.lu@intel.com, jbeulich@suse.com, "Mo, Zewei" Subject: [PATCH v4 6/9] Support APX Push2/Pop2 Date: Tue, 19 Dec 2023 12:12:15 +0000 Message-Id: <20231219121218.974012-7-lili.cui@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20231219121218.974012-1-lili.cui@intel.com> References: <20231219121218.974012-1-lili.cui@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-10.0 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,GIT_PATCH_0,KAM_NUMSUBJECT,SPF_HELO_NONE,SPF_NONE,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: From: "Mo, Zewei" PPX functionality for PUSH/POP is not implemented in this patch and will be implemented separately. gas/ChangeLog: 2023-12-19 Zewei Mo H.J. Lu Lili Cui * config/tc-i386.c: (enum i386_error): New unsupported_rsp_register and invalid_src_register_set. (md_assemble): Add handler for unsupported_rsp_register and invalid_src_register_set. (check_APX_operands): Add invalid check for push2/pop2. (match_template): Handle check_APX_operands. * testsuite/gas/i386/i386.exp: Add apx-push2pop2 tests. * testsuite/gas/i386/x86-64.exp: Ditto. * testsuite/gas/i386/x86-64-apx-push2pop2.d: New test. * testsuite/gas/i386/x86-64-apx-push2pop2.s: Ditto. * testsuite/gas/i386/x86-64-apx-push2pop2-intel.d: Ditto. * testsuite/gas/i386/x86-64-apx-push2pop2-inval.l: Ditto. * testsuite/gas/i386/x86-64-apx-push2pop2-inval.s: Ditto. * testsuite/gas/i386/apx-push2pop2-inval.s: Ditto. * testsuite/gas/i386/apx-push2pop2-inval.d: Ditto. * testsuite/gas/i386/x86-64-apx-evex-promoted-bad.d: Added bad testcases for POP2. * testsuite/gas/i386/x86-64-apx-evex-promoted-bad.s: Ditto. opcodes/ChangeLog: * i386-dis-evex-reg.h: Add REG_EVEX_MAP4_8F. * i386-dis-evex-w.h: Add EVEX_W_MAP4_8F_R_0 and EVEX_W_MAP4_FF_R_6 * i386-dis-evex.h: Add REG_EVEX_MAP4_8F. * i386-dis.c (PUSH2_POP2_Fixup): Add special handling for PUSH2/POP2. (get_valid_dis386): Add handler for vector length and address_mode for APX-Push2/Pop2 insn. (nd): define nd as b for EVEX-promoted instrutions. (OP_VEX): Add handler of 64-bit vvvv register for APX-Push2/Pop2 insn. * i386-gen.c: Add Push2Pop2 bitfield. * i386-opc.h: Regenerated. * i386-opc.tbl: Regenerated. --- gas/config/tc-i386.c | 44 +++++++++++++++++++ gas/testsuite/gas/i386/apx-push2pop2-inval.l | 5 +++ gas/testsuite/gas/i386/apx-push2pop2-inval.s | 9 ++++ gas/testsuite/gas/i386/i386.exp | 1 + .../gas/i386/x86-64-apx-evex-promoted-bad.d | 5 +++ .../gas/i386/x86-64-apx-evex-promoted-bad.s | 7 +++ .../gas/i386/x86-64-apx-push2pop2-intel.d | 42 ++++++++++++++++++ .../gas/i386/x86-64-apx-push2pop2-inval.l | 13 ++++++ .../gas/i386/x86-64-apx-push2pop2-inval.s | 17 +++++++ gas/testsuite/gas/i386/x86-64-apx-push2pop2.d | 42 ++++++++++++++++++ gas/testsuite/gas/i386/x86-64-apx-push2pop2.s | 39 ++++++++++++++++ gas/testsuite/gas/i386/x86-64.exp | 3 ++ opcodes/i386-dis-evex-reg.h | 9 ++++ opcodes/i386-dis-evex-w.h | 10 +++++ opcodes/i386-dis-evex.h | 2 +- opcodes/i386-dis.c | 31 +++++++++++++ opcodes/i386-opc.tbl | 9 ++++ 17 files changed, 287 insertions(+), 1 deletion(-) create mode 100644 gas/testsuite/gas/i386/apx-push2pop2-inval.l create mode 100644 gas/testsuite/gas/i386/apx-push2pop2-inval.s create mode 100644 gas/testsuite/gas/i386/x86-64-apx-push2pop2-intel.d create mode 100644 gas/testsuite/gas/i386/x86-64-apx-push2pop2-inval.l create mode 100644 gas/testsuite/gas/i386/x86-64-apx-push2pop2-inval.s create mode 100644 gas/testsuite/gas/i386/x86-64-apx-push2pop2.d create mode 100644 gas/testsuite/gas/i386/x86-64-apx-push2pop2.s diff --git a/gas/config/tc-i386.c b/gas/config/tc-i386.c index 4a3dd5e96ca..4771373f4f8 100644 --- a/gas/config/tc-i386.c +++ b/gas/config/tc-i386.c @@ -251,6 +251,7 @@ enum i386_error invalid_vector_register_set, invalid_tmm_register_set, invalid_dest_and_src_register_set, + invalid_dest_register_set, invalid_pseudo_prefix, unsupported_vector_index_register, unsupported_broadcast, @@ -260,6 +261,7 @@ enum i386_error no_default_mask, unsupported_rc_sae, unsupported_vector_size, + unsupported_rsp_register, internal_error, }; @@ -5423,6 +5425,9 @@ md_assemble (char *line) case invalid_dest_and_src_register_set: err_msg = _("destination and source registers must be distinct"); break; + case invalid_dest_register_set: + err_msg = _("two dest registers must be distinct"); + break; case invalid_pseudo_prefix: err_msg = _("rex2 pseudo prefix cannot be used here"); break; @@ -5451,6 +5456,9 @@ md_assemble (char *line) as_bad (_("vector size above %u required for `%s'"), 128u << vector_size, pass1_mnem ? pass1_mnem : insn_name (current_templates.start)); return; + case unsupported_rsp_register: + err_msg = _("'rsp' register cannot be used"); + break; case internal_error: err_msg = _("internal error"); break; @@ -7170,6 +7178,35 @@ check_EgprOperands (const insn_template *t) return 0; } +/* Check if APX operands are valid for the instruction. */ +static bool +check_APX_operands (const insn_template *t) +{ + /* Push2* and Pop2* cannot use RSP and Pop2* cannot pop two same registers. + */ + switch (t->mnem_off) + { + case MN_pop2: + case MN_pop2p: + if (register_number (i.op[0].regs) == register_number (i.op[1].regs)) + { + i.error = invalid_dest_register_set; + return 1; + } + /* fall through */ + case MN_push2: + case MN_push2p: + if (register_number (i.op[0].regs) == 4 + || register_number (i.op[1].regs) == 4) + { + i.error = unsupported_rsp_register; + return 1; + } + break; + } + return 0; +} + /* Helper function for the progress() macro in match_template(). */ static INLINE enum i386_error progress (enum i386_error new, enum i386_error last, @@ -7671,6 +7708,13 @@ match_template (char mnem_suffix) continue; } + /* Check if APX operands are valid. */ + if (check_APX_operands (t)) + { + specific_error = progress (i.error); + continue; + } + /* Check whether to use the shorter VEX encoding for certain insns where the EVEX encoding comes first in the table. This requires the respective AVX-* feature to be explicitly enabled. diff --git a/gas/testsuite/gas/i386/apx-push2pop2-inval.l b/gas/testsuite/gas/i386/apx-push2pop2-inval.l new file mode 100644 index 00000000000..a55a71520c8 --- /dev/null +++ b/gas/testsuite/gas/i386/apx-push2pop2-inval.l @@ -0,0 +1,5 @@ +.* Assembler messages: +.*:6: Error: `push2' is only supported in 64-bit mode +.*:7: Error: `push2p' is only supported in 64-bit mode +.*:8: Error: `pop2' is only supported in 64-bit mode +.*:9: Error: `pop2p' is only supported in 64-bit mode diff --git a/gas/testsuite/gas/i386/apx-push2pop2-inval.s b/gas/testsuite/gas/i386/apx-push2pop2-inval.s new file mode 100644 index 00000000000..77166327ed1 --- /dev/null +++ b/gas/testsuite/gas/i386/apx-push2pop2-inval.s @@ -0,0 +1,9 @@ +# Check 32bit APX-PUSH2/POP2 instructions + + .allow_index_reg + .text +_start: + push2 %rax, %rbx + push2p %rax, %rbx + pop2 %rax, %rbx + pop2p %rax, %rbx diff --git a/gas/testsuite/gas/i386/i386.exp b/gas/testsuite/gas/i386/i386.exp index 3917be6be70..f9ee85b4bb3 100644 --- a/gas/testsuite/gas/i386/i386.exp +++ b/gas/testsuite/gas/i386/i386.exp @@ -511,6 +511,7 @@ if [gas_32_check] then { run_dump_test "sm4-intel" run_list_test "pbndkb-inval" run_list_test "user_msr-inval" + run_list_test "apx-push2pop2-inval" run_list_test "sg" run_dump_test "clzero" run_dump_test "invlpgb" diff --git a/gas/testsuite/gas/i386/x86-64-apx-evex-promoted-bad.d b/gas/testsuite/gas/i386/x86-64-apx-evex-promoted-bad.d index e0b14e30178..1e5ad254b5e 100644 --- a/gas/testsuite/gas/i386/x86-64-apx-evex-promoted-bad.d +++ b/gas/testsuite/gas/i386/x86-64-apx-evex-promoted-bad.d @@ -34,3 +34,8 @@ Disassembly of section .text: [ ]*[a-f0-9]+:[ ]+62 f4 e4[ ]+\(bad\) [ ]*[a-f0-9]+:[ ]+08 ff[ ]+.* [ ]*[a-f0-9]+:[ ]+04 08[ ]+.* +[ ]*[a-f0-9]+:[ ]+62 f4 3c[ ]+\(bad\) +[ ]*[a-f0-9]+:[ ]+08 8f c0 ff ff ff[ ]+or.* +[ ]*[a-f0-9]+:[ ]+62 74 7c 18 8f c0[ ]+pop2 %rax,\(bad\) +[ ]*[a-f0-9]+:[ ]+62 d4 3c 18 8f[ ]+\(bad\) +[ ]*[a-f0-9]+:[ ]+c0[ ]+.* diff --git a/gas/testsuite/gas/i386/x86-64-apx-evex-promoted-bad.s b/gas/testsuite/gas/i386/x86-64-apx-evex-promoted-bad.s index 9a08a45eb76..5f85648d39c 100644 --- a/gas/testsuite/gas/i386/x86-64-apx-evex-promoted-bad.s +++ b/gas/testsuite/gas/i386/x86-64-apx-evex-promoted-bad.s @@ -34,3 +34,10 @@ _start: .insn EVEX.L0.NP.0f38.W0 0xf5, %rax ,(%rax,%rbx){1to8}, %rcx #{evex} inc %rax %rbx EVEX.vvvv != 1111 && EVEX.ND = 0. .insn EVEX.L0.NP.M4.W1 0xff/0, (%rax,%rcx), %rbx + # pop2 %rax, %r8 set EVEX.ND=0. + .insn EVEX.L0.M4.W0 0x8f/0, %rax, %r8 + .byte 0xff, 0xff, 0xff + # pop2 %rax, %r8 set EVEX.vvvv = 1111. + .insn EVEX.L0.M4.W0 0x8f, %rax, {rn-sae},%r8 + # pop2 %r8, %r8. + .insn EVEX.L0.M4.W0 0x8f/0, %r8,{rn-sae}, %r8 diff --git a/gas/testsuite/gas/i386/x86-64-apx-push2pop2-intel.d b/gas/testsuite/gas/i386/x86-64-apx-push2pop2-intel.d new file mode 100644 index 00000000000..46b21219582 --- /dev/null +++ b/gas/testsuite/gas/i386/x86-64-apx-push2pop2-intel.d @@ -0,0 +1,42 @@ +#as: --64 +#objdump: -dw -Mintel +#name: i386 APX-push2pop2 insns (Intel disassembly) +#source: x86-64-apx-push2pop2.s + +.*: +file format .* + +Disassembly of section \.text: + +0+ <_start>: +\s*[a-f0-9]+:\s*62 f4 7c 18 ff f3\s+push2\s+rax,rbx +\s*[a-f0-9]+:\s*62 fc 3c 18 ff f1\s+push2\s+r8,r17 +\s*[a-f0-9]+:\s*62 d4 04 10 ff f1\s+push2\s+r31,r9 +\s*[a-f0-9]+:\s*62 dc 3c 10 ff f7\s+push2\s+r24,r31 +\s*[a-f0-9]+:\s*62 f4 fc 18 ff f3\s+push2p\s+rax,rbx +\s*[a-f0-9]+:\s*62 fc bc 18 ff f1\s+push2p\s+r8,r17 +\s*[a-f0-9]+:\s*62 d4 84 10 ff f1\s+push2p\s+r31,r9 +\s*[a-f0-9]+:\s*62 dc bc 10 ff f7\s+push2p\s+r24,r31 +\s*[a-f0-9]+:\s*62 f4 64 18 8f c0\s+pop2\s+rbx,rax +\s*[a-f0-9]+:\s*62 d4 74 10 8f c0\s+pop2\s+r17,r8 +\s*[a-f0-9]+:\s*62 dc 34 18 8f c7\s+pop2\s+r9,r31 +\s*[a-f0-9]+:\s*62 dc 04 10 8f c0\s+pop2\s+r31,r24 +\s*[a-f0-9]+:\s*62 f4 e4 18 8f c0\s+pop2p\s+rbx,rax +\s*[a-f0-9]+:\s*62 d4 f4 10 8f c0\s+pop2p\s+r17,r8 +\s*[a-f0-9]+:\s*62 dc b4 18 8f c7\s+pop2p\s+r9,r31 +\s*[a-f0-9]+:\s*62 dc 84 10 8f c0\s+pop2p\s+r31,r24 +\s*[a-f0-9]+:\s*62 f4 7c 18 ff f3\s+push2\s+rax,rbx +\s*[a-f0-9]+:\s*62 fc 3c 18 ff f1\s+push2\s+r8,r17 +\s*[a-f0-9]+:\s*62 d4 04 10 ff f1\s+push2\s+r31,r9 +\s*[a-f0-9]+:\s*62 dc 3c 10 ff f7\s+push2\s+r24,r31 +\s*[a-f0-9]+:\s*62 f4 fc 18 ff f3\s+push2p\s+rax,rbx +\s*[a-f0-9]+:\s*62 fc bc 18 ff f1\s+push2p\s+r8,r17 +\s*[a-f0-9]+:\s*62 d4 84 10 ff f1\s+push2p\s+r31,r9 +\s*[a-f0-9]+:\s*62 dc bc 10 ff f7\s+push2p\s+r24,r31 +\s*[a-f0-9]+:\s*62 f4 64 18 8f c0\s+pop2\s+rbx,rax +\s*[a-f0-9]+:\s*62 d4 74 10 8f c0\s+pop2\s+r17,r8 +\s*[a-f0-9]+:\s*62 dc 34 18 8f c7\s+pop2\s+r9,r31 +\s*[a-f0-9]+:\s*62 dc 04 10 8f c0\s+pop2\s+r31,r24 +\s*[a-f0-9]+:\s*62 f4 e4 18 8f c0\s+pop2p\s+rbx,rax +\s*[a-f0-9]+:\s*62 d4 f4 10 8f c0\s+pop2p\s+r17,r8 +\s*[a-f0-9]+:\s*62 dc b4 18 8f c7\s+pop2p\s+r9,r31 +\s*[a-f0-9]+:\s*62 dc 84 10 8f c0\s+pop2p\s+r31,r24 diff --git a/gas/testsuite/gas/i386/x86-64-apx-push2pop2-inval.l b/gas/testsuite/gas/i386/x86-64-apx-push2pop2-inval.l new file mode 100644 index 00000000000..2cd142885a1 --- /dev/null +++ b/gas/testsuite/gas/i386/x86-64-apx-push2pop2-inval.l @@ -0,0 +1,13 @@ +.* Assembler messages: +.*:6: Error: operand size mismatch for `push2' +.*:7: Error: operand size mismatch for `push2' +.*:8: Error: 'rsp' register cannot be used for `push2' +.*:9: Error: 'rsp' register cannot be used for `push2' +.*:10: Error: operand size mismatch for `push2p' +.*:11: Error: 'rsp' register cannot be used for `push2p' +.*:12: Error: operand size mismatch for `pop2' +.*:13: Error: 'rsp' register cannot be used for `pop2' +.*:14: Error: 'rsp' register cannot be used for `pop2' +.*:15: Error: two dest registers must be distinct for `pop2' +.*:16: Error: 'rsp' register cannot be used for `pop2p' +.*:17: Error: two dest registers must be distinct for `pop2p' diff --git a/gas/testsuite/gas/i386/x86-64-apx-push2pop2-inval.s b/gas/testsuite/gas/i386/x86-64-apx-push2pop2-inval.s new file mode 100644 index 00000000000..83cef97d57e --- /dev/null +++ b/gas/testsuite/gas/i386/x86-64-apx-push2pop2-inval.s @@ -0,0 +1,17 @@ +# Check illegal APX-Push2Pop2 instructions + + .allow_index_reg + .text +_start: + push2 %ax, %bx + push2 %eax, %ebx + push2 %rsp, %r17 + push2 %r17, %rsp + push2p %eax, %ebx + push2p %rsp, %r17 + pop2 %ax, %bx + pop2 %rax, %rsp + pop2 %rsp, %rax + pop2 %r12, %r12 + pop2p %rax, %rsp + pop2p %r12, %r12 diff --git a/gas/testsuite/gas/i386/x86-64-apx-push2pop2.d b/gas/testsuite/gas/i386/x86-64-apx-push2pop2.d new file mode 100644 index 00000000000..54f22a7f94e --- /dev/null +++ b/gas/testsuite/gas/i386/x86-64-apx-push2pop2.d @@ -0,0 +1,42 @@ +#as: --64 +#objdump: -dw +#name: x86_64 APX-push2pop2 insns +#source: x86-64-apx-push2pop2.s + +.*: +file format .* + +Disassembly of section \.text: + +0+ <_start>: +\s*[a-f0-9]+:\s*62 f4 7c 18 ff f3\s+push2\s+%rbx,%rax +\s*[a-f0-9]+:\s*62 fc 3c 18 ff f1\s+push2\s+%r17,%r8 +\s*[a-f0-9]+:\s*62 d4 04 10 ff f1\s+push2\s+%r9,%r31 +\s*[a-f0-9]+:\s*62 dc 3c 10 ff f7\s+push2\s+%r31,%r24 +\s*[a-f0-9]+:\s*62 f4 fc 18 ff f3\s+push2p\s+%rbx,%rax +\s*[a-f0-9]+:\s*62 fc bc 18 ff f1\s+push2p\s+%r17,%r8 +\s*[a-f0-9]+:\s*62 d4 84 10 ff f1\s+push2p\s+%r9,%r31 +\s*[a-f0-9]+:\s*62 dc bc 10 ff f7\s+push2p\s+%r31,%r24 +\s*[a-f0-9]+:\s*62 f4 64 18 8f c0\s+pop2\s+%rax,%rbx +\s*[a-f0-9]+:\s*62 d4 74 10 8f c0\s+pop2\s+%r8,%r17 +\s*[a-f0-9]+:\s*62 dc 34 18 8f c7\s+pop2\s+%r31,%r9 +\s*[a-f0-9]+:\s*62 dc 04 10 8f c0\s+pop2\s+%r24,%r31 +\s*[a-f0-9]+:\s*62 f4 e4 18 8f c0\s+pop2p\s+%rax,%rbx +\s*[a-f0-9]+:\s*62 d4 f4 10 8f c0\s+pop2p\s+%r8,%r17 +\s*[a-f0-9]+:\s*62 dc b4 18 8f c7\s+pop2p\s+%r31,%r9 +\s*[a-f0-9]+:\s*62 dc 84 10 8f c0\s+pop2p\s+%r24,%r31 +\s*[a-f0-9]+:\s*62 f4 7c 18 ff f3\s+push2\s+%rbx,%rax +\s*[a-f0-9]+:\s*62 fc 3c 18 ff f1\s+push2\s+%r17,%r8 +\s*[a-f0-9]+:\s*62 d4 04 10 ff f1\s+push2\s+%r9,%r31 +\s*[a-f0-9]+:\s*62 dc 3c 10 ff f7\s+push2\s+%r31,%r24 +\s*[a-f0-9]+:\s*62 f4 fc 18 ff f3\s+push2p\s+%rbx,%rax +\s*[a-f0-9]+:\s*62 fc bc 18 ff f1\s+push2p\s+%r17,%r8 +\s*[a-f0-9]+:\s*62 d4 84 10 ff f1\s+push2p\s+%r9,%r31 +\s*[a-f0-9]+:\s*62 dc bc 10 ff f7\s+push2p\s+%r31,%r24 +\s*[a-f0-9]+:\s*62 f4 64 18 8f c0\s+pop2\s+%rax,%rbx +\s*[a-f0-9]+:\s*62 d4 74 10 8f c0\s+pop2\s+%r8,%r17 +\s*[a-f0-9]+:\s*62 dc 34 18 8f c7\s+pop2\s+%r31,%r9 +\s*[a-f0-9]+:\s*62 dc 04 10 8f c0\s+pop2\s+%r24,%r31 +\s*[a-f0-9]+:\s*62 f4 e4 18 8f c0\s+pop2p\s+%rax,%rbx +\s*[a-f0-9]+:\s*62 d4 f4 10 8f c0\s+pop2p\s+%r8,%r17 +\s*[a-f0-9]+:\s*62 dc b4 18 8f c7\s+pop2p\s+%r31,%r9 +\s*[a-f0-9]+:\s*62 dc 84 10 8f c0\s+pop2p\s+%r24,%r31 diff --git a/gas/testsuite/gas/i386/x86-64-apx-push2pop2.s b/gas/testsuite/gas/i386/x86-64-apx-push2pop2.s new file mode 100644 index 00000000000..5c28c13ba2e --- /dev/null +++ b/gas/testsuite/gas/i386/x86-64-apx-push2pop2.s @@ -0,0 +1,39 @@ +# Check 64bit APX-Push2Pop2 instructions + + .allow_index_reg + .text +_start: + push2 %rbx, %rax + push2 %r17, %r8 + push2 %r9, %r31 + push2 %r31, %r24 + push2p %rbx, %rax + push2p %r17, %r8 + push2p %r9, %r31 + push2p %r31, %r24 + pop2 %rax, %rbx + pop2 %r8, %r17 + pop2 %r31, %r9 + pop2 %r24, %r31 + pop2p %rax, %rbx + pop2p %r8, %r17 + pop2p %r31, %r9 + pop2p %r24, %r31 + + .intel_syntax noprefix + push2 rax, rbx + push2 r8, r17 + push2 r31, r9 + push2 r24, r31 + push2p rax, rbx + push2p r8, r17 + push2p r31, r9 + push2p r24, r31 + pop2 rbx, rax + pop2 r17, r8 + pop2 r9, r31 + pop2 r31, r24 + pop2p rbx, rax + pop2p r17, r8 + pop2p r9, r31 + pop2p r31, r24 diff --git a/gas/testsuite/gas/i386/x86-64.exp b/gas/testsuite/gas/i386/x86-64.exp index 5e2e302b22a..2296ad4af7d 100644 --- a/gas/testsuite/gas/i386/x86-64.exp +++ b/gas/testsuite/gas/i386/x86-64.exp @@ -345,6 +345,9 @@ run_dump_test "x86-64-avx512dq-rcigrd-intel" run_dump_test "x86-64-avx512dq-rcigrd" run_dump_test "x86-64-avx512dq-rcigrne-intel" run_dump_test "x86-64-avx512dq-rcigrne" +run_dump_test "x86-64-apx-push2pop2" +run_dump_test "x86-64-apx-push2pop2-intel" +run_list_test "x86-64-apx-push2pop2-inval" run_dump_test "x86-64-avx512dq-rcigru-intel" run_dump_test "x86-64-avx512dq-rcigru" run_dump_test "x86-64-avx512dq-rcigrz-intel" diff --git a/opcodes/i386-dis-evex-reg.h b/opcodes/i386-dis-evex-reg.h index 4dc736253b1..eeae0603721 100644 --- a/opcodes/i386-dis-evex-reg.h +++ b/opcodes/i386-dis-evex-reg.h @@ -86,6 +86,10 @@ { "subQ", { VexGv, Ev, sIb }, PREFIX_NP_OR_DATA }, { "xorQ", { VexGv, Ev, sIb }, PREFIX_NP_OR_DATA }, }, + /* REG_EVEX_MAP4_8F */ + { + { VEX_W_TABLE (EVEX_W_MAP4_8F_R_0) }, + }, /* REG_EVEX_MAP4_F6 */ { { Bad_Opcode }, @@ -109,4 +113,9 @@ { { "incQ", { VexGv, Ev }, PREFIX_NP_OR_DATA }, { "decQ", { VexGv, Ev }, PREFIX_NP_OR_DATA }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { VEX_W_TABLE (EVEX_W_MAP4_FF_R_6) }, }, diff --git a/opcodes/i386-dis-evex-w.h b/opcodes/i386-dis-evex-w.h index b828277d413..12ab29544bb 100644 --- a/opcodes/i386-dis-evex-w.h +++ b/opcodes/i386-dis-evex-w.h @@ -442,6 +442,16 @@ { Bad_Opcode }, { "vpshrdw", { XM, Vex, EXx, Ib }, 0 }, }, + /* EVEX_W_MAP4_8F_R_0 */ + { + { "pop2", { { PUSH2_POP2_Fixup, q_mode}, Eq }, NO_PREFIX }, + { "pop2p", { { PUSH2_POP2_Fixup, q_mode}, Eq }, NO_PREFIX }, + }, + /* EVEX_W_MAP4_FF_R_6 */ + { + { "push2", { { PUSH2_POP2_Fixup, q_mode}, Eq }, 0 }, + { "push2p", { { PUSH2_POP2_Fixup, q_mode}, Eq }, 0 }, + }, /* EVEX_W_MAP5_5B_P_0 */ { { "vcvtdq2ph%XY", { XMxmmq, EXx, EXxEVexR }, 0 }, diff --git a/opcodes/i386-dis-evex.h b/opcodes/i386-dis-evex.h index a8a891d7f0e..4f2ec966457 100644 --- a/opcodes/i386-dis-evex.h +++ b/opcodes/i386-dis-evex.h @@ -1035,7 +1035,7 @@ static const struct dis386 evex_table[][256] = { { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, - { Bad_Opcode }, + { REG_TABLE (REG_EVEX_MAP4_8F) }, /* 90 */ { Bad_Opcode }, { Bad_Opcode }, diff --git a/opcodes/i386-dis.c b/opcodes/i386-dis.c index 50274e39ba6..cf02e34bcc8 100644 --- a/opcodes/i386-dis.c +++ b/opcodes/i386-dis.c @@ -105,6 +105,7 @@ static bool FXSAVE_Fixup (instr_info *, int, int); static bool MOVSXD_Fixup (instr_info *, int, int); static bool DistinctDest_Fixup (instr_info *, int, int); static bool PREFETCHI_Fixup (instr_info *, int, int); +static bool PUSH2_POP2_Fixup (instr_info *, int, int); static void ATTRIBUTE_PRINTF_3 i386_dis_printf (const disassemble_info *, enum disassembler_style, @@ -903,6 +904,7 @@ enum REG_EVEX_MAP4_80, REG_EVEX_MAP4_81, REG_EVEX_MAP4_83, + REG_EVEX_MAP4_8F, REG_EVEX_MAP4_F6, REG_EVEX_MAP4_F7, REG_EVEX_MAP4_FE, @@ -1746,6 +1748,9 @@ enum EVEX_W_0F3A70, EVEX_W_0F3A72, + EVEX_W_MAP4_8F_R_0, + EVEX_W_MAP4_FF_R_6, + EVEX_W_MAP5_5B_P_0, EVEX_W_MAP5_7A_P_3, }; @@ -13517,6 +13522,9 @@ OP_VEX (instr_info *ins, int bytemode, int sizeflag ATTRIBUTE_UNUSED) case b_mode: names = att_names8rex; break; + case q_mode: + names = att_names64; + break; case mask_bd_mode: case mask_mode: if (reg > 0x7) @@ -13901,3 +13909,26 @@ PREFETCHI_Fixup (instr_info *ins, int bytemode, int sizeflag) return OP_M (ins, bytemode, sizeflag); } + +static bool +PUSH2_POP2_Fixup (instr_info *ins, int bytemode, int sizeflag) +{ + if (ins->modrm.mod != 3) + return true; + + unsigned int vvvv_reg = ins->vex.register_specifier + | (!ins->vex.v << 4); + unsigned int rm_reg = ins->modrm.rm + (ins->rex & REX_B ? 8 : 0) + + (ins->rex2 & REX_B ? 16 : 0); + + /* Push2/Pop2 cannot use RSP and Pop2 cannot pop two same registers. */ + if (!ins->vex.nd || vvvv_reg == 0x4 || rm_reg == 0x4 + || (!ins->modrm.reg + && vvvv_reg == rm_reg)) + { + oappend (ins, "(bad)"); + return true; + } + + return OP_VEX (ins, bytemode, sizeflag); +} diff --git a/opcodes/i386-opc.tbl b/opcodes/i386-opc.tbl index 8f4ce62c789..4bb268c4bfb 100644 --- a/opcodes/i386-opc.tbl +++ b/opcodes/i386-opc.tbl @@ -3482,3 +3482,12 @@ uwrmsr, 0xf30f38f8, USER_MSR, Modrm|NoSuf|NoRex64, { Reg64, Reg64 } uwrmsr, 0xf3f8/0, USER_MSR, Modrm|Vex128|VexMap7|VexW0|NoSuf, { Imm32, Reg64 } // USER_MSR instructions end. + +// APX Push2/Pop2 instructions. + +push2, 0xff/6, APX_F, Modrm|VexW0|EVex128|EVexMap4|VexVVVV|No_bSuf|No_wSuf|No_lSuf|No_sSuf, { Reg64, Reg64 } +push2p, 0xff/6, APX_F, Modrm|VexW1|EVex128|EVexMap4|VexVVVV|No_bSuf|No_wSuf|No_lSuf|No_sSuf, { Reg64, Reg64 } +pop2, 0x8f/0, APX_F, Modrm|VexW0|EVex128|EVexMap4|VexVVVV|No_bSuf|No_wSuf|No_lSuf|No_sSuf, { Reg64, Reg64 } +pop2p, 0x8f/0, APX_F, Modrm|VexW1|EVex128|EVexMap4|VexVVVV|No_bSuf|No_wSuf|No_lSuf|No_sSuf, { Reg64, Reg64 } + +// APX Push2/Pop2 instructions end. -- 2.25.1