From: Victor Do Nascimento <victor.donascimento@arm.com>
To: <binutils@sourceware.org>
Cc: <richard.earnshaw@arm.com>, <nickc@redhat.com>,
Victor Do Nascimento <victor.donascimento@arm.com>
Subject: [PATCH 10/12] aarch64: Add TLBIP tests
Date: Wed, 3 Jan 2024 01:17:24 +0000 [thread overview]
Message-ID: <20240103011739.2444792-11-victor.donascimento@arm.com> (raw)
In-Reply-To: <20240103011739.2444792-1-victor.donascimento@arm.com>
---
gas/testsuite/gas/aarch64/tlbip.d | 127 ++++++++++++++++++++++++++++
gas/testsuite/gas/aarch64/tlbip.s | 132 ++++++++++++++++++++++++++++++
2 files changed, 259 insertions(+)
create mode 100644 gas/testsuite/gas/aarch64/tlbip.d
create mode 100644 gas/testsuite/gas/aarch64/tlbip.s
diff --git a/gas/testsuite/gas/aarch64/tlbip.d b/gas/testsuite/gas/aarch64/tlbip.d
new file mode 100644
index 00000000000..81c22cf8e20
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/tlbip.d
@@ -0,0 +1,127 @@
+#objdump: -dr
+
+.*: file format .*
+
+Disassembly of section \.text:
+
+0+ <.*>:
+ 0: d5488120 sysp #0, C8, C1, #1, x0, x1
+ 4: d5488160 sysp #0, C8, C1, #3, x0, x1
+ 8: d54881a0 sysp #0, C8, C1, #5, x0, x1
+ c: d54881e0 sysp #0, C8, C1, #7, x0, x1
+ 10: d5488220 sysp #0, C8, C2, #1, x0, x1
+ 14: d5488260 sysp #0, C8, C2, #3, x0, x1
+ 18: d54882a0 sysp #0, C8, C2, #5, x0, x1
+ 1c: d54882e0 sysp #0, C8, C2, #7, x0, x1
+ 20: d5488320 sysp #0, C8, C3, #1, x0, x1
+ 24: d5488360 sysp #0, C8, C3, #3, x0, x1
+ 28: d54883a0 sysp #0, C8, C3, #5, x0, x1
+ 2c: d54883e0 sysp #0, C8, C3, #7, x0, x1
+ 30: d5488520 sysp #0, C8, C5, #1, x0, x1
+ 34: d5488560 sysp #0, C8, C5, #3, x0, x1
+ 38: d54885a0 sysp #0, C8, C5, #5, x0, x1
+ 3c: d54885e0 sysp #0, C8, C5, #7, x0, x1
+ 40: d5488620 sysp #0, C8, C6, #1, x0, x1
+ 44: d5488660 sysp #0, C8, C6, #3, x0, x1
+ 48: d54886a0 sysp #0, C8, C6, #5, x0, x1
+ 4c: d54886e0 sysp #0, C8, C6, #7, x0, x1
+ 50: d5488720 sysp #0, C8, C7, #1, x0, x1
+ 54: d5488760 sysp #0, C8, C7, #3, x0, x1
+ 58: d54887a0 sysp #0, C8, C7, #5, x0, x1
+ 5c: d54887e0 sysp #0, C8, C7, #7, x0, x1
+ 60: d5489120 sysp #0, C9, C1, #1, x0, x1
+ 64: d5489160 sysp #0, C9, C1, #3, x0, x1
+ 68: d54891a0 sysp #0, C9, C1, #5, x0, x1
+ 6c: d54891e0 sysp #0, C9, C1, #7, x0, x1
+ 70: d5489220 sysp #0, C9, C2, #1, x0, x1
+ 74: d5489260 sysp #0, C9, C2, #3, x0, x1
+ 78: d54892a0 sysp #0, C9, C2, #5, x0, x1
+ 7c: d54892e0 sysp #0, C9, C2, #7, x0, x1
+ 80: d5489320 sysp #0, C9, C3, #1, x0, x1
+ 84: d5489360 sysp #0, C9, C3, #3, x0, x1
+ 88: d54893a0 sysp #0, C9, C3, #5, x0, x1
+ 8c: d54893e0 sysp #0, C9, C3, #7, x0, x1
+ 90: d5489520 sysp #0, C9, C5, #1, x0, x1
+ 94: d5489560 sysp #0, C9, C5, #3, x0, x1
+ 98: d54895a0 sysp #0, C9, C5, #5, x0, x1
+ 9c: d54895e0 sysp #0, C9, C5, #7, x0, x1
+ a0: d5489620 sysp #0, C9, C6, #1, x0, x1
+ a4: d5489660 sysp #0, C9, C6, #3, x0, x1
+ a8: d54896a0 sysp #0, C9, C6, #5, x0, x1
+ ac: d54896e0 sysp #0, C9, C6, #7, x0, x1
+ b0: d5489720 sysp #0, C9, C7, #1, x0, x1
+ b4: d5489760 sysp #0, C9, C7, #3, x0, x1
+ b8: d54897a0 sysp #0, C9, C7, #5, x0, x1
+ bc: d54897e0 sysp #0, C9, C7, #7, x0, x1
+ c0: d54c8020 sysp #4, C8, C0, #1, x0, x1
+ c4: d54c8040 sysp #4, C8, C0, #2, x0, x1
+ c8: d54c80a0 sysp #4, C8, C0, #5, x0, x1
+ cc: d54c80c0 sysp #4, C8, C0, #6, x0, x1
+ d0: d54c8120 sysp #4, C8, C1, #1, x0, x1
+ d4: d54c81a0 sysp #4, C8, C1, #5, x0, x1
+ d8: d54c8220 sysp #4, C8, C2, #1, x0, x1
+ dc: d54c82a0 sysp #4, C8, C2, #5, x0, x1
+ e0: d54c8320 sysp #4, C8, C3, #1, x0, x1
+ e4: d54c83a0 sysp #4, C8, C3, #5, x0, x1
+ e8: d54c8400 sysp #4, C8, C4, #0, x0, x1
+ ec: d54c8420 sysp #4, C8, C4, #1, x0, x1
+ f0: d54c8440 sysp #4, C8, C4, #2, x0, x1
+ f4: d54c8460 sysp #4, C8, C4, #3, x0, x1
+ f8: d54c8480 sysp #4, C8, C4, #4, x0, x1
+ fc: d54c84a0 sysp #4, C8, C4, #5, x0, x1
+ 100: d54c84c0 sysp #4, C8, C4, #6, x0, x1
+ 104: d54c84e0 sysp #4, C8, C4, #7, x0, x1
+ 108: d54c8520 sysp #4, C8, C5, #1, x0, x1
+ 10c: d54c85a0 sysp #4, C8, C5, #5, x0, x1
+ 110: d54c8620 sysp #4, C8, C6, #1, x0, x1
+ 114: d54c86a0 sysp #4, C8, C6, #5, x0, x1
+ 118: d54c8720 sysp #4, C8, C7, #1, x0, x1
+ 11c: d54c87a0 sysp #4, C8, C7, #5, x0, x1
+ 120: d54c9020 sysp #4, C9, C0, #1, x0, x1
+ 124: d54c9040 sysp #4, C9, C0, #2, x0, x1
+ 128: d54c90a0 sysp #4, C9, C0, #5, x0, x1
+ 12c: d54c90c0 sysp #4, C9, C0, #6, x0, x1
+ 130: d54c9120 sysp #4, C9, C1, #1, x0, x1
+ 134: d54c91a0 sysp #4, C9, C1, #5, x0, x1
+ 138: d54c9220 sysp #4, C9, C2, #1, x0, x1
+ 13c: d54c92a0 sysp #4, C9, C2, #5, x0, x1
+ 140: d54c9320 sysp #4, C9, C3, #1, x0, x1
+ 144: d54c93a0 sysp #4, C9, C3, #5, x0, x1
+ 148: d54c9400 sysp #4, C9, C4, #0, x0, x1
+ 14c: d54c9420 sysp #4, C9, C4, #1, x0, x1
+ 150: d54c9440 sysp #4, C9, C4, #2, x0, x1
+ 154: d54c9460 sysp #4, C9, C4, #3, x0, x1
+ 158: d54c9480 sysp #4, C9, C4, #4, x0, x1
+ 15c: d54c94a0 sysp #4, C9, C4, #5, x0, x1
+ 160: d54c94c0 sysp #4, C9, C4, #6, x0, x1
+ 164: d54c94e0 sysp #4, C9, C4, #7, x0, x1
+ 168: d54c9520 sysp #4, C9, C5, #1, x0, x1
+ 16c: d54c95a0 sysp #4, C9, C5, #5, x0, x1
+ 170: d54c9620 sysp #4, C9, C6, #1, x0, x1
+ 174: d54c96a0 sysp #4, C9, C6, #5, x0, x1
+ 178: d54c9720 sysp #4, C9, C7, #1, x0, x1
+ 17c: d54c97a0 sysp #4, C9, C7, #5, x0, x1
+ 180: d54e8120 sysp #6, C8, C1, #1, x0, x1
+ 184: d54e81a0 sysp #6, C8, C1, #5, x0, x1
+ 188: d54e8220 sysp #6, C8, C2, #1, x0, x1
+ 18c: d54e82a0 sysp #6, C8, C2, #5, x0, x1
+ 190: d54e8320 sysp #6, C8, C3, #1, x0, x1
+ 194: d54e83a0 sysp #6, C8, C3, #5, x0, x1
+ 198: d54e8520 sysp #6, C8, C5, #1, x0, x1
+ 19c: d54e85a0 sysp #6, C8, C5, #5, x0, x1
+ 1a0: d54e8620 sysp #6, C8, C6, #1, x0, x1
+ 1a4: d54e86a0 sysp #6, C8, C6, #5, x0, x1
+ 1a8: d54e8720 sysp #6, C8, C7, #1, x0, x1
+ 1ac: d54e87a0 sysp #6, C8, C7, #5, x0, x1
+ 1b0: d54e9120 sysp #6, C9, C1, #1, x0, x1
+ 1b4: d54e91a0 sysp #6, C9, C1, #5, x0, x1
+ 1b8: d54e9220 sysp #6, C9, C2, #1, x0, x1
+ 1bc: d54e92a0 sysp #6, C9, C2, #5, x0, x1
+ 1c0: d54e9320 sysp #6, C9, C3, #1, x0, x1
+ 1c4: d54e93a0 sysp #6, C9, C3, #5, x0, x1
+ 1c8: d54e9520 sysp #6, C9, C5, #1, x0, x1
+ 1cc: d54e95a0 sysp #6, C9, C5, #5, x0, x1
+ 1d0: d54e9620 sysp #6, C9, C6, #1, x0, x1
+ 1d4: d54e96a0 sysp #6, C9, C6, #5, x0, x1
+ 1d8: d54e9720 sysp #6, C9, C7, #1, x0, x1
+ 1dc: d54e97a0 sysp #6, C9, C7, #5, x0, x1
\ No newline at end of file
diff --git a/gas/testsuite/gas/aarch64/tlbip.s b/gas/testsuite/gas/aarch64/tlbip.s
new file mode 100644
index 00000000000..52148d9fc45
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/tlbip.s
@@ -0,0 +1,132 @@
+ // Test file for AArch64 GAS -- TLB invalidation instructions.
+
+ .macro tlbip_m op expl
+ .ifc \expl, 1
+ tlbip \op, x0, x1
+ .else
+ tlbip \op
+ .endif
+ .endm
+
+ .arch armv9.4-a+d128
+
+ tlbip_m vae1os 1
+ tlbip_m vaae1os 1
+ tlbip_m vale1os 1
+ tlbip_m vaale1os 1
+ tlbip_m rvae1is 1
+ tlbip_m rvaae1is 1
+ tlbip_m rvale1is 1
+ tlbip_m rvaale1is 1
+ tlbip_m vae1is 1
+ tlbip_m vaae1is 1
+ tlbip_m vale1is 1
+ tlbip_m vaale1is 1
+ tlbip_m rvae1os 1
+ tlbip_m rvaae1os 1
+ tlbip_m rvale1os 1
+ tlbip_m rvaale1os 1
+ tlbip_m rvae1 1
+ tlbip_m rvaae1 1
+ tlbip_m rvale1 1
+ tlbip_m rvaale1 1
+ tlbip_m vae1 1
+ tlbip_m vaae1 1
+ tlbip_m vale1 1
+ tlbip_m vaale1 1
+ tlbip_m vae1osnxs 1
+ tlbip_m vaae1osnxs 1
+ tlbip_m vale1osnxs 1
+ tlbip_m vaale1osnxs 1
+ tlbip_m rvae1isnxs 1
+ tlbip_m rvaae1isnxs 1
+ tlbip_m rvale1isnxs 1
+ tlbip_m rvaale1isnxs 1
+ tlbip_m vae1isnxs 1
+ tlbip_m vaae1isnxs 1
+ tlbip_m vale1isnxs 1
+ tlbip_m vaale1isnxs 1
+ tlbip_m rvae1osnxs 1
+ tlbip_m rvaae1osnxs 1
+ tlbip_m rvale1osnxs 1
+ tlbip_m rvaale1osnxs 1
+ tlbip_m rvae1nxs 1
+ tlbip_m rvaae1nxs 1
+ tlbip_m rvale1nxs 1
+ tlbip_m rvaale1nxs 1
+ tlbip_m vae1nxs 1
+ tlbip_m vaae1nxs 1
+ tlbip_m vale1nxs 1
+ tlbip_m vaale1nxs 1
+ tlbip_m ipas2e1is 1
+ tlbip_m ripas2e1is 1
+ tlbip_m ipas2le1is 1
+ tlbip_m ripas2le1is 1
+ tlbip_m vae2os 1
+ tlbip_m vale2os 1
+ tlbip_m rvae2is 1
+ tlbip_m rvale2is 1
+ tlbip_m vae2is 1
+ tlbip_m vale2is 1
+ tlbip_m ipas2e1os 1
+ tlbip_m ipas2e1 1
+ tlbip_m ripas2e1 1
+ tlbip_m ripas2e1os 1
+ tlbip_m ipas2le1os 1
+ tlbip_m ipas2le1 1
+ tlbip_m ripas2le1 1
+ tlbip_m ripas2le1os 1
+ tlbip_m rvae2os 1
+ tlbip_m rvale2os 1
+ tlbip_m rvae2 1
+ tlbip_m rvale2 1
+ tlbip_m vae2 1
+ tlbip_m vale2 1
+ tlbip_m ipas2e1isnxs 1
+ tlbip_m ripas2e1isnxs 1
+ tlbip_m ipas2le1isnxs 1
+ tlbip_m ripas2le1isnxs 1
+ tlbip_m vae2osnxs 1
+ tlbip_m vale2osnxs 1
+ tlbip_m rvae2isnxs 1
+ tlbip_m rvale2isnxs 1
+ tlbip_m vae2isnxs 1
+ tlbip_m vale2isnxs 1
+ tlbip_m ipas2e1osnxs 1
+ tlbip_m ipas2e1nxs 1
+ tlbip_m ripas2e1nxs 1
+ tlbip_m ripas2e1osnxs 1
+ tlbip_m ipas2le1osnxs 1
+ tlbip_m ipas2le1nxs 1
+ tlbip_m ripas2le1nxs 1
+ tlbip_m ripas2le1osnxs 1
+ tlbip_m rvae2osnxs 1
+ tlbip_m rvale2osnxs 1
+ tlbip_m rvae2nxs 1
+ tlbip_m rvale2nxs 1
+ tlbip_m vae2nxs 1
+ tlbip_m vale2nxs 1
+ tlbip_m vae3os 1
+ tlbip_m vale3os 1
+ tlbip_m rvae3is 1
+ tlbip_m rvale3is 1
+ tlbip_m vae3is 1
+ tlbip_m vale3is 1
+ tlbip_m rvae3os 1
+ tlbip_m rvale3os 1
+ tlbip_m rvae3 1
+ tlbip_m rvale3 1
+ tlbip_m vae3 1
+ tlbip_m vale3 1
+ tlbip_m vae3osnxs 1
+ tlbip_m vale3osnxs 1
+ tlbip_m rvae3isnxs 1
+ tlbip_m rvale3isnxs 1
+ tlbip_m vae3isnxs 1
+ tlbip_m vale3isnxs 1
+ tlbip_m rvae3osnxs 1
+ tlbip_m rvale3osnxs 1
+ tlbip_m rvae3nxs 1
+ tlbip_m rvale3nxs 1
+ tlbip_m vae3nxs 1
+ tlbip_m vale3nxs 1
--
2.42.0
next prev parent reply other threads:[~2024-01-03 1:18 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-01-03 1:17 [PATCH 00/12] aarch64: Add Armv9.4-A support for the d128 extension Victor Do Nascimento
2024-01-03 1:17 ` [PATCH 01/12] aarch64: Add +d128 architectural feature support Victor Do Nascimento
2024-01-03 1:17 ` [PATCH 02/12] aarch64: Expand maximum number of operands from 5 to 6 Victor Do Nascimento
2024-01-03 1:17 ` [PATCH 03/12] aarch64: Add support for xzr register in register pair operands Victor Do Nascimento
2024-01-03 1:17 ` [PATCH 04/12] aarch64: Add support for optional operand pairs Victor Do Nascimento
2024-01-03 1:17 ` [PATCH 05/12] aarch64: Add support for the SYSP 128-bit system instruction Victor Do Nascimento
2024-01-03 1:17 ` [PATCH 06/12] aarch64: Apply narrowing of allowed immediate values for SYSP Victor Do Nascimento
2024-01-03 1:17 ` [PATCH 07/12] aarch64: Create QL_SRC_X2 and QL_DEST_X2 qualifier macros Victor Do Nascimento
2024-01-03 1:17 ` [PATCH 08/12] aarch64: Implement TLBIP 128-bit instruction Victor Do Nascimento
2024-01-03 1:17 ` [PATCH 09/12] aarch64: Add xs variants of tlbip operands Victor Do Nascimento
2024-01-03 1:17 ` Victor Do Nascimento [this message]
2024-01-03 1:17 ` [PATCH 11/12] aarch64: Add support for 128-bit system register mrrs and msrr insns Victor Do Nascimento
2024-01-03 1:17 ` [PATCH 12/12] arch64: Add optional operand register pair support tests Victor Do Nascimento
2024-01-05 16:10 ` [PATCH 00/12] aarch64: Add Armv9.4-A support for the d128 extension Nick Clifton
2024-01-05 16:53 ` Victor Do Nascimento
2024-01-08 10:04 ` Nick Clifton
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