From: Victor Do Nascimento <victor.donascimento@arm.com>
To: <binutils@sourceware.org>
Cc: <richard.earnshaw@arm.com>, <nickc@redhat.com>,
Victor Do Nascimento <victor.donascimento@arm.com>
Subject: [PATCH 12/12] arch64: Add optional operand register pair support tests
Date: Wed, 3 Jan 2024 01:17:26 +0000 [thread overview]
Message-ID: <20240103011739.2444792-13-victor.donascimento@arm.com> (raw)
In-Reply-To: <20240103011739.2444792-1-victor.donascimento@arm.com>
Add tests to cover the full range of behaviors observed around
optional register operands for the `tlbip' and `sysp' instructions,
namely:
* Not all `tlbip' operations take GPR operands. When this is the
case, we should check that neither optional operand was supplied.
* When a `tlbip' operation is labeled with the `F_HASXT' flag, xzr
is not a valid optional operand. In such case, at least the fist
optional register needs to be specified with a non-xzr value.
* The first operand for both insns should be either xzr or an
even-numbered register (n % 2 == 0). In the former scenario, the
second operand should default to xzr too, while in the latter, it
should default to n + 1.
---
.../gas/aarch64/illegal-sysp-tlbip-optional.d | 4 ++++
.../gas/aarch64/illegal-sysp-tlbip-optional.l | 4 ++++
.../gas/aarch64/illegal-sysp-tlbip-optional.s | 10 +++++++++
.../gas/aarch64/sysp-tlbip-optional.d | 17 ++++++++++++++
.../gas/aarch64/sysp-tlbip-optional.s | 22 +++++++++++++++++++
5 files changed, 57 insertions(+)
create mode 100644 gas/testsuite/gas/aarch64/illegal-sysp-tlbip-optional.d
create mode 100644 gas/testsuite/gas/aarch64/illegal-sysp-tlbip-optional.l
create mode 100644 gas/testsuite/gas/aarch64/illegal-sysp-tlbip-optional.s
create mode 100644 gas/testsuite/gas/aarch64/sysp-tlbip-optional.d
create mode 100644 gas/testsuite/gas/aarch64/sysp-tlbip-optional.s
diff --git a/gas/testsuite/gas/aarch64/illegal-sysp-tlbip-optional.d b/gas/testsuite/gas/aarch64/illegal-sysp-tlbip-optional.d
new file mode 100644
index 00000000000..0bf5af405cb
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/illegal-sysp-tlbip-optional.d
@@ -0,0 +1,4 @@
+#name: Illegal optional operand pair use
+#as: -mno-verbose-error
+#source: illegal-sysp-tlbip-optional.s
+#error_output: illegal-sysp-tlbip-optional.l
diff --git a/gas/testsuite/gas/aarch64/illegal-sysp-tlbip-optional.l b/gas/testsuite/gas/aarch64/illegal-sysp-tlbip-optional.l
new file mode 100644
index 00000000000..69450747b15
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/illegal-sysp-tlbip-optional.l
@@ -0,0 +1,4 @@
+[^:]*: Assembler messages:
+[^:]*:5: Error: missing register at operand 2 -- `tlbip vale3nxs'
+[^:]*:9: Error: extraneous register at operand 2 -- `tlbip paall,x0'
+[^:]*:10: Error: extraneous register at operand 2 -- `tlbip paall,x0,x1'
diff --git a/gas/testsuite/gas/aarch64/illegal-sysp-tlbip-optional.s b/gas/testsuite/gas/aarch64/illegal-sysp-tlbip-optional.s
new file mode 100644
index 00000000000..1e02b71fdba
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/illegal-sysp-tlbip-optional.s
@@ -0,0 +1,10 @@
+ .arch armv9.4-a+d128
+
+ /* TLBIP operands marked with the F_HASXT don not allow xzr to be used
+ as GPR arguments and so require at least one register to be specified. */
+ tlbip vale3nxs
+
+ /* Conversely, those without the flag do not allow us to specify registers,
+ so the only accepted alternative is the complete omission of optional ops. */
+ tlbip paall, x0
+ tlbip paall, x0, x1
diff --git a/gas/testsuite/gas/aarch64/sysp-tlbip-optional.d b/gas/testsuite/gas/aarch64/sysp-tlbip-optional.d
new file mode 100644
index 00000000000..977dedbf843
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sysp-tlbip-optional.d
@@ -0,0 +1,17 @@
+#objdump: -dr
+
+.*
+
+Disassembly of section \.text:
+
+0+ <\.text>:
+[^:]*: d54e97a0 sysp #6, C9, C7, #5, x0, x1
+[^:]*: d54e97a0 sysp #6, C9, C7, #5, x0, x1
+[^:]*: d54e97a2 sysp #6, C9, C7, #5, x2, x3
+[^:]*: d54e97a2 sysp #6, C9, C7, #5, x2, x3
+[^:]*: d54e879f sysp #6, C8, C7, #4
+[^:]*: d54e97bf sysp #6, C9, C7, #5
+[^:]*: d54e97a0 sysp #6, C9, C7, #5, x0, x1
+[^:]*: d54e97a0 sysp #6, C9, C7, #5, x0, x1
+[^:]*: d54e97a2 sysp #6, C9, C7, #5, x2, x3
+[^:]*: d54e97a2 sysp #6, C9, C7, #5, x2, x3
diff --git a/gas/testsuite/gas/aarch64/sysp-tlbip-optional.s b/gas/testsuite/gas/aarch64/sysp-tlbip-optional.s
new file mode 100644
index 00000000000..3635db1d039
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sysp-tlbip-optional.s
@@ -0,0 +1,22 @@
+ .arch armv9.4-a+d128
+
+ /* TLBIP operands marked with the F_HASXT don not allow xzr to be used
+ as GPR arguments and so require at least one register to be specified. */
+ tlbip vale3nxs, x0
+ tlbip vale3nxs, x0, x1
+ tlbip vale3nxs, x2
+ tlbip vale3nxs, x2, x3
+
+
+ /* Conversely, those without the flag do not allow us to specify registers,
+ so the only accepted alternative is the complete omission of optional ops. */
+ tlbip paall
+
+ /* No such checking is carried out when the same instruction is issued
+ directly via the sysp implementation defined maintenance instruction,
+ such that both GRPs are optional. */
+ sysp #6, C9, C7, #5
+ sysp #6, C9, C7, #5, x0
+ sysp #6, C9, C7, #5, x0, x1
+ sysp #6, c9, c7, #5, x2
+ sysp #6, c9, c7, #5, x2, x3
--
2.42.0
next prev parent reply other threads:[~2024-01-03 1:18 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-01-03 1:17 [PATCH 00/12] aarch64: Add Armv9.4-A support for the d128 extension Victor Do Nascimento
2024-01-03 1:17 ` [PATCH 01/12] aarch64: Add +d128 architectural feature support Victor Do Nascimento
2024-01-03 1:17 ` [PATCH 02/12] aarch64: Expand maximum number of operands from 5 to 6 Victor Do Nascimento
2024-01-03 1:17 ` [PATCH 03/12] aarch64: Add support for xzr register in register pair operands Victor Do Nascimento
2024-01-03 1:17 ` [PATCH 04/12] aarch64: Add support for optional operand pairs Victor Do Nascimento
2024-01-03 1:17 ` [PATCH 05/12] aarch64: Add support for the SYSP 128-bit system instruction Victor Do Nascimento
2024-01-03 1:17 ` [PATCH 06/12] aarch64: Apply narrowing of allowed immediate values for SYSP Victor Do Nascimento
2024-01-03 1:17 ` [PATCH 07/12] aarch64: Create QL_SRC_X2 and QL_DEST_X2 qualifier macros Victor Do Nascimento
2024-01-03 1:17 ` [PATCH 08/12] aarch64: Implement TLBIP 128-bit instruction Victor Do Nascimento
2024-01-03 1:17 ` [PATCH 09/12] aarch64: Add xs variants of tlbip operands Victor Do Nascimento
2024-01-03 1:17 ` [PATCH 10/12] aarch64: Add TLBIP tests Victor Do Nascimento
2024-01-03 1:17 ` [PATCH 11/12] aarch64: Add support for 128-bit system register mrrs and msrr insns Victor Do Nascimento
2024-01-03 1:17 ` Victor Do Nascimento [this message]
2024-01-05 16:10 ` [PATCH 00/12] aarch64: Add Armv9.4-A support for the d128 extension Nick Clifton
2024-01-05 16:53 ` Victor Do Nascimento
2024-01-08 10:04 ` Nick Clifton
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