* [PATCH 01/12] aarch64: Add +d128 architectural feature support
2024-01-03 1:17 [PATCH 00/12] aarch64: Add Armv9.4-A support for the d128 extension Victor Do Nascimento
@ 2024-01-03 1:17 ` Victor Do Nascimento
2024-01-03 1:17 ` [PATCH 02/12] aarch64: Expand maximum number of operands from 5 to 6 Victor Do Nascimento
` (11 subsequent siblings)
12 siblings, 0 replies; 16+ messages in thread
From: Victor Do Nascimento @ 2024-01-03 1:17 UTC (permalink / raw)
To: binutils; +Cc: richard.earnshaw, nickc, Victor Do Nascimento
Indicating the presence of the Armv9.4-a features concerning 128-bit
Page Table Descriptors, 128-bit System Registers and Instructions,
the "+d128" architectural extension flag is added to the list of
possible -march options in Binutils, together with the necessary macro
for encoding d128 instructions.
---
gas/config/tc-aarch64.c | 2 ++
gas/doc/c-aarch64.texi | 2 ++
include/opcode/aarch64.h | 3 +++
opcodes/aarch64-tbl.h | 5 +++++
4 files changed, 12 insertions(+)
diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c
index c10d8201f5e..bfe91c90139 100644
--- a/gas/config/tc-aarch64.c
+++ b/gas/config/tc-aarch64.c
@@ -10297,6 +10297,8 @@ static const struct aarch64_option_cpu_value_table aarch64_features[] = {
{"the", AARCH64_FEATURE (THE), AARCH64_NO_FEATURES},
{"rasv2", AARCH64_FEATURE (RASv2), AARCH64_FEATURE (RAS)},
{"ite", AARCH64_FEATURE (ITE), AARCH64_NO_FEATURES},
+ {"d128", AARCH64_FEATURE (D128),
+ AARCH64_FEATURE (LSE128)},
{NULL, AARCH64_NO_FEATURES, AARCH64_NO_FEATURES},
};
diff --git a/gas/doc/c-aarch64.texi b/gas/doc/c-aarch64.texi
index 209d20fa832..7383343d167 100644
--- a/gas/doc/c-aarch64.texi
+++ b/gas/doc/c-aarch64.texi
@@ -274,6 +274,8 @@ automatically cause those extensions to be disabled.
@tab Enable Prediction instructions.
@item @code{ite} @tab N/A @tab no
@tab Enable TRCIT instruction.
+@item @code{d128} @tab Armv9.4-A @tab No
+ @tab Enable the 128-bit Page Descriptor Extension. This implies @code{lse128}.
@end multitable
@node AArch64 Syntax
diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h
index 1da337aaa58..9fc7643ffa1 100644
--- a/include/opcode/aarch64.h
+++ b/include/opcode/aarch64.h
@@ -201,6 +201,9 @@ enum aarch64_feature_bit {
AARCH64_FEATURE_PREDRES2,
/* Instrumentation Extension. */
AARCH64_FEATURE_ITE,
+ /* 128-bit page table descriptor, system registers
+ and isntructions. */
+ AARCH64_FEATURE_D128,
AARCH64_NUM_FEATURES
};
diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h
index 5dd0864c0ab..3be6daeb3b0 100644
--- a/opcodes/aarch64-tbl.h
+++ b/opcodes/aarch64-tbl.h
@@ -2582,6 +2582,8 @@ static const aarch64_feature_set aarch64_feature_gcs =
AARCH64_FEATURE (GCS);
static const aarch64_feature_set aarch64_feature_ite =
AARCH64_FEATURE (ITE);
+static const aarch64_feature_set aarch64_feature_d128 =
+ AARCH64_FEATURE (D128);
#define CORE &aarch64_feature_v8
#define FP &aarch64_feature_fp
@@ -2645,6 +2647,7 @@ static const aarch64_feature_set aarch64_feature_ite =
#define CHK &aarch64_feature_chk
#define GCS &aarch64_feature_gcs
#define ITE &aarch64_feature_ite
+#define D128 &aarch64_feature_d128
#define CORE_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS) \
{ NAME, OPCODE, MASK, CLASS, OP, CORE, OPS, QUALS, FLAGS, 0, 0, NULL }
@@ -2798,6 +2801,8 @@ static const aarch64_feature_set aarch64_feature_ite =
{ NAME, OPCODE, MASK, ic_system, 0, CHK, OPS, QUALS, FLAGS, 0, 0, NULL }
#define GCS_INSN(NAME, OPCODE, MASK, OPS, QUALS, FLAGS) \
{ NAME, OPCODE, MASK, gcs, 0, GCS, OPS, QUALS, FLAGS, 0, 0, NULL }
+#define D128_INSN(NAME,OPCODE,MASK,OPS,QUALS,FLAGS) \
+ { NAME, OPCODE, MASK, ic_system, 0, D128, OPS, QUALS, FLAGS, 0, 0, NULL }
#define MOPS_CPY_OP1_OP2_PME_INSN(NAME, OPCODE, MASK, FLAGS, CONSTRAINTS) \
MOPS_INSN (NAME, OPCODE, MASK, 0, \
--
2.42.0
^ permalink raw reply [flat|nested] 16+ messages in thread* [PATCH 02/12] aarch64: Expand maximum number of operands from 5 to 6
2024-01-03 1:17 [PATCH 00/12] aarch64: Add Armv9.4-A support for the d128 extension Victor Do Nascimento
2024-01-03 1:17 ` [PATCH 01/12] aarch64: Add +d128 architectural feature support Victor Do Nascimento
@ 2024-01-03 1:17 ` Victor Do Nascimento
2024-01-03 1:17 ` [PATCH 03/12] aarch64: Add support for xzr register in register pair operands Victor Do Nascimento
` (10 subsequent siblings)
12 siblings, 0 replies; 16+ messages in thread
From: Victor Do Nascimento @ 2024-01-03 1:17 UTC (permalink / raw)
To: binutils; +Cc: richard.earnshaw, nickc, Victor Do Nascimento
Given the introduction of the new Armv9.4-a `sysp' insn using the
following syntax:
sysp #<op1>, <Cn>, <Cm>, #<op2>{, <Xt1>, <Xt2>}
and by extension the need to encode 6 assembly operands, extend
Binutils to handle instructions taking 6 operands, up from a previous
maximum of 5.
---
include/opcode/aarch64.h | 2 +-
opcodes/aarch64-tbl.h | 2 ++
2 files changed, 3 insertions(+), 1 deletion(-)
diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h
index 9fc7643ffa1..b9ea73c4259 100644
--- a/include/opcode/aarch64.h
+++ b/include/opcode/aarch64.h
@@ -1075,7 +1075,7 @@ enum err_type
};
/* Maximum number of operands an instruction can have. */
-#define AARCH64_MAX_OPND_NUM 6
+#define AARCH64_MAX_OPND_NUM 7
/* Maximum number of qualifier sequences an instruction can have. */
#define AARCH64_MAX_QLF_SEQ_NUM 10
/* Operand qualifier typedef; optimized for the size. */
diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h
index 3be6daeb3b0..605f6f2438f 100644
--- a/opcodes/aarch64-tbl.h
+++ b/opcodes/aarch64-tbl.h
@@ -34,6 +34,7 @@
#define OP3(a,b,c) {OPND(a), OPND(b), OPND(c)}
#define OP4(a,b,c,d) {OPND(a), OPND(b), OPND(c), OPND(d)}
#define OP5(a,b,c,d,e) {OPND(a), OPND(b), OPND(c), OPND(d), OPND(e)}
+#define OP6(a,b,c,d,e,f) {OPND(a), OPND(b), OPND(c), OPND(d), OPND(e), OPND(f)}
#define QLF(x) AARCH64_OPND_QLF_##x
#define QLF1(a) {QLF(a)}
@@ -41,6 +42,7 @@
#define QLF3(a,b,c) {QLF(a), QLF(b), QLF(c)}
#define QLF4(a,b,c,d) {QLF(a), QLF(b), QLF(c), QLF(d)}
#define QLF5(a,b,c,d,e) {QLF(a), QLF(b), QLF(c), QLF(d), QLF(e)}
+#define QLF6(a,b,c,d,e) {QLF(a), QLF(b), QLF(c), QLF(d), QLF(e), QLF(f)}
/* Qualifiers list. */
--
2.42.0
^ permalink raw reply [flat|nested] 16+ messages in thread* [PATCH 03/12] aarch64: Add support for xzr register in register pair operands
2024-01-03 1:17 [PATCH 00/12] aarch64: Add Armv9.4-A support for the d128 extension Victor Do Nascimento
2024-01-03 1:17 ` [PATCH 01/12] aarch64: Add +d128 architectural feature support Victor Do Nascimento
2024-01-03 1:17 ` [PATCH 02/12] aarch64: Expand maximum number of operands from 5 to 6 Victor Do Nascimento
@ 2024-01-03 1:17 ` Victor Do Nascimento
2024-01-03 1:17 ` [PATCH 04/12] aarch64: Add support for optional operand pairs Victor Do Nascimento
` (9 subsequent siblings)
12 siblings, 0 replies; 16+ messages in thread
From: Victor Do Nascimento @ 2024-01-03 1:17 UTC (permalink / raw)
To: binutils; +Cc: richard.earnshaw, nickc, Victor Do Nascimento
Analysis of the allowed operand values for `sysp' and `tlbip' reveals
a significant departure from the allowed behavior for operand register
pairs (hitherto labeled AARCH64_OPND_PAIRREG) observed for other
insns in this category.
For instructions `casp', `mrrs' and `msrr' the register pair must
always start at an even index and the second register in the pair is
the index + 1. This precludes the use of xzr as the first register,
given it corresponds to register number 31.
This is different in the case of `sysp' and `tlbip', however. These
allow the use of xzr and, where the first operand in the pair is
omitted, this is the default value assigned to it. When this
operand is assigned xzr, it is expected that the second operand will
likewise take on a value of xzr.
These two instructions therefore "break" two rules of register pairs:
* The first of the two registers is odd-numbered.
* The index of the second register is equal to that of the first,
and not n+1.
To allow for this departure from hitherto standard behavior, we
extend the functionality of the assembler by defining an extension of
the AARCH64_OPND_PAIRREG, called AARCH64_OPND_PAIRREG_OR_XZR.
It is used in defining `sysp' and `tlbip' and allows
`operand_general_constraint_met_p' to allow the pair to both take on
the value of xzr.
---
gas/config/tc-aarch64.c | 1 +
include/opcode/aarch64.h | 1 +
opcodes/aarch64-dis.c | 7 +++++--
opcodes/aarch64-opc.c | 19 +++++++++++++++++--
opcodes/aarch64-tbl.h | 2 ++
5 files changed, 26 insertions(+), 4 deletions(-)
diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c
index bfe91c90139..796a6da267b 100644
--- a/gas/config/tc-aarch64.c
+++ b/gas/config/tc-aarch64.c
@@ -6532,6 +6532,7 @@ parse_operands (char *str, const aarch64_opcode *opcode)
case AARCH64_OPND_Rt_LS64:
case AARCH64_OPND_Rt_SYS:
case AARCH64_OPND_PAIRREG:
+ case AARCH64_OPND_PAIRREG_OR_XZR:
case AARCH64_OPND_SVE_Rm:
po_int_fp_reg_or_fail (REG_TYPE_R_ZR);
diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h
index b9ea73c4259..d3db252e5c2 100644
--- a/include/opcode/aarch64.h
+++ b/include/opcode/aarch64.h
@@ -455,6 +455,7 @@ enum aarch64_opnd
AARCH64_OPND_Rn_SP, /* Integer Rn or SP. */
AARCH64_OPND_Rm_SP, /* Integer Rm or SP. */
AARCH64_OPND_PAIRREG, /* Paired register operand. */
+ AARCH64_OPND_PAIRREG_OR_XZR, /* Paired register operand, optionally xzr. */
AARCH64_OPND_Rm_EXT, /* Integer Rm extended. */
AARCH64_OPND_Rm_SFT, /* Integer Rm shifted. */
diff --git a/opcodes/aarch64-dis.c b/opcodes/aarch64-dis.c
index 3bf5f50effc..e9f47807654 100644
--- a/opcodes/aarch64-dis.c
+++ b/opcodes/aarch64-dis.c
@@ -302,8 +302,11 @@ aarch64_ext_regno_pair (const aarch64_operand *self ATTRIBUTE_UNUSED, aarch64_op
aarch64_operand_error *errors ATTRIBUTE_UNUSED)
{
assert (info->idx == 1
- || info->idx ==3);
- info->reg.regno = inst->operands[info->idx - 1].reg.regno + 1;
+ || info->idx == 3);
+
+ unsigned prev_regno = inst->operands[info->idx - 1].reg.regno;
+ info->reg.regno = (prev_regno == 0x1f) ? 0x1f
+ : prev_regno + 1;
return true;
}
diff --git a/opcodes/aarch64-opc.c b/opcodes/aarch64-opc.c
index 4d84071ba8c..4530591b329 100644
--- a/opcodes/aarch64-opc.c
+++ b/opcodes/aarch64-opc.c
@@ -1693,8 +1693,22 @@ operand_general_constraint_met_p (const aarch64_opnd_info *opnds, int idx,
switch (aarch64_operands[type].op_class)
{
case AARCH64_OPND_CLASS_INT_REG:
- /* Check pair reg constraints for cas* instructions. */
- if (type == AARCH64_OPND_PAIRREG)
+ /* Check for pair of xzr registers. */
+ if (type == AARCH64_OPND_PAIRREG_OR_XZR
+ && opnds[idx - 1].reg.regno == 0x1f)
+ {
+ if (opnds[idx].reg.regno != 0x1f)
+ {
+ set_syntax_error (mismatch_detail, idx - 1,
+ _("second reg in pair should be xzr if first is"
+ " xzr"));
+ return 0;
+ }
+ }
+ /* Check pair reg constraints for instructions taking a pair of
+ consecutively-numbered general-purpose registers. */
+ else if (type == AARCH64_OPND_PAIRREG
+ || type == AARCH64_OPND_PAIRREG_OR_XZR)
{
assert (idx == 1 || idx == 3);
if (opnds[idx - 1].reg.regno % 2 != 0)
@@ -3771,6 +3785,7 @@ aarch64_print_operand (char *buf, size_t size, bfd_vma pc,
case AARCH64_OPND_Rt_LS64:
case AARCH64_OPND_Rt_SYS:
case AARCH64_OPND_PAIRREG:
+ case AARCH64_OPND_PAIRREG_OR_XZR:
case AARCH64_OPND_SVE_Rm:
case AARCH64_OPND_LSE128_Rt:
case AARCH64_OPND_LSE128_Rt2:
diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h
index 605f6f2438f..1dfbee25786 100644
--- a/opcodes/aarch64-tbl.h
+++ b/opcodes/aarch64-tbl.h
@@ -6174,6 +6174,8 @@ const struct aarch64_opcode aarch64_opcode_table[] =
"an integer or stack pointer register") \
X(INT_REG, 0, ext_regno_pair, "PAIRREG", 0, F(), \
"the second reg of a pair") \
+ X(INT_REG, 0, ext_regno_pair, "PAIRREG_OR_XZR", 0, F(), \
+ "the second reg of a pair") \
Y(MODIFIED_REG, reg_extended, "Rm_EXT", 0, F(), \
"an integer register with optional extension") \
Y(MODIFIED_REG, reg_shifted, "Rm_SFT", 0, F(), \
--
2.42.0
^ permalink raw reply [flat|nested] 16+ messages in thread* [PATCH 04/12] aarch64: Add support for optional operand pairs
2024-01-03 1:17 [PATCH 00/12] aarch64: Add Armv9.4-A support for the d128 extension Victor Do Nascimento
` (2 preceding siblings ...)
2024-01-03 1:17 ` [PATCH 03/12] aarch64: Add support for xzr register in register pair operands Victor Do Nascimento
@ 2024-01-03 1:17 ` Victor Do Nascimento
2024-01-03 1:17 ` [PATCH 05/12] aarch64: Add support for the SYSP 128-bit system instruction Victor Do Nascimento
` (8 subsequent siblings)
12 siblings, 0 replies; 16+ messages in thread
From: Victor Do Nascimento @ 2024-01-03 1:17 UTC (permalink / raw)
To: binutils; +Cc: richard.earnshaw, nickc, Victor Do Nascimento
Two of the instructions added by the `+d128' architectural extension
add the flexibility to have two optional operands. Prior to the
addition of the `tlbip' and `sysp' instructions, no mnemonic allowed
more than one such optional operand.
With `tlbip' as an example, some TLBIP instruction names do not allow
for any optional operands, while others allow for both to be optional.
In the latter case, it is possible that either the second operand
alone is omitted or both operands are omitted.
Therefore, a considerable degree of flexibility needed to be added to
the way operands were parsed. It was, however, possible to achieve
this with relatively few changes to existing code.
it is noteworthy that opcode flags specifying the optional operand
number are non-orthogonal. For example, we have:
#define F_OPD1_OPT (2 << 12) : 0b10 << 12
#define F_OPD2_OPT (3 << 12) : 0b11 << 12
such that by virtue of the observation that
(F_OPD1_OPT | F_OPD2_OPT) == F_OPD2_OPT
it is impossible to mark both operands 1 and 2 as optional for an
instruction and it is assumed that a maximum of 1 operand can ever be
optional. This is not overly-problematic given that, for optional
pairs, the second optional operand is always found immediately after
the first. Thus, it suffices for us to flag that there is a second
optional operand. With this fact, we can infer its position in the
mnemonic from the position of the first (e.g. if the second operand in
the mnemonic is optional, we know the third is too). We therefore
define the `F_OPD_PAIR_OPT' flag and calculate its position in the
mnemonic from the value encoded by the `F_OPD<n>_OPT' flag.
Another observation is that there is a tight coupling between default
values assigned to the two registers when one (or both) are omitted
from the mnemonic. Namely, if Xt1 has a value of 0x1f (the zero
register is specified), Xt2 defaults to the same value, otherwise Xt2
will be assigned Xt + 1. This meant that where you have default value
validation, in checking the second optional operand's value, it is
also necessary to look at the value assigned to the
previously-processed operand value before deciding its validity. Thus
`process_omitted_operand' needs not only access to its `operand'
argument, but also to the global `inst' struct.
---
gas/config/tc-aarch64.c | 19 +++++++++++++++++--
include/opcode/aarch64.h | 12 +++++++++++-
2 files changed, 28 insertions(+), 3 deletions(-)
diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c
index 796a6da267b..12fb1740635 100644
--- a/gas/config/tc-aarch64.c
+++ b/gas/config/tc-aarch64.c
@@ -6179,6 +6179,17 @@ process_omitted_operand (enum aarch64_opnd type, const aarch64_opcode *opcode,
case AARCH64_OPND_VnD1:
operand->reg.regno = default_value;
break;
+ case AARCH64_OPND_PAIRREG_OR_XZR:
+ if (inst.base.operands[idx - 1].reg.regno == 0x1f)
+ {
+ operand->reg.regno = 0x1f;
+ break;
+ }
+ operand->reg.regno = inst.base.operands[idx - 1].reg.regno + 1;
+ break;
+ case AARCH64_OPND_PAIRREG:
+ operand->reg.regno = inst.base.operands[idx - 1].reg.regno + 1;
+ break;
case AARCH64_OPND_Ed:
case AARCH64_OPND_En:
@@ -7875,6 +7886,12 @@ parse_operands (char *str, const aarch64_opcode *opcode)
/* If we get here, this operand was successfully parsed. */
inst.base.operands[i].present = 1;
+
+ /* As instructions can have multiple optional operands, it is imporant to
+ reset the backtrack_pos variable once we finish processing an operand
+ successfully. */
+ backtrack_pos = 0;
+
continue;
failure:
@@ -7896,8 +7913,6 @@ parse_operands (char *str, const aarch64_opcode *opcode)
char *tmp = backtrack_pos;
char endchar = END_OF_INSN;
- if (i != (aarch64_num_of_operands (opcode) - 1))
- endchar = ',';
skip_past_char (&tmp, ',');
if (*tmp != endchar)
diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h
index d3db252e5c2..c69f85557d0 100644
--- a/include/opcode/aarch64.h
+++ b/include/opcode/aarch64.h
@@ -1220,7 +1220,11 @@ extern const aarch64_opcode aarch64_opcode_table[];
/* This instruction has an extra constraint on it that imposes a requirement on
subsequent instructions. */
#define F_SCAN (1ULL << 31)
-/* Next bit is 32. */
+/* Instruction takes a pair of optional operands. If we specify the Nth operand
+ to be optional, then we also implicitly specify (N+1)th operand to also be
+ optional. */
+#define F_OPD_PAIR_OPT (1ULL << 32)
+/* Next bit is 33. */
/* Instruction constraints. */
/* This instruction has a predication constraint on the instruction at PC+4. */
@@ -1259,9 +1263,15 @@ pseudo_opcode_p (const aarch64_opcode *opcode)
return (opcode->flags & F_PSEUDO) != 0lu;
}
+/* Deal with two possible scenarios: If F_OP_PAIR_OPT not set, as is the case
+ by default, F_OPDn_OPT must equal IDX + 1, else F_OPDn_OPT must be in range
+ [IDX, IDX + 1]. */
static inline bool
optional_operand_p (const aarch64_opcode *opcode, unsigned int idx)
{
+ if (opcode->flags & F_OPD_PAIR_OPT)
+ return (((opcode->flags >> 12) & 0x7) == idx
+ || ((opcode->flags >> 12) & 0x7) == idx + 1);
return ((opcode->flags >> 12) & 0x7) == idx + 1;
}
--
2.42.0
^ permalink raw reply [flat|nested] 16+ messages in thread* [PATCH 05/12] aarch64: Add support for the SYSP 128-bit system instruction
2024-01-03 1:17 [PATCH 00/12] aarch64: Add Armv9.4-A support for the d128 extension Victor Do Nascimento
` (3 preceding siblings ...)
2024-01-03 1:17 ` [PATCH 04/12] aarch64: Add support for optional operand pairs Victor Do Nascimento
@ 2024-01-03 1:17 ` Victor Do Nascimento
2024-01-03 1:17 ` [PATCH 06/12] aarch64: Apply narrowing of allowed immediate values for SYSP Victor Do Nascimento
` (7 subsequent siblings)
12 siblings, 0 replies; 16+ messages in thread
From: Victor Do Nascimento @ 2024-01-03 1:17 UTC (permalink / raw)
To: binutils; +Cc: richard.earnshaw, nickc, Victor Do Nascimento
Mirroring the use of the `sys' - System Instruction assembly
instruction, this implements its 128-bit counterpart, `sysp'.
This optionally takes two contiguous general-purpose registers
starting at an even number or, when these are omitted, by default
sets both of these to xzr.
Syntax:
sysp #<op1>, <Cn>, <Cm>, #<op2>{, <Xt1>, <Xt2>}
---
gas/testsuite/gas/aarch64/illegal-sys128.l | 4 ++++
gas/testsuite/gas/aarch64/illegal-sys128.s | 5 +++++
opcodes/aarch64-dis.c | 3 ++-
opcodes/aarch64-opc.c | 2 +-
opcodes/aarch64-tbl.h | 9 ++++++++-
5 files changed, 20 insertions(+), 3 deletions(-)
create mode 100644 gas/testsuite/gas/aarch64/illegal-sys128.l
create mode 100644 gas/testsuite/gas/aarch64/illegal-sys128.s
diff --git a/gas/testsuite/gas/aarch64/illegal-sys128.l b/gas/testsuite/gas/aarch64/illegal-sys128.l
new file mode 100644
index 00000000000..b86fbc86af0
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/illegal-sys128.l
@@ -0,0 +1,4 @@
+.*: Assembler messages:
+.*: Error: C8 - C9 expected at operand 2 -- `sysp #0,C7,C0,#0,x0,x1'
+.*: Error: C8 - C9 expected at operand 2 -- `sysp #0,C10,C0,#0,x0,x1'
+.*: Error: C0 - C7 expected at operand 3 -- `sysp #6,C9,C8,#7,x27,x28'
diff --git a/gas/testsuite/gas/aarch64/illegal-sys128.s b/gas/testsuite/gas/aarch64/illegal-sys128.s
new file mode 100644
index 00000000000..42473c9b40e
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/illegal-sys128.s
@@ -0,0 +1,5 @@
+ .arch armv8-a+d128
+
+ sysp #0, C7, C0, #0, x0, x1
+ sysp #0, C10, C0, #0, x0, x1
+ sysp #6, C9, C8, #7, x27, x28
diff --git a/opcodes/aarch64-dis.c b/opcodes/aarch64-dis.c
index e9f47807654..32831e855cd 100644
--- a/opcodes/aarch64-dis.c
+++ b/opcodes/aarch64-dis.c
@@ -302,7 +302,8 @@ aarch64_ext_regno_pair (const aarch64_operand *self ATTRIBUTE_UNUSED, aarch64_op
aarch64_operand_error *errors ATTRIBUTE_UNUSED)
{
assert (info->idx == 1
- || info->idx == 3);
+ || info->idx == 3
+ || info->idx == 5);
unsigned prev_regno = inst->operands[info->idx - 1].reg.regno;
info->reg.regno = (prev_regno == 0x1f) ? 0x1f
diff --git a/opcodes/aarch64-opc.c b/opcodes/aarch64-opc.c
index 4530591b329..38a377110de 100644
--- a/opcodes/aarch64-opc.c
+++ b/opcodes/aarch64-opc.c
@@ -1710,7 +1710,7 @@ operand_general_constraint_met_p (const aarch64_opnd_info *opnds, int idx,
else if (type == AARCH64_OPND_PAIRREG
|| type == AARCH64_OPND_PAIRREG_OR_XZR)
{
- assert (idx == 1 || idx == 3);
+ assert (idx == 1 || idx == 3 || idx == 5);
if (opnds[idx - 1].reg.regno % 2 != 0)
{
set_syntax_error (mismatch_detail, idx - 1,
diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h
index 1dfbee25786..79830e007d5 100644
--- a/opcodes/aarch64-tbl.h
+++ b/opcodes/aarch64-tbl.h
@@ -42,7 +42,7 @@
#define QLF3(a,b,c) {QLF(a), QLF(b), QLF(c)}
#define QLF4(a,b,c,d) {QLF(a), QLF(b), QLF(c), QLF(d)}
#define QLF5(a,b,c,d,e) {QLF(a), QLF(b), QLF(c), QLF(d), QLF(e)}
-#define QLF6(a,b,c,d,e) {QLF(a), QLF(b), QLF(c), QLF(d), QLF(e), QLF(f)}
+#define QLF6(a,b,c,d,e,f) {QLF(a), QLF(b), QLF(c), QLF(d), QLF(e), QLF(f)}
/* Qualifiers list. */
@@ -70,6 +70,12 @@
QLF5(X,NIL,CR,CR,NIL), \
}
+/* e.g. SYSP #<op1>, <Cn>, <Cm>, #<op2>{, <Xt>, <Xt+1>}. */
+#define QL_SYSP \
+{ \
+ QLF6(NIL,CR,CR,NIL,X,X), \
+}
+
/* e.g. ADRP <Xd>, <label>. */
#define QL_ADRP \
{ \
@@ -4195,6 +4201,7 @@ const struct aarch64_opcode aarch64_opcode_table[] =
GCS_INSN ("gcssttr", 0xd91f1c00, 0xfffffc00, OP2 (Rt, Rn_SP), QL_I2SAMEX, 0),
CORE_INSN ("gcsb", 0xd503227f, 0xffffffff, ic_system, 0, OP1 (BARRIER_GCSB), {}, F_ALIAS),
CORE_INSN ("sys", 0xd5080000, 0xfff80000, ic_system, 0, OP5 (UIMM3_OP1, CRn, CRm, UIMM3_OP2, Rt), QL_SYS, F_HAS_ALIAS | F_OPD4_OPT | F_DEFAULT (0x1F)),
+ D128_INSN ("sysp", 0xd5480000, 0xfff80000, OP6 (UIMM3_OP1, CRn, CRm, UIMM3_OP2, Rt, PAIRREG_OR_XZR), QL_SYSP, F_HAS_ALIAS | F_OPD4_OPT | F_OPD_PAIR_OPT | F_DEFAULT (0x1f)),
CORE_INSN ("at", 0xd5080000, 0xfff80000, ic_system, 0, OP2 (SYSREG_AT, Rt), QL_SRC_X, F_ALIAS),
CORE_INSN ("dc", 0xd5080000, 0xfff80000, ic_system, 0, OP2 (SYSREG_DC, Rt), QL_SRC_X, F_ALIAS),
CORE_INSN ("ic", 0xd5080000, 0xfff80000, ic_system, 0, OP2 (SYSREG_IC, Rt_SYS), QL_SRC_X, F_ALIAS | F_OPD1_OPT | F_DEFAULT (0x1F)),
--
2.42.0
^ permalink raw reply [flat|nested] 16+ messages in thread* [PATCH 06/12] aarch64: Apply narrowing of allowed immediate values for SYSP
2024-01-03 1:17 [PATCH 00/12] aarch64: Add Armv9.4-A support for the d128 extension Victor Do Nascimento
` (4 preceding siblings ...)
2024-01-03 1:17 ` [PATCH 05/12] aarch64: Add support for the SYSP 128-bit system instruction Victor Do Nascimento
@ 2024-01-03 1:17 ` Victor Do Nascimento
2024-01-03 1:17 ` [PATCH 07/12] aarch64: Create QL_SRC_X2 and QL_DEST_X2 qualifier macros Victor Do Nascimento
` (6 subsequent siblings)
12 siblings, 0 replies; 16+ messages in thread
From: Victor Do Nascimento @ 2024-01-03 1:17 UTC (permalink / raw)
To: binutils; +Cc: richard.earnshaw, nickc, Victor Do Nascimento
While CRn and CRm fields in the SYSP instruction are 4-bit wide and
are thus able to accommodate values in the range 0-15, the
specifications for the SYSP instructions limit their ranges to 8-9 for
CRm and 0-7 in the case of CRn.
This led to the need to signal in some way to the operand parser that
a given operand is under special restrictions regarding its use. This
is done via the new `F_OPD_NARROW' flag, indicating a narrowing in the
range of operand values for fields in the instruction tagged with the
flag.
The flag is then used in `parse_operands' when the instruction is
assembled, but needs not be taken into consideration during
disassembly.
---
gas/config/tc-aarch64.c | 18 +++++++++++++++++-
gas/testsuite/gas/aarch64/illegal-sys128.d | 3 +++
gas/testsuite/gas/aarch64/sysp.d | 10 ++++++++++
gas/testsuite/gas/aarch64/sysp.s | 4 ++++
include/opcode/aarch64.h | 7 ++++++-
opcodes/aarch64-tbl.h | 2 +-
6 files changed, 41 insertions(+), 3 deletions(-)
create mode 100644 gas/testsuite/gas/aarch64/illegal-sys128.d
create mode 100644 gas/testsuite/gas/aarch64/sysp.d
create mode 100644 gas/testsuite/gas/aarch64/sysp.s
diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c
index 12fb1740635..cc08fd31dd4 100644
--- a/gas/config/tc-aarch64.c
+++ b/gas/config/tc-aarch64.c
@@ -6485,6 +6485,7 @@ parse_operands (char *str, const aarch64_opcode *opcode)
int i;
char *backtrack_pos = 0;
const enum aarch64_opnd *operands = opcode->operands;
+ const uint64_t flags = opcode->flags;
aarch64_reg_type imm_reg_type;
clear_error ();
@@ -6833,7 +6834,22 @@ parse_operands (char *str, const aarch64_opcode *opcode)
goto failure;
po_imm_nc_or_fail ();
- if (val > 15)
+ if (flags & F_OPD_NARROW)
+ {
+ if ((operands[i] == AARCH64_OPND_CRn)
+ && (val < 8 || val > 9))
+ {
+ set_fatal_syntax_error (_(N_ ("C8 - C9 expected")));
+ goto failure;
+ }
+ else if ((operands[i] == AARCH64_OPND_CRm)
+ && (val > 7))
+ {
+ set_fatal_syntax_error (_(N_ ("C0 - C7 expected")));
+ goto failure;
+ }
+ }
+ else if (val > 15)
{
set_fatal_syntax_error (_(N_ ("C0 - C15 expected")));
goto failure;
diff --git a/gas/testsuite/gas/aarch64/illegal-sys128.d b/gas/testsuite/gas/aarch64/illegal-sys128.d
new file mode 100644
index 00000000000..891b9347167
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/illegal-sys128.d
@@ -0,0 +1,3 @@
+#name: Out-of-bounds SYSP operand tests
+#source: illegal-sys128.s
+#error_output: illegal-sys128.l
diff --git a/gas/testsuite/gas/aarch64/sysp.d b/gas/testsuite/gas/aarch64/sysp.d
new file mode 100644
index 00000000000..80286c19ffd
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sysp.d
@@ -0,0 +1,10 @@
+#objdump: -dr
+
+.*
+
+
+Disassembly of section \.text:
+
+0+ <\.text>:
+[^:]*: d5488000 sysp #0, C8, C0, #0, x0, x1
+[^:]*: d54e97fa sysp #6, C9, C7, #7, x26, x27
\ No newline at end of file
diff --git a/gas/testsuite/gas/aarch64/sysp.s b/gas/testsuite/gas/aarch64/sysp.s
new file mode 100644
index 00000000000..f50d3ab05a8
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sysp.s
@@ -0,0 +1,4 @@
+ .arch armv9.4-a+d128
+
+ sysp #0, C8, C0, #0, x0, x1
+ sysp #6, C9, C7, #7, x26, x27
diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h
index c69f85557d0..d170bdf0bde 100644
--- a/include/opcode/aarch64.h
+++ b/include/opcode/aarch64.h
@@ -1224,7 +1224,12 @@ extern const aarch64_opcode aarch64_opcode_table[];
to be optional, then we also implicitly specify (N+1)th operand to also be
optional. */
#define F_OPD_PAIR_OPT (1ULL << 32)
-/* Next bit is 33. */
+/* This instruction does not allow the full range of values that the
+ width of fields in the assembler instruction would theoretically
+ allow. This impacts the constraintts on assembly but yelds no
+ impact on disassembly. */
+#define F_OPD_NARROW (1ULL << 33)
+/* Next bit is 34. */
/* Instruction constraints. */
/* This instruction has a predication constraint on the instruction at PC+4. */
diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h
index 79830e007d5..98feb56e08a 100644
--- a/opcodes/aarch64-tbl.h
+++ b/opcodes/aarch64-tbl.h
@@ -4201,7 +4201,7 @@ const struct aarch64_opcode aarch64_opcode_table[] =
GCS_INSN ("gcssttr", 0xd91f1c00, 0xfffffc00, OP2 (Rt, Rn_SP), QL_I2SAMEX, 0),
CORE_INSN ("gcsb", 0xd503227f, 0xffffffff, ic_system, 0, OP1 (BARRIER_GCSB), {}, F_ALIAS),
CORE_INSN ("sys", 0xd5080000, 0xfff80000, ic_system, 0, OP5 (UIMM3_OP1, CRn, CRm, UIMM3_OP2, Rt), QL_SYS, F_HAS_ALIAS | F_OPD4_OPT | F_DEFAULT (0x1F)),
- D128_INSN ("sysp", 0xd5480000, 0xfff80000, OP6 (UIMM3_OP1, CRn, CRm, UIMM3_OP2, Rt, PAIRREG_OR_XZR), QL_SYSP, F_HAS_ALIAS | F_OPD4_OPT | F_OPD_PAIR_OPT | F_DEFAULT (0x1f)),
+ D128_INSN ("sysp", 0xd5480000, 0xfff80000, OP6 (UIMM3_OP1, CRn, CRm, UIMM3_OP2, Rt, PAIRREG_OR_XZR), QL_SYSP, F_HAS_ALIAS | F_OPD_NARROW | F_OPD4_OPT | F_OPD_PAIR_OPT | F_DEFAULT (0x1f)),
CORE_INSN ("at", 0xd5080000, 0xfff80000, ic_system, 0, OP2 (SYSREG_AT, Rt), QL_SRC_X, F_ALIAS),
CORE_INSN ("dc", 0xd5080000, 0xfff80000, ic_system, 0, OP2 (SYSREG_DC, Rt), QL_SRC_X, F_ALIAS),
CORE_INSN ("ic", 0xd5080000, 0xfff80000, ic_system, 0, OP2 (SYSREG_IC, Rt_SYS), QL_SRC_X, F_ALIAS | F_OPD1_OPT | F_DEFAULT (0x1F)),
--
2.42.0
^ permalink raw reply [flat|nested] 16+ messages in thread* [PATCH 07/12] aarch64: Create QL_SRC_X2 and QL_DEST_X2 qualifier macros
2024-01-03 1:17 [PATCH 00/12] aarch64: Add Armv9.4-A support for the d128 extension Victor Do Nascimento
` (5 preceding siblings ...)
2024-01-03 1:17 ` [PATCH 06/12] aarch64: Apply narrowing of allowed immediate values for SYSP Victor Do Nascimento
@ 2024-01-03 1:17 ` Victor Do Nascimento
2024-01-03 1:17 ` [PATCH 08/12] aarch64: Implement TLBIP 128-bit instruction Victor Do Nascimento
` (5 subsequent siblings)
12 siblings, 0 replies; 16+ messages in thread
From: Victor Do Nascimento @ 2024-01-03 1:17 UTC (permalink / raw)
To: binutils; +Cc: richard.earnshaw, nickc, Victor Do Nascimento
Some 128-bit system operations (mrrs, msrr, tlbip, and sysp) take two
qualified operands and one of unqualified type (e.g. system register
name, tlbip operation). This creates the need for adequate qualifiers
to handle this.
This patch therefore introduces the `QL_SRC_X2' and `QL_DST_X2' qualifier
specifiers, which expand to `QLF3(NIL,X,X)' and `QLF3(X,X,NIL)',
respectively.
---
opcodes/aarch64-tbl.h | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h
index 98feb56e08a..06b1550e9a3 100644
--- a/opcodes/aarch64-tbl.h
+++ b/opcodes/aarch64-tbl.h
@@ -52,12 +52,24 @@
QLF2(NIL,X), \
}
+/* e.g. MSRR <systemreg>, <Xt>, <Xt2>. */
+#define QL_SRC_X2 \
+{ \
+ QLF3(NIL,X,X), \
+}
+
/* e.g. MRS <Xt>, <systemreg>. */
#define QL_DST_X \
{ \
QLF2(X,NIL), \
}
+/* e.g. MRRS <Xt>, <Xt2>, <systemreg>. */
+#define QL_DST_X2 \
+{ \
+ QLF3(X,X,NIL), \
+}
+
/* e.g. SYS #<op1>, <Cn>, <Cm>, #<op2>{, <Xt>}. */
#define QL_SYS \
{ \
--
2.42.0
^ permalink raw reply [flat|nested] 16+ messages in thread* [PATCH 08/12] aarch64: Implement TLBIP 128-bit instruction
2024-01-03 1:17 [PATCH 00/12] aarch64: Add Armv9.4-A support for the d128 extension Victor Do Nascimento
` (6 preceding siblings ...)
2024-01-03 1:17 ` [PATCH 07/12] aarch64: Create QL_SRC_X2 and QL_DEST_X2 qualifier macros Victor Do Nascimento
@ 2024-01-03 1:17 ` Victor Do Nascimento
2024-01-03 1:17 ` [PATCH 09/12] aarch64: Add xs variants of tlbip operands Victor Do Nascimento
` (4 subsequent siblings)
12 siblings, 0 replies; 16+ messages in thread
From: Victor Do Nascimento @ 2024-01-03 1:17 UTC (permalink / raw)
To: binutils; +Cc: richard.earnshaw, nickc, Victor Do Nascimento
The addition of 128-bit page table descriptors and, with it, the
addition of 128-bit system registers for these means that special
"invalidate translation table entry" instructions are needed to cope
with the new 128-bit model. This is introduced with the `tlbpi'
instruction, implemented here.
---
gas/config/tc-aarch64.c | 1 +
include/opcode/aarch64.h | 1 +
opcodes/aarch64-tbl.h | 3 +++
3 files changed, 5 insertions(+)
diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c
index cc08fd31dd4..95661445f0c 100644
--- a/gas/config/tc-aarch64.c
+++ b/gas/config/tc-aarch64.c
@@ -7677,6 +7677,7 @@ parse_operands (char *str, const aarch64_opcode *opcode)
goto sys_reg_ins;
case AARCH64_OPND_SYSREG_TLBI:
+ case AARCH64_OPND_SYSREG_TLBIP:
inst.base.operands[i].sysins_op =
parse_sys_ins_reg (&str, aarch64_sys_regs_tlbi_hsh);
sys_reg_ins:
diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h
index d170bdf0bde..55d584d16eb 100644
--- a/include/opcode/aarch64.h
+++ b/include/opcode/aarch64.h
@@ -566,6 +566,7 @@ enum aarch64_opnd
AARCH64_OPND_SYSREG_DC, /* System register <dc_op> operand. */
AARCH64_OPND_SYSREG_IC, /* System register <ic_op> operand. */
AARCH64_OPND_SYSREG_TLBI, /* System register <tlbi_op> operand. */
+ AARCH64_OPND_SYSREG_TLBIP, /* System register <tlbip_op> operand. */
AARCH64_OPND_SYSREG_SR, /* System register RCTX operand. */
AARCH64_OPND_BARRIER, /* Barrier operand. */
AARCH64_OPND_BARRIER_DSB_NXS, /* Barrier operand for DSB nXS variant. */
diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h
index 06b1550e9a3..7ce6807c1f1 100644
--- a/opcodes/aarch64-tbl.h
+++ b/opcodes/aarch64-tbl.h
@@ -4218,6 +4218,7 @@ const struct aarch64_opcode aarch64_opcode_table[] =
CORE_INSN ("dc", 0xd5080000, 0xfff80000, ic_system, 0, OP2 (SYSREG_DC, Rt), QL_SRC_X, F_ALIAS),
CORE_INSN ("ic", 0xd5080000, 0xfff80000, ic_system, 0, OP2 (SYSREG_IC, Rt_SYS), QL_SRC_X, F_ALIAS | F_OPD1_OPT | F_DEFAULT (0x1F)),
CORE_INSN ("tlbi",0xd5080000, 0xfff80000, ic_system, 0, OP2 (SYSREG_TLBI, Rt_SYS), QL_SRC_X, F_ALIAS | F_OPD1_OPT | F_DEFAULT (0x1F)),
+ D128_INSN ("tlbip",0xd5480000, 0xfff80000, OP3 (SYSREG_TLBIP, Rt_SYS, PAIRREG_OR_XZR), QL_SRC_X2, F_ALIAS| F_OPD1_OPT | F_OPD_PAIR_OPT | F_DEFAULT (0x1f)),
V8_7A_INSN ("wfet", 0xd5031000, 0xffffffe0, ic_system, OP1 (Rd), QL_I1X, F_HAS_ALIAS),
V8_7A_INSN ("wfit", 0xd5031020, 0xffffffe0, ic_system, OP1 (Rd), QL_I1X, F_HAS_ALIAS),
PREDRES_INSN ("cfp", 0xd50b7380, 0xffffffe0, ic_system, OP2 (SYSREG_SR, Rt), QL_SRC_X, F_ALIAS),
@@ -6351,6 +6352,8 @@ const struct aarch64_opcode aarch64_opcode_table[] =
"an instruction cache maintenance operation specifier") \
Y(SYSTEM, sysins_op, "SYSREG_TLBI", 0, F(), \
"a TBL invalidation operation specifier") \
+ Y(SYSTEM, sysins_op, "SYSREG_TLBIP", 0, F(), \
+ "a 128-bit TBL invalidation operation specifier") \
Y(SYSTEM, sysins_op, "SYSREG_SR", 0, F(), \
"a Speculation Restriction option name (RCTX)") \
Y(SYSTEM, barrier, "BARRIER", 0, F(), \
--
2.42.0
^ permalink raw reply [flat|nested] 16+ messages in thread* [PATCH 09/12] aarch64: Add xs variants of tlbip operands
2024-01-03 1:17 [PATCH 00/12] aarch64: Add Armv9.4-A support for the d128 extension Victor Do Nascimento
` (7 preceding siblings ...)
2024-01-03 1:17 ` [PATCH 08/12] aarch64: Implement TLBIP 128-bit instruction Victor Do Nascimento
@ 2024-01-03 1:17 ` Victor Do Nascimento
2024-01-03 1:17 ` [PATCH 10/12] aarch64: Add TLBIP tests Victor Do Nascimento
` (3 subsequent siblings)
12 siblings, 0 replies; 16+ messages in thread
From: Victor Do Nascimento @ 2024-01-03 1:17 UTC (permalink / raw)
To: binutils; +Cc: richard.earnshaw, nickc, Victor Do Nascimento
The 2020 Architecture Extensions to the Arm A-profile architecture
added FEAT_XS, the XS attribute feature, giving cores the ability to
identify devices which can be subject to long response delays. TLB
invalidate (TLBI) operations and barriers can also be annotated with
this attribute[1].
With the introduction of the 128-bit translation tables with the
Armv8.9-a/Armv9.4-a Translation Hardening Extension, a series of new
TLB invalidate operations are introduced which make use of this
extension. These are added to aarch64_sys_regs_tlbi[] for use
with the `tlbip' insn.
[1] https://community.arm.com/arm-community-blogs/b/architectures-and-processors-blog/posts/arm-a-profile-architecture-developments-2020
---
opcodes/aarch64-opc.c | 124 ++++++++++++++++++++++++++++++++++++++++++
opcodes/aarch64-opc.h | 1 +
2 files changed, 125 insertions(+)
diff --git a/opcodes/aarch64-opc.c b/opcodes/aarch64-opc.c
index 38a377110de..4380c294ff8 100644
--- a/opcodes/aarch64-opc.c
+++ b/opcodes/aarch64-opc.c
@@ -4919,6 +4919,67 @@ const aarch64_sys_ins_reg aarch64_sys_regs_tlbi[] =
{ "paallos", CPENS (6, C8, C1, 4), 0},
{ "paall", CPENS (6, C8, C7, 4), 0},
+ { "vae1osnxs", CPENS (0, C9, C1, 1), F_HASXT | F_ARCHEXT },
+ { "vaae1osnxs", CPENS (0, C9, C1, 3), F_HASXT | F_ARCHEXT },
+ { "vale1osnxs", CPENS (0, C9, C1, 5), F_HASXT | F_ARCHEXT },
+ { "vaale1osnxs", CPENS (0, C9, C1, 7), F_HASXT | F_ARCHEXT },
+ { "rvae1isnxs", CPENS (0, C9, C2, 1), F_HASXT | F_ARCHEXT },
+ { "rvaae1isnxs", CPENS (0, C9, C2, 3), F_HASXT | F_ARCHEXT },
+ { "rvale1isnxs", CPENS (0, C9, C2, 5), F_HASXT | F_ARCHEXT },
+ { "rvaale1isnxs", CPENS (0, C9, C2, 7), F_HASXT | F_ARCHEXT },
+ { "vae1isnxs", CPENS (0, C9, C3, 1), F_HASXT },
+ { "vaae1isnxs", CPENS (0, C9, C3, 3), F_HASXT },
+ { "vale1isnxs", CPENS (0, C9, C3, 5), F_HASXT },
+ { "vaale1isnxs", CPENS (0, C9, C3, 7), F_HASXT },
+ { "rvae1osnxs", CPENS (0, C9, C5, 1), F_HASXT | F_ARCHEXT },
+ { "rvaae1osnxs", CPENS (0, C9, C5, 3), F_HASXT | F_ARCHEXT },
+ { "rvale1osnxs", CPENS (0, C9, C5, 5), F_HASXT | F_ARCHEXT },
+ { "rvaale1osnxs", CPENS (0, C9, C5, 7), F_HASXT | F_ARCHEXT },
+ { "rvae1nxs", CPENS (0, C9, C6, 1), F_HASXT | F_ARCHEXT },
+ { "rvaae1nxs", CPENS (0, C9, C6, 3), F_HASXT | F_ARCHEXT },
+ { "rvale1nxs", CPENS (0, C9, C6, 5), F_HASXT | F_ARCHEXT },
+ { "rvaale1nxs", CPENS (0, C9, C6, 7), F_HASXT | F_ARCHEXT },
+ { "vae1nxs", CPENS (0, C9, C7, 1), F_HASXT },
+ { "vaae1nxs", CPENS (0, C9, C7, 3), F_HASXT },
+ { "vale1nxs", CPENS (0, C9, C7, 5), F_HASXT },
+ { "vaale1nxs", CPENS (0, C9, C7, 7), F_HASXT },
+ { "ipas2e1isnxs", CPENS (4, C9, C0, 1), F_HASXT },
+ { "ripas2e1isnxs", CPENS (4, C9, C0, 2), F_HASXT | F_ARCHEXT },
+ { "ipas2le1isnxs", CPENS (4, C9, C0, 5), F_HASXT },
+ { "ripas2le1isnxs", CPENS (4, C9, C0, 6), F_HASXT | F_ARCHEXT },
+ { "vae2osnxs", CPENS (4, C9, C1, 1), F_HASXT | F_ARCHEXT },
+ { "vale2osnxs", CPENS (4, C9, C1, 5), F_HASXT | F_ARCHEXT },
+ { "rvae2isnxs", CPENS (4, C9, C2, 1), F_HASXT | F_ARCHEXT },
+ { "rvale2isnxs", CPENS (4, C9, C2, 5), F_HASXT | F_ARCHEXT },
+ { "vae2isnxs", CPENS (4, C9, C3, 1), F_HASXT },
+ { "vale2isnxs", CPENS (4, C9, C3, 5), F_HASXT },
+ { "ipas2e1osnxs", CPENS (4, C9, C4, 0), F_HASXT | F_ARCHEXT },
+ { "ipas2e1nxs", CPENS (4, C9, C4, 1), F_HASXT },
+ { "ripas2e1nxs", CPENS (4, C9, C4, 2), F_HASXT | F_ARCHEXT },
+ { "ripas2e1osnxs", CPENS (4, C9, C4, 3), F_HASXT | F_ARCHEXT },
+ { "ipas2le1osnxs", CPENS (4, C9, C4, 4), F_HASXT | F_ARCHEXT },
+ { "ipas2le1nxs", CPENS (4, C9, C4, 5), F_HASXT },
+ { "ripas2le1nxs", CPENS (4, C9, C4, 6), F_HASXT | F_ARCHEXT },
+ { "ripas2le1osnxs", CPENS (4, C9, C4, 7), F_HASXT | F_ARCHEXT },
+ { "rvae2osnxs", CPENS (4, C9, C5, 1), F_HASXT | F_ARCHEXT },
+ { "rvale2osnxs", CPENS (4, C9, C5, 5), F_HASXT | F_ARCHEXT },
+ { "rvae2nxs", CPENS (4, C9, C6, 1), F_HASXT | F_ARCHEXT },
+ { "rvale2nxs", CPENS (4, C9, C6, 5), F_HASXT | F_ARCHEXT },
+ { "vae2nxs", CPENS (4, C9, C7, 1), F_HASXT },
+ { "vale2nxs", CPENS (4, C9, C7, 5), F_HASXT },
+ { "vae3osnxs", CPENS (6, C9, C1, 1), F_HASXT | F_ARCHEXT },
+ { "vale3osnxs", CPENS (6, C9, C1, 5), F_HASXT | F_ARCHEXT },
+ { "rvae3isnxs", CPENS (6, C9, C2, 1), F_HASXT | F_ARCHEXT },
+ { "rvale3isnxs", CPENS (6, C9, C2, 5), F_HASXT | F_ARCHEXT },
+ { "vae3isnxs", CPENS (6, C9, C3, 1), F_HASXT },
+ { "vale3isnxs", CPENS (6, C9, C3, 5), F_HASXT },
+ { "rvae3osnxs", CPENS (6, C9, C5, 1), F_HASXT | F_ARCHEXT },
+ { "rvale3osnxs", CPENS (6, C9, C5, 5), F_HASXT | F_ARCHEXT },
+ { "rvae3nxs", CPENS (6, C9, C6, 1), F_HASXT | F_ARCHEXT },
+ { "rvale3nxs", CPENS (6, C9, C6, 5), F_HASXT | F_ARCHEXT },
+ { "vae3nxs", CPENS (6, C9, C7, 1), F_HASXT },
+ { "vale3nxs", CPENS (6, C9, C7, 5), F_HASXT },
+
{ 0, CPENS(0,0,0,0), 0 }
};
@@ -5043,6 +5104,69 @@ aarch64_sys_ins_reg_supported_p (const aarch64_feature_set features,
&& AARCH64_CPU_HAS_FEATURE (features, MEMTAG))
return true;
+ if ((reg_value == CPENS (0, C9, C1, 1)
+ || reg_value == CPENS (0, C9, C1, 3)
+ || reg_value == CPENS (0, C9, C1, 5)
+ || reg_value == CPENS (0, C9, C1, 7)
+ || reg_value == CPENS (0, C9, C2, 1)
+ || reg_value == CPENS (0, C9, C2, 3)
+ || reg_value == CPENS (0, C9, C2, 5)
+ || reg_value == CPENS (0, C9, C2, 7)
+ || reg_value == CPENS (0, C9, C3, 1)
+ || reg_value == CPENS (0, C9, C3, 3)
+ || reg_value == CPENS (0, C9, C3, 5)
+ || reg_value == CPENS (0, C9, C3, 7)
+ || reg_value == CPENS (0, C9, C5, 1)
+ || reg_value == CPENS (0, C9, C5, 3)
+ || reg_value == CPENS (0, C9, C5, 5)
+ || reg_value == CPENS (0, C9, C5, 7)
+ || reg_value == CPENS (0, C9, C6, 1)
+ || reg_value == CPENS (0, C9, C6, 3)
+ || reg_value == CPENS (0, C9, C6, 5)
+ || reg_value == CPENS (0, C9, C6, 7)
+ || reg_value == CPENS (0, C9, C7, 1)
+ || reg_value == CPENS (0, C9, C7, 3)
+ || reg_value == CPENS (0, C9, C7, 5)
+ || reg_value == CPENS (0, C9, C7, 7)
+ || reg_value == CPENS (4, C9, C0, 1)
+ || reg_value == CPENS (4, C9, C0, 2)
+ || reg_value == CPENS (4, C9, C0, 5)
+ || reg_value == CPENS (4, C9, C0, 6)
+ || reg_value == CPENS (4, C9, C1, 1)
+ || reg_value == CPENS (4, C9, C1, 5)
+ || reg_value == CPENS (4, C9, C2, 1)
+ || reg_value == CPENS (4, C9, C2, 5)
+ || reg_value == CPENS (4, C9, C3, 1)
+ || reg_value == CPENS (4, C9, C3, 5)
+ || reg_value == CPENS (4, C9, C4, 0)
+ || reg_value == CPENS (4, C9, C4, 1)
+ || reg_value == CPENS (4, C9, C4, 2)
+ || reg_value == CPENS (4, C9, C4, 3)
+ || reg_value == CPENS (4, C9, C4, 4)
+ || reg_value == CPENS (4, C9, C4, 5)
+ || reg_value == CPENS (4, C9, C4, 6)
+ || reg_value == CPENS (4, C9, C4, 7)
+ || reg_value == CPENS (4, C9, C5, 1)
+ || reg_value == CPENS (4, C9, C5, 5)
+ || reg_value == CPENS (4, C9, C6, 1)
+ || reg_value == CPENS (4, C9, C6, 5)
+ || reg_value == CPENS (4, C9, C7, 1)
+ || reg_value == CPENS (4, C9, C7, 5)
+ || reg_value == CPENS (6, C9, C1, 1)
+ || reg_value == CPENS (6, C9, C1, 5)
+ || reg_value == CPENS (6, C9, C2, 1)
+ || reg_value == CPENS (6, C9, C2, 5)
+ || reg_value == CPENS (6, C9, C3, 1)
+ || reg_value == CPENS (6, C9, C3, 5)
+ || reg_value == CPENS (6, C9, C5, 1)
+ || reg_value == CPENS (6, C9, C5, 5)
+ || reg_value == CPENS (6, C9, C6, 1)
+ || reg_value == CPENS (6, C9, C6, 5)
+ || reg_value == CPENS (6, C9, C7, 1)
+ || reg_value == CPENS (6, C9, C7, 5))
+ && AARCH64_CPU_HAS_FEATURE (features, D128))
+ return true;
+
/* AT S1E1RP, AT S1E1WP. Values are from aarch64_sys_regs_at. */
if ((reg_value == CPENS (0, C7, C9, 0)
|| reg_value == CPENS (0, C7, C9, 1))
diff --git a/opcodes/aarch64-opc.h b/opcodes/aarch64-opc.h
index cf217e86376..fde0a2e2c12 100644
--- a/opcodes/aarch64-opc.h
+++ b/opcodes/aarch64-opc.h
@@ -300,6 +300,7 @@ verify_constraints (const struct aarch64_inst *, const aarch64_insn, bfd_vma,
#undef F_REG_128
#define F_REG_128 (1 << 7) /* System regsister implementable as 128-bit wide. */
+
/* PSTATE field name for the MSR instruction this is encoded in "op1:op2:CRm".
Part of CRm can be used to encode <pstatefield>. E.g. CRm[3:1] for SME.
In order to set/get full PSTATE field name use flag F_REG_IN_CRM and below
--
2.42.0
^ permalink raw reply [flat|nested] 16+ messages in thread* [PATCH 10/12] aarch64: Add TLBIP tests
2024-01-03 1:17 [PATCH 00/12] aarch64: Add Armv9.4-A support for the d128 extension Victor Do Nascimento
` (8 preceding siblings ...)
2024-01-03 1:17 ` [PATCH 09/12] aarch64: Add xs variants of tlbip operands Victor Do Nascimento
@ 2024-01-03 1:17 ` Victor Do Nascimento
2024-01-03 1:17 ` [PATCH 11/12] aarch64: Add support for 128-bit system register mrrs and msrr insns Victor Do Nascimento
` (2 subsequent siblings)
12 siblings, 0 replies; 16+ messages in thread
From: Victor Do Nascimento @ 2024-01-03 1:17 UTC (permalink / raw)
To: binutils; +Cc: richard.earnshaw, nickc, Victor Do Nascimento
---
gas/testsuite/gas/aarch64/tlbip.d | 127 ++++++++++++++++++++++++++++
gas/testsuite/gas/aarch64/tlbip.s | 132 ++++++++++++++++++++++++++++++
2 files changed, 259 insertions(+)
create mode 100644 gas/testsuite/gas/aarch64/tlbip.d
create mode 100644 gas/testsuite/gas/aarch64/tlbip.s
diff --git a/gas/testsuite/gas/aarch64/tlbip.d b/gas/testsuite/gas/aarch64/tlbip.d
new file mode 100644
index 00000000000..81c22cf8e20
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/tlbip.d
@@ -0,0 +1,127 @@
+#objdump: -dr
+
+.*: file format .*
+
+Disassembly of section \.text:
+
+0+ <.*>:
+ 0: d5488120 sysp #0, C8, C1, #1, x0, x1
+ 4: d5488160 sysp #0, C8, C1, #3, x0, x1
+ 8: d54881a0 sysp #0, C8, C1, #5, x0, x1
+ c: d54881e0 sysp #0, C8, C1, #7, x0, x1
+ 10: d5488220 sysp #0, C8, C2, #1, x0, x1
+ 14: d5488260 sysp #0, C8, C2, #3, x0, x1
+ 18: d54882a0 sysp #0, C8, C2, #5, x0, x1
+ 1c: d54882e0 sysp #0, C8, C2, #7, x0, x1
+ 20: d5488320 sysp #0, C8, C3, #1, x0, x1
+ 24: d5488360 sysp #0, C8, C3, #3, x0, x1
+ 28: d54883a0 sysp #0, C8, C3, #5, x0, x1
+ 2c: d54883e0 sysp #0, C8, C3, #7, x0, x1
+ 30: d5488520 sysp #0, C8, C5, #1, x0, x1
+ 34: d5488560 sysp #0, C8, C5, #3, x0, x1
+ 38: d54885a0 sysp #0, C8, C5, #5, x0, x1
+ 3c: d54885e0 sysp #0, C8, C5, #7, x0, x1
+ 40: d5488620 sysp #0, C8, C6, #1, x0, x1
+ 44: d5488660 sysp #0, C8, C6, #3, x0, x1
+ 48: d54886a0 sysp #0, C8, C6, #5, x0, x1
+ 4c: d54886e0 sysp #0, C8, C6, #7, x0, x1
+ 50: d5488720 sysp #0, C8, C7, #1, x0, x1
+ 54: d5488760 sysp #0, C8, C7, #3, x0, x1
+ 58: d54887a0 sysp #0, C8, C7, #5, x0, x1
+ 5c: d54887e0 sysp #0, C8, C7, #7, x0, x1
+ 60: d5489120 sysp #0, C9, C1, #1, x0, x1
+ 64: d5489160 sysp #0, C9, C1, #3, x0, x1
+ 68: d54891a0 sysp #0, C9, C1, #5, x0, x1
+ 6c: d54891e0 sysp #0, C9, C1, #7, x0, x1
+ 70: d5489220 sysp #0, C9, C2, #1, x0, x1
+ 74: d5489260 sysp #0, C9, C2, #3, x0, x1
+ 78: d54892a0 sysp #0, C9, C2, #5, x0, x1
+ 7c: d54892e0 sysp #0, C9, C2, #7, x0, x1
+ 80: d5489320 sysp #0, C9, C3, #1, x0, x1
+ 84: d5489360 sysp #0, C9, C3, #3, x0, x1
+ 88: d54893a0 sysp #0, C9, C3, #5, x0, x1
+ 8c: d54893e0 sysp #0, C9, C3, #7, x0, x1
+ 90: d5489520 sysp #0, C9, C5, #1, x0, x1
+ 94: d5489560 sysp #0, C9, C5, #3, x0, x1
+ 98: d54895a0 sysp #0, C9, C5, #5, x0, x1
+ 9c: d54895e0 sysp #0, C9, C5, #7, x0, x1
+ a0: d5489620 sysp #0, C9, C6, #1, x0, x1
+ a4: d5489660 sysp #0, C9, C6, #3, x0, x1
+ a8: d54896a0 sysp #0, C9, C6, #5, x0, x1
+ ac: d54896e0 sysp #0, C9, C6, #7, x0, x1
+ b0: d5489720 sysp #0, C9, C7, #1, x0, x1
+ b4: d5489760 sysp #0, C9, C7, #3, x0, x1
+ b8: d54897a0 sysp #0, C9, C7, #5, x0, x1
+ bc: d54897e0 sysp #0, C9, C7, #7, x0, x1
+ c0: d54c8020 sysp #4, C8, C0, #1, x0, x1
+ c4: d54c8040 sysp #4, C8, C0, #2, x0, x1
+ c8: d54c80a0 sysp #4, C8, C0, #5, x0, x1
+ cc: d54c80c0 sysp #4, C8, C0, #6, x0, x1
+ d0: d54c8120 sysp #4, C8, C1, #1, x0, x1
+ d4: d54c81a0 sysp #4, C8, C1, #5, x0, x1
+ d8: d54c8220 sysp #4, C8, C2, #1, x0, x1
+ dc: d54c82a0 sysp #4, C8, C2, #5, x0, x1
+ e0: d54c8320 sysp #4, C8, C3, #1, x0, x1
+ e4: d54c83a0 sysp #4, C8, C3, #5, x0, x1
+ e8: d54c8400 sysp #4, C8, C4, #0, x0, x1
+ ec: d54c8420 sysp #4, C8, C4, #1, x0, x1
+ f0: d54c8440 sysp #4, C8, C4, #2, x0, x1
+ f4: d54c8460 sysp #4, C8, C4, #3, x0, x1
+ f8: d54c8480 sysp #4, C8, C4, #4, x0, x1
+ fc: d54c84a0 sysp #4, C8, C4, #5, x0, x1
+ 100: d54c84c0 sysp #4, C8, C4, #6, x0, x1
+ 104: d54c84e0 sysp #4, C8, C4, #7, x0, x1
+ 108: d54c8520 sysp #4, C8, C5, #1, x0, x1
+ 10c: d54c85a0 sysp #4, C8, C5, #5, x0, x1
+ 110: d54c8620 sysp #4, C8, C6, #1, x0, x1
+ 114: d54c86a0 sysp #4, C8, C6, #5, x0, x1
+ 118: d54c8720 sysp #4, C8, C7, #1, x0, x1
+ 11c: d54c87a0 sysp #4, C8, C7, #5, x0, x1
+ 120: d54c9020 sysp #4, C9, C0, #1, x0, x1
+ 124: d54c9040 sysp #4, C9, C0, #2, x0, x1
+ 128: d54c90a0 sysp #4, C9, C0, #5, x0, x1
+ 12c: d54c90c0 sysp #4, C9, C0, #6, x0, x1
+ 130: d54c9120 sysp #4, C9, C1, #1, x0, x1
+ 134: d54c91a0 sysp #4, C9, C1, #5, x0, x1
+ 138: d54c9220 sysp #4, C9, C2, #1, x0, x1
+ 13c: d54c92a0 sysp #4, C9, C2, #5, x0, x1
+ 140: d54c9320 sysp #4, C9, C3, #1, x0, x1
+ 144: d54c93a0 sysp #4, C9, C3, #5, x0, x1
+ 148: d54c9400 sysp #4, C9, C4, #0, x0, x1
+ 14c: d54c9420 sysp #4, C9, C4, #1, x0, x1
+ 150: d54c9440 sysp #4, C9, C4, #2, x0, x1
+ 154: d54c9460 sysp #4, C9, C4, #3, x0, x1
+ 158: d54c9480 sysp #4, C9, C4, #4, x0, x1
+ 15c: d54c94a0 sysp #4, C9, C4, #5, x0, x1
+ 160: d54c94c0 sysp #4, C9, C4, #6, x0, x1
+ 164: d54c94e0 sysp #4, C9, C4, #7, x0, x1
+ 168: d54c9520 sysp #4, C9, C5, #1, x0, x1
+ 16c: d54c95a0 sysp #4, C9, C5, #5, x0, x1
+ 170: d54c9620 sysp #4, C9, C6, #1, x0, x1
+ 174: d54c96a0 sysp #4, C9, C6, #5, x0, x1
+ 178: d54c9720 sysp #4, C9, C7, #1, x0, x1
+ 17c: d54c97a0 sysp #4, C9, C7, #5, x0, x1
+ 180: d54e8120 sysp #6, C8, C1, #1, x0, x1
+ 184: d54e81a0 sysp #6, C8, C1, #5, x0, x1
+ 188: d54e8220 sysp #6, C8, C2, #1, x0, x1
+ 18c: d54e82a0 sysp #6, C8, C2, #5, x0, x1
+ 190: d54e8320 sysp #6, C8, C3, #1, x0, x1
+ 194: d54e83a0 sysp #6, C8, C3, #5, x0, x1
+ 198: d54e8520 sysp #6, C8, C5, #1, x0, x1
+ 19c: d54e85a0 sysp #6, C8, C5, #5, x0, x1
+ 1a0: d54e8620 sysp #6, C8, C6, #1, x0, x1
+ 1a4: d54e86a0 sysp #6, C8, C6, #5, x0, x1
+ 1a8: d54e8720 sysp #6, C8, C7, #1, x0, x1
+ 1ac: d54e87a0 sysp #6, C8, C7, #5, x0, x1
+ 1b0: d54e9120 sysp #6, C9, C1, #1, x0, x1
+ 1b4: d54e91a0 sysp #6, C9, C1, #5, x0, x1
+ 1b8: d54e9220 sysp #6, C9, C2, #1, x0, x1
+ 1bc: d54e92a0 sysp #6, C9, C2, #5, x0, x1
+ 1c0: d54e9320 sysp #6, C9, C3, #1, x0, x1
+ 1c4: d54e93a0 sysp #6, C9, C3, #5, x0, x1
+ 1c8: d54e9520 sysp #6, C9, C5, #1, x0, x1
+ 1cc: d54e95a0 sysp #6, C9, C5, #5, x0, x1
+ 1d0: d54e9620 sysp #6, C9, C6, #1, x0, x1
+ 1d4: d54e96a0 sysp #6, C9, C6, #5, x0, x1
+ 1d8: d54e9720 sysp #6, C9, C7, #1, x0, x1
+ 1dc: d54e97a0 sysp #6, C9, C7, #5, x0, x1
\ No newline at end of file
diff --git a/gas/testsuite/gas/aarch64/tlbip.s b/gas/testsuite/gas/aarch64/tlbip.s
new file mode 100644
index 00000000000..52148d9fc45
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/tlbip.s
@@ -0,0 +1,132 @@
+ // Test file for AArch64 GAS -- TLB invalidation instructions.
+
+ .macro tlbip_m op expl
+ .ifc \expl, 1
+ tlbip \op, x0, x1
+ .else
+ tlbip \op
+ .endif
+ .endm
+
+ .arch armv9.4-a+d128
+
+ tlbip_m vae1os 1
+ tlbip_m vaae1os 1
+ tlbip_m vale1os 1
+ tlbip_m vaale1os 1
+ tlbip_m rvae1is 1
+ tlbip_m rvaae1is 1
+ tlbip_m rvale1is 1
+ tlbip_m rvaale1is 1
+ tlbip_m vae1is 1
+ tlbip_m vaae1is 1
+ tlbip_m vale1is 1
+ tlbip_m vaale1is 1
+ tlbip_m rvae1os 1
+ tlbip_m rvaae1os 1
+ tlbip_m rvale1os 1
+ tlbip_m rvaale1os 1
+ tlbip_m rvae1 1
+ tlbip_m rvaae1 1
+ tlbip_m rvale1 1
+ tlbip_m rvaale1 1
+ tlbip_m vae1 1
+ tlbip_m vaae1 1
+ tlbip_m vale1 1
+ tlbip_m vaale1 1
+ tlbip_m vae1osnxs 1
+ tlbip_m vaae1osnxs 1
+ tlbip_m vale1osnxs 1
+ tlbip_m vaale1osnxs 1
+ tlbip_m rvae1isnxs 1
+ tlbip_m rvaae1isnxs 1
+ tlbip_m rvale1isnxs 1
+ tlbip_m rvaale1isnxs 1
+ tlbip_m vae1isnxs 1
+ tlbip_m vaae1isnxs 1
+ tlbip_m vale1isnxs 1
+ tlbip_m vaale1isnxs 1
+ tlbip_m rvae1osnxs 1
+ tlbip_m rvaae1osnxs 1
+ tlbip_m rvale1osnxs 1
+ tlbip_m rvaale1osnxs 1
+ tlbip_m rvae1nxs 1
+ tlbip_m rvaae1nxs 1
+ tlbip_m rvale1nxs 1
+ tlbip_m rvaale1nxs 1
+ tlbip_m vae1nxs 1
+ tlbip_m vaae1nxs 1
+ tlbip_m vale1nxs 1
+ tlbip_m vaale1nxs 1
+ tlbip_m ipas2e1is 1
+ tlbip_m ripas2e1is 1
+ tlbip_m ipas2le1is 1
+ tlbip_m ripas2le1is 1
+ tlbip_m vae2os 1
+ tlbip_m vale2os 1
+ tlbip_m rvae2is 1
+ tlbip_m rvale2is 1
+ tlbip_m vae2is 1
+ tlbip_m vale2is 1
+ tlbip_m ipas2e1os 1
+ tlbip_m ipas2e1 1
+ tlbip_m ripas2e1 1
+ tlbip_m ripas2e1os 1
+ tlbip_m ipas2le1os 1
+ tlbip_m ipas2le1 1
+ tlbip_m ripas2le1 1
+ tlbip_m ripas2le1os 1
+ tlbip_m rvae2os 1
+ tlbip_m rvale2os 1
+ tlbip_m rvae2 1
+ tlbip_m rvale2 1
+ tlbip_m vae2 1
+ tlbip_m vale2 1
+ tlbip_m ipas2e1isnxs 1
+ tlbip_m ripas2e1isnxs 1
+ tlbip_m ipas2le1isnxs 1
+ tlbip_m ripas2le1isnxs 1
+ tlbip_m vae2osnxs 1
+ tlbip_m vale2osnxs 1
+ tlbip_m rvae2isnxs 1
+ tlbip_m rvale2isnxs 1
+ tlbip_m vae2isnxs 1
+ tlbip_m vale2isnxs 1
+ tlbip_m ipas2e1osnxs 1
+ tlbip_m ipas2e1nxs 1
+ tlbip_m ripas2e1nxs 1
+ tlbip_m ripas2e1osnxs 1
+ tlbip_m ipas2le1osnxs 1
+ tlbip_m ipas2le1nxs 1
+ tlbip_m ripas2le1nxs 1
+ tlbip_m ripas2le1osnxs 1
+ tlbip_m rvae2osnxs 1
+ tlbip_m rvale2osnxs 1
+ tlbip_m rvae2nxs 1
+ tlbip_m rvale2nxs 1
+ tlbip_m vae2nxs 1
+ tlbip_m vale2nxs 1
+ tlbip_m vae3os 1
+ tlbip_m vale3os 1
+ tlbip_m rvae3is 1
+ tlbip_m rvale3is 1
+ tlbip_m vae3is 1
+ tlbip_m vale3is 1
+ tlbip_m rvae3os 1
+ tlbip_m rvale3os 1
+ tlbip_m rvae3 1
+ tlbip_m rvale3 1
+ tlbip_m vae3 1
+ tlbip_m vale3 1
+ tlbip_m vae3osnxs 1
+ tlbip_m vale3osnxs 1
+ tlbip_m rvae3isnxs 1
+ tlbip_m rvale3isnxs 1
+ tlbip_m vae3isnxs 1
+ tlbip_m vale3isnxs 1
+ tlbip_m rvae3osnxs 1
+ tlbip_m rvale3osnxs 1
+ tlbip_m rvae3nxs 1
+ tlbip_m rvale3nxs 1
+ tlbip_m vae3nxs 1
+ tlbip_m vale3nxs 1
--
2.42.0
^ permalink raw reply [flat|nested] 16+ messages in thread* [PATCH 11/12] aarch64: Add support for 128-bit system register mrrs and msrr insns
2024-01-03 1:17 [PATCH 00/12] aarch64: Add Armv9.4-A support for the d128 extension Victor Do Nascimento
` (9 preceding siblings ...)
2024-01-03 1:17 ` [PATCH 10/12] aarch64: Add TLBIP tests Victor Do Nascimento
@ 2024-01-03 1:17 ` Victor Do Nascimento
2024-01-03 1:17 ` [PATCH 12/12] arch64: Add optional operand register pair support tests Victor Do Nascimento
2024-01-05 16:10 ` [PATCH 00/12] aarch64: Add Armv9.4-A support for the d128 extension Nick Clifton
12 siblings, 0 replies; 16+ messages in thread
From: Victor Do Nascimento @ 2024-01-03 1:17 UTC (permalink / raw)
To: binutils; +Cc: richard.earnshaw, nickc, Victor Do Nascimento
With the addition of 128-bit system registers to the Arm architecture
starting with Armv9.4-a, a mechanism for manipulating their contents
is introduced with the `msrr' and `mrrs' instruction pair.
These move values from one such 128-bit system register into a pair of
contiguous general-purpose registers and vice-versa, as for example:
msrr ttlb0_el1, x0, x1
mrrs x0, x1, ttlb0_el1
This patch adds the necessary support for these instructions, adding
checks for system-register width by defining a new operand type in the
form of `AARCH64_OPND_SYSREG128' and the `aarch64_sys_reg_128bit_p'
predicate, responsible for checking whether the requested system
register table entry is marked as implemented in the 128-bit mode via
the F_REG_128 flag.
---
gas/config/tc-aarch64.c | 13 ++++++---
gas/testsuite/gas/aarch64/illegal-sysreg128.d | 2 ++
gas/testsuite/gas/aarch64/illegal-sysreg128.l | 11 ++++++++
gas/testsuite/gas/aarch64/illegal-sysreg128.s | 8 ++++++
gas/testsuite/gas/aarch64/sysreg128.d | 28 +++++++++++++++++++
gas/testsuite/gas/aarch64/sysreg128.s | 17 +++++++++++
include/opcode/aarch64.h | 2 ++
opcodes/aarch64-dis.c | 1 +
opcodes/aarch64-opc.c | 9 +++++-
opcodes/aarch64-tbl.h | 3 ++
10 files changed, 89 insertions(+), 5 deletions(-)
create mode 100644 gas/testsuite/gas/aarch64/illegal-sysreg128.d
create mode 100644 gas/testsuite/gas/aarch64/illegal-sysreg128.l
create mode 100644 gas/testsuite/gas/aarch64/illegal-sysreg128.s
create mode 100644 gas/testsuite/gas/aarch64/sysreg128.d
create mode 100644 gas/testsuite/gas/aarch64/sysreg128.s
diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c
index 95661445f0c..d1c64c64fc6 100644
--- a/gas/config/tc-aarch64.c
+++ b/gas/config/tc-aarch64.c
@@ -4799,7 +4799,7 @@ parse_sme_sm_za (char **str)
static int
parse_sys_reg (char **str, htab_t sys_regs,
int imple_defined_p, int pstatefield_p,
- uint32_t* flags)
+ uint32_t* flags, bool sysreg128_p)
{
char *p, *q;
char buf[AARCH64_MAX_SYSREG_NAME_LEN];
@@ -4849,6 +4849,9 @@ parse_sys_reg (char **str, htab_t sys_regs,
&o->features))
as_bad (_("selected processor does not support system register "
"name '%s'"), buf);
+ if (sysreg128_p && !aarch64_sys_reg_128bit_p (o->flags))
+ as_bad (_("128-bit-wide accsess not allowed on selected system"
+ " register '%s'"), buf);
if (aarch64_sys_reg_deprecated_p (o->flags))
as_warn (_("system register name '%s' is deprecated and may be "
"removed in a future release"), buf);
@@ -7627,12 +7630,14 @@ parse_operands (char *str, const aarch64_opcode *opcode)
}
info->qualifier = base_qualifier;
goto regoff_addr;
-
case AARCH64_OPND_SYSREG:
+ case AARCH64_OPND_SYSREG128:
{
+ bool sysreg128_p = operands[i] == AARCH64_OPND_SYSREG128;
uint32_t sysreg_flags;
if ((val = parse_sys_reg (&str, aarch64_sys_regs_hsh, 1, 0,
- &sysreg_flags)) == PARSE_FAIL)
+ &sysreg_flags,
+ sysreg128_p)) == PARSE_FAIL)
{
set_syntax_error (_("unknown or missing system register name"));
goto failure;
@@ -7646,7 +7651,7 @@ parse_operands (char *str, const aarch64_opcode *opcode)
{
uint32_t sysreg_flags;
if ((val = parse_sys_reg (&str, aarch64_pstatefield_hsh, 0, 1,
- &sysreg_flags)) == PARSE_FAIL)
+ &sysreg_flags, false)) == PARSE_FAIL)
{
set_syntax_error (_("unknown or missing PSTATE field name"));
goto failure;
diff --git a/gas/testsuite/gas/aarch64/illegal-sysreg128.d b/gas/testsuite/gas/aarch64/illegal-sysreg128.d
new file mode 100644
index 00000000000..05bafecd0a0
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/illegal-sysreg128.d
@@ -0,0 +1,2 @@
+#name: Instruction validation testing for mrrs and msrr.
+#error_output: illegal-sysreg128.l
diff --git a/gas/testsuite/gas/aarch64/illegal-sysreg128.l b/gas/testsuite/gas/aarch64/illegal-sysreg128.l
new file mode 100644
index 00000000000..a7d06b762a5
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/illegal-sysreg128.l
@@ -0,0 +1,11 @@
+.*: Assembler messages:
+.*: Error: 128-bit-wide accsess not allowed on selected system register 'accdata_el1'
+.*: Error: 128-bit-wide accsess not allowed on selected system register 'accdata_el1'
+.*: Error: operand mismatch -- `mrrs w0,w1,ttbr0_el1'
+.*: Info: did you mean this\?
+.*: Info: mrrs x0, x1, ttbr0_el1
+.*: Error: operand mismatch -- `msrr ttbr0_el1,w0,w1'
+.*: Info: did you mean this\?
+.*: Info: msrr ttbr0_el1, x0, x1
+.*: Error: reg pair must be contiguous at operand 2 -- `mrrs x0,x2,ttbr0_el1'
+.*: Error: reg pair must be contiguous at operand 3 -- `msrr ttbr0_el1,x0,x2'
diff --git a/gas/testsuite/gas/aarch64/illegal-sysreg128.s b/gas/testsuite/gas/aarch64/illegal-sysreg128.s
new file mode 100644
index 00000000000..90dcfefe5dd
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/illegal-sysreg128.s
@@ -0,0 +1,8 @@
+ .arch armv8.1-a+d128
+
+ mrrs x0, x1, accdata_el1
+ msrr accdata_el1, x0, x1
+ mrrs w0, w1, ttbr0_el1
+ msrr ttbr0_el1, w0, w1
+ mrrs x0, x2, ttbr0_el1
+ msrr ttbr0_el1, x0, x2
diff --git a/gas/testsuite/gas/aarch64/sysreg128.d b/gas/testsuite/gas/aarch64/sysreg128.d
new file mode 100644
index 00000000000..8c9f7ca14d1
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sysreg128.d
@@ -0,0 +1,28 @@
+#objdump: -dr
+
+.*
+
+
+Disassembly of section \.text:
+
+0+ <\.text>:
+[^:]*: d5787402 mrrs x2, x3, par_el1
+[^:]*: d5587404 msrr par_el1, x4, x5
+[^:]*: d578d0c2 mrrs x2, x3, rcwmask_el1
+[^:]*: d558d0c4 msrr rcwmask_el1, x4, x5
+[^:]*: d578d062 mrrs x2, x3, rcwsmask_el1
+[^:]*: d558d064 msrr rcwsmask_el1, x4, x5
+[^:]*: d5782002 mrrs x2, x3, ttbr0_el1
+[^:]*: d5582004 msrr ttbr0_el1, x4, x5
+[^:]*: d57d2002 mrrs x2, x3, ttbr0_el12
+[^:]*: d55d2004 msrr ttbr0_el12, x4, x5
+[^:]*: d57c2002 mrrs x2, x3, ttbr0_el2
+[^:]*: d55c2004 msrr ttbr0_el2, x4, x5
+[^:]*: d5782022 mrrs x2, x3, ttbr1_el1
+[^:]*: d5582024 msrr ttbr1_el1, x4, x5
+[^:]*: d57d2022 mrrs x2, x3, ttbr1_el12
+[^:]*: d55d2024 msrr ttbr1_el12, x4, x5
+[^:]*: d57c2022 mrrs x2, x3, ttbr1_el2
+[^:]*: d55c2024 msrr ttbr1_el2, x4, x5
+[^:]*: d57c2102 mrrs x2, x3, vttbr_el2
+[^:]*: d55c2104 msrr vttbr_el2, x4, x5
\ No newline at end of file
diff --git a/gas/testsuite/gas/aarch64/sysreg128.s b/gas/testsuite/gas/aarch64/sysreg128.s
new file mode 100644
index 00000000000..4093315973d
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sysreg128.s
@@ -0,0 +1,17 @@
+ .arch armv9.4-a+d128+the
+
+ .macro rwreg128, name
+ mrrs x2, x3, \name
+ msrr \name, x4, x5
+ .endm
+
+ rwreg128 par_el1
+ rwreg128 rcwmask_el1
+ rwreg128 rcwsmask_el1
+ rwreg128 ttbr0_el1
+ rwreg128 ttbr0_el12
+ rwreg128 ttbr0_el2
+ rwreg128 ttbr1_el1
+ rwreg128 ttbr1_el12
+ rwreg128 ttbr1_el2
+ rwreg128 vttbr_el2
diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h
index 55d584d16eb..351477870b6 100644
--- a/include/opcode/aarch64.h
+++ b/include/opcode/aarch64.h
@@ -561,6 +561,7 @@ enum aarch64_opnd
AARCH64_OPND_SIMD_ADDR_POST, /* Address of ld/st multiple post-indexed. */
AARCH64_OPND_SYSREG, /* System register operand. */
+ AARCH64_OPND_SYSREG128, /* 128-bit system register operand. */
AARCH64_OPND_PSTATEFIELD, /* PSTATE field name operand. */
AARCH64_OPND_SYSREG_AT, /* System register <at_op> operand. */
AARCH64_OPND_SYSREG_DC, /* System register <dc_op> operand. */
@@ -1328,6 +1329,7 @@ typedef struct
extern const aarch64_sys_reg aarch64_sys_regs [];
extern const aarch64_sys_reg aarch64_pstatefields [];
extern bool aarch64_sys_reg_deprecated_p (const uint32_t);
+extern bool aarch64_sys_reg_128bit_p (const uint32_t);
extern bool aarch64_sys_reg_alias_p (const uint32_t);
extern bool aarch64_pstatefield_supported_p (const aarch64_feature_set,
const aarch64_sys_reg *);
diff --git a/opcodes/aarch64-dis.c b/opcodes/aarch64-dis.c
index 32831e855cd..be4c7f1dcdb 100644
--- a/opcodes/aarch64-dis.c
+++ b/opcodes/aarch64-dis.c
@@ -302,6 +302,7 @@ aarch64_ext_regno_pair (const aarch64_operand *self ATTRIBUTE_UNUSED, aarch64_op
aarch64_operand_error *errors ATTRIBUTE_UNUSED)
{
assert (info->idx == 1
+ || info->idx == 2
|| info->idx == 3
|| info->idx == 5);
diff --git a/opcodes/aarch64-opc.c b/opcodes/aarch64-opc.c
index 4380c294ff8..209fbb2c9c7 100644
--- a/opcodes/aarch64-opc.c
+++ b/opcodes/aarch64-opc.c
@@ -1710,7 +1710,7 @@ operand_general_constraint_met_p (const aarch64_opnd_info *opnds, int idx,
else if (type == AARCH64_OPND_PAIRREG
|| type == AARCH64_OPND_PAIRREG_OR_XZR)
{
- assert (idx == 1 || idx == 3 || idx == 5);
+ assert (idx == 1 || idx == 2 || idx == 3 || idx == 5);
if (opnds[idx - 1].reg.regno % 2 != 0)
{
set_syntax_error (mismatch_detail, idx - 1,
@@ -4514,6 +4514,7 @@ aarch64_print_operand (char *buf, size_t size, bfd_vma pc,
break;
case AARCH64_OPND_SYSREG:
+ case AARCH64_OPND_SYSREG128:
for (i = 0; aarch64_sys_regs[i].name; ++i)
{
const aarch64_sys_reg *sr = aarch64_sys_regs + i;
@@ -4723,6 +4724,12 @@ aarch64_sys_reg_deprecated_p (const uint32_t reg_flags)
return (reg_flags & F_DEPRECATED) != 0;
}
+bool
+aarch64_sys_reg_128bit_p (const uint32_t reg_flags)
+{
+ return (reg_flags & F_REG_128) != 0;
+}
+
bool
aarch64_sys_reg_alias_p (const uint32_t reg_flags)
{
diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h
index 7ce6807c1f1..a4a5ec5e1bb 100644
--- a/opcodes/aarch64-tbl.h
+++ b/opcodes/aarch64-tbl.h
@@ -4236,6 +4236,8 @@ const struct aarch64_opcode aarch64_opcode_table[] =
CORE_INSN ("msr", 0xd5000000, 0xffe00000, ic_system, 0, OP2 (SYSREG, Rt), QL_SRC_X, F_SYS_WRITE),
CORE_INSN ("sysl",0xd5280000, 0xfff80000, ic_system, 0, OP5 (Rt, UIMM3_OP1, CRn, CRm, UIMM3_OP2), QL_SYSL, 0),
CORE_INSN ("mrs", 0xd5200000, 0xffe00000, ic_system, 0, OP2 (Rt, SYSREG), QL_DST_X, F_SYS_READ),
+ D128_INSN ("mrrs", 0xd5700000, 0xfff00000, OP3 (Rt, PAIRREG, SYSREG128), QL_DST_X2, F_SYS_READ),
+ D128_INSN ("msrr", 0xd5500000, 0xfff00000, OP3 (SYSREG128, Rt, PAIRREG), QL_SRC_X2, F_SYS_WRITE),
CORE_INSN ("paciaz", 0xd503231f, 0xffffffff, ic_system, 0, OP0 (), {}, F_ALIAS),
CORE_INSN ("paciasp", 0xd503233f, 0xffffffff, ic_system, 0, OP0 (), {}, F_ALIAS),
CORE_INSN ("pacibz", 0xd503235f, 0xffffffff, ic_system, 0, OP0 (), {}, F_ALIAS),
@@ -6342,6 +6344,7 @@ const struct aarch64_opcode aarch64_opcode_table[] =
Y(ADDRESS, simd_addr_post, "SIMD_ADDR_POST", 0, F(), \
"a post-indexed address with immediate or register increment") \
Y(SYSTEM, sysreg, "SYSREG", 0, F(), "a system register") \
+ Y(SYSTEM, sysreg, "SYSREG128", 0, F(), "a 128-bit system register") \
Y(SYSTEM, pstatefield, "PSTATEFIELD", 0, F(), \
"a PSTATE field name") \
Y(SYSTEM, sysins_op, "SYSREG_AT", 0, F(), \
--
2.42.0
^ permalink raw reply [flat|nested] 16+ messages in thread* [PATCH 12/12] arch64: Add optional operand register pair support tests
2024-01-03 1:17 [PATCH 00/12] aarch64: Add Armv9.4-A support for the d128 extension Victor Do Nascimento
` (10 preceding siblings ...)
2024-01-03 1:17 ` [PATCH 11/12] aarch64: Add support for 128-bit system register mrrs and msrr insns Victor Do Nascimento
@ 2024-01-03 1:17 ` Victor Do Nascimento
2024-01-05 16:10 ` [PATCH 00/12] aarch64: Add Armv9.4-A support for the d128 extension Nick Clifton
12 siblings, 0 replies; 16+ messages in thread
From: Victor Do Nascimento @ 2024-01-03 1:17 UTC (permalink / raw)
To: binutils; +Cc: richard.earnshaw, nickc, Victor Do Nascimento
Add tests to cover the full range of behaviors observed around
optional register operands for the `tlbip' and `sysp' instructions,
namely:
* Not all `tlbip' operations take GPR operands. When this is the
case, we should check that neither optional operand was supplied.
* When a `tlbip' operation is labeled with the `F_HASXT' flag, xzr
is not a valid optional operand. In such case, at least the fist
optional register needs to be specified with a non-xzr value.
* The first operand for both insns should be either xzr or an
even-numbered register (n % 2 == 0). In the former scenario, the
second operand should default to xzr too, while in the latter, it
should default to n + 1.
---
.../gas/aarch64/illegal-sysp-tlbip-optional.d | 4 ++++
.../gas/aarch64/illegal-sysp-tlbip-optional.l | 4 ++++
.../gas/aarch64/illegal-sysp-tlbip-optional.s | 10 +++++++++
.../gas/aarch64/sysp-tlbip-optional.d | 17 ++++++++++++++
.../gas/aarch64/sysp-tlbip-optional.s | 22 +++++++++++++++++++
5 files changed, 57 insertions(+)
create mode 100644 gas/testsuite/gas/aarch64/illegal-sysp-tlbip-optional.d
create mode 100644 gas/testsuite/gas/aarch64/illegal-sysp-tlbip-optional.l
create mode 100644 gas/testsuite/gas/aarch64/illegal-sysp-tlbip-optional.s
create mode 100644 gas/testsuite/gas/aarch64/sysp-tlbip-optional.d
create mode 100644 gas/testsuite/gas/aarch64/sysp-tlbip-optional.s
diff --git a/gas/testsuite/gas/aarch64/illegal-sysp-tlbip-optional.d b/gas/testsuite/gas/aarch64/illegal-sysp-tlbip-optional.d
new file mode 100644
index 00000000000..0bf5af405cb
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/illegal-sysp-tlbip-optional.d
@@ -0,0 +1,4 @@
+#name: Illegal optional operand pair use
+#as: -mno-verbose-error
+#source: illegal-sysp-tlbip-optional.s
+#error_output: illegal-sysp-tlbip-optional.l
diff --git a/gas/testsuite/gas/aarch64/illegal-sysp-tlbip-optional.l b/gas/testsuite/gas/aarch64/illegal-sysp-tlbip-optional.l
new file mode 100644
index 00000000000..69450747b15
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/illegal-sysp-tlbip-optional.l
@@ -0,0 +1,4 @@
+[^:]*: Assembler messages:
+[^:]*:5: Error: missing register at operand 2 -- `tlbip vale3nxs'
+[^:]*:9: Error: extraneous register at operand 2 -- `tlbip paall,x0'
+[^:]*:10: Error: extraneous register at operand 2 -- `tlbip paall,x0,x1'
diff --git a/gas/testsuite/gas/aarch64/illegal-sysp-tlbip-optional.s b/gas/testsuite/gas/aarch64/illegal-sysp-tlbip-optional.s
new file mode 100644
index 00000000000..1e02b71fdba
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/illegal-sysp-tlbip-optional.s
@@ -0,0 +1,10 @@
+ .arch armv9.4-a+d128
+
+ /* TLBIP operands marked with the F_HASXT don not allow xzr to be used
+ as GPR arguments and so require at least one register to be specified. */
+ tlbip vale3nxs
+
+ /* Conversely, those without the flag do not allow us to specify registers,
+ so the only accepted alternative is the complete omission of optional ops. */
+ tlbip paall, x0
+ tlbip paall, x0, x1
diff --git a/gas/testsuite/gas/aarch64/sysp-tlbip-optional.d b/gas/testsuite/gas/aarch64/sysp-tlbip-optional.d
new file mode 100644
index 00000000000..977dedbf843
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sysp-tlbip-optional.d
@@ -0,0 +1,17 @@
+#objdump: -dr
+
+.*
+
+Disassembly of section \.text:
+
+0+ <\.text>:
+[^:]*: d54e97a0 sysp #6, C9, C7, #5, x0, x1
+[^:]*: d54e97a0 sysp #6, C9, C7, #5, x0, x1
+[^:]*: d54e97a2 sysp #6, C9, C7, #5, x2, x3
+[^:]*: d54e97a2 sysp #6, C9, C7, #5, x2, x3
+[^:]*: d54e879f sysp #6, C8, C7, #4
+[^:]*: d54e97bf sysp #6, C9, C7, #5
+[^:]*: d54e97a0 sysp #6, C9, C7, #5, x0, x1
+[^:]*: d54e97a0 sysp #6, C9, C7, #5, x0, x1
+[^:]*: d54e97a2 sysp #6, C9, C7, #5, x2, x3
+[^:]*: d54e97a2 sysp #6, C9, C7, #5, x2, x3
diff --git a/gas/testsuite/gas/aarch64/sysp-tlbip-optional.s b/gas/testsuite/gas/aarch64/sysp-tlbip-optional.s
new file mode 100644
index 00000000000..3635db1d039
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sysp-tlbip-optional.s
@@ -0,0 +1,22 @@
+ .arch armv9.4-a+d128
+
+ /* TLBIP operands marked with the F_HASXT don not allow xzr to be used
+ as GPR arguments and so require at least one register to be specified. */
+ tlbip vale3nxs, x0
+ tlbip vale3nxs, x0, x1
+ tlbip vale3nxs, x2
+ tlbip vale3nxs, x2, x3
+
+
+ /* Conversely, those without the flag do not allow us to specify registers,
+ so the only accepted alternative is the complete omission of optional ops. */
+ tlbip paall
+
+ /* No such checking is carried out when the same instruction is issued
+ directly via the sysp implementation defined maintenance instruction,
+ such that both GRPs are optional. */
+ sysp #6, C9, C7, #5
+ sysp #6, C9, C7, #5, x0
+ sysp #6, C9, C7, #5, x0, x1
+ sysp #6, c9, c7, #5, x2
+ sysp #6, c9, c7, #5, x2, x3
--
2.42.0
^ permalink raw reply [flat|nested] 16+ messages in thread* Re: [PATCH 00/12] aarch64: Add Armv9.4-A support for the d128 extension
2024-01-03 1:17 [PATCH 00/12] aarch64: Add Armv9.4-A support for the d128 extension Victor Do Nascimento
` (11 preceding siblings ...)
2024-01-03 1:17 ` [PATCH 12/12] arch64: Add optional operand register pair support tests Victor Do Nascimento
@ 2024-01-05 16:10 ` Nick Clifton
2024-01-05 16:53 ` Victor Do Nascimento
12 siblings, 1 reply; 16+ messages in thread
From: Nick Clifton @ 2024-01-05 16:10 UTC (permalink / raw)
To: Victor Do Nascimento, binutils; +Cc: richard.earnshaw
Hi Victor,
> The d128 extension released as an optional architectural feature for
> Armv9.4-a introduces 128-bit page table descriptors and support for
> these.
Did you run the testsuites after applying this patch series ?
I ask because I am seeing a *lot* of new failures in the assembler,
linker and binutils testsuites with this series applied. :-(
For example:
FAIL: gas/aarch64/addsub
and the log shows:
regexp_diff match failure
regexp "^ 0: 0b0100f0 add w16, w7, w1$"
line " 0: 0b0000f1 add w17, w7, w17, none #0"
regexp_diff match failure
regexp "^ 4: 0b2100f0 add w16, w7, w1, uxtb$"
line " 4: 0b2100f0 .inst 0x0b2100f0 ; undefined"
[...]
Perhaps I have mis-applied the patch series, but before I investigate
further, please could you confirm that these failures are not something
that you see in your local builds.
Cheers
Nick
^ permalink raw reply [flat|nested] 16+ messages in thread* Re: [PATCH 00/12] aarch64: Add Armv9.4-A support for the d128 extension
2024-01-05 16:10 ` [PATCH 00/12] aarch64: Add Armv9.4-A support for the d128 extension Nick Clifton
@ 2024-01-05 16:53 ` Victor Do Nascimento
2024-01-08 10:04 ` Nick Clifton
0 siblings, 1 reply; 16+ messages in thread
From: Victor Do Nascimento @ 2024-01-05 16:53 UTC (permalink / raw)
To: Nick Clifton, binutils; +Cc: richard.earnshaw
On 1/5/24 16:10, Nick Clifton wrote:
> Hi Victor,
>
>> The d128 extension released as an optional architectural feature for
>> Armv9.4-a introduces 128-bit page table descriptors and support for
>> these.
>
> Did you run the testsuites after applying this patch series ?
Sure did (and in this particular case, as did colleagues in the course
of development discussions) :)
First thing I will ask is this: Did you remember to regenerate the
opcodes/aarch64-(asm|dis|opc)-2.c files??
If you're seeing a *lot* of new failures (easily in the order of the
hundreds), then I'm betting good money that this might be to blame.
Please let me know if you continue face any issues!
Best regards,
Victor
> I ask because I am seeing a *lot* of new failures in the assembler,
> linker and binutils testsuites with this series applied. :-(
>
> For example:
>
> FAIL: gas/aarch64/addsub
>
> and the log shows:
>
> regexp_diff match failure
> regexp "^ 0: 0b0100f0 add w16, w7, w1$"
> line " 0: 0b0000f1 add w17, w7, w17, none #0"
> regexp_diff match failure
> regexp "^ 4: 0b2100f0 add w16, w7, w1, uxtb$"
> line " 4: 0b2100f0 .inst 0x0b2100f0 ; undefined"
> [...]
>
> Perhaps I have mis-applied the patch series, but before I investigate
> further, please could you confirm that these failures are not something
> that you see in your local builds.
>
> Cheers
> Nick
>
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH 00/12] aarch64: Add Armv9.4-A support for the d128 extension
2024-01-05 16:53 ` Victor Do Nascimento
@ 2024-01-08 10:04 ` Nick Clifton
0 siblings, 0 replies; 16+ messages in thread
From: Nick Clifton @ 2024-01-08 10:04 UTC (permalink / raw)
To: Victor Do Nascimento, binutils; +Cc: richard.earnshaw
Hi Victor,
>> Did you run the testsuites after applying this patch series ?
> First thing I will ask is this: Did you remember to regenerate the opcodes/aarch64-(asm|dis|opc)-2.c files??
*silence*
Doh!
*sigh*, no, I forgot. Boy do I feel stupid now.
OK, so with the tables rebuilt the testsuite failures do not appear and
everything looks peachy.
Patch series approved - please apply them all.
Cheers
Nick
^ permalink raw reply [flat|nested] 16+ messages in thread