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X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 12 Jan 2024 16:56:52.2288 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: fa95b9e1-836b-4824-d647-08dc138f79b4 X-MS-Exchange-CrossTenant-Id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=f34e5979-57d9-4aaa-ad4d-b122a662184d;Ip=[63.35.35.123];Helo=[64aa7808-outbound-1.mta.getcheckrecipient.com] X-MS-Exchange-CrossTenant-AuthSource: AMS0EPF000001B6.eurprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DB4PR08MB8079 X-Spam-Status: No, score=-12.4 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,FORGED_SPF_HELO,GIT_PATCH_0,KAM_DMARC_NONE,RCVD_IN_DNSWL_NONE,RCVD_IN_MSPIKE_H2,SPF_HELO_PASS,SPF_NONE,TXREP,T_SCC_BODY_TEXT_LINE,UNPARSEABLE_RELAY autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: The particular choices of address indexing, along with their encoding for RCPC3 instructions lead to the requirement of a new set of operand descriptions, along with the relevant inserter/extractor set. That is, for the integer load/stores, there is only a single valid indexing offset quantity and offset mode is allowed - The value is always equivalent to the amount of data read/stored by the operation and the offset is post-indexed for Load-Acquire RCpc, and pre-indexed with writeback for Store-Release insns. This indexing quantity/mode pair is selected by the setting of a single bit in the instruction. To represent these insns, we add the following operand types: - AARCH64_OPND_RCPC3_ADDR_OPT_POSTIND - AARCH64_OPND_RCPC3_ADDR_OPT_PREIND_WB In the case of loads and stores involving SIMD/FP registers, the optional offset is encoded as an 8-bit signed immediate, but neither post-indexing or pre-indexing with writeback is available. This created the need for an operand type similar to AARCH64_OPND_ADDR_OFFSET, with the difference that FLD_index should not be checked. We thus introduce the AARCH64_OPND_RCPC3_ADDR_OFFSET operand, a variant of AARCH64_OPND_ADDR_OFFSET, w/o the FLD_index bitfield. --- gas/config/tc-aarch64.c | 65 ++++++++++++++++++++++++++++++++++++++++ include/opcode/aarch64.h | 5 ++++ opcodes/aarch64-opc.c | 5 ++++ opcodes/aarch64-tbl.h | 16 +++++++++- 4 files changed, 90 insertions(+), 1 deletion(-) diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c index 66df5b863dd..9a3480b565b 100644 --- a/gas/config/tc-aarch64.c +++ b/gas/config/tc-aarch64.c @@ -7263,7 +7263,52 @@ parse_operands (char *str, const aarch64_opcode *opcode) inst.reloc.pc_rel = 1; } break; + case AARCH64_OPND_RCPC3_ADDR_PREIND_WB: + case AARCH64_OPND_RCPC3_ADDR_POSTIND: + po_misc_or_fail (parse_address (&str, info)); + if (info->addr.writeback) + { + assign_imm_if_const_or_fixup_later (&inst.reloc, info, + /* addr_off_p */ 1, + /* need_libopcodes_p */ 1, + /* skip_p */ 0); + break; + } + set_syntax_error (_("invalid addressing mode")); + goto failure; + case AARCH64_OPND_RCPC3_ADDR_OPT_PREIND_WB: + case AARCH64_OPND_RCPC3_ADDR_OPT_POSTIND: + { + char *start = str; + /* First use the normal address-parsing routines, to get + the usual syntax errors. */ + po_misc_or_fail (parse_address (&str, info)); + if ((operands[i] == AARCH64_OPND_RCPC3_ADDR_OPT_PREIND_WB + && info->addr.writeback && info->addr.preind) + || (operands[i] == AARCH64_OPND_RCPC3_ADDR_OPT_POSTIND + && info->addr.writeback && info->addr.postind)) + { + assign_imm_if_const_or_fixup_later (&inst.reloc, info, + /* addr_off_p */ 1, + /* need_libopcodes_p */ 1, + /* skip_p */ 0); + break; + } + if (info->addr.pcrel || info->addr.offset.is_reg + || !info->addr.preind || info->addr.postind + || info->addr.writeback) + { + set_syntax_error (_("invalid addressing mode")); + goto failure; + } + /* Then retry, matching the specific syntax of these addresses. */ + str = start; + po_char_or_fail ('['); + po_reg_or_fail (REG_TYPE_R64_SP); + po_char_or_fail (']'); + break; + } case AARCH64_OPND_ADDR_SIMPLE: case AARCH64_OPND_SIMD_ADDR_SIMPLE: { @@ -7384,6 +7429,26 @@ parse_operands (char *str, const aarch64_opcode *opcode) /* skip_p */ 0); break; + case AARCH64_OPND_RCPC3_ADDR_OFFSET: + po_misc_or_fail (parse_address (&str, info)); + if (info->addr.pcrel || info->addr.offset.is_reg + || !info->addr.preind || info->addr.postind + || info->addr.writeback) + { + set_syntax_error (_("invalid addressing mode")); + goto failure; + } + if (inst.reloc.type != BFD_RELOC_UNUSED) + { + set_syntax_error (_("relocation not allowed")); + goto failure; + } + assign_imm_if_const_or_fixup_later (&inst.reloc, info, + /* addr_off_p */ 1, + /* need_libopcodes_p */ 1, + /* skip_p */ 0); + break; + case AARCH64_OPND_ADDR_UIMM12: po_misc_or_fail (parse_address (&str, info)); if (info->addr.pcrel || info->addr.offset.is_reg diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h index dc9c98353d4..f337d14eb24 100644 --- a/include/opcode/aarch64.h +++ b/include/opcode/aarch64.h @@ -783,6 +783,11 @@ enum aarch64_opnd AARCH64_OPND_MOPS_WB_Rn, /* Rn!, in bits [5, 9]. */ AARCH64_OPND_CSSC_SIMM8, /* CSSC signed 8-bit immediate. */ AARCH64_OPND_CSSC_UIMM8, /* CSSC unsigned 8-bit immediate. */ + AARCH64_OPND_RCPC3_ADDR_OPT_POSTIND, /* []{, #}. */ + AARCH64_OPND_RCPC3_ADDR_OPT_PREIND_WB, /* [] or [, #]!. */ + AARCH64_OPND_RCPC3_ADDR_POSTIND, /* [], #. */ + AARCH64_OPND_RCPC3_ADDR_PREIND_WB, /* [, #]!. */ + AARCH64_OPND_RCPC3_ADDR_OFFSET }; /* Qualifier constrains an operand. It either specifies a variant of an diff --git a/opcodes/aarch64-opc.c b/opcodes/aarch64-opc.c index 9d994c12f1a..cf0eabeb946 100644 --- a/opcodes/aarch64-opc.c +++ b/opcodes/aarch64-opc.c @@ -4488,7 +4488,12 @@ aarch64_print_operand (char *buf, size_t size, bfd_vma pc, case AARCH64_OPND_ADDR_SIMM10: case AARCH64_OPND_ADDR_SIMM11: case AARCH64_OPND_ADDR_SIMM13: + case AARCH64_OPND_RCPC3_ADDR_OFFSET: case AARCH64_OPND_ADDR_OFFSET: + case AARCH64_OPND_RCPC3_ADDR_OPT_POSTIND: + case AARCH64_OPND_RCPC3_ADDR_OPT_PREIND_WB: + case AARCH64_OPND_RCPC3_ADDR_POSTIND: + case AARCH64_OPND_RCPC3_ADDR_PREIND_WB: case AARCH64_OPND_SME_ADDR_RI_U4xVL: case AARCH64_OPND_SVE_ADDR_RI_S4x16: case AARCH64_OPND_SVE_ADDR_RI_S4x32: diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h index 708459e287d..3176cb877c2 100644 --- a/opcodes/aarch64-tbl.h +++ b/opcodes/aarch64-tbl.h @@ -6875,4 +6875,18 @@ const struct aarch64_opcode aarch64_opcode_table[] = Y(IMMEDIATE, imm, "CSSC_SIMM8", OPD_F_SEXT, F(FLD_CSSC_imm8), \ "an 8-bit signed immediate") \ Y(IMMEDIATE, imm, "CSSC_UIMM8", 0, F(FLD_CSSC_imm8), \ - "an 8-bit unsigned immediate") + "an 8-bit unsigned immediate") \ + X(ADDRESS, ins_rcpc3_addr_opt_offset, ext_rcpc3_addr_opt_offset, \ + "RCPC3_ADDR_OPT_POSTIND", 0, F(FLD_opc2), \ + "an address with post-incrementing by ammount of loaded bytes") \ + X(ADDRESS, ins_rcpc3_addr_opt_offset, ext_rcpc3_addr_opt_offset, \ + "RCPC3_ADDR_OPT_PREIND_WB", 0, F(FLD_opc2), \ + "an address with pre-incrementing with write-back by ammount of stored bytes") \ + X(ADDRESS, ins_rcpc3_addr_opt_offset, ext_rcpc3_addr_opt_offset, \ + "RCPC3_ADDR_POSTIND", 0, F(), \ + "an address with post-incrementing by ammount of loaded bytes") \ + X(ADDRESS, ins_rcpc3_addr_opt_offset, ext_rcpc3_addr_opt_offset, \ + "RCPC3_ADDR_PREIND_WB", 0, F(), \ + "an address with pre-incrementing with write-back by ammount of stored bytes") \ + Y(ADDRESS, rcpc3_addr_offset, "RCPC3_ADDR_OFFSET", 0, F(FLD_Rn,FLD_imm9), \ + "an address with an optional 8-bit signed immediate offset") -- 2.42.0