[PUSHED] arc: Put DBNZ instruction to a separate class

[Shahab Vahedi <list+bin@vahedi.org>]

From: Yuriy Kolerov <Yuriy.Kolerov@synopsys.com>

DBNZ instruction decrements its source register operand, and if
the result is non-zero it branches to the location defined by a signed
half-word displacement operand.

DBNZ instruction is in BRANCH class as other branch instrucitons
like B, Bcc, etc. However, DBNZ is the only branch instruction
that stores a branch offset in the second operand. Thus it must
be placed in a distinct class and treated differently.

For example, current logic of arc_insn_get_branch_target in GDB
assumes that a branch offset is always stored in the first operand
for BRANCH class and it's wrong for DBNZ.

include/ChangeLog:

2024-02-14  Yuriy Kolerov  <ykolerov@synopsys.com>

	* opcode/arc.h (enum insn_class_t): Add DBNZ class.

opcodes/ChangeLog:

2024-02-14  Yuriy Kolerov  <ykolerov@synopsys.com>

	* arc-tbl.h (dbnz): Use "DBNZ" class.
	* arc-dis.c (arc_opcode_to_insn_type): Handle "DBNZ" class.

gas/ChangeLog:

2024-02-14  Yuriy Kolerov  <ykolerov@synopsys.com>

	* config/tc-arc.c (is_br_jmp_insn_p): Add check against "DBNZ".
---
 gas/ChangeLog        | 4 ++++
 gas/config/tc-arc.c  | 1 +
 include/ChangeLog    | 4 ++++
 include/opcode/arc.h | 1 +
 opcodes/ChangeLog    | 5 +++++
 opcodes/arc-dis.c    | 1 +
 opcodes/arc-tbl.h    | 2 +-
 7 files changed, 17 insertions(+), 1 deletion(-)

diff --git a/gas/ChangeLog b/gas/ChangeLog
index b1c8d09bf1b..b277f47b05d 100644
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,3 +1,7 @@
+2024-02-14  Yuriy Kolerov  <ykolerov@synopsys.com>
+
+	* config/tc-arc.c (is_br_jmp_insn_p): Add check against "DBNZ".
+
 2024-01-29  Jose E. Marchesi  <jose.marchesi@oracle.com>
 
 	* doc/c-bpf.texi (BPF Instructions): There is no indirect 64-bit
diff --git a/gas/config/tc-arc.c b/gas/config/tc-arc.c
index 69de96e43fc..f7d8e8938ce 100644
--- a/gas/config/tc-arc.c
+++ b/gas/config/tc-arc.c
@@ -109,6 +109,7 @@ enum arc_rlx_types
 				  || (op)->insn_class == BBIT0		\
 				  || (op)->insn_class == BBIT1		\
 				  || (op)->insn_class == BI		\
+				  || (op)->insn_class == DBNZ		\
 				  || (op)->insn_class == EI		\
 				  || (op)->insn_class == ENTER		\
 				  || (op)->insn_class == JLI		\
diff --git a/include/ChangeLog b/include/ChangeLog
index 11c4b321a49..db5c258cbdf 100644
--- a/include/ChangeLog
+++ b/include/ChangeLog
@@ -1,3 +1,7 @@
+2024-02-14  Yuriy Kolerov  <ykolerov@synopsys.com>
+
+	* opcode/arc.h (enum insn_class_t): Add DBNZ class.
+
 2024-02-12  Frederic Cambus  <fred@statdns.com>
 
 	* elf/common.h (PT_OPENBSD_SYSCALLS): Define.
diff --git a/include/opcode/arc.h b/include/opcode/arc.h
index df2be17d839..c16e1298b89 100644
--- a/include/opcode/arc.h
+++ b/include/opcode/arc.h
@@ -52,6 +52,7 @@ typedef enum
   BRANCH,
   BRCC,
   CONTROL,
+  DBNZ,
   DIVREM,
   DMA,
   DPI,
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 4bc815780fd..4fb2d0de207 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,8 @@
+2024-02-14  Yuriy Kolerov  <ykolerov@synopsys.com>
+
+	* arc-tbl.h (dbnz): Use "DBNZ" class.
+	* arc-dis.c (arc_opcode_to_insn_type): Handle "DBNZ" class.
+
 2024-01-29  Jose E. Marchesi  <jose.marchesi@oracle.com>
 
 	* bpf-opc.c (bpf_opcodes): Remove BPF_INSN_LDINDDW and
diff --git a/opcodes/arc-dis.c b/opcodes/arc-dis.c
index c75e4406046..16fbc8ab007 100644
--- a/opcodes/arc-dis.c
+++ b/opcodes/arc-dis.c
@@ -894,6 +894,7 @@ arc_opcode_to_insn_type (const struct arc_opcode *opcode)
     case BI:
     case BIH:
     case BRCC:
+    case DBNZ:
     case EI:
     case JLI:
     case JUMP:
diff --git a/opcodes/arc-tbl.h b/opcodes/arc-tbl.h
index e0415c8021d..4572f7d6590 100644
--- a/opcodes/arc-tbl.h
+++ b/opcodes/arc-tbl.h
@@ -3656,7 +3656,7 @@
 { "daddh22", 0x36F77F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2EM, FLOAT, DPA, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
 
 /* dbnz<.d> b,s13 00100bbb1000110N0BBBssssssSSSSSS.  */
-{ "dbnz", 0x208C0000, 0xF8FE8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE, { RB, SIMM13_A16_20}, { C_DNZ_D }},
+{ "dbnz", 0x208C0000, 0xF8FE8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, DBNZ, NONE, { RB, SIMM13_A16_20}, { C_DNZ_D }},
 
 /* dexcl1<.f> a,b,c 00110bbb00011000FBBBCCCCCCAAAAAA.  */
 { "dexcl1", 0x30180000, 0xF8FF0000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, FLOAT, DPX, { RA, RB, RC }, { C_F }},
-- 
2.35.8