From: Jens Remus <jremus@linux.ibm.com>
To: binutils@sourceware.org
Cc: Jens Remus <jremus@linux.ibm.com>,
Andreas Krebbel <krebbel@linux.ibm.com>
Subject: [PATCH 10/14] s390: Warn when register name type does not match operand
Date: Thu, 15 Feb 2024 16:58:17 +0100 [thread overview]
Message-ID: <20240215155821.4065623-11-jremus@linux.ibm.com> (raw)
In-Reply-To: <20240215155821.4065623-1-jremus@linux.ibm.com>
Print a warning message when the register type of a specified register
name does not match with the operand's register type:
operand {#}: expected {access|control|floating-point|general|vector}
register name [as {base|index} register]
Introduce a s390-specific assembler option "warn-regtype-mismatch"
with the values "strict", "relaxed", and "no" as well as an option
"no-warn-regtype-mismatch" which control whether the assembler
performs register name type checks and generates above warning messages.
warn-regtype-mismatch=strict:
Perform strict register name type checks.
warn-regtype-mismatch=relaxed:
Perform relaxed register name type checks, which allow floating-point
register (FPR) names %f0 to %f15 to be specified as argument to vector
register (VR) operands and vector register (VR) names %v0 to %v15 to
be specified as argument to floating-point register (FPR) operands.
This is acceptable as the FPRs are embedded into the lower halves of
the VRs. Make "relaxed" the default, as GCC generates assembler code
using FPR and VR interchangeably, which would cause assembler warnings
to be generated with "strict".
warn-regtype-mismatch=no:
no-warn-regtype-mismatch:
Disable any register name type checks.
Tag .insn pseudo mnemonics as such, to skip register name type checks
on those. They need to be skipped, as there do not exist .insn pseudo
mnemonics for every possible operand register type combination. Keep
track of the currently parsed operand number to provide it as reference
in warning messages.
To verify that the introduction of this change does not unnecessarily
affect the compilation of existing code the GNU Binutils, GNU C Library,
and Linux Kernel have been build with the new assembler, verifying that
the assembler did not generate any of the new warning messages.
gas/
* config/tc-s390.c: Handle new assembler options
"[no]warn-regtype-mismatch[=strict|relaxed|no". Annotate
parsed register expressions with register type. Keep track of
operand number being parsed. Print warning message in case of
register type mismatch between instruction operand and parsed
register expression.
* doc/as.texi: Document new s390-specific assembler options
"[no-]warn-regtype-mismatch[=strict|relaxed|no]".
* NEWS: Mention new s390-specific register name type checks and
related assembler option "warn-regtype-mismatch=strict|
relaxed|no".
* testsuite/gas/s390/s390.exp: Add test cases for new assembler
option "warn-regtype-mismatch={strict|relaxed}".
* testsuite/gas/s390/esa-g5.s: Fix register types in tests for
didbr, diebr, tbdr, and tbedr.
* testsuite/gas/s390/zarch-z13.s: Fix register types in tests
for vgef, vgeg, vscef, and vsceg.
* testsuite/gas/s390/zarch-warn-regtype-mismatch-strict.s:
Tests for assembler option "warn-regtype-mismatch=strict".
* testsuite/gas/s390/zarch-warn-regtype-mismatch-strict.l:
Likewise.
* gas/testsuite/gas/s390/zarch-warn-regtype-mismatch-relaxed.s:
Tests for assembler option "warn-regtype-mismatch=relaxed".
* gas/testsuite/gas/s390/zarch-warn-regtype-mismatch-relaxed.l:
Likewise.
* gas/testsuite/gas/s390/zarch-omitted-base-index-err.s: Update
test cases for assembler option "warn-regtype-mismatch"
defaulting to "relaxed".
* testsuite/gas/s390/zarch-omitted-base-index-err.l: Likewise.
include/
* opcode/s390.h (S390_INSTR_FLAG_PSEUDO_MNEMONIC): Add
instruction flag to tag .insn pseudo-mnemonics.
opcodes/
* s390-opc.c (s390_opformats): Tag .insn pseudo-mnemonics as
such.
Reviewed-by: Andreas Krebbel <krebbel@linux.ibm.com>
Signed-off-by: Jens Remus <jremus@linux.ibm.com>
---
gas/NEWS | 6 +
gas/config/tc-s390.c | 108 ++++++++++++++++++
gas/doc/as.texi | 20 ++++
gas/testsuite/gas/s390/esa-g5.s | 8 +-
gas/testsuite/gas/s390/s390.exp | 2 +
.../gas/s390/zarch-omitted-base-index-err.l | 29 ++---
.../gas/s390/zarch-omitted-base-index-err.s | 1 +
.../zarch-warn-regtype-mismatch-relaxed.l | 15 +++
.../zarch-warn-regtype-mismatch-relaxed.s | 7 ++
.../s390/zarch-warn-regtype-mismatch-strict.l | 15 +++
.../s390/zarch-warn-regtype-mismatch-strict.s | 7 ++
gas/testsuite/gas/s390/zarch-z13.s | 8 +-
include/opcode/s390.h | 3 +
opcodes/s390-opc.c | 62 +++++-----
14 files changed, 238 insertions(+), 53 deletions(-)
create mode 100644 gas/testsuite/gas/s390/zarch-warn-regtype-mismatch-relaxed.l
create mode 100644 gas/testsuite/gas/s390/zarch-warn-regtype-mismatch-relaxed.s
create mode 100644 gas/testsuite/gas/s390/zarch-warn-regtype-mismatch-strict.l
create mode 100644 gas/testsuite/gas/s390/zarch-warn-regtype-mismatch-strict.s
diff --git a/gas/NEWS b/gas/NEWS
index 6494acfa3ea4..e5572da5f7b8 100644
--- a/gas/NEWS
+++ b/gas/NEWS
@@ -1,5 +1,11 @@
-*- text -*-
+* Warn when a register name type does not match the operand type on s390.
+ Add support for s390-specific option "warn-regtype-mismatch=[strict|relaxed|
+ no]" to override the register name type check behavior. The default
+ is "relaxed", which allows floating-point and vector register names to be
+ used interchangeably.
+
Changes in 2.42:
* Add support for AMD znver5 processor.
diff --git a/gas/config/tc-s390.c b/gas/config/tc-s390.c
index eef8428b40a6..daa44bb3f816 100644
--- a/gas/config/tc-s390.c
+++ b/gas/config/tc-s390.c
@@ -60,6 +60,20 @@ static bool reg_names_p = TARGET_REG_NAMES_P;
/* Set to TRUE if we want to warn about zero base/index registers. */
static bool warn_areg_zero = false;
+/* Whether to warn about register name type check mismatches. */
+#ifndef S390_REGTYPE_CHECK
+#define S390_REGTYPE_CHECK S390_REGTYPE_CHECK_RELAXED
+#endif
+
+enum s390_regtype_check {
+ S390_REGTYPE_CHECK_NONE = 0, /* No register name type checks. */
+ S390_REGTYPE_CHECK_RELAXED, /* Relaxed register name type checks. */
+ S390_REGTYPE_CHECK_STRICT /* Strict register name type checks. */
+};
+
+/* Whether to warn about register name type check mismatches. */
+static enum s390_regtype_check warn_regtype_mismatch = S390_REGTYPE_CHECK;
+
/* Generic assembler global variables which must be defined by all
targets. */
@@ -110,6 +124,16 @@ const pseudo_typeS md_pseudo_table[] =
{ NULL, NULL, 0 }
};
+/* Register types. */
+enum s390_register_type
+ {
+ S390_REGTYPE_AR, /* Access register. */
+ S390_REGTYPE_CR, /* Control register. */
+ S390_REGTYPE_FPR, /* Floating-point register. */
+ S390_REGTYPE_GR, /* General register. */
+ S390_REGTYPE_VR, /* Vector register. */
+ };
+
/* Given NAME, find the register number associated with that name, return
the integer value associated with the given name or -1 on failure. */
@@ -180,6 +204,26 @@ register_name (expressionS *expressionP)
{
expressionP->X_op = O_register;
expressionP->X_add_number = reg_number;
+ switch (name[0])
+ {
+ case 'a':
+ expressionP->X_md = S390_REGTYPE_AR;
+ break;
+ case 'c':
+ expressionP->X_md = S390_REGTYPE_CR;
+ break;
+ case 'f':
+ expressionP->X_md = S390_REGTYPE_FPR;
+ break;
+ case 'r':
+ expressionP->X_md = S390_REGTYPE_GR;
+ break;
+ case 'v':
+ expressionP->X_md = S390_REGTYPE_VR;
+ break;
+ default:
+ expressionP->X_md = 0;
+ }
/* Make the rest nice. */
expressionP->X_add_symbol = NULL;
@@ -415,6 +459,18 @@ md_parse_option (int c, const char *arg)
else if (arg != NULL && strcmp (arg, "warn-areg-zero") == 0)
warn_areg_zero = true;
+ else if (arg != NULL && strcmp (arg, "warn-regtype-mismatch=strict") == 0)
+ warn_regtype_mismatch = S390_REGTYPE_CHECK_STRICT;
+
+ else if (arg != NULL && strcmp (arg, "warn-regtype-mismatch=relaxed") == 0)
+ warn_regtype_mismatch = S390_REGTYPE_CHECK_RELAXED;
+
+ else if (arg != NULL && strcmp (arg, "warn-regtype-mismatch=no") == 0)
+ warn_regtype_mismatch = S390_REGTYPE_CHECK_NONE;
+
+ else if (arg != NULL && strcmp (arg, "no-warn-regtype-mismatch") == 0)
+ warn_regtype_mismatch = S390_REGTYPE_CHECK_NONE;
+
else if (arg != NULL && strcmp (arg, "31") == 0)
s390_arch_size = 32;
@@ -484,6 +540,13 @@ S390 options:\n\
-mregnames allow symbolic names for registers\n\
-mno-regnames do not allow symbolic names for registers\n\
-mwarn-areg-zero warn about base/index register zero\n\
+ -mwarn-regtype-mismatch=strict\n\
+ warn about register name type mismatches\n\
+ -mwarn-regtype-mismatch=relaxed\n\
+ warn about register name type mismatches,\n\
+ but allow FPR and VR to be used interchangeably\n\
+ -mno-warn-regtype-mismatch\n\
+ do not warn about register name type mismatches\n\
"));
fprintf (stream, _("\
-V print assembler version number\n\
@@ -1279,6 +1342,7 @@ md_gather_operands (char *str,
elf_suffix_type suffix;
bfd_reloc_code_real_type reloc;
int omitted_base_or_index;
+ int operand_number;
char *f;
int fc, i;
@@ -1287,6 +1351,7 @@ md_gather_operands (char *str,
/* Gather the operands. */
omitted_base_or_index = 0; /* Whether B in D(L,B) or X in D(X,B) were omitted. */
+ operand_number = 1; /* Current operand number in e.g. R1,I2,M3,D4(B4). */
fc = 0;
for (opindex_ptr = opcode->operands; *opindex_ptr != 0; opindex_ptr++)
{
@@ -1378,6 +1443,44 @@ md_gather_operands (char *str,
as_bad (_("invalid floating point register pair. Valid fp "
"register pair operands are 0, 1, 4, 5, 8, 9, "
"12 or 13."));
+ if (warn_regtype_mismatch && ex.X_op == O_register
+ && !(opcode->flags & S390_INSTR_FLAG_PSEUDO_MNEMONIC))
+ {
+ const char *expected_regtype = NULL;
+
+ if ((operand->flags & S390_OPERAND_AR)
+ && ex.X_md != S390_REGTYPE_AR)
+ expected_regtype = _("access register");
+ else if ((operand->flags & S390_OPERAND_CR)
+ && ex.X_md != S390_REGTYPE_CR)
+ expected_regtype = _("control register");
+ else if ((operand->flags & S390_OPERAND_FPR)
+ && ex.X_md != S390_REGTYPE_FPR
+ && (warn_regtype_mismatch == S390_REGTYPE_CHECK_STRICT
+ || (ex.X_md != S390_REGTYPE_VR)))
+ expected_regtype = _("floating-point register");
+ else if ((operand->flags & S390_OPERAND_GPR)
+ && ex.X_md != S390_REGTYPE_GR)
+ expected_regtype = _("general register");
+ else if ((operand->flags & S390_OPERAND_VR)
+ && ex.X_md != S390_REGTYPE_VR
+ && (warn_regtype_mismatch == S390_REGTYPE_CHECK_STRICT
+ || (ex.X_md != S390_REGTYPE_FPR)))
+ expected_regtype = _("vector register");
+
+ if (expected_regtype)
+ {
+ if (operand->flags & S390_OPERAND_BASE)
+ as_warn (_("operand %d: expected %s name as base register"),
+ operand_number, expected_regtype);
+ else if (operand->flags & S390_OPERAND_INDEX)
+ as_warn (_("operand %d: expected %s name as index register"),
+ operand_number, expected_regtype);
+ else
+ as_warn (_("operand %d: expected %s name"),
+ operand_number, expected_regtype);
+ }
+ }
s390_insert_operand (insn, operand, ex.X_add_number, NULL, 0);
}
}
@@ -1516,6 +1619,7 @@ md_gather_operands (char *str,
{
/* Comma. */
str++;
+ operand_number++;
}
}
}
@@ -1572,6 +1676,7 @@ md_gather_operands (char *str,
{
/* Comma. */
str++;
+ operand_number++;
}
}
}
@@ -1610,6 +1715,9 @@ md_gather_operands (char *str,
{
/* Comma. */
str++;
+ if (!(operand->flags & (S390_OPERAND_INDEX
+ | S390_OPERAND_LENGTH)))
+ operand_number++;
}
}
}
diff --git a/gas/doc/as.texi b/gas/doc/as.texi
index 50c054361416..1e122ccbbde0 100644
--- a/gas/doc/as.texi
+++ b/gas/doc/as.texi
@@ -584,6 +584,10 @@ gcc(1), ld(1), and the Info entries for @file{binutils} and @file{ld}.
[@b{-m31}|@b{-m64}] [@b{-mesa}|@b{-mzarch}] [@b{-march}=@var{CPU}]
[@b{-mregnames}|@b{-mno-regnames}]
[@b{-mwarn-areg-zero}]
+ [@b{-mwarn-regtype-mismatch=strict}
+ @b{-mwarn-regtype-mismatch=relaxed}
+ @b{-mwarn-regtype-mismatch=no}
+ @b{-mno-warn-regtype-mismatch}]
@end ifset
@ifset SCORE
@@ -1963,6 +1967,22 @@ Allow or disallow symbolic names for registers.
@item -mwarn-areg-zero
Warn whenever the operand for a base or index register has been specified
but evaluates to zero.
+@item -mwarn-regtype-mismatch=strict
+@itemx -mwarn-regtype-mismatch=relaxed
+@itemx -mwarn-regtype-mismatch=no
+@itemx -mno-warn-regtype-mismatch
+Controls whether the assembler performs register name type checks and generates
+a warning message in case of a mismatch with the operand register type.
+The default (which can be restored by using the @option{relaxed} argument) is
+to perform relaxed register name type checks, which allow floating point
+register (FPR) names %f0 to %f15 to be specified as argument to vector register
+(VR) operands and vector register (VR) names %v0 to %v15 to be specified as
+argument to floating point register (FPR) operands. This is acceptable as the
+FPR are embedded into the lower half of the VR.
+Using the @option{strict} argument strict register name type checks are
+performed.
+The @option{no} argument, which is equivalent to
+@samp{-mno-warn-regtype-mismatch}, disables any register name type checks.
@end table
@end ifset
@c man end
diff --git a/gas/testsuite/gas/s390/esa-g5.s b/gas/testsuite/gas/s390/esa-g5.s
index 2901a866ec93..812d56e65dbf 100644
--- a/gas/testsuite/gas/s390/esa-g5.s
+++ b/gas/testsuite/gas/s390/esa-g5.s
@@ -146,8 +146,8 @@ foo:
debr %f6,%f9
der %f6,%f9
diag %r6,%r9,4095(%r5)
- didbr %f6,%r9,%r5,10
- diebr %f6,%r9,%r5,10
+ didbr %f6,%f9,%f5,10
+ diebr %f6,%f9,%f5,10
dp 4095(6,%r5),4095(9,%r10)
dr %r6,%r9
dxbr %f5,%f8
@@ -465,8 +465,8 @@ foo:
sxr %f5,%f8
tar %a6,%r9
tb %r6,%r9
- tbdr %r6,5,%r9
- tbedr %r6,5,%r9
+ tbdr %f6,5,%f9
+ tbedr %f6,5,%f9
tcdb %f6,4095(%r5,%r10)
tceb %f6,4095(%r5,%r10)
tcxb %f5,4095(%r5,%r10)
diff --git a/gas/testsuite/gas/s390/s390.exp b/gas/testsuite/gas/s390/s390.exp
index 613487fc453c..a4e8dbc44a50 100644
--- a/gas/testsuite/gas/s390/s390.exp
+++ b/gas/testsuite/gas/s390/s390.exp
@@ -61,4 +61,6 @@ if [expr [istarget "s390-*-*"] || [istarget "s390x-*-*"]] then {
run_dump_test "zarch-base-index-0" "{as -m64}"
run_list_test "zarch-base-index-0-err" ""
run_list_test "zarch-warn-areg-zero" "-m64 -mwarn-areg-zero"
+ run_list_test "zarch-warn-regtype-mismatch-strict" "-m64 -mwarn-regtype-mismatch=strict"
+ run_list_test "zarch-warn-regtype-mismatch-relaxed" "-m64 -mwarn-regtype-mismatch=relaxed"
}
diff --git a/gas/testsuite/gas/s390/zarch-omitted-base-index-err.l b/gas/testsuite/gas/s390/zarch-omitted-base-index-err.l
index fe13f95d3174..e4bd7a8c4171 100644
--- a/gas/testsuite/gas/s390/zarch-omitted-base-index-err.l
+++ b/gas/testsuite/gas/s390/zarch-omitted-base-index-err.l
@@ -7,18 +7,19 @@
.*:9: Error: syntax error; missing '\)' after base register
.*:12: Error: bad expression
.*:12: Error: syntax error; missing '\)' after base register
-.*:13: Error: bad expression
-.*:13: Error: syntax error; missing '\)' after base register
-.*:16: Error: missing operand
+.*:13: Warning: operand 2: expected general register name as base register
+.*:14: Error: bad expression
+.*:14: Error: syntax error; missing '\)' after base register
.*:17: Error: missing operand
-.*:18: Error: invalid length field specified
-.*:19: Error: bad expression
-.*:19: Error: operand out of range \(0 is not between 1 and 256\)
-.*:19: Error: operand out of range \(32 is not between 0 and 15\)
-.*:19: Error: syntax error; missing '\)' after base register
-.*:19: Error: syntax error; expected ','
-.*:19: Error: bad expression
-.*:19: Error: found 'r', expected: '\)'
-.*:19: Error: syntax error; missing '\)' after base register
-.*:19: Error: junk at end of line: `r2\)'
-.*:20: Error: syntax error; missing '\(' after displacement
+.*:18: Error: missing operand
+.*:19: Error: invalid length field specified
+.*:20: Error: bad expression
+.*:20: Error: operand out of range \(0 is not between 1 and 256\)
+.*:20: Error: operand out of range \(32 is not between 0 and 15\)
+.*:20: Error: syntax error; missing '\)' after base register
+.*:20: Error: syntax error; expected ','
+.*:20: Error: bad expression
+.*:20: Error: found 'r', expected: '\)'
+.*:20: Error: syntax error; missing '\)' after base register
+.*:20: Error: junk at end of line: `r2\)'
+.*:21: Error: syntax error; missing '\(' after displacement
diff --git a/gas/testsuite/gas/s390/zarch-omitted-base-index-err.s b/gas/testsuite/gas/s390/zarch-omitted-base-index-err.s
index 65ad739d02c6..dd0e9fe183f3 100644
--- a/gas/testsuite/gas/s390/zarch-omitted-base-index-err.s
+++ b/gas/testsuite/gas/s390/zarch-omitted-base-index-err.s
@@ -10,6 +10,7 @@ foo:
# V1,D2(VX2,B2),M3
vgef %v1,16(%v2,),0
+ vgef %v1,16(%v2),0
vgef %v1,16(),0
# D1(L1,B1),D2(B2)
diff --git a/gas/testsuite/gas/s390/zarch-warn-regtype-mismatch-relaxed.l b/gas/testsuite/gas/s390/zarch-warn-regtype-mismatch-relaxed.l
new file mode 100644
index 000000000000..e91f0206934f
--- /dev/null
+++ b/gas/testsuite/gas/s390/zarch-warn-regtype-mismatch-relaxed.l
@@ -0,0 +1,15 @@
+.*: Assembler messages:
+.*:3: Warning: operand 1: expected general register name
+.*:3: Warning: operand 2: expected general register name as index register
+.*:3: Warning: operand 2: expected general register name as base register
+.*:4: Warning: operand 1: expected floating-point register name
+.*:4: Warning: operand 2: expected general register name as index register
+.*:4: Warning: operand 2: expected general register name as base register
+.*:5: Warning: operand 1: expected vector register name
+.*:5: Warning: operand 2: expected general register name as index register
+.*:5: Warning: operand 2: expected general register name as base register
+.*:6: Warning: operand 1: expected vector register name
+.*:6: Warning: operand 2: expected vector register name as index register
+.*:6: Warning: operand 2: expected general register name as base register
+.*:7: Warning: operand 1: expected access register name
+.*:7: Warning: operand 2: expected general register name
diff --git a/gas/testsuite/gas/s390/zarch-warn-regtype-mismatch-relaxed.s b/gas/testsuite/gas/s390/zarch-warn-regtype-mismatch-relaxed.s
new file mode 100644
index 000000000000..ed6688db7027
--- /dev/null
+++ b/gas/testsuite/gas/s390/zarch-warn-regtype-mismatch-relaxed.s
@@ -0,0 +1,7 @@
+.text
+foo:
+ la %f1,16(%f2,%f3) # la %r1,16(%r2,%r3)
+ ld %r1,16(%f2,%f3) # ld %f1,16(%r2,%r3)
+ vl %r1,16(%f2,%f3),0 # vl %v1,16(%r2,%r3),0
+ vgef %r1,16(%r1,%f3),0 # vgef %v1,16(%v2,%r3),0
+ sar %r1,%a2 # sar %a1,%r2
diff --git a/gas/testsuite/gas/s390/zarch-warn-regtype-mismatch-strict.l b/gas/testsuite/gas/s390/zarch-warn-regtype-mismatch-strict.l
new file mode 100644
index 000000000000..e91f0206934f
--- /dev/null
+++ b/gas/testsuite/gas/s390/zarch-warn-regtype-mismatch-strict.l
@@ -0,0 +1,15 @@
+.*: Assembler messages:
+.*:3: Warning: operand 1: expected general register name
+.*:3: Warning: operand 2: expected general register name as index register
+.*:3: Warning: operand 2: expected general register name as base register
+.*:4: Warning: operand 1: expected floating-point register name
+.*:4: Warning: operand 2: expected general register name as index register
+.*:4: Warning: operand 2: expected general register name as base register
+.*:5: Warning: operand 1: expected vector register name
+.*:5: Warning: operand 2: expected general register name as index register
+.*:5: Warning: operand 2: expected general register name as base register
+.*:6: Warning: operand 1: expected vector register name
+.*:6: Warning: operand 2: expected vector register name as index register
+.*:6: Warning: operand 2: expected general register name as base register
+.*:7: Warning: operand 1: expected access register name
+.*:7: Warning: operand 2: expected general register name
diff --git a/gas/testsuite/gas/s390/zarch-warn-regtype-mismatch-strict.s b/gas/testsuite/gas/s390/zarch-warn-regtype-mismatch-strict.s
new file mode 100644
index 000000000000..ed6688db7027
--- /dev/null
+++ b/gas/testsuite/gas/s390/zarch-warn-regtype-mismatch-strict.s
@@ -0,0 +1,7 @@
+.text
+foo:
+ la %f1,16(%f2,%f3) # la %r1,16(%r2,%r3)
+ ld %r1,16(%f2,%f3) # ld %f1,16(%r2,%r3)
+ vl %r1,16(%f2,%f3),0 # vl %v1,16(%r2,%r3),0
+ vgef %r1,16(%r1,%f3),0 # vgef %v1,16(%v2,%r3),0
+ sar %r1,%a2 # sar %a1,%r2
diff --git a/gas/testsuite/gas/s390/zarch-z13.s b/gas/testsuite/gas/s390/zarch-z13.s
index 646dd3097fb3..8c2fb706e0c0 100644
--- a/gas/testsuite/gas/s390/zarch-z13.s
+++ b/gas/testsuite/gas/s390/zarch-z13.s
@@ -1,8 +1,8 @@
.text
foo:
lcbb %r6,4000(%r9,%r11),13
- vgef %v15,4000(%r6,%r9),13
- vgeg %v15,4000(%r6,%r9),13
+ vgef %v15,4000(%v6,%r9),13
+ vgeg %v15,4000(%v6,%r9),13
vgbm %v15,65533
vzero %v15
vone %v15
@@ -83,8 +83,8 @@ foo:
vrepih %v15,-32765
vrepif %v15,-32765
vrepig %v15,-32765
- vscef %v15,4000(%r6,%r9),13
- vsceg %v15,4000(%r6,%r9),13
+ vscef %v15,4000(%v6,%r9),13
+ vsceg %v15,4000(%v6,%r9),13
vsel %v15,%v17,%v20,%v24
vseg %v15,%v17,13
vsegb %v15,%v17
diff --git a/include/opcode/s390.h b/include/opcode/s390.h
index 5656368726a4..e5dfcb275707 100644
--- a/include/opcode/s390.h
+++ b/include/opcode/s390.h
@@ -77,6 +77,9 @@ enum s390_opcode_cpu_val
(S390_INSTR_FLAG_CLASS_BRANCH | S390_INSTR_FLAG_CLASS_RELATIVE \
| S390_INSTR_FLAG_CLASS_SUBROUTINE)
+/* Instruction is an .insn pseudo-mnemonic. */
+#define S390_INSTR_FLAG_PSEUDO_MNEMONIC 0x100
+
/* The opcode table is an array of struct s390_opcode. */
struct s390_opcode
diff --git a/opcodes/s390-opc.c b/opcodes/s390-opc.c
index 377a4a915893..10482fbc1e01 100644
--- a/opcodes/s390-opc.c
+++ b/opcodes/s390-opc.c
@@ -774,37 +774,37 @@ unused_s390_operands_static_asserts (void)
const struct s390_opcode s390_opformats[] =
{
- { "e", OP8(0x00LL), MASK_E, INSTR_E, 3, 0, 0, NULL },
- { "ri", OP8(0x00LL), MASK_RI_RI, INSTR_RI_RI, 3, 0, 0, NULL },
- { "rie", OP8(0x00LL), MASK_RIE_RRP, INSTR_RIE_RRP, 3, 0, 0, NULL },
- { "ril", OP8(0x00LL), MASK_RIL_RP, INSTR_RIL_RP, 3, 0, 0, NULL },
- { "rilu", OP8(0x00LL), MASK_RIL_RU, INSTR_RIL_RU, 3, 0, 0, NULL },
- { "ris", OP8(0x00LL), MASK_RIS_RURDI, INSTR_RIS_RURDI, 3, 6, 0, NULL },
- { "rr", OP8(0x00LL), MASK_RR_RR, INSTR_RR_RR, 3, 0, 0, NULL },
- { "rre", OP8(0x00LL), MASK_RRE_RR, INSTR_RRE_RR, 3, 0, 0, NULL },
- { "rrf", OP8(0x00LL), MASK_RRF_RURR, INSTR_RRF_RURR, 3, 0, 0, NULL },
- { "rrs", OP8(0x00LL), MASK_RRS_RRRDU, INSTR_RRS_RRRDU, 3, 6, 0, NULL },
- { "rs", OP8(0x00LL), MASK_RS_RRRD, INSTR_RS_RRRD, 3, 0, 0, NULL },
- { "rse", OP8(0x00LL), MASK_RSE_RRRD, INSTR_RSE_RRRD, 3, 0, 0, NULL },
- { "rsi", OP8(0x00LL), MASK_RSI_RRP, INSTR_RSI_RRP, 3, 0, 0, NULL },
- { "rsy", OP8(0x00LL), MASK_RSY_RRRD, INSTR_RSY_RRRD, 3, 3, 0, NULL },
- { "rx", OP8(0x00LL), MASK_RX_RRRD, INSTR_RX_RRRD, 3, 0, 0, NULL },
- { "rxe", OP8(0x00LL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 3, 0, 0, NULL },
- { "rxf", OP8(0x00LL), MASK_RXF_RRRDR, INSTR_RXF_RRRDR, 3, 0, 0, NULL },
- { "rxy", OP8(0x00LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 3, 3, 0, NULL },
- { "s", OP8(0x00LL), MASK_S_RD, INSTR_S_RD, 3, 0, 0, NULL },
- { "si", OP8(0x00LL), MASK_SI_URD, INSTR_SI_URD, 3, 0, 0, NULL },
- { "siy", OP8(0x00LL), MASK_SIY_URD, INSTR_SIY_URD, 3, 3, 0, NULL },
- { "sil", OP8(0x00LL), MASK_SIL_RDI, INSTR_SIL_RDI, 3, 6, 0, NULL },
- { "ss", OP8(0x00LL), MASK_SS_RRRDRD, INSTR_SS_RRRDRD, 3, 0, 0, NULL },
- { "sse", OP8(0x00LL), MASK_SSE_RDRD, INSTR_SSE_RDRD, 3, 0, 0, NULL },
- { "ssf", OP8(0x00LL), MASK_SSF_RRDRD, INSTR_SSF_RRDRD, 3, 0, 0, NULL },
- { "vrv", OP8(0x00LL), MASK_VRV_VVXRDU, INSTR_VRV_VVXRDU, 3, 9, 0, NULL },
- { "vri", OP8(0x00LL), MASK_VRI_VVUUU, INSTR_VRI_VVUUU, 3, 9, 0, NULL },
- { "vrx", OP8(0x00LL), MASK_VRX_VRRDU, INSTR_VRX_VRRDU, 3, 9, 0, NULL },
- { "vrs", OP8(0x00LL), MASK_VRS_RVRDU, INSTR_VRS_RVRDU, 3, 9, 0, NULL },
- { "vrr", OP8(0x00LL), MASK_VRR_VVV0UUU, INSTR_VRR_VVV0UUU, 3, 9, 0, NULL },
- { "vsi", OP8(0x00LL), MASK_VSI_URDV, INSTR_VSI_URDV, 3, 10, 0, NULL },
+ { "e", OP8(0x00LL), MASK_E, INSTR_E, 3, 0, 256, NULL },
+ { "ri", OP8(0x00LL), MASK_RI_RI, INSTR_RI_RI, 3, 0, 256, NULL },
+ { "rie", OP8(0x00LL), MASK_RIE_RRP, INSTR_RIE_RRP, 3, 0, 256, NULL },
+ { "ril", OP8(0x00LL), MASK_RIL_RP, INSTR_RIL_RP, 3, 0, 256, NULL },
+ { "rilu", OP8(0x00LL), MASK_RIL_RU, INSTR_RIL_RU, 3, 0, 256, NULL },
+ { "ris", OP8(0x00LL), MASK_RIS_RURDI, INSTR_RIS_RURDI, 3, 6, 256, NULL },
+ { "rr", OP8(0x00LL), MASK_RR_RR, INSTR_RR_RR, 3, 0, 256, NULL },
+ { "rre", OP8(0x00LL), MASK_RRE_RR, INSTR_RRE_RR, 3, 0, 256, NULL },
+ { "rrf", OP8(0x00LL), MASK_RRF_RURR, INSTR_RRF_RURR, 3, 0, 256, NULL },
+ { "rrs", OP8(0x00LL), MASK_RRS_RRRDU, INSTR_RRS_RRRDU, 3, 6, 256, NULL },
+ { "rs", OP8(0x00LL), MASK_RS_RRRD, INSTR_RS_RRRD, 3, 0, 256, NULL },
+ { "rse", OP8(0x00LL), MASK_RSE_RRRD, INSTR_RSE_RRRD, 3, 0, 256, NULL },
+ { "rsi", OP8(0x00LL), MASK_RSI_RRP, INSTR_RSI_RRP, 3, 0, 256, NULL },
+ { "rsy", OP8(0x00LL), MASK_RSY_RRRD, INSTR_RSY_RRRD, 3, 3, 256, NULL },
+ { "rx", OP8(0x00LL), MASK_RX_RRRD, INSTR_RX_RRRD, 3, 0, 256, NULL },
+ { "rxe", OP8(0x00LL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 3, 0, 256, NULL },
+ { "rxf", OP8(0x00LL), MASK_RXF_RRRDR, INSTR_RXF_RRRDR, 3, 0, 256, NULL },
+ { "rxy", OP8(0x00LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 3, 3, 256, NULL },
+ { "s", OP8(0x00LL), MASK_S_RD, INSTR_S_RD, 3, 0, 256, NULL },
+ { "si", OP8(0x00LL), MASK_SI_URD, INSTR_SI_URD, 3, 0, 256, NULL },
+ { "siy", OP8(0x00LL), MASK_SIY_URD, INSTR_SIY_URD, 3, 3, 256, NULL },
+ { "sil", OP8(0x00LL), MASK_SIL_RDI, INSTR_SIL_RDI, 3, 6, 256, NULL },
+ { "ss", OP8(0x00LL), MASK_SS_RRRDRD, INSTR_SS_RRRDRD, 3, 0, 256, NULL },
+ { "sse", OP8(0x00LL), MASK_SSE_RDRD, INSTR_SSE_RDRD, 3, 0, 256, NULL },
+ { "ssf", OP8(0x00LL), MASK_SSF_RRDRD, INSTR_SSF_RRDRD, 3, 0, 256, NULL },
+ { "vrv", OP8(0x00LL), MASK_VRV_VVXRDU, INSTR_VRV_VVXRDU, 3, 9, 256, NULL },
+ { "vri", OP8(0x00LL), MASK_VRI_VVUUU, INSTR_VRI_VVUUU, 3, 9, 256, NULL },
+ { "vrx", OP8(0x00LL), MASK_VRX_VRRDU, INSTR_VRX_VRRDU, 3, 9, 256, NULL },
+ { "vrs", OP8(0x00LL), MASK_VRS_RVRDU, INSTR_VRS_RVRDU, 3, 9, 256, NULL },
+ { "vrr", OP8(0x00LL), MASK_VRR_VVV0UUU, INSTR_VRR_VVV0UUU, 3, 9, 256, NULL },
+ { "vsi", OP8(0x00LL), MASK_VSI_URDV, INSTR_VSI_URDV, 3, 10, 256, NULL },
};
const int s390_num_opformats =
--
2.40.1
next prev parent reply other threads:[~2024-02-15 15:58 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-02-15 15:58 [PATCH 00/14] s390: Enhancements to working with addressing operands Jens Remus
2024-02-15 15:58 ` [PATCH 01/14] s390: Lower severity of assembler syntax errors from fatal to error Jens Remus
2024-02-15 15:58 ` [PATCH 02/14] s390: Enhance handling of syntax errors in assembler Jens Remus
2024-02-15 15:58 ` [PATCH 03/14] s390: Do not erroneously use base operand value for length operand Jens Remus
2024-02-15 15:58 ` [PATCH 04/14] s390: Correct setting of highgprs flag in ELF output Jens Remus
2024-02-15 15:58 ` [PATCH 05/14] s390: Assemble processor specific test cases for their processor Jens Remus
2024-02-15 15:58 ` [PATCH 06/14] s390: Add comments to assembler operand parsing logic Jens Remus
2024-02-15 15:58 ` [PATCH 07/14] s390: Add test cases for base/index register 0 Jens Remus
2024-02-15 15:58 ` [PATCH 08/14] s390: Add test case for disassembler option warn-areg-zero Jens Remus
2024-02-15 15:58 ` [PATCH 09/14] s390: Revise s390-specific assembler option descriptions Jens Remus
2024-02-15 15:58 ` Jens Remus [this message]
2024-02-15 15:58 ` [PATCH 11/14] s390: Print base register 0 as "0" in disassembly Jens Remus
2024-02-15 15:58 ` [PATCH 12/14] s390: Allow to explicitly omit base register operand in assembly Jens Remus
2024-02-15 15:58 ` [PATCH 13/14] s390: Provide operand number in assembler warning and error messages Jens Remus
2024-02-15 15:58 ` [PATCH 14/14] s390: Be more verbose about missing operand type Jens Remus
2024-03-01 12:24 ` [PATCH 00/14] s390: Enhancements to working with addressing operands Jens Remus
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