From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-pf1-x429.google.com (mail-pf1-x429.google.com [IPv6:2607:f8b0:4864:20::429]) by sourceware.org (Postfix) with ESMTPS id 9EC3A3858C56 for ; Tue, 20 Feb 2024 17:56:29 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 9EC3A3858C56 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=gmail.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 9EC3A3858C56 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=2607:f8b0:4864:20::429 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1708451791; cv=none; b=mJQytdMbYgL42L2ZcyiZ59AEphmclsZC+MHoOkwFRgRxFvhln0dphvG5Rcjd6yz+aMYpbRwukEroIedK1sZ7l/qTKKDLO/3BUiPn/beXngQzRkjhrWWEWGKw39Pcr2xLYP5QXbSWnndogm17s1MPexjPwCCrWmnexqTr156h41k= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1708451791; c=relaxed/simple; bh=0BlLHj6R8Z5GZGNJhT3gr2QH6zg4djp/VheAlgPGrcE=; h=DKIM-Signature:From:To:Subject:Date:Message-ID:MIME-Version; b=IoJFzRUfieTGTaatXzGEpVuco39Ar8O9BnYhwZgjSN6dICXB5zKvoDbCP80+0ZpDgZNAXZvGbUz9IMiTBYBnc2pLfKnz1trnWAbhBPM2/W1uq/N1787IHbCX4++/qjfNaa/cubPEcc/Jv7HmUCTYQSwP8FZ8R926dggEltJkTkQ= ARC-Authentication-Results: i=1; server2.sourceware.org Received: by mail-pf1-x429.google.com with SMTP id d2e1a72fcca58-6e28029f2b4so88364b3a.1 for ; Tue, 20 Feb 2024 09:56:29 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1708451788; x=1709056588; darn=sourceware.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=D7VclN+GWmO8MMSWo0Dp0TbyfivX9IDaVLooPsUNv4Y=; b=b8+mgeUAjH2B2pYZLkuol8IjLPFQvFdoPHsXDZhEhP4O9G+GW5JXxO56/HEoJOZELs TtgxB6mElx8NxFqvmQgQwiQsYFSUhMpdwxgO1dwV0D/GItx1UoAX4G1jwKivWMKCKdVT nYLVe47FrnQmQBin51+/Qoa6Bje4uupN5dsOT8dzMHVYJv8Uu+I5SW3VgF15vZrYmRDg OaVHAaGQY3Xpa81lvZ6QNtkYi1TjP/DdVcPoYJRQHsuMW22HJzFvBFy8HrUgnlHu9YWB V0MbwDqWqvJTGl51tPQezOOblEZzvpWjSnQD9cZhP3R9TMu094HrpT/P6oZBE3Mztcl5 BLJw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1708451788; x=1709056588; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=D7VclN+GWmO8MMSWo0Dp0TbyfivX9IDaVLooPsUNv4Y=; b=E97b2TJ1QY7ifEaMiuaz8ca0zgbWNV1r4uf1sYWM67AIbWAzHqTVYxTcbHCuXxNUyv itp8wX0UopZZKtC2y5DwHUJrF9/1Bn466LJIdWKY6Kq6C40NRGrjYVf9lmUwBf3ANljh 2MD5k5oCXd8M4RmJtaTeLtV4QQWgidkTnhj+q+LdE0G7jg77Lv5TqFxRonAlDZ/AsRDP 7VMJGjL19GhD6NUj1WdQAw/z8kVmsoDTSnHEoiKHXBIUeLq3b8jJf0gknVUThMB2z07A +XZQ8gbSQQ74l1WwCN7CQEpw+G9qM+XlG8W8Icsk7sZuWrqToYp+VlWdnSniKdEU/f5+ Xj0g== X-Gm-Message-State: AOJu0YxnoWkJS1nDWgCKoQl6mlC2UIGKekcelNC72qlNXpDOTLpxv9nA dL5gbSzv3YiLH2ZjozBxFfkNoLG3iH25lcdDQiF7laj56NbIuz0FfSjLF51l9d1tJA== X-Google-Smtp-Source: AGHT+IHTOdvxBj9SfXb0NoI/W5P40lAzsmvtHfj0Md1Llun58QeiheudUlHzWLOQugg/aen6mDePcg== X-Received: by 2002:a05:6a21:7895:b0:1a0:b4fa:b90c with SMTP id bf21-20020a056a21789500b001a0b4fab90cmr2427389pzc.5.1708451787927; Tue, 20 Feb 2024 09:56:27 -0800 (PST) Received: from localhost (zz20184013906F627101.userreverse.dion.ne.jp. [111.98.113.1]) by smtp.gmail.com with ESMTPSA id h4-20020a170902eec400b001db7ed7ac34sm6465631plb.297.2024.02.20.09.56.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 20 Feb 2024 09:56:27 -0800 (PST) From: Tatsuyuki Ishi To: binutils@sourceware.org Cc: i@maskray.me, nelson@rivosinc.com, rui314@gmail.com, ruiu@bluewhale.systems, Tatsuyuki Ishi Subject: [PATCH v4 3/9] RISC-V: Add assembly support for TLSDESC. Date: Wed, 21 Feb 2024 02:55:50 +0900 Message-ID: <20240220175556.304692-4-ishitatsuyuki@gmail.com> X-Mailer: git-send-email 2.43.2 In-Reply-To: <20240220175556.304692-1-ishitatsuyuki@gmail.com> References: <20230817180852.121628-2-ishitatsuyuki@gmail.com> <20240220175556.304692-1-ishitatsuyuki@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-11.3 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM,GIT_PATCH_0,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: gas/ * tc-riscv.c (percent_op_*): Add support for %tlsdesc_hi, %tlsdesc_load_lo, %tlsdesc_add_lo and %tlsdesc_call. percent_op_rtype renamed to percent_op_relax_only as this matcher is extended to handle jalr as well which is not R-type. (riscv_ip): Apply the percent_op_relax_only rename and update comment. (md_apply_fix): Add TLSDESC_* to relaxable list. Add TLSDESC_HI20 to TLS relocation check list. * testsuite/gas/riscv/tlsdesc.*: New test cases for TLSDESC relocation generation. opcodes/ * riscv-opc.c (riscv_opcodes): Add a new syntax for jalr with %tlsdesc_call annotations. --- v4: Change test case to use objdump: -dr, and remove the rv32 arch restriction. gas/config/tc-riscv.c | 18 +++++++++++----- gas/testsuite/gas/riscv/tlsdesc.d | 36 +++++++++++++++++++++++++++++++ gas/testsuite/gas/riscv/tlsdesc.s | 24 +++++++++++++++++++++ opcodes/riscv-opc.c | 1 + 4 files changed, 74 insertions(+), 5 deletions(-) create mode 100644 gas/testsuite/gas/riscv/tlsdesc.d create mode 100644 gas/testsuite/gas/riscv/tlsdesc.s diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c index a4161420128..55c527520d5 100644 --- a/gas/config/tc-riscv.c +++ b/gas/config/tc-riscv.c @@ -2202,6 +2202,7 @@ static const struct percent_op_match percent_op_utype[] = {"tprel_hi", BFD_RELOC_RISCV_TPREL_HI20}, {"pcrel_hi", BFD_RELOC_RISCV_PCREL_HI20}, {"got_pcrel_hi", BFD_RELOC_RISCV_GOT_HI20}, + {"tlsdesc_hi", BFD_RELOC_RISCV_TLSDESC_HI20}, {"tls_ie_pcrel_hi", BFD_RELOC_RISCV_TLS_GOT_HI20}, {"tls_gd_pcrel_hi", BFD_RELOC_RISCV_TLS_GD_HI20}, {"hi", BFD_RELOC_RISCV_HI20}, @@ -2213,6 +2214,8 @@ static const struct percent_op_match percent_op_itype[] = {"lo", BFD_RELOC_RISCV_LO12_I}, {"tprel_lo", BFD_RELOC_RISCV_TPREL_LO12_I}, {"pcrel_lo", BFD_RELOC_RISCV_PCREL_LO12_I}, + {"tlsdesc_load_lo", BFD_RELOC_RISCV_TLSDESC_LOAD_LO12}, + {"tlsdesc_add_lo", BFD_RELOC_RISCV_TLSDESC_ADD_LO12}, {0, 0} }; @@ -2224,8 +2227,9 @@ static const struct percent_op_match percent_op_stype[] = {0, 0} }; -static const struct percent_op_match percent_op_rtype[] = +static const struct percent_op_match percent_op_relax_only[] = { + {"tlsdesc_call", BFD_RELOC_RISCV_TLSDESC_CALL}, {"tprel_add", BFD_RELOC_RISCV_TPREL_ADD}, {0, 0} }; @@ -3386,10 +3390,10 @@ riscv_ip (char *str, struct riscv_cl_insn *ip, expressionS *imm_expr, *imm_reloc = BFD_RELOC_RISCV_LO12_I; goto load_store; case '1': - /* This is used for TLS, where the fourth operand is - %tprel_add, to get a relocation applied to an add - instruction, for relaxation to use. */ - p = percent_op_rtype; + /* This is used for TLS relocations that acts as relaxation + markers and do not change the instruction encoding, + i.e. %tprel_add and %tlsdesc_call. */ + p = percent_op_relax_only; goto alu_op; case '0': /* AMO displacement, which must be zero. */ load_store: @@ -4252,6 +4256,7 @@ md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED) case BFD_RELOC_RISCV_TPREL_LO12_I: case BFD_RELOC_RISCV_TPREL_LO12_S: case BFD_RELOC_RISCV_TPREL_ADD: + case BFD_RELOC_RISCV_TLSDESC_HI20: relaxable = true; /* Fall through. */ @@ -4425,6 +4430,9 @@ md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED) case BFD_RELOC_RISCV_CALL: case BFD_RELOC_RISCV_CALL_PLT: + case BFD_RELOC_RISCV_TLSDESC_LOAD_LO12: + case BFD_RELOC_RISCV_TLSDESC_ADD_LO12: + case BFD_RELOC_RISCV_TLSDESC_CALL: relaxable = true; break; diff --git a/gas/testsuite/gas/riscv/tlsdesc.d b/gas/testsuite/gas/riscv/tlsdesc.d new file mode 100644 index 00000000000..5cd26ac3280 --- /dev/null +++ b/gas/testsuite/gas/riscv/tlsdesc.d @@ -0,0 +1,36 @@ +#source: tlsdesc.s +#objdump: -dr + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+00 <_start>: +[ ]+0:[ ]+00000517[ ]+auipc[ ]+a0,0x0 +[ ]+0:[ ]+R_RISCV_TLSDESC_HI20[ ]+sg1 +[ ]+0:[ ]+R_RISCV_RELAX[ ]+\*ABS\* +[ ]+4:[ ]+00052283[ ]+lw[ ]+t0,0\(a0\) # 0( <.*>)? +[ ]+4:[ ]+R_RISCV_TLSDESC_LOAD_LO12[ ]+\.desc1 +[ ]+4:[ ]+R_RISCV_RELAX[ ]+\*ABS\* +[ ]+8:[ ]+00050513[ ]+mv[ ]+a0,a0 +[ ]+8:[ ]+R_RISCV_TLSDESC_ADD_LO12[ ]+\.desc1 +[ ]+8:[ ]+R_RISCV_RELAX[ ]+\*ABS\* +[ ]+c:[ ]+000282e7[ ]+jalr[ ]+t0,t0 +[ ]+c:[ ]+R_RISCV_TLSDESC_CALL[ ]+\.desc1 +[ ]+c:[ ]+R_RISCV_RELAX[ ]+\*ABS\* + +0+10 <\.desc2>: +[ ]+10:[ ]+00000517[ ]+auipc[ ]+a0,0x0 +[ ]+10:[ ]+R_RISCV_TLSDESC_HI20[ ]+sl1 +[ ]+10:[ ]+R_RISCV_RELAX[ ]+\*ABS\* +[ ]+14:[ ]+00052283[ ]+lw[ ]+t0,0\(a0\) # 10( <.*>)? +[ ]+14:[ ]+R_RISCV_TLSDESC_LOAD_LO12[ ]+\.desc2 +[ ]+14:[ ]+R_RISCV_RELAX[ ]+\*ABS\* +[ ]+18:[ ]+00050513[ ]+mv[ ]+a0,a0 +[ ]+18:[ ]+R_RISCV_TLSDESC_ADD_LO12[ ]+\.desc2 +[ ]+18:[ ]+R_RISCV_RELAX[ ]+\*ABS\* +[ ]+1c:[ ]+000282e7[ ]+jalr[ ]+t0,t0 +[ ]+1c:[ ]+R_RISCV_TLSDESC_CALL[ ]+\.desc2 +[ ]+1c:[ ]+R_RISCV_RELAX[ ]+\*ABS\* +[ ]+20:[ ]+00008067[ ]+ret diff --git a/gas/testsuite/gas/riscv/tlsdesc.s b/gas/testsuite/gas/riscv/tlsdesc.s new file mode 100644 index 00000000000..15468d5f947 --- /dev/null +++ b/gas/testsuite/gas/riscv/tlsdesc.s @@ -0,0 +1,24 @@ + .section .tbss,"awT",@nobits + .global sg1 +sg1: + .zero 4 +sl1: + .zero 4 + + .text + .globl _start + .type _start,@function +_start: +.desc1: + auipc a0, %tlsdesc_hi(sg1) + lw t0, %tlsdesc_load_lo(.desc1)(a0) + addi a0, a0, %tlsdesc_add_lo(.desc1) + jalr t0, t0, %tlsdesc_call(.desc1) + +.desc2: + auipc a0, %tlsdesc_hi(sl1) + lw t0, %tlsdesc_load_lo(.desc2)(a0) + addi a0, a0, %tlsdesc_add_lo(.desc2) + jalr t0, t0, %tlsdesc_call(.desc2) + + ret diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c index fdd05ac75dc..dcc592e1fc2 100644 --- a/opcodes/riscv-opc.c +++ b/opcodes/riscv-opc.c @@ -384,6 +384,7 @@ const struct riscv_opcode riscv_opcodes[] = {"jalr", 0, INSN_CLASS_I, "s,j", MATCH_JALR|(X_RA << OP_SH_RD), MASK_JALR|MASK_RD, match_opcode, INSN_ALIAS|INSN_JSR }, {"jalr", 0, INSN_CLASS_I, "d,s", MATCH_JALR, MASK_JALR|MASK_IMM, match_opcode, INSN_ALIAS|INSN_JSR }, {"jalr", 0, INSN_CLASS_I, "d,o(s)", MATCH_JALR, MASK_JALR, match_opcode, INSN_JSR }, +{"jalr", 0, INSN_CLASS_I, "d,s,1", MATCH_JALR, MASK_JALR|MASK_IMM, match_opcode, INSN_JSR }, {"jalr", 0, INSN_CLASS_I, "d,s,j", MATCH_JALR, MASK_JALR, match_opcode, INSN_JSR }, {"j", 0, INSN_CLASS_C, "Ca", MATCH_C_J, MASK_C_J, match_opcode, INSN_ALIAS|INSN_BRANCH }, {"j", 0, INSN_CLASS_I, "a", MATCH_JAL, MASK_JAL|MASK_RD, match_opcode, INSN_ALIAS|INSN_BRANCH }, -- 2.43.2