diff --git a/gas/testsuite/gas/aarch64/sysreg/fp8-feature-enables-fpmr.d b/gas/testsuite/gas/aarch64/sysreg/fp8-feature-enables-fpmr.d new file mode 100644 index 00000000000..edef376de87 --- /dev/null +++ b/gas/testsuite/gas/aarch64/sysreg/fp8-feature-enables-fpmr.d @@ -0,0 +1,12 @@ +#name: Test that fpmr register is gated and available via the fp8 feature +#source: fpmr.s +#as: -march=armv9.2-a+fp8 +#objdump: -dr + +.*: file format .* + +Disassembly of section \.text: + +0+ <.*>: + 0: d53b4440 mrs x0, fpmr + 4: d51b4440 msr fpmr, x0 diff --git a/gas/testsuite/gas/aarch64/sysreg/fpmr-unsupported-by-default.d b/gas/testsuite/gas/aarch64/sysreg/fpmr-unsupported-by-default.d new file mode 100644 index 00000000000..c0b30c2e149 --- /dev/null +++ b/gas/testsuite/gas/aarch64/sysreg/fpmr-unsupported-by-default.d @@ -0,0 +1,4 @@ +#name: Test that fpmr register is not supported by default +#source: fpmr.s +#as: -march=armv9.2-a +#error_output: fpmr-unsupported-by-default.l diff --git a/gas/testsuite/gas/aarch64/sysreg/fpmr-unsupported-by-default.l b/gas/testsuite/gas/aarch64/sysreg/fpmr-unsupported-by-default.l new file mode 100644 index 00000000000..43de01860c4 --- /dev/null +++ b/gas/testsuite/gas/aarch64/sysreg/fpmr-unsupported-by-default.l @@ -0,0 +1,3 @@ +[^:]*: Assembler messages: +.*: Error: selected processor does not support system register name 'fpmr' +.*: Error: selected processor does not support system register name 'fpmr' diff --git a/gas/testsuite/gas/aarch64/sysreg/fpmr.s b/gas/testsuite/gas/aarch64/sysreg/fpmr.s new file mode 100644 index 00000000000..302847daaba --- /dev/null +++ b/gas/testsuite/gas/aarch64/sysreg/fpmr.s @@ -0,0 +1,4 @@ + .text + + mrs x0, fpmr + msr fpmr, x0 diff --git a/opcodes/aarch64-sys-regs.def b/opcodes/aarch64-sys-regs.def index 8b65673a5d6..fabcea1fc7d 100644 --- a/opcodes/aarch64-sys-regs.def +++ b/opcodes/aarch64-sys-regs.def @@ -423,6 +423,7 @@ SYSREG ("far_el3", CPENC (3,6,6,0,0), 0, AARCH64_NO_FEATURES) SYSREG ("fpcr", CPENC (3,3,4,4,0), 0, AARCH64_NO_FEATURES) SYSREG ("fpexc32_el2", CPENC (3,4,5,3,0), 0, AARCH64_NO_FEATURES) + SYSREG ("fpmr", CPENC (3,3,4,4,2), F_ARCHEXT, AARCH64_FEATURE (FP8)) SYSREG ("fpsr", CPENC (3,3,4,4,1), 0, AARCH64_NO_FEATURES) SYSREG ("gcspr_el0", CPENC (3,3,2,5,1), F_ARCHEXT, AARCH64_FEATURE (GCS)) SYSREG ("gcspr_el1", CPENC (3,0,2,5,1), F_ARCHEXT, AARCH64_FEATURE (GCS))