From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail.loongson.cn (mail.loongson.cn [114.242.206.163]) by sourceware.org (Postfix) with ESMTP id E55F938930DE; Wed, 8 May 2024 09:29:34 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org E55F938930DE Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=loongson.cn Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=loongson.cn ARC-Filter: OpenARC Filter v1.0.0 sourceware.org E55F938930DE Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=114.242.206.163 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1715160600; cv=none; b=bClLTrr/2WCP+GGLBGr8vJhb3+J/BTPBpn0160PYqOuNTSDv7BiVVIwg7Sy57o6Bpded6auTSk5LD9x12st/bImZxlPMwLH4eOyQAK4PCpGXOzDOrWXhwfVIf9vK7CohL9XWoj1onhNJVdk0TGgO7wd5Fj4WAbgzEvTQH8C/0sM= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1715160600; c=relaxed/simple; bh=ZA5bVhkN9S5b5g1f05MKZSelgjA5DzJUNF+6bQEB36g=; h=From:To:Subject:Date:Message-ID:MIME-Version; b=DCSbXYAHZTP7wRP+CBg1hUfWvw/otgKBNOZE1Vzx6+mYBy0tg5dxHWxSBGqH+3rqB/J1EIjReheRnTzGXq/eWsbXxqkHmh2B3rETBVC3o58MtJtBkUC6D78515T1pq7wd7aswurw/dufOJLk7hSjDowshhNnDVvf2XcHstbXj+s= ARC-Authentication-Results: i=1; server2.sourceware.org Received: from loongson.cn (unknown [113.200.148.30]) by gateway (Coremail) with SMTP id _____8AxJ+n4RTtm0U0JAA--.12313S3; Wed, 08 May 2024 17:29:28 +0800 (CST) Received: from linux.localdomain (unknown [113.200.148.30]) by localhost.localdomain (Coremail) with SMTP id AQAAf8DxLlXnRTtmzHQVAA--.24860S3; Wed, 08 May 2024 17:29:17 +0800 (CST) From: Tiezhu Yang To: binutils@sourceware.org, gdb-patches@sourceware.org Cc: Jim Wilson , Jeff Johnston , Kevin Buettner Subject: [PATCH 1/2] binutils: Remove Itanium (IA-64) architecture Date: Wed, 8 May 2024 17:29:09 +0800 Message-ID: <20240508092911.24823-2-yangtiezhu@loongson.cn> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20240508092911.24823-1-yangtiezhu@loongson.cn> References: <20240508092911.24823-1-yangtiezhu@loongson.cn> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID:AQAAf8DxLlXnRTtmzHQVAA--.24860S3 X-CM-SenderInfo: p1dqw3xlh2x3gn0dqz5rrqw2lrqou0/ X-Coremail-Antispam: 1Uk129KBj9PXoW8Xw1rWFWxJw4rGFWDArWxZw1kp5X_Xr4kGr yxAoW3Xw4rta1fGry7Xa9F9asrJFWxWF18KF47tr98Aw17Kan3G3yDKr1DZ3W5u3yfXr1k Xry3C34xAas5Gw4UKrn7l-sFpf9Il3svdjkaLaAFLSUrUUUUUb8apTn2vfkv8UJUUUU8wc xFpf9Il3svdxBIdaVrnO8qx4xG64xvF2IEw4CE5I8CrVC2j2WlIxkvb40EIxkG14v26r4j 6ryUYxn0WfASr-VFAUDa7-sFnT9fnUUIcSsGvfJTRUUUbIkYFVCjjxCrM7AC8VAFwI0_Jr 0_Gr1l1xkIjI8I6I8E6xAIw20EY4v20xvaj40_Wr0E3s1l1IIY67AEw4v_Jr0_Jr4l8cAv FVAK0II2c7xJM28CjxkF64kEwVA0rcxSw2x7M28EF7xvwVC0I7IYx2IY67AKxVWUCVW8Jw A2z4x0Y4vE2Ix0cI8IcVCY1x0267AKxVW8JVWxJwA2z4x0Y4vEx4A2jsIE14v26r4UJVWx Jr1l84ACjcxK6I8E87Iv6xkF7I0E14v26r4UJVWxJr1le2I262IYc4CY6c8Ij28IcVAaY2 xG8wAqjxCEc2xF0cIa020Ex4CE44I27wAqx4xG64xvF2IEw4CE5I8CrVC2j2WlYx0E2Ix0 cI8IcVAFwI0_Jrv_JF1lYx0Ex4A2jsIE14v26r1j6r4UMcvjeVCFs4IE7xkEbVWUJVW8Jw ACjcxG0xvY0x0EwIxGrwCF04k20xvY0x0EwIxGrwCFx2IqxVCFs4IE7xkEbVWUJVW8JwC2 0s026c02F40E14v26r1j6r18MI8I3I0E7480Y4vE14v26r106r1rMI8E67AF67kF1VAFwI 0_JF0_Jw1lIxkvb40EIxkG14v26r4j6ryUMIIYrxkI7VAKI48JMIIF0xvE2Ix0cI8IcVAF wI0_Jr0_JF4lIxAIcVC0I7IYx2IY6xkF7I0E14v26r1j6r4UMIIF0xvE42xK8VAvwI8IcI k0rVWUJVWUCwCI42IY6I8E87Iv67AKxVWUJVW8JwCI42IY6I8E87Iv6xkF7I0E14v26r1j 6r4UYxBIdaVFxhVjvjDU0xZFpf9x07U_EfrUUUUU= X-Spam-Status: No, score=-11.2 required=5.0 tests=BAYES_00,GIT_PATCH_0,KAM_DMARC_STATUS,KAM_STOCKGEN,SPF_HELO_NONE,SPF_PASS,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: The Itanium architecture is obsolete, after the upstream Linux kernel commit cf8e8658100d ("arch: Remove Itanium (IA-64) architecture"), the IA-64 port has been removed from the Linux kernel, so also remove the IA-64 specific code from binutils. Link: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/co= mmit/?id=3Dcf8e8658100d Signed-off-by: Tiezhu Yang --- bfd/.gitignore | 2 - bfd/Makefile.am | 23 +- bfd/Makefile.in | 29 +- bfd/archures.c | 5 - bfd/bfd-in2.h | 3 - bfd/coff-ia64.c | 214 - bfd/coffcode.h | 11 - bfd/config.bfd | 15 - bfd/configure | 107 +- bfd/configure.ac | 7 - bfd/configure.com | 9 - bfd/configure.host | 4 - bfd/cpu-ia64-opc.c | 669 - bfd/cpu-ia64.c | 50 - bfd/elf-eh-frame.c | 4 - bfd/elf64-ia64-vms.c | 5630 -------- bfd/elfnn-ia64.c | 5116 ------- bfd/elfxx-ia64.c | 764 - bfd/elfxx-ia64.h | 40 - bfd/libbfd-in.h | 4 - bfd/libbfd.h | 4 - bfd/makefile.vms | 8 - bfd/peXXigen.c | 2 - bfd/pei-ia64.c | 38 - bfd/targets.c | 19 - bfd/vms-lib.c | 39 +- binutils/MAINTAINERS | 1 - binutils/Makefile.am | 7 +- binutils/Makefile.in | 10 +- binutils/NEWS | 2 + binutils/configure | 100 +- binutils/configure.com | 1 - binutils/makefile.vms | 4 +- binutils/readelf.c | 1329 +- binutils/testsuite/binutils-all/nm.exp | 3 +- binutils/testsuite/binutils-all/objcopy.exp | 10 +- binutils/testsuite/binutils-all/objdump.exp | 1 - .../testsuite/binutils-all/testranges-ia64.d | 15 - .../testsuite/binutils-all/testranges-ia64.s | 57 - binutils/testsuite/binutils-all/testranges.d | 1 - binutils/testsuite/lib/binutils-common.exp | 3 +- binutils/unwind-ia64.c | 1164 -- binutils/unwind-ia64.h | 32 - config.guess | 19 - config.rpath | 30 +- config.sub | 2 +- config/picflag.m4 | 5 - config/tcl.m4 | 19 +- config/unwind_ipinfo.m4 | 2 - configure | 15 - configure.ac | 15 - gas/Makefile.am | 3 - gas/Makefile.in | 6 - gas/config/obj-coff-seh.c | 3 - gas/config/tc-ia64.c | 11982 ---------------- gas/config/tc-ia64.h | 331 - gas/config/te-ia64aix.h | 23 - gas/configure | 100 +- gas/configure.com | 16 - gas/configure.tgt | 10 +- gas/doc/as.texi | 18 - gas/doc/c-ia64.texi | 201 - gas/testsuite/gas/all/gas.exp | 3 - gas/testsuite/gas/all/local-label-overflow.d | 2 +- gas/testsuite/gas/elf/bad-bss.d | 2 +- gas/testsuite/gas/elf/bss.d | 2 +- gas/testsuite/gas/elf/elf.exp | 4 - gas/testsuite/gas/elf/file.s | 3 - gas/testsuite/gas/ia64/alias-ilp32.d | 28 - gas/testsuite/gas/ia64/alias.d | 35 - gas/testsuite/gas/ia64/alias.s | 11 - gas/testsuite/gas/ia64/align.d | 7 - gas/testsuite/gas/ia64/align.s | 3 - gas/testsuite/gas/ia64/alloc.l | 11 - gas/testsuite/gas/ia64/alloc.s | 14 - gas/testsuite/gas/ia64/bundling.d | 14 - gas/testsuite/gas/ia64/bundling.s | 15 - gas/testsuite/gas/ia64/dependency-1.d | 17 - gas/testsuite/gas/ia64/dependency-1.s | 7 - gas/testsuite/gas/ia64/dv-branch.d | 15 - gas/testsuite/gas/ia64/dv-branch.s | 16 - gas/testsuite/gas/ia64/dv-entry-err.l | 3 - gas/testsuite/gas/ia64/dv-entry-err.s | 15 - gas/testsuite/gas/ia64/dv-imply.d | 45 - gas/testsuite/gas/ia64/dv-imply.s | 44 - gas/testsuite/gas/ia64/dv-mutex-err.l | 13 - gas/testsuite/gas/ia64/dv-mutex-err.s | 33 - gas/testsuite/gas/ia64/dv-mutex.d | 39 - gas/testsuite/gas/ia64/dv-mutex.s | 36 - gas/testsuite/gas/ia64/dv-raw-err.l | 309 - gas/testsuite/gas/ia64/dv-raw-err.s | 625 - gas/testsuite/gas/ia64/dv-safe.d | 21 - gas/testsuite/gas/ia64/dv-safe.s | 19 - gas/testsuite/gas/ia64/dv-srlz.d | 24 - gas/testsuite/gas/ia64/dv-srlz.s | 13 - gas/testsuite/gas/ia64/dv-war-err.l | 3 - gas/testsuite/gas/ia64/dv-war-err.s | 9 - gas/testsuite/gas/ia64/dv-waw-err.l | 395 - gas/testsuite/gas/ia64/dv-waw-err.s | 581 - gas/testsuite/gas/ia64/fixup-dump.pl | 12 - gas/testsuite/gas/ia64/forward.d | 15 - gas/testsuite/gas/ia64/forward.s | 27 - gas/testsuite/gas/ia64/global.d | 10 - gas/testsuite/gas/ia64/global.s | 3 - gas/testsuite/gas/ia64/group-1.d | 32 - gas/testsuite/gas/ia64/group-1.s | 10 - gas/testsuite/gas/ia64/group-2.d | 42 - gas/testsuite/gas/ia64/group-2.s | 6 - gas/testsuite/gas/ia64/hint.b-err.l | 3 - gas/testsuite/gas/ia64/hint.b-err.s | 2 - gas/testsuite/gas/ia64/hint.b-warn.l | 3 - gas/testsuite/gas/ia64/hint.b-warn.s | 2 - gas/testsuite/gas/ia64/ia64.exp | 118 - gas/testsuite/gas/ia64/index.l | 42 - gas/testsuite/gas/ia64/index.s | 63 - gas/testsuite/gas/ia64/invalid-ar.l | 125 - gas/testsuite/gas/ia64/invalid-ar.s | 135 - gas/testsuite/gas/ia64/label.l | 3 - gas/testsuite/gas/ia64/label.s | 26 - gas/testsuite/gas/ia64/last.l | 3 - gas/testsuite/gas/ia64/last.s | 12 - gas/testsuite/gas/ia64/ldxmov-1.d | 19 - gas/testsuite/gas/ia64/ldxmov-1.s | 8 - gas/testsuite/gas/ia64/ldxmov-2.l | 5 - gas/testsuite/gas/ia64/ldxmov-2.s | 8 - gas/testsuite/gas/ia64/ltoff22x-1.d | 10 - gas/testsuite/gas/ia64/ltoff22x-1.s | 4 - gas/testsuite/gas/ia64/ltoff22x-2.d | 11 - gas/testsuite/gas/ia64/ltoff22x-2.s | 13 - gas/testsuite/gas/ia64/ltoff22x-3.d | 11 - gas/testsuite/gas/ia64/ltoff22x-3.s | 13 - gas/testsuite/gas/ia64/ltoff22x-4.d | 11 - gas/testsuite/gas/ia64/ltoff22x-4.s | 13 - gas/testsuite/gas/ia64/ltoff22x-5.d | 11 - gas/testsuite/gas/ia64/ltoff22x-5.s | 13 - gas/testsuite/gas/ia64/mov-ar.d | 26 - gas/testsuite/gas/ia64/mov-ar.s | 21 - gas/testsuite/gas/ia64/no-fit.l | 8 - gas/testsuite/gas/ia64/no-fit.s | 33 - gas/testsuite/gas/ia64/nop_x.d | 11 - gas/testsuite/gas/ia64/nop_x.s | 6 - gas/testsuite/gas/ia64/nostkreg.d | 16 - gas/testsuite/gas/ia64/nostkreg.s | 9 - gas/testsuite/gas/ia64/opc-a-err.l | 18 - gas/testsuite/gas/ia64/opc-a-err.s | 24 - gas/testsuite/gas/ia64/opc-a.d | 363 - gas/testsuite/gas/ia64/opc-a.pl | 142 - gas/testsuite/gas/ia64/opc-a.s | 396 - gas/testsuite/gas/ia64/opc-b.d | 1021 -- gas/testsuite/gas/ia64/opc-b.pl | 95 - gas/testsuite/gas/ia64/opc-b.s | 837 -- gas/testsuite/gas/ia64/opc-f.d | 1572 -- gas/testsuite/gas/ia64/opc-f.pl | 174 - gas/testsuite/gas/ia64/opc-f.s | 612 - gas/testsuite/gas/ia64/opc-i.d | 312 - gas/testsuite/gas/ia64/opc-i.pl | 189 - gas/testsuite/gas/ia64/opc-i.s | 258 - gas/testsuite/gas/ia64/opc-m.d | 1359 -- gas/testsuite/gas/ia64/opc-m.pl | 218 - gas/testsuite/gas/ia64/opc-m.s | 1037 -- gas/testsuite/gas/ia64/opc-x.d | 39 - gas/testsuite/gas/ia64/opc-x.s | 19 - gas/testsuite/gas/ia64/operand-or.d | 30 - gas/testsuite/gas/ia64/operand-or.s | 11 - gas/testsuite/gas/ia64/operands.l | 5 - gas/testsuite/gas/ia64/operands.s | 6 - gas/testsuite/gas/ia64/order.d | 36 - gas/testsuite/gas/ia64/order.s | 37 - gas/testsuite/gas/ia64/pcrel.d | 63 - gas/testsuite/gas/ia64/pcrel.s | 87 - gas/testsuite/gas/ia64/pound.l | 58 - gas/testsuite/gas/ia64/pound.s | 43 - gas/testsuite/gas/ia64/pr13167.d | 43 - gas/testsuite/gas/ia64/pr13167.s | 9 - gas/testsuite/gas/ia64/pred-rel.s | 21 - gas/testsuite/gas/ia64/proc.l | 6 - gas/testsuite/gas/ia64/proc.s | 13 - gas/testsuite/gas/ia64/pseudo.d | 29 - gas/testsuite/gas/ia64/pseudo.s | 19 - gas/testsuite/gas/ia64/psn.d | 1467 -- gas/testsuite/gas/ia64/psn.s | 1018 -- gas/testsuite/gas/ia64/radix.l | 4 - gas/testsuite/gas/ia64/radix.s | 5 - gas/testsuite/gas/ia64/real.d | 10 - gas/testsuite/gas/ia64/real.s | 8 - gas/testsuite/gas/ia64/reg-err.l | 14 - gas/testsuite/gas/ia64/reg-err.s | 14 - gas/testsuite/gas/ia64/regs.d | 2349 --- gas/testsuite/gas/ia64/regs.pl | 150 - gas/testsuite/gas/ia64/regs.s | 1020 -- gas/testsuite/gas/ia64/regval.l | 17 - gas/testsuite/gas/ia64/regval.s | 48 - gas/testsuite/gas/ia64/reloc-bad.l | 43 - gas/testsuite/gas/ia64/reloc-bad.s | 62 - gas/testsuite/gas/ia64/reloc-mlx.d | 8 - gas/testsuite/gas/ia64/reloc-mlx.s | 7 - gas/testsuite/gas/ia64/reloc-uw-ilp32.d | 15 - gas/testsuite/gas/ia64/reloc-uw.d | 13 - gas/testsuite/gas/ia64/reloc-uw.s | 13 - gas/testsuite/gas/ia64/reloc.d | 64 - gas/testsuite/gas/ia64/reloc.s | 82 - gas/testsuite/gas/ia64/rotX.l | 5 - gas/testsuite/gas/ia64/rotX.s | 4 - gas/testsuite/gas/ia64/secname-ilp32.d | 19 - gas/testsuite/gas/ia64/secname.d | 26 - gas/testsuite/gas/ia64/secname.s | 2 - gas/testsuite/gas/ia64/slot2.l | 3 - gas/testsuite/gas/ia64/slot2.s | 18 - gas/testsuite/gas/ia64/slotcount.d | 10 - gas/testsuite/gas/ia64/slotcount.s | 51 - gas/testsuite/gas/ia64/strange.d | 19 - gas/testsuite/gas/ia64/strange.s | 18 - gas/testsuite/gas/ia64/tls.d | 54 - gas/testsuite/gas/ia64/tls.s | 64 - gas/testsuite/gas/ia64/unwind-bad.l | 51 - gas/testsuite/gas/ia64/unwind-bad.s | 155 - gas/testsuite/gas/ia64/unwind-err.l | 35 - gas/testsuite/gas/ia64/unwind-err.s | 67 - gas/testsuite/gas/ia64/unwind-ilp32.d | 20 - gas/testsuite/gas/ia64/unwind-ok.d | 224 - gas/testsuite/gas/ia64/unwind-ok.s | 272 - gas/testsuite/gas/ia64/unwind.d | 28 - gas/testsuite/gas/ia64/unwind.s | 4 - gas/testsuite/gas/ia64/xdata-ilp32.d | 29 - gas/testsuite/gas/ia64/xdata.d | 47 - gas/testsuite/gas/ia64/xdata.s | 45 - gas/testsuite/gas/lns/lns-common-1-ia64.s | 18 - gas/testsuite/gas/lns/lns.exp | 2 - gas/testsuite/gas/symver/symver.exp | 5 - gas/write.c | 4 +- gnulib/configure | 3 +- gnulib/import/isnan.c | 4 +- gnulib/import/m4/isnanl.m4 | 2 +- gnulib/import/m4/stdalign.m4 | 1 - gnulib/import/stdalign.in.h | 1 - gprof/configure | 100 +- gprofng/configure | 171 +- gprofng/libcollector/configure | 175 +- include/coff/ia64.h | 89 - include/elf/ia64.h | 415 - include/floatformat.h | 3 - include/longlong.h | 49 - include/opcode/ia64.h | 428 - ld/Makefile.am | 3 - ld/Makefile.in | 6 - ld/configure | 171 +- ld/configure.tgt | 21 +- ld/emulparams/elf64_aix.sh | 21 - ld/emulparams/elf64_ia64.sh | 39 - ld/emulparams/elf64_ia64_fbsd.sh | 6 - ld/emulparams/elf64_ia64_vms.sh | 6 - ld/emultempl/ia64elf.em | 63 - ld/emultempl/vms.em | 11 - ld/ldlex.h | 2 - ld/scripttempl/ia64vms.sc | 132 - ld/testsuite/ld-bootstrap/bootstrap.exp | 9 +- ld/testsuite/ld-checks/checks.exp | 4 +- ld/testsuite/ld-elf/eh-group.exp | 2 +- ld/testsuite/ld-elf/elf.exp | 1 - ld/testsuite/ld-elf/pr21884.d | 2 +- ld/testsuite/ld-elf/shared.exp | 4 +- ld/testsuite/ld-elf/stab.d | 2 +- ld/testsuite/ld-elf/tls.exp | 4 +- ld/testsuite/ld-elfvers/vers.exp | 3 - ld/testsuite/ld-elfweak/elfweak.exp | 2 - ld/testsuite/ld-ia64/error1.d | 5 - ld/testsuite/ld-ia64/error1.s | 30 - ld/testsuite/ld-ia64/error2.d | 5 - ld/testsuite/ld-ia64/error3.d | 5 - ld/testsuite/ld-ia64/ia64.exp | 65 - ld/testsuite/ld-ia64/line.exp | 57 - ld/testsuite/ld-ia64/link-order.d | 9 - ld/testsuite/ld-ia64/local1.d | 9 - ld/testsuite/ld-ia64/local1.map | 6 - ld/testsuite/ld-ia64/local1.s | 21 - ld/testsuite/ld-ia64/merge1.d | 10 - ld/testsuite/ld-ia64/merge1.s | 12 - ld/testsuite/ld-ia64/merge2.d | 10 - ld/testsuite/ld-ia64/merge2.s | 12 - ld/testsuite/ld-ia64/merge3.d | 13 - ld/testsuite/ld-ia64/merge3.s | 16 - ld/testsuite/ld-ia64/merge4.d | 13 - ld/testsuite/ld-ia64/merge4.s | 21 - ld/testsuite/ld-ia64/merge5.d | 16 - ld/testsuite/ld-ia64/merge5.s | 24 - ld/testsuite/ld-ia64/tlsbin.dd | 74 - ld/testsuite/ld-ia64/tlsbin.rd | 136 - ld/testsuite/ld-ia64/tlsbin.s | 54 - ld/testsuite/ld-ia64/tlsbin.sd | 15 - ld/testsuite/ld-ia64/tlsbin.td | 16 - ld/testsuite/ld-ia64/tlsbinpic.s | 97 - ld/testsuite/ld-ia64/tlsg.s | 14 - ld/testsuite/ld-ia64/tlsg.sd | 10 - ld/testsuite/ld-ia64/tlslib.s | 18 - ld/testsuite/ld-ia64/tlspic.dd | 64 - ld/testsuite/ld-ia64/tlspic.rd | 127 - ld/testsuite/ld-ia64/tlspic.sd | 15 - ld/testsuite/ld-ia64/tlspic.td | 16 - ld/testsuite/ld-ia64/tlspic1.s | 114 - ld/testsuite/ld-ia64/tlspic2.s | 11 - ld/testsuite/ld-ia64/undefined.s | 152 - ld/testsuite/ld-scripts/fill.d | 3 +- ld/testsuite/ld-shared/shared.exp | 5 - ld/testsuite/ld-srec/srec.exp | 4 - ld/testsuite/ld-unique/pr21529.d | 2 +- ld/testsuite/ld-vsb/vsb.exp | 4 - ld/testsuite/lib/ld-lib.exp | 1 - libbacktrace/configure | 106 +- libctf/configure | 100 +- libiberty/configure | 5 - libiberty/floatformat.c | 16 - libsframe/configure | 100 +- libtool.m4 | 150 +- opcodes/Makefile.am | 27 +- opcodes/Makefile.in | 30 +- opcodes/configure | 101 +- opcodes/configure.ac | 1 - opcodes/configure.com | 8 - opcodes/disassemble.c | 11 - opcodes/disassemble.h | 1 - opcodes/ia64-asmtab.c | 10669 -------------- opcodes/ia64-asmtab.h | 148 - opcodes/ia64-dis.c | 320 - opcodes/ia64-gen.c | 2865 ---- opcodes/ia64-ic.tbl | 258 - opcodes/ia64-opc-a.c | 418 - opcodes/ia64-opc-b.c | 511 - opcodes/ia64-opc-d.c | 34 - opcodes/ia64-opc-f.c | 656 - opcodes/ia64-opc-i.c | 340 - opcodes/ia64-opc-m.c | 2235 --- opcodes/ia64-opc-x.c | 188 - opcodes/ia64-opc.c | 735 - opcodes/ia64-opc.h | 138 - opcodes/ia64-raw.tbl | 199 - opcodes/ia64-war.tbl | 2 - opcodes/ia64-waw.tbl | 140 - readline/readline/support/config.guess | 19 - readline/readline/support/config.rpath | 25 +- readline/readline/support/config.sub | 2 +- sim/configure | 100 +- zlib/configure | 100 +- zlib/make_vms.com | 7 +- 343 files changed, 213 insertions(+), 72515 deletions(-) delete mode 100644 bfd/coff-ia64.c delete mode 100644 bfd/cpu-ia64-opc.c delete mode 100644 bfd/cpu-ia64.c delete mode 100644 bfd/elf64-ia64-vms.c delete mode 100644 bfd/elfnn-ia64.c delete mode 100644 bfd/elfxx-ia64.c delete mode 100644 bfd/elfxx-ia64.h delete mode 100644 bfd/pei-ia64.c delete mode 100644 binutils/testsuite/binutils-all/testranges-ia64.d delete mode 100644 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delete mode 100644 opcodes/ia64-gen.c delete mode 100644 opcodes/ia64-ic.tbl delete mode 100644 opcodes/ia64-opc-a.c delete mode 100644 opcodes/ia64-opc-b.c delete mode 100644 opcodes/ia64-opc-d.c delete mode 100644 opcodes/ia64-opc-f.c delete mode 100644 opcodes/ia64-opc-i.c delete mode 100644 opcodes/ia64-opc-m.c delete mode 100644 opcodes/ia64-opc-x.c delete mode 100644 opcodes/ia64-opc.c delete mode 100644 opcodes/ia64-opc.h delete mode 100644 opcodes/ia64-raw.tbl delete mode 100644 opcodes/ia64-war.tbl delete mode 100644 opcodes/ia64-waw.tbl diff --git a/bfd/.gitignore b/bfd/.gitignore index ba2aea70156..d091ef76068 100644 --- a/bfd/.gitignore +++ b/bfd/.gitignore @@ -1,9 +1,7 @@ /bfd-in3.h /bfd.h /bfdver.h -/elf32-ia64.c /elf32-target.h -/elf64-ia64.c /elf64-target.h /libtool-soversion /ofiles diff --git a/bfd/Makefile.am b/bfd/Makefile.am index 0dc733eaba9..fbde3be930a 100644 --- a/bfd/Makefile.am +++ b/bfd/Makefile.am @@ -117,7 +117,6 @@ ALL_MACHINES =3D \ cpu-h8300.lo \ cpu-hppa.lo \ cpu-i386.lo \ - cpu-ia64.lo \ cpu-iamcu.lo \ cpu-ip2k.lo \ cpu-iq2000.lo \ @@ -201,7 +200,6 @@ ALL_MACHINES_CFILES =3D \ cpu-h8300.c \ cpu-hppa.c \ cpu-i386.c \ - cpu-ia64.c \ cpu-iamcu.c \ cpu-ip2k.c \ cpu-iq2000.c \ @@ -536,8 +534,6 @@ BFD32_BACKENDS_CFILES =3D \ # The .o files needed by all of the 64 bit vectors that are configured into # target_vector in targets.c if configured with --enable-targets=3Dall # and --enable-64-bit-bfd. -# elf32-ia64.c requires a 64-bit bfd_vma, and hence can not be put in -# BFD32_BACKENDS. BFD64_BACKENDS =3D \ aix5ppc-core.lo \ aout64.lo \ @@ -545,7 +541,6 @@ BFD64_BACKENDS =3D \ coff-x86_64.lo \ coff64-rs6000.lo \ elf32-aarch64.lo \ - elf32-ia64.lo \ elf32-kvx.lo \ elf32-loongarch.lo \ elf32-mips.lo \ @@ -558,8 +553,6 @@ BFD64_BACKENDS =3D \ elf64-bpf.lo \ elf64-gen.lo \ elf64-hppa.lo \ - elf64-ia64-vms.lo \ - elf64-ia64.lo \ elf64-kvx.lo \ elf64-loongarch.lo \ elf64-mips.lo \ @@ -574,7 +567,6 @@ BFD64_BACKENDS =3D \ elf64.lo \ elfn32-mips.lo \ elfxx-aarch64.lo \ - elfxx-ia64.lo \ elfxx-kvx.lo \ elfxx-loongarch.lo \ elfxx-mips.lo \ @@ -589,7 +581,6 @@ BFD64_BACKENDS =3D \ pe-riscv64igen.lo \ pe-x86_64.lo \ pei-aarch64.lo \ - pei-ia64.lo \ pei-loongarch64.lo \ pei-riscv64.lo \ pei-x86_64.lo \ @@ -611,7 +602,6 @@ BFD64_BACKENDS_CFILES =3D \ elf64-bpf.c \ elf64-gen.c \ elf64-hppa.c \ - elf64-ia64-vms.c \ elf64-mips.c \ elf64-mmix.c \ elf64-nfp.c \ @@ -623,7 +613,6 @@ BFD64_BACKENDS_CFILES =3D \ elf64.c \ elfn32-mips.c \ elfxx-aarch64.c \ - elfxx-ia64.c \ elfxx-kvx.c \ elfxx-loongarch.c \ elfxx-mips.c \ @@ -635,7 +624,6 @@ BFD64_BACKENDS_CFILES =3D \ pe-aarch64.c \ pe-x86_64.c \ pei-aarch64.c \ - pei-ia64.c \ pei-loongarch64.c \ pei-riscv64.c \ pei-x86_64.c \ @@ -691,7 +679,6 @@ SOURCE_CFILES =3D \ BUILD_CFILES =3D \ elf32-aarch64.c elf64-aarch64.c \ elf32-kvx.c elf64-kvx.c \ - elf32-ia64.c elf64-ia64.c \ elf32-loongarch.c elf64-loongarch.c \ elf32-riscv.c elf64-riscv.c \ peigen.c pepigen.c pex64igen.c pe-aarch64igen.c pe-loongarch64igen.c \ @@ -714,7 +701,7 @@ SOURCE_HFILES =3D \ elf64-hppa.h elf64-ppc.h elf64-tilegx.h \ elf-bfd.h elfcode.h elfcore.h elf-hppa.h elf-linker-x86.h \ elf-linux-core.h elf-nacl.h elf-s390.h elf-vxworks.h \ - elfxx-aarch64.h elfxx-ia64.h elfxx-mips.h elfxx-riscv.h \ + elfxx-aarch64.h elfxx-mips.h elfxx-riscv.h \ elfxx-sparc.h elfxx-tilegx.h elfxx-x86.h elfxx-loongarch.h \ genlink.h go32stub.h \ libaout.h libbfd.h libcoff.h libecoff.h libhppa.h \ @@ -853,14 +840,6 @@ elf64-aarch64.c : elfnn-aarch64.c $(AM_V_at)echo "#line 1 \"$<\"" > $@ $(AM_V_GEN)$(SED) -e s/NN/64/g < $< >> $@ =20 -elf32-ia64.c : elfnn-ia64.c - $(AM_V_at)echo "#line 1 \"$<\"" > $@ - $(AM_V_GEN)$(SED) -e s/NN/32/g < $< >> $@ - -elf64-ia64.c : elfnn-ia64.c - $(AM_V_at)echo "#line 1 \"$<\"" > $@ - $(AM_V_GEN)$(SED) -e s/NN/64/g < $< >> $@ - elf32-kvx.c : elfnn-kvx.c $(AM_V_at)echo "#line 1 \"$<\"" > $@ $(AM_V_GEN)$(SED) -e s/NN/32/g < $< >> $@ diff --git a/bfd/Makefile.in b/bfd/Makefile.in index b3d97d478ea..543a4c567aa 100644 --- a/bfd/Makefile.in +++ b/bfd/Makefile.in @@ -583,7 +583,6 @@ ALL_MACHINES =3D \ cpu-h8300.lo \ cpu-hppa.lo \ cpu-i386.lo \ - cpu-ia64.lo \ cpu-iamcu.lo \ cpu-ip2k.lo \ cpu-iq2000.lo \ @@ -667,7 +666,6 @@ ALL_MACHINES_CFILES =3D \ cpu-h8300.c \ cpu-hppa.c \ cpu-i386.c \ - cpu-ia64.c \ cpu-iamcu.c \ cpu-ip2k.c \ cpu-iq2000.c \ @@ -1004,8 +1002,6 @@ BFD32_BACKENDS_CFILES =3D \ # The .o files needed by all of the 64 bit vectors that are configured into # target_vector in targets.c if configured with --enable-targets=3Dall # and --enable-64-bit-bfd. -# elf32-ia64.c requires a 64-bit bfd_vma, and hence can not be put in -# BFD32_BACKENDS. BFD64_BACKENDS =3D \ aix5ppc-core.lo \ aout64.lo \ @@ -1013,7 +1009,6 @@ BFD64_BACKENDS =3D \ coff-x86_64.lo \ coff64-rs6000.lo \ elf32-aarch64.lo \ - elf32-ia64.lo \ elf32-kvx.lo \ elf32-loongarch.lo \ elf32-mips.lo \ @@ -1026,8 +1021,6 @@ BFD64_BACKENDS =3D \ elf64-bpf.lo \ elf64-gen.lo \ elf64-hppa.lo \ - elf64-ia64-vms.lo \ - elf64-ia64.lo \ elf64-kvx.lo \ elf64-loongarch.lo \ elf64-mips.lo \ @@ -1042,7 +1035,6 @@ BFD64_BACKENDS =3D \ elf64.lo \ elfn32-mips.lo \ elfxx-aarch64.lo \ - elfxx-ia64.lo \ elfxx-kvx.lo \ elfxx-loongarch.lo \ elfxx-mips.lo \ @@ -1057,7 +1049,6 @@ BFD64_BACKENDS =3D \ pe-riscv64igen.lo \ pe-x86_64.lo \ pei-aarch64.lo \ - pei-ia64.lo \ pei-loongarch64.lo \ pei-riscv64.lo \ pei-x86_64.lo \ @@ -1079,7 +1070,6 @@ BFD64_BACKENDS_CFILES =3D \ elf64-bpf.c \ elf64-gen.c \ elf64-hppa.c \ - elf64-ia64-vms.c \ elf64-mips.c \ elf64-mmix.c \ elf64-nfp.c \ @@ -1091,7 +1081,6 @@ BFD64_BACKENDS_CFILES =3D \ elf64.c \ elfn32-mips.c \ elfxx-aarch64.c \ - elfxx-ia64.c \ elfxx-kvx.c \ elfxx-loongarch.c \ elfxx-mips.c \ @@ -1103,7 +1092,6 @@ BFD64_BACKENDS_CFILES =3D \ pe-aarch64.c \ pe-x86_64.c \ pei-aarch64.c \ - pei-ia64.c \ pei-loongarch64.c \ pei-riscv64.c \ pei-x86_64.c \ @@ -1158,7 +1146,6 @@ SOURCE_CFILES =3D \ BUILD_CFILES =3D \ elf32-aarch64.c elf64-aarch64.c \ elf32-kvx.c elf64-kvx.c \ - elf32-ia64.c elf64-ia64.c \ elf32-loongarch.c elf64-loongarch.c \ elf32-riscv.c elf64-riscv.c \ peigen.c pepigen.c pex64igen.c pe-aarch64igen.c pe-loongarch64igen.c \ @@ -1178,7 +1165,7 @@ SOURCE_HFILES =3D \ elf64-hppa.h elf64-ppc.h elf64-tilegx.h \ elf-bfd.h elfcode.h elfcore.h elf-hppa.h elf-linker-x86.h \ elf-linux-core.h elf-nacl.h elf-s390.h elf-vxworks.h \ - elfxx-aarch64.h elfxx-ia64.h elfxx-mips.h elfxx-riscv.h \ + elfxx-aarch64.h elfxx-mips.h elfxx-riscv.h \ elfxx-sparc.h elfxx-tilegx.h elfxx-x86.h elfxx-loongarch.h \ genlink.h go32stub.h \ libaout.h libbfd.h libcoff.h libecoff.h libhppa.h \ @@ -1497,7 +1484,6 @@ distclean-compile: @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/cpu-h8300.Plo@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/cpu-hppa.Plo@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/cpu-i386.Plo@am__quote@ -@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/cpu-ia64.Plo@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/cpu-iamcu.Plo@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/cpu-ip2k.Plo@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/cpu-iq2000.Plo@am__quote@ @@ -1593,7 +1579,6 @@ distclean-compile: @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf32-h8300.Plo@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf32-hppa.Plo@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf32-i386.Plo@am__quote@ -@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf32-ia64.Plo@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf32-ip2k.Plo@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf32-iq2000.Plo@am__quot= e@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf32-kvx.Plo@am__quote@ @@ -1647,8 +1632,6 @@ distclean-compile: @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf64-bpf.Plo@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf64-gen.Plo@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf64-hppa.Plo@am__quote@ -@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf64-ia64-vms.Plo@am__qu= ote@ -@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf64-ia64.Plo@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf64-kvx.Plo@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf64-loongarch.Plo@am__q= uote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf64-mips.Plo@am__quote@ @@ -1664,7 +1647,6 @@ distclean-compile: @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elflink.Plo@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elfn32-mips.Plo@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elfxx-aarch64.Plo@am__quo= te@ -@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elfxx-ia64.Plo@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elfxx-kvx.Plo@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elfxx-loongarch.Plo@am__q= uote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elfxx-mips.Plo@am__quote@ @@ -1713,7 +1695,6 @@ distclean-compile: @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/pei-arm-wince.Plo@am__quo= te@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/pei-arm.Plo@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/pei-i386.Plo@am__quote@ -@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/pei-ia64.Plo@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/pei-loongarch64.Plo@am__q= uote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/pei-mcore.Plo@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/pei-riscv64.Plo@am__quote@ @@ -2364,14 +2345,6 @@ elf64-aarch64.c : elfnn-aarch64.c $(AM_V_at)echo "#line 1 \"$<\"" > $@ $(AM_V_GEN)$(SED) -e s/NN/64/g < $< >> $@ =20 -elf32-ia64.c : elfnn-ia64.c - $(AM_V_at)echo "#line 1 \"$<\"" > $@ - $(AM_V_GEN)$(SED) -e s/NN/32/g < $< >> $@ - -elf64-ia64.c : elfnn-ia64.c - $(AM_V_at)echo "#line 1 \"$<\"" > $@ - $(AM_V_GEN)$(SED) -e s/NN/64/g < $< >> $@ - elf32-kvx.c : elfnn-kvx.c $(AM_V_at)echo "#line 1 \"$<\"" > $@ $(AM_V_GEN)$(SED) -e s/NN/32/g < $< >> $@ diff --git a/bfd/archures.c b/bfd/archures.c index 94118b8d2cf..f7e5e6d6867 100644 --- a/bfd/archures.c +++ b/bfd/archures.c @@ -396,9 +396,6 @@ DESCRIPTION .#define bfd_mach_mep_c5 0x6335 . bfd_arch_metag, .#define bfd_mach_metag 1 -. bfd_arch_ia64, {* HP/Intel ia64. *} -.#define bfd_mach_ia64_elf64 64 -.#define bfd_mach_ia64_elf32 32 . bfd_arch_ip2k, {* Ubicom IP2K microcontrollers. *} .#define bfd_mach_ip2022 1 .#define bfd_mach_ip2022ext 2 @@ -653,7 +650,6 @@ extern const bfd_arch_info_type bfd_h8300_arch; extern const bfd_arch_info_type bfd_hppa_arch; extern const bfd_arch_info_type bfd_i386_arch; extern const bfd_arch_info_type bfd_iamcu_arch; -extern const bfd_arch_info_type bfd_ia64_arch; extern const bfd_arch_info_type bfd_ip2k_arch; extern const bfd_arch_info_type bfd_iq2000_arch; extern const bfd_arch_info_type bfd_kvx_arch; @@ -742,7 +738,6 @@ static const bfd_arch_info_type * const bfd_archures_li= st[] =3D &bfd_hppa_arch, &bfd_i386_arch, &bfd_iamcu_arch, - &bfd_ia64_arch, &bfd_ip2k_arch, &bfd_iq2000_arch, &bfd_kvx_arch, diff --git a/bfd/bfd-in2.h b/bfd/bfd-in2.h index e3b5a8b8522..1a997a043df 100644 --- a/bfd/bfd-in2.h +++ b/bfd/bfd-in2.h @@ -1657,9 +1657,6 @@ enum bfd_architecture #define bfd_mach_mep_c5 0x6335 bfd_arch_metag, #define bfd_mach_metag 1 - bfd_arch_ia64, /* HP/Intel ia64. */ -#define bfd_mach_ia64_elf64 64 -#define bfd_mach_ia64_elf32 32 bfd_arch_ip2k, /* Ubicom IP2K microcontrollers. */ #define bfd_mach_ip2022 1 #define bfd_mach_ip2022ext 2 diff --git a/bfd/coff-ia64.c b/bfd/coff-ia64.c deleted file mode 100644 index c579bfdfe16..00000000000 --- a/bfd/coff-ia64.c +++ /dev/null @@ -1,214 +0,0 @@ -/* BFD back-end for HP/Intel IA-64 COFF files. - Copyright (C) 1999-2024 Free Software Foundation, Inc. - Contributed by David Mosberger - - This file is part of BFD, the Binary File Descriptor library. - - This program is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - This program is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program; if not, write to the Free Software - Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, - MA 02110-1301, USA. */ - -#include "sysdep.h" -#include "bfd.h" -#include "libbfd.h" -#include "coff/ia64.h" -#include "coff/internal.h" -#include "coff/pe.h" -#include "libcoff.h" - -#define COFF_DEFAULT_SECTION_ALIGNMENT_POWER (2) - -/* Windows ia64 uses 8K page size. */ -#define COFF_PAGE_SIZE 0x2000 - -static reloc_howto_type howto_table[] =3D -{ - EMPTY_HOWTO (0), -}; - -#define BADMAG(x) IA64BADMAG(x) -#define IA64 1 /* Customize coffcode.h */ - -#ifdef COFF_WITH_pep -# undef AOUTSZ -# define AOUTSZ PEPAOUTSZ -# define PEAOUTHDR PEPAOUTHDR -#endif - -#define RTYPE2HOWTO(cache_ptr, dst) \ - (cache_ptr)->howto =3D howto_table; - -#ifdef COFF_WITH_PE -/* Return TRUE if this relocation should - appear in the output .reloc section. */ - -static bool -in_reloc_p (bfd * abfd ATTRIBUTE_UNUSED, - reloc_howto_type *howto ATTRIBUTE_UNUSED) -{ - return false; /* We don't do relocs for now... */ -} -#endif - -#ifndef bfd_pe_print_pdata -#define bfd_pe_print_pdata NULL -#endif - -#include "coffcode.h" - -static bfd_cleanup -ia64coff_object_p (bfd *abfd) -{ -#ifdef COFF_IMAGE_WITH_PE - { - struct external_DOS_hdr dos_hdr; - struct external_PEI_IMAGE_hdr image_hdr; - file_ptr offset; - - if (bfd_seek (abfd, 0, SEEK_SET) !=3D 0 - || (bfd_read (&dos_hdr, sizeof (dos_hdr), abfd) !=3D sizeof (dos_hdr))) - { - if (bfd_get_error () !=3D bfd_error_system_call) - bfd_set_error (bfd_error_wrong_format); - return NULL; - } - - /* There are really two magic numbers involved; the magic number - that says this is a NT executable (PEI) and the magic number - that determines the architecture. The former is IMAGE_DOS_SIGNATUR= E, - stored in the e_magic field. The latter is stored in the - f_magic field. If the NT magic number isn't valid, the - architecture magic number could be mimicked by some other - field (specifically, the number of relocs in section 3). Since - this routine can only be called correctly for a PEI file, check - the e_magic number here, and, if it doesn't match, clobber the - f_magic number so that we don't get a false match. */ - if (H_GET_16 (abfd, dos_hdr.e_magic) !=3D IMAGE_DOS_SIGNATURE) - { - bfd_set_error (bfd_error_wrong_format); - return NULL; - } - - offset =3D H_GET_32 (abfd, dos_hdr.e_lfanew); - if (bfd_seek (abfd, offset, SEEK_SET) !=3D 0 - || (bfd_read (&image_hdr, sizeof (image_hdr), abfd) - !=3D sizeof (image_hdr))) - { - if (bfd_get_error () !=3D bfd_error_system_call) - bfd_set_error (bfd_error_wrong_format); - return NULL; - } - - if (H_GET_32 (abfd, image_hdr.nt_signature) - !=3D 0x4550) - { - bfd_set_error (bfd_error_wrong_format); - return NULL; - } - - /* Here is the hack. coff_object_p wants to read filhsz bytes to - pick up the COFF header for PE, see "struct external_PEI_filehdr" - in include/coff/pe.h. We adjust so that that will work. */ - if (bfd_seek (abfd, offset - sizeof (dos_hdr), SEEK_SET) !=3D 0) - { - if (bfd_get_error () !=3D bfd_error_system_call) - bfd_set_error (bfd_error_wrong_format); - return NULL; - } - } -#endif - - return coff_object_p (abfd); -} - -const bfd_target -#ifdef TARGET_SYM - TARGET_SYM =3D -#else - ia64coff_vec =3D -#endif -{ -#ifdef TARGET_NAME - TARGET_NAME, -#else - "coff-ia64", /* name */ -#endif - bfd_target_coff_flavour, - BFD_ENDIAN_LITTLE, /* data byte order is little */ - BFD_ENDIAN_LITTLE, /* header byte order is little */ - - (HAS_RELOC | EXEC_P /* object flags */ - | HAS_LINENO | HAS_DEBUG - | HAS_SYMS | HAS_LOCALS | WP_TEXT | D_PAGED), - -#ifndef COFF_WITH_PE - (SEC_HAS_CONTENTS | SEC_ALLOC | SEC_LOAD | SEC_RELOC /* section flags */ - | SEC_CODE | SEC_DATA), -#else - (SEC_HAS_CONTENTS | SEC_ALLOC | SEC_LOAD | SEC_RELOC /* section flags */ - | SEC_CODE | SEC_DATA - | SEC_LINK_ONCE | SEC_LINK_DUPLICATES), -#endif - -#ifdef TARGET_UNDERSCORE - TARGET_UNDERSCORE, /* leading underscore */ -#else - 0, /* leading underscore */ -#endif - '/', /* ar_pad_char */ - 15, /* ar_max_namelen */ - 0, /* match priority. */ - TARGET_KEEP_UNUSED_SECTION_SYMBOLS, /* keep unused section symbols. */ - - bfd_getl64, bfd_getl_signed_64, bfd_putl64, - bfd_getl32, bfd_getl_signed_32, bfd_putl32, - bfd_getl16, bfd_getl_signed_16, bfd_putl16, /* data */ - bfd_getl64, bfd_getl_signed_64, bfd_putl64, - bfd_getl32, bfd_getl_signed_32, bfd_putl32, - bfd_getl16, bfd_getl_signed_16, bfd_putl16, /* hdrs */ - -/* Note that we allow an object file to be treated as a core file as well.= */ - { /* bfd_check_format */ - _bfd_dummy_target, - ia64coff_object_p, - bfd_generic_archive_p, - ia64coff_object_p - }, - { /* bfd_set_format */ - _bfd_bool_bfd_false_error, - coff_mkobject, - _bfd_generic_mkarchive, - _bfd_bool_bfd_false_error - }, - { /* bfd_write_contents */ - _bfd_bool_bfd_false_error, - coff_write_object_contents, - _bfd_write_archive_contents, - _bfd_bool_bfd_false_error - }, - - BFD_JUMP_TABLE_GENERIC (coff), - BFD_JUMP_TABLE_COPY (coff), - BFD_JUMP_TABLE_CORE (_bfd_nocore), - BFD_JUMP_TABLE_ARCHIVE (_bfd_archive_coff), - BFD_JUMP_TABLE_SYMBOLS (coff), - BFD_JUMP_TABLE_RELOCS (coff), - BFD_JUMP_TABLE_WRITE (coff), - BFD_JUMP_TABLE_LINK (coff), - BFD_JUMP_TABLE_DYNAMIC (_bfd_nodynamic), - - NULL, - - COFF_SWAP_TABLE -}; diff --git a/bfd/coffcode.h b/bfd/coffcode.h index ebf4f513fde..3cce4950c9e 100644 --- a/bfd/coffcode.h +++ b/bfd/coffcode.h @@ -2191,11 +2191,6 @@ coff_set_arch_mach_hook (bfd *abfd, void * filehdr) machine =3D bfd_mach_x86_64; break; #endif -#ifdef IA64MAGIC - case IA64MAGIC: - arch =3D bfd_arch_ia64; - break; -#endif #ifdef ARMMAGIC case ARMMAGIC: case ARMPEMAGIC: @@ -2872,12 +2867,6 @@ coff_set_flags (bfd * abfd, return true; #endif =20 -#ifdef IA64MAGIC - case bfd_arch_ia64: - *magicp =3D IA64MAGIC; - return true; -#endif - #ifdef SH_ARCH_MAGIC_BIG case bfd_arch_sh: #ifdef COFF_IMAGE_WITH_PE diff --git a/bfd/config.bfd b/bfd/config.bfd index 6553aac1e99..ba3777a58ee 100644 --- a/bfd/config.bfd +++ b/bfd/config.bfd @@ -332,21 +332,6 @@ case "${targ}" in targ_defvec=3Damdgcn_elf64_le_vec want64=3Dtrue ;; - ia64*-*-freebsd* | ia64*-*-netbsd* | ia64*-*-linux-* | ia64*-*-elf* | ia= 64*-*-kfreebsd*-gnu) - targ_defvec=3Dia64_elf64_le_vec - targ_selvecs=3D"ia64_elf64_be_vec ia64_pei_vec" - want64=3Dtrue - ;; - ia64*-*-hpux*) - targ_defvec=3Dia64_elf32_hpux_be_vec - targ_selvecs=3D"ia64_elf64_hpux_be_vec" - want64=3Dtrue - ;; - ia64*-*-*vms*) - targ_defvec=3Dia64_elf64_vms_vec - targ_selvecs=3Dalpha_vms_lib_txt_vec - want64=3Dtrue - ;; #endif /* BFD64 */ =20 am33_2.0-*-linux*) diff --git a/bfd/configure b/bfd/configure index 89fe4388171..13f374bd88a 100755 --- a/bfd/configure +++ b/bfd/configure @@ -6073,10 +6073,6 @@ haiku*) hpux10.20* | hpux11*) lt_cv_file_magic_cmd=3D/usr/bin/file case $host_cpu in - ia64*) - lt_cv_deplibs_check_method=3D'file_magic (s[0-9][0-9][0-9]|ELF-[0-9][0= -9]) shared object file - IA64' - lt_cv_file_magic_test_file=3D/usr/lib/hpux32/libc.so - ;; hppa*64*) lt_cv_deplibs_check_method=3D'file_magic (s[0-9][0-9][0-9]|ELF[ -][0-9= ][0-9])(-bit)?( [LM]SB)? shared object( file)?[, -]* PA-RISC [0-9]\.[0-9]' lt_cv_file_magic_test_file=3D/usr/lib/pa20_64/libc.sl @@ -6635,11 +6631,6 @@ aix*) cygwin* | mingw* | pw32* | cegcc*) symcode=3D'[ABCDGISTW]' ;; -hpux*) - if test "$host_cpu" =3D ia64; then - symcode=3D'[ABCDEGRST]' - fi - ;; irix* | nonstopux*) symcode=3D'[BCDEGRST]' ;; @@ -6670,7 +6661,7 @@ case `$NM -V 2>&1` in esac =20 # Transform an extracted symbol line into a proper C declaration. -# Some systems (esp. on ia64) link data and code symbols differently, +# Some systems link data and code symbols differently, # so use this general approach. lt_cv_sys_global_symbol_to_cdecl=3D"sed -n -e 's/^T .* \(.*\)$/extern int = \1();/p' -e 's/^$symcode* .* \(.*\)$/extern char \1;/p'" =20 @@ -6870,25 +6861,6 @@ test "x$enable_libtool_lock" !=3D xno && enable_libt= ool_lock=3Dyes # Some flags need to be propagated to the compiler or linker for good # libtool support. case $host in -ia64-*-hpux*) - # Find out which ABI we are using. - echo 'int i;' > conftest.$ac_ext - if { { eval echo "\"\$as_me\":${as_lineno-$LINENO}: \"$ac_compile\""; } = >&5 - (eval $ac_compile) 2>&5 - ac_status=3D$? - $as_echo "$as_me:${as_lineno-$LINENO}: \$? =3D $ac_status" >&5 - test $ac_status =3D 0; }; then - case `/usr/bin/file conftest.$ac_objext` in - *ELF-32*) - HPUX_IA64_MODE=3D"32" - ;; - *ELF-64*) - HPUX_IA64_MODE=3D"64" - ;; - esac - fi - rm -rf conftest* - ;; *-*-irix6*) # Find out which ABI we are using. echo '#line '$LINENO' "configure"' > conftest.$ac_ext @@ -8192,10 +8164,6 @@ $as_echo_n "checking for $compiler option to produce= PIC... " >&6; } case $host_os in aix*) # All AIX code is PIC. - if test "$host_cpu" =3D ia64; then - # AIX 5 now supports IA64 processor - lt_prog_compiler_static=3D'-Bstatic' - fi lt_prog_compiler_pic=3D'-fPIC' ;; =20 @@ -8292,12 +8260,7 @@ $as_echo_n "checking for $compiler option to produce= PIC... " >&6; } case $host_os in aix*) lt_prog_compiler_wl=3D'-Wl,' - if test "$host_cpu" =3D ia64; then - # AIX 5 now supports IA64 processor - lt_prog_compiler_static=3D'-Bstatic' - else - lt_prog_compiler_static=3D'-bnso -bI:/lib/syscalls.exp' - fi + lt_prog_compiler_static=3D'-bnso -bI:/lib/syscalls.exp' ;; =20 mingw* | cygwin* | pw32* | os2* | cegcc*) @@ -8311,7 +8274,7 @@ $as_echo_n "checking for $compiler option to produce = PIC... " >&6; } # PIC is the default for IA64 HP-UX and 64-bit HP-UX, but # not for PA HP-UX. case $host_cpu in - hppa*64*|ia64*) + hppa*64*) # +Z the default ;; *) @@ -8836,7 +8799,6 @@ $as_echo_n "checking whether the $compiler linker ($L= D) supports shared librarie case $host_os in aix[3-9]*) # On AIX/PPC, the GNU linker is very broken - if test "$host_cpu" !=3D ia64; then ld_shlibs=3Dno cat <<_LT_EOF 1>&2 =20 @@ -8848,7 +8810,6 @@ $as_echo_n "checking whether the $compiler linker ($L= D) supports shared librarie *** You will then need to restart the configuration process. =20 _LT_EOF - fi ;; =20 amigaos*) @@ -8944,10 +8905,6 @@ _LT_EOF # Portland Group f77 and f90 compilers whole_archive_flag_spec=3D'${wl}--whole-archive`for conv in $convenienc= e\"\"; do test -n \"$conv\" && new_convenience=3D\"$new_convenience,$conv\= "; done; func_echo_all \"$new_convenience\"` ${wl}--no-whole-archive' tmp_addflag=3D' $pic_flag -Mnomain' ;; - ecc*,ia64* | icc*,ia64*) # Intel C compiler on ia64 - tmp_addflag=3D' -i_dynamic' ;; - efc*,ia64* | ifort*,ia64*) # Intel Fortran compiler on ia64 - tmp_addflag=3D' -i_dynamic -nofor_main' ;; ifc* | ifort*) # Intel Fortran compiler tmp_addflag=3D' -nofor_main' ;; lf95*) # Lahey Fortran 8.1 @@ -9101,13 +9058,6 @@ _LT_EOF ;; =20 aix[4-9]*) - if test "$host_cpu" =3D ia64; then - # On IA64, the linker does run time linking by default, so we don't - # have to do anything special. - aix_use_runtimelinking=3Dno - exp_sym_flag=3D'-Bexport' - no_entry_flag=3D"" - else # If we're using GNU nm, then we don't want the "-C" option. # -C means demangle to AIX nm, but means don't demangle with GNU nm # Also, AIX nm treats weak defined symbols like other global @@ -9134,7 +9084,6 @@ _LT_EOF =20 exp_sym_flag=3D'-bexport' no_entry_flag=3D'-bnoentry' - fi =20 # When large executables or shared objects are built, AIX ld can # have problems creating the table of contents. If linking a library @@ -9177,17 +9126,11 @@ _LT_EOF fi else # not using gcc - if test "$host_cpu" =3D ia64; then - # VisualAge C++, Version 5.5 for AIX 5L for IA-64, Beta 3 Release - # chokes on -Wl,-G. The following line is correct: - shared_flag=3D'-G' - else if test "$aix_use_runtimelinking" =3D yes; then shared_flag=3D'${wl}-G' else shared_flag=3D'${wl}-bM:SRE' fi - fi fi =20 export_dynamic_flag_spec=3D'${wl}-bexpall' @@ -9233,11 +9176,6 @@ if test -z "$aix_libpath"; then aix_libpath=3D"/usr/= lib:/lib"; fi hardcode_libdir_flag_spec=3D'${wl}-blibpath:$libdir:'"$aix_libpath" archive_expsym_cmds=3D'$CC -o $output_objdir/$soname $libobjs $dep= libs '"\${wl}$no_entry_flag"' $compiler_flags `if test "x${allow_undefined_= flag}" !=3D "x"; then func_echo_all "${wl}${allow_undefined_flag}"; else :;= fi` '"\${wl}$exp_sym_flag:\$export_symbols $shared_flag" else - if test "$host_cpu" =3D ia64; then - hardcode_libdir_flag_spec=3D'${wl}-R $libdir:/usr/lib:/lib' - allow_undefined_flag=3D"-z nodefs" - archive_expsym_cmds=3D"\$CC $shared_flag"' -o $output_objdir/$soname $l= ibobjs $deplibs '"\${wl}$no_entry_flag"' $compiler_flags ${wl}${allow_undef= ined_flag} '"\${wl}$exp_sym_flag:\$export_symbols" - else # Determine the default libpath from the value encoded in an # empty executable. cat confdefs.h - <<_ACEOF >conftest.$ac_ext @@ -9285,7 +9223,6 @@ if test -z "$aix_libpath"; then aix_libpath=3D"/usr/l= ib:/lib"; fi archive_cmds_need_lc=3Dyes # This is similar to how AIX traditionally builds its shared libraries. archive_expsym_cmds=3D"\$CC $shared_flag"' -o $output_objdir/$soname $l= ibobjs $deplibs ${wl}-bnoentry $compiler_flags ${wl}-bE:$export_symbols${al= low_undefined_flag}~$AR $AR_FLAGS $output_objdir/$libname$release.a $output= _objdir/$soname' - fi fi ;; =20 @@ -9434,9 +9371,6 @@ if test -z "$aix_libpath"; then aix_libpath=3D"/usr/l= ib:/lib"; fi hppa*64*) archive_cmds=3D'$CC -shared ${wl}+h ${wl}$soname ${wl}+nodefaultrpath -= o $lib $libobjs $deplibs $compiler_flags' ;; - ia64*) - archive_cmds=3D'$CC -shared -fPIC ${wl}+h ${wl}$soname ${wl}+nodefaultr= path -o $lib $libobjs $deplibs $compiler_flags' - ;; *) archive_cmds=3D'$CC -shared -fPIC ${wl}+h ${wl}$soname ${wl}+b ${wl}$in= stall_libdir -o $lib $libobjs $deplibs $compiler_flags' ;; @@ -9446,9 +9380,6 @@ if test -z "$aix_libpath"; then aix_libpath=3D"/usr/l= ib:/lib"; fi hppa*64*) archive_cmds=3D'$CC -b ${wl}+h ${wl}$soname ${wl}+nodefaultrpath -o $li= b $libobjs $deplibs $compiler_flags' ;; - ia64*) - archive_cmds=3D'$CC -b ${wl}+h ${wl}$soname ${wl}+nodefaultrpath -o $li= b $libobjs $deplibs $compiler_flags' - ;; *) =20 # Older versions of the 11.00 compiler do not understand -b yet @@ -9498,7 +9429,7 @@ fi hardcode_libdir_separator=3D: =20 case $host_cpu in - hppa*64*|ia64*) + hppa*64*) hardcode_direct=3Dno hardcode_shlibpath_var=3Dno ;; @@ -10135,11 +10066,6 @@ aix[4-9]*) need_lib_prefix=3Dno need_version=3Dno hardcode_into_libs=3Dyes - if test "$host_cpu" =3D ia64; then - # AIX 5 supports IA64 - library_names_spec=3D'${libname}${release}${shared_ext}$major ${libnam= e}${release}${shared_ext}$versuffix $libname${shared_ext}' - shlibpath_var=3DLD_LIBRARY_PATH - else # With GCC up to 2.95.x, collect2 would create an import file # for dependence libraries. The import file would start with # the line `#! .'. This would cause the generated library to @@ -10171,7 +10097,6 @@ aix[4-9]*) soname_spec=3D'${libname}${release}${shared_ext}$major' fi shlibpath_var=3DLIBPATH - fi ;; =20 amigaos*) @@ -10348,21 +10273,6 @@ hpux9* | hpux10* | hpux11*) need_lib_prefix=3Dno need_version=3Dno case $host_cpu in - ia64*) - shrext_cmds=3D'.so' - hardcode_into_libs=3Dyes - dynamic_linker=3D"$host_os dld.so" - shlibpath_var=3DLD_LIBRARY_PATH - shlibpath_overrides_runpath=3Dyes # Unless +noenvvar is specified. - library_names_spec=3D'${libname}${release}${shared_ext}$versuffix ${li= bname}${release}${shared_ext}$major $libname${shared_ext}' - soname_spec=3D'${libname}${release}${shared_ext}$major' - if test "X$HPUX_IA64_MODE" =3D X32; then - sys_lib_search_path_spec=3D"/usr/lib/hpux32 /usr/local/lib/hpux32 /u= sr/local/lib" - else - sys_lib_search_path_spec=3D"/usr/lib/hpux64 /usr/local/lib/hpux64" - fi - sys_lib_dlsearch_path_spec=3D$sys_lib_search_path_spec - ;; hppa*64*) shrext_cmds=3D'.sl' hardcode_into_libs=3Dyes @@ -11453,7 +11363,7 @@ $as_echo_n "checking whether to build shared librar= ies... " >&6; } ;; =20 aix[4-9]*) - if test "$host_cpu" !=3D ia64 && test "$aix_use_runtimelinking" =3D no= ; then + if test "$aix_use_runtimelinking" =3D no ; then test "$enable_shared" =3D yes && enable_static=3Dno fi ;; @@ -15903,13 +15813,6 @@ do i386_pe_big_vec) tb=3D"$tb pe-i386.lo peigen.lo $coff" ;; i386_pei_vec) tb=3D"$tb pei-i386.lo peigen.lo $coff" ;; iamcu_elf32_vec) tb=3D"$tb elf32-i386.lo $elfxx_x86 elf32.lo $elf" ;; - ia64_elf32_be_vec) tb=3D"$tb elf32-ia64.lo elfxx-ia64.lo elf32.lo $e= lf" ;; - ia64_elf32_hpux_be_vec) tb=3D"$tb elf32-ia64.lo elfxx-ia64.lo elf32.l= o $elf" ;; - ia64_elf64_be_vec) tb=3D"$tb elf64-ia64.lo elfxx-ia64.lo elf64.lo $e= lf"; target_size=3D64 ;; - ia64_elf64_le_vec) tb=3D"$tb elf64-ia64.lo elfxx-ia64.lo elf64.lo $e= lf"; target_size=3D64 ;; - ia64_elf64_hpux_be_vec) tb=3D"$tb elf64-ia64.lo elfxx-ia64.lo elf64.l= o $elf"; target_size=3D64 ;; - ia64_elf64_vms_vec) tb=3D"$tb elf64-ia64-vms.lo elf64-ia64.lo elfxx-= ia64.lo elf64.lo vms-lib.lo vms-misc.lo $elf"; target_size=3D64 ;; - ia64_pei_vec) tb=3D"$tb pei-ia64.lo pepigen.lo $coff"; target_size= =3D64 ;; ip2k_elf32_vec) tb=3D"$tb elf32-ip2k.lo elf32.lo $elf" ;; iq2000_elf32_vec) tb=3D"$tb elf32-iq2000.lo elf32.lo $elf" ;; kvx_elf32_vec) tb=3D"$tb elf32-kvx.lo elfxx-kvx.lo elf32.lo $elf $ip= a" ;; diff --git a/bfd/configure.ac b/bfd/configure.ac index 29ede92b993..cf771a8a6d6 100644 --- a/bfd/configure.ac +++ b/bfd/configure.ac @@ -488,13 +488,6 @@ do i386_pe_big_vec) tb=3D"$tb pe-i386.lo peigen.lo $coff" ;; i386_pei_vec) tb=3D"$tb pei-i386.lo peigen.lo $coff" ;; iamcu_elf32_vec) tb=3D"$tb elf32-i386.lo $elfxx_x86 elf32.lo $elf" ;; - ia64_elf32_be_vec) tb=3D"$tb elf32-ia64.lo elfxx-ia64.lo elf32.lo $e= lf" ;; - ia64_elf32_hpux_be_vec) tb=3D"$tb elf32-ia64.lo elfxx-ia64.lo elf32.l= o $elf" ;; - ia64_elf64_be_vec) tb=3D"$tb elf64-ia64.lo elfxx-ia64.lo elf64.lo $e= lf"; target_size=3D64 ;; - ia64_elf64_le_vec) tb=3D"$tb elf64-ia64.lo elfxx-ia64.lo elf64.lo $e= lf"; target_size=3D64 ;; - ia64_elf64_hpux_be_vec) tb=3D"$tb elf64-ia64.lo elfxx-ia64.lo elf64.l= o $elf"; target_size=3D64 ;; - ia64_elf64_vms_vec) tb=3D"$tb elf64-ia64-vms.lo elf64-ia64.lo elfxx-= ia64.lo elf64.lo vms-lib.lo vms-misc.lo $elf"; target_size=3D64 ;; - ia64_pei_vec) tb=3D"$tb pei-ia64.lo pepigen.lo $coff"; target_size= =3D64 ;; ip2k_elf32_vec) tb=3D"$tb elf32-ip2k.lo elf32.lo $elf" ;; iq2000_elf32_vec) tb=3D"$tb elf32-iq2000.lo elf32.lo $elf" ;; kvx_elf32_vec) tb=3D"$tb elf32-kvx.lo elfxx-kvx.lo elf32.lo $elf $ip= a" ;; diff --git a/bfd/configure.com b/bfd/configure.com index 6022b305f0d..32ce83430e6 100644 --- a/bfd/configure.com +++ b/bfd/configure.com @@ -284,15 +284,6 @@ $ DEFS=3D"""SELECT_VECS=3D&alpha_vms_vec"","+- $ FILES=3D"cpu-alpha,vms,vms-hdr,vms-gsd,vms-tir,vms-misc," $EOD $ endif -$ if ARCH.eqs."ia64" -$ then -$ create build.com -$DECK -$ DEFS=3D"""SELECT_VECS=3D&ia64_elf64_vms_vec"","+- - """SELECT_ARCHITECTURES=3D&bfd_ia64_arch""" -$ FILES=3D"cpu-ia64,elf64-ia64,elf-strtab,corefile,stabs,merge,elf-eh-fram= e,"+- - "elflink,elf-attrs,dwarf1,elf64," -$EOD $ create substxx.tpu $DECK set (success,off); diff --git a/bfd/configure.host b/bfd/configure.host index 74342f7cc89..7f19e06586c 100644 --- a/bfd/configure.host +++ b/bfd/configure.host @@ -48,10 +48,6 @@ hppa*-*-mpeix*) HDEFINES=3D-DHOST_HPPAMPEIX ;; hppa*-*-bsd*) HDEFINES=3D-DHOST_HPPABSD ;; hppa*-*-osf*) HDEFINES=3D-DHOST_HPPAOSF ;; =20 -ia64-*-hpux*) HDEFINES=3D-D_LARGEFILE64_SOURCE - host64=3Dtrue;; -ia64-*-*) host64=3Dtrue;; - # Workaround for limitations on win9x where file contents are # not zero'd out if you seek past the end and then write. i[3-7]86-*-mingw32*) HDEFINES=3D-D__USE_MINGW_FSEEK;; diff --git a/bfd/cpu-ia64-opc.c b/bfd/cpu-ia64-opc.c deleted file mode 100644 index b8884ca4c50..00000000000 --- a/bfd/cpu-ia64-opc.c +++ /dev/null @@ -1,669 +0,0 @@ -/* Copyright (C) 1998-2024 Free Software Foundation, Inc. - Contributed by David Mosberger-Tang - - This file is part of BFD, the Binary File Descriptor library. - - This program is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - This program is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program; if not, write to the Free Software - Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, - MA 02110-1301, USA. */ - -/* Logically, this code should be part of libopcode but since some of - the operand insertion/extraction functions help bfd to implement - relocations, this code is included as part of cpu-ia64.c. This - avoids circular dependencies between libopcode and libbfd and also - obviates the need for applications to link in libopcode when all - they really want is libbfd. - - --davidm Mon Apr 13 22:14:02 1998 */ - -#include "../opcodes/ia64-opc.h" - -#define NELEMS(a) ((int) (sizeof (a) / sizeof ((a)[0]))) - -static const char* -ins_rsvd (const struct ia64_operand *self ATTRIBUTE_UNUSED, - ia64_insn value ATTRIBUTE_UNUSED, ia64_insn *code ATTRIBUTE_UNUSED) -{ - return "internal error---this shouldn't happen"; -} - -static const char* -ext_rsvd (const struct ia64_operand *self ATTRIBUTE_UNUSED, - ia64_insn code ATTRIBUTE_UNUSED, ia64_insn *valuep ATTRIBUTE_UNUSED) -{ - return "internal error---this shouldn't happen"; -} - -static const char* -ins_const (const struct ia64_operand *self ATTRIBUTE_UNUSED, - ia64_insn value ATTRIBUTE_UNUSED, ia64_insn *code ATTRIBUTE_UNUSED) -{ - return 0; -} - -static const char* -ext_const (const struct ia64_operand *self ATTRIBUTE_UNUSED, - ia64_insn code ATTRIBUTE_UNUSED, ia64_insn *valuep ATTRIBUTE_UNUSED) -{ - return 0; -} - -static const char* -ins_reg (const struct ia64_operand *self, ia64_insn value, ia64_insn *code) -{ - if (value >=3D 1u << self->field[0].bits) - return "register number out of range"; - - *code |=3D value << self->field[0].shift; - return 0; -} - -static const char* -ext_reg (const struct ia64_operand *self, ia64_insn code, ia64_insn *value= p) -{ - *valuep =3D ((code >> self->field[0].shift) - & ((1u << self->field[0].bits) - 1)); - return 0; -} - -static const char* -ins_immu (const struct ia64_operand *self, ia64_insn value, ia64_insn *cod= e) -{ - ia64_insn new_insn =3D 0; - int i; - - for (i =3D 0; i < NELEMS (self->field) && self->field[i].bits; ++i) - { - new_insn |=3D ((value & ((((ia64_insn) 1) << self->field[i].bits) - = 1)) - << self->field[i].shift); - value >>=3D self->field[i].bits; - } - if (value) - return "integer operand out of range"; - - *code |=3D new_insn; - return 0; -} - -static const char* -ext_immu (const struct ia64_operand *self, ia64_insn code, ia64_insn *valu= ep) -{ - uint64_t value =3D 0; - int i, bits =3D 0, total =3D 0; - - for (i =3D 0; i < NELEMS (self->field) && self->field[i].bits; ++i) - { - bits =3D self->field[i].bits; - value |=3D ((code >> self->field[i].shift) - & (((uint64_t) 1 << bits) - 1)) << total; - total +=3D bits; - } - *valuep =3D value; - return 0; -} - -static const char* -ins_immu5b (const struct ia64_operand *self, ia64_insn value, - ia64_insn *code) -{ - if (value < 32 || value > 63) - return "value must be between 32 and 63"; - return ins_immu (self, value - 32, code); -} - -static const char* -ext_immu5b (const struct ia64_operand *self, ia64_insn code, - ia64_insn *valuep) -{ - const char *result; - - result =3D ext_immu (self, code, valuep); - if (result) - return result; - - *valuep =3D *valuep + 32; - return 0; -} - -static const char* -ins_immus8 (const struct ia64_operand *self, ia64_insn value, ia64_insn *c= ode) -{ - if (value & 0x7) - return "value not an integer multiple of 8"; - return ins_immu (self, value >> 3, code); -} - -static const char* -ext_immus8 (const struct ia64_operand *self, ia64_insn code, ia64_insn *va= luep) -{ - const char *result; - - result =3D ext_immu (self, code, valuep); - if (result) - return result; - - *valuep =3D *valuep << 3; - return 0; -} - -static const char* -ins_imms_scaled (const struct ia64_operand *self, ia64_insn value, - ia64_insn *code, int scale) -{ - int64_t svalue =3D value, sign_bit =3D 0; - ia64_insn new_insn =3D 0; - int i; - - svalue >>=3D scale; - - for (i =3D 0; i < NELEMS (self->field) && self->field[i].bits; ++i) - { - new_insn |=3D ((svalue & ((((ia64_insn) 1) << self->field[i].bits) -= 1)) - << self->field[i].shift); - sign_bit =3D (svalue >> (self->field[i].bits - 1)) & 1; - svalue >>=3D self->field[i].bits; - } - if ((!sign_bit && svalue !=3D 0) || (sign_bit && svalue !=3D -1)) - return "integer operand out of range"; - - *code |=3D new_insn; - return 0; -} - -static const char* -ext_imms_scaled (const struct ia64_operand *self, ia64_insn code, - ia64_insn *valuep, int scale) -{ - int i, bits =3D 0, total =3D 0; - uint64_t val =3D 0, sign; - - for (i =3D 0; i < NELEMS (self->field) && self->field[i].bits; ++i) - { - bits =3D self->field[i].bits; - val |=3D ((code >> self->field[i].shift) - & (((uint64_t) 1 << bits) - 1)) << total; - total +=3D bits; - } - /* sign extend: */ - sign =3D (uint64_t) 1 << (total - 1); - val =3D (val ^ sign) - sign; - - *valuep =3D val << scale; - return 0; -} - -static const char* -ins_imms (const struct ia64_operand *self, ia64_insn value, ia64_insn *cod= e) -{ - return ins_imms_scaled (self, value, code, 0); -} - -static const char* -ins_immsu4 (const struct ia64_operand *self, ia64_insn value, ia64_insn *c= ode) -{ - value =3D ((value & 0xffffffff) ^ 0x80000000) - 0x80000000; - - return ins_imms_scaled (self, value, code, 0); -} - -static const char* -ext_imms (const struct ia64_operand *self, ia64_insn code, ia64_insn *valu= ep) -{ - return ext_imms_scaled (self, code, valuep, 0); -} - -static const char* -ins_immsm1 (const struct ia64_operand *self, ia64_insn value, ia64_insn *c= ode) -{ - --value; - return ins_imms_scaled (self, value, code, 0); -} - -static const char* -ins_immsm1u4 (const struct ia64_operand *self, ia64_insn value, - ia64_insn *code) -{ - value =3D ((value & 0xffffffff) ^ 0x80000000) - 0x80000000; - - --value; - return ins_imms_scaled (self, value, code, 0); -} - -static const char* -ext_immsm1 (const struct ia64_operand *self, ia64_insn code, ia64_insn *va= luep) -{ - const char *res =3D ext_imms_scaled (self, code, valuep, 0); - - ++*valuep; - return res; -} - -static const char* -ins_imms1 (const struct ia64_operand *self, ia64_insn value, ia64_insn *co= de) -{ - return ins_imms_scaled (self, value, code, 1); -} - -static const char* -ext_imms1 (const struct ia64_operand *self, ia64_insn code, ia64_insn *val= uep) -{ - return ext_imms_scaled (self, code, valuep, 1); -} - -static const char* -ins_imms4 (const struct ia64_operand *self, ia64_insn value, ia64_insn *co= de) -{ - return ins_imms_scaled (self, value, code, 4); -} - -static const char* -ext_imms4 (const struct ia64_operand *self, ia64_insn code, ia64_insn *val= uep) -{ - return ext_imms_scaled (self, code, valuep, 4); -} - -static const char* -ins_imms16 (const struct ia64_operand *self, ia64_insn value, ia64_insn *c= ode) -{ - return ins_imms_scaled (self, value, code, 16); -} - -static const char* -ext_imms16 (const struct ia64_operand *self, ia64_insn code, ia64_insn *va= luep) -{ - return ext_imms_scaled (self, code, valuep, 16); -} - -static const char* -ins_cimmu (const struct ia64_operand *self, ia64_insn value, ia64_insn *co= de) -{ - ia64_insn mask =3D (((ia64_insn) 1) << self->field[0].bits) - 1; - return ins_immu (self, value ^ mask, code); -} - -static const char* -ext_cimmu (const struct ia64_operand *self, ia64_insn code, ia64_insn *val= uep) -{ - const char *result; - ia64_insn mask; - - mask =3D (((ia64_insn) 1) << self->field[0].bits) - 1; - result =3D ext_immu (self, code, valuep); - if (!result) - { - mask =3D (((ia64_insn) 1) << self->field[0].bits) - 1; - *valuep ^=3D mask; - } - return result; -} - -static const char* -ins_cnt (const struct ia64_operand *self, ia64_insn value, ia64_insn *code) -{ - --value; - if (value >=3D (uint64_t) 1 << self->field[0].bits) - return "count out of range"; - - *code |=3D value << self->field[0].shift; - return 0; -} - -static const char* -ext_cnt (const struct ia64_operand *self, ia64_insn code, ia64_insn *value= p) -{ - *valuep =3D ((code >> self->field[0].shift) - & (((uint64_t) 1 << self->field[0].bits) - 1)) + 1; - return 0; -} - -static const char* -ins_cnt2b (const struct ia64_operand *self, ia64_insn value, ia64_insn *co= de) -{ - --value; - - if (value > 2) - return "count must be in range 1..3"; - - *code |=3D value << self->field[0].shift; - return 0; -} - -static const char* -ext_cnt2b (const struct ia64_operand *self, ia64_insn code, ia64_insn *val= uep) -{ - *valuep =3D ((code >> self->field[0].shift) & 0x3) + 1; - return 0; -} - -static const char* -ins_cnt2c (const struct ia64_operand *self, ia64_insn value, ia64_insn *co= de) -{ - switch (value) - { - case 0: value =3D 0; break; - case 7: value =3D 1; break; - case 15: value =3D 2; break; - case 16: value =3D 3; break; - default: return "count must be 0, 7, 15, or 16"; - } - *code |=3D value << self->field[0].shift; - return 0; -} - -static const char* -ext_cnt2c (const struct ia64_operand *self, ia64_insn code, ia64_insn *val= uep) -{ - ia64_insn value; - - value =3D (code >> self->field[0].shift) & 0x3; - switch (value) - { - case 0: value =3D 0; break; - case 1: value =3D 7; break; - case 2: value =3D 15; break; - case 3: value =3D 16; break; - } - *valuep =3D value; - return 0; -} - -static const char* -ins_cnt6a (const struct ia64_operand *self, ia64_insn value, - ia64_insn *code) -{ - if (value < 1 || value > 64) - return "value must be between 1 and 64"; - return ins_immu (self, value - 1, code); -} - -static const char* -ext_cnt6a (const struct ia64_operand *self, ia64_insn code, - ia64_insn *valuep) -{ - const char *result; - - result =3D ext_immu (self, code, valuep); - if (result) - return result; - - *valuep =3D *valuep + 1; - return 0; -} - -static const char* -ins_strd5b (const struct ia64_operand *self, ia64_insn value, - ia64_insn *code) -{ - if ( value & 0x3f ) - return "value must be a multiple of 64"; - return ins_imms_scaled (self, value, code, 6); -} - -static const char* -ext_strd5b (const struct ia64_operand *self, ia64_insn code, - ia64_insn *valuep) -{ - return ext_imms_scaled (self, code, valuep, 6); -} - - -static const char* -ins_inc3 (const struct ia64_operand *self, ia64_insn value, ia64_insn *cod= e) -{ - int64_t val =3D value; - uint64_t sign =3D 0; - - if (val < 0) - { - sign =3D 0x4; - value =3D -value; - } - switch (value) - { - case 1: value =3D 3; break; - case 4: value =3D 2; break; - case 8: value =3D 1; break; - case 16: value =3D 0; break; - default: return "count must be +/- 1, 4, 8, or 16"; - } - *code |=3D (sign | value) << self->field[0].shift; - return 0; -} - -static const char* -ext_inc3 (const struct ia64_operand *self, ia64_insn code, ia64_insn *valu= ep) -{ - int64_t val; - int negate; - - val =3D (code >> self->field[0].shift) & 0x7; - negate =3D val & 0x4; - switch (val & 0x3) - { - case 0: val =3D 16; break; - case 1: val =3D 8; break; - case 2: val =3D 4; break; - case 3: val =3D 1; break; - } - if (negate) - val =3D -val; - - *valuep =3D val; - return 0; -} - -#define CST IA64_OPND_CLASS_CST -#define REG IA64_OPND_CLASS_REG -#define IND IA64_OPND_CLASS_IND -#define ABS IA64_OPND_CLASS_ABS -#define REL IA64_OPND_CLASS_REL - -#define SDEC IA64_OPND_FLAG_DECIMAL_SIGNED -#define UDEC IA64_OPND_FLAG_DECIMAL_UNSIGNED - -const struct ia64_operand elf64_ia64_operands[IA64_OPND_COUNT] =3D - { - /* constants: */ - { CST, ins_const, ext_const, "NIL", {{ 0, 0}}, 0, "" }, - { CST, ins_const, ext_const, "ar.csd", {{ 0, 0}}, 0, "ar.csd" }, - { CST, ins_const, ext_const, "ar.ccv", {{ 0, 0}}, 0, "ar.ccv" }, - { CST, ins_const, ext_const, "ar.pfs", {{ 0, 0}}, 0, "ar.pfs" }, - { CST, ins_const, ext_const, "1", {{ 0, 0}}, 0, "1" }, - { CST, ins_const, ext_const, "8", {{ 0, 0}}, 0, "8" }, - { CST, ins_const, ext_const, "16", {{ 0, 0}}, 0, "16" }, - { CST, ins_const, ext_const, "r0", {{ 0, 0}}, 0, "r0" }, - { CST, ins_const, ext_const, "ip", {{ 0, 0}}, 0, "ip" }, - { CST, ins_const, ext_const, "pr", {{ 0, 0}}, 0, "pr" }, - { CST, ins_const, ext_const, "pr.rot", {{ 0, 0}}, 0, "pr.rot" }, - { CST, ins_const, ext_const, "psr", {{ 0, 0}}, 0, "psr" }, - { CST, ins_const, ext_const, "psr.l", {{ 0, 0}}, 0, "psr.l" }, - { CST, ins_const, ext_const, "psr.um", {{ 0, 0}}, 0, "psr.um" }, - - /* register operands: */ - { REG, ins_reg, ext_reg, "ar", {{ 7, 20}}, 0, /* AR3 */ - "an application register" }, - { REG, ins_reg, ext_reg, "b", {{ 3, 6}}, 0, /* B1 */ - "a branch register" }, - { REG, ins_reg, ext_reg, "b", {{ 3, 13}}, 0, /* B2 */ - "a branch register"}, - { REG, ins_reg, ext_reg, "cr", {{ 7, 20}}, 0, /* CR */ - "a control register"}, - { REG, ins_reg, ext_reg, "f", {{ 7, 6}}, 0, /* F1 */ - "a floating-point register" }, - { REG, ins_reg, ext_reg, "f", {{ 7, 13}}, 0, /* F2 */ - "a floating-point register" }, - { REG, ins_reg, ext_reg, "f", {{ 7, 20}}, 0, /* F3 */ - "a floating-point register" }, - { REG, ins_reg, ext_reg, "f", {{ 7, 27}}, 0, /* F4 */ - "a floating-point register" }, - { REG, ins_reg, ext_reg, "p", {{ 6, 6}}, 0, /* P1 */ - "a predicate register" }, - { REG, ins_reg, ext_reg, "p", {{ 6, 27}}, 0, /* P2 */ - "a predicate register" }, - { REG, ins_reg, ext_reg, "r", {{ 7, 6}}, 0, /* R1 */ - "a general register" }, - { REG, ins_reg, ext_reg, "r", {{ 7, 13}}, 0, /* R2 */ - "a general register" }, - { REG, ins_reg, ext_reg, "r", {{ 7, 20}}, 0, /* R3 */ - "a general register" }, - { REG, ins_reg, ext_reg, "r", {{ 2, 20}}, 0, /* R3_2 */ - "a general register r0-r3" }, - { REG, ins_reg, ext_reg, "dahr", {{ 3, 23}}, 0, /* DAHR */ - "a dahr register dahr0-7" }, - - /* memory operands: */ - { IND, ins_reg, ext_reg, "", {{7, 20}}, 0, /* MR3 */ - "a memory address" }, - - /* indirect operands: */ - { IND, ins_reg, ext_reg, "cpuid", {{7, 20}}, 0, /* CPUID_R3 */ - "a cpuid register" }, - { IND, ins_reg, ext_reg, "dbr", {{7, 20}}, 0, /* DBR_R3 */ - "a dbr register" }, - { IND, ins_reg, ext_reg, "dtr", {{7, 20}}, 0, /* DTR_R3 */ - "a dtr register" }, - { IND, ins_reg, ext_reg, "itr", {{7, 20}}, 0, /* ITR_R3 */ - "an itr register" }, - { IND, ins_reg, ext_reg, "ibr", {{7, 20}}, 0, /* IBR_R3 */ - "an ibr register" }, - { IND, ins_reg, ext_reg, "msr", {{7, 20}}, 0, /* MSR_R3 */ - "an msr register" }, - { IND, ins_reg, ext_reg, "pkr", {{7, 20}}, 0, /* PKR_R3 */ - "a pkr register" }, - { IND, ins_reg, ext_reg, "pmc", {{7, 20}}, 0, /* PMC_R3 */ - "a pmc register" }, - { IND, ins_reg, ext_reg, "pmd", {{7, 20}}, 0, /* PMD_R3 */ - "a pmd register" }, - { IND, ins_reg, ext_reg, "dahr", {{7, 20}}, 0, /* DAHR_R3 */ - "a dahr register" }, - { IND, ins_reg, ext_reg, "rr", {{7, 20}}, 0, /* RR_R3 */ - "an rr register" }, - - /* immediate operands: */ - { ABS, ins_cimmu, ext_cimmu, 0, {{ 5, 20 }}, UDEC, /* CCNT5 */ - "a 5-bit count (0-31)" }, - { ABS, ins_cnt, ext_cnt, 0, {{ 2, 27 }}, UDEC, /* CNT2a */ - "a 2-bit count (1-4)" }, - { ABS, ins_cnt2b, ext_cnt2b, 0, {{ 2, 27 }}, UDEC, /* CNT2b */ - "a 2-bit count (1-3)" }, - { ABS, ins_cnt2c, ext_cnt2c, 0, {{ 2, 30 }}, UDEC, /* CNT2c */ - "a count (0, 7, 15, or 16)" }, - { ABS, ins_immu, ext_immu, 0, {{ 5, 14}}, UDEC, /* CNT5 */ - "a 5-bit count (0-31)" }, - { ABS, ins_immu, ext_immu, 0, {{ 6, 27}}, UDEC, /* CNT6 */ - "a 6-bit count (0-63)" }, - { ABS, ins_cimmu, ext_cimmu, 0, {{ 6, 20}}, UDEC, /* CPOS6a */ - "a 6-bit bit pos (0-63)" }, - { ABS, ins_cimmu, ext_cimmu, 0, {{ 6, 14}}, UDEC, /* CPOS6b */ - "a 6-bit bit pos (0-63)" }, - { ABS, ins_cimmu, ext_cimmu, 0, {{ 6, 31}}, UDEC, /* CPOS6c */ - "a 6-bit bit pos (0-63)" }, - { ABS, ins_imms, ext_imms, 0, {{ 1, 36}}, SDEC, /* IMM1 */ - "a 1-bit integer (-1, 0)" }, - { ABS, ins_immu, ext_immu, 0, {{ 2, 13}}, UDEC, /* IMMU2 */ - "a 2-bit unsigned (0-3)" }, - { ABS, ins_immu5b, ext_immu5b, 0, {{ 5, 14}}, UDEC, /* IMMU5b */ - "a 5-bit unsigned (32 + (0-31))" }, - { ABS, ins_immu, ext_immu, 0, {{ 7, 13}}, 0, /* IMMU7a */ - "a 7-bit unsigned (0-127)" }, - { ABS, ins_immu, ext_immu, 0, {{ 7, 20}}, 0, /* IMMU7b */ - "a 7-bit unsigned (0-127)" }, - { ABS, ins_immu, ext_immu, 0, {{ 7, 13}}, UDEC, /* SOF */ - "a frame size (register count)" }, - { ABS, ins_immu, ext_immu, 0, {{ 7, 20}}, UDEC, /* SOL */ - "a local register count" }, - { ABS, ins_immus8,ext_immus8,0, {{ 4, 27}}, UDEC, /* SOR */ - "a rotating register count (integer multiple of 8)" }, - { ABS, ins_imms, ext_imms, 0, /* IMM8 */ - {{ 7, 13}, { 1, 36}}, SDEC, - "an 8-bit integer (-128-127)" }, - { ABS, ins_immsu4, ext_imms, 0, /* IMM8U4 */ - {{ 7, 13}, { 1, 36}}, SDEC, - "an 8-bit signed integer for 32-bit unsigned compare (-128-127)" }, - { ABS, ins_immsm1, ext_immsm1, 0, /* IMM8M1 */ - {{ 7, 13}, { 1, 36}}, SDEC, - "an 8-bit integer (-127-128)" }, - { ABS, ins_immsm1u4, ext_immsm1, 0, /* IMM8M1U4 */ - {{ 7, 13}, { 1, 36}}, SDEC, - "an 8-bit integer for 32-bit unsigned compare (-127-(-1),1-128,0x100= 000000)" }, - { ABS, ins_immsm1, ext_immsm1, 0, /* IMM8M1U8 */ - {{ 7, 13}, { 1, 36}}, SDEC, - "an 8-bit integer for 64-bit unsigned compare (-127-(-1),1-128,0x100= 00000000000000)" }, - { ABS, ins_immu, ext_immu, 0, {{ 2, 33}, { 7, 20}}, 0, /* IMMU9 */ - "a 9-bit unsigned (0-511)" }, - { ABS, ins_imms, ext_imms, 0, /* IMM9a */ - {{ 7, 6}, { 1, 27}, { 1, 36}}, SDEC, - "a 9-bit integer (-256-255)" }, - { ABS, ins_imms, ext_imms, 0, /* IMM9b */ - {{ 7, 13}, { 1, 27}, { 1, 36}}, SDEC, - "a 9-bit integer (-256-255)" }, - { ABS, ins_imms, ext_imms, 0, /* IMM14 */ - {{ 7, 13}, { 6, 27}, { 1, 36}}, SDEC, - "a 14-bit integer (-8192-8191)" }, - { ABS, ins_immu, ext_immu, 0, /* IMMU16 */ - {{4, 6}, {11, 12}, { 1, 36}}, UDEC, - "a 16-bit unsigned" }, - { ABS, ins_imms1, ext_imms1, 0, /* IMM17 */ - {{ 7, 6}, { 8, 24}, { 1, 36}}, 0, - "a 17-bit integer (-65536-65535)" }, - { ABS, ins_immu, ext_immu, 0, /* IMMU19 */ - {{4, 6}, {14, 12}, { 1, 36}}, UDEC, - "a 19-bit unsigned" }, - { ABS, ins_immu, ext_immu, 0, {{20, 6}, { 1, 36}}, 0, /* IMMU21 */ - "a 21-bit unsigned" }, - { ABS, ins_imms, ext_imms, 0, /* IMM22 */ - {{ 7, 13}, { 9, 27}, { 5, 22}, { 1, 36}}, SDEC, - "a 22-bit signed integer" }, - { ABS, ins_immu, ext_immu, 0, /* IMMU24 */ - {{21, 6}, { 2, 31}, { 1, 36}}, 0, - "a 24-bit unsigned" }, - { ABS, ins_imms16,ext_imms16,0, {{27, 6}, { 1, 36}}, 0, /* IMM44 */ - "a 44-bit unsigned (least 16 bits ignored/zeroes)" }, - { ABS, ins_rsvd, ext_rsvd, 0, {{0, 0}}, 0, /* IMMU62 */ - "a 62-bit unsigned" }, - { ABS, ins_rsvd, ext_rsvd, 0, {{0, 0}}, 0, /* IMMU64 */ - "a 64-bit unsigned" }, - { ABS, ins_inc3, ext_inc3, 0, {{ 3, 13}}, SDEC, /* INC3 */ - "an increment (+/- 1, 4, 8, or 16)" }, - { ABS, ins_cnt, ext_cnt, 0, {{ 4, 27}}, UDEC, /* LEN4 */ - "a 4-bit length (1-16)" }, - { ABS, ins_cnt, ext_cnt, 0, {{ 6, 27}}, UDEC, /* LEN6 */ - "a 6-bit length (1-64)" }, - { ABS, ins_immu, ext_immu, 0, {{ 4, 20}}, 0, /* MBTYPE4 */ - "a mix type (@rev, @mix, @shuf, @alt, or @brcst)" }, - { ABS, ins_immu, ext_immu, 0, {{ 8, 20}}, 0, /* MBTYPE8 */ - "an 8-bit mix type" }, - { ABS, ins_immu, ext_immu, 0, {{ 6, 14}}, UDEC, /* POS6 */ - "a 6-bit bit pos (0-63)" }, - { REL, ins_imms4, ext_imms4, 0, {{ 7, 6}, { 2, 33}}, 0, /* TAG13 */ - "a branch tag" }, - { REL, ins_imms4, ext_imms4, 0, {{ 9, 24}}, 0, /* TAG13b */ - "a branch tag" }, - { REL, ins_imms4, ext_imms4, 0, {{20, 6}, { 1, 36}}, 0, /* TGT25 */ - "a branch target" }, - { REL, ins_imms4, ext_imms4, 0, /* TGT25b */ - {{ 7, 6}, {13, 20}, { 1, 36}}, 0, - "a branch target" }, - { REL, ins_imms4, ext_imms4, 0, {{20, 13}, { 1, 36}}, 0, /* TGT25c */ - "a branch target" }, - { REL, ins_rsvd, ext_rsvd, 0, {{0, 0}}, 0, /* TGT64 */ - "a branch target" }, - - { ABS, ins_const, ext_const, 0, {{0, 0}}, 0, /* LDXMOV */ - "ldxmov target" }, - { ABS, ins_cnt6a, ext_cnt6a, 0, {{6, 6}}, UDEC, /* CNT6a */ - "lfetch count" }, - { ABS, ins_strd5b, ext_strd5b, 0, {{5, 13}}, SDEC, /* STRD5b*/ - "lfetch stride" }, - }; diff --git a/bfd/cpu-ia64.c b/bfd/cpu-ia64.c deleted file mode 100644 index 7d35def44b2..00000000000 --- a/bfd/cpu-ia64.c +++ /dev/null @@ -1,50 +0,0 @@ -/* BFD support for the ia64 architecture. - Copyright (C) 1998-2024 Free Software Foundation, Inc. - Contributed by David Mosberger-Tang - - This file is part of BFD, the Binary File Descriptor library. - - This program is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - This program is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program; if not, write to the Free Software - Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, - MA 02110-1301, USA. */ - -#include "sysdep.h" -#include "bfd.h" -#include "libbfd.h" - -#define N(BITS_ADDR, NUMBER, PRINT, DEFAULT, NEXT) \ - { \ - 64, /* Bits in a word. */ \ - BITS_ADDR, /* Bits in an address. */ \ - 8, /* Bits in a byte. */ \ - bfd_arch_ia64, \ - NUMBER, \ - "ia64", \ - PRINT, \ - 3, /* Section alignment power. */ \ - DEFAULT, \ - bfd_default_compatible, \ - bfd_default_scan, \ - bfd_arch_default_fill, \ - NEXT, \ - 0 /* Maximum offset of a reloc from the start of an insn. */ \ - } - -const bfd_arch_info_type bfd_ia64_elf32_arch =3D - N (32, bfd_mach_ia64_elf32, "ia64-elf32", false, NULL); - -const bfd_arch_info_type bfd_ia64_arch =3D - N (64, bfd_mach_ia64_elf64, "ia64-elf64", true, &bfd_ia64_elf32_arch); - -#include "cpu-ia64-opc.c" diff --git a/bfd/elf-eh-frame.c b/bfd/elf-eh-frame.c index 902d7c16334..441f9454c9f 100644 --- a/bfd/elf-eh-frame.c +++ b/bfd/elf-eh-frame.c @@ -2134,10 +2134,6 @@ _bfd_elf_write_section_eh_frame (bfd *abfd, { switch (abfd->arch_info->arch) { - case bfd_arch_ia64: - BFD_ASSERT (elf_gp (abfd) !=3D 0); - address +=3D elf_gp (abfd); - break; default: _bfd_error_handler (_("DW_EH_PE_datarel unspecified" diff --git a/bfd/elf64-ia64-vms.c b/bfd/elf64-ia64-vms.c deleted file mode 100644 index 54133c94c91..00000000000 --- a/bfd/elf64-ia64-vms.c +++ /dev/null @@ -1,5630 +0,0 @@ -/* IA-64 support for OpenVMS - Copyright (C) 1998-2024 Free Software Foundation, Inc. - - This file is part of BFD, the Binary File Descriptor library. - - This program is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - This program is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program; if not, write to the Free Software - Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, - MA 02110-1301, USA. */ - -#include "sysdep.h" -#include "bfd.h" -#include "libbfd.h" -#include "elf-bfd.h" -#include "opcode/ia64.h" -#include "elf/ia64.h" -#include "objalloc.h" -#include "hashtab.h" -#include "elfxx-ia64.h" -#include "vms.h" -#include "bfdver.h" - -/* THE RULES for all the stuff the linker creates -- - - GOT Entries created in response to LTOFF or LTOFF_FPTR - relocations. Dynamic relocs created for dynamic - symbols in an application; REL relocs for locals - in a shared library. - - FPTR The canonical function descriptor. Created for local - symbols in applications. Descriptors for dynamic symbols - and local symbols in shared libraries are created by - ld.so. Thus there are no dynamic relocs against these - objects. The FPTR relocs for such _are_ passed through - to the dynamic relocation tables. - - FULL_PLT Created for a PCREL21B relocation against a dynamic symbol. - Requires the creation of a PLTOFF entry. This does not - require any dynamic relocations. - - PLTOFF Created by PLTOFF relocations. For local symbols, this - is an alternate function descriptor, and in shared libraries - requires two REL relocations. Note that this cannot be - transformed into an FPTR relocation, since it must be in - range of the GP. For dynamic symbols, this is a function - descriptor. */ - -typedef struct bfd_hash_entry *(*new_hash_entry_func) - (struct bfd_hash_entry *, struct bfd_hash_table *, const char *); - -/* In dynamically (linker-) created sections, we generally need to keep tr= ack - of the place a symbol or expression got allocated to. This is done via = hash - tables that store entries of the following type. */ - -struct elf64_ia64_dyn_sym_info -{ - /* The addend for which this entry is relevant. */ - bfd_vma addend; - - bfd_vma got_offset; - bfd_vma fptr_offset; - bfd_vma pltoff_offset; - bfd_vma plt_offset; - bfd_vma plt2_offset; - - /* The symbol table entry, if any, that this was derived from. */ - struct elf_link_hash_entry *h; - - /* Used to count non-got, non-plt relocations for delayed sizing - of relocation sections. */ - struct elf64_ia64_dyn_reloc_entry - { - struct elf64_ia64_dyn_reloc_entry *next; - asection *srel; - int type; - int count; - } *reloc_entries; - - /* TRUE when the section contents have been updated. */ - unsigned got_done : 1; - unsigned fptr_done : 1; - unsigned pltoff_done : 1; - - /* TRUE for the different kinds of linker data we want created. */ - unsigned want_got : 1; - unsigned want_gotx : 1; - unsigned want_fptr : 1; - unsigned want_ltoff_fptr : 1; - unsigned want_plt : 1; /* A MIN_PLT entry. */ - unsigned want_plt2 : 1; /* A FULL_PLT. */ - unsigned want_pltoff : 1; -}; - -struct elf64_ia64_local_hash_entry -{ - int id; - unsigned int r_sym; - /* The number of elements in elf64_ia64_dyn_sym_info array. */ - unsigned int count; - /* The number of sorted elements in elf64_ia64_dyn_sym_info array. */ - unsigned int sorted_count; - /* The size of elf64_ia64_dyn_sym_info array. */ - unsigned int size; - /* The array of elf64_ia64_dyn_sym_info. */ - struct elf64_ia64_dyn_sym_info *info; - - /* TRUE if this hash entry's addends was translated for - SHF_MERGE optimization. */ - unsigned sec_merge_done : 1; -}; - -struct elf64_ia64_link_hash_entry -{ - struct elf_link_hash_entry root; - - /* Set if this symbol is defined in a shared library. - We can't use root.u.def.section->owner as the symbol is an absolute - symbol. */ - bfd *shl; - - /* The number of elements in elf64_ia64_dyn_sym_info array. */ - unsigned int count; - /* The number of sorted elements in elf64_ia64_dyn_sym_info array. */ - unsigned int sorted_count; - /* The size of elf64_ia64_dyn_sym_info array. */ - unsigned int size; - /* The array of elf64_ia64_dyn_sym_info. */ - struct elf64_ia64_dyn_sym_info *info; -}; - -struct elf64_ia64_link_hash_table -{ - /* The main hash table. */ - struct elf_link_hash_table root; - - asection *fptr_sec; /* Function descriptor table (or NULL). */ - asection *rel_fptr_sec; /* Dynamic relocation section for same. */ - asection *pltoff_sec; /* Private descriptors for plt (or NULL). */ - asection *fixups_sec; /* Fixups section. */ - asection *transfer_sec; /* Transfer vector section. */ - asection *note_sec; /* .note section. */ - - /* There are maybe R_IA64_GPREL22 relocations, including those - optimized from R_IA64_LTOFF22X, against non-SHF_IA_64_SHORT - sections. We need to record those sections so that we can choose - a proper GP to cover all R_IA64_GPREL22 relocations. */ - asection *max_short_sec; /* Maximum short output section. */ - bfd_vma max_short_offset; /* Maximum short offset. */ - asection *min_short_sec; /* Minimum short output section. */ - bfd_vma min_short_offset; /* Minimum short offset. */ - - htab_t loc_hash_table; - void *loc_hash_memory; -}; - -struct elf64_ia64_allocate_data -{ - struct bfd_link_info *info; - bfd_size_type ofs; -}; - -#define elf64_ia64_hash_table(p) \ - ((is_elf_hash_table ((p)->hash) \ - && elf_hash_table_id (elf_hash_table (p)) =3D=3D IA64_ELF_DATA) \ - ? (struct elf64_ia64_link_hash_table *) (p)->hash : NULL) - -struct elf64_ia64_vms_obj_tdata -{ - struct elf_obj_tdata root; - - /* Ident for shared library. */ - uint64_t ident; - - /* Used only during link: offset in the .fixups section for this bfd. */ - bfd_vma fixups_off; - - /* Max number of shared libraries. */ - unsigned int needed_count; -}; - -#define elf_ia64_vms_tdata(abfd) \ - ((struct elf64_ia64_vms_obj_tdata *)((abfd)->tdata.any)) -#define elf_ia64_vms_ident(abfd) (elf_ia64_vms_tdata(abfd)->ident) - -struct elf64_vms_transfer -{ - unsigned char size[4]; - unsigned char spare[4]; - unsigned char tfradr1[8]; - unsigned char tfradr2[8]; - unsigned char tfradr3[8]; - unsigned char tfradr4[8]; - unsigned char tfradr5[8]; - - /* Local function descriptor for tfr3. */ - unsigned char tfr3_func[8]; - unsigned char tfr3_gp[8]; -}; - -typedef struct -{ - Elf64_External_Ehdr ehdr; - unsigned char vms_needed_count[8]; -} Elf64_External_VMS_Ehdr; - -static struct elf64_ia64_dyn_sym_info * get_dyn_sym_info - (struct elf64_ia64_link_hash_table *, - struct elf_link_hash_entry *, - bfd *, const Elf_Internal_Rela *, bool); -static bool elf64_ia64_dynamic_symbol_p - (struct elf_link_hash_entry *); -static bool elf64_ia64_choose_gp - (bfd *, struct bfd_link_info *, bool); -static void elf64_ia64_dyn_sym_traverse - (struct elf64_ia64_link_hash_table *, - bool (*) (struct elf64_ia64_dyn_sym_info *, void *), - void *); -static bool allocate_global_data_got - (struct elf64_ia64_dyn_sym_info *, void *); -static bool allocate_global_fptr_got - (struct elf64_ia64_dyn_sym_info *, void *); -static bool allocate_local_got - (struct elf64_ia64_dyn_sym_info *, void *); -static bool allocate_dynrel_entries - (struct elf64_ia64_dyn_sym_info *, void *); -static asection *get_pltoff - (bfd *, struct elf64_ia64_link_hash_table *); -static asection *get_got - (bfd *, struct elf64_ia64_link_hash_table *); - - -/* Given a ELF reloc, return the matching HOWTO structure. */ - -static bool -elf64_ia64_info_to_howto (bfd *abfd ATTRIBUTE_UNUSED, - arelent *bfd_reloc, - Elf_Internal_Rela *elf_reloc) -{ - unsigned int r_type =3D ELF32_R_TYPE (elf_reloc->r_info); - - bfd_reloc->howto =3D ia64_elf_lookup_howto (r_type); - if (bfd_reloc->howto =3D=3D NULL) - { - /* xgettext:c-format */ - _bfd_error_handler (_("%pB: unsupported relocation type %#x"), - abfd, r_type); - bfd_set_error (bfd_error_bad_value); - return false; - } - - return true; -} - - -#define PLT_FULL_ENTRY_SIZE (2 * 16) - -static const bfd_byte plt_full_entry[PLT_FULL_ENTRY_SIZE] =3D -{ - 0x0b, 0x78, 0x00, 0x02, 0x00, 0x24, /* [MMI] addl r15=3D0,r1;; */ - 0x00, 0x41, 0x3c, 0x70, 0x29, 0xc0, /* ld8.acq r16=3D[r15],8*/ - 0x01, 0x08, 0x00, 0x84, /* mov r14=3Dr1;; */ - 0x11, 0x08, 0x00, 0x1e, 0x18, 0x10, /* [MIB] ld8 r1=3D[r15] */ - 0x60, 0x80, 0x04, 0x80, 0x03, 0x00, /* mov b6=3Dr16 */ - 0x60, 0x00, 0x80, 0x00 /* br.few b6;; */ -}; - -static const bfd_byte oor_brl[16] =3D -{ - 0x05, 0x00, 0x00, 0x00, 0x01, 0x00, /* [MLX] nop.m 0 */ - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* brl.sptk.few tgt;;*/ - 0x00, 0x00, 0x00, 0xc0 -}; - - -/* These functions do relaxation for IA-64 ELF. */ - -/* Rename some of the generic section flags to better document how they - are used here. */ -#define skip_relax_pass_0 sec_flg0 -#define skip_relax_pass_1 sec_flg1 - -static void -elf64_ia64_update_short_info (asection *sec, bfd_vma offset, - struct elf64_ia64_link_hash_table *ia64_info) -{ - /* Skip ABS and SHF_IA_64_SHORT sections. */ - if (sec =3D=3D bfd_abs_section_ptr - || (sec->flags & SEC_SMALL_DATA) !=3D 0) - return; - - if (!ia64_info->min_short_sec) - { - ia64_info->max_short_sec =3D sec; - ia64_info->max_short_offset =3D offset; - ia64_info->min_short_sec =3D sec; - ia64_info->min_short_offset =3D offset; - } - else if (sec =3D=3D ia64_info->max_short_sec - && offset > ia64_info->max_short_offset) - ia64_info->max_short_offset =3D offset; - else if (sec =3D=3D ia64_info->min_short_sec - && offset < ia64_info->min_short_offset) - ia64_info->min_short_offset =3D offset; - else if (sec->output_section->vma - > ia64_info->max_short_sec->vma) - { - ia64_info->max_short_sec =3D sec; - ia64_info->max_short_offset =3D offset; - } - else if (sec->output_section->vma - < ia64_info->min_short_sec->vma) - { - ia64_info->min_short_sec =3D sec; - ia64_info->min_short_offset =3D offset; - } -} - -/* Use a two passes algorithm. In the first pass, branches are relaxed - (which may increase the size of the section). In the second pass, - the other relaxations are done. -*/ - -static bool -elf64_ia64_relax_section (bfd *abfd, asection *sec, - struct bfd_link_info *link_info, - bool *again) -{ - struct one_fixup - { - struct one_fixup *next; - asection *tsec; - bfd_vma toff; - bfd_vma trampoff; - }; - - Elf_Internal_Shdr *symtab_hdr; - Elf_Internal_Rela *internal_relocs; - Elf_Internal_Rela *irel, *irelend; - bfd_byte *contents; - Elf_Internal_Sym *isymbuf =3D NULL; - struct elf64_ia64_link_hash_table *ia64_info; - struct one_fixup *fixups =3D NULL; - bool changed_contents =3D false; - bool changed_relocs =3D false; - bool skip_relax_pass_0 =3D true; - bool skip_relax_pass_1 =3D true; - bfd_vma gp =3D 0; - - /* Assume we're not going to change any sizes, and we'll only need - one pass. */ - *again =3D false; - - if (bfd_link_relocatable (link_info)) - (*link_info->callbacks->einfo) - (_("%P%F: --relax and -r may not be used together\n")); - - /* Don't even try to relax for non-ELF outputs. */ - if (!is_elf_hash_table (link_info->hash)) - return false; - - /* Nothing to do if there are no relocations or there is no need for - the current pass. */ - if (sec->reloc_count =3D=3D 0 - || (sec->flags & SEC_RELOC) =3D=3D 0 - || (sec->flags & SEC_HAS_CONTENTS) =3D=3D 0 - || (link_info->relax_pass =3D=3D 0 && sec->skip_relax_pass_0) - || (link_info->relax_pass =3D=3D 1 && sec->skip_relax_pass_1)) - return true; - - ia64_info =3D elf64_ia64_hash_table (link_info); - if (ia64_info =3D=3D NULL) - return false; - - symtab_hdr =3D &elf_tdata (abfd)->symtab_hdr; - - /* Load the relocations for this section. */ - internal_relocs =3D (_bfd_elf_link_read_relocs - (abfd, sec, NULL, (Elf_Internal_Rela *) NULL, - link_info->keep_memory)); - if (internal_relocs =3D=3D NULL) - return false; - - irelend =3D internal_relocs + sec->reloc_count; - - /* Get the section contents. */ - if (elf_section_data (sec)->this_hdr.contents !=3D NULL) - contents =3D elf_section_data (sec)->this_hdr.contents; - else - { - if (!bfd_malloc_and_get_section (abfd, sec, &contents)) - goto error_return; - } - - for (irel =3D internal_relocs; irel < irelend; irel++) - { - unsigned long r_type =3D ELF64_R_TYPE (irel->r_info); - bfd_vma symaddr, reladdr, trampoff, toff, roff; - asection *tsec; - struct one_fixup *f; - bfd_size_type amt; - bool is_branch; - struct elf64_ia64_dyn_sym_info *dyn_i; - - switch (r_type) - { - case R_IA64_PCREL21B: - case R_IA64_PCREL21BI: - case R_IA64_PCREL21M: - case R_IA64_PCREL21F: - /* In pass 1, all br relaxations are done. We can skip it. */ - if (link_info->relax_pass =3D=3D 1) - continue; - skip_relax_pass_0 =3D false; - is_branch =3D true; - break; - - case R_IA64_PCREL60B: - /* We can't optimize brl to br in pass 0 since br relaxations - will increase the code size. Defer it to pass 1. */ - if (link_info->relax_pass =3D=3D 0) - { - skip_relax_pass_1 =3D false; - continue; - } - is_branch =3D true; - break; - - case R_IA64_GPREL22: - /* Update max_short_sec/min_short_sec. */ - - case R_IA64_LTOFF22X: - case R_IA64_LDXMOV: - /* We can't relax ldx/mov in pass 0 since br relaxations will - increase the code size. Defer it to pass 1. */ - if (link_info->relax_pass =3D=3D 0) - { - skip_relax_pass_1 =3D false; - continue; - } - is_branch =3D false; - break; - - default: - continue; - } - - /* Get the value of the symbol referred to by the reloc. */ - if (ELF64_R_SYM (irel->r_info) < symtab_hdr->sh_info) - { - /* A local symbol. */ - Elf_Internal_Sym *isym; - - /* Read this BFD's local symbols. */ - if (isymbuf =3D=3D NULL) - { - isymbuf =3D (Elf_Internal_Sym *) symtab_hdr->contents; - if (isymbuf =3D=3D NULL) - isymbuf =3D bfd_elf_get_elf_syms (abfd, symtab_hdr, - symtab_hdr->sh_info, 0, - NULL, NULL, NULL); - if (isymbuf =3D=3D 0) - goto error_return; - } - - isym =3D isymbuf + ELF64_R_SYM (irel->r_info); - if (isym->st_shndx =3D=3D SHN_UNDEF) - continue; /* We can't do anything with undefined symbols. */ - else if (isym->st_shndx =3D=3D SHN_ABS) - tsec =3D bfd_abs_section_ptr; - else if (isym->st_shndx =3D=3D SHN_COMMON) - tsec =3D bfd_com_section_ptr; - else if (isym->st_shndx =3D=3D SHN_IA_64_ANSI_COMMON) - tsec =3D bfd_com_section_ptr; - else - tsec =3D bfd_section_from_elf_index (abfd, isym->st_shndx); - - toff =3D isym->st_value; - dyn_i =3D get_dyn_sym_info (ia64_info, NULL, abfd, irel, false); - } - else - { - unsigned long indx; - struct elf_link_hash_entry *h; - - indx =3D ELF64_R_SYM (irel->r_info) - symtab_hdr->sh_info; - h =3D elf_sym_hashes (abfd)[indx]; - BFD_ASSERT (h !=3D NULL); - - while (h->root.type =3D=3D bfd_link_hash_indirect - || h->root.type =3D=3D bfd_link_hash_warning) - h =3D (struct elf_link_hash_entry *) h->root.u.i.link; - - dyn_i =3D get_dyn_sym_info (ia64_info, h, abfd, irel, false); - - /* For branches to dynamic symbols, we're interested instead - in a branch to the PLT entry. */ - if (is_branch && dyn_i && dyn_i->want_plt2) - { - /* Internal branches shouldn't be sent to the PLT. - Leave this for now and we'll give an error later. */ - if (r_type !=3D R_IA64_PCREL21B) - continue; - - tsec =3D ia64_info->root.splt; - toff =3D dyn_i->plt2_offset; - BFD_ASSERT (irel->r_addend =3D=3D 0); - } - - /* Can't do anything else with dynamic symbols. */ - else if (elf64_ia64_dynamic_symbol_p (h)) - continue; - - else - { - /* We can't do anything with undefined symbols. */ - if (h->root.type =3D=3D bfd_link_hash_undefined - || h->root.type =3D=3D bfd_link_hash_undefweak) - continue; - - tsec =3D h->root.u.def.section; - toff =3D h->root.u.def.value; - } - } - - toff +=3D irel->r_addend; - - symaddr =3D tsec->output_section->vma + tsec->output_offset + toff; - - roff =3D irel->r_offset; - - if (is_branch) - { - bfd_signed_vma offset; - - reladdr =3D (sec->output_section->vma - + sec->output_offset - + roff) & (bfd_vma) -4; - - /* The .plt section is aligned at 32byte and the .text section - is aligned at 64byte. The .text section is right after the - .plt section. After the first relaxation pass, linker may - increase the gap between the .plt and .text sections up - to 32byte. We assume linker will always insert 32byte - between the .plt and .text sections after the first - relaxation pass. */ - if (tsec =3D=3D ia64_info->root.splt) - offset =3D -0x1000000 + 32; - else - offset =3D -0x1000000; - - /* If the branch is in range, no need to do anything. */ - if ((bfd_signed_vma) (symaddr - reladdr) >=3D offset - && (bfd_signed_vma) (symaddr - reladdr) <=3D 0x0FFFFF0) - { - /* If the 60-bit branch is in 21-bit range, optimize it. */ - if (r_type =3D=3D R_IA64_PCREL60B) - { - ia64_elf_relax_brl (contents, roff); - - irel->r_info =3D ELF64_R_INFO (ELF64_R_SYM (irel->r_info), - R_IA64_PCREL21B); - - /* If the original relocation offset points to slot - 1, change it to slot 2. */ - if ((irel->r_offset & 3) =3D=3D 1) - irel->r_offset +=3D 1; - } - - continue; - } - else if (r_type =3D=3D R_IA64_PCREL60B) - continue; - else if (ia64_elf_relax_br (contents, roff)) - { - irel->r_info =3D ELF64_R_INFO (ELF64_R_SYM (irel->r_info), - R_IA64_PCREL60B); - - /* Make the relocation offset point to slot 1. */ - irel->r_offset =3D (irel->r_offset & ~((bfd_vma) 0x3)) + 1; - continue; - } - - /* We can't put a trampoline in a .init/.fini section. Issue - an error. */ - if (strcmp (sec->output_section->name, ".init") =3D=3D 0 - || strcmp (sec->output_section->name, ".fini") =3D=3D 0) - { - _bfd_error_handler - /* xgettext:c-format */ - (_("%pB: can't relax br at %#" PRIx64 " in section `%pA';" - " please use brl or indirect branch"), - sec->owner, (uint64_t) roff, sec); - bfd_set_error (bfd_error_bad_value); - goto error_return; - } - - /* If the branch and target are in the same section, you've - got one honking big section and we can't help you unless - you are branching backwards. You'll get an error message - later. */ - if (tsec =3D=3D sec && toff > roff) - continue; - - /* Look for an existing fixup to this address. */ - for (f =3D fixups; f ; f =3D f->next) - if (f->tsec =3D=3D tsec && f->toff =3D=3D toff) - break; - - if (f =3D=3D NULL) - { - /* Two alternatives: If it's a branch to a PLT entry, we can - make a copy of the FULL_PLT entry. Otherwise, we'll have - to use a `brl' insn to get where we're going. */ - - size_t size; - - if (tsec =3D=3D ia64_info->root.splt) - size =3D sizeof (plt_full_entry); - else - size =3D sizeof (oor_brl); - - /* Resize the current section to make room for the new branch. */ - trampoff =3D (sec->size + 15) & (bfd_vma) -16; - - /* If trampoline is out of range, there is nothing we - can do. */ - offset =3D trampoff - (roff & (bfd_vma) -4); - if (offset < -0x1000000 || offset > 0x0FFFFF0) - continue; - - amt =3D trampoff + size; - contents =3D (bfd_byte *) bfd_realloc (contents, amt); - if (contents =3D=3D NULL) - goto error_return; - sec->size =3D amt; - - if (tsec =3D=3D ia64_info->root.splt) - { - memcpy (contents + trampoff, plt_full_entry, size); - - /* Hijack the old relocation for use as the PLTOFF reloc. */ - irel->r_info =3D ELF64_R_INFO (ELF64_R_SYM (irel->r_info), - R_IA64_PLTOFF22); - irel->r_offset =3D trampoff; - } - else - { - memcpy (contents + trampoff, oor_brl, size); - irel->r_info =3D ELF64_R_INFO (ELF64_R_SYM (irel->r_info), - R_IA64_PCREL60B); - irel->r_offset =3D trampoff + 2; - } - - /* Record the fixup so we don't do it again this section. */ - f =3D (struct one_fixup *) - bfd_malloc ((bfd_size_type) sizeof (*f)); - f->next =3D fixups; - f->tsec =3D tsec; - f->toff =3D toff; - f->trampoff =3D trampoff; - fixups =3D f; - } - else - { - /* If trampoline is out of range, there is nothing we - can do. */ - offset =3D f->trampoff - (roff & (bfd_vma) -4); - if (offset < -0x1000000 || offset > 0x0FFFFF0) - continue; - - /* Nop out the reloc, since we're finalizing things here. */ - irel->r_info =3D ELF64_R_INFO (0, R_IA64_NONE); - } - - /* Fix up the existing branch to hit the trampoline. */ - if (ia64_elf_install_value (contents + roff, offset, r_type) - !=3D bfd_reloc_ok) - goto error_return; - - changed_contents =3D true; - changed_relocs =3D true; - } - else - { - /* Fetch the gp. */ - if (gp =3D=3D 0) - { - bfd *obfd =3D sec->output_section->owner; - gp =3D _bfd_get_gp_value (obfd); - if (gp =3D=3D 0) - { - if (!elf64_ia64_choose_gp (obfd, link_info, false)) - goto error_return; - gp =3D _bfd_get_gp_value (obfd); - } - } - - /* If the data is out of range, do nothing. */ - if ((bfd_signed_vma) (symaddr - gp) >=3D 0x200000 - ||(bfd_signed_vma) (symaddr - gp) < -0x200000) - continue; - - if (r_type =3D=3D R_IA64_GPREL22) - elf64_ia64_update_short_info (tsec->output_section, - tsec->output_offset + toff, - ia64_info); - else if (r_type =3D=3D R_IA64_LTOFF22X) - { - /* Can't deal yet correctly with ABS symbols. */ - if (bfd_is_abs_section (tsec)) - continue; - - irel->r_info =3D ELF64_R_INFO (ELF64_R_SYM (irel->r_info), - R_IA64_GPREL22); - changed_relocs =3D true; - - elf64_ia64_update_short_info (tsec->output_section, - tsec->output_offset + toff, - ia64_info); - } - else - { - ia64_elf_relax_ldxmov (contents, roff); - irel->r_info =3D ELF64_R_INFO (0, R_IA64_NONE); - changed_contents =3D true; - changed_relocs =3D true; - } - } - } - - /* ??? If we created fixups, this may push the code segment large - enough that the data segment moves, which will change the GP. - Reset the GP so that we re-calculate next round. We need to - do this at the _beginning_ of the next round; now will not do. */ - - /* Clean up and go home. */ - while (fixups) - { - struct one_fixup *f =3D fixups; - fixups =3D fixups->next; - free (f); - } - - if (isymbuf !=3D NULL - && symtab_hdr->contents !=3D (unsigned char *) isymbuf) - { - if (! link_info->keep_memory) - free (isymbuf); - else - { - /* Cache the symbols for elf_link_input_bfd. */ - symtab_hdr->contents =3D (unsigned char *) isymbuf; - } - } - - if (contents !=3D NULL - && elf_section_data (sec)->this_hdr.contents !=3D contents) - { - if (!changed_contents && !link_info->keep_memory) - free (contents); - else - { - /* Cache the section contents for elf_link_input_bfd. */ - elf_section_data (sec)->this_hdr.contents =3D contents; - } - } - - if (elf_section_data (sec)->relocs !=3D internal_relocs) - { - if (!changed_relocs) - free (internal_relocs); - else - elf_section_data (sec)->relocs =3D internal_relocs; - } - - if (link_info->relax_pass =3D=3D 0) - { - /* Pass 0 is only needed to relax br. */ - sec->skip_relax_pass_0 =3D skip_relax_pass_0; - sec->skip_relax_pass_1 =3D skip_relax_pass_1; - } - - *again =3D changed_contents || changed_relocs; - return true; - - error_return: - if ((unsigned char *) isymbuf !=3D symtab_hdr->contents) - free (isymbuf); - if (elf_section_data (sec)->this_hdr.contents !=3D contents) - free (contents); - if (elf_section_data (sec)->relocs !=3D internal_relocs) - free (internal_relocs); - return false; -} -#undef skip_relax_pass_0 -#undef skip_relax_pass_1 - -/* Return TRUE if NAME is an unwind table section name. */ - -static inline bool -is_unwind_section_name (bfd *abfd ATTRIBUTE_UNUSED, const char *name) -{ - return ((startswith (name, ELF_STRING_ia64_unwind) - && ! startswith (name, ELF_STRING_ia64_unwind_info)) - || startswith (name, ELF_STRING_ia64_unwind_once)); -} - - -/* Convert IA-64 specific section flags to bfd internal section flags. */ - -/* ??? There is no bfd internal flag equivalent to the SHF_IA_64_NORECOV - flag. */ - -static bool -elf64_ia64_section_flags (const Elf_Internal_Shdr *hdr) -{ - if (hdr->sh_flags & SHF_IA_64_SHORT) - hdr->bfd_section->flags |=3D SEC_SMALL_DATA; - - return true; -} - -/* Set the correct type for an IA-64 ELF section. We do this by the - section name, which is a hack, but ought to work. */ - -static bool -elf64_ia64_fake_sections (bfd *abfd, Elf_Internal_Shdr *hdr, - asection *sec) -{ - const char *name; - - name =3D bfd_section_name (sec); - - if (is_unwind_section_name (abfd, name)) - { - /* We don't have the sections numbered at this point, so sh_info - is set later, in elf64_ia64_final_write_processing. */ - hdr->sh_type =3D SHT_IA_64_UNWIND; - hdr->sh_flags |=3D SHF_LINK_ORDER; - } - else if (strcmp (name, ELF_STRING_ia64_archext) =3D=3D 0) - hdr->sh_type =3D SHT_IA_64_EXT; - - if (sec->flags & SEC_SMALL_DATA) - hdr->sh_flags |=3D SHF_IA_64_SHORT; - - return true; -} - -/* Hook called by the linker routine which adds symbols from an object - file. We use it to put .comm items in .sbss, and not .bss. */ - -static bool -elf64_ia64_add_symbol_hook (bfd *abfd, - struct bfd_link_info *info, - Elf_Internal_Sym *sym, - const char **namep ATTRIBUTE_UNUSED, - flagword *flagsp ATTRIBUTE_UNUSED, - asection **secp, - bfd_vma *valp) -{ - if (sym->st_shndx =3D=3D SHN_COMMON - && !bfd_link_relocatable (info) - && sym->st_size <=3D elf_gp_size (abfd)) - { - /* Common symbols less than or equal to -G nn bytes are - automatically put into .sbss. */ - - asection *scomm =3D bfd_get_section_by_name (abfd, ".scommon"); - - if (scomm =3D=3D NULL) - { - scomm =3D bfd_make_section_with_flags (abfd, ".scommon", - (SEC_ALLOC - | SEC_IS_COMMON - | SEC_SMALL_DATA - | SEC_LINKER_CREATED)); - if (scomm =3D=3D NULL) - return false; - } - - *secp =3D scomm; - *valp =3D sym->st_size; - } - - return true; -} - -/* According to the Tahoe assembler spec, all labels starting with a - '.' are local. */ - -static bool -elf64_ia64_is_local_label_name (bfd *abfd ATTRIBUTE_UNUSED, - const char *name) -{ - return name[0] =3D=3D '.'; -} - -/* Should we do dynamic things to this symbol? */ - -static bool -elf64_ia64_dynamic_symbol_p (struct elf_link_hash_entry *h) -{ - return h !=3D NULL && h->def_dynamic; -} - -static struct bfd_hash_entry* -elf64_ia64_new_elf_hash_entry (struct bfd_hash_entry *entry, - struct bfd_hash_table *table, - const char *string) -{ - struct elf64_ia64_link_hash_entry *ret; - ret =3D (struct elf64_ia64_link_hash_entry *) entry; - - /* Allocate the structure if it has not already been allocated by a - subclass. */ - if (!ret) - ret =3D bfd_hash_allocate (table, sizeof (*ret)); - - if (!ret) - return 0; - - /* Call the allocation method of the superclass. */ - ret =3D ((struct elf64_ia64_link_hash_entry *) - _bfd_elf_link_hash_newfunc ((struct bfd_hash_entry *) ret, - table, string)); - - ret->info =3D NULL; - ret->count =3D 0; - ret->sorted_count =3D 0; - ret->size =3D 0; - return (struct bfd_hash_entry *) ret; -} - -static void -elf64_ia64_hash_hide_symbol (struct bfd_link_info *info, - struct elf_link_hash_entry *xh, - bool force_local) -{ - struct elf64_ia64_link_hash_entry *h; - struct elf64_ia64_dyn_sym_info *dyn_i; - unsigned int count; - - h =3D (struct elf64_ia64_link_hash_entry *)xh; - - _bfd_elf_link_hash_hide_symbol (info, &h->root, force_local); - - for (count =3D h->count, dyn_i =3D h->info; - count !=3D 0; - count--, dyn_i++) - { - dyn_i->want_plt2 =3D 0; - dyn_i->want_plt =3D 0; - } -} - -/* Compute a hash of a local hash entry. */ - -static hashval_t -elf64_ia64_local_htab_hash (const void *ptr) -{ - struct elf64_ia64_local_hash_entry *entry - =3D (struct elf64_ia64_local_hash_entry *) ptr; - - return ELF_LOCAL_SYMBOL_HASH (entry->id, entry->r_sym); -} - -/* Compare local hash entries. */ - -static int -elf64_ia64_local_htab_eq (const void *ptr1, const void *ptr2) -{ - struct elf64_ia64_local_hash_entry *entry1 - =3D (struct elf64_ia64_local_hash_entry *) ptr1; - struct elf64_ia64_local_hash_entry *entry2 - =3D (struct elf64_ia64_local_hash_entry *) ptr2; - - return entry1->id =3D=3D entry2->id && entry1->r_sym =3D=3D entry2->r_sy= m; -} - -/* Free the global elf64_ia64_dyn_sym_info array. */ - -static bool -elf64_ia64_global_dyn_info_free (struct elf_link_hash_entry *xentry, - void * unused ATTRIBUTE_UNUSED) -{ - struct elf64_ia64_link_hash_entry *entry - =3D (struct elf64_ia64_link_hash_entry *) xentry; - - if (entry->root.root.type =3D=3D bfd_link_hash_warning) - entry =3D (struct elf64_ia64_link_hash_entry *) entry->root.root.u.i.l= ink; - - free (entry->info); - entry->info =3D NULL; - entry->count =3D 0; - entry->sorted_count =3D 0; - entry->size =3D 0; - - return true; -} - -/* Free the local elf64_ia64_dyn_sym_info array. */ - -static int -elf64_ia64_local_dyn_info_free (void **slot, - void * unused ATTRIBUTE_UNUSED) -{ - struct elf64_ia64_local_hash_entry *entry - =3D (struct elf64_ia64_local_hash_entry *) *slot; - - free (entry->info); - entry->info =3D NULL; - entry->count =3D 0; - entry->sorted_count =3D 0; - entry->size =3D 0; - - return true; -} - -/* Destroy IA-64 linker hash table. */ - -static void -elf64_ia64_link_hash_table_free (bfd *obfd) -{ - struct elf64_ia64_link_hash_table *ia64_info - =3D (struct elf64_ia64_link_hash_table *) obfd->link.hash; - if (ia64_info->loc_hash_table) - { - htab_traverse (ia64_info->loc_hash_table, - elf64_ia64_local_dyn_info_free, NULL); - htab_delete (ia64_info->loc_hash_table); - } - if (ia64_info->loc_hash_memory) - objalloc_free ((struct objalloc *) ia64_info->loc_hash_memory); - elf_link_hash_traverse (&ia64_info->root, - elf64_ia64_global_dyn_info_free, NULL); - _bfd_elf_link_hash_table_free (obfd); -} - -/* Create the derived linker hash table. The IA-64 ELF port uses this - derived hash table to keep information specific to the IA-64 ElF - linker (without using static variables). */ - -static struct bfd_link_hash_table * -elf64_ia64_hash_table_create (bfd *abfd) -{ - struct elf64_ia64_link_hash_table *ret; - - ret =3D bfd_zmalloc ((bfd_size_type) sizeof (*ret)); - if (!ret) - return NULL; - - if (!_bfd_elf_link_hash_table_init (&ret->root, abfd, - elf64_ia64_new_elf_hash_entry, - sizeof (struct elf64_ia64_link_hash_entry), - IA64_ELF_DATA)) - { - free (ret); - return NULL; - } - - ret->loc_hash_table =3D htab_try_create (1024, elf64_ia64_local_htab_has= h, - elf64_ia64_local_htab_eq, NULL); - ret->loc_hash_memory =3D objalloc_create (); - if (!ret->loc_hash_table || !ret->loc_hash_memory) - { - elf64_ia64_link_hash_table_free (abfd); - return NULL; - } - ret->root.root.hash_table_free =3D elf64_ia64_link_hash_table_free; - - return &ret->root.root; -} - -/* Traverse both local and global hash tables. */ - -struct elf64_ia64_dyn_sym_traverse_data -{ - bool (*func) (struct elf64_ia64_dyn_sym_info *, void *); - void * data; -}; - -static bool -elf64_ia64_global_dyn_sym_thunk (struct elf_link_hash_entry *xentry, - void * xdata) -{ - struct elf64_ia64_link_hash_entry *entry - =3D (struct elf64_ia64_link_hash_entry *) xentry; - struct elf64_ia64_dyn_sym_traverse_data *data - =3D (struct elf64_ia64_dyn_sym_traverse_data *) xdata; - struct elf64_ia64_dyn_sym_info *dyn_i; - unsigned int count; - - if (entry->root.root.type =3D=3D bfd_link_hash_warning) - entry =3D (struct elf64_ia64_link_hash_entry *) entry->root.root.u.i.l= ink; - - for (count =3D entry->count, dyn_i =3D entry->info; - count !=3D 0; - count--, dyn_i++) - if (! (*data->func) (dyn_i, data->data)) - return false; - return true; -} - -static int -elf64_ia64_local_dyn_sym_thunk (void **slot, void * xdata) -{ - struct elf64_ia64_local_hash_entry *entry - =3D (struct elf64_ia64_local_hash_entry *) *slot; - struct elf64_ia64_dyn_sym_traverse_data *data - =3D (struct elf64_ia64_dyn_sym_traverse_data *) xdata; - struct elf64_ia64_dyn_sym_info *dyn_i; - unsigned int count; - - for (count =3D entry->count, dyn_i =3D entry->info; - count !=3D 0; - count--, dyn_i++) - if (! (*data->func) (dyn_i, data->data)) - return false; - return true; -} - -static void -elf64_ia64_dyn_sym_traverse (struct elf64_ia64_link_hash_table *ia64_info, - bool (*func) (struct elf64_ia64_dyn_sym_info *, void *), - void * data) -{ - struct elf64_ia64_dyn_sym_traverse_data xdata; - - xdata.func =3D func; - xdata.data =3D data; - - elf_link_hash_traverse (&ia64_info->root, - elf64_ia64_global_dyn_sym_thunk, &xdata); - htab_traverse (ia64_info->loc_hash_table, - elf64_ia64_local_dyn_sym_thunk, &xdata); -} - -#define NOTE_NAME "IPF/VMS" - -static bool -create_ia64_vms_notes (bfd *abfd, struct bfd_link_info *info, - unsigned int time_hi, unsigned int time_lo) -{ -#define NBR_NOTES 7 - Elf_Internal_Note notes[NBR_NOTES]; - char *module_name; - int module_name_len; - unsigned char cur_time[8]; - Elf64_External_VMS_ORIG_DYN_Note *orig_dyn; - unsigned int orig_dyn_size; - unsigned int note_size; - int i; - unsigned char *noteptr; - unsigned char *note_contents; - struct elf64_ia64_link_hash_table *ia64_info; - - ia64_info =3D elf64_ia64_hash_table (info); - - module_name =3D vms_get_module_name (bfd_get_filename (abfd), true); - module_name_len =3D strlen (module_name) + 1; - - bfd_putl32 (time_lo, cur_time + 0); - bfd_putl32 (time_hi, cur_time + 4); - - /* Note 0: IMGNAM. */ - notes[0].type =3D NT_VMS_IMGNAM; - notes[0].descdata =3D module_name; - notes[0].descsz =3D module_name_len; - - /* Note 1: GSTNAM. */ - notes[1].type =3D NT_VMS_GSTNAM; - notes[1].descdata =3D module_name; - notes[1].descsz =3D module_name_len; - - /* Note 2: IMGID. */ -#define IMG_ID "V1.0" - notes[2].type =3D NT_VMS_IMGID; - notes[2].descdata =3D IMG_ID; - notes[2].descsz =3D sizeof (IMG_ID); - - /* Note 3: Linktime. */ - notes[3].type =3D NT_VMS_LINKTIME; - notes[3].descdata =3D (char *)cur_time; - notes[3].descsz =3D sizeof (cur_time); - - /* Note 4: Linker id. */ - notes[4].type =3D NT_VMS_LINKID; - notes[4].descdata =3D "GNU ld " BFD_VERSION_STRING; - notes[4].descsz =3D strlen (notes[4].descdata) + 1; - - /* Note 5: Original dyn. */ - orig_dyn_size =3D (sizeof (*orig_dyn) + sizeof (IMG_ID) - 1 + 7) & ~7; - orig_dyn =3D bfd_zalloc (abfd, orig_dyn_size); - if (orig_dyn =3D=3D NULL) - return false; - bfd_putl32 (1, orig_dyn->major_id); - bfd_putl32 (3, orig_dyn->minor_id); - memcpy (orig_dyn->manipulation_date, cur_time, sizeof (cur_time)); - bfd_putl64 (VMS_LF_IMGSTA | VMS_LF_MAIN, orig_dyn->link_flags); - bfd_putl32 (EF_IA_64_ABI64, orig_dyn->elf_flags); - memcpy (orig_dyn->imgid, IMG_ID, sizeof (IMG_ID)); - notes[5].type =3D NT_VMS_ORIG_DYN; - notes[5].descdata =3D (char *)orig_dyn; - notes[5].descsz =3D orig_dyn_size; - - /* Note 3: Patchtime. */ - notes[6].type =3D NT_VMS_PATCHTIME; - notes[6].descdata =3D (char *)cur_time; - notes[6].descsz =3D sizeof (cur_time); - - /* Compute notes size. */ - note_size =3D 0; - for (i =3D 0; i < NBR_NOTES; i++) - note_size +=3D sizeof (Elf64_External_VMS_Note) - 1 - + ((sizeof (NOTE_NAME) - 1 + 7) & ~7) - + ((notes[i].descsz + 7) & ~7); - - /* Malloc a temporary buffer large enough for most notes */ - note_contents =3D (unsigned char *) bfd_zalloc (abfd, note_size); - if (note_contents =3D=3D NULL) - return false; - noteptr =3D note_contents; - - /* Fill notes. */ - for (i =3D 0; i < NBR_NOTES; i++) - { - Elf64_External_VMS_Note *enote =3D (Elf64_External_VMS_Note *) notep= tr; - - bfd_putl64 (sizeof (NOTE_NAME) - 1, enote->namesz); - bfd_putl64 (notes[i].descsz, enote->descsz); - bfd_putl64 (notes[i].type, enote->type); - - noteptr =3D (unsigned char *)enote->name; - memcpy (noteptr, NOTE_NAME, sizeof (NOTE_NAME) - 1); - noteptr +=3D (sizeof (NOTE_NAME) - 1 + 7) & ~7; - memcpy (noteptr, notes[i].descdata, notes[i].descsz); - noteptr +=3D (notes[i].descsz + 7) & ~7; - } - - ia64_info->note_sec->contents =3D note_contents; - ia64_info->note_sec->size =3D note_size; - - free (module_name); - - return true; -} - -static bool -elf64_ia64_create_dynamic_sections (bfd *abfd, - struct bfd_link_info *info) -{ - struct elf64_ia64_link_hash_table *ia64_info; - asection *s; - flagword flags; - const struct elf_backend_data *bed; - - ia64_info =3D elf64_ia64_hash_table (info); - if (ia64_info =3D=3D NULL) - return false; - - if (elf_hash_table (info)->dynamic_sections_created) - return true; - - abfd =3D elf_hash_table (info)->dynobj; - bed =3D get_elf_backend_data (abfd); - - flags =3D bed->dynamic_sec_flags; - - s =3D bfd_make_section_anyway_with_flags (abfd, ".dynamic", - flags | SEC_READONLY); - if (s =3D=3D NULL - || !bfd_set_section_alignment (s, bed->s->log_file_align)) - return false; - - s =3D bfd_make_section_anyway_with_flags (abfd, ".plt", flags | SEC_READ= ONLY); - if (s =3D=3D NULL - || !bfd_set_section_alignment (s, bed->plt_alignment)) - return false; - ia64_info->root.splt =3D s; - - if (!get_got (abfd, ia64_info)) - return false; - - if (!get_pltoff (abfd, ia64_info)) - return false; - - s =3D bfd_make_section_anyway_with_flags (abfd, ".vmsdynstr", - (SEC_ALLOC - | SEC_HAS_CONTENTS - | SEC_IN_MEMORY - | SEC_LINKER_CREATED)); - if (s =3D=3D NULL - || !bfd_set_section_alignment (s, 0)) - return false; - - /* Create a fixup section. */ - s =3D bfd_make_section_anyway_with_flags (abfd, ".fixups", - (SEC_ALLOC - | SEC_HAS_CONTENTS - | SEC_IN_MEMORY - | SEC_LINKER_CREATED)); - if (s =3D=3D NULL - || !bfd_set_section_alignment (s, 3)) - return false; - ia64_info->fixups_sec =3D s; - - /* Create the transfer fixup section. */ - s =3D bfd_make_section_anyway_with_flags (abfd, ".transfer", - (SEC_ALLOC - | SEC_HAS_CONTENTS - | SEC_IN_MEMORY - | SEC_LINKER_CREATED)); - if (s =3D=3D NULL - || !bfd_set_section_alignment (s, 3)) - return false; - s->size =3D sizeof (struct elf64_vms_transfer); - ia64_info->transfer_sec =3D s; - - /* Create note section. */ - s =3D bfd_make_section_anyway_with_flags (abfd, ".vms.note", - (SEC_LINKER_CREATED - | SEC_HAS_CONTENTS - | SEC_IN_MEMORY - | SEC_READONLY)); - if (s =3D=3D NULL - || !bfd_set_section_alignment (s, 3)) - return false; - ia64_info->note_sec =3D s; - - elf_hash_table (info)->dynamic_sections_created =3D true; - return true; -} - -/* Find and/or create a hash entry for local symbol. */ -static struct elf64_ia64_local_hash_entry * -get_local_sym_hash (struct elf64_ia64_link_hash_table *ia64_info, - bfd *abfd, const Elf_Internal_Rela *rel, - bool create) -{ - struct elf64_ia64_local_hash_entry e, *ret; - asection *sec =3D abfd->sections; - hashval_t h =3D ELF_LOCAL_SYMBOL_HASH (sec->id, - ELF64_R_SYM (rel->r_info)); - void **slot; - - e.id =3D sec->id; - e.r_sym =3D ELF64_R_SYM (rel->r_info); - slot =3D htab_find_slot_with_hash (ia64_info->loc_hash_table, &e, h, - create ? INSERT : NO_INSERT); - - if (!slot) - return NULL; - - if (*slot) - return (struct elf64_ia64_local_hash_entry *) *slot; - - ret =3D (struct elf64_ia64_local_hash_entry *) - objalloc_alloc ((struct objalloc *) ia64_info->loc_hash_memory, - sizeof (struct elf64_ia64_local_hash_entry)); - if (ret) - { - memset (ret, 0, sizeof (*ret)); - ret->id =3D sec->id; - ret->r_sym =3D ELF64_R_SYM (rel->r_info); - *slot =3D ret; - } - return ret; -} - -/* Used to sort elf64_ia64_dyn_sym_info array. */ - -static int -addend_compare (const void *xp, const void *yp) -{ - const struct elf64_ia64_dyn_sym_info *x - =3D (const struct elf64_ia64_dyn_sym_info *) xp; - const struct elf64_ia64_dyn_sym_info *y - =3D (const struct elf64_ia64_dyn_sym_info *) yp; - - return x->addend < y->addend ? -1 : x->addend > y->addend ? 1 : 0; -} - -/* Sort elf64_ia64_dyn_sym_info array and remove duplicates. */ - -static unsigned int -sort_dyn_sym_info (struct elf64_ia64_dyn_sym_info *info, - unsigned int count) -{ - bfd_vma curr, prev, got_offset; - unsigned int i, kept, dupes, diff, dest, src, len; - - qsort (info, count, sizeof (*info), addend_compare); - - /* Find the first duplicate. */ - prev =3D info [0].addend; - got_offset =3D info [0].got_offset; - for (i =3D 1; i < count; i++) - { - curr =3D info [i].addend; - if (curr =3D=3D prev) - { - /* For duplicates, make sure that GOT_OFFSET is valid. */ - if (got_offset =3D=3D (bfd_vma) -1) - got_offset =3D info [i].got_offset; - break; - } - got_offset =3D info [i].got_offset; - prev =3D curr; - } - - /* We may move a block of elements to here. */ - dest =3D i++; - - /* Remove duplicates. */ - if (i < count) - { - while (i < count) - { - /* For duplicates, make sure that the kept one has a valid - got_offset. */ - kept =3D dest - 1; - if (got_offset !=3D (bfd_vma) -1) - info [kept].got_offset =3D got_offset; - - curr =3D info [i].addend; - got_offset =3D info [i].got_offset; - - /* Move a block of elements whose first one is different from - the previous. */ - if (curr =3D=3D prev) - { - for (src =3D i + 1; src < count; src++) - { - if (info [src].addend !=3D curr) - break; - /* For duplicates, make sure that GOT_OFFSET is - valid. */ - if (got_offset =3D=3D (bfd_vma) -1) - got_offset =3D info [src].got_offset; - } - - /* Make sure that the kept one has a valid got_offset. */ - if (got_offset !=3D (bfd_vma) -1) - info [kept].got_offset =3D got_offset; - } - else - src =3D i; - - if (src >=3D count) - break; - - /* Find the next duplicate. SRC will be kept. */ - prev =3D info [src].addend; - got_offset =3D info [src].got_offset; - for (dupes =3D src + 1; dupes < count; dupes ++) - { - curr =3D info [dupes].addend; - if (curr =3D=3D prev) - { - /* Make sure that got_offset is valid. */ - if (got_offset =3D=3D (bfd_vma) -1) - got_offset =3D info [dupes].got_offset; - - /* For duplicates, make sure that the kept one has - a valid got_offset. */ - if (got_offset !=3D (bfd_vma) -1) - info [dupes - 1].got_offset =3D got_offset; - break; - } - got_offset =3D info [dupes].got_offset; - prev =3D curr; - } - - /* How much to move. */ - len =3D dupes - src; - i =3D dupes + 1; - - if (len =3D=3D 1 && dupes < count) - { - /* If we only move 1 element, we combine it with the next - one. There must be at least a duplicate. Find the - next different one. */ - for (diff =3D dupes + 1, src++; diff < count; diff++, src++) - { - if (info [diff].addend !=3D curr) - break; - /* Make sure that got_offset is valid. */ - if (got_offset =3D=3D (bfd_vma) -1) - got_offset =3D info [diff].got_offset; - } - - /* Makre sure that the last duplicated one has an valid - offset. */ - BFD_ASSERT (curr =3D=3D prev); - if (got_offset !=3D (bfd_vma) -1) - info [diff - 1].got_offset =3D got_offset; - - if (diff < count) - { - /* Find the next duplicate. Track the current valid - offset. */ - prev =3D info [diff].addend; - got_offset =3D info [diff].got_offset; - for (dupes =3D diff + 1; dupes < count; dupes ++) - { - curr =3D info [dupes].addend; - if (curr =3D=3D prev) - { - /* For duplicates, make sure that GOT_OFFSET - is valid. */ - if (got_offset =3D=3D (bfd_vma) -1) - got_offset =3D info [dupes].got_offset; - break; - } - got_offset =3D info [dupes].got_offset; - prev =3D curr; - diff++; - } - - len =3D diff - src + 1; - i =3D diff + 1; - } - } - - memmove (&info [dest], &info [src], len * sizeof (*info)); - - dest +=3D len; - } - - count =3D dest; - } - else - { - /* When we get here, either there is no duplicate at all or - the only duplicate is the last element. */ - if (dest < count) - { - /* If the last element is a duplicate, make sure that the - kept one has a valid got_offset. We also update count. */ - if (got_offset !=3D (bfd_vma) -1) - info [dest - 1].got_offset =3D got_offset; - count =3D dest; - } - } - - return count; -} - -/* Find and/or create a descriptor for dynamic symbol info. This will - vary based on global or local symbol, and the addend to the reloc. - - We don't sort when inserting. Also, we sort and eliminate - duplicates if there is an unsorted section. Typically, this will - only happen once, because we do all insertions before lookups. We - then use bsearch to do a lookup. This also allows lookups to be - fast. So we have fast insertion (O(log N) due to duplicate check), - fast lookup (O(log N)) and one sort (O(N log N) expected time). - Previously, all lookups were O(N) because of the use of the linked - list and also all insertions were O(N) because of the check for - duplicates. There are some complications here because the array - size grows occasionally, which may add an O(N) factor, but this - should be rare. Also, we free the excess array allocation, which - requires a copy which is O(N), but this only happens once. */ - -static struct elf64_ia64_dyn_sym_info * -get_dyn_sym_info (struct elf64_ia64_link_hash_table *ia64_info, - struct elf_link_hash_entry *h, bfd *abfd, - const Elf_Internal_Rela *rel, bool create) -{ - struct elf64_ia64_dyn_sym_info **info_p, *info, *dyn_i, key; - unsigned int *count_p, *sorted_count_p, *size_p; - unsigned int count, sorted_count, size; - bfd_vma addend =3D rel ? rel->r_addend : 0; - bfd_size_type amt; - - if (h) - { - struct elf64_ia64_link_hash_entry *global_h; - - global_h =3D (struct elf64_ia64_link_hash_entry *) h; - info_p =3D &global_h->info; - count_p =3D &global_h->count; - sorted_count_p =3D &global_h->sorted_count; - size_p =3D &global_h->size; - } - else - { - struct elf64_ia64_local_hash_entry *loc_h; - - loc_h =3D get_local_sym_hash (ia64_info, abfd, rel, create); - if (!loc_h) - { - BFD_ASSERT (!create); - return NULL; - } - - info_p =3D &loc_h->info; - count_p =3D &loc_h->count; - sorted_count_p =3D &loc_h->sorted_count; - size_p =3D &loc_h->size; - } - - count =3D *count_p; - sorted_count =3D *sorted_count_p; - size =3D *size_p; - info =3D *info_p; - if (create) - { - /* When we create the array, we don't check for duplicates, - except in the previously sorted section if one exists, and - against the last inserted entry. This allows insertions to - be fast. */ - if (info) - { - if (sorted_count) - { - /* Try bsearch first on the sorted section. */ - key.addend =3D addend; - dyn_i =3D bsearch (&key, info, sorted_count, - sizeof (*info), addend_compare); - - if (dyn_i) - { - return dyn_i; - } - } - - /* Do a quick check for the last inserted entry. */ - dyn_i =3D info + count - 1; - if (dyn_i->addend =3D=3D addend) - { - return dyn_i; - } - } - - if (size =3D=3D 0) - { - /* It is the very first element. We create the array of size - 1. */ - size =3D 1; - amt =3D size * sizeof (*info); - info =3D bfd_malloc (amt); - } - else if (size <=3D count) - { - /* We double the array size every time when we reach the - size limit. */ - size +=3D size; - amt =3D size * sizeof (*info); - info =3D bfd_realloc (info, amt); - } - else - goto has_space; - - if (info =3D=3D NULL) - return NULL; - *size_p =3D size; - *info_p =3D info; - - has_space: - /* Append the new one to the array. */ - dyn_i =3D info + count; - memset (dyn_i, 0, sizeof (*dyn_i)); - dyn_i->got_offset =3D (bfd_vma) -1; - dyn_i->addend =3D addend; - - /* We increment count only since the new ones are unsorted and - may have duplicate. */ - (*count_p)++; - } - else - { - /* It is a lookup without insertion. Sort array if part of the - array isn't sorted. */ - if (count !=3D sorted_count) - { - count =3D sort_dyn_sym_info (info, count); - *count_p =3D count; - *sorted_count_p =3D count; - } - - /* Free unused memory. */ - if (size !=3D count) - { - amt =3D count * sizeof (*info); - info =3D bfd_malloc (amt); - if (info !=3D NULL) - { - memcpy (info, *info_p, amt); - free (*info_p); - *size_p =3D count; - *info_p =3D info; - } - } - - key.addend =3D addend; - dyn_i =3D bsearch (&key, info, count, - sizeof (*info), addend_compare); - } - - return dyn_i; -} - -static asection * -get_got (bfd *abfd, struct elf64_ia64_link_hash_table *ia64_info) -{ - asection *got; - bfd *dynobj; - - got =3D ia64_info->root.sgot; - if (!got) - { - flagword flags; - - dynobj =3D ia64_info->root.dynobj; - if (!dynobj) - ia64_info->root.dynobj =3D dynobj =3D abfd; - - /* The .got section is always aligned at 8 bytes. */ - flags =3D get_elf_backend_data (dynobj)->dynamic_sec_flags; - got =3D bfd_make_section_anyway_with_flags (dynobj, ".got", - flags | SEC_SMALL_DATA); - if (got =3D=3D NULL - || !bfd_set_section_alignment (got, 3)) - return NULL; - ia64_info->root.sgot =3D got; - } - - return got; -} - -/* Create function descriptor section (.opd). This section is called .opd - because it contains "official procedure descriptors". The "official" - refers to the fact that these descriptors are used when taking the addr= ess - of a procedure, thus ensuring a unique address for each procedure. */ - -static asection * -get_fptr (bfd *abfd, struct bfd_link_info *info, - struct elf64_ia64_link_hash_table *ia64_info) -{ - asection *fptr; - bfd *dynobj; - - fptr =3D ia64_info->fptr_sec; - if (!fptr) - { - dynobj =3D ia64_info->root.dynobj; - if (!dynobj) - ia64_info->root.dynobj =3D dynobj =3D abfd; - - fptr =3D bfd_make_section_anyway_with_flags (dynobj, ".opd", - (SEC_ALLOC - | SEC_LOAD - | SEC_HAS_CONTENTS - | SEC_IN_MEMORY - | (bfd_link_pie (info) ? 0 - : SEC_READONLY) - | SEC_LINKER_CREATED)); - if (!fptr - || !bfd_set_section_alignment (fptr, 4)) - { - BFD_ASSERT (0); - return NULL; - } - - ia64_info->fptr_sec =3D fptr; - - if (bfd_link_pie (info)) - { - asection *fptr_rel; - fptr_rel =3D bfd_make_section_anyway_with_flags (dynobj, ".rela.opd", - (SEC_ALLOC | SEC_LOAD - | SEC_HAS_CONTENTS - | SEC_IN_MEMORY - | SEC_LINKER_CREATED - | SEC_READONLY)); - if (fptr_rel =3D=3D NULL - || !bfd_set_section_alignment (fptr_rel, 3)) - { - BFD_ASSERT (0); - return NULL; - } - - ia64_info->rel_fptr_sec =3D fptr_rel; - } - } - - return fptr; -} - -static asection * -get_pltoff (bfd *abfd, struct elf64_ia64_link_hash_table *ia64_info) -{ - asection *pltoff; - bfd *dynobj; - - pltoff =3D ia64_info->pltoff_sec; - if (!pltoff) - { - dynobj =3D ia64_info->root.dynobj; - if (!dynobj) - ia64_info->root.dynobj =3D dynobj =3D abfd; - - pltoff =3D bfd_make_section_anyway_with_flags (dynobj, - ELF_STRING_ia64_pltoff, - (SEC_ALLOC - | SEC_LOAD - | SEC_HAS_CONTENTS - | SEC_IN_MEMORY - | SEC_SMALL_DATA - | SEC_LINKER_CREATED)); - if (!pltoff - || !bfd_set_section_alignment (pltoff, 4)) - { - BFD_ASSERT (0); - return NULL; - } - - ia64_info->pltoff_sec =3D pltoff; - } - - return pltoff; -} - -static asection * -get_reloc_section (bfd *abfd, - struct elf64_ia64_link_hash_table *ia64_info, - asection *sec, bool create) -{ - const char *srel_name; - asection *srel; - bfd *dynobj; - - srel_name =3D (bfd_elf_string_from_elf_section - (abfd, elf_elfheader(abfd)->e_shstrndx, - _bfd_elf_single_rel_hdr (sec)->sh_name)); - if (srel_name =3D=3D NULL) - return NULL; - - BFD_ASSERT ((startswith (srel_name, ".rela") - && strcmp (bfd_section_name (sec), srel_name+5) =3D=3D 0) - || (startswith (srel_name, ".rel") - && strcmp (bfd_section_name (sec), srel_name+4) =3D=3D 0)); - - dynobj =3D ia64_info->root.dynobj; - if (!dynobj) - ia64_info->root.dynobj =3D dynobj =3D abfd; - - srel =3D bfd_get_linker_section (dynobj, srel_name); - if (srel =3D=3D NULL && create) - { - srel =3D bfd_make_section_anyway_with_flags (dynobj, srel_name, - (SEC_ALLOC | SEC_LOAD - | SEC_HAS_CONTENTS - | SEC_IN_MEMORY - | SEC_LINKER_CREATED - | SEC_READONLY)); - if (srel =3D=3D NULL - || !bfd_set_section_alignment (srel, 3)) - return NULL; - } - - return srel; -} - -static bool -count_dyn_reloc (bfd *abfd, struct elf64_ia64_dyn_sym_info *dyn_i, - asection *srel, int type) -{ - struct elf64_ia64_dyn_reloc_entry *rent; - - for (rent =3D dyn_i->reloc_entries; rent; rent =3D rent->next) - if (rent->srel =3D=3D srel && rent->type =3D=3D type) - break; - - if (!rent) - { - rent =3D ((struct elf64_ia64_dyn_reloc_entry *) - bfd_alloc (abfd, (bfd_size_type) sizeof (*rent))); - if (!rent) - return false; - - rent->next =3D dyn_i->reloc_entries; - rent->srel =3D srel; - rent->type =3D type; - rent->count =3D 0; - dyn_i->reloc_entries =3D rent; - } - rent->count++; - - return true; -} - -static bool -elf64_ia64_check_relocs (bfd *abfd, struct bfd_link_info *info, - asection *sec, - const Elf_Internal_Rela *relocs) -{ - struct elf64_ia64_link_hash_table *ia64_info; - const Elf_Internal_Rela *relend; - Elf_Internal_Shdr *symtab_hdr; - const Elf_Internal_Rela *rel; - asection *got, *fptr, *srel, *pltoff; - enum { - NEED_GOT =3D 1, - NEED_GOTX =3D 2, - NEED_FPTR =3D 4, - NEED_PLTOFF =3D 8, - NEED_MIN_PLT =3D 16, - NEED_FULL_PLT =3D 32, - NEED_DYNREL =3D 64, - NEED_LTOFF_FPTR =3D 128 - }; - int need_entry; - struct elf_link_hash_entry *h; - unsigned long r_symndx; - bool maybe_dynamic; - - if (bfd_link_relocatable (info)) - return true; - - symtab_hdr =3D &elf_tdata (abfd)->symtab_hdr; - ia64_info =3D elf64_ia64_hash_table (info); - if (ia64_info =3D=3D NULL) - return false; - - got =3D fptr =3D srel =3D pltoff =3D NULL; - - relend =3D relocs + sec->reloc_count; - - /* We scan relocations first to create dynamic relocation arrays. We - modified get_dyn_sym_info to allow fast insertion and support fast - lookup in the next loop. */ - for (rel =3D relocs; rel < relend; ++rel) - { - r_symndx =3D ELF64_R_SYM (rel->r_info); - if (r_symndx >=3D symtab_hdr->sh_info) - { - long indx =3D r_symndx - symtab_hdr->sh_info; - h =3D elf_sym_hashes (abfd)[indx]; - while (h->root.type =3D=3D bfd_link_hash_indirect - || h->root.type =3D=3D bfd_link_hash_warning) - h =3D (struct elf_link_hash_entry *) h->root.u.i.link; - } - else - h =3D NULL; - - /* We can only get preliminary data on whether a symbol is - locally or externally defined, as not all of the input files - have yet been processed. Do something with what we know, as - this may help reduce memory usage and processing time later. */ - maybe_dynamic =3D (h && ((!bfd_link_executable (info) - && (!SYMBOLIC_BIND (info, h) - || info->unresolved_syms_in_shared_libs =3D=3D RM_IGNORE)) - || !h->def_regular - || h->root.type =3D=3D bfd_link_hash_defweak)); - - need_entry =3D 0; - switch (ELF64_R_TYPE (rel->r_info)) - { - case R_IA64_TPREL64MSB: - case R_IA64_TPREL64LSB: - case R_IA64_LTOFF_TPREL22: - case R_IA64_DTPREL32MSB: - case R_IA64_DTPREL32LSB: - case R_IA64_DTPREL64MSB: - case R_IA64_DTPREL64LSB: - case R_IA64_LTOFF_DTPREL22: - case R_IA64_DTPMOD64MSB: - case R_IA64_DTPMOD64LSB: - case R_IA64_LTOFF_DTPMOD22: - abort (); - break; - - case R_IA64_IPLTMSB: - case R_IA64_IPLTLSB: - break; - - case R_IA64_LTOFF_FPTR22: - case R_IA64_LTOFF_FPTR64I: - case R_IA64_LTOFF_FPTR32MSB: - case R_IA64_LTOFF_FPTR32LSB: - case R_IA64_LTOFF_FPTR64MSB: - case R_IA64_LTOFF_FPTR64LSB: - need_entry =3D NEED_FPTR | NEED_GOT | NEED_LTOFF_FPTR; - break; - - case R_IA64_FPTR64I: - case R_IA64_FPTR32MSB: - case R_IA64_FPTR32LSB: - case R_IA64_FPTR64MSB: - case R_IA64_FPTR64LSB: - if (bfd_link_pic (info) || h) - need_entry =3D NEED_FPTR | NEED_DYNREL; - else - need_entry =3D NEED_FPTR; - break; - - case R_IA64_LTOFF22: - case R_IA64_LTOFF64I: - need_entry =3D NEED_GOT; - break; - - case R_IA64_LTOFF22X: - need_entry =3D NEED_GOTX; - break; - - case R_IA64_PLTOFF22: - case R_IA64_PLTOFF64I: - case R_IA64_PLTOFF64MSB: - case R_IA64_PLTOFF64LSB: - need_entry =3D NEED_PLTOFF; - if (h) - { - if (maybe_dynamic) - need_entry |=3D NEED_MIN_PLT; - } - else - { - (*info->callbacks->warning) - (info, _("@pltoff reloc against local symbol"), 0, - abfd, 0, (bfd_vma) 0); - } - break; - - case R_IA64_PCREL21B: - case R_IA64_PCREL60B: - /* Depending on where this symbol is defined, we may or may not - need a full plt entry. Only skip if we know we'll not need - the entry -- static or symbolic, and the symbol definition - has already been seen. */ - if (maybe_dynamic && rel->r_addend =3D=3D 0) - need_entry =3D NEED_FULL_PLT; - break; - - case R_IA64_IMM14: - case R_IA64_IMM22: - case R_IA64_IMM64: - case R_IA64_DIR32MSB: - case R_IA64_DIR32LSB: - case R_IA64_DIR64MSB: - case R_IA64_DIR64LSB: - /* Shared objects will always need at least a REL relocation. */ - if (bfd_link_pic (info) || maybe_dynamic) - need_entry =3D NEED_DYNREL; - break; - - case R_IA64_PCREL22: - case R_IA64_PCREL64I: - case R_IA64_PCREL32MSB: - case R_IA64_PCREL32LSB: - case R_IA64_PCREL64MSB: - case R_IA64_PCREL64LSB: - if (maybe_dynamic) - need_entry =3D NEED_DYNREL; - break; - } - - if (!need_entry) - continue; - - if ((need_entry & NEED_FPTR) !=3D 0 - && rel->r_addend) - { - (*info->callbacks->warning) - (info, _("non-zero addend in @fptr reloc"), 0, - abfd, 0, (bfd_vma) 0); - } - - if (get_dyn_sym_info (ia64_info, h, abfd, rel, true) =3D=3D NULL) - return false; - } - - /* Now, we only do lookup without insertion, which is very fast - with the modified get_dyn_sym_info. */ - for (rel =3D relocs; rel < relend; ++rel) - { - struct elf64_ia64_dyn_sym_info *dyn_i; - int dynrel_type =3D R_IA64_NONE; - - r_symndx =3D ELF64_R_SYM (rel->r_info); - if (r_symndx >=3D symtab_hdr->sh_info) - { - /* We're dealing with a global symbol -- find its hash entry - and mark it as being referenced. */ - long indx =3D r_symndx - symtab_hdr->sh_info; - h =3D elf_sym_hashes (abfd)[indx]; - while (h->root.type =3D=3D bfd_link_hash_indirect - || h->root.type =3D=3D bfd_link_hash_warning) - h =3D (struct elf_link_hash_entry *) h->root.u.i.link; - - /* PR15323, ref flags aren't set for references in the same - object. */ - h->ref_regular =3D 1; - } - else - h =3D NULL; - - /* We can only get preliminary data on whether a symbol is - locally or externally defined, as not all of the input files - have yet been processed. Do something with what we know, as - this may help reduce memory usage and processing time later. */ - maybe_dynamic =3D (h && ((!bfd_link_executable (info) - && (!SYMBOLIC_BIND (info, h) - || info->unresolved_syms_in_shared_libs =3D=3D RM_IGNORE)) - || !h->def_regular - || h->root.type =3D=3D bfd_link_hash_defweak)); - - need_entry =3D 0; - switch (ELF64_R_TYPE (rel->r_info)) - { - case R_IA64_TPREL64MSB: - case R_IA64_TPREL64LSB: - case R_IA64_LTOFF_TPREL22: - case R_IA64_DTPREL32MSB: - case R_IA64_DTPREL32LSB: - case R_IA64_DTPREL64MSB: - case R_IA64_DTPREL64LSB: - case R_IA64_LTOFF_DTPREL22: - case R_IA64_DTPMOD64MSB: - case R_IA64_DTPMOD64LSB: - case R_IA64_LTOFF_DTPMOD22: - abort (); - break; - - case R_IA64_LTOFF_FPTR22: - case R_IA64_LTOFF_FPTR64I: - case R_IA64_LTOFF_FPTR32MSB: - case R_IA64_LTOFF_FPTR32LSB: - case R_IA64_LTOFF_FPTR64MSB: - case R_IA64_LTOFF_FPTR64LSB: - need_entry =3D NEED_FPTR | NEED_GOT | NEED_LTOFF_FPTR; - break; - - case R_IA64_FPTR64I: - case R_IA64_FPTR32MSB: - case R_IA64_FPTR32LSB: - case R_IA64_FPTR64MSB: - case R_IA64_FPTR64LSB: - if (bfd_link_pic (info) || h) - need_entry =3D NEED_FPTR | NEED_DYNREL; - else - need_entry =3D NEED_FPTR; - dynrel_type =3D R_IA64_FPTR64LSB; - break; - - case R_IA64_LTOFF22: - case R_IA64_LTOFF64I: - need_entry =3D NEED_GOT; - break; - - case R_IA64_LTOFF22X: - need_entry =3D NEED_GOTX; - break; - - case R_IA64_PLTOFF22: - case R_IA64_PLTOFF64I: - case R_IA64_PLTOFF64MSB: - case R_IA64_PLTOFF64LSB: - need_entry =3D NEED_PLTOFF; - if (h) - { - if (maybe_dynamic) - need_entry |=3D NEED_MIN_PLT; - } - break; - - case R_IA64_PCREL21B: - case R_IA64_PCREL60B: - /* Depending on where this symbol is defined, we may or may not - need a full plt entry. Only skip if we know we'll not need - the entry -- static or symbolic, and the symbol definition - has already been seen. */ - if (maybe_dynamic && rel->r_addend =3D=3D 0) - need_entry =3D NEED_FULL_PLT; - break; - - case R_IA64_IMM14: - case R_IA64_IMM22: - case R_IA64_IMM64: - case R_IA64_DIR32MSB: - case R_IA64_DIR32LSB: - case R_IA64_DIR64MSB: - case R_IA64_DIR64LSB: - /* Shared objects will always need at least a REL relocation. */ - if (bfd_link_pic (info) || maybe_dynamic) - need_entry =3D NEED_DYNREL; - dynrel_type =3D R_IA64_DIR64LSB; - break; - - case R_IA64_IPLTMSB: - case R_IA64_IPLTLSB: - break; - - case R_IA64_PCREL22: - case R_IA64_PCREL64I: - case R_IA64_PCREL32MSB: - case R_IA64_PCREL32LSB: - case R_IA64_PCREL64MSB: - case R_IA64_PCREL64LSB: - if (maybe_dynamic) - need_entry =3D NEED_DYNREL; - dynrel_type =3D R_IA64_PCREL64LSB; - break; - } - - if (!need_entry) - continue; - - dyn_i =3D get_dyn_sym_info (ia64_info, h, abfd, rel, false); - - /* Record whether or not this is a local symbol. */ - dyn_i->h =3D h; - - /* Create what's needed. */ - if (need_entry & (NEED_GOT | NEED_GOTX)) - { - if (!got) - { - got =3D get_got (abfd, ia64_info); - if (!got) - return false; - } - if (need_entry & NEED_GOT) - dyn_i->want_got =3D 1; - if (need_entry & NEED_GOTX) - dyn_i->want_gotx =3D 1; - } - if (need_entry & NEED_FPTR) - { - /* Create the .opd section. */ - if (!fptr) - { - fptr =3D get_fptr (abfd, info, ia64_info); - if (!fptr) - return false; - } - dyn_i->want_fptr =3D 1; - } - if (need_entry & NEED_LTOFF_FPTR) - dyn_i->want_ltoff_fptr =3D 1; - if (need_entry & (NEED_MIN_PLT | NEED_FULL_PLT)) - { - if (!ia64_info->root.dynobj) - ia64_info->root.dynobj =3D abfd; - h->needs_plt =3D 1; - dyn_i->want_plt =3D 1; - } - if (need_entry & NEED_FULL_PLT) - dyn_i->want_plt2 =3D 1; - if (need_entry & NEED_PLTOFF) - { - /* This is needed here, in case @pltoff is used in a non-shared - link. */ - if (!pltoff) - { - pltoff =3D get_pltoff (abfd, ia64_info); - if (!pltoff) - return false; - } - - dyn_i->want_pltoff =3D 1; - } - if ((need_entry & NEED_DYNREL) && (sec->flags & SEC_ALLOC)) - { - if (!srel) - { - srel =3D get_reloc_section (abfd, ia64_info, sec, true); - if (!srel) - return false; - } - if (!count_dyn_reloc (abfd, dyn_i, srel, dynrel_type)) - return false; - } - } - - return true; -} - -/* For cleanliness, and potentially faster dynamic loading, allocate - external GOT entries first. */ - -static bool -allocate_global_data_got (struct elf64_ia64_dyn_sym_info *dyn_i, - void * data) -{ - struct elf64_ia64_allocate_data *x =3D (struct elf64_ia64_allocate_data = *)data; - - if ((dyn_i->want_got || dyn_i->want_gotx) - && ! dyn_i->want_fptr - && elf64_ia64_dynamic_symbol_p (dyn_i->h)) - { - /* GOT entry with FPTR is done by allocate_global_fptr_got. */ - dyn_i->got_offset =3D x->ofs; - x->ofs +=3D 8; - } - return true; -} - -/* Next, allocate all the GOT entries used by LTOFF_FPTR relocs. */ - -static bool -allocate_global_fptr_got (struct elf64_ia64_dyn_sym_info *dyn_i, - void * data) -{ - struct elf64_ia64_allocate_data *x =3D (struct elf64_ia64_allocate_data = *)data; - - if (dyn_i->want_got - && dyn_i->want_fptr - && elf64_ia64_dynamic_symbol_p (dyn_i->h)) - { - dyn_i->got_offset =3D x->ofs; - x->ofs +=3D 8; - } - return true; -} - -/* Lastly, allocate all the GOT entries for local data. */ - -static bool -allocate_local_got (struct elf64_ia64_dyn_sym_info *dyn_i, - void * data) -{ - struct elf64_ia64_allocate_data *x =3D (struct elf64_ia64_allocate_data = *) data; - - if ((dyn_i->want_got || dyn_i->want_gotx) - && !elf64_ia64_dynamic_symbol_p (dyn_i->h)) - { - dyn_i->got_offset =3D x->ofs; - x->ofs +=3D 8; - } - return true; -} - -/* Allocate function descriptors. We can do these for every function - in a main executable that is not exported. */ - -static bool -allocate_fptr (struct elf64_ia64_dyn_sym_info *dyn_i, void * data) -{ - struct elf64_ia64_allocate_data *x =3D (struct elf64_ia64_allocate_data = *) data; - - if (dyn_i->want_fptr) - { - struct elf_link_hash_entry *h =3D dyn_i->h; - - if (h) - while (h->root.type =3D=3D bfd_link_hash_indirect - || h->root.type =3D=3D bfd_link_hash_warning) - h =3D (struct elf_link_hash_entry *) h->root.u.i.link; - - if (h =3D=3D NULL || !h->def_dynamic) - { - /* A non dynamic symbol. */ - dyn_i->fptr_offset =3D x->ofs; - x->ofs +=3D 16; - } - else - dyn_i->want_fptr =3D 0; - } - return true; -} - -/* Allocate all the minimal PLT entries. */ - -static bool -allocate_plt_entries (struct elf64_ia64_dyn_sym_info *dyn_i, - void * data ATTRIBUTE_UNUSED) -{ - if (dyn_i->want_plt) - { - struct elf_link_hash_entry *h =3D dyn_i->h; - - if (h) - while (h->root.type =3D=3D bfd_link_hash_indirect - || h->root.type =3D=3D bfd_link_hash_warning) - h =3D (struct elf_link_hash_entry *) h->root.u.i.link; - - /* ??? Versioned symbols seem to lose NEEDS_PLT. */ - if (elf64_ia64_dynamic_symbol_p (h)) - { - dyn_i->want_pltoff =3D 1; - } - else - { - dyn_i->want_plt =3D 0; - dyn_i->want_plt2 =3D 0; - } - } - return true; -} - -/* Allocate all the full PLT entries. */ - -static bool -allocate_plt2_entries (struct elf64_ia64_dyn_sym_info *dyn_i, - void * data) -{ - struct elf64_ia64_allocate_data *x =3D (struct elf64_ia64_allocate_data = *)data; - - if (dyn_i->want_plt2) - { - struct elf_link_hash_entry *h =3D dyn_i->h; - bfd_size_type ofs =3D x->ofs; - - dyn_i->plt2_offset =3D ofs; - x->ofs =3D ofs + PLT_FULL_ENTRY_SIZE; - - while (h->root.type =3D=3D bfd_link_hash_indirect - || h->root.type =3D=3D bfd_link_hash_warning) - h =3D (struct elf_link_hash_entry *) h->root.u.i.link; - dyn_i->h->plt.offset =3D ofs; - } - return true; -} - -/* Allocate all the PLTOFF entries requested by relocations and - plt entries. We can't share space with allocated FPTR entries, - because the latter are not necessarily addressable by the GP. - ??? Relaxation might be able to determine that they are. */ - -static bool -allocate_pltoff_entries (struct elf64_ia64_dyn_sym_info *dyn_i, - void * data) -{ - struct elf64_ia64_allocate_data *x =3D (struct elf64_ia64_allocate_data = *)data; - - if (dyn_i->want_pltoff) - { - dyn_i->pltoff_offset =3D x->ofs; - x->ofs +=3D 16; - } - return true; -} - -/* Allocate dynamic relocations for those symbols that turned out - to be dynamic. */ - -static bool -allocate_dynrel_entries (struct elf64_ia64_dyn_sym_info *dyn_i, - void * data) -{ - struct elf64_ia64_allocate_data *x =3D (struct elf64_ia64_allocate_data = *)data; - struct elf64_ia64_link_hash_table *ia64_info; - struct elf64_ia64_dyn_reloc_entry *rent; - bool dynamic_symbol, shared, resolved_zero; - struct elf64_ia64_link_hash_entry *h_ia64; - - ia64_info =3D elf64_ia64_hash_table (x->info); - if (ia64_info =3D=3D NULL) - return false; - - /* Note that this can't be used in relation to FPTR relocs below. */ - dynamic_symbol =3D elf64_ia64_dynamic_symbol_p (dyn_i->h); - - shared =3D bfd_link_pic (x->info); - resolved_zero =3D (dyn_i->h - && ELF_ST_VISIBILITY (dyn_i->h->other) - && dyn_i->h->root.type =3D=3D bfd_link_hash_undefweak); - - /* Take care of the GOT and PLT relocations. */ - - if ((!resolved_zero - && (dynamic_symbol || shared) - && (dyn_i->want_got || dyn_i->want_gotx)) - || (dyn_i->want_ltoff_fptr - && dyn_i->h - && dyn_i->h->def_dynamic)) - { - /* VMS: FIX64. */ - if (dyn_i->h !=3D NULL && dyn_i->h->def_dynamic) - { - h_ia64 =3D (struct elf64_ia64_link_hash_entry *) dyn_i->h; - elf_ia64_vms_tdata (h_ia64->shl)->fixups_off +=3D - sizeof (Elf64_External_VMS_IMAGE_FIXUP); - ia64_info->fixups_sec->size +=3D - sizeof (Elf64_External_VMS_IMAGE_FIXUP); - } - } - - if (ia64_info->rel_fptr_sec && dyn_i->want_fptr) - { - /* VMS: only image reloc. */ - if (dyn_i->h =3D=3D NULL || dyn_i->h->root.type !=3D bfd_link_hash_u= ndefweak) - ia64_info->rel_fptr_sec->size +=3D sizeof (Elf64_External_Rela); - } - - if (!resolved_zero && dyn_i->want_pltoff) - { - /* VMS: FIXFD. */ - if (dyn_i->h !=3D NULL && dyn_i->h->def_dynamic) - { - h_ia64 =3D (struct elf64_ia64_link_hash_entry *) dyn_i->h; - elf_ia64_vms_tdata (h_ia64->shl)->fixups_off +=3D - sizeof (Elf64_External_VMS_IMAGE_FIXUP); - ia64_info->fixups_sec->size +=3D - sizeof (Elf64_External_VMS_IMAGE_FIXUP); - } - } - - /* Take care of the normal data relocations. */ - - for (rent =3D dyn_i->reloc_entries; rent; rent =3D rent->next) - { - switch (rent->type) - { - case R_IA64_FPTR32LSB: - case R_IA64_FPTR64LSB: - /* Allocate one iff !want_fptr and not PIE, which by this point - will be true only if we're actually allocating one statically - in the main executable. Position independent executables - need a relative reloc. */ - if (dyn_i->want_fptr && !bfd_link_pie (x->info)) - continue; - break; - case R_IA64_PCREL32LSB: - case R_IA64_PCREL64LSB: - if (!dynamic_symbol) - continue; - break; - case R_IA64_DIR32LSB: - case R_IA64_DIR64LSB: - if (!dynamic_symbol && !shared) - continue; - break; - case R_IA64_IPLTLSB: - if (!dynamic_symbol && !shared) - continue; - break; - case R_IA64_DTPREL32LSB: - case R_IA64_TPREL64LSB: - case R_IA64_DTPREL64LSB: - case R_IA64_DTPMOD64LSB: - break; - default: - abort (); - } - - /* Add a fixup. */ - if (!dynamic_symbol) - abort (); - - h_ia64 =3D (struct elf64_ia64_link_hash_entry *) dyn_i->h; - elf_ia64_vms_tdata (h_ia64->shl)->fixups_off +=3D - sizeof (Elf64_External_VMS_IMAGE_FIXUP); - ia64_info->fixups_sec->size +=3D - sizeof (Elf64_External_VMS_IMAGE_FIXUP); - } - - return true; -} - -static bool -elf64_ia64_adjust_dynamic_symbol (struct bfd_link_info *info ATTRIBUTE_UNU= SED, - struct elf_link_hash_entry *h) -{ - /* ??? Undefined symbols with PLT entries should be re-defined - to be the PLT entry. */ - - /* If this is a weak symbol, and there is a real definition, the - processor independent code will have arranged for us to see the - real definition first, and we can just use the same value. */ - if (h->is_weakalias) - { - struct elf_link_hash_entry *def =3D weakdef (h); - BFD_ASSERT (def->root.type =3D=3D bfd_link_hash_defined); - h->root.u.def.section =3D def->root.u.def.section; - h->root.u.def.value =3D def->root.u.def.value; - return true; - } - - /* If this is a reference to a symbol defined by a dynamic object which - is not a function, we might allocate the symbol in our .dynbss section - and allocate a COPY dynamic relocation. - - But IA-64 code is canonically PIC, so as a rule we can avoid this sort - of hackery. */ - - return true; -} - -static bool -elf64_ia64_late_size_sections (bfd *output_bfd ATTRIBUTE_UNUSED, - struct bfd_link_info *info) -{ - struct elf64_ia64_allocate_data data; - struct elf64_ia64_link_hash_table *ia64_info; - asection *sec; - bfd *dynobj; - struct elf_link_hash_table *hash_table; - - hash_table =3D elf_hash_table (info); - ia64_info =3D elf64_ia64_hash_table (info); - if (ia64_info =3D=3D NULL) - return false; - dynobj =3D hash_table->dynobj; - if (dynobj =3D=3D NULL) - return true; - data.info =3D info; - - /* Allocate the GOT entries. */ - - if (ia64_info->root.sgot) - { - data.ofs =3D 0; - elf64_ia64_dyn_sym_traverse (ia64_info, allocate_global_data_got, &d= ata); - elf64_ia64_dyn_sym_traverse (ia64_info, allocate_global_fptr_got, &d= ata); - elf64_ia64_dyn_sym_traverse (ia64_info, allocate_local_got, &data); - ia64_info->root.sgot->size =3D data.ofs; - } - - /* Allocate the FPTR entries. */ - - if (ia64_info->fptr_sec) - { - data.ofs =3D 0; - elf64_ia64_dyn_sym_traverse (ia64_info, allocate_fptr, &data); - ia64_info->fptr_sec->size =3D data.ofs; - } - - /* Now that we've seen all of the input files, we can decide which - symbols need plt entries. Allocate the minimal PLT entries first. - We do this even though dynamic_sections_created may be FALSE, because - this has the side-effect of clearing want_plt and want_plt2. */ - - data.ofs =3D 0; - elf64_ia64_dyn_sym_traverse (ia64_info, allocate_plt_entries, &data); - - /* Align the pointer for the plt2 entries. */ - data.ofs =3D (data.ofs + 31) & (bfd_vma) -32; - - elf64_ia64_dyn_sym_traverse (ia64_info, allocate_plt2_entries, &data); - if (data.ofs !=3D 0 || ia64_info->root.dynamic_sections_created) - { - /* FIXME: we always reserve the memory for dynamic linker even if - there are no PLT entries since dynamic linker may assume the - reserved memory always exists. */ - - BFD_ASSERT (ia64_info->root.dynamic_sections_created); - - ia64_info->root.splt->size =3D data.ofs; - } - - /* Allocate the PLTOFF entries. */ - - if (ia64_info->pltoff_sec) - { - data.ofs =3D 0; - elf64_ia64_dyn_sym_traverse (ia64_info, allocate_pltoff_entries, &da= ta); - ia64_info->pltoff_sec->size =3D data.ofs; - } - - if (ia64_info->root.dynamic_sections_created) - { - /* Allocate space for the dynamic relocations that turned out to be - required. */ - elf64_ia64_dyn_sym_traverse (ia64_info, allocate_dynrel_entries, &da= ta); - } - - /* We have now determined the sizes of the various dynamic sections. - Allocate memory for them. */ - for (sec =3D dynobj->sections; sec !=3D NULL; sec =3D sec->next) - { - bool strip; - - if (!(sec->flags & SEC_LINKER_CREATED)) - continue; - - /* If we don't need this section, strip it from the output file. - There were several sections primarily related to dynamic - linking that must be create before the linker maps input - sections to output sections. The linker does that before - bfd_elf_size_dynamic_sections is called, and it is that - function which decides whether anything needs to go into - these sections. */ - - strip =3D (sec->size =3D=3D 0); - - if (sec =3D=3D ia64_info->root.sgot) - strip =3D false; - else if (sec =3D=3D ia64_info->root.srelgot) - { - if (strip) - ia64_info->root.srelgot =3D NULL; - else - /* We use the reloc_count field as a counter if we need to - copy relocs into the output file. */ - sec->reloc_count =3D 0; - } - else if (sec =3D=3D ia64_info->fptr_sec) - { - if (strip) - ia64_info->fptr_sec =3D NULL; - } - else if (sec =3D=3D ia64_info->rel_fptr_sec) - { - if (strip) - ia64_info->rel_fptr_sec =3D NULL; - else - /* We use the reloc_count field as a counter if we need to - copy relocs into the output file. */ - sec->reloc_count =3D 0; - } - else if (sec =3D=3D ia64_info->root.splt) - { - if (strip) - ia64_info->root.splt =3D NULL; - } - else if (sec =3D=3D ia64_info->pltoff_sec) - { - if (strip) - ia64_info->pltoff_sec =3D NULL; - } - else if (sec =3D=3D ia64_info->fixups_sec) - { - if (strip) - ia64_info->fixups_sec =3D NULL; - } - else if (sec =3D=3D ia64_info->transfer_sec) - { - ; - } - else - { - const char *name; - - /* It's OK to base decisions on the section name, because none - of the dynobj section names depend upon the input files. */ - name =3D bfd_section_name (sec); - - if (strcmp (name, ".got.plt") =3D=3D 0) - strip =3D false; - else if (startswith (name, ".rel")) - { - if (!strip) - { - /* We use the reloc_count field as a counter if we need to - copy relocs into the output file. */ - sec->reloc_count =3D 0; - } - } - else - continue; - } - - if (strip) - sec->flags |=3D SEC_EXCLUDE; - else - { - /* Allocate memory for the section contents. */ - sec->contents =3D (bfd_byte *) bfd_zalloc (dynobj, sec->size); - if (sec->contents =3D=3D NULL && sec->size !=3D 0) - return false; - } - } - - if (elf_hash_table (info)->dynamic_sections_created) - { - bfd *abfd; - asection *dynsec; - asection *dynstrsec; - Elf_Internal_Dyn dyn; - const struct elf_backend_data *bed; - unsigned int shl_num =3D 0; - bfd_vma fixups_off =3D 0; - bfd_vma strdyn_off; - unsigned int time_hi, time_lo; - - /* The .dynamic section must exist and be empty. */ - dynsec =3D bfd_get_linker_section (hash_table->dynobj, ".dynamic"); - BFD_ASSERT (dynsec !=3D NULL); - BFD_ASSERT (dynsec->size =3D=3D 0); - - dynstrsec =3D bfd_get_linker_section (hash_table->dynobj, ".vmsdynst= r"); - BFD_ASSERT (dynstrsec !=3D NULL); - BFD_ASSERT (dynstrsec->size =3D=3D 0); - dynstrsec->size =3D 1; /* Initial blank. */ - - /* Ident + link time. */ - vms_get_time (&time_hi, &time_lo); - - if (!_bfd_elf_add_dynamic_entry (info, DT_IA_64_VMS_IDENT, 0)) - return false; - if (!_bfd_elf_add_dynamic_entry (info, DT_IA_64_VMS_LINKTIME, - ((uint64_t) time_hi << 32) - + time_lo)) - return false; - - /* Strtab. */ - strdyn_off =3D dynsec->size; - if (!_bfd_elf_add_dynamic_entry (info, DT_IA_64_VMS_STRTAB_OFFSET, 0= )) - return false; - if (!_bfd_elf_add_dynamic_entry (info, DT_STRSZ, 0)) - return false; - - /* PLTGOT */ - if (!_bfd_elf_add_dynamic_entry (info, DT_IA_64_VMS_PLTGOT_SEG, 0)) - return false; - if (!_bfd_elf_add_dynamic_entry (info, DT_IA_64_VMS_PLTGOT_OFFSET, 0= )) - return false; - - /* Misc. */ - if (!_bfd_elf_add_dynamic_entry (info, DT_IA_64_VMS_FPMODE, 0x980000= 0)) - return false; - if (!_bfd_elf_add_dynamic_entry (info, DT_IA_64_VMS_LNKFLAGS, - VMS_LF_IMGSTA | VMS_LF_MAIN)) - return false; - - /* Add entries for shared libraries. */ - for (abfd =3D info->input_bfds; abfd; abfd =3D abfd->link.next) - { - char *soname; - size_t soname_len; - bfd_size_type strindex; - bfd_byte *newcontents; - bfd_vma fixups_shl_off; - - if (!(abfd->flags & DYNAMIC)) - continue; - BFD_ASSERT (abfd->xvec =3D=3D output_bfd->xvec); - - if (!_bfd_elf_add_dynamic_entry (info, DT_IA_64_VMS_NEEDED_IDENT, - elf_ia64_vms_ident (abfd))) - return false; - - soname =3D vms_get_module_name (bfd_get_filename (abfd), true); - if (soname =3D=3D NULL) - return false; - strindex =3D dynstrsec->size; - soname_len =3D strlen (soname) + 1; - newcontents =3D (bfd_byte *) bfd_realloc (dynstrsec->contents, - strindex + soname_len); - if (newcontents =3D=3D NULL) - return false; - memcpy (newcontents + strindex, soname, soname_len); - dynstrsec->size +=3D soname_len; - dynstrsec->contents =3D newcontents; - - if (!_bfd_elf_add_dynamic_entry (info, DT_NEEDED, strindex)) - return false; - - if (!_bfd_elf_add_dynamic_entry (info, DT_IA_64_VMS_FIXUP_NEEDED, - shl_num)) - return false; - shl_num++; - - /* The fixups_off was in fact containing the size of the fixup - section. Remap into the offset. */ - fixups_shl_off =3D elf_ia64_vms_tdata (abfd)->fixups_off; - elf_ia64_vms_tdata (abfd)->fixups_off =3D fixups_off; - - if (!_bfd_elf_add_dynamic_entry - (info, DT_IA_64_VMS_FIXUP_RELA_CNT, - fixups_shl_off / sizeof (Elf64_External_VMS_IMAGE_FIXUP))) - return false; - if (!_bfd_elf_add_dynamic_entry (info, DT_IA_64_VMS_FIXUP_RELA_OFF, - fixups_off)) - return false; - fixups_off +=3D fixups_shl_off; - } - - /* Unwind. */ - if (!_bfd_elf_add_dynamic_entry (info, DT_IA_64_VMS_UNWINDSZ, 0)) - return false; - if (!_bfd_elf_add_dynamic_entry (info, DT_IA_64_VMS_UNWIND_CODSEG, 0= )) - return false; - if (!_bfd_elf_add_dynamic_entry (info, DT_IA_64_VMS_UNWIND_INFOSEG, = 0)) - return false; - if (!_bfd_elf_add_dynamic_entry (info, DT_IA_64_VMS_UNWIND_OFFSET, 0= )) - return false; - if (!_bfd_elf_add_dynamic_entry (info, DT_IA_64_VMS_UNWIND_SEG, 0)) - return false; - - if (!_bfd_elf_add_dynamic_entry (info, DT_NULL, 0xdead)) - return false; - - /* Fix the strtab entries. */ - bed =3D get_elf_backend_data (hash_table->dynobj); - - if (dynstrsec->size > 1) - dynstrsec->contents[0] =3D 0; - else - dynstrsec->size =3D 0; - - /* Note: one 'spare' (ie DT_NULL) entry is added by - bfd_elf_size_dynsym_hash_dynstr. */ - dyn.d_tag =3D DT_IA_64_VMS_STRTAB_OFFSET; - dyn.d_un.d_val =3D dynsec->size /* + sizeof (Elf64_External_Dyn) */; - bed->s->swap_dyn_out (hash_table->dynobj, &dyn, - dynsec->contents + strdyn_off); - - dyn.d_tag =3D DT_STRSZ; - dyn.d_un.d_val =3D dynstrsec->size; - bed->s->swap_dyn_out (hash_table->dynobj, &dyn, - dynsec->contents + strdyn_off + bed->s->sizeof_dyn); - - elf_ia64_vms_tdata (output_bfd)->needed_count =3D shl_num; - - /* Note section. */ - if (!create_ia64_vms_notes (output_bfd, info, time_hi, time_lo)) - return false; - } - - /* ??? Perhaps force __gp local. */ - - return true; -} - -static void -elf64_ia64_install_fixup (bfd *output_bfd, - struct elf64_ia64_link_hash_table *ia64_info, - struct elf_link_hash_entry *h, - unsigned int type, asection *sec, bfd_vma offset, - bfd_vma addend) -{ - asection *relsec; - Elf64_External_VMS_IMAGE_FIXUP *fixup; - struct elf64_ia64_link_hash_entry *h_ia64; - bfd_vma fixoff; - Elf_Internal_Phdr *phdr; - - if (h =3D=3D NULL || !h->def_dynamic) - abort (); - - h_ia64 =3D (struct elf64_ia64_link_hash_entry *) h; - fixoff =3D elf_ia64_vms_tdata (h_ia64->shl)->fixups_off; - elf_ia64_vms_tdata (h_ia64->shl)->fixups_off +=3D - sizeof (Elf64_External_VMS_IMAGE_FIXUP); - relsec =3D ia64_info->fixups_sec; - - fixup =3D (Elf64_External_VMS_IMAGE_FIXUP *)(relsec->contents + fixoff); - offset +=3D sec->output_section->vma + sec->output_offset; - - /* FIXME: this is slow. We should cache the last one used, or create a - map. */ - phdr =3D _bfd_elf_find_segment_containing_section - (output_bfd, sec->output_section); - BFD_ASSERT (phdr !=3D NULL); - - bfd_putl64 (offset - phdr->p_vaddr, fixup->fixup_offset); - bfd_putl32 (type, fixup->type); - bfd_putl32 (phdr - elf_tdata (output_bfd)->phdr, fixup->fixup_seg); - bfd_putl64 (addend, fixup->addend); - bfd_putl32 (h->root.u.def.value, fixup->symvec_index); - bfd_putl32 (2, fixup->data_type); -} - -/* Store an entry for target address TARGET_ADDR in the linkage table - and return the gp-relative address of the linkage table entry. */ - -static bfd_vma -set_got_entry (bfd *abfd, struct bfd_link_info *info, - struct elf64_ia64_dyn_sym_info *dyn_i, - bfd_vma addend, bfd_vma value, unsigned int dyn_r_type) -{ - struct elf64_ia64_link_hash_table *ia64_info; - asection *got_sec; - bool done; - bfd_vma got_offset; - - ia64_info =3D elf64_ia64_hash_table (info); - if (ia64_info =3D=3D NULL) - return 0; - - got_sec =3D ia64_info->root.sgot; - - switch (dyn_r_type) - { - case R_IA64_TPREL64LSB: - case R_IA64_DTPMOD64LSB: - case R_IA64_DTPREL32LSB: - case R_IA64_DTPREL64LSB: - abort (); - break; - default: - done =3D dyn_i->got_done; - dyn_i->got_done =3D true; - got_offset =3D dyn_i->got_offset; - break; - } - - BFD_ASSERT ((got_offset & 7) =3D=3D 0); - - if (! done) - { - /* Store the target address in the linkage table entry. */ - bfd_put_64 (abfd, value, got_sec->contents + got_offset); - - /* Install a dynamic relocation if needed. */ - if (((bfd_link_pic (info) - && (!dyn_i->h - || ELF_ST_VISIBILITY (dyn_i->h->other) =3D=3D STV_DEFAULT - || dyn_i->h->root.type !=3D bfd_link_hash_undefweak)) - || elf64_ia64_dynamic_symbol_p (dyn_i->h)) - && (!dyn_i->want_ltoff_fptr - || !bfd_link_pie (info) - || !dyn_i->h - || dyn_i->h->root.type !=3D bfd_link_hash_undefweak)) - { - if (!dyn_i->h || !dyn_i->h->def_dynamic) - { - dyn_r_type =3D R_IA64_REL64LSB; - addend =3D value; - } - - /* VMS: install a FIX32 or FIX64. */ - switch (dyn_r_type) - { - case R_IA64_DIR32LSB: - case R_IA64_FPTR32LSB: - dyn_r_type =3D R_IA64_VMS_FIX32; - break; - case R_IA64_DIR64LSB: - case R_IA64_FPTR64LSB: - dyn_r_type =3D R_IA64_VMS_FIX64; - break; - default: - BFD_ASSERT (false); - break; - } - elf64_ia64_install_fixup - (info->output_bfd, ia64_info, dyn_i->h, - dyn_r_type, got_sec, got_offset, addend); - } - } - - /* Return the address of the linkage table entry. */ - value =3D (got_sec->output_section->vma - + got_sec->output_offset - + got_offset); - - return value; -} - -/* Fill in a function descriptor consisting of the function's code - address and its global pointer. Return the descriptor's address. */ - -static bfd_vma -set_fptr_entry (bfd *abfd, struct bfd_link_info *info, - struct elf64_ia64_dyn_sym_info *dyn_i, - bfd_vma value) -{ - struct elf64_ia64_link_hash_table *ia64_info; - asection *fptr_sec; - - ia64_info =3D elf64_ia64_hash_table (info); - if (ia64_info =3D=3D NULL) - return 0; - - fptr_sec =3D ia64_info->fptr_sec; - - if (!dyn_i->fptr_done) - { - dyn_i->fptr_done =3D 1; - - /* Fill in the function descriptor. */ - bfd_put_64 (abfd, value, fptr_sec->contents + dyn_i->fptr_offset); - bfd_put_64 (abfd, _bfd_get_gp_value (abfd), - fptr_sec->contents + dyn_i->fptr_offset + 8); - } - - /* Return the descriptor's address. */ - value =3D (fptr_sec->output_section->vma - + fptr_sec->output_offset - + dyn_i->fptr_offset); - - return value; -} - -/* Fill in a PLTOFF entry consisting of the function's code address - and its global pointer. Return the descriptor's address. */ - -static bfd_vma -set_pltoff_entry (bfd *abfd, struct bfd_link_info *info, - struct elf64_ia64_dyn_sym_info *dyn_i, - bfd_vma value, bool is_plt) -{ - struct elf64_ia64_link_hash_table *ia64_info; - asection *pltoff_sec; - - ia64_info =3D elf64_ia64_hash_table (info); - if (ia64_info =3D=3D NULL) - return 0; - - pltoff_sec =3D ia64_info->pltoff_sec; - - /* Don't do anything if this symbol uses a real PLT entry. In - that case, we'll fill this in during finish_dynamic_symbol. */ - if ((! dyn_i->want_plt || is_plt) - && !dyn_i->pltoff_done) - { - bfd_vma gp =3D _bfd_get_gp_value (abfd); - - /* Fill in the function descriptor. */ - bfd_put_64 (abfd, value, pltoff_sec->contents + dyn_i->pltoff_offset= ); - bfd_put_64 (abfd, gp, pltoff_sec->contents + dyn_i->pltoff_offset + = 8); - - /* Install dynamic relocations if needed. */ - if (!is_plt - && bfd_link_pic (info) - && (!dyn_i->h - || ELF_ST_VISIBILITY (dyn_i->h->other) =3D=3D STV_DEFAULT - || dyn_i->h->root.type !=3D bfd_link_hash_undefweak)) - { - /* VMS: */ - abort (); - } - - dyn_i->pltoff_done =3D 1; - } - - /* Return the descriptor's address. */ - value =3D (pltoff_sec->output_section->vma - + pltoff_sec->output_offset - + dyn_i->pltoff_offset); - - return value; -} - -/* Called through qsort to sort the .IA_64.unwind section during a - non-relocatable link. Set elf64_ia64_unwind_entry_compare_bfd - to the output bfd so we can do proper endianness frobbing. */ - -static bfd *elf64_ia64_unwind_entry_compare_bfd; - -static int -elf64_ia64_unwind_entry_compare (const void * a, const void * b) -{ - bfd_vma av, bv; - - av =3D bfd_get_64 (elf64_ia64_unwind_entry_compare_bfd, a); - bv =3D bfd_get_64 (elf64_ia64_unwind_entry_compare_bfd, b); - - return (av < bv ? -1 : av > bv ? 1 : 0); -} - -/* Make sure we've got ourselves a nice fat __gp value. */ -static bool -elf64_ia64_choose_gp (bfd *abfd, struct bfd_link_info *info, bool final) -{ - bfd_vma min_vma =3D (bfd_vma) -1, max_vma =3D 0; - bfd_vma min_short_vma =3D min_vma, max_short_vma =3D 0; - struct elf_link_hash_entry *gp; - bfd_vma gp_val; - asection *os; - struct elf64_ia64_link_hash_table *ia64_info; - - ia64_info =3D elf64_ia64_hash_table (info); - if (ia64_info =3D=3D NULL) - return false; - - /* Find the min and max vma of all sections marked short. Also collect - min and max vma of any type, for use in selecting a nice gp. */ - for (os =3D abfd->sections; os ; os =3D os->next) - { - bfd_vma lo, hi; - - if ((os->flags & SEC_ALLOC) =3D=3D 0) - continue; - - lo =3D os->vma; - /* When this function is called from elfNN_ia64_final_link - the correct value to use is os->size. When called from - elfNN_ia64_relax_section we are in the middle of section - sizing; some sections will already have os->size set, others - will have os->size zero and os->rawsize the previous size. */ - hi =3D os->vma + (!final && os->rawsize ? os->rawsize : os->size); - if (hi < lo) - hi =3D (bfd_vma) -1; - - if (min_vma > lo) - min_vma =3D lo; - if (max_vma < hi) - max_vma =3D hi; - if (os->flags & SEC_SMALL_DATA) - { - if (min_short_vma > lo) - min_short_vma =3D lo; - if (max_short_vma < hi) - max_short_vma =3D hi; - } - } - - if (ia64_info->min_short_sec) - { - if (min_short_vma - > (ia64_info->min_short_sec->vma - + ia64_info->min_short_offset)) - min_short_vma =3D (ia64_info->min_short_sec->vma - + ia64_info->min_short_offset); - if (max_short_vma - < (ia64_info->max_short_sec->vma - + ia64_info->max_short_offset)) - max_short_vma =3D (ia64_info->max_short_sec->vma - + ia64_info->max_short_offset); - } - - /* See if the user wants to force a value. */ - gp =3D elf_link_hash_lookup (elf_hash_table (info), "__gp", false, - false, false); - - if (gp - && (gp->root.type =3D=3D bfd_link_hash_defined - || gp->root.type =3D=3D bfd_link_hash_defweak)) - { - asection *gp_sec =3D gp->root.u.def.section; - gp_val =3D (gp->root.u.def.value - + gp_sec->output_section->vma - + gp_sec->output_offset); - } - else - { - /* Pick a sensible value. */ - - if (ia64_info->min_short_sec) - { - bfd_vma short_range =3D max_short_vma - min_short_vma; - - /* If min_short_sec is set, pick one in the middle bewteen - min_short_vma and max_short_vma. */ - if (short_range >=3D 0x400000) - goto overflow; - gp_val =3D min_short_vma + short_range / 2; - } - else - { - asection *got_sec =3D ia64_info->root.sgot; - - /* Start with just the address of the .got. */ - if (got_sec) - gp_val =3D got_sec->output_section->vma; - else if (max_short_vma !=3D 0) - gp_val =3D min_short_vma; - else if (max_vma - min_vma < 0x200000) - gp_val =3D min_vma; - else - gp_val =3D max_vma - 0x200000 + 8; - } - - /* If it is possible to address the entire image, but we - don't with the choice above, adjust. */ - if (max_vma - min_vma < 0x400000 - && (max_vma - gp_val >=3D 0x200000 - || gp_val - min_vma > 0x200000)) - gp_val =3D min_vma + 0x200000; - else if (max_short_vma !=3D 0) - { - /* If we don't cover all the short data, adjust. */ - if (max_short_vma - gp_val >=3D 0x200000) - gp_val =3D min_short_vma + 0x200000; - - /* If we're addressing stuff past the end, adjust back. */ - if (gp_val > max_vma) - gp_val =3D max_vma - 0x200000 + 8; - } - } - - /* Validate whether all SHF_IA_64_SHORT sections are within - range of the chosen GP. */ - - if (max_short_vma !=3D 0) - { - if (max_short_vma - min_short_vma >=3D 0x400000) - { - overflow: - _bfd_error_handler - /* xgettext:c-format */ - (_("%pB: short data segment overflowed (%#" PRIx64 " >=3D 0x400000)"), - abfd, (uint64_t) (max_short_vma - min_short_vma)); - return false; - } - else if ((gp_val > min_short_vma - && gp_val - min_short_vma > 0x200000) - || (gp_val < max_short_vma - && max_short_vma - gp_val >=3D 0x200000)) - { - _bfd_error_handler - (_("%pB: __gp does not cover short data segment"), abfd); - return false; - } - } - - _bfd_set_gp_value (abfd, gp_val); - - return true; -} - -static bool -elf64_ia64_final_link (bfd *abfd, struct bfd_link_info *info) -{ - struct elf64_ia64_link_hash_table *ia64_info; - asection *unwind_output_sec; - - ia64_info =3D elf64_ia64_hash_table (info); - if (ia64_info =3D=3D NULL) - return false; - - /* Make sure we've got ourselves a nice fat __gp value. */ - if (!bfd_link_relocatable (info)) - { - bfd_vma gp_val; - struct elf_link_hash_entry *gp; - - /* We assume after gp is set, section size will only decrease. We - need to adjust gp for it. */ - _bfd_set_gp_value (abfd, 0); - if (! elf64_ia64_choose_gp (abfd, info, true)) - return false; - gp_val =3D _bfd_get_gp_value (abfd); - - gp =3D elf_link_hash_lookup (elf_hash_table (info), "__gp", false, - false, false); - if (gp) - { - gp->root.type =3D bfd_link_hash_defined; - gp->root.u.def.value =3D gp_val; - gp->root.u.def.section =3D bfd_abs_section_ptr; - } - } - - /* If we're producing a final executable, we need to sort the contents - of the .IA_64.unwind section. Force this section to be relocated - into memory rather than written immediately to the output file. */ - unwind_output_sec =3D NULL; - if (!bfd_link_relocatable (info)) - { - asection *s =3D bfd_get_section_by_name (abfd, ELF_STRING_ia64_unwin= d); - if (s) - { - unwind_output_sec =3D s->output_section; - unwind_output_sec->contents - =3D bfd_malloc (unwind_output_sec->size); - if (unwind_output_sec->contents =3D=3D NULL) - return false; - } - } - - /* Invoke the regular ELF backend linker to do all the work. */ - if (!bfd_elf_final_link (abfd, info)) - return false; - - if (unwind_output_sec) - { - elf64_ia64_unwind_entry_compare_bfd =3D abfd; - qsort (unwind_output_sec->contents, - (size_t) (unwind_output_sec->size / 24), - 24, - elf64_ia64_unwind_entry_compare); - - if (! bfd_set_section_contents (abfd, unwind_output_sec, - unwind_output_sec->contents, (bfd_vma) 0, - unwind_output_sec->size)) - return false; - } - - return true; -} - -static int -elf64_ia64_relocate_section (bfd *output_bfd, - struct bfd_link_info *info, - bfd *input_bfd, - asection *input_section, - bfd_byte *contents, - Elf_Internal_Rela *relocs, - Elf_Internal_Sym *local_syms, - asection **local_sections) -{ - struct elf64_ia64_link_hash_table *ia64_info; - Elf_Internal_Shdr *symtab_hdr; - Elf_Internal_Rela *rel; - Elf_Internal_Rela *relend; - bool ret_val =3D true; /* for non-fatal errors */ - bfd_vma gp_val; - - symtab_hdr =3D &elf_tdata (input_bfd)->symtab_hdr; - ia64_info =3D elf64_ia64_hash_table (info); - if (ia64_info =3D=3D NULL) - return false; - - /* Infect various flags from the input section to the output section. */ - if (bfd_link_relocatable (info)) - { - bfd_vma flags; - - flags =3D elf_section_data(input_section)->this_hdr.sh_flags; - flags &=3D SHF_IA_64_NORECOV; - - elf_section_data(input_section->output_section) - ->this_hdr.sh_flags |=3D flags; - } - - gp_val =3D _bfd_get_gp_value (output_bfd); - - rel =3D relocs; - relend =3D relocs + input_section->reloc_count; - for (; rel < relend; ++rel) - { - struct elf_link_hash_entry *h; - struct elf64_ia64_dyn_sym_info *dyn_i; - bfd_reloc_status_type r; - reloc_howto_type *howto; - unsigned long r_symndx; - Elf_Internal_Sym *sym; - unsigned int r_type; - bfd_vma value; - asection *sym_sec; - bfd_byte *hit_addr; - bool dynamic_symbol_p; - bool undef_weak_ref; - - r_type =3D ELF64_R_TYPE (rel->r_info); - if (r_type > R_IA64_MAX_RELOC_CODE) - { - /* xgettext:c-format */ - _bfd_error_handler (_("%pB: unsupported relocation type %#x"), - input_bfd, (int) r_type); - bfd_set_error (bfd_error_bad_value); - ret_val =3D false; - continue; - } - - howto =3D ia64_elf_lookup_howto (r_type); - if (howto =3D=3D NULL) - { - ret_val =3D false; - continue; - } - r_symndx =3D ELF64_R_SYM (rel->r_info); - h =3D NULL; - sym =3D NULL; - sym_sec =3D NULL; - undef_weak_ref =3D false; - - if (r_symndx < symtab_hdr->sh_info) - { - /* Reloc against local symbol. */ - asection *msec; - sym =3D local_syms + r_symndx; - sym_sec =3D local_sections[r_symndx]; - msec =3D sym_sec; - value =3D _bfd_elf_rela_local_sym (output_bfd, sym, &msec, rel); - if (!bfd_link_relocatable (info) - && (sym_sec->flags & SEC_MERGE) !=3D 0 - && ELF_ST_TYPE (sym->st_info) =3D=3D STT_SECTION - && sym_sec->sec_info_type =3D=3D SEC_INFO_TYPE_MERGE) - { - struct elf64_ia64_local_hash_entry *loc_h; - - loc_h =3D get_local_sym_hash (ia64_info, input_bfd, rel, false); - if (loc_h && ! loc_h->sec_merge_done) - { - struct elf64_ia64_dyn_sym_info *dynent; - unsigned int count; - - for (count =3D loc_h->count, dynent =3D loc_h->info; - count !=3D 0; - count--, dynent++) - { - msec =3D sym_sec; - dynent->addend =3D - _bfd_merged_section_offset (output_bfd, &msec, - elf_section_data (msec)-> - sec_info, - sym->st_value - + dynent->addend); - dynent->addend -=3D sym->st_value; - dynent->addend +=3D msec->output_section->vma - + msec->output_offset - - sym_sec->output_section->vma - - sym_sec->output_offset; - } - - /* We may have introduced duplicated entries. We need - to remove them properly. */ - count =3D sort_dyn_sym_info (loc_h->info, loc_h->count); - if (count !=3D loc_h->count) - { - loc_h->count =3D count; - loc_h->sorted_count =3D count; - } - - loc_h->sec_merge_done =3D 1; - } - } - } - else - { - bool unresolved_reloc; - bool warned, ignored; - struct elf_link_hash_entry **sym_hashes =3D elf_sym_hashes (input_bfd); - - RELOC_FOR_GLOBAL_SYMBOL (info, input_bfd, input_section, rel, - r_symndx, symtab_hdr, sym_hashes, - h, sym_sec, value, - unresolved_reloc, warned, ignored); - - if (h->root.type =3D=3D bfd_link_hash_undefweak) - undef_weak_ref =3D true; - else if (warned) - continue; - } - - /* For relocs against symbols from removed linkonce sections, - or sections discarded by a linker script, we just want the - section contents zeroed. Avoid any special processing. */ - if (sym_sec !=3D NULL && discarded_section (sym_sec)) - RELOC_AGAINST_DISCARDED_SECTION (info, input_bfd, input_section, - rel, 1, relend, howto, 0, contents); - - if (bfd_link_relocatable (info)) - continue; - - hit_addr =3D contents + rel->r_offset; - value +=3D rel->r_addend; - dynamic_symbol_p =3D elf64_ia64_dynamic_symbol_p (h); - - switch (r_type) - { - case R_IA64_NONE: - case R_IA64_LDXMOV: - continue; - - case R_IA64_IMM14: - case R_IA64_IMM22: - case R_IA64_IMM64: - case R_IA64_DIR32MSB: - case R_IA64_DIR32LSB: - case R_IA64_DIR64MSB: - case R_IA64_DIR64LSB: - /* Install a dynamic relocation for this reloc. */ - if ((dynamic_symbol_p || bfd_link_pic (info)) - && r_symndx !=3D 0 - && (input_section->flags & SEC_ALLOC) !=3D 0) - { - unsigned int dyn_r_type; - bfd_vma addend; - - switch (r_type) - { - case R_IA64_IMM14: - case R_IA64_IMM22: - case R_IA64_IMM64: - /* ??? People shouldn't be doing non-pic code in - shared libraries nor dynamic executables. */ - _bfd_error_handler - /* xgettext:c-format */ - (_("%pB: non-pic code with imm relocation against" - " dynamic symbol `%s'"), - input_bfd, - h ? h->root.root.string - : bfd_elf_sym_name (input_bfd, symtab_hdr, sym, - sym_sec)); - ret_val =3D false; - continue; - - default: - break; - } - - /* If we don't need dynamic symbol lookup, find a - matching RELATIVE relocation. */ - dyn_r_type =3D r_type; - if (dynamic_symbol_p) - { - addend =3D rel->r_addend; - value =3D 0; - } - else - { - addend =3D value; - } - - /* VMS: install a FIX64. */ - switch (dyn_r_type) - { - case R_IA64_DIR32LSB: - dyn_r_type =3D R_IA64_VMS_FIX32; - break; - case R_IA64_DIR64LSB: - dyn_r_type =3D R_IA64_VMS_FIX64; - break; - default: - BFD_ASSERT (false); - break; - } - elf64_ia64_install_fixup - (output_bfd, ia64_info, h, - dyn_r_type, input_section, rel->r_offset, addend); - r =3D bfd_reloc_ok; - break; - } - /* Fall through. */ - - case R_IA64_LTV32MSB: - case R_IA64_LTV32LSB: - case R_IA64_LTV64MSB: - case R_IA64_LTV64LSB: - r =3D ia64_elf_install_value (hit_addr, value, r_type); - break; - - case R_IA64_GPREL22: - case R_IA64_GPREL64I: - case R_IA64_GPREL32MSB: - case R_IA64_GPREL32LSB: - case R_IA64_GPREL64MSB: - case R_IA64_GPREL64LSB: - if (dynamic_symbol_p) - { - _bfd_error_handler - /* xgettext:c-format */ - (_("%pB: @gprel relocation against dynamic symbol %s"), - input_bfd, - h ? h->root.root.string - : bfd_elf_sym_name (input_bfd, symtab_hdr, sym, - sym_sec)); - ret_val =3D false; - continue; - } - value -=3D gp_val; - r =3D ia64_elf_install_value (hit_addr, value, r_type); - break; - - case R_IA64_LTOFF22: - case R_IA64_LTOFF22X: - case R_IA64_LTOFF64I: - dyn_i =3D get_dyn_sym_info (ia64_info, h, input_bfd, rel, false); - value =3D set_got_entry (input_bfd, info, dyn_i, - rel->r_addend, value, R_IA64_DIR64LSB); - value -=3D gp_val; - r =3D ia64_elf_install_value (hit_addr, value, r_type); - break; - - case R_IA64_PLTOFF22: - case R_IA64_PLTOFF64I: - case R_IA64_PLTOFF64MSB: - case R_IA64_PLTOFF64LSB: - dyn_i =3D get_dyn_sym_info (ia64_info, h, input_bfd, rel, false); - value =3D set_pltoff_entry (output_bfd, info, dyn_i, value, false); - value -=3D gp_val; - r =3D ia64_elf_install_value (hit_addr, value, r_type); - break; - - case R_IA64_FPTR64I: - case R_IA64_FPTR32MSB: - case R_IA64_FPTR32LSB: - case R_IA64_FPTR64MSB: - case R_IA64_FPTR64LSB: - dyn_i =3D get_dyn_sym_info (ia64_info, h, input_bfd, rel, false); - if (dyn_i->want_fptr) - { - if (!undef_weak_ref) - value =3D set_fptr_entry (output_bfd, info, dyn_i, value); - } - if (!dyn_i->want_fptr || bfd_link_pie (info)) - { - /* Otherwise, we expect the dynamic linker to create - the entry. */ - - if (dyn_i->want_fptr) - { - if (r_type =3D=3D R_IA64_FPTR64I) - { - /* We can't represent this without a dynamic symbol. - Adjust the relocation to be against an output - section symbol, which are always present in the - dynamic symbol table. */ - /* ??? People shouldn't be doing non-pic code in - shared libraries. Hork. */ - _bfd_error_handler - (_("%pB: linking non-pic code in a position independent executable"), - input_bfd); - ret_val =3D false; - continue; - } - } - else - { - value =3D 0; - } - - /* VMS: FIXFD. */ - elf64_ia64_install_fixup - (output_bfd, ia64_info, h, R_IA64_VMS_FIXFD, - input_section, rel->r_offset, 0); - r =3D bfd_reloc_ok; - break; - } - - r =3D ia64_elf_install_value (hit_addr, value, r_type); - break; - - case R_IA64_LTOFF_FPTR22: - case R_IA64_LTOFF_FPTR64I: - case R_IA64_LTOFF_FPTR32MSB: - case R_IA64_LTOFF_FPTR32LSB: - case R_IA64_LTOFF_FPTR64MSB: - case R_IA64_LTOFF_FPTR64LSB: - dyn_i =3D get_dyn_sym_info (ia64_info, h, input_bfd, rel, false); - if (dyn_i->want_fptr) - { - BFD_ASSERT (h =3D=3D NULL || !h->def_dynamic); - if (!undef_weak_ref) - value =3D set_fptr_entry (output_bfd, info, dyn_i, value); - } - else - value =3D 0; - - value =3D set_got_entry (output_bfd, info, dyn_i, - rel->r_addend, value, R_IA64_FPTR64LSB); - value -=3D gp_val; - r =3D ia64_elf_install_value (hit_addr, value, r_type); - break; - - case R_IA64_PCREL32MSB: - case R_IA64_PCREL32LSB: - case R_IA64_PCREL64MSB: - case R_IA64_PCREL64LSB: - /* Install a dynamic relocation for this reloc. */ - if (dynamic_symbol_p && r_symndx !=3D 0) - { - /* VMS: doesn't exist ??? */ - abort (); - } - goto finish_pcrel; - - case R_IA64_PCREL21B: - case R_IA64_PCREL60B: - /* We should have created a PLT entry for any dynamic symbol. */ - dyn_i =3D NULL; - if (h) - dyn_i =3D get_dyn_sym_info (ia64_info, h, NULL, NULL, false); - - if (dyn_i && dyn_i->want_plt2) - { - /* Should have caught this earlier. */ - BFD_ASSERT (rel->r_addend =3D=3D 0); - - value =3D (ia64_info->root.splt->output_section->vma - + ia64_info->root.splt->output_offset - + dyn_i->plt2_offset); - } - else - { - /* Since there's no PLT entry, Validate that this is - locally defined. */ - BFD_ASSERT (undef_weak_ref || sym_sec->output_section !=3D NULL); - - /* If the symbol is undef_weak, we shouldn't be trying - to call it. There's every chance that we'd wind up - with an out-of-range fixup here. Don't bother setting - any value at all. */ - if (undef_weak_ref) - continue; - } - goto finish_pcrel; - - case R_IA64_PCREL21BI: - case R_IA64_PCREL21F: - case R_IA64_PCREL21M: - case R_IA64_PCREL22: - case R_IA64_PCREL64I: - /* The PCREL21BI reloc is specifically not intended for use with - dynamic relocs. PCREL21F and PCREL21M are used for speculation - fixup code, and thus probably ought not be dynamic. The - PCREL22 and PCREL64I relocs aren't emitted as dynamic relocs. */ - if (dynamic_symbol_p) - { - const char *msg; - - if (r_type =3D=3D R_IA64_PCREL21BI) - /* xgettext:c-format */ - msg =3D _("%pB: @internal branch to dynamic symbol %s"); - else if (r_type =3D=3D R_IA64_PCREL21F || r_type =3D=3D R_IA64_PCRE= L21M) - /* xgettext:c-format */ - msg =3D _("%pB: speculation fixup to dynamic symbol %s"); - else - /* xgettext:c-format */ - msg =3D _("%pB: @pcrel relocation against dynamic symbol %s"); - _bfd_error_handler (msg, input_bfd, - h ? h->root.root.string - : bfd_elf_sym_name (input_bfd, - symtab_hdr, - sym, - sym_sec)); - ret_val =3D false; - continue; - } - goto finish_pcrel; - - finish_pcrel: - /* Make pc-relative. */ - value -=3D (input_section->output_section->vma - + input_section->output_offset - + rel->r_offset) & ~ (bfd_vma) 0x3; - r =3D ia64_elf_install_value (hit_addr, value, r_type); - break; - - case R_IA64_SEGREL32MSB: - case R_IA64_SEGREL32LSB: - case R_IA64_SEGREL64MSB: - case R_IA64_SEGREL64LSB: - { - /* Find the segment that contains the output_section. */ - Elf_Internal_Phdr *p =3D _bfd_elf_find_segment_containing_section - (output_bfd, sym_sec->output_section); - - if (p =3D=3D NULL) - { - r =3D bfd_reloc_notsupported; - } - else - { - /* The VMA of the segment is the vaddr of the associated - program header. */ - if (value > p->p_vaddr) - value -=3D p->p_vaddr; - else - value =3D 0; - r =3D ia64_elf_install_value (hit_addr, value, r_type); - } - break; - } - - case R_IA64_SECREL32MSB: - case R_IA64_SECREL32LSB: - case R_IA64_SECREL64MSB: - case R_IA64_SECREL64LSB: - /* Make output-section relative to section where the symbol - is defined. PR 475 */ - if (sym_sec) - value -=3D sym_sec->output_section->vma; - r =3D ia64_elf_install_value (hit_addr, value, r_type); - break; - - case R_IA64_IPLTMSB: - case R_IA64_IPLTLSB: - /* Install a dynamic relocation for this reloc. */ - if ((dynamic_symbol_p || bfd_link_pic (info)) - && (input_section->flags & SEC_ALLOC) !=3D 0) - { - /* VMS: FIXFD ?? */ - abort (); - } - - if (r_type =3D=3D R_IA64_IPLTMSB) - r_type =3D R_IA64_DIR64MSB; - else - r_type =3D R_IA64_DIR64LSB; - ia64_elf_install_value (hit_addr, value, r_type); - r =3D ia64_elf_install_value (hit_addr + 8, gp_val, r_type); - break; - - case R_IA64_TPREL14: - case R_IA64_TPREL22: - case R_IA64_TPREL64I: - r =3D bfd_reloc_notsupported; - break; - - case R_IA64_DTPREL14: - case R_IA64_DTPREL22: - case R_IA64_DTPREL64I: - case R_IA64_DTPREL32LSB: - case R_IA64_DTPREL32MSB: - case R_IA64_DTPREL64LSB: - case R_IA64_DTPREL64MSB: - r =3D bfd_reloc_notsupported; - break; - - case R_IA64_LTOFF_TPREL22: - case R_IA64_LTOFF_DTPMOD22: - case R_IA64_LTOFF_DTPREL22: - r =3D bfd_reloc_notsupported; - break; - - default: - r =3D bfd_reloc_notsupported; - break; - } - - switch (r) - { - case bfd_reloc_ok: - break; - - case bfd_reloc_undefined: - /* This can happen for global table relative relocs if - __gp is undefined. This is a panic situation so we - don't try to continue. */ - (*info->callbacks->undefined_symbol) - (info, "__gp", input_bfd, input_section, rel->r_offset, 1); - return false; - - case bfd_reloc_notsupported: - { - const char *name; - - if (h) - name =3D h->root.root.string; - else - name =3D bfd_elf_sym_name (input_bfd, symtab_hdr, sym, - sym_sec); - (*info->callbacks->warning) (info, _("unsupported reloc"), - name, input_bfd, - input_section, rel->r_offset); - ret_val =3D false; - } - break; - - case bfd_reloc_dangerous: - case bfd_reloc_outofrange: - case bfd_reloc_overflow: - default: - { - const char *name; - - if (h) - name =3D h->root.root.string; - else - name =3D bfd_elf_sym_name (input_bfd, symtab_hdr, sym, - sym_sec); - - switch (r_type) - { - case R_IA64_TPREL14: - case R_IA64_TPREL22: - case R_IA64_TPREL64I: - case R_IA64_DTPREL14: - case R_IA64_DTPREL22: - case R_IA64_DTPREL64I: - case R_IA64_DTPREL32LSB: - case R_IA64_DTPREL32MSB: - case R_IA64_DTPREL64LSB: - case R_IA64_DTPREL64MSB: - case R_IA64_LTOFF_TPREL22: - case R_IA64_LTOFF_DTPMOD22: - case R_IA64_LTOFF_DTPREL22: - _bfd_error_handler - /* xgettext:c-format */ - (_("%pB: missing TLS section for relocation %s against `%s'" - " at %#" PRIx64 " in section `%pA'."), - input_bfd, howto->name, name, - (uint64_t) rel->r_offset, input_section); - break; - - case R_IA64_PCREL21B: - case R_IA64_PCREL21BI: - case R_IA64_PCREL21M: - case R_IA64_PCREL21F: - if (is_elf_hash_table (info->hash)) - { - /* Relaxtion is always performed for ELF output. - Overflow failures for those relocations mean - that the section is too big to relax. */ - _bfd_error_handler - /* xgettext:c-format */ - (_("%pB: Can't relax br (%s) to `%s' " - "at %#" PRIx64 " in section `%pA' " - "with size %#" PRIx64 " (> 0x1000000)."), - input_bfd, howto->name, name, (uint64_t) rel->r_offset, - input_section, (uint64_t) input_section->size); - break; - } - /* Fall through. */ - default: - (*info->callbacks->reloc_overflow) (info, - &h->root, - name, - howto->name, - (bfd_vma) 0, - input_bfd, - input_section, - rel->r_offset); - break; - } - - ret_val =3D false; - } - break; - } - } - - return ret_val; -} - -static bool -elf64_ia64_finish_dynamic_symbol (bfd *output_bfd, - struct bfd_link_info *info, - struct elf_link_hash_entry *h, - Elf_Internal_Sym *sym) -{ - struct elf64_ia64_link_hash_table *ia64_info; - struct elf64_ia64_dyn_sym_info *dyn_i; - - ia64_info =3D elf64_ia64_hash_table (info); - - dyn_i =3D get_dyn_sym_info (ia64_info, h, NULL, NULL, false); - - /* Fill in the PLT data, if required. */ - if (dyn_i && dyn_i->want_plt) - { - bfd_byte *loc; - asection *plt_sec; - bfd_vma plt_addr, pltoff_addr, gp_val; - - gp_val =3D _bfd_get_gp_value (output_bfd); - - plt_sec =3D ia64_info->root.splt; - plt_addr =3D 0; /* Not used as overriden by FIXUPs. */ - pltoff_addr =3D set_pltoff_entry (output_bfd, info, dyn_i, plt_addr,= true); - - /* Initialize the FULL PLT entry, if needed. */ - if (dyn_i->want_plt2) - { - loc =3D plt_sec->contents + dyn_i->plt2_offset; - - memcpy (loc, plt_full_entry, PLT_FULL_ENTRY_SIZE); - ia64_elf_install_value (loc, pltoff_addr - gp_val, R_IA64_IMM22); - - /* Mark the symbol as undefined, rather than as defined in the - plt section. Leave the value alone. */ - /* ??? We didn't redefine it in adjust_dynamic_symbol in the - first place. But perhaps elflink.c did some for us. */ - if (!h->def_regular) - sym->st_shndx =3D SHN_UNDEF; - } - - /* VMS: FIXFD. */ - elf64_ia64_install_fixup - (output_bfd, ia64_info, h, R_IA64_VMS_FIXFD, ia64_info->pltoff_sec, - pltoff_addr - (ia64_info->pltoff_sec->output_section->vma - + ia64_info->pltoff_sec->output_offset), 0); - } - - /* Mark some specially defined symbols as absolute. */ - if (h =3D=3D ia64_info->root.hdynamic - || h =3D=3D ia64_info->root.hgot - || h =3D=3D ia64_info->root.hplt) - sym->st_shndx =3D SHN_ABS; - - return true; -} - -static bool -elf64_ia64_finish_dynamic_sections (bfd *abfd, - struct bfd_link_info *info) -{ - struct elf64_ia64_link_hash_table *ia64_info; - bfd *dynobj; - - ia64_info =3D elf64_ia64_hash_table (info); - if (ia64_info =3D=3D NULL) - return false; - - dynobj =3D ia64_info->root.dynobj; - - if (elf_hash_table (info)->dynamic_sections_created) - { - Elf64_External_Dyn *dyncon, *dynconend; - asection *sdyn; - asection *unwind_sec; - bfd_vma gp_val; - unsigned int gp_seg; - bfd_vma gp_off; - Elf_Internal_Phdr *phdr; - Elf_Internal_Phdr *base_phdr; - unsigned int unwind_seg =3D 0; - unsigned int code_seg =3D 0; - - sdyn =3D bfd_get_linker_section (dynobj, ".dynamic"); - BFD_ASSERT (sdyn !=3D NULL); - dyncon =3D (Elf64_External_Dyn *) sdyn->contents; - dynconend =3D (Elf64_External_Dyn *) (sdyn->contents + sdyn->size); - - gp_val =3D _bfd_get_gp_value (abfd); - phdr =3D _bfd_elf_find_segment_containing_section - (info->output_bfd, ia64_info->pltoff_sec->output_section); - BFD_ASSERT (phdr !=3D NULL); - base_phdr =3D elf_tdata (info->output_bfd)->phdr; - gp_seg =3D phdr - base_phdr; - gp_off =3D gp_val - phdr->p_vaddr; - - unwind_sec =3D bfd_get_section_by_name (abfd, ELF_STRING_ia64_unwind= ); - if (unwind_sec !=3D NULL) - { - asection *code_sec; - - phdr =3D _bfd_elf_find_segment_containing_section (abfd, unwind_sec); - BFD_ASSERT (phdr !=3D NULL); - unwind_seg =3D phdr - base_phdr; - - code_sec =3D bfd_get_section_by_name (abfd, "$CODE$"); - phdr =3D _bfd_elf_find_segment_containing_section (abfd, code_sec); - BFD_ASSERT (phdr !=3D NULL); - code_seg =3D phdr - base_phdr; - } - - for (; dyncon < dynconend; dyncon++) - { - Elf_Internal_Dyn dyn; - - bfd_elf64_swap_dyn_in (dynobj, dyncon, &dyn); - - switch (dyn.d_tag) - { - case DT_IA_64_VMS_FIXUP_RELA_OFF: - dyn.d_un.d_val +=3D - (ia64_info->fixups_sec->output_section->vma - + ia64_info->fixups_sec->output_offset) - - (sdyn->output_section->vma + sdyn->output_offset); - break; - - case DT_IA_64_VMS_PLTGOT_OFFSET: - dyn.d_un.d_val =3D gp_off; - break; - - case DT_IA_64_VMS_PLTGOT_SEG: - dyn.d_un.d_val =3D gp_seg; - break; - - case DT_IA_64_VMS_UNWINDSZ: - if (unwind_sec =3D=3D NULL) - { - dyn.d_tag =3D DT_NULL; - dyn.d_un.d_val =3D 0xdead; - } - else - dyn.d_un.d_val =3D unwind_sec->size; - break; - - case DT_IA_64_VMS_UNWIND_CODSEG: - dyn.d_un.d_val =3D code_seg; - break; - - case DT_IA_64_VMS_UNWIND_INFOSEG: - case DT_IA_64_VMS_UNWIND_SEG: - dyn.d_un.d_val =3D unwind_seg; - break; - - case DT_IA_64_VMS_UNWIND_OFFSET: - break; - - default: - /* No need to rewrite the entry. */ - continue; - } - - bfd_elf64_swap_dyn_out (abfd, &dyn, dyncon); - } - } - - /* Handle transfer addresses. */ - { - asection *tfr_sec =3D ia64_info->transfer_sec; - struct elf64_vms_transfer *tfr; - struct elf_link_hash_entry *tfr3; - - tfr =3D (struct elf64_vms_transfer *)tfr_sec->contents; - bfd_putl32 (6 * 8, tfr->size); - bfd_putl64 (tfr_sec->output_section->vma - + tfr_sec->output_offset - + 6 * 8, tfr->tfradr3); - - tfr3 =3D elf_link_hash_lookup (elf_hash_table (info), "ELF$TFRADR", fa= lse, - false, false); - - if (tfr3 - && (tfr3->root.type =3D=3D bfd_link_hash_defined - || tfr3->root.type =3D=3D bfd_link_hash_defweak)) - { - asection *tfr3_sec =3D tfr3->root.u.def.section; - bfd_vma tfr3_val; - - tfr3_val =3D (tfr3->root.u.def.value - + tfr3_sec->output_section->vma - + tfr3_sec->output_offset); - - bfd_putl64 (tfr3_val, tfr->tfr3_func); - bfd_putl64 (_bfd_get_gp_value (info->output_bfd), tfr->tfr3_gp); - } - - /* FIXME: set linker flags, - handle lib$initialize. */ - } - - return true; -} - -/* ELF file flag handling: */ - -/* Function to keep IA-64 specific file flags. */ -static bool -elf64_ia64_set_private_flags (bfd *abfd, flagword flags) -{ - BFD_ASSERT (!elf_flags_init (abfd) - || elf_elfheader (abfd)->e_flags =3D=3D flags); - - elf_elfheader (abfd)->e_flags =3D flags; - elf_flags_init (abfd) =3D true; - return true; -} - -/* Merge backend specific data from an object file to the output - object file when linking. */ -static bool -elf64_ia64_merge_private_bfd_data (bfd *ibfd, struct bfd_link_info *info) -{ - bfd *obfd =3D info->output_bfd; - flagword out_flags; - flagword in_flags; - bool ok =3D true; - - /* FIXME: What should be checked when linking shared libraries? */ - if ((ibfd->flags & DYNAMIC) !=3D 0) - return true; - - /* Don't even pretend to support mixed-format linking. */ - if (bfd_get_flavour (ibfd) !=3D bfd_target_elf_flavour - || bfd_get_flavour (obfd) !=3D bfd_target_elf_flavour) - return false; - - in_flags =3D elf_elfheader (ibfd)->e_flags; - out_flags =3D elf_elfheader (obfd)->e_flags; - - if (! elf_flags_init (obfd)) - { - elf_flags_init (obfd) =3D true; - elf_elfheader (obfd)->e_flags =3D in_flags; - - if (bfd_get_arch (obfd) =3D=3D bfd_get_arch (ibfd) - && bfd_get_arch_info (obfd)->the_default) - { - return bfd_set_arch_mach (obfd, bfd_get_arch (ibfd), - bfd_get_mach (ibfd)); - } - - return true; - } - - /* Check flag compatibility. */ - if (in_flags =3D=3D out_flags) - return true; - - /* Output has EF_IA_64_REDUCEDFP set only if all inputs have it set. */ - if (!(in_flags & EF_IA_64_REDUCEDFP) && (out_flags & EF_IA_64_REDUCEDFP)) - elf_elfheader (obfd)->e_flags &=3D ~EF_IA_64_REDUCEDFP; - - if ((in_flags & EF_IA_64_TRAPNIL) !=3D (out_flags & EF_IA_64_TRAPNIL)) - { - _bfd_error_handler - (_("%pB: linking trap-on-NULL-dereference with non-trapping files"), - ibfd); - - bfd_set_error (bfd_error_bad_value); - ok =3D false; - } - if ((in_flags & EF_IA_64_BE) !=3D (out_flags & EF_IA_64_BE)) - { - _bfd_error_handler - (_("%pB: linking big-endian files with little-endian files"), - ibfd); - - bfd_set_error (bfd_error_bad_value); - ok =3D false; - } - if ((in_flags & EF_IA_64_ABI64) !=3D (out_flags & EF_IA_64_ABI64)) - { - _bfd_error_handler - (_("%pB: linking 64-bit files with 32-bit files"), - ibfd); - - bfd_set_error (bfd_error_bad_value); - ok =3D false; - } - if ((in_flags & EF_IA_64_CONS_GP) !=3D (out_flags & EF_IA_64_CONS_GP)) - { - _bfd_error_handler - (_("%pB: linking constant-gp files with non-constant-gp files"), - ibfd); - - bfd_set_error (bfd_error_bad_value); - ok =3D false; - } - if ((in_flags & EF_IA_64_NOFUNCDESC_CONS_GP) - !=3D (out_flags & EF_IA_64_NOFUNCDESC_CONS_GP)) - { - _bfd_error_handler - (_("%pB: linking auto-pic files with non-auto-pic files"), - ibfd); - - bfd_set_error (bfd_error_bad_value); - ok =3D false; - } - - return ok; -} - -static bool -elf64_ia64_print_private_bfd_data (bfd *abfd, void * ptr) -{ - FILE *file =3D (FILE *) ptr; - flagword flags =3D elf_elfheader (abfd)->e_flags; - - BFD_ASSERT (abfd !=3D NULL && ptr !=3D NULL); - - fprintf (file, "private flags =3D %s%s%s%s%s%s%s%s\n", - (flags & EF_IA_64_TRAPNIL) ? "TRAPNIL, " : "", - (flags & EF_IA_64_EXT) ? "EXT, " : "", - (flags & EF_IA_64_BE) ? "BE, " : "LE, ", - (flags & EF_IA_64_REDUCEDFP) ? "REDUCEDFP, " : "", - (flags & EF_IA_64_CONS_GP) ? "CONS_GP, " : "", - (flags & EF_IA_64_NOFUNCDESC_CONS_GP) ? "NOFUNCDESC_CONS_GP, " : "", - (flags & EF_IA_64_ABSOLUTE) ? "ABSOLUTE, " : "", - (flags & EF_IA_64_ABI64) ? "ABI64" : "ABI32"); - - _bfd_elf_print_private_bfd_data (abfd, ptr); - return true; -} - -static enum elf_reloc_type_class -elf64_ia64_reloc_type_class (const struct bfd_link_info *info ATTRIBUTE_UN= USED, - const asection *rel_sec ATTRIBUTE_UNUSED, - const Elf_Internal_Rela *rela) -{ - switch ((int) ELF64_R_TYPE (rela->r_info)) - { - case R_IA64_REL32MSB: - case R_IA64_REL32LSB: - case R_IA64_REL64MSB: - case R_IA64_REL64LSB: - return reloc_class_relative; - case R_IA64_IPLTMSB: - case R_IA64_IPLTLSB: - return reloc_class_plt; - case R_IA64_COPY: - return reloc_class_copy; - default: - return reloc_class_normal; - } -} - -static const struct bfd_elf_special_section elf64_ia64_special_sections[] = =3D -{ - { STRING_COMMA_LEN (".sbss"), -1, SHT_NOBITS, SHF_ALLOC + SHF_WRITE += SHF_IA_64_SHORT }, - { STRING_COMMA_LEN (".sdata"), -1, SHT_PROGBITS, SHF_ALLOC + SHF_WRITE += SHF_IA_64_SHORT }, - { NULL, 0, 0, 0, 0 } -}; - -static bool -elf64_ia64_object_p (bfd *abfd) -{ - asection *sec; - asection *group, *unwi, *unw; - flagword flags; - const char *name; - char *unwi_name, *unw_name; - size_t amt; - - if (abfd->flags & DYNAMIC) - return true; - - /* Flags for fake group section. */ - flags =3D (SEC_LINKER_CREATED | SEC_GROUP | SEC_LINK_ONCE - | SEC_EXCLUDE); - - /* We add a fake section group for each .gnu.linkonce.t.* section, - which isn't in a section group, and its unwind sections. */ - for (sec =3D abfd->sections; sec !=3D NULL; sec =3D sec->next) - { - if (elf_sec_group (sec) =3D=3D NULL - && ((sec->flags & (SEC_LINK_ONCE | SEC_CODE | SEC_GROUP)) - =3D=3D (SEC_LINK_ONCE | SEC_CODE)) - && startswith (sec->name, ".gnu.linkonce.t.")) - { - name =3D sec->name + 16; - - amt =3D strlen (name) + sizeof (".gnu.linkonce.ia64unwi."); - unwi_name =3D bfd_alloc (abfd, amt); - if (!unwi_name) - return false; - - strcpy (stpcpy (unwi_name, ".gnu.linkonce.ia64unwi."), name); - unwi =3D bfd_get_section_by_name (abfd, unwi_name); - - amt =3D strlen (name) + sizeof (".gnu.linkonce.ia64unw."); - unw_name =3D bfd_alloc (abfd, amt); - if (!unw_name) - return false; - - strcpy (stpcpy (unw_name, ".gnu.linkonce.ia64unw."), name); - unw =3D bfd_get_section_by_name (abfd, unw_name); - - /* We need to create a fake group section for it and its - unwind sections. */ - group =3D bfd_make_section_anyway_with_flags (abfd, name, - flags); - if (group =3D=3D NULL) - return false; - - /* Move the fake group section to the beginning. */ - bfd_section_list_remove (abfd, group); - bfd_section_list_prepend (abfd, group); - - elf_next_in_group (group) =3D sec; - - elf_group_name (sec) =3D name; - elf_next_in_group (sec) =3D sec; - elf_sec_group (sec) =3D group; - - if (unwi) - { - elf_group_name (unwi) =3D name; - elf_next_in_group (unwi) =3D sec; - elf_next_in_group (sec) =3D unwi; - elf_sec_group (unwi) =3D group; - } - - if (unw) - { - elf_group_name (unw) =3D name; - if (unwi) - { - elf_next_in_group (unw) =3D elf_next_in_group (unwi); - elf_next_in_group (unwi) =3D unw; - } - else - { - elf_next_in_group (unw) =3D sec; - elf_next_in_group (sec) =3D unw; - } - elf_sec_group (unw) =3D group; - } - - /* Fake SHT_GROUP section header. */ - elf_section_data (group)->this_hdr.bfd_section =3D group; - elf_section_data (group)->this_hdr.sh_type =3D SHT_GROUP; - } - } - return true; -} - -/* Handle an IA-64 specific section when reading an object file. This - is called when bfd_section_from_shdr finds a section with an unknown - type. */ - -static bool -elf64_vms_section_from_shdr (bfd *abfd, - Elf_Internal_Shdr *hdr, - const char *name, - int shindex) -{ - flagword secflags =3D 0; - - switch (hdr->sh_type) - { - case SHT_IA_64_VMS_TRACE: - case SHT_IA_64_VMS_DEBUG: - case SHT_IA_64_VMS_DEBUG_STR: - secflags =3D SEC_DEBUGGING; - break; - - case SHT_IA_64_UNWIND: - case SHT_IA_64_HP_OPT_ANOT: - break; - - case SHT_IA_64_EXT: - if (strcmp (name, ELF_STRING_ia64_archext) !=3D 0) - return false; - break; - - default: - return false; - } - - if (! _bfd_elf_make_section_from_shdr (abfd, hdr, name, shindex)) - return false; - - if (secflags !=3D 0) - { - asection *newsect =3D hdr->bfd_section; - - if (!bfd_set_section_flags (newsect, - bfd_section_flags (newsect) | secflags)) - return false; - } - - return true; -} - -static bool -elf64_vms_object_p (bfd *abfd) -{ - Elf_Internal_Ehdr *i_ehdrp =3D elf_elfheader (abfd); - Elf_Internal_Phdr *i_phdr =3D elf_tdata (abfd)->phdr; - unsigned int i; - unsigned int num_text =3D 0; - unsigned int num_data =3D 0; - unsigned int num_rodata =3D 0; - char name[16]; - - if (!elf64_ia64_object_p (abfd)) - return false; - - /* Many VMS compilers do not generate sections for the corresponding - segment. This is boring as binutils tools won't be able to disassemb= le - the code. So we simply create all the missing sections. */ - for (i =3D 0; i < i_ehdrp->e_phnum; i++, i_phdr++) - { - /* Is there a section for this segment? */ - bfd_vma base_vma =3D i_phdr->p_vaddr; - bfd_vma limit_vma =3D base_vma + i_phdr->p_filesz; - - if (i_phdr->p_type !=3D PT_LOAD) - continue; - - /* We need to cover from base_vms to limit_vma. */ - again: - while (base_vma < limit_vma) - { - bfd_vma next_vma =3D limit_vma; - asection *nsec; - asection *sec; - flagword flags; - char *nname =3D NULL; - - /* Find a section covering [base_vma;limit_vma) */ - for (sec =3D abfd->sections; sec !=3D NULL; sec =3D sec->next) - { - /* Skip uninteresting sections (either not in memory or - below base_vma. */ - if ((sec->flags & (SEC_ALLOC | SEC_LOAD)) =3D=3D 0 - || sec->vma + sec->size <=3D base_vma) - continue; - if (sec->vma <=3D base_vma) - { - /* This section covers (maybe partially) the beginning - of the range. */ - base_vma =3D sec->vma + sec->size; - goto again; - } - if (sec->vma < next_vma) - { - /* This section partially covers the end of the range. - Used to compute the size of the hole. */ - next_vma =3D sec->vma; - } - } - - /* No section covering [base_vma; next_vma). Create a fake one. */ - flags =3D SEC_ALLOC | SEC_LOAD | SEC_HAS_CONTENTS; - if (i_phdr->p_flags & PF_X) - { - flags |=3D SEC_CODE; - if (num_text++ =3D=3D 0) - nname =3D ".text"; - else - sprintf (name, ".text$%u", num_text); - } - else if ((i_phdr->p_flags & (PF_R | PF_W)) =3D=3D PF_R) - { - flags |=3D SEC_READONLY; - sprintf (name, ".rodata$%u", num_rodata++); - } - else - { - flags |=3D SEC_DATA; - sprintf (name, ".data$%u", num_data++); - } - - /* Allocate name. */ - if (nname =3D=3D NULL) - { - size_t name_len =3D strlen (name) + 1; - nname =3D bfd_alloc (abfd, name_len); - if (nname =3D=3D NULL) - return false; - memcpy (nname, name, name_len); - } - - /* Create and fill new section. */ - nsec =3D bfd_make_section_anyway_with_flags (abfd, nname, flags); - if (nsec =3D=3D NULL) - return false; - nsec->vma =3D base_vma; - nsec->size =3D next_vma - base_vma; - nsec->filepos =3D i_phdr->p_offset + (base_vma - i_phdr->p_vaddr); - - base_vma =3D next_vma; - } - } - return true; -} - -static bool -elf64_vms_init_file_header (bfd *abfd, struct bfd_link_info *info) -{ - Elf_Internal_Ehdr *i_ehdrp; - - if (!_bfd_elf_init_file_header (abfd, info)) - return false; - - i_ehdrp =3D elf_elfheader (abfd); - i_ehdrp->e_ident[EI_OSABI] =3D ELFOSABI_OPENVMS; - i_ehdrp->e_ident[EI_ABIVERSION] =3D 2; - return true; -} - -static bool -elf64_vms_section_processing (bfd *abfd ATTRIBUTE_UNUSED, - Elf_Internal_Shdr *hdr) -{ - if (hdr->bfd_section !=3D NULL) - { - const char *name =3D bfd_section_name (hdr->bfd_section); - - if (strcmp (name, ".text") =3D=3D 0) - hdr->sh_flags |=3D SHF_IA_64_VMS_SHARED; - else if ((strcmp (name, ".debug") =3D=3D 0) - || (strcmp (name, ".debug_abbrev") =3D=3D 0) - || (strcmp (name, ".debug_aranges") =3D=3D 0) - || (strcmp (name, ".debug_frame") =3D=3D 0) - || (strcmp (name, ".debug_info") =3D=3D 0) - || (strcmp (name, ".debug_loc") =3D=3D 0) - || (strcmp (name, ".debug_macinfo") =3D=3D 0) - || (strcmp (name, ".debug_pubnames") =3D=3D 0) - || (strcmp (name, ".debug_pubtypes") =3D=3D 0)) - hdr->sh_type =3D SHT_IA_64_VMS_DEBUG; - else if ((strcmp (name, ".debug_line") =3D=3D 0) - || (strcmp (name, ".debug_ranges") =3D=3D 0) - || (strcmp (name, ".trace_info") =3D=3D 0) - || (strcmp (name, ".trace_abbrev") =3D=3D 0) - || (strcmp (name, ".trace_aranges") =3D=3D 0)) - hdr->sh_type =3D SHT_IA_64_VMS_TRACE; - else if (strcmp (name, ".debug_str") =3D=3D 0) - hdr->sh_type =3D SHT_IA_64_VMS_DEBUG_STR; - } - - return true; -} - -/* The final processing done just before writing out a VMS IA-64 ELF - object file. */ - -static bool -elf64_vms_final_write_processing (bfd *abfd) -{ - Elf_Internal_Shdr *hdr; - asection *s; - int unwind_info_sect_idx =3D 0; - - for (s =3D abfd->sections; s; s =3D s->next) - { - hdr =3D &elf_section_data (s)->this_hdr; - - if (strcmp (bfd_section_name (hdr->bfd_section), - ".IA_64.unwind_info") =3D=3D 0) - unwind_info_sect_idx =3D elf_section_data (s)->this_idx; - - switch (hdr->sh_type) - { - case SHT_IA_64_UNWIND: - /* VMS requires sh_info to point to the unwind info section. */ - hdr->sh_info =3D unwind_info_sect_idx; - break; - } - } - - if (! elf_flags_init (abfd)) - { - unsigned long flags =3D 0; - - if (abfd->xvec->byteorder =3D=3D BFD_ENDIAN_BIG) - flags |=3D EF_IA_64_BE; - if (bfd_get_mach (abfd) =3D=3D bfd_mach_ia64_elf64) - flags |=3D EF_IA_64_ABI64; - - elf_elfheader (abfd)->e_flags =3D flags; - elf_flags_init (abfd) =3D true; - } - return _bfd_elf_final_write_processing (abfd); -} - -static bool -elf64_vms_write_shdrs_and_ehdr (bfd *abfd) -{ - unsigned char needed_count[8]; - - if (!bfd_elf64_write_shdrs_and_ehdr (abfd)) - return false; - - bfd_putl64 (elf_ia64_vms_tdata (abfd)->needed_count, needed_count); - - if (bfd_seek (abfd, sizeof (Elf64_External_Ehdr), SEEK_SET) !=3D 0 - || bfd_write (needed_count, 8, abfd) !=3D 8) - return false; - - return true; -} - -static bool -elf64_vms_close_and_cleanup (bfd *abfd) -{ - bool ret =3D true; - if (bfd_get_format (abfd) =3D=3D bfd_object - && bfd_write_p (abfd)) - { - long isize; - - /* Pad to 8 byte boundary for IPF/VMS. */ - isize =3D bfd_get_size (abfd); - if ((isize & 7) !=3D 0) - { - unsigned int ishort =3D 8 - (isize & 7); - uint64_t pad =3D 0; - - if (bfd_seek (abfd, isize, SEEK_SET) !=3D 0 - || bfd_write (&pad, ishort, abfd) !=3D ishort) - ret =3D false; - } - } - - return _bfd_generic_close_and_cleanup (abfd) && ret; -} - -/* Add symbols from an ELF object file to the linker hash table. */ - -static bool -elf64_vms_link_add_object_symbols (bfd *abfd, struct bfd_link_info *info) -{ - Elf_Internal_Shdr *hdr; - bfd_size_type symcount; - bfd_size_type extsymcount; - bfd_size_type extsymoff; - struct elf_link_hash_entry **sym_hash; - bool dynamic; - Elf_Internal_Sym *isymbuf =3D NULL; - Elf_Internal_Sym *isym; - Elf_Internal_Sym *isymend; - const struct elf_backend_data *bed; - struct elf_link_hash_table *htab; - bfd_size_type amt; - - htab =3D elf_hash_table (info); - bed =3D get_elf_backend_data (abfd); - - if ((abfd->flags & DYNAMIC) =3D=3D 0) - dynamic =3D false; - else - { - dynamic =3D true; - - /* You can't use -r against a dynamic object. Also, there's no - hope of using a dynamic object which does not exactly match - the format of the output file. */ - if (bfd_link_relocatable (info) - || !is_elf_hash_table (&htab->root) - || info->output_bfd->xvec !=3D abfd->xvec) - { - if (bfd_link_relocatable (info)) - bfd_set_error (bfd_error_invalid_operation); - else - bfd_set_error (bfd_error_wrong_format); - goto error_return; - } - } - - if (! dynamic) - { - /* If we are creating a shared library, create all the dynamic - sections immediately. We need to attach them to something, - so we attach them to this BFD, provided it is the right - format. FIXME: If there are no input BFD's of the same - format as the output, we can't make a shared library. */ - if (bfd_link_pic (info) - && is_elf_hash_table (&htab->root) - && info->output_bfd->xvec =3D=3D abfd->xvec - && !htab->dynamic_sections_created) - { - if (! elf64_ia64_create_dynamic_sections (abfd, info)) - goto error_return; - } - } - else if (!is_elf_hash_table (&htab->root)) - goto error_return; - else - { - asection *s; - bfd_byte *dynbuf; - bfd_byte *extdyn; - - /* ld --just-symbols and dynamic objects don't mix very well. - ld shouldn't allow it. */ - if ((s =3D abfd->sections) !=3D NULL - && s->sec_info_type =3D=3D SEC_INFO_TYPE_JUST_SYMS) - abort (); - - /* Be sure there are dynamic sections. */ - if (! elf64_ia64_create_dynamic_sections (htab->dynobj, info)) - goto error_return; - - s =3D bfd_get_section_by_name (abfd, ".dynamic"); - if (s =3D=3D NULL) - { - /* VMS libraries do not have dynamic sections. Create one from - the segment. */ - Elf_Internal_Phdr *phdr; - unsigned int i, phnum; - - phdr =3D elf_tdata (abfd)->phdr; - if (phdr =3D=3D NULL) - goto error_return; - phnum =3D elf_elfheader (abfd)->e_phnum; - for (i =3D 0; i < phnum; phdr++) - if (phdr->p_type =3D=3D PT_DYNAMIC) - { - s =3D bfd_make_section (abfd, ".dynamic"); - if (s =3D=3D NULL) - goto error_return; - s->vma =3D phdr->p_vaddr; - s->lma =3D phdr->p_paddr; - s->size =3D phdr->p_filesz; - s->filepos =3D phdr->p_offset; - s->flags |=3D SEC_HAS_CONTENTS; - s->alignment_power =3D bfd_log2 (phdr->p_align); - break; - } - if (s =3D=3D NULL) - goto error_return; - } - - /* Extract IDENT. */ - if (!bfd_malloc_and_get_section (abfd, s, &dynbuf)) - { - error_free_dyn: - free (dynbuf); - goto error_return; - } - - for (extdyn =3D dynbuf; - (size_t) (dynbuf + s->size - extdyn) >=3D bed->s->sizeof_dyn; - extdyn +=3D bed->s->sizeof_dyn) - { - Elf_Internal_Dyn dyn; - - bed->s->swap_dyn_in (abfd, extdyn, &dyn); - if (dyn.d_tag =3D=3D DT_IA_64_VMS_IDENT) - { - uint64_t tagv =3D dyn.d_un.d_val; - elf_ia64_vms_ident (abfd) =3D tagv; - break; - } - } - if (extdyn >=3D dynbuf + s->size) - { - /* Ident not found. */ - goto error_free_dyn; - } - free (dynbuf); - - /* We do not want to include any of the sections in a dynamic - object in the output file. We hack by simply clobbering the - list of sections in the BFD. This could be handled more - cleanly by, say, a new section flag; the existing - SEC_NEVER_LOAD flag is not the one we want, because that one - still implies that the section takes up space in the output - file. */ - bfd_section_list_clear (abfd); - - /* FIXME: should we detect if this library is already included ? - This should be harmless and shouldn't happen in practice. */ - } - - hdr =3D &elf_tdata (abfd)->symtab_hdr; - symcount =3D hdr->sh_size / bed->s->sizeof_sym; - - /* The sh_info field of the symtab header tells us where the - external symbols start. We don't care about the local symbols at - this point. */ - extsymcount =3D symcount - hdr->sh_info; - extsymoff =3D hdr->sh_info; - - sym_hash =3D NULL; - if (extsymcount !=3D 0) - { - isymbuf =3D bfd_elf_get_elf_syms (abfd, hdr, extsymcount, extsymoff, - NULL, NULL, NULL); - if (isymbuf =3D=3D NULL) - goto error_return; - - /* We store a pointer to the hash table entry for each external - symbol. */ - amt =3D extsymcount * sizeof (struct elf_link_hash_entry *); - sym_hash =3D (struct elf_link_hash_entry **) bfd_alloc (abfd, amt); - if (sym_hash =3D=3D NULL) - goto error_free_sym; - elf_sym_hashes (abfd) =3D sym_hash; - } - - for (isym =3D isymbuf, isymend =3D isymbuf + extsymcount; - isym < isymend; - isym++, sym_hash++) - { - int bind; - bfd_vma value; - asection *sec, *new_sec; - flagword flags; - const char *name; - struct elf_link_hash_entry *h; - bool definition; - bool size_change_ok; - bool type_change_ok; - bool common; - unsigned int old_alignment; - bfd *old_bfd; - - flags =3D BSF_NO_FLAGS; - sec =3D NULL; - value =3D isym->st_value; - *sym_hash =3D NULL; - common =3D bed->common_definition (isym); - - bind =3D ELF_ST_BIND (isym->st_info); - switch (bind) - { - case STB_LOCAL: - /* This should be impossible, since ELF requires that all - global symbols follow all local symbols, and that sh_info - point to the first global symbol. Unfortunately, Irix 5 - screws this up. */ - continue; - - case STB_GLOBAL: - if (isym->st_shndx !=3D SHN_UNDEF && !common) - flags =3D BSF_GLOBAL; - break; - - case STB_WEAK: - flags =3D BSF_WEAK; - break; - - case STB_GNU_UNIQUE: - flags =3D BSF_GNU_UNIQUE; - break; - - default: - /* Leave it up to the processor backend. */ - break; - } - - if (isym->st_shndx =3D=3D SHN_UNDEF) - sec =3D bfd_und_section_ptr; - else if (isym->st_shndx =3D=3D SHN_ABS) - sec =3D bfd_abs_section_ptr; - else if (isym->st_shndx =3D=3D SHN_COMMON) - { - sec =3D bfd_com_section_ptr; - /* What ELF calls the size we call the value. What ELF - calls the value we call the alignment. */ - value =3D isym->st_size; - } - else - { - sec =3D bfd_section_from_elf_index (abfd, isym->st_shndx); - if (sec =3D=3D NULL) - sec =3D bfd_abs_section_ptr; - else if (sec->kept_section) - { - /* Symbols from discarded section are undefined. We keep - its visibility. */ - sec =3D bfd_und_section_ptr; - isym->st_shndx =3D SHN_UNDEF; - } - else if ((abfd->flags & (EXEC_P | DYNAMIC)) !=3D 0) - value -=3D sec->vma; - } - - name =3D bfd_elf_string_from_elf_section (abfd, hdr->sh_link, - isym->st_name); - if (name =3D=3D NULL) - goto error_free_vers; - - if (bed->elf_add_symbol_hook) - { - if (! (*bed->elf_add_symbol_hook) (abfd, info, isym, &name, &flags, - &sec, &value)) - goto error_free_vers; - - /* The hook function sets the name to NULL if this symbol - should be skipped for some reason. */ - if (name =3D=3D NULL) - continue; - } - - /* Sanity check that all possibilities were handled. */ - if (sec =3D=3D NULL) - { - bfd_set_error (bfd_error_bad_value); - goto error_free_vers; - } - - if (bfd_is_und_section (sec) - || bfd_is_com_section (sec)) - definition =3D false; - else - definition =3D true; - - size_change_ok =3D false; - type_change_ok =3D bed->type_change_ok; - old_alignment =3D 0; - old_bfd =3D NULL; - new_sec =3D sec; - - if (! bfd_is_und_section (sec)) - h =3D elf_link_hash_lookup (htab, name, true, false, false); - else - h =3D ((struct elf_link_hash_entry *) bfd_wrapped_link_hash_lookup - (abfd, info, name, true, false, false)); - if (h =3D=3D NULL) - goto error_free_sym; - - *sym_hash =3D h; - - if (is_elf_hash_table (&htab->root)) - { - while (h->root.type =3D=3D bfd_link_hash_indirect - || h->root.type =3D=3D bfd_link_hash_warning) - h =3D (struct elf_link_hash_entry *) h->root.u.i.link; - - /* Remember the old alignment if this is a common symbol, so - that we don't reduce the alignment later on. We can't - check later, because _bfd_generic_link_add_one_symbol - will set a default for the alignment which we want to - override. We also remember the old bfd where the existing - definition comes from. */ - switch (h->root.type) - { - default: - break; - - case bfd_link_hash_defined: - if (abfd->selective_search) - continue; - /* Fall-through. */ - case bfd_link_hash_defweak: - old_bfd =3D h->root.u.def.section->owner; - break; - - case bfd_link_hash_common: - old_bfd =3D h->root.u.c.p->section->owner; - old_alignment =3D h->root.u.c.p->alignment_power; - break; - } - } - - if (! (_bfd_generic_link_add_one_symbol - (info, abfd, name, flags, sec, value, NULL, false, bed->collect, - (struct bfd_link_hash_entry **) sym_hash))) - goto error_free_vers; - - h =3D *sym_hash; - while (h->root.type =3D=3D bfd_link_hash_indirect - || h->root.type =3D=3D bfd_link_hash_warning) - h =3D (struct elf_link_hash_entry *) h->root.u.i.link; - - *sym_hash =3D h; - if (definition) - h->unique_global =3D (flags & BSF_GNU_UNIQUE) !=3D 0; - - /* Set the alignment of a common symbol. */ - if ((common || bfd_is_com_section (sec)) - && h->root.type =3D=3D bfd_link_hash_common) - { - unsigned int align; - - if (common) - align =3D bfd_log2 (isym->st_value); - else - { - /* The new symbol is a common symbol in a shared object. - We need to get the alignment from the section. */ - align =3D new_sec->alignment_power; - } - if (align > old_alignment - /* Permit an alignment power of zero if an alignment of one - is specified and no other alignments have been specified. */ - || (isym->st_value =3D=3D 1 && old_alignment =3D=3D 0)) - h->root.u.c.p->alignment_power =3D align; - else - h->root.u.c.p->alignment_power =3D old_alignment; - } - - if (is_elf_hash_table (&htab->root)) - { - /* Check the alignment when a common symbol is involved. This - can change when a common symbol is overridden by a normal - definition or a common symbol is ignored due to the old - normal definition. We need to make sure the maximum - alignment is maintained. */ - if ((old_alignment || common) - && h->root.type !=3D bfd_link_hash_common) - { - unsigned int common_align; - unsigned int normal_align; - unsigned int symbol_align; - bfd *normal_bfd; - bfd *common_bfd; - - symbol_align =3D ffs (h->root.u.def.value) - 1; - if (h->root.u.def.section->owner !=3D NULL - && (h->root.u.def.section->owner->flags & DYNAMIC) =3D=3D 0) - { - normal_align =3D h->root.u.def.section->alignment_power; - if (normal_align > symbol_align) - normal_align =3D symbol_align; - } - else - normal_align =3D symbol_align; - - if (old_alignment) - { - common_align =3D old_alignment; - common_bfd =3D old_bfd; - normal_bfd =3D abfd; - } - else - { - common_align =3D bfd_log2 (isym->st_value); - common_bfd =3D abfd; - normal_bfd =3D old_bfd; - } - - if (normal_align < common_align) - { - /* PR binutils/2735 */ - if (normal_bfd =3D=3D NULL) - _bfd_error_handler - /* xgettext:c-format */ - (_("warning: alignment %u of common symbol `%s' in %pB" - " is greater than the alignment (%u) of its section %pA"), - 1 << common_align, name, common_bfd, - 1 << normal_align, h->root.u.def.section); - else - _bfd_error_handler - /* xgettext:c-format */ - (_("warning: alignment %u of symbol `%s' in %pB" - " is smaller than %u in %pB"), - 1 << normal_align, name, normal_bfd, - 1 << common_align, common_bfd); - } - } - - /* Remember the symbol size if it isn't undefined. */ - if ((isym->st_size !=3D 0 && isym->st_shndx !=3D SHN_UNDEF) - && (definition || h->size =3D=3D 0)) - { - if (h->size !=3D 0 - && h->size !=3D isym->st_size - && ! size_change_ok) - _bfd_error_handler - /* xgettext:c-format */ - (_("warning: size of symbol `%s' changed" - " from %" PRIu64 " in %pB to %" PRIu64 " in %pB"), - name, (uint64_t) h->size, old_bfd, - (uint64_t) isym->st_size, abfd); - - h->size =3D isym->st_size; - } - - /* If this is a common symbol, then we always want H->SIZE - to be the size of the common symbol. The code just above - won't fix the size if a common symbol becomes larger. We - don't warn about a size change here, because that is - covered by --warn-common. Allow changed between different - function types. */ - if (h->root.type =3D=3D bfd_link_hash_common) - h->size =3D h->root.u.c.size; - - if (ELF_ST_TYPE (isym->st_info) !=3D STT_NOTYPE - && (definition || h->type =3D=3D STT_NOTYPE)) - { - unsigned int type =3D ELF_ST_TYPE (isym->st_info); - - if (h->type !=3D type) - { - if (h->type !=3D STT_NOTYPE && ! type_change_ok) - _bfd_error_handler - /* xgettext:c-format */ - (_("warning: type of symbol `%s' changed" - " from %d to %d in %pB"), - name, h->type, type, abfd); - - h->type =3D type; - } - } - - /* Set a flag in the hash table entry indicating the type of - reference or definition we just found. Keep a count of - the number of dynamic symbols we find. A dynamic symbol - is one which is referenced or defined by both a regular - object and a shared object. */ - if (! dynamic) - { - if (! definition) - { - h->ref_regular =3D 1; - if (bind !=3D STB_WEAK) - h->ref_regular_nonweak =3D 1; - } - else - { - BFD_ASSERT (!h->def_dynamic); - h->def_regular =3D 1; - } - } - else - { - BFD_ASSERT (definition); - h->def_dynamic =3D 1; - h->dynindx =3D -2; - ((struct elf64_ia64_link_hash_entry *)h)->shl =3D abfd; - } - } - } - - free (isymbuf); - isymbuf =3D NULL; - - /* If this object is the same format as the output object, and it is - not a shared library, then let the backend look through the - relocs. - - This is required to build global offset table entries and to - arrange for dynamic relocs. It is not required for the - particular common case of linking non PIC code, even when linking - against shared libraries, but unfortunately there is no way of - knowing whether an object file has been compiled PIC or not. - Looking through the relocs is not particularly time consuming. - The problem is that we must either (1) keep the relocs in memory, - which causes the linker to require additional runtime memory or - (2) read the relocs twice from the input file, which wastes time. - This would be a good case for using mmap. - - I have no idea how to handle linking PIC code into a file of a - different format. It probably can't be done. */ - if (! dynamic - && is_elf_hash_table (&htab->root) - && bed->check_relocs !=3D NULL - && (*bed->relocs_compatible) (abfd->xvec, info->output_bfd->xvec)) - { - asection *o; - - for (o =3D abfd->sections; o !=3D NULL; o =3D o->next) - { - Elf_Internal_Rela *internal_relocs; - bool ok; - - if ((o->flags & SEC_RELOC) =3D=3D 0 - || o->reloc_count =3D=3D 0 - || ((info->strip =3D=3D strip_all || info->strip =3D=3D strip_debug= ger) - && (o->flags & SEC_DEBUGGING) !=3D 0) - || bfd_is_abs_section (o->output_section)) - continue; - - internal_relocs =3D _bfd_elf_link_read_relocs (abfd, o, NULL, NULL, - info->keep_memory); - if (internal_relocs =3D=3D NULL) - goto error_return; - - ok =3D (*bed->check_relocs) (abfd, info, o, internal_relocs); - - if (elf_section_data (o)->relocs !=3D internal_relocs) - free (internal_relocs); - - if (! ok) - goto error_return; - } - } - - return true; - - error_free_vers: - error_free_sym: - free (isymbuf); - error_return: - return false; -} - -static bool -elf64_vms_link_add_archive_symbols (bfd *abfd, struct bfd_link_info *info) -{ - int pass; - struct bfd_link_hash_entry **pundef; - struct bfd_link_hash_entry **next_pundef; - - /* We only accept VMS libraries. */ - if (info->output_bfd->xvec !=3D abfd->xvec) - { - bfd_set_error (bfd_error_wrong_format); - return false; - } - - /* The archive_pass field in the archive itself is used to - initialize PASS, since we may search the same archive multiple - times. */ - pass =3D ++abfd->archive_pass; - - /* Look through the list of undefined symbols. */ - for (pundef =3D &info->hash->undefs; *pundef !=3D NULL; pundef =3D next_= pundef) - { - struct bfd_link_hash_entry *h; - symindex symidx; - bfd *element; - bfd *orig_element; - - h =3D *pundef; - next_pundef =3D &(*pundef)->u.undef.next; - - /* When a symbol is defined, it is not necessarily removed from - the list. */ - if (h->type !=3D bfd_link_hash_undefined - && h->type !=3D bfd_link_hash_common) - { - /* Remove this entry from the list, for general cleanliness - and because we are going to look through the list again - if we search any more libraries. We can't remove the - entry if it is the tail, because that would lose any - entries we add to the list later on. */ - if (*pundef !=3D info->hash->undefs_tail) - { - *pundef =3D *next_pundef; - next_pundef =3D pundef; - } - continue; - } - - /* Look for this symbol in the archive hash table. */ - symidx =3D _bfd_vms_lib_find_symbol (abfd, h->root.string); - if (symidx =3D=3D BFD_NO_MORE_SYMBOLS) - { - /* Nothing in this slot. */ - continue; - } - - element =3D bfd_get_elt_at_index (abfd, symidx); - if (element =3D=3D NULL) - return false; - - if (element->archive_pass =3D=3D -1 || element->archive_pass =3D=3D = pass) - { - /* Next symbol if this archive is wrong or already handled. */ - continue; - } - - orig_element =3D element; - if (bfd_is_thin_archive (abfd)) - { - element =3D _bfd_vms_lib_get_imagelib_file (element); - if (element =3D=3D NULL || !bfd_check_format (element, bfd_object)) - { - orig_element->archive_pass =3D -1; - return false; - } - } - else if (! bfd_check_format (element, bfd_object)) - { - element->archive_pass =3D -1; - return false; - } - - /* Unlike the generic linker, we know that this element provides - a definition for an undefined symbol and we know that we want - to include it. We don't need to check anything. */ - if (! (*info->callbacks->add_archive_element) (info, element, - h->root.string, &element)) - continue; - if (! elf64_vms_link_add_object_symbols (element, info)) - return false; - - orig_element->archive_pass =3D pass; - } - - return true; -} - -static bool -elf64_vms_bfd_link_add_symbols (bfd *abfd, struct bfd_link_info *info) -{ - switch (bfd_get_format (abfd)) - { - case bfd_object: - return elf64_vms_link_add_object_symbols (abfd, info); - break; - case bfd_archive: - return elf64_vms_link_add_archive_symbols (abfd, info); - break; - default: - bfd_set_error (bfd_error_wrong_format); - return false; - } -} - -static bool -elf64_ia64_vms_mkobject (bfd *abfd) -{ - return bfd_elf_allocate_object - (abfd, sizeof (struct elf64_ia64_vms_obj_tdata), IA64_ELF_DATA); -} - - -/* Size-dependent data and functions. */ -static const struct elf_size_info elf64_ia64_vms_size_info =3D { - sizeof (Elf64_External_VMS_Ehdr), - sizeof (Elf64_External_Phdr), - sizeof (Elf64_External_Shdr), - sizeof (Elf64_External_Rel), - sizeof (Elf64_External_Rela), - sizeof (Elf64_External_Sym), - sizeof (Elf64_External_Dyn), - sizeof (Elf_External_Note), - 4, - 1, - 64, 3, /* ARCH_SIZE, LOG_FILE_ALIGN */ - ELFCLASS64, EV_CURRENT, - bfd_elf64_write_out_phdrs, - elf64_vms_write_shdrs_and_ehdr, - bfd_elf64_checksum_contents, - bfd_elf64_write_relocs, - bfd_elf64_swap_symbol_in, - bfd_elf64_swap_symbol_out, - bfd_elf64_slurp_reloc_table, - bfd_elf64_slurp_symbol_table, - bfd_elf64_swap_dyn_in, - bfd_elf64_swap_dyn_out, - bfd_elf64_swap_reloc_in, - bfd_elf64_swap_reloc_out, - bfd_elf64_swap_reloca_in, - bfd_elf64_swap_reloca_out -}; - -#define ELF_ARCH bfd_arch_ia64 -#define ELF_MACHINE_CODE EM_IA_64 -#define ELF_MAXPAGESIZE 0x10000 /* 64KB */ -#define ELF_COMMONPAGESIZE 0x200 /* 16KB */ - -#define elf_backend_section_from_shdr \ - elf64_ia64_section_from_shdr -#define elf_backend_section_flags \ - elf64_ia64_section_flags -#define elf_backend_fake_sections \ - elf64_ia64_fake_sections -#define elf_backend_final_write_processing \ - elf64_ia64_final_write_processing -#define elf_backend_add_symbol_hook \ - elf64_ia64_add_symbol_hook -#define elf_info_to_howto \ - elf64_ia64_info_to_howto - -#define bfd_elf64_bfd_reloc_type_lookup \ - ia64_elf_reloc_type_lookup -#define bfd_elf64_bfd_reloc_name_lookup \ - ia64_elf_reloc_name_lookup -#define bfd_elf64_bfd_is_local_label_name \ - elf64_ia64_is_local_label_name -#define bfd_elf64_bfd_relax_section \ - elf64_ia64_relax_section - -#define elf_backend_object_p \ - elf64_ia64_object_p - -/* Stuff for the BFD linker: */ -#define bfd_elf64_bfd_link_hash_table_create \ - elf64_ia64_hash_table_create -#define elf_backend_create_dynamic_sections \ - elf64_ia64_create_dynamic_sections -#define elf_backend_check_relocs \ - elf64_ia64_check_relocs -#define elf_backend_adjust_dynamic_symbol \ - elf64_ia64_adjust_dynamic_symbol -#define elf_backend_late_size_sections \ - elf64_ia64_late_size_sections -#define elf_backend_omit_section_dynsym \ - _bfd_elf_omit_section_dynsym_all -#define elf_backend_relocate_section \ - elf64_ia64_relocate_section -#define elf_backend_finish_dynamic_symbol \ - elf64_ia64_finish_dynamic_symbol -#define elf_backend_finish_dynamic_sections \ - elf64_ia64_finish_dynamic_sections -#define bfd_elf64_bfd_final_link \ - elf64_ia64_final_link - -#define bfd_elf64_bfd_merge_private_bfd_data \ - elf64_ia64_merge_private_bfd_data -#define bfd_elf64_bfd_set_private_flags \ - elf64_ia64_set_private_flags -#define bfd_elf64_bfd_print_private_bfd_data \ - elf64_ia64_print_private_bfd_data - -#define elf_backend_plt_readonly 1 -#define elf_backend_want_plt_sym 0 -#define elf_backend_plt_alignment 5 -#define elf_backend_got_header_size 0 -#define elf_backend_want_got_plt 1 -#define elf_backend_may_use_rel_p 1 -#define elf_backend_may_use_rela_p 1 -#define elf_backend_default_use_rela_p 1 -#define elf_backend_want_dynbss 0 -#define elf_backend_hide_symbol elf64_ia64_hash_hide_symbol -#define elf_backend_fixup_symbol _bfd_elf_link_hash_fixup_symbol -#define elf_backend_reloc_type_class elf64_ia64_reloc_type_class -#define elf_backend_rela_normal 1 -#define elf_backend_special_sections elf64_ia64_special_sections -#define elf_backend_default_execstack 0 - -/* FIXME: PR 290: The Intel C compiler generates SHT_IA_64_UNWIND with - SHF_LINK_ORDER. But it doesn't set the sh_link or sh_info fields. - We don't want to flood users with so many error messages. We turn - off the warning for now. It will be turned on later when the Intel - compiler is fixed. */ -#define elf_backend_link_order_error_handler NULL - -/* VMS-specific vectors. */ - -#undef TARGET_LITTLE_SYM -#define TARGET_LITTLE_SYM ia64_elf64_vms_vec -#undef TARGET_LITTLE_NAME -#define TARGET_LITTLE_NAME "elf64-ia64-vms" -#undef TARGET_BIG_SYM -#undef TARGET_BIG_NAME - -/* These are VMS specific functions. */ - -#undef elf_backend_object_p -#define elf_backend_object_p elf64_vms_object_p - -#undef elf_backend_section_from_shdr -#define elf_backend_section_from_shdr elf64_vms_section_from_shdr - -#undef elf_backend_init_file_header -#define elf_backend_init_file_header elf64_vms_init_file_header - -#undef elf_backend_section_processing -#define elf_backend_section_processing elf64_vms_section_processing - -#undef elf_backend_final_write_processing -#define elf_backend_final_write_processing elf64_vms_final_write_processing - -#undef bfd_elf64_close_and_cleanup -#define bfd_elf64_close_and_cleanup elf64_vms_close_and_cleanup - -#undef elf_backend_section_from_bfd_section - -#undef elf_backend_symbol_processing - -#undef elf_backend_want_p_paddr_set_to_zero - -#undef ELF_OSABI -#define ELF_OSABI ELFOSABI_OPENVMS - -#undef ELF_MAXPAGESIZE -#define ELF_MAXPAGESIZE 0x10000 /* 64KB */ - -#undef elf64_bed -#define elf64_bed elf64_ia64_vms_bed - -#define elf_backend_size_info elf64_ia64_vms_size_info - -/* Use VMS-style archives (in particular, don't use the standard coff - archive format). */ -#define bfd_elf64_archive_functions - -#undef bfd_elf64_archive_p -#define bfd_elf64_archive_p _bfd_vms_lib_ia64_archive_p -#undef bfd_elf64_write_archive_contents -#define bfd_elf64_write_archive_contents _bfd_vms_lib_write_archive_conten= ts -#undef bfd_elf64_mkarchive -#define bfd_elf64_mkarchive _bfd_vms_lib_ia64_mkarchive - -#define bfd_elf64_archive_slurp_armap \ - _bfd_vms_lib_slurp_armap -#define bfd_elf64_archive_slurp_extended_name_table \ - _bfd_vms_lib_slurp_extended_name_table -#define bfd_elf64_archive_construct_extended_name_table \ - _bfd_vms_lib_construct_extended_name_table -#define bfd_elf64_archive_truncate_arname \ - _bfd_vms_lib_truncate_arname -#define bfd_elf64_archive_write_armap \ - _bfd_vms_lib_write_armap -#define bfd_elf64_archive_read_ar_hdr \ - _bfd_vms_lib_read_ar_hdr -#define bfd_elf64_archive_write_ar_hdr \ - _bfd_vms_lib_write_ar_hdr -#define bfd_elf64_archive_openr_next_archived_file \ - _bfd_vms_lib_openr_next_archived_file -#define bfd_elf64_archive_get_elt_at_index \ - _bfd_vms_lib_get_elt_at_index -#define bfd_elf64_archive_generic_stat_arch_elt \ - _bfd_vms_lib_generic_stat_arch_elt -#define bfd_elf64_archive_update_armap_timestamp \ - _bfd_vms_lib_update_armap_timestamp - -/* VMS link methods. */ -#undef bfd_elf64_bfd_link_add_symbols -#define bfd_elf64_bfd_link_add_symbols elf64_vms_bfd_link_add_symbols - -#undef elf_backend_want_got_sym -#define elf_backend_want_got_sym 0 - -#undef bfd_elf64_mkobject -#define bfd_elf64_mkobject elf64_ia64_vms_mkobject - -/* Redefine to align segments on block size. */ -#undef ELF_MAXPAGESIZE -#define ELF_MAXPAGESIZE 0x200 /* 512B */ - -#undef elf_backend_want_got_plt -#define elf_backend_want_got_plt 0 - -#include "elf64-target.h" diff --git a/bfd/elfnn-ia64.c b/bfd/elfnn-ia64.c deleted file mode 100644 index 4dabaa792f6..00000000000 --- a/bfd/elfnn-ia64.c +++ /dev/null @@ -1,5116 +0,0 @@ -/* IA-64 support for 64-bit ELF - Copyright (C) 1998-2024 Free Software Foundation, Inc. - Contributed by David Mosberger-Tang - - This file is part of BFD, the Binary File Descriptor library. - - This program is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - This program is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program; if not, write to the Free Software - Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, - MA 02110-1301, USA. */ - -#include "sysdep.h" -#include "bfd.h" -#include "libbfd.h" -#include "elf-bfd.h" -#include "opcode/ia64.h" -#include "elf/ia64.h" -#include "objalloc.h" -#include "hashtab.h" -#include "elfxx-ia64.h" - -#define ARCH_SIZE NN - -#if ARCH_SIZE =3D=3D 64 -#define LOG_SECTION_ALIGN 3 -#endif - -#if ARCH_SIZE =3D=3D 32 -#define LOG_SECTION_ALIGN 2 -#endif - -#define is_ia64_elf(bfd) \ - (bfd_get_flavour (bfd) =3D=3D bfd_target_elf_flavour \ - && elf_object_id (bfd) =3D=3D IA64_ELF_DATA) - -typedef struct bfd_hash_entry *(*new_hash_entry_func) - (struct bfd_hash_entry *, struct bfd_hash_table *, const char *); - -/* In dynamically (linker-) created sections, we generally need to keep tr= ack - of the place a symbol or expression got allocated to. This is done via = hash - tables that store entries of the following type. */ - -struct elfNN_ia64_dyn_sym_info -{ - /* The addend for which this entry is relevant. */ - bfd_vma addend; - - bfd_vma got_offset; - bfd_vma fptr_offset; - bfd_vma pltoff_offset; - bfd_vma plt_offset; - bfd_vma plt2_offset; - bfd_vma tprel_offset; - bfd_vma dtpmod_offset; - bfd_vma dtprel_offset; - - /* The symbol table entry, if any, that this was derived from. */ - struct elf_link_hash_entry *h; - - /* Used to count non-got, non-plt relocations for delayed sizing - of relocation sections. */ - struct elfNN_ia64_dyn_reloc_entry - { - struct elfNN_ia64_dyn_reloc_entry *next; - asection *srel; - int type; - int count; - - /* Is this reloc against readonly section? */ - bool reltext; - } *reloc_entries; - - /* TRUE when the section contents have been updated. */ - unsigned got_done : 1; - unsigned fptr_done : 1; - unsigned pltoff_done : 1; - unsigned tprel_done : 1; - unsigned dtpmod_done : 1; - unsigned dtprel_done : 1; - - /* TRUE for the different kinds of linker data we want created. */ - unsigned want_got : 1; - unsigned want_gotx : 1; - unsigned want_fptr : 1; - unsigned want_ltoff_fptr : 1; - unsigned want_plt : 1; - unsigned want_plt2 : 1; - unsigned want_pltoff : 1; - unsigned want_tprel : 1; - unsigned want_dtpmod : 1; - unsigned want_dtprel : 1; -}; - -struct elfNN_ia64_local_hash_entry -{ - int id; - unsigned int r_sym; - /* The number of elements in elfNN_ia64_dyn_sym_info array. */ - unsigned int count; - /* The number of sorted elements in elfNN_ia64_dyn_sym_info array. */ - unsigned int sorted_count; - /* The size of elfNN_ia64_dyn_sym_info array. */ - unsigned int size; - /* The array of elfNN_ia64_dyn_sym_info. */ - struct elfNN_ia64_dyn_sym_info *info; - - /* TRUE if this hash entry's addends was translated for - SHF_MERGE optimization. */ - unsigned sec_merge_done : 1; -}; - -struct elfNN_ia64_link_hash_entry -{ - struct elf_link_hash_entry root; - /* The number of elements in elfNN_ia64_dyn_sym_info array. */ - unsigned int count; - /* The number of sorted elements in elfNN_ia64_dyn_sym_info array. */ - unsigned int sorted_count; - /* The size of elfNN_ia64_dyn_sym_info array. */ - unsigned int size; - /* The array of elfNN_ia64_dyn_sym_info. */ - struct elfNN_ia64_dyn_sym_info *info; -}; - -struct elfNN_ia64_link_hash_table -{ - /* The main hash table. */ - struct elf_link_hash_table root; - - asection *fptr_sec; /* Function descriptor table (or NULL). */ - asection *rel_fptr_sec; /* Dynamic relocation section for same. */ - asection *pltoff_sec; /* Private descriptors for plt (or NULL). */ - asection *rel_pltoff_sec; /* Dynamic relocation section for same. */ - - bfd_size_type minplt_entries; /* Number of minplt entries. */ - unsigned self_dtpmod_done : 1;/* Has self DTPMOD entry been finished? */ - bfd_vma self_dtpmod_offset; /* .got offset to self DTPMOD entry. */ - /* There are maybe R_IA64_GPREL22 relocations, including those - optimized from R_IA64_LTOFF22X, against non-SHF_IA_64_SHORT - sections. We need to record those sections so that we can choose - a proper GP to cover all R_IA64_GPREL22 relocations. */ - asection *max_short_sec; /* Maximum short output section. */ - bfd_vma max_short_offset; /* Maximum short offset. */ - asection *min_short_sec; /* Minimum short output section. */ - bfd_vma min_short_offset; /* Minimum short offset. */ - - htab_t loc_hash_table; - void *loc_hash_memory; -}; - -struct elfNN_ia64_allocate_data -{ - struct bfd_link_info *info; - bfd_size_type ofs; - bool only_got; -}; - -#define elfNN_ia64_hash_table(p) \ - ((is_elf_hash_table ((p)->hash) \ - && elf_hash_table_id (elf_hash_table (p)) =3D=3D IA64_ELF_DATA) \ - ? (struct elfNN_ia64_link_hash_table *) (p)->hash : NULL) - -static struct elfNN_ia64_dyn_sym_info * get_dyn_sym_info - (struct elfNN_ia64_link_hash_table *ia64_info, - struct elf_link_hash_entry *h, - bfd *abfd, const Elf_Internal_Rela *rel, bool create); -static bool elfNN_ia64_dynamic_symbol_p - (struct elf_link_hash_entry *h, struct bfd_link_info *info, int); -static bool elfNN_ia64_choose_gp - (bfd *abfd, struct bfd_link_info *info, bool final); -static void elfNN_ia64_dyn_sym_traverse - (struct elfNN_ia64_link_hash_table *ia64_info, - bool (*func) (struct elfNN_ia64_dyn_sym_info *, void *), - void * info); -static bool allocate_global_data_got - (struct elfNN_ia64_dyn_sym_info *dyn_i, void * data); -static bool allocate_global_fptr_got - (struct elfNN_ia64_dyn_sym_info *dyn_i, void * data); -static bool allocate_local_got - (struct elfNN_ia64_dyn_sym_info *dyn_i, void * data); -static bool elfNN_ia64_hpux_vec - (const bfd_target *vec); -static bool allocate_dynrel_entries - (struct elfNN_ia64_dyn_sym_info *dyn_i, void * data); -static asection *get_pltoff - (bfd *abfd, struct bfd_link_info *info, - struct elfNN_ia64_link_hash_table *ia64_info); -=0C -/* ia64-specific relocation. */ - -/* Given a ELF reloc, return the matching HOWTO structure. */ - -static bool -elfNN_ia64_info_to_howto (bfd *abfd ATTRIBUTE_UNUSED, - arelent *bfd_reloc, - Elf_Internal_Rela *elf_reloc) -{ - unsigned int r_type =3D ELF32_R_TYPE (elf_reloc->r_info); - - bfd_reloc->howto =3D ia64_elf_lookup_howto (r_type); - if (bfd_reloc->howto =3D=3D NULL) - { - /* xgettext:c-format */ - _bfd_error_handler (_("%pB: unsupported relocation type %#x"), - abfd, r_type); - bfd_set_error (bfd_error_bad_value); - return false; - } - - return true; -} -=0C -#define PLT_HEADER_SIZE (3 * 16) -#define PLT_MIN_ENTRY_SIZE (1 * 16) -#define PLT_FULL_ENTRY_SIZE (2 * 16) -#define PLT_RESERVED_WORDS 3 - -static const bfd_byte plt_header[PLT_HEADER_SIZE] =3D -{ - 0x0b, 0x10, 0x00, 0x1c, 0x00, 0x21, /* [MMI] mov r2=3Dr14;; */ - 0xe0, 0x00, 0x08, 0x00, 0x48, 0x00, /* addl r14=3D0,r2 */ - 0x00, 0x00, 0x04, 0x00, /* nop.i 0x0;; */ - 0x0b, 0x80, 0x20, 0x1c, 0x18, 0x14, /* [MMI] ld8 r16=3D[r14],8;; */ - 0x10, 0x41, 0x38, 0x30, 0x28, 0x00, /* ld8 r17=3D[r14],8 */ - 0x00, 0x00, 0x04, 0x00, /* nop.i 0x0;; */ - 0x11, 0x08, 0x00, 0x1c, 0x18, 0x10, /* [MIB] ld8 r1=3D[r14] */ - 0x60, 0x88, 0x04, 0x80, 0x03, 0x00, /* mov b6=3Dr17 */ - 0x60, 0x00, 0x80, 0x00 /* br.few b6;; */ -}; - -static const bfd_byte plt_min_entry[PLT_MIN_ENTRY_SIZE] =3D -{ - 0x11, 0x78, 0x00, 0x00, 0x00, 0x24, /* [MIB] mov r15=3D0 */ - 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, /* nop.i 0x0 */ - 0x00, 0x00, 0x00, 0x40 /* br.few 0 ;; */ -}; - -static const bfd_byte plt_full_entry[PLT_FULL_ENTRY_SIZE] =3D -{ - 0x0b, 0x78, 0x00, 0x02, 0x00, 0x24, /* [MMI] addl r15=3D0,r1;; */ - 0x00, 0x41, 0x3c, 0x70, 0x29, 0xc0, /* ld8.acq r16=3D[r15],8*/ - 0x01, 0x08, 0x00, 0x84, /* mov r14=3Dr1;; */ - 0x11, 0x08, 0x00, 0x1e, 0x18, 0x10, /* [MIB] ld8 r1=3D[r15] */ - 0x60, 0x80, 0x04, 0x80, 0x03, 0x00, /* mov b6=3Dr16 */ - 0x60, 0x00, 0x80, 0x00 /* br.few b6;; */ -}; - -#define ELF_DYNAMIC_INTERPRETER "/usr/lib/ld.so.1" - -static const bfd_byte oor_brl[16] =3D -{ - 0x05, 0x00, 0x00, 0x00, 0x01, 0x00, /* [MLX] nop.m 0 */ - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* brl.sptk.few tgt;; */ - 0x00, 0x00, 0x00, 0xc0 -}; - -static const bfd_byte oor_ip[48] =3D -{ - 0x04, 0x00, 0x00, 0x00, 0x01, 0x00, /* [MLX] nop.m 0 */ - 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, /* movl r15=3D0 */ - 0x01, 0x00, 0x00, 0x60, - 0x03, 0x00, 0x00, 0x00, 0x01, 0x00, /* [MII] nop.m 0 */ - 0x00, 0x01, 0x00, 0x60, 0x00, 0x00, /* mov r16=3Dip;; */ - 0xf2, 0x80, 0x00, 0x80, /* add r16=3Dr15,r16;; */ - 0x11, 0x00, 0x00, 0x00, 0x01, 0x00, /* [MIB] nop.m 0 */ - 0x60, 0x80, 0x04, 0x80, 0x03, 0x00, /* mov b6=3Dr16 */ - 0x60, 0x00, 0x80, 0x00 /* br b6;; */ -}; - -static size_t oor_branch_size =3D sizeof (oor_brl); - -void -bfd_elfNN_ia64_after_parse (int itanium) -{ - oor_branch_size =3D itanium ? sizeof (oor_ip) : sizeof (oor_brl); -} -=0C - -/* Rename some of the generic section flags to better document how they - are used here. */ -#define skip_relax_pass_0 sec_flg0 -#define skip_relax_pass_1 sec_flg1 - -/* These functions do relaxation for IA-64 ELF. */ - -static void -elfNN_ia64_update_short_info (asection *sec, bfd_vma offset, - struct elfNN_ia64_link_hash_table *ia64_info) -{ - /* Skip ABS and SHF_IA_64_SHORT sections. */ - if (sec =3D=3D bfd_abs_section_ptr - || (sec->flags & SEC_SMALL_DATA) !=3D 0) - return; - - if (!ia64_info->min_short_sec) - { - ia64_info->max_short_sec =3D sec; - ia64_info->max_short_offset =3D offset; - ia64_info->min_short_sec =3D sec; - ia64_info->min_short_offset =3D offset; - } - else if (sec =3D=3D ia64_info->max_short_sec - && offset > ia64_info->max_short_offset) - ia64_info->max_short_offset =3D offset; - else if (sec =3D=3D ia64_info->min_short_sec - && offset < ia64_info->min_short_offset) - ia64_info->min_short_offset =3D offset; - else if (sec->output_section->vma - > ia64_info->max_short_sec->vma) - { - ia64_info->max_short_sec =3D sec; - ia64_info->max_short_offset =3D offset; - } - else if (sec->output_section->vma - < ia64_info->min_short_sec->vma) - { - ia64_info->min_short_sec =3D sec; - ia64_info->min_short_offset =3D offset; - } -} - -static bool -elfNN_ia64_relax_section (bfd *abfd, asection *sec, - struct bfd_link_info *link_info, - bool *again) -{ - struct one_fixup - { - struct one_fixup *next; - asection *tsec; - bfd_vma toff; - bfd_vma trampoff; - }; - - Elf_Internal_Shdr *symtab_hdr; - Elf_Internal_Rela *internal_relocs; - Elf_Internal_Rela *irel, *irelend; - bfd_byte *contents; - Elf_Internal_Sym *isymbuf =3D NULL; - struct elfNN_ia64_link_hash_table *ia64_info; - struct one_fixup *fixups =3D NULL; - bool changed_contents =3D false; - bool changed_relocs =3D false; - bool changed_got =3D false; - bool skip_relax_pass_0 =3D true; - bool skip_relax_pass_1 =3D true; - bfd_vma gp =3D 0; - - /* Assume we're not going to change any sizes, and we'll only need - one pass. */ - *again =3D false; - - if (bfd_link_relocatable (link_info)) - (*link_info->callbacks->einfo) - (_("%P%F: --relax and -r may not be used together\n")); - - /* Don't even try to relax for non-ELF outputs. */ - if (!is_elf_hash_table (link_info->hash)) - return false; - - /* Nothing to do if there are no relocations or there is no need for - the current pass. */ - if (sec->reloc_count =3D=3D 0 - || (sec->flags & SEC_RELOC) =3D=3D 0 - || (sec->flags & SEC_HAS_CONTENTS) =3D=3D 0 - || (link_info->relax_pass =3D=3D 0 && sec->skip_relax_pass_0) - || (link_info->relax_pass =3D=3D 1 && sec->skip_relax_pass_1)) - return true; - - ia64_info =3D elfNN_ia64_hash_table (link_info); - if (ia64_info =3D=3D NULL) - return false; - - symtab_hdr =3D &elf_tdata (abfd)->symtab_hdr; - - /* Load the relocations for this section. */ - internal_relocs =3D (_bfd_elf_link_read_relocs - (abfd, sec, NULL, (Elf_Internal_Rela *) NULL, - link_info->keep_memory)); - if (internal_relocs =3D=3D NULL) - return false; - - irelend =3D internal_relocs + sec->reloc_count; - - /* Get the section contents. */ - if (elf_section_data (sec)->this_hdr.contents !=3D NULL) - contents =3D elf_section_data (sec)->this_hdr.contents; - else - { - if (!bfd_malloc_and_get_section (abfd, sec, &contents)) - goto error_return; - } - - for (irel =3D internal_relocs; irel < irelend; irel++) - { - unsigned long r_type =3D ELFNN_R_TYPE (irel->r_info); - bfd_vma symaddr, reladdr, trampoff, toff, roff; - asection *tsec; - struct one_fixup *f; - bfd_size_type amt; - bool is_branch; - struct elfNN_ia64_dyn_sym_info *dyn_i; - char symtype; - - switch (r_type) - { - case R_IA64_PCREL21B: - case R_IA64_PCREL21BI: - case R_IA64_PCREL21M: - case R_IA64_PCREL21F: - /* In pass 1, all br relaxations are done. We can skip it. */ - if (link_info->relax_pass =3D=3D 1) - continue; - skip_relax_pass_0 =3D false; - is_branch =3D true; - break; - - case R_IA64_PCREL60B: - /* We can't optimize brl to br in pass 0 since br relaxations - will increase the code size. Defer it to pass 1. */ - if (link_info->relax_pass =3D=3D 0) - { - skip_relax_pass_1 =3D false; - continue; - } - is_branch =3D true; - break; - - case R_IA64_GPREL22: - /* Update max_short_sec/min_short_sec. */ - - case R_IA64_LTOFF22X: - case R_IA64_LDXMOV: - /* We can't relax ldx/mov in pass 0 since br relaxations will - increase the code size. Defer it to pass 1. */ - if (link_info->relax_pass =3D=3D 0) - { - skip_relax_pass_1 =3D false; - continue; - } - is_branch =3D false; - break; - - default: - continue; - } - - /* Get the value of the symbol referred to by the reloc. */ - if (ELFNN_R_SYM (irel->r_info) < symtab_hdr->sh_info) - { - /* A local symbol. */ - Elf_Internal_Sym *isym; - - /* Read this BFD's local symbols. */ - if (isymbuf =3D=3D NULL) - { - isymbuf =3D (Elf_Internal_Sym *) symtab_hdr->contents; - if (isymbuf =3D=3D NULL) - isymbuf =3D bfd_elf_get_elf_syms (abfd, symtab_hdr, - symtab_hdr->sh_info, 0, - NULL, NULL, NULL); - if (isymbuf =3D=3D 0) - goto error_return; - } - - isym =3D isymbuf + ELFNN_R_SYM (irel->r_info); - if (isym->st_shndx =3D=3D SHN_UNDEF) - continue; /* We can't do anything with undefined symbols. */ - else if (isym->st_shndx =3D=3D SHN_ABS) - tsec =3D bfd_abs_section_ptr; - else if (isym->st_shndx =3D=3D SHN_COMMON) - tsec =3D bfd_com_section_ptr; - else if (isym->st_shndx =3D=3D SHN_IA_64_ANSI_COMMON) - tsec =3D bfd_com_section_ptr; - else - tsec =3D bfd_section_from_elf_index (abfd, isym->st_shndx); - - toff =3D isym->st_value; - dyn_i =3D get_dyn_sym_info (ia64_info, NULL, abfd, irel, false); - symtype =3D ELF_ST_TYPE (isym->st_info); - } - else - { - unsigned long indx; - struct elf_link_hash_entry *h; - - indx =3D ELFNN_R_SYM (irel->r_info) - symtab_hdr->sh_info; - h =3D elf_sym_hashes (abfd)[indx]; - BFD_ASSERT (h !=3D NULL); - - while (h->root.type =3D=3D bfd_link_hash_indirect - || h->root.type =3D=3D bfd_link_hash_warning) - h =3D (struct elf_link_hash_entry *) h->root.u.i.link; - - dyn_i =3D get_dyn_sym_info (ia64_info, h, abfd, irel, false); - - /* For branches to dynamic symbols, we're interested instead - in a branch to the PLT entry. */ - if (is_branch && dyn_i && dyn_i->want_plt2) - { - /* Internal branches shouldn't be sent to the PLT. - Leave this for now and we'll give an error later. */ - if (r_type !=3D R_IA64_PCREL21B) - continue; - - tsec =3D ia64_info->root.splt; - toff =3D dyn_i->plt2_offset; - BFD_ASSERT (irel->r_addend =3D=3D 0); - } - - /* Can't do anything else with dynamic symbols. */ - else if (elfNN_ia64_dynamic_symbol_p (h, link_info, r_type)) - continue; - - else - { - /* We can't do anything with undefined symbols. */ - if (h->root.type =3D=3D bfd_link_hash_undefined - || h->root.type =3D=3D bfd_link_hash_undefweak) - continue; - - tsec =3D h->root.u.def.section; - toff =3D h->root.u.def.value; - } - - symtype =3D h->type; - } - - if (tsec->sec_info_type =3D=3D SEC_INFO_TYPE_MERGE) - { - /* At this stage in linking, no SEC_MERGE symbol has been - adjusted, so all references to such symbols need to be - passed through _bfd_merged_section_offset. (Later, in - relocate_section, all SEC_MERGE symbols *except* for - section symbols have been adjusted.) - - gas may reduce relocations against symbols in SEC_MERGE - sections to a relocation against the section symbol when - the original addend was zero. When the reloc is against - a section symbol we should include the addend in the - offset passed to _bfd_merged_section_offset, since the - location of interest is the original symbol. On the - other hand, an access to "sym+addend" where "sym" is not - a section symbol should not include the addend; Such an - access is presumed to be an offset from "sym"; The - location of interest is just "sym". */ - if (symtype =3D=3D STT_SECTION) - toff +=3D irel->r_addend; - - toff =3D _bfd_merged_section_offset (abfd, &tsec, - elf_section_data (tsec)->sec_info, - toff); - - if (symtype !=3D STT_SECTION) - toff +=3D irel->r_addend; - } - else - toff +=3D irel->r_addend; - - symaddr =3D tsec->output_section->vma + tsec->output_offset + toff; - - roff =3D irel->r_offset; - - if (is_branch) - { - bfd_signed_vma offset; - - reladdr =3D (sec->output_section->vma - + sec->output_offset - + roff) & (bfd_vma) -4; - - /* The .plt section is aligned at 32byte and the .text section - is aligned at 64byte. The .text section is right after the - .plt section. After the first relaxation pass, linker may - increase the gap between the .plt and .text sections up - to 32byte. We assume linker will always insert 32byte - between the .plt and .text sections after the first - relaxation pass. */ - if (tsec =3D=3D ia64_info->root.splt) - offset =3D -0x1000000 + 32; - else - offset =3D -0x1000000; - - /* If the branch is in range, no need to do anything. */ - if ((bfd_signed_vma) (symaddr - reladdr) >=3D offset - && (bfd_signed_vma) (symaddr - reladdr) <=3D 0x0FFFFF0) - { - /* If the 60-bit branch is in 21-bit range, optimize it. */ - if (r_type =3D=3D R_IA64_PCREL60B) - { - ia64_elf_relax_brl (contents, roff); - - irel->r_info - =3D ELFNN_R_INFO (ELFNN_R_SYM (irel->r_info), - R_IA64_PCREL21B); - - /* If the original relocation offset points to slot - 1, change it to slot 2. */ - if ((irel->r_offset & 3) =3D=3D 1) - irel->r_offset +=3D 1; - - changed_contents =3D true; - changed_relocs =3D true; - } - - continue; - } - else if (r_type =3D=3D R_IA64_PCREL60B) - continue; - else if (ia64_elf_relax_br (contents, roff)) - { - irel->r_info - =3D ELFNN_R_INFO (ELFNN_R_SYM (irel->r_info), - R_IA64_PCREL60B); - - /* Make the relocation offset point to slot 1. */ - irel->r_offset =3D (irel->r_offset & ~((bfd_vma) 0x3)) + 1; - - changed_contents =3D true; - changed_relocs =3D true; - continue; - } - - /* We can't put a trampoline in a .init/.fini section. Issue - an error. */ - if (strcmp (sec->output_section->name, ".init") =3D=3D 0 - || strcmp (sec->output_section->name, ".fini") =3D=3D 0) - { - _bfd_error_handler - /* xgettext:c-format */ - (_("%pB: can't relax br at %#" PRIx64 " in section `%pA';" - " please use brl or indirect branch"), - sec->owner, (uint64_t) roff, sec); - bfd_set_error (bfd_error_bad_value); - goto error_return; - } - - /* If the branch and target are in the same section, you've - got one honking big section and we can't help you unless - you are branching backwards. You'll get an error message - later. */ - if (tsec =3D=3D sec && toff > roff) - continue; - - /* Look for an existing fixup to this address. */ - for (f =3D fixups; f ; f =3D f->next) - if (f->tsec =3D=3D tsec && f->toff =3D=3D toff) - break; - - if (f =3D=3D NULL) - { - /* Two alternatives: If it's a branch to a PLT entry, we can - make a copy of the FULL_PLT entry. Otherwise, we'll have - to use a `brl' insn to get where we're going. */ - - size_t size; - - if (tsec =3D=3D ia64_info->root.splt) - size =3D sizeof (plt_full_entry); - else - size =3D oor_branch_size; - - /* Resize the current section to make room for the new branch. */ - trampoff =3D (sec->size + 15) & (bfd_vma) -16; - - /* If trampoline is out of range, there is nothing we - can do. */ - offset =3D trampoff - (roff & (bfd_vma) -4); - if (offset < -0x1000000 || offset > 0x0FFFFF0) - continue; - - amt =3D trampoff + size; - contents =3D (bfd_byte *) bfd_realloc (contents, amt); - if (contents =3D=3D NULL) - goto error_return; - sec->size =3D amt; - - if (tsec =3D=3D ia64_info->root.splt) - { - memcpy (contents + trampoff, plt_full_entry, size); - - /* Hijack the old relocation for use as the PLTOFF reloc. */ - irel->r_info =3D ELFNN_R_INFO (ELFNN_R_SYM (irel->r_info), - R_IA64_PLTOFF22); - irel->r_offset =3D trampoff; - } - else - { - if (size =3D=3D sizeof (oor_ip)) - { - memcpy (contents + trampoff, oor_ip, size); - irel->r_info =3D ELFNN_R_INFO (ELFNN_R_SYM (irel->r_info), - R_IA64_PCREL64I); - irel->r_addend -=3D 16; - irel->r_offset =3D trampoff + 2; - } - else - { - memcpy (contents + trampoff, oor_brl, size); - irel->r_info =3D ELFNN_R_INFO (ELFNN_R_SYM (irel->r_info), - R_IA64_PCREL60B); - irel->r_offset =3D trampoff + 2; - } - - } - - /* Record the fixup so we don't do it again this section. */ - f =3D (struct one_fixup *) - bfd_malloc ((bfd_size_type) sizeof (*f)); - f->next =3D fixups; - f->tsec =3D tsec; - f->toff =3D toff; - f->trampoff =3D trampoff; - fixups =3D f; - } - else - { - /* If trampoline is out of range, there is nothing we - can do. */ - offset =3D f->trampoff - (roff & (bfd_vma) -4); - if (offset < -0x1000000 || offset > 0x0FFFFF0) - continue; - - /* Nop out the reloc, since we're finalizing things here. */ - irel->r_info =3D ELFNN_R_INFO (0, R_IA64_NONE); - } - - /* Fix up the existing branch to hit the trampoline. */ - if (ia64_elf_install_value (contents + roff, offset, r_type) - !=3D bfd_reloc_ok) - goto error_return; - - changed_contents =3D true; - changed_relocs =3D true; - } - else - { - /* Fetch the gp. */ - if (gp =3D=3D 0) - { - bfd *obfd =3D sec->output_section->owner; - gp =3D _bfd_get_gp_value (obfd); - if (gp =3D=3D 0) - { - if (!elfNN_ia64_choose_gp (obfd, link_info, false)) - goto error_return; - gp =3D _bfd_get_gp_value (obfd); - } - } - - /* If the data is out of range, do nothing. */ - if ((bfd_signed_vma) (symaddr - gp) >=3D 0x200000 - ||(bfd_signed_vma) (symaddr - gp) < -0x200000) - continue; - - if (r_type =3D=3D R_IA64_GPREL22) - elfNN_ia64_update_short_info (tsec->output_section, - tsec->output_offset + toff, - ia64_info); - else if (r_type =3D=3D R_IA64_LTOFF22X) - { - irel->r_info =3D ELFNN_R_INFO (ELFNN_R_SYM (irel->r_info), - R_IA64_GPREL22); - changed_relocs =3D true; - if (dyn_i->want_gotx) - { - dyn_i->want_gotx =3D 0; - changed_got |=3D !dyn_i->want_got; - } - - elfNN_ia64_update_short_info (tsec->output_section, - tsec->output_offset + toff, - ia64_info); - } - else - { - ia64_elf_relax_ldxmov (contents, roff); - irel->r_info =3D ELFNN_R_INFO (0, R_IA64_NONE); - changed_contents =3D true; - changed_relocs =3D true; - } - } - } - - /* ??? If we created fixups, this may push the code segment large - enough that the data segment moves, which will change the GP. - Reset the GP so that we re-calculate next round. We need to - do this at the _beginning_ of the next round; now will not do. */ - - /* Clean up and go home. */ - while (fixups) - { - struct one_fixup *f =3D fixups; - fixups =3D fixups->next; - free (f); - } - - if (isymbuf !=3D NULL - && symtab_hdr->contents !=3D (unsigned char *) isymbuf) - { - if (! link_info->keep_memory) - free (isymbuf); - else - { - /* Cache the symbols for elf_link_input_bfd. */ - symtab_hdr->contents =3D (unsigned char *) isymbuf; - } - } - - if (contents !=3D NULL - && elf_section_data (sec)->this_hdr.contents !=3D contents) - { - if (!changed_contents && !link_info->keep_memory) - free (contents); - else - { - /* Cache the section contents for elf_link_input_bfd. */ - elf_section_data (sec)->this_hdr.contents =3D contents; - } - } - - if (elf_section_data (sec)->relocs !=3D internal_relocs) - { - if (!changed_relocs) - free (internal_relocs); - else - elf_section_data (sec)->relocs =3D internal_relocs; - } - - if (changed_got) - { - struct elfNN_ia64_allocate_data data; - data.info =3D link_info; - data.ofs =3D 0; - ia64_info->self_dtpmod_offset =3D (bfd_vma) -1; - - elfNN_ia64_dyn_sym_traverse (ia64_info, allocate_global_data_got, &d= ata); - elfNN_ia64_dyn_sym_traverse (ia64_info, allocate_global_fptr_got, &d= ata); - elfNN_ia64_dyn_sym_traverse (ia64_info, allocate_local_got, &data); - ia64_info->root.sgot->size =3D data.ofs; - - if (ia64_info->root.dynamic_sections_created - && ia64_info->root.srelgot !=3D NULL) - { - /* Resize .rela.got. */ - ia64_info->root.srelgot->size =3D 0; - if (bfd_link_pic (link_info) - && ia64_info->self_dtpmod_offset !=3D (bfd_vma) -1) - ia64_info->root.srelgot->size +=3D sizeof (ElfNN_External_Rela); - data.only_got =3D true; - elfNN_ia64_dyn_sym_traverse (ia64_info, allocate_dynrel_entries, - &data); - } - } - - if (link_info->relax_pass =3D=3D 0) - { - /* Pass 0 is only needed to relax br. */ - sec->skip_relax_pass_0 =3D skip_relax_pass_0; - sec->skip_relax_pass_1 =3D skip_relax_pass_1; - } - - *again =3D changed_contents || changed_relocs; - return true; - - error_return: - if ((unsigned char *) isymbuf !=3D symtab_hdr->contents) - free (isymbuf); - if (elf_section_data (sec)->this_hdr.contents !=3D contents) - free (contents); - if (elf_section_data (sec)->relocs !=3D internal_relocs) - free (internal_relocs); - return false; -} -#undef skip_relax_pass_0 -#undef skip_relax_pass_1 -=0C -/* Return TRUE if NAME is an unwind table section name. */ - -static inline bool -is_unwind_section_name (bfd *abfd, const char *name) -{ - if (elfNN_ia64_hpux_vec (abfd->xvec) - && !strcmp (name, ELF_STRING_ia64_unwind_hdr)) - return false; - - return ((startswith (name, ELF_STRING_ia64_unwind) - && ! startswith (name, ELF_STRING_ia64_unwind_info)) - || startswith (name, ELF_STRING_ia64_unwind_once)); -} - -/* Handle an IA-64 specific section when reading an object file. This - is called when bfd_section_from_shdr finds a section with an unknown - type. */ - -static bool -elfNN_ia64_section_from_shdr (bfd *abfd, - Elf_Internal_Shdr *hdr, - const char *name, - int shindex) -{ - /* There ought to be a place to keep ELF backend specific flags, but - at the moment there isn't one. We just keep track of the - sections by their name, instead. Fortunately, the ABI gives - suggested names for all the MIPS specific sections, so we will - probably get away with this. */ - switch (hdr->sh_type) - { - case SHT_IA_64_UNWIND: - case SHT_IA_64_HP_OPT_ANOT: - break; - - case SHT_IA_64_EXT: - if (strcmp (name, ELF_STRING_ia64_archext) !=3D 0) - return false; - break; - - default: - return false; - } - - if (! _bfd_elf_make_section_from_shdr (abfd, hdr, name, shindex)) - return false; - - return true; -} - -/* Convert IA-64 specific section flags to bfd internal section flags. */ - -/* ??? There is no bfd internal flag equivalent to the SHF_IA_64_NORECOV - flag. */ - -static bool -elfNN_ia64_section_flags (const Elf_Internal_Shdr *hdr) -{ - if (hdr->sh_flags & SHF_IA_64_SHORT) - hdr->bfd_section->flags |=3D SEC_SMALL_DATA; - - return true; -} - -/* Set the correct type for an IA-64 ELF section. We do this by the - section name, which is a hack, but ought to work. */ - -static bool -elfNN_ia64_fake_sections (bfd *abfd, Elf_Internal_Shdr *hdr, - asection *sec) -{ - const char *name; - - name =3D bfd_section_name (sec); - - if (is_unwind_section_name (abfd, name)) - { - /* We don't have the sections numbered at this point, so sh_info - is set later, in elfNN_ia64_final_write_processing. */ - hdr->sh_type =3D SHT_IA_64_UNWIND; - hdr->sh_flags |=3D SHF_LINK_ORDER; - } - else if (strcmp (name, ELF_STRING_ia64_archext) =3D=3D 0) - hdr->sh_type =3D SHT_IA_64_EXT; - else if (strcmp (name, ".HP.opt_annot") =3D=3D 0) - hdr->sh_type =3D SHT_IA_64_HP_OPT_ANOT; - else if (strcmp (name, ".reloc") =3D=3D 0) - /* This is an ugly, but unfortunately necessary hack that is - needed when producing EFI binaries on IA-64. It tells - elf.c:elf_fake_sections() not to consider ".reloc" as a section - containing ELF relocation info. We need this hack in order to - be able to generate ELF binaries that can be translated into - EFI applications (which are essentially COFF objects). Those - files contain a COFF ".reloc" section inside an ELFNN object, - which would normally cause BFD to segfault because it would - attempt to interpret this section as containing relocation - entries for section "oc". With this hack enabled, ".reloc" - will be treated as a normal data section, which will avoid the - segfault. However, you won't be able to create an ELFNN binary - with a section named "oc" that needs relocations, but that's - the kind of ugly side-effects you get when detecting section - types based on their names... In practice, this limitation is - unlikely to bite. */ - hdr->sh_type =3D SHT_PROGBITS; - - if (sec->flags & SEC_SMALL_DATA) - hdr->sh_flags |=3D SHF_IA_64_SHORT; - - /* Some HP linkers look for the SHF_IA_64_HP_TLS flag instead of SHF_TLS= . */ - - if (elfNN_ia64_hpux_vec (abfd->xvec) && (sec->flags & SHF_TLS)) - hdr->sh_flags |=3D SHF_IA_64_HP_TLS; - - return true; -} - -/* The final processing done just before writing out an IA-64 ELF - object file. */ - -static bool -elfNN_ia64_final_write_processing (bfd *abfd) -{ - Elf_Internal_Shdr *hdr; - asection *s; - - for (s =3D abfd->sections; s; s =3D s->next) - { - hdr =3D &elf_section_data (s)->this_hdr; - switch (hdr->sh_type) - { - case SHT_IA_64_UNWIND: - /* The IA-64 processor-specific ABI requires setting sh_link - to the unwind section, whereas HP-UX requires sh_info to - do so. For maximum compatibility, we'll set both for - now... */ - hdr->sh_info =3D hdr->sh_link; - break; - } - } - - if (! elf_flags_init (abfd)) - { - unsigned long flags =3D 0; - - if (abfd->xvec->byteorder =3D=3D BFD_ENDIAN_BIG) - flags |=3D EF_IA_64_BE; - if (bfd_get_mach (abfd) =3D=3D bfd_mach_ia64_elf64) - flags |=3D EF_IA_64_ABI64; - - elf_elfheader(abfd)->e_flags =3D flags; - elf_flags_init (abfd) =3D true; - } - return _bfd_elf_final_write_processing (abfd); -} - -/* Hook called by the linker routine which adds symbols from an object - file. We use it to put .comm items in .sbss, and not .bss. */ - -static bool -elfNN_ia64_add_symbol_hook (bfd *abfd, - struct bfd_link_info *info, - Elf_Internal_Sym *sym, - const char **namep ATTRIBUTE_UNUSED, - flagword *flagsp ATTRIBUTE_UNUSED, - asection **secp, - bfd_vma *valp) -{ - if (sym->st_shndx =3D=3D SHN_COMMON - && !bfd_link_relocatable (info) - && sym->st_size <=3D elf_gp_size (abfd)) - { - /* Common symbols less than or equal to -G nn bytes are - automatically put into .sbss. */ - - asection *scomm =3D bfd_get_section_by_name (abfd, ".scommon"); - - if (scomm =3D=3D NULL) - { - scomm =3D bfd_make_section_with_flags (abfd, ".scommon", - (SEC_ALLOC - | SEC_IS_COMMON - | SEC_SMALL_DATA - | SEC_LINKER_CREATED)); - if (scomm =3D=3D NULL) - return false; - } - - *secp =3D scomm; - *valp =3D sym->st_size; - } - - return true; -} - -/* Return the number of additional phdrs we will need. */ - -static int -elfNN_ia64_additional_program_headers (bfd *abfd, - struct bfd_link_info *info ATTRIBUTE_UNUSED) -{ - asection *s; - int ret =3D 0; - - /* See if we need a PT_IA_64_ARCHEXT segment. */ - s =3D bfd_get_section_by_name (abfd, ELF_STRING_ia64_archext); - if (s && (s->flags & SEC_LOAD)) - ++ret; - - /* Count how many PT_IA_64_UNWIND segments we need. */ - for (s =3D abfd->sections; s; s =3D s->next) - if (is_unwind_section_name (abfd, s->name) && (s->flags & SEC_LOAD)) - ++ret; - - return ret; -} - -static bool -elfNN_ia64_modify_segment_map (bfd *abfd, - struct bfd_link_info *info ATTRIBUTE_UNUSED) -{ - struct elf_segment_map *m, **pm; - Elf_Internal_Shdr *hdr; - asection *s; - - /* If we need a PT_IA_64_ARCHEXT segment, it must come before - all PT_LOAD segments. */ - s =3D bfd_get_section_by_name (abfd, ELF_STRING_ia64_archext); - if (s && (s->flags & SEC_LOAD)) - { - for (m =3D elf_seg_map (abfd); m !=3D NULL; m =3D m->next) - if (m->p_type =3D=3D PT_IA_64_ARCHEXT) - break; - if (m =3D=3D NULL) - { - m =3D ((struct elf_segment_map *) - bfd_zalloc (abfd, (bfd_size_type) sizeof *m)); - if (m =3D=3D NULL) - return false; - - m->p_type =3D PT_IA_64_ARCHEXT; - m->count =3D 1; - m->sections[0] =3D s; - - /* We want to put it after the PHDR and INTERP segments. */ - pm =3D &elf_seg_map (abfd); - while (*pm !=3D NULL - && ((*pm)->p_type =3D=3D PT_PHDR - || (*pm)->p_type =3D=3D PT_INTERP)) - pm =3D &(*pm)->next; - - m->next =3D *pm; - *pm =3D m; - } - } - - /* Install PT_IA_64_UNWIND segments, if needed. */ - for (s =3D abfd->sections; s; s =3D s->next) - { - hdr =3D &elf_section_data (s)->this_hdr; - if (hdr->sh_type !=3D SHT_IA_64_UNWIND) - continue; - - if (s && (s->flags & SEC_LOAD)) - { - for (m =3D elf_seg_map (abfd); m !=3D NULL; m =3D m->next) - if (m->p_type =3D=3D PT_IA_64_UNWIND) - { - int i; - - /* Look through all sections in the unwind segment - for a match since there may be multiple sections - to a segment. */ - for (i =3D m->count - 1; i >=3D 0; --i) - if (m->sections[i] =3D=3D s) - break; - - if (i >=3D 0) - break; - } - - if (m =3D=3D NULL) - { - m =3D ((struct elf_segment_map *) - bfd_zalloc (abfd, (bfd_size_type) sizeof *m)); - if (m =3D=3D NULL) - return false; - - m->p_type =3D PT_IA_64_UNWIND; - m->count =3D 1; - m->sections[0] =3D s; - m->next =3D NULL; - - /* We want to put it last. */ - pm =3D &elf_seg_map (abfd); - while (*pm !=3D NULL) - pm =3D &(*pm)->next; - *pm =3D m; - } - } - } - - return true; -} - -/* Turn on PF_IA_64_NORECOV if needed. This involves traversing all of - the input sections for each output section in the segment and testing - for SHF_IA_64_NORECOV on each. */ - -static bool -elfNN_ia64_modify_headers (bfd *abfd, struct bfd_link_info *info) -{ - struct elf_obj_tdata *tdata =3D elf_tdata (abfd); - struct elf_segment_map *m; - Elf_Internal_Phdr *p; - - for (p =3D tdata->phdr, m =3D elf_seg_map (abfd); m !=3D NULL; m =3D m->= next, p++) - if (m->p_type =3D=3D PT_LOAD) - { - int i; - for (i =3D m->count - 1; i >=3D 0; --i) - { - struct bfd_link_order *order =3D m->sections[i]->map_head.link_order; - - while (order !=3D NULL) - { - if (order->type =3D=3D bfd_indirect_link_order) - { - asection *is =3D order->u.indirect.section; - bfd_vma flags =3D elf_section_data(is)->this_hdr.sh_flags; - if (flags & SHF_IA_64_NORECOV) - { - p->p_flags |=3D PF_IA_64_NORECOV; - goto found; - } - } - order =3D order->next; - } - } - found:; - } - - return _bfd_elf_modify_headers (abfd, info); -} - -/* According to the Tahoe assembler spec, all labels starting with a - '.' are local. */ - -static bool -elfNN_ia64_is_local_label_name (bfd *abfd ATTRIBUTE_UNUSED, - const char *name) -{ - return name[0] =3D=3D '.'; -} - -/* Should we do dynamic things to this symbol? */ - -static bool -elfNN_ia64_dynamic_symbol_p (struct elf_link_hash_entry *h, - struct bfd_link_info *info, int r_type) -{ - bool ignore_protected - =3D ((r_type & 0xf8) =3D=3D 0x40 /* FPTR relocs */ - || (r_type & 0xf8) =3D=3D 0x50); /* LTOFF_FPTR relocs */ - - return _bfd_elf_dynamic_symbol_p (h, info, ignore_protected); -} -=0C -static struct bfd_hash_entry* -elfNN_ia64_new_elf_hash_entry (struct bfd_hash_entry *entry, - struct bfd_hash_table *table, - const char *string) -{ - struct elfNN_ia64_link_hash_entry *ret; - ret =3D (struct elfNN_ia64_link_hash_entry *) entry; - - /* Allocate the structure if it has not already been allocated by a - subclass. */ - if (!ret) - ret =3D bfd_hash_allocate (table, sizeof (*ret)); - - if (!ret) - return 0; - - /* Call the allocation method of the superclass. */ - ret =3D ((struct elfNN_ia64_link_hash_entry *) - _bfd_elf_link_hash_newfunc ((struct bfd_hash_entry *) ret, - table, string)); - - ret->info =3D NULL; - ret->count =3D 0; - ret->sorted_count =3D 0; - ret->size =3D 0; - return (struct bfd_hash_entry *) ret; -} - -static void -elfNN_ia64_hash_copy_indirect (struct bfd_link_info *info, - struct elf_link_hash_entry *xdir, - struct elf_link_hash_entry *xind) -{ - struct elfNN_ia64_link_hash_entry *dir, *ind; - - dir =3D (struct elfNN_ia64_link_hash_entry *) xdir; - ind =3D (struct elfNN_ia64_link_hash_entry *) xind; - - /* Copy down any references that we may have already seen to the - symbol which just became indirect. */ - - if (dir->root.versioned !=3D versioned_hidden) - dir->root.ref_dynamic |=3D ind->root.ref_dynamic; - dir->root.ref_regular |=3D ind->root.ref_regular; - dir->root.ref_regular_nonweak |=3D ind->root.ref_regular_nonweak; - dir->root.needs_plt |=3D ind->root.needs_plt; - - if (ind->root.root.type !=3D bfd_link_hash_indirect) - return; - - /* Copy over the got and plt data. This would have been done - by check_relocs. */ - - if (ind->info !=3D NULL) - { - struct elfNN_ia64_dyn_sym_info *dyn_i; - unsigned int count; - - free (dir->info); - - dir->info =3D ind->info; - dir->count =3D ind->count; - dir->sorted_count =3D ind->sorted_count; - dir->size =3D ind->size; - - ind->info =3D NULL; - ind->count =3D 0; - ind->sorted_count =3D 0; - ind->size =3D 0; - - /* Fix up the dyn_sym_info pointers to the global symbol. */ - for (count =3D dir->count, dyn_i =3D dir->info; - count !=3D 0; - count--, dyn_i++) - dyn_i->h =3D &dir->root; - } - - /* Copy over the dynindx. */ - - if (ind->root.dynindx !=3D -1) - { - if (dir->root.dynindx !=3D -1) - _bfd_elf_strtab_delref (elf_hash_table (info)->dynstr, - dir->root.dynstr_index); - dir->root.dynindx =3D ind->root.dynindx; - dir->root.dynstr_index =3D ind->root.dynstr_index; - ind->root.dynindx =3D -1; - ind->root.dynstr_index =3D 0; - } -} - -static void -elfNN_ia64_hash_hide_symbol (struct bfd_link_info *info, - struct elf_link_hash_entry *xh, - bool force_local) -{ - struct elfNN_ia64_link_hash_entry *h; - struct elfNN_ia64_dyn_sym_info *dyn_i; - unsigned int count; - - h =3D (struct elfNN_ia64_link_hash_entry *)xh; - - _bfd_elf_link_hash_hide_symbol (info, &h->root, force_local); - - for (count =3D h->count, dyn_i =3D h->info; - count !=3D 0; - count--, dyn_i++) - { - dyn_i->want_plt2 =3D 0; - dyn_i->want_plt =3D 0; - } -} - -/* Compute a hash of a local hash entry. */ - -static hashval_t -elfNN_ia64_local_htab_hash (const void *ptr) -{ - struct elfNN_ia64_local_hash_entry *entry - =3D (struct elfNN_ia64_local_hash_entry *) ptr; - - return ELF_LOCAL_SYMBOL_HASH (entry->id, entry->r_sym); -} - -/* Compare local hash entries. */ - -static int -elfNN_ia64_local_htab_eq (const void *ptr1, const void *ptr2) -{ - struct elfNN_ia64_local_hash_entry *entry1 - =3D (struct elfNN_ia64_local_hash_entry *) ptr1; - struct elfNN_ia64_local_hash_entry *entry2 - =3D (struct elfNN_ia64_local_hash_entry *) ptr2; - - return entry1->id =3D=3D entry2->id && entry1->r_sym =3D=3D entry2->r_sy= m; -} - -/* Free the global elfNN_ia64_dyn_sym_info array. */ - -static bool -elfNN_ia64_global_dyn_info_free (struct elf_link_hash_entry *xentry, - void *unused ATTRIBUTE_UNUSED) -{ - struct elfNN_ia64_link_hash_entry *entry - =3D (struct elfNN_ia64_link_hash_entry *) xentry; - - free (entry->info); - entry->info =3D NULL; - entry->count =3D 0; - entry->sorted_count =3D 0; - entry->size =3D 0; - - return true; -} - -/* Free the local elfNN_ia64_dyn_sym_info array. */ - -static int -elfNN_ia64_local_dyn_info_free (void **slot, - void * unused ATTRIBUTE_UNUSED) -{ - struct elfNN_ia64_local_hash_entry *entry - =3D (struct elfNN_ia64_local_hash_entry *) *slot; - - free (entry->info); - entry->info =3D NULL; - entry->count =3D 0; - entry->sorted_count =3D 0; - entry->size =3D 0; - - return true; -} - -/* Destroy IA-64 linker hash table. */ - -static void -elfNN_ia64_link_hash_table_free (bfd *obfd) -{ - struct elfNN_ia64_link_hash_table *ia64_info - =3D (struct elfNN_ia64_link_hash_table *) obfd->link.hash; - if (ia64_info->loc_hash_table) - { - htab_traverse (ia64_info->loc_hash_table, - elfNN_ia64_local_dyn_info_free, NULL); - htab_delete (ia64_info->loc_hash_table); - } - if (ia64_info->loc_hash_memory) - objalloc_free ((struct objalloc *) ia64_info->loc_hash_memory); - elf_link_hash_traverse (&ia64_info->root, - elfNN_ia64_global_dyn_info_free, NULL); - _bfd_elf_link_hash_table_free (obfd); -} - -/* Create the derived linker hash table. The IA-64 ELF port uses this - derived hash table to keep information specific to the IA-64 ElF - linker (without using static variables). */ - -static struct bfd_link_hash_table * -elfNN_ia64_hash_table_create (bfd *abfd) -{ - struct elfNN_ia64_link_hash_table *ret; - - ret =3D bfd_zmalloc ((bfd_size_type) sizeof (*ret)); - if (!ret) - return NULL; - - if (!_bfd_elf_link_hash_table_init (&ret->root, abfd, - elfNN_ia64_new_elf_hash_entry, - sizeof (struct elfNN_ia64_link_hash_entry), - IA64_ELF_DATA)) - { - free (ret); - return NULL; - } - - ret->loc_hash_table =3D htab_try_create (1024, elfNN_ia64_local_htab_has= h, - elfNN_ia64_local_htab_eq, NULL); - ret->loc_hash_memory =3D objalloc_create (); - if (!ret->loc_hash_table || !ret->loc_hash_memory) - { - elfNN_ia64_link_hash_table_free (abfd); - return NULL; - } - ret->root.root.hash_table_free =3D elfNN_ia64_link_hash_table_free; - ret->root.dt_pltgot_required =3D true; - - return &ret->root.root; -} - -/* Traverse both local and global hash tables. */ - -struct elfNN_ia64_dyn_sym_traverse_data -{ - bool (*func) (struct elfNN_ia64_dyn_sym_info *, void *); - void * data; -}; - -static bool -elfNN_ia64_global_dyn_sym_thunk (struct elf_link_hash_entry *xentry, - void * xdata) -{ - struct elfNN_ia64_link_hash_entry *entry - =3D (struct elfNN_ia64_link_hash_entry *) xentry; - struct elfNN_ia64_dyn_sym_traverse_data *data - =3D (struct elfNN_ia64_dyn_sym_traverse_data *) xdata; - struct elfNN_ia64_dyn_sym_info *dyn_i; - unsigned int count; - - for (count =3D entry->count, dyn_i =3D entry->info; - count !=3D 0; - count--, dyn_i++) - if (! (*data->func) (dyn_i, data->data)) - return false; - return true; -} - -static int -elfNN_ia64_local_dyn_sym_thunk (void **slot, void * xdata) -{ - struct elfNN_ia64_local_hash_entry *entry - =3D (struct elfNN_ia64_local_hash_entry *) *slot; - struct elfNN_ia64_dyn_sym_traverse_data *data - =3D (struct elfNN_ia64_dyn_sym_traverse_data *) xdata; - struct elfNN_ia64_dyn_sym_info *dyn_i; - unsigned int count; - - for (count =3D entry->count, dyn_i =3D entry->info; - count !=3D 0; - count--, dyn_i++) - if (! (*data->func) (dyn_i, data->data)) - return false; - return true; -} - -static void -elfNN_ia64_dyn_sym_traverse (struct elfNN_ia64_link_hash_table *ia64_info, - bool (*func) (struct elfNN_ia64_dyn_sym_info *, - void *), - void * data) -{ - struct elfNN_ia64_dyn_sym_traverse_data xdata; - - xdata.func =3D func; - xdata.data =3D data; - - elf_link_hash_traverse (&ia64_info->root, - elfNN_ia64_global_dyn_sym_thunk, &xdata); - htab_traverse (ia64_info->loc_hash_table, - elfNN_ia64_local_dyn_sym_thunk, &xdata); -} -=0C -static bool -elfNN_ia64_create_dynamic_sections (bfd *abfd, - struct bfd_link_info *info) -{ - struct elfNN_ia64_link_hash_table *ia64_info; - asection *s; - - if (! _bfd_elf_create_dynamic_sections (abfd, info)) - return false; - - ia64_info =3D elfNN_ia64_hash_table (info); - if (ia64_info =3D=3D NULL) - return false; - - { - flagword flags =3D bfd_section_flags (ia64_info->root.sgot); - bfd_set_section_flags (ia64_info->root.sgot, SEC_SMALL_DATA | flags); - /* The .got section is always aligned at 8 bytes. */ - if (!bfd_set_section_alignment (ia64_info->root.sgot, 3)) - return false; - } - - if (!get_pltoff (abfd, info, ia64_info)) - return false; - - s =3D bfd_make_section_anyway_with_flags (abfd, ".rela.IA_64.pltoff", - (SEC_ALLOC | SEC_LOAD - | SEC_HAS_CONTENTS - | SEC_IN_MEMORY - | SEC_LINKER_CREATED - | SEC_READONLY)); - if (s =3D=3D NULL - || !bfd_set_section_alignment (s, LOG_SECTION_ALIGN)) - return false; - ia64_info->rel_pltoff_sec =3D s; - - return true; -} - -/* Find and/or create a hash entry for local symbol. */ -static struct elfNN_ia64_local_hash_entry * -get_local_sym_hash (struct elfNN_ia64_link_hash_table *ia64_info, - bfd *abfd, const Elf_Internal_Rela *rel, - bool create) -{ - struct elfNN_ia64_local_hash_entry e, *ret; - asection *sec =3D abfd->sections; - hashval_t h =3D ELF_LOCAL_SYMBOL_HASH (sec->id, - ELFNN_R_SYM (rel->r_info)); - void **slot; - - e.id =3D sec->id; - e.r_sym =3D ELFNN_R_SYM (rel->r_info); - slot =3D htab_find_slot_with_hash (ia64_info->loc_hash_table, &e, h, - create ? INSERT : NO_INSERT); - - if (!slot) - return NULL; - - if (*slot) - return (struct elfNN_ia64_local_hash_entry *) *slot; - - ret =3D (struct elfNN_ia64_local_hash_entry *) - objalloc_alloc ((struct objalloc *) ia64_info->loc_hash_memory, - sizeof (struct elfNN_ia64_local_hash_entry)); - if (ret) - { - memset (ret, 0, sizeof (*ret)); - ret->id =3D sec->id; - ret->r_sym =3D ELFNN_R_SYM (rel->r_info); - *slot =3D ret; - } - return ret; -} - -/* Used to sort elfNN_ia64_dyn_sym_info array. */ - -static int -addend_compare (const void *xp, const void *yp) -{ - const struct elfNN_ia64_dyn_sym_info *x - =3D (const struct elfNN_ia64_dyn_sym_info *) xp; - const struct elfNN_ia64_dyn_sym_info *y - =3D (const struct elfNN_ia64_dyn_sym_info *) yp; - - return x->addend < y->addend ? -1 : x->addend > y->addend ? 1 : 0; -} - -/* Sort elfNN_ia64_dyn_sym_info array and remove duplicates. */ - -static unsigned int -sort_dyn_sym_info (struct elfNN_ia64_dyn_sym_info *info, - unsigned int count) -{ - bfd_vma curr, prev, got_offset; - unsigned int i, kept, dupes, diff, dest, src, len; - - qsort (info, count, sizeof (*info), addend_compare); - - /* Find the first duplicate. */ - prev =3D info [0].addend; - got_offset =3D info [0].got_offset; - for (i =3D 1; i < count; i++) - { - curr =3D info [i].addend; - if (curr =3D=3D prev) - { - /* For duplicates, make sure that GOT_OFFSET is valid. */ - if (got_offset =3D=3D (bfd_vma) -1) - got_offset =3D info [i].got_offset; - break; - } - got_offset =3D info [i].got_offset; - prev =3D curr; - } - - /* We may move a block of elements to here. */ - dest =3D i++; - - /* Remove duplicates. */ - if (i < count) - { - while (i < count) - { - /* For duplicates, make sure that the kept one has a valid - got_offset. */ - kept =3D dest - 1; - if (got_offset !=3D (bfd_vma) -1) - info [kept].got_offset =3D got_offset; - - curr =3D info [i].addend; - got_offset =3D info [i].got_offset; - - /* Move a block of elements whose first one is different from - the previous. */ - if (curr =3D=3D prev) - { - for (src =3D i + 1; src < count; src++) - { - if (info [src].addend !=3D curr) - break; - /* For duplicates, make sure that GOT_OFFSET is - valid. */ - if (got_offset =3D=3D (bfd_vma) -1) - got_offset =3D info [src].got_offset; - } - - /* Make sure that the kept one has a valid got_offset. */ - if (got_offset !=3D (bfd_vma) -1) - info [kept].got_offset =3D got_offset; - } - else - src =3D i; - - if (src >=3D count) - break; - - /* Find the next duplicate. SRC will be kept. */ - prev =3D info [src].addend; - got_offset =3D info [src].got_offset; - for (dupes =3D src + 1; dupes < count; dupes ++) - { - curr =3D info [dupes].addend; - if (curr =3D=3D prev) - { - /* Make sure that got_offset is valid. */ - if (got_offset =3D=3D (bfd_vma) -1) - got_offset =3D info [dupes].got_offset; - - /* For duplicates, make sure that the kept one has - a valid got_offset. */ - if (got_offset !=3D (bfd_vma) -1) - info [dupes - 1].got_offset =3D got_offset; - break; - } - got_offset =3D info [dupes].got_offset; - prev =3D curr; - } - - /* How much to move. */ - len =3D dupes - src; - i =3D dupes + 1; - - if (len =3D=3D 1 && dupes < count) - { - /* If we only move 1 element, we combine it with the next - one. There must be at least a duplicate. Find the - next different one. */ - for (diff =3D dupes + 1, src++; diff < count; diff++, src++) - { - if (info [diff].addend !=3D curr) - break; - /* Make sure that got_offset is valid. */ - if (got_offset =3D=3D (bfd_vma) -1) - got_offset =3D info [diff].got_offset; - } - - /* Makre sure that the last duplicated one has an valid - offset. */ - BFD_ASSERT (curr =3D=3D prev); - if (got_offset !=3D (bfd_vma) -1) - info [diff - 1].got_offset =3D got_offset; - - if (diff < count) - { - /* Find the next duplicate. Track the current valid - offset. */ - prev =3D info [diff].addend; - got_offset =3D info [diff].got_offset; - for (dupes =3D diff + 1; dupes < count; dupes ++) - { - curr =3D info [dupes].addend; - if (curr =3D=3D prev) - { - /* For duplicates, make sure that GOT_OFFSET - is valid. */ - if (got_offset =3D=3D (bfd_vma) -1) - got_offset =3D info [dupes].got_offset; - break; - } - got_offset =3D info [dupes].got_offset; - prev =3D curr; - diff++; - } - - len =3D diff - src + 1; - i =3D diff + 1; - } - } - - memmove (&info [dest], &info [src], len * sizeof (*info)); - - dest +=3D len; - } - - count =3D dest; - } - else - { - /* When we get here, either there is no duplicate at all or - the only duplicate is the last element. */ - if (dest < count) - { - /* If the last element is a duplicate, make sure that the - kept one has a valid got_offset. We also update count. */ - if (got_offset !=3D (bfd_vma) -1) - info [dest - 1].got_offset =3D got_offset; - count =3D dest; - } - } - - return count; -} - -/* Find and/or create a descriptor for dynamic symbol info. This will - vary based on global or local symbol, and the addend to the reloc. - - We don't sort when inserting. Also, we sort and eliminate - duplicates if there is an unsorted section. Typically, this will - only happen once, because we do all insertions before lookups. We - then use bsearch to do a lookup. This also allows lookups to be - fast. So we have fast insertion (O(log N) due to duplicate check), - fast lookup (O(log N)) and one sort (O(N log N) expected time). - Previously, all lookups were O(N) because of the use of the linked - list and also all insertions were O(N) because of the check for - duplicates. There are some complications here because the array - size grows occasionally, which may add an O(N) factor, but this - should be rare. Also, we free the excess array allocation, which - requires a copy which is O(N), but this only happens once. */ - -static struct elfNN_ia64_dyn_sym_info * -get_dyn_sym_info (struct elfNN_ia64_link_hash_table *ia64_info, - struct elf_link_hash_entry *h, bfd *abfd, - const Elf_Internal_Rela *rel, bool create) -{ - struct elfNN_ia64_dyn_sym_info **info_p, *info, *dyn_i, key; - unsigned int *count_p, *sorted_count_p, *size_p; - unsigned int count, sorted_count, size; - bfd_vma addend =3D rel ? rel->r_addend : 0; - bfd_size_type amt; - - if (h) - { - struct elfNN_ia64_link_hash_entry *global_h; - - global_h =3D (struct elfNN_ia64_link_hash_entry *) h; - info_p =3D &global_h->info; - count_p =3D &global_h->count; - sorted_count_p =3D &global_h->sorted_count; - size_p =3D &global_h->size; - } - else - { - struct elfNN_ia64_local_hash_entry *loc_h; - - loc_h =3D get_local_sym_hash (ia64_info, abfd, rel, create); - if (!loc_h) - { - BFD_ASSERT (!create); - return NULL; - } - - info_p =3D &loc_h->info; - count_p =3D &loc_h->count; - sorted_count_p =3D &loc_h->sorted_count; - size_p =3D &loc_h->size; - } - - count =3D *count_p; - sorted_count =3D *sorted_count_p; - size =3D *size_p; - info =3D *info_p; - if (create) - { - /* When we create the array, we don't check for duplicates, - except in the previously sorted section if one exists, and - against the last inserted entry. This allows insertions to - be fast. */ - if (info) - { - if (sorted_count) - { - /* Try bsearch first on the sorted section. */ - key.addend =3D addend; - dyn_i =3D bsearch (&key, info, sorted_count, - sizeof (*info), addend_compare); - if (dyn_i) - return dyn_i; - } - - if (count !=3D 0) - { - /* Do a quick check for the last inserted entry. */ - dyn_i =3D info + count - 1; - if (dyn_i->addend =3D=3D addend) - return dyn_i; - } - } - - if (size =3D=3D 0) - { - /* It is the very first element. We create the array of size - 1. */ - size =3D 1; - amt =3D size * sizeof (*info); - info =3D bfd_malloc (amt); - } - else if (size <=3D count) - { - /* We double the array size every time when we reach the - size limit. */ - size +=3D size; - amt =3D size * sizeof (*info); - info =3D bfd_realloc (info, amt); - } - else - goto has_space; - - if (info =3D=3D NULL) - return NULL; - *size_p =3D size; - *info_p =3D info; - - has_space: - /* Append the new one to the array. */ - dyn_i =3D info + count; - memset (dyn_i, 0, sizeof (*dyn_i)); - dyn_i->got_offset =3D (bfd_vma) -1; - dyn_i->addend =3D addend; - - /* We increment count only since the new ones are unsorted and - may have duplicate. */ - (*count_p)++; - } - else - { - /* It is a lookup without insertion. Sort array if part of the - array isn't sorted. */ - if (count !=3D sorted_count) - { - count =3D sort_dyn_sym_info (info, count); - *count_p =3D count; - *sorted_count_p =3D count; - } - - /* Free unused memory. */ - if (size !=3D count) - { - amt =3D count * sizeof (*info); - info =3D bfd_realloc (info, amt); - *size_p =3D count; - if (info =3D=3D NULL && count !=3D 0) - /* realloc should never fail since we are reducing size here, - but if it does use the old array. */ - info =3D *info_p; - else - *info_p =3D info; - } - - if (count =3D=3D 0) - dyn_i =3D NULL; - else - { - key.addend =3D addend; - dyn_i =3D bsearch (&key, info, count, sizeof (*info), addend_compare); - } - } - - return dyn_i; -} - -static asection * -get_got (bfd *abfd, struct bfd_link_info *info, - struct elfNN_ia64_link_hash_table *ia64_info) -{ - asection *got; - bfd *dynobj; - - got =3D ia64_info->root.sgot; - if (!got) - { - flagword flags; - - dynobj =3D ia64_info->root.dynobj; - if (!dynobj) - ia64_info->root.dynobj =3D dynobj =3D abfd; - if (!_bfd_elf_create_got_section (dynobj, info)) - return NULL; - - got =3D ia64_info->root.sgot; - - /* The .got section is always aligned at 8 bytes. */ - if (!bfd_set_section_alignment (got, 3)) - return NULL; - - flags =3D bfd_section_flags (got); - if (!bfd_set_section_flags (got, SEC_SMALL_DATA | flags)) - return NULL; - } - - return got; -} - -/* Create function descriptor section (.opd). This section is called .opd - because it contains "official procedure descriptors". The "official" - refers to the fact that these descriptors are used when taking the addr= ess - of a procedure, thus ensuring a unique address for each procedure. */ - -static asection * -get_fptr (bfd *abfd, struct bfd_link_info *info, - struct elfNN_ia64_link_hash_table *ia64_info) -{ - asection *fptr; - bfd *dynobj; - - fptr =3D ia64_info->fptr_sec; - if (!fptr) - { - dynobj =3D ia64_info->root.dynobj; - if (!dynobj) - ia64_info->root.dynobj =3D dynobj =3D abfd; - - fptr =3D bfd_make_section_anyway_with_flags (dynobj, ".opd", - (SEC_ALLOC - | SEC_LOAD - | SEC_HAS_CONTENTS - | SEC_IN_MEMORY - | (bfd_link_pie (info) - ? 0 : SEC_READONLY) - | SEC_LINKER_CREATED)); - if (!fptr - || !bfd_set_section_alignment (fptr, 4)) - { - BFD_ASSERT (0); - return NULL; - } - - ia64_info->fptr_sec =3D fptr; - - if (bfd_link_pie (info)) - { - asection *fptr_rel; - fptr_rel =3D bfd_make_section_anyway_with_flags (dynobj, ".rela.opd", - (SEC_ALLOC | SEC_LOAD - | SEC_HAS_CONTENTS - | SEC_IN_MEMORY - | SEC_LINKER_CREATED - | SEC_READONLY)); - if (fptr_rel =3D=3D NULL - || !bfd_set_section_alignment (fptr_rel, LOG_SECTION_ALIGN)) - { - BFD_ASSERT (0); - return NULL; - } - - ia64_info->rel_fptr_sec =3D fptr_rel; - } - } - - return fptr; -} - -static asection * -get_pltoff (bfd *abfd, struct bfd_link_info *info ATTRIBUTE_UNUSED, - struct elfNN_ia64_link_hash_table *ia64_info) -{ - asection *pltoff; - bfd *dynobj; - - pltoff =3D ia64_info->pltoff_sec; - if (!pltoff) - { - dynobj =3D ia64_info->root.dynobj; - if (!dynobj) - ia64_info->root.dynobj =3D dynobj =3D abfd; - - pltoff =3D bfd_make_section_anyway_with_flags (dynobj, - ELF_STRING_ia64_pltoff, - (SEC_ALLOC - | SEC_LOAD - | SEC_HAS_CONTENTS - | SEC_IN_MEMORY - | SEC_SMALL_DATA - | SEC_LINKER_CREATED)); - if (!pltoff - || !bfd_set_section_alignment (pltoff, 4)) - { - BFD_ASSERT (0); - return NULL; - } - - ia64_info->pltoff_sec =3D pltoff; - } - - return pltoff; -} - -static asection * -get_reloc_section (bfd *abfd, - struct elfNN_ia64_link_hash_table *ia64_info, - asection *sec, bool create) -{ - const char *srel_name; - asection *srel; - bfd *dynobj; - - srel_name =3D (bfd_elf_string_from_elf_section - (abfd, elf_elfheader(abfd)->e_shstrndx, - _bfd_elf_single_rel_hdr (sec)->sh_name)); - if (srel_name =3D=3D NULL) - return NULL; - - dynobj =3D ia64_info->root.dynobj; - if (!dynobj) - ia64_info->root.dynobj =3D dynobj =3D abfd; - - srel =3D bfd_get_linker_section (dynobj, srel_name); - if (srel =3D=3D NULL && create) - { - srel =3D bfd_make_section_anyway_with_flags (dynobj, srel_name, - (SEC_ALLOC | SEC_LOAD - | SEC_HAS_CONTENTS - | SEC_IN_MEMORY - | SEC_LINKER_CREATED - | SEC_READONLY)); - if (srel =3D=3D NULL - || !bfd_set_section_alignment (srel, LOG_SECTION_ALIGN)) - return NULL; - } - - return srel; -} - -static bool -count_dyn_reloc (bfd *abfd, struct elfNN_ia64_dyn_sym_info *dyn_i, - asection *srel, int type, bool reltext) -{ - struct elfNN_ia64_dyn_reloc_entry *rent; - - for (rent =3D dyn_i->reloc_entries; rent; rent =3D rent->next) - if (rent->srel =3D=3D srel && rent->type =3D=3D type) - break; - - if (!rent) - { - rent =3D ((struct elfNN_ia64_dyn_reloc_entry *) - bfd_alloc (abfd, (bfd_size_type) sizeof (*rent))); - if (!rent) - return false; - - rent->next =3D dyn_i->reloc_entries; - rent->srel =3D srel; - rent->type =3D type; - rent->count =3D 0; - dyn_i->reloc_entries =3D rent; - } - rent->reltext =3D reltext; - rent->count++; - - return true; -} - -static bool -elfNN_ia64_check_relocs (bfd *abfd, struct bfd_link_info *info, - asection *sec, - const Elf_Internal_Rela *relocs) -{ - struct elfNN_ia64_link_hash_table *ia64_info; - const Elf_Internal_Rela *relend; - Elf_Internal_Shdr *symtab_hdr; - const Elf_Internal_Rela *rel; - asection *got, *fptr, *srel, *pltoff; - enum { - NEED_GOT =3D 1, - NEED_GOTX =3D 2, - NEED_FPTR =3D 4, - NEED_PLTOFF =3D 8, - NEED_MIN_PLT =3D 16, - NEED_FULL_PLT =3D 32, - NEED_DYNREL =3D 64, - NEED_LTOFF_FPTR =3D 128, - NEED_TPREL =3D 256, - NEED_DTPMOD =3D 512, - NEED_DTPREL =3D 1024 - }; - int need_entry; - struct elf_link_hash_entry *h; - unsigned long r_symndx; - bool maybe_dynamic; - - if (bfd_link_relocatable (info)) - return true; - - symtab_hdr =3D &elf_tdata (abfd)->symtab_hdr; - ia64_info =3D elfNN_ia64_hash_table (info); - if (ia64_info =3D=3D NULL) - return false; - - got =3D fptr =3D srel =3D pltoff =3D NULL; - - relend =3D relocs + sec->reloc_count; - - /* We scan relocations first to create dynamic relocation arrays. We - modified get_dyn_sym_info to allow fast insertion and support fast - lookup in the next loop. */ - for (rel =3D relocs; rel < relend; ++rel) - { - r_symndx =3D ELFNN_R_SYM (rel->r_info); - if (r_symndx >=3D symtab_hdr->sh_info) - { - long indx =3D r_symndx - symtab_hdr->sh_info; - h =3D elf_sym_hashes (abfd)[indx]; - while (h->root.type =3D=3D bfd_link_hash_indirect - || h->root.type =3D=3D bfd_link_hash_warning) - h =3D (struct elf_link_hash_entry *) h->root.u.i.link; - } - else - h =3D NULL; - - /* We can only get preliminary data on whether a symbol is - locally or externally defined, as not all of the input files - have yet been processed. Do something with what we know, as - this may help reduce memory usage and processing time later. */ - maybe_dynamic =3D (h && ((!bfd_link_executable (info) - && (!SYMBOLIC_BIND (info, h) - || info->unresolved_syms_in_shared_libs =3D=3D RM_IGNORE)) - || !h->def_regular - || h->root.type =3D=3D bfd_link_hash_defweak)); - - need_entry =3D 0; - switch (ELFNN_R_TYPE (rel->r_info)) - { - case R_IA64_TPREL64MSB: - case R_IA64_TPREL64LSB: - if (bfd_link_pic (info) || maybe_dynamic) - need_entry =3D NEED_DYNREL; - break; - - case R_IA64_LTOFF_TPREL22: - need_entry =3D NEED_TPREL; - if (bfd_link_pic (info)) - info->flags |=3D DF_STATIC_TLS; - break; - - case R_IA64_DTPREL32MSB: - case R_IA64_DTPREL32LSB: - case R_IA64_DTPREL64MSB: - case R_IA64_DTPREL64LSB: - if (bfd_link_pic (info) || maybe_dynamic) - need_entry =3D NEED_DYNREL; - break; - - case R_IA64_LTOFF_DTPREL22: - need_entry =3D NEED_DTPREL; - break; - - case R_IA64_DTPMOD64MSB: - case R_IA64_DTPMOD64LSB: - if (bfd_link_pic (info) || maybe_dynamic) - need_entry =3D NEED_DYNREL; - break; - - case R_IA64_LTOFF_DTPMOD22: - need_entry =3D NEED_DTPMOD; - break; - - case R_IA64_LTOFF_FPTR22: - case R_IA64_LTOFF_FPTR64I: - case R_IA64_LTOFF_FPTR32MSB: - case R_IA64_LTOFF_FPTR32LSB: - case R_IA64_LTOFF_FPTR64MSB: - case R_IA64_LTOFF_FPTR64LSB: - need_entry =3D NEED_FPTR | NEED_GOT | NEED_LTOFF_FPTR; - break; - - case R_IA64_FPTR64I: - case R_IA64_FPTR32MSB: - case R_IA64_FPTR32LSB: - case R_IA64_FPTR64MSB: - case R_IA64_FPTR64LSB: - if (bfd_link_pic (info) || h) - need_entry =3D NEED_FPTR | NEED_DYNREL; - else - need_entry =3D NEED_FPTR; - break; - - case R_IA64_LTOFF22: - case R_IA64_LTOFF64I: - need_entry =3D NEED_GOT; - break; - - case R_IA64_LTOFF22X: - need_entry =3D NEED_GOTX; - break; - - case R_IA64_PLTOFF22: - case R_IA64_PLTOFF64I: - case R_IA64_PLTOFF64MSB: - case R_IA64_PLTOFF64LSB: - need_entry =3D NEED_PLTOFF; - if (h) - { - if (maybe_dynamic) - need_entry |=3D NEED_MIN_PLT; - } - else - { - (*info->callbacks->warning) - (info, _("@pltoff reloc against local symbol"), 0, - abfd, 0, (bfd_vma) 0); - } - break; - - case R_IA64_PCREL21B: - case R_IA64_PCREL60B: - /* Depending on where this symbol is defined, we may or may not - need a full plt entry. Only skip if we know we'll not need - the entry -- static or symbolic, and the symbol definition - has already been seen. */ - if (maybe_dynamic && rel->r_addend =3D=3D 0) - need_entry =3D NEED_FULL_PLT; - break; - - case R_IA64_IMM14: - case R_IA64_IMM22: - case R_IA64_IMM64: - case R_IA64_DIR32MSB: - case R_IA64_DIR32LSB: - case R_IA64_DIR64MSB: - case R_IA64_DIR64LSB: - /* Shared objects will always need at least a REL relocation. */ - if (bfd_link_pic (info) || maybe_dynamic) - need_entry =3D NEED_DYNREL; - break; - - case R_IA64_IPLTMSB: - case R_IA64_IPLTLSB: - /* Shared objects will always need at least a REL relocation. */ - if (bfd_link_pic (info) || maybe_dynamic) - need_entry =3D NEED_DYNREL; - break; - - case R_IA64_PCREL22: - case R_IA64_PCREL64I: - case R_IA64_PCREL32MSB: - case R_IA64_PCREL32LSB: - case R_IA64_PCREL64MSB: - case R_IA64_PCREL64LSB: - if (maybe_dynamic) - need_entry =3D NEED_DYNREL; - break; - } - - if (!need_entry) - continue; - - if ((need_entry & NEED_FPTR) !=3D 0 - && rel->r_addend) - { - (*info->callbacks->warning) - (info, _("non-zero addend in @fptr reloc"), 0, - abfd, 0, (bfd_vma) 0); - } - - if (get_dyn_sym_info (ia64_info, h, abfd, rel, true) =3D=3D NULL) - return false; - } - - /* Now, we only do lookup without insertion, which is very fast - with the modified get_dyn_sym_info. */ - for (rel =3D relocs; rel < relend; ++rel) - { - struct elfNN_ia64_dyn_sym_info *dyn_i; - int dynrel_type =3D R_IA64_NONE; - - r_symndx =3D ELFNN_R_SYM (rel->r_info); - if (r_symndx >=3D symtab_hdr->sh_info) - { - /* We're dealing with a global symbol -- find its hash entry - and mark it as being referenced. */ - long indx =3D r_symndx - symtab_hdr->sh_info; - h =3D elf_sym_hashes (abfd)[indx]; - while (h->root.type =3D=3D bfd_link_hash_indirect - || h->root.type =3D=3D bfd_link_hash_warning) - h =3D (struct elf_link_hash_entry *) h->root.u.i.link; - - /* PR15323, ref flags aren't set for references in the same - object. */ - h->ref_regular =3D 1; - } - else - h =3D NULL; - - /* We can only get preliminary data on whether a symbol is - locally or externally defined, as not all of the input files - have yet been processed. Do something with what we know, as - this may help reduce memory usage and processing time later. */ - maybe_dynamic =3D (h && ((!bfd_link_executable (info) - && (!SYMBOLIC_BIND (info, h) - || info->unresolved_syms_in_shared_libs =3D=3D RM_IGNORE)) - || !h->def_regular - || h->root.type =3D=3D bfd_link_hash_defweak)); - - need_entry =3D 0; - switch (ELFNN_R_TYPE (rel->r_info)) - { - case R_IA64_TPREL64MSB: - case R_IA64_TPREL64LSB: - if (bfd_link_pic (info) || maybe_dynamic) - need_entry =3D NEED_DYNREL; - dynrel_type =3D R_IA64_TPREL64LSB; - if (bfd_link_pic (info)) - info->flags |=3D DF_STATIC_TLS; - break; - - case R_IA64_LTOFF_TPREL22: - need_entry =3D NEED_TPREL; - if (bfd_link_pic (info)) - info->flags |=3D DF_STATIC_TLS; - break; - - case R_IA64_DTPREL32MSB: - case R_IA64_DTPREL32LSB: - case R_IA64_DTPREL64MSB: - case R_IA64_DTPREL64LSB: - if (bfd_link_pic (info) || maybe_dynamic) - need_entry =3D NEED_DYNREL; - dynrel_type =3D R_IA64_DTPRELNNLSB; - break; - - case R_IA64_LTOFF_DTPREL22: - need_entry =3D NEED_DTPREL; - break; - - case R_IA64_DTPMOD64MSB: - case R_IA64_DTPMOD64LSB: - if (bfd_link_pic (info) || maybe_dynamic) - need_entry =3D NEED_DYNREL; - dynrel_type =3D R_IA64_DTPMOD64LSB; - break; - - case R_IA64_LTOFF_DTPMOD22: - need_entry =3D NEED_DTPMOD; - break; - - case R_IA64_LTOFF_FPTR22: - case R_IA64_LTOFF_FPTR64I: - case R_IA64_LTOFF_FPTR32MSB: - case R_IA64_LTOFF_FPTR32LSB: - case R_IA64_LTOFF_FPTR64MSB: - case R_IA64_LTOFF_FPTR64LSB: - need_entry =3D NEED_FPTR | NEED_GOT | NEED_LTOFF_FPTR; - break; - - case R_IA64_FPTR64I: - case R_IA64_FPTR32MSB: - case R_IA64_FPTR32LSB: - case R_IA64_FPTR64MSB: - case R_IA64_FPTR64LSB: - if (bfd_link_pic (info) || h) - need_entry =3D NEED_FPTR | NEED_DYNREL; - else - need_entry =3D NEED_FPTR; - dynrel_type =3D R_IA64_FPTRNNLSB; - break; - - case R_IA64_LTOFF22: - case R_IA64_LTOFF64I: - need_entry =3D NEED_GOT; - break; - - case R_IA64_LTOFF22X: - need_entry =3D NEED_GOTX; - break; - - case R_IA64_PLTOFF22: - case R_IA64_PLTOFF64I: - case R_IA64_PLTOFF64MSB: - case R_IA64_PLTOFF64LSB: - need_entry =3D NEED_PLTOFF; - if (h) - { - if (maybe_dynamic) - need_entry |=3D NEED_MIN_PLT; - } - break; - - case R_IA64_PCREL21B: - case R_IA64_PCREL60B: - /* Depending on where this symbol is defined, we may or may not - need a full plt entry. Only skip if we know we'll not need - the entry -- static or symbolic, and the symbol definition - has already been seen. */ - if (maybe_dynamic && rel->r_addend =3D=3D 0) - need_entry =3D NEED_FULL_PLT; - break; - - case R_IA64_IMM14: - case R_IA64_IMM22: - case R_IA64_IMM64: - case R_IA64_DIR32MSB: - case R_IA64_DIR32LSB: - case R_IA64_DIR64MSB: - case R_IA64_DIR64LSB: - /* Shared objects will always need at least a REL relocation. */ - if (bfd_link_pic (info) || maybe_dynamic) - need_entry =3D NEED_DYNREL; - dynrel_type =3D R_IA64_DIRNNLSB; - break; - - case R_IA64_IPLTMSB: - case R_IA64_IPLTLSB: - /* Shared objects will always need at least a REL relocation. */ - if (bfd_link_pic (info) || maybe_dynamic) - need_entry =3D NEED_DYNREL; - dynrel_type =3D R_IA64_IPLTLSB; - break; - - case R_IA64_PCREL22: - case R_IA64_PCREL64I: - case R_IA64_PCREL32MSB: - case R_IA64_PCREL32LSB: - case R_IA64_PCREL64MSB: - case R_IA64_PCREL64LSB: - if (maybe_dynamic) - need_entry =3D NEED_DYNREL; - dynrel_type =3D R_IA64_PCRELNNLSB; - break; - } - - if (!need_entry) - continue; - - dyn_i =3D get_dyn_sym_info (ia64_info, h, abfd, rel, false); - - /* Record whether or not this is a local symbol. */ - dyn_i->h =3D h; - - /* Create what's needed. */ - if (need_entry & (NEED_GOT | NEED_GOTX | NEED_TPREL - | NEED_DTPMOD | NEED_DTPREL)) - { - if (!got) - { - got =3D get_got (abfd, info, ia64_info); - if (!got) - return false; - } - if (need_entry & NEED_GOT) - dyn_i->want_got =3D 1; - if (need_entry & NEED_GOTX) - dyn_i->want_gotx =3D 1; - if (need_entry & NEED_TPREL) - dyn_i->want_tprel =3D 1; - if (need_entry & NEED_DTPMOD) - dyn_i->want_dtpmod =3D 1; - if (need_entry & NEED_DTPREL) - dyn_i->want_dtprel =3D 1; - } - if (need_entry & NEED_FPTR) - { - if (!fptr) - { - fptr =3D get_fptr (abfd, info, ia64_info); - if (!fptr) - return false; - } - - /* FPTRs for shared libraries are allocated by the dynamic - linker. Make sure this local symbol will appear in the - dynamic symbol table. */ - if (!h && bfd_link_pic (info)) - { - if (! (bfd_elf_link_record_local_dynamic_symbol - (info, abfd, (long) r_symndx))) - return false; - } - - dyn_i->want_fptr =3D 1; - } - if (need_entry & NEED_LTOFF_FPTR) - dyn_i->want_ltoff_fptr =3D 1; - if (need_entry & (NEED_MIN_PLT | NEED_FULL_PLT)) - { - if (!ia64_info->root.dynobj) - ia64_info->root.dynobj =3D abfd; - h->needs_plt =3D 1; - dyn_i->want_plt =3D 1; - } - if (need_entry & NEED_FULL_PLT) - dyn_i->want_plt2 =3D 1; - if (need_entry & NEED_PLTOFF) - { - /* This is needed here, in case @pltoff is used in a non-shared - link. */ - if (!pltoff) - { - pltoff =3D get_pltoff (abfd, info, ia64_info); - if (!pltoff) - return false; - } - - dyn_i->want_pltoff =3D 1; - } - if ((need_entry & NEED_DYNREL) && (sec->flags & SEC_ALLOC)) - { - if (!srel) - { - srel =3D get_reloc_section (abfd, ia64_info, sec, true); - if (!srel) - return false; - } - if (!count_dyn_reloc (abfd, dyn_i, srel, dynrel_type, - (sec->flags & SEC_READONLY) !=3D 0)) - return false; - } - } - - return true; -} - -/* For cleanliness, and potentially faster dynamic loading, allocate - external GOT entries first. */ - -static bool -allocate_global_data_got (struct elfNN_ia64_dyn_sym_info *dyn_i, - void * data) -{ - struct elfNN_ia64_allocate_data *x =3D (struct elfNN_ia64_allocate_data = *)data; - - if ((dyn_i->want_got || dyn_i->want_gotx) - && ! dyn_i->want_fptr - && elfNN_ia64_dynamic_symbol_p (dyn_i->h, x->info, 0)) - { - dyn_i->got_offset =3D x->ofs; - x->ofs +=3D 8; - } - if (dyn_i->want_tprel) - { - dyn_i->tprel_offset =3D x->ofs; - x->ofs +=3D 8; - } - if (dyn_i->want_dtpmod) - { - if (elfNN_ia64_dynamic_symbol_p (dyn_i->h, x->info, 0)) - { - dyn_i->dtpmod_offset =3D x->ofs; - x->ofs +=3D 8; - } - else - { - struct elfNN_ia64_link_hash_table *ia64_info; - - ia64_info =3D elfNN_ia64_hash_table (x->info); - if (ia64_info =3D=3D NULL) - return false; - - if (ia64_info->self_dtpmod_offset =3D=3D (bfd_vma) -1) - { - ia64_info->self_dtpmod_offset =3D x->ofs; - x->ofs +=3D 8; - } - dyn_i->dtpmod_offset =3D ia64_info->self_dtpmod_offset; - } - } - if (dyn_i->want_dtprel) - { - dyn_i->dtprel_offset =3D x->ofs; - x->ofs +=3D 8; - } - return true; -} - -/* Next, allocate all the GOT entries used by LTOFF_FPTR relocs. */ - -static bool -allocate_global_fptr_got (struct elfNN_ia64_dyn_sym_info *dyn_i, - void * data) -{ - struct elfNN_ia64_allocate_data *x =3D (struct elfNN_ia64_allocate_data = *)data; - - if (dyn_i->want_got - && dyn_i->want_fptr - && elfNN_ia64_dynamic_symbol_p (dyn_i->h, x->info, R_IA64_FPTRNNLSB)) - { - dyn_i->got_offset =3D x->ofs; - x->ofs +=3D 8; - } - return true; -} - -/* Lastly, allocate all the GOT entries for local data. */ - -static bool -allocate_local_got (struct elfNN_ia64_dyn_sym_info *dyn_i, - void * data) -{ - struct elfNN_ia64_allocate_data *x =3D (struct elfNN_ia64_allocate_data = *)data; - - if ((dyn_i->want_got || dyn_i->want_gotx) - && !elfNN_ia64_dynamic_symbol_p (dyn_i->h, x->info, 0)) - { - dyn_i->got_offset =3D x->ofs; - x->ofs +=3D 8; - } - return true; -} - -/* Search for the index of a global symbol in it's defining object file. = */ - -static long -global_sym_index (struct elf_link_hash_entry *h) -{ - struct elf_link_hash_entry **p; - bfd *obj; - - BFD_ASSERT (h->root.type =3D=3D bfd_link_hash_defined - || h->root.type =3D=3D bfd_link_hash_defweak); - - obj =3D h->root.u.def.section->owner; - for (p =3D elf_sym_hashes (obj); *p !=3D h; ++p) - continue; - - return p - elf_sym_hashes (obj) + elf_tdata (obj)->symtab_hdr.sh_info; -} - -/* Allocate function descriptors. We can do these for every function - in a main executable that is not exported. */ - -static bool -allocate_fptr (struct elfNN_ia64_dyn_sym_info *dyn_i, void * data) -{ - struct elfNN_ia64_allocate_data *x =3D (struct elfNN_ia64_allocate_data = *)data; - - if (dyn_i->want_fptr) - { - struct elf_link_hash_entry *h =3D dyn_i->h; - - if (h) - while (h->root.type =3D=3D bfd_link_hash_indirect - || h->root.type =3D=3D bfd_link_hash_warning) - h =3D (struct elf_link_hash_entry *) h->root.u.i.link; - - if (!bfd_link_executable (x->info) - && (!h - || ELF_ST_VISIBILITY (h->other) =3D=3D STV_DEFAULT - || (h->root.type !=3D bfd_link_hash_undefweak - && h->root.type !=3D bfd_link_hash_undefined))) - { - if (h && h->dynindx =3D=3D -1) - { - BFD_ASSERT ((h->root.type =3D=3D bfd_link_hash_defined) - || (h->root.type =3D=3D bfd_link_hash_defweak)); - - if (!bfd_elf_link_record_local_dynamic_symbol - (x->info, h->root.u.def.section->owner, - global_sym_index (h))) - return false; - } - - dyn_i->want_fptr =3D 0; - } - else if (h =3D=3D NULL || h->dynindx =3D=3D -1) - { - dyn_i->fptr_offset =3D x->ofs; - x->ofs +=3D 16; - } - else - dyn_i->want_fptr =3D 0; - } - return true; -} - -/* Allocate all the minimal PLT entries. */ - -static bool -allocate_plt_entries (struct elfNN_ia64_dyn_sym_info *dyn_i, - void * data) -{ - struct elfNN_ia64_allocate_data *x =3D (struct elfNN_ia64_allocate_data = *)data; - - if (dyn_i->want_plt) - { - struct elf_link_hash_entry *h =3D dyn_i->h; - - if (h) - while (h->root.type =3D=3D bfd_link_hash_indirect - || h->root.type =3D=3D bfd_link_hash_warning) - h =3D (struct elf_link_hash_entry *) h->root.u.i.link; - - /* ??? Versioned symbols seem to lose NEEDS_PLT. */ - if (elfNN_ia64_dynamic_symbol_p (h, x->info, 0)) - { - bfd_size_type offset =3D x->ofs; - if (offset =3D=3D 0) - offset =3D PLT_HEADER_SIZE; - dyn_i->plt_offset =3D offset; - x->ofs =3D offset + PLT_MIN_ENTRY_SIZE; - - dyn_i->want_pltoff =3D 1; - } - else - { - dyn_i->want_plt =3D 0; - dyn_i->want_plt2 =3D 0; - } - } - return true; -} - -/* Allocate all the full PLT entries. */ - -static bool -allocate_plt2_entries (struct elfNN_ia64_dyn_sym_info *dyn_i, - void * data) -{ - struct elfNN_ia64_allocate_data *x =3D (struct elfNN_ia64_allocate_data = *)data; - - if (dyn_i->want_plt2) - { - struct elf_link_hash_entry *h =3D dyn_i->h; - bfd_size_type ofs =3D x->ofs; - - dyn_i->plt2_offset =3D ofs; - x->ofs =3D ofs + PLT_FULL_ENTRY_SIZE; - - while (h->root.type =3D=3D bfd_link_hash_indirect - || h->root.type =3D=3D bfd_link_hash_warning) - h =3D (struct elf_link_hash_entry *) h->root.u.i.link; - dyn_i->h->plt.offset =3D ofs; - } - return true; -} - -/* Allocate all the PLTOFF entries requested by relocations and - plt entries. We can't share space with allocated FPTR entries, - because the latter are not necessarily addressable by the GP. - ??? Relaxation might be able to determine that they are. */ - -static bool -allocate_pltoff_entries (struct elfNN_ia64_dyn_sym_info *dyn_i, - void * data) -{ - struct elfNN_ia64_allocate_data *x =3D (struct elfNN_ia64_allocate_data = *)data; - - if (dyn_i->want_pltoff) - { - dyn_i->pltoff_offset =3D x->ofs; - x->ofs +=3D 16; - } - return true; -} - -/* Allocate dynamic relocations for those symbols that turned out - to be dynamic. */ - -static bool -allocate_dynrel_entries (struct elfNN_ia64_dyn_sym_info *dyn_i, - void * data) -{ - struct elfNN_ia64_allocate_data *x =3D (struct elfNN_ia64_allocate_data = *)data; - struct elfNN_ia64_link_hash_table *ia64_info; - struct elfNN_ia64_dyn_reloc_entry *rent; - bool dynamic_symbol, shared, resolved_zero; - - ia64_info =3D elfNN_ia64_hash_table (x->info); - if (ia64_info =3D=3D NULL) - return false; - - /* Note that this can't be used in relation to FPTR relocs below. */ - dynamic_symbol =3D elfNN_ia64_dynamic_symbol_p (dyn_i->h, x->info, 0); - - shared =3D bfd_link_pic (x->info); - resolved_zero =3D (dyn_i->h - && ELF_ST_VISIBILITY (dyn_i->h->other) - && dyn_i->h->root.type =3D=3D bfd_link_hash_undefweak); - - /* Take care of the GOT and PLT relocations. */ - - if ((!resolved_zero - && (dynamic_symbol || shared) - && (dyn_i->want_got || dyn_i->want_gotx)) - || (dyn_i->want_ltoff_fptr - && dyn_i->h - && dyn_i->h->dynindx !=3D -1)) - { - if (!dyn_i->want_ltoff_fptr - || !bfd_link_pie (x->info) - || dyn_i->h =3D=3D NULL - || dyn_i->h->root.type !=3D bfd_link_hash_undefweak) - ia64_info->root.srelgot->size +=3D sizeof (ElfNN_External_Rela); - } - if ((dynamic_symbol || shared) && dyn_i->want_tprel) - ia64_info->root.srelgot->size +=3D sizeof (ElfNN_External_Rela); - if (dynamic_symbol && dyn_i->want_dtpmod) - ia64_info->root.srelgot->size +=3D sizeof (ElfNN_External_Rela); - if (dynamic_symbol && dyn_i->want_dtprel) - ia64_info->root.srelgot->size +=3D sizeof (ElfNN_External_Rela); - - if (x->only_got) - return true; - - if (ia64_info->rel_fptr_sec && dyn_i->want_fptr) - { - if (dyn_i->h =3D=3D NULL || dyn_i->h->root.type !=3D bfd_link_hash_u= ndefweak) - ia64_info->rel_fptr_sec->size +=3D sizeof (ElfNN_External_Rela); - } - - if (!resolved_zero && dyn_i->want_pltoff) - { - bfd_size_type t =3D 0; - - /* Dynamic symbols get one IPLT relocation. Local symbols in - shared libraries get two REL relocations. Local symbols in - main applications get nothing. */ - if (dynamic_symbol) - t =3D sizeof (ElfNN_External_Rela); - else if (shared) - t =3D 2 * sizeof (ElfNN_External_Rela); - - ia64_info->rel_pltoff_sec->size +=3D t; - } - - /* Take care of the normal data relocations. */ - - for (rent =3D dyn_i->reloc_entries; rent; rent =3D rent->next) - { - int count =3D rent->count; - - switch (rent->type) - { - case R_IA64_FPTR32LSB: - case R_IA64_FPTR64LSB: - /* Allocate one iff !want_fptr and not PIE, which by this point - will be true only if we're actually allocating one statically - in the main executable. Position independent executables - need a relative reloc. */ - if (dyn_i->want_fptr && !bfd_link_pie (x->info)) - continue; - break; - case R_IA64_PCREL32LSB: - case R_IA64_PCREL64LSB: - if (!dynamic_symbol) - continue; - break; - case R_IA64_DIR32LSB: - case R_IA64_DIR64LSB: - if (!dynamic_symbol && !shared) - continue; - break; - case R_IA64_IPLTLSB: - if (!dynamic_symbol && !shared) - continue; - /* Use two REL relocations for IPLT relocations - against local symbols. */ - if (!dynamic_symbol) - count *=3D 2; - break; - case R_IA64_DTPREL32LSB: - case R_IA64_TPREL64LSB: - case R_IA64_DTPREL64LSB: - case R_IA64_DTPMOD64LSB: - break; - default: - abort (); - } - if (rent->reltext) - x->info->flags |=3D DF_TEXTREL; - rent->srel->size +=3D sizeof (ElfNN_External_Rela) * count; - } - - return true; -} - -static bool -elfNN_ia64_adjust_dynamic_symbol (struct bfd_link_info *info ATTRIBUTE_UNU= SED, - struct elf_link_hash_entry *h) -{ - /* ??? Undefined symbols with PLT entries should be re-defined - to be the PLT entry. */ - - /* If this is a weak symbol, and there is a real definition, the - processor independent code will have arranged for us to see the - real definition first, and we can just use the same value. */ - if (h->is_weakalias) - { - struct elf_link_hash_entry *def =3D weakdef (h); - BFD_ASSERT (def->root.type =3D=3D bfd_link_hash_defined); - h->root.u.def.section =3D def->root.u.def.section; - h->root.u.def.value =3D def->root.u.def.value; - return true; - } - - /* If this is a reference to a symbol defined by a dynamic object which - is not a function, we might allocate the symbol in our .dynbss section - and allocate a COPY dynamic relocation. - - But IA-64 code is canonically PIC, so as a rule we can avoid this sort - of hackery. */ - - return true; -} - -static bool -elfNN_ia64_late_size_sections (bfd *output_bfd ATTRIBUTE_UNUSED, - struct bfd_link_info *info) -{ - struct elfNN_ia64_allocate_data data; - struct elfNN_ia64_link_hash_table *ia64_info; - asection *sec; - bfd *dynobj; - - ia64_info =3D elfNN_ia64_hash_table (info); - if (ia64_info =3D=3D NULL) - return false; - dynobj =3D ia64_info->root.dynobj; - if (dynobj =3D=3D NULL) - return true; - ia64_info->self_dtpmod_offset =3D (bfd_vma) -1; - data.info =3D info; - - /* Set the contents of the .interp section to the interpreter. */ - if (ia64_info->root.dynamic_sections_created - && bfd_link_executable (info) && !info->nointerp) - { - sec =3D bfd_get_linker_section (dynobj, ".interp"); - BFD_ASSERT (sec !=3D NULL); - sec->contents =3D (bfd_byte *) ELF_DYNAMIC_INTERPRETER; - sec->size =3D strlen (ELF_DYNAMIC_INTERPRETER) + 1; - } - - /* Allocate the GOT entries. */ - - if (ia64_info->root.sgot) - { - data.ofs =3D 0; - elfNN_ia64_dyn_sym_traverse (ia64_info, allocate_global_data_got, &d= ata); - elfNN_ia64_dyn_sym_traverse (ia64_info, allocate_global_fptr_got, &d= ata); - elfNN_ia64_dyn_sym_traverse (ia64_info, allocate_local_got, &data); - ia64_info->root.sgot->size =3D data.ofs; - } - - /* Allocate the FPTR entries. */ - - if (ia64_info->fptr_sec) - { - data.ofs =3D 0; - elfNN_ia64_dyn_sym_traverse (ia64_info, allocate_fptr, &data); - ia64_info->fptr_sec->size =3D data.ofs; - } - - /* Now that we've seen all of the input files, we can decide which - symbols need plt entries. Allocate the minimal PLT entries first. - We do this even though dynamic_sections_created may be FALSE, because - this has the side-effect of clearing want_plt and want_plt2. */ - - data.ofs =3D 0; - elfNN_ia64_dyn_sym_traverse (ia64_info, allocate_plt_entries, &data); - - ia64_info->minplt_entries =3D 0; - if (data.ofs) - { - ia64_info->minplt_entries - =3D (data.ofs - PLT_HEADER_SIZE) / PLT_MIN_ENTRY_SIZE; - } - - /* Align the pointer for the plt2 entries. */ - data.ofs =3D (data.ofs + 31) & (bfd_vma) -32; - - elfNN_ia64_dyn_sym_traverse (ia64_info, allocate_plt2_entries, &data); - if (data.ofs !=3D 0 || ia64_info->root.dynamic_sections_created) - { - /* FIXME: we always reserve the memory for dynamic linker even if - there are no PLT entries since dynamic linker may assume the - reserved memory always exists. */ - - BFD_ASSERT (ia64_info->root.dynamic_sections_created); - - ia64_info->root.splt->size =3D data.ofs; - - /* If we've got a .plt, we need some extra memory for the dynamic - linker. We stuff these in .got.plt. */ - ia64_info->root.sgotplt->size =3D 8 * PLT_RESERVED_WORDS; - } - - /* Allocate the PLTOFF entries. */ - - if (ia64_info->pltoff_sec) - { - data.ofs =3D 0; - elfNN_ia64_dyn_sym_traverse (ia64_info, allocate_pltoff_entries, &da= ta); - ia64_info->pltoff_sec->size =3D data.ofs; - } - - if (ia64_info->root.dynamic_sections_created) - { - /* Allocate space for the dynamic relocations that turned out to be - required. */ - - if (bfd_link_pic (info) && ia64_info->self_dtpmod_offset !=3D (bfd_v= ma) -1) - ia64_info->root.srelgot->size +=3D sizeof (ElfNN_External_Rela); - data.only_got =3D false; - elfNN_ia64_dyn_sym_traverse (ia64_info, allocate_dynrel_entries, &da= ta); - } - - /* We have now determined the sizes of the various dynamic sections. - Allocate memory for them. */ - for (sec =3D dynobj->sections; sec !=3D NULL; sec =3D sec->next) - { - bool strip; - - if (!(sec->flags & SEC_LINKER_CREATED)) - continue; - - /* If we don't need this section, strip it from the output file. - There were several sections primarily related to dynamic - linking that must be create before the linker maps input - sections to output sections. The linker does that before - bfd_elf_size_dynamic_sections is called, and it is that - function which decides whether anything needs to go into - these sections. */ - - strip =3D (sec->size =3D=3D 0); - - if (sec =3D=3D ia64_info->root.sgot) - strip =3D false; - else if (sec =3D=3D ia64_info->root.srelgot) - { - if (strip) - ia64_info->root.srelgot =3D NULL; - else - /* We use the reloc_count field as a counter if we need to - copy relocs into the output file. */ - sec->reloc_count =3D 0; - } - else if (sec =3D=3D ia64_info->fptr_sec) - { - if (strip) - ia64_info->fptr_sec =3D NULL; - } - else if (sec =3D=3D ia64_info->rel_fptr_sec) - { - if (strip) - ia64_info->rel_fptr_sec =3D NULL; - else - /* We use the reloc_count field as a counter if we need to - copy relocs into the output file. */ - sec->reloc_count =3D 0; - } - else if (sec =3D=3D ia64_info->root.splt) - { - if (strip) - ia64_info->root.splt =3D NULL; - } - else if (sec =3D=3D ia64_info->pltoff_sec) - { - if (strip) - ia64_info->pltoff_sec =3D NULL; - } - else if (sec =3D=3D ia64_info->rel_pltoff_sec) - { - if (strip) - ia64_info->rel_pltoff_sec =3D NULL; - else - { - ia64_info->root.dt_jmprel_required =3D true; - /* We use the reloc_count field as a counter if we need to - copy relocs into the output file. */ - sec->reloc_count =3D 0; - } - } - else - { - const char *name; - - /* It's OK to base decisions on the section name, because none - of the dynobj section names depend upon the input files. */ - name =3D bfd_section_name (sec); - - if (strcmp (name, ".got.plt") =3D=3D 0) - strip =3D false; - else if (startswith (name, ".rel")) - { - if (!strip) - { - /* We use the reloc_count field as a counter if we need to - copy relocs into the output file. */ - sec->reloc_count =3D 0; - } - } - else - continue; - } - - if (strip) - sec->flags |=3D SEC_EXCLUDE; - else - { - /* Allocate memory for the section contents. */ - sec->contents =3D (bfd_byte *) bfd_zalloc (dynobj, sec->size); - if (sec->contents =3D=3D NULL && sec->size !=3D 0) - return false; - } - } - - if (ia64_info->root.dynamic_sections_created) - { - /* Add some entries to the .dynamic section. We fill in the values - later (in finish_dynamic_sections) but we must add the entries now - so that we get the correct size for the .dynamic section. */ - -#define add_dynamic_entry(TAG, VAL) \ - _bfd_elf_add_dynamic_entry (info, TAG, VAL) - - if (!_bfd_elf_add_dynamic_tags (output_bfd, info, true)) - return false; - - if (!add_dynamic_entry (DT_IA_64_PLT_RESERVE, 0)) - return false; - } - - /* ??? Perhaps force __gp local. */ - - return true; -} - -static void -elfNN_ia64_install_dyn_reloc (bfd *abfd, struct bfd_link_info *info, - asection *sec, asection *srel, - bfd_vma offset, unsigned int type, - long dynindx, bfd_vma addend) -{ - Elf_Internal_Rela outrel; - bfd_byte *loc; - - BFD_ASSERT (dynindx !=3D -1); - outrel.r_info =3D ELFNN_R_INFO (dynindx, type); - outrel.r_addend =3D addend; - outrel.r_offset =3D _bfd_elf_section_offset (abfd, info, sec, offset); - if (outrel.r_offset >=3D (bfd_vma) -2) - { - /* Run for the hills. We shouldn't be outputting a relocation - for this. So do what everyone else does and output a no-op. */ - outrel.r_info =3D ELFNN_R_INFO (0, R_IA64_NONE); - outrel.r_addend =3D 0; - outrel.r_offset =3D 0; - } - else - outrel.r_offset +=3D sec->output_section->vma + sec->output_offset; - - loc =3D srel->contents; - loc +=3D srel->reloc_count++ * sizeof (ElfNN_External_Rela); - bfd_elfNN_swap_reloca_out (abfd, &outrel, loc); - BFD_ASSERT (sizeof (ElfNN_External_Rela) * srel->reloc_count <=3D srel->= size); -} - -/* Store an entry for target address TARGET_ADDR in the linkage table - and return the gp-relative address of the linkage table entry. */ - -static bfd_vma -set_got_entry (bfd *abfd, struct bfd_link_info *info, - struct elfNN_ia64_dyn_sym_info *dyn_i, - long dynindx, bfd_vma addend, bfd_vma value, - unsigned int dyn_r_type) -{ - struct elfNN_ia64_link_hash_table *ia64_info; - asection *got_sec; - bool done; - bfd_vma got_offset; - - ia64_info =3D elfNN_ia64_hash_table (info); - if (ia64_info =3D=3D NULL) - return 0; - - got_sec =3D ia64_info->root.sgot; - - switch (dyn_r_type) - { - case R_IA64_TPREL64LSB: - done =3D dyn_i->tprel_done; - dyn_i->tprel_done =3D true; - got_offset =3D dyn_i->tprel_offset; - break; - case R_IA64_DTPMOD64LSB: - if (dyn_i->dtpmod_offset !=3D ia64_info->self_dtpmod_offset) - { - done =3D dyn_i->dtpmod_done; - dyn_i->dtpmod_done =3D true; - } - else - { - done =3D ia64_info->self_dtpmod_done; - ia64_info->self_dtpmod_done =3D true; - dynindx =3D 0; - } - got_offset =3D dyn_i->dtpmod_offset; - break; - case R_IA64_DTPREL32LSB: - case R_IA64_DTPREL64LSB: - done =3D dyn_i->dtprel_done; - dyn_i->dtprel_done =3D true; - got_offset =3D dyn_i->dtprel_offset; - break; - default: - done =3D dyn_i->got_done; - dyn_i->got_done =3D true; - got_offset =3D dyn_i->got_offset; - break; - } - - BFD_ASSERT ((got_offset & 7) =3D=3D 0); - - if (! done) - { - /* Store the target address in the linkage table entry. */ - bfd_put_64 (abfd, value, got_sec->contents + got_offset); - - /* Install a dynamic relocation if needed. */ - if (((bfd_link_pic (info) - && (!dyn_i->h - || ELF_ST_VISIBILITY (dyn_i->h->other) =3D=3D STV_DEFAULT - || dyn_i->h->root.type !=3D bfd_link_hash_undefweak) - && dyn_r_type !=3D R_IA64_DTPREL32LSB - && dyn_r_type !=3D R_IA64_DTPREL64LSB) - || elfNN_ia64_dynamic_symbol_p (dyn_i->h, info, dyn_r_type) - || (dynindx !=3D -1 - && (dyn_r_type =3D=3D R_IA64_FPTR32LSB - || dyn_r_type =3D=3D R_IA64_FPTR64LSB))) - && (!dyn_i->want_ltoff_fptr - || !bfd_link_pie (info) - || !dyn_i->h - || dyn_i->h->root.type !=3D bfd_link_hash_undefweak)) - { - if (dynindx =3D=3D -1 - && dyn_r_type !=3D R_IA64_TPREL64LSB - && dyn_r_type !=3D R_IA64_DTPMOD64LSB - && dyn_r_type !=3D R_IA64_DTPREL32LSB - && dyn_r_type !=3D R_IA64_DTPREL64LSB) - { - dyn_r_type =3D R_IA64_RELNNLSB; - dynindx =3D 0; - addend =3D value; - } - - if (bfd_big_endian (abfd)) - { - switch (dyn_r_type) - { - case R_IA64_REL32LSB: - dyn_r_type =3D R_IA64_REL32MSB; - break; - case R_IA64_DIR32LSB: - dyn_r_type =3D R_IA64_DIR32MSB; - break; - case R_IA64_FPTR32LSB: - dyn_r_type =3D R_IA64_FPTR32MSB; - break; - case R_IA64_DTPREL32LSB: - dyn_r_type =3D R_IA64_DTPREL32MSB; - break; - case R_IA64_REL64LSB: - dyn_r_type =3D R_IA64_REL64MSB; - break; - case R_IA64_DIR64LSB: - dyn_r_type =3D R_IA64_DIR64MSB; - break; - case R_IA64_FPTR64LSB: - dyn_r_type =3D R_IA64_FPTR64MSB; - break; - case R_IA64_TPREL64LSB: - dyn_r_type =3D R_IA64_TPREL64MSB; - break; - case R_IA64_DTPMOD64LSB: - dyn_r_type =3D R_IA64_DTPMOD64MSB; - break; - case R_IA64_DTPREL64LSB: - dyn_r_type =3D R_IA64_DTPREL64MSB; - break; - default: - BFD_ASSERT (false); - break; - } - } - - elfNN_ia64_install_dyn_reloc (abfd, NULL, got_sec, - ia64_info->root.srelgot, - got_offset, dyn_r_type, - dynindx, addend); - } - } - - /* Return the address of the linkage table entry. */ - value =3D (got_sec->output_section->vma - + got_sec->output_offset - + got_offset); - - return value; -} - -/* Fill in a function descriptor consisting of the function's code - address and its global pointer. Return the descriptor's address. */ - -static bfd_vma -set_fptr_entry (bfd *abfd, struct bfd_link_info *info, - struct elfNN_ia64_dyn_sym_info *dyn_i, - bfd_vma value) -{ - struct elfNN_ia64_link_hash_table *ia64_info; - asection *fptr_sec; - - ia64_info =3D elfNN_ia64_hash_table (info); - if (ia64_info =3D=3D NULL) - return 0; - - fptr_sec =3D ia64_info->fptr_sec; - - if (!dyn_i->fptr_done) - { - dyn_i->fptr_done =3D 1; - - /* Fill in the function descriptor. */ - bfd_put_64 (abfd, value, fptr_sec->contents + dyn_i->fptr_offset); - bfd_put_64 (abfd, _bfd_get_gp_value (abfd), - fptr_sec->contents + dyn_i->fptr_offset + 8); - if (ia64_info->rel_fptr_sec) - { - Elf_Internal_Rela outrel; - bfd_byte *loc; - - if (bfd_little_endian (abfd)) - outrel.r_info =3D ELFNN_R_INFO (0, R_IA64_IPLTLSB); - else - outrel.r_info =3D ELFNN_R_INFO (0, R_IA64_IPLTMSB); - outrel.r_addend =3D value; - outrel.r_offset =3D (fptr_sec->output_section->vma - + fptr_sec->output_offset - + dyn_i->fptr_offset); - loc =3D ia64_info->rel_fptr_sec->contents; - loc +=3D ia64_info->rel_fptr_sec->reloc_count++ - * sizeof (ElfNN_External_Rela); - bfd_elfNN_swap_reloca_out (abfd, &outrel, loc); - } - } - - /* Return the descriptor's address. */ - value =3D (fptr_sec->output_section->vma - + fptr_sec->output_offset - + dyn_i->fptr_offset); - - return value; -} - -/* Fill in a PLTOFF entry consisting of the function's code address - and its global pointer. Return the descriptor's address. */ - -static bfd_vma -set_pltoff_entry (bfd *abfd, struct bfd_link_info *info, - struct elfNN_ia64_dyn_sym_info *dyn_i, - bfd_vma value, bool is_plt) -{ - struct elfNN_ia64_link_hash_table *ia64_info; - asection *pltoff_sec; - - ia64_info =3D elfNN_ia64_hash_table (info); - if (ia64_info =3D=3D NULL) - return 0; - - pltoff_sec =3D ia64_info->pltoff_sec; - - /* Don't do anything if this symbol uses a real PLT entry. In - that case, we'll fill this in during finish_dynamic_symbol. */ - if ((! dyn_i->want_plt || is_plt) - && !dyn_i->pltoff_done) - { - bfd_vma gp =3D _bfd_get_gp_value (abfd); - - /* Fill in the function descriptor. */ - bfd_put_64 (abfd, value, pltoff_sec->contents + dyn_i->pltoff_offset= ); - bfd_put_64 (abfd, gp, pltoff_sec->contents + dyn_i->pltoff_offset + = 8); - - /* Install dynamic relocations if needed. */ - if (!is_plt - && bfd_link_pic (info) - && (!dyn_i->h - || ELF_ST_VISIBILITY (dyn_i->h->other) =3D=3D STV_DEFAULT - || dyn_i->h->root.type !=3D bfd_link_hash_undefweak)) - { - unsigned int dyn_r_type; - - if (bfd_big_endian (abfd)) - dyn_r_type =3D R_IA64_RELNNMSB; - else - dyn_r_type =3D R_IA64_RELNNLSB; - - elfNN_ia64_install_dyn_reloc (abfd, NULL, pltoff_sec, - ia64_info->rel_pltoff_sec, - dyn_i->pltoff_offset, - dyn_r_type, 0, value); - elfNN_ia64_install_dyn_reloc (abfd, NULL, pltoff_sec, - ia64_info->rel_pltoff_sec, - dyn_i->pltoff_offset + ARCH_SIZE / 8, - dyn_r_type, 0, gp); - } - - dyn_i->pltoff_done =3D 1; - } - - /* Return the descriptor's address. */ - value =3D (pltoff_sec->output_section->vma - + pltoff_sec->output_offset - + dyn_i->pltoff_offset); - - return value; -} - -/* Return the base VMA address which should be subtracted from real addres= ses - when resolving @tprel() relocation. - Main program TLS (whose template starts at PT_TLS p_vaddr) - is assigned offset round(2 * size of pointer, PT_TLS p_align). */ - -static bfd_vma -elfNN_ia64_tprel_base (struct bfd_link_info *info) -{ - asection *tls_sec =3D elf_hash_table (info)->tls_sec; - return tls_sec->vma - align_power ((bfd_vma) ARCH_SIZE / 4, - tls_sec->alignment_power); -} - -/* Return the base VMA address which should be subtracted from real addres= ses - when resolving @dtprel() relocation. - This is PT_TLS segment p_vaddr. */ - -static bfd_vma -elfNN_ia64_dtprel_base (struct bfd_link_info *info) -{ - return elf_hash_table (info)->tls_sec->vma; -} - -/* Called through qsort to sort the .IA_64.unwind section during a - non-relocatable link. Set elfNN_ia64_unwind_entry_compare_bfd - to the output bfd so we can do proper endianness frobbing. */ - -static bfd *elfNN_ia64_unwind_entry_compare_bfd; - -static int -elfNN_ia64_unwind_entry_compare (const void * a, const void * b) -{ - bfd_vma av, bv; - - av =3D bfd_get_64 (elfNN_ia64_unwind_entry_compare_bfd, a); - bv =3D bfd_get_64 (elfNN_ia64_unwind_entry_compare_bfd, b); - - return (av < bv ? -1 : av > bv ? 1 : 0); -} - -/* Make sure we've got ourselves a nice fat __gp value. */ -static bool -elfNN_ia64_choose_gp (bfd *abfd, struct bfd_link_info *info, bool final) -{ - bfd_vma min_vma =3D (bfd_vma) -1, max_vma =3D 0; - bfd_vma min_short_vma =3D min_vma, max_short_vma =3D 0; - struct elf_link_hash_entry *gp; - bfd_vma gp_val; - asection *os; - struct elfNN_ia64_link_hash_table *ia64_info; - - ia64_info =3D elfNN_ia64_hash_table (info); - if (ia64_info =3D=3D NULL) - return false; - - /* Find the min and max vma of all sections marked short. Also collect - min and max vma of any type, for use in selecting a nice gp. */ - for (os =3D abfd->sections; os ; os =3D os->next) - { - bfd_vma lo, hi; - - if ((os->flags & SEC_ALLOC) =3D=3D 0) - continue; - - lo =3D os->vma; - /* When this function is called from elfNN_ia64_final_link - the correct value to use is os->size. When called from - elfNN_ia64_relax_section we are in the middle of section - sizing; some sections will already have os->size set, others - will have os->size zero and os->rawsize the previous size. */ - hi =3D os->vma + (!final && os->rawsize ? os->rawsize : os->size); - if (hi < lo) - hi =3D (bfd_vma) -1; - - if (min_vma > lo) - min_vma =3D lo; - if (max_vma < hi) - max_vma =3D hi; - if (os->flags & SEC_SMALL_DATA) - { - if (min_short_vma > lo) - min_short_vma =3D lo; - if (max_short_vma < hi) - max_short_vma =3D hi; - } - } - - if (ia64_info->min_short_sec) - { - if (min_short_vma - > (ia64_info->min_short_sec->vma - + ia64_info->min_short_offset)) - min_short_vma =3D (ia64_info->min_short_sec->vma - + ia64_info->min_short_offset); - if (max_short_vma - < (ia64_info->max_short_sec->vma - + ia64_info->max_short_offset)) - max_short_vma =3D (ia64_info->max_short_sec->vma - + ia64_info->max_short_offset); - } - - /* See if the user wants to force a value. */ - gp =3D elf_link_hash_lookup (elf_hash_table (info), "__gp", false, - false, false); - - if (gp - && (gp->root.type =3D=3D bfd_link_hash_defined - || gp->root.type =3D=3D bfd_link_hash_defweak)) - { - asection *gp_sec =3D gp->root.u.def.section; - gp_val =3D (gp->root.u.def.value - + gp_sec->output_section->vma - + gp_sec->output_offset); - } - else - { - /* Pick a sensible value. */ - - if (ia64_info->min_short_sec) - { - bfd_vma short_range =3D max_short_vma - min_short_vma; - - /* If min_short_sec is set, pick one in the middle bewteen - min_short_vma and max_short_vma. */ - if (short_range >=3D 0x400000) - goto overflow; - gp_val =3D min_short_vma + short_range / 2; - } - else - { - asection *got_sec =3D ia64_info->root.sgot; - - /* Start with just the address of the .got. */ - if (got_sec) - gp_val =3D got_sec->output_section->vma; - else if (max_short_vma !=3D 0) - gp_val =3D min_short_vma; - else if (max_vma - min_vma < 0x200000) - gp_val =3D min_vma; - else - gp_val =3D max_vma - 0x200000 + 8; - } - - /* If it is possible to address the entire image, but we - don't with the choice above, adjust. */ - if (max_vma - min_vma < 0x400000 - && (max_vma - gp_val >=3D 0x200000 - || gp_val - min_vma > 0x200000)) - gp_val =3D min_vma + 0x200000; - else if (max_short_vma !=3D 0) - { - /* If we don't cover all the short data, adjust. */ - if (max_short_vma - gp_val >=3D 0x200000) - gp_val =3D min_short_vma + 0x200000; - - /* If we're addressing stuff past the end, adjust back. */ - if (gp_val > max_vma) - gp_val =3D max_vma - 0x200000 + 8; - } - } - - /* Validate whether all SHF_IA_64_SHORT sections are within - range of the chosen GP. */ - - if (max_short_vma !=3D 0) - { - if (max_short_vma - min_short_vma >=3D 0x400000) - { - overflow: - _bfd_error_handler - /* xgettext:c-format */ - (_("%pB: short data segment overflowed (%#" PRIx64 " >=3D 0x400000)"), - abfd, (uint64_t) (max_short_vma - min_short_vma)); - return false; - } - else if ((gp_val > min_short_vma - && gp_val - min_short_vma > 0x200000) - || (gp_val < max_short_vma - && max_short_vma - gp_val >=3D 0x200000)) - { - _bfd_error_handler - (_("%pB: __gp does not cover short data segment"), abfd); - return false; - } - } - - _bfd_set_gp_value (abfd, gp_val); - - return true; -} - -static bool -elfNN_ia64_final_link (bfd *abfd, struct bfd_link_info *info) -{ - struct elfNN_ia64_link_hash_table *ia64_info; - asection *unwind_output_sec; - - ia64_info =3D elfNN_ia64_hash_table (info); - if (ia64_info =3D=3D NULL) - return false; - - /* Make sure we've got ourselves a nice fat __gp value. */ - if (!bfd_link_relocatable (info)) - { - bfd_vma gp_val; - struct elf_link_hash_entry *gp; - - /* We assume after gp is set, section size will only decrease. We - need to adjust gp for it. */ - _bfd_set_gp_value (abfd, 0); - if (! elfNN_ia64_choose_gp (abfd, info, true)) - return false; - gp_val =3D _bfd_get_gp_value (abfd); - - gp =3D elf_link_hash_lookup (elf_hash_table (info), "__gp", false, - false, false); - if (gp) - { - gp->root.type =3D bfd_link_hash_defined; - gp->root.u.def.value =3D gp_val; - gp->root.u.def.section =3D bfd_abs_section_ptr; - } - } - - /* If we're producing a final executable, we need to sort the contents - of the .IA_64.unwind section. Force this section to be relocated - into memory rather than written immediately to the output file. */ - unwind_output_sec =3D NULL; - if (!bfd_link_relocatable (info)) - { - asection *s =3D bfd_get_section_by_name (abfd, ELF_STRING_ia64_unwin= d); - if (s) - { - unwind_output_sec =3D s->output_section; - unwind_output_sec->contents - =3D bfd_malloc (unwind_output_sec->size); - if (unwind_output_sec->contents =3D=3D NULL) - return false; - } - } - - /* Invoke the regular ELF backend linker to do all the work. */ - if (!bfd_elf_final_link (abfd, info)) - return false; - - if (unwind_output_sec) - { - elfNN_ia64_unwind_entry_compare_bfd =3D abfd; - qsort (unwind_output_sec->contents, - (size_t) (unwind_output_sec->size / 24), - 24, - elfNN_ia64_unwind_entry_compare); - - if (! bfd_set_section_contents (abfd, unwind_output_sec, - unwind_output_sec->contents, (bfd_vma) 0, - unwind_output_sec->size)) - return false; - } - - return true; -} - -static int -elfNN_ia64_relocate_section (bfd *output_bfd, - struct bfd_link_info *info, - bfd *input_bfd, - asection *input_section, - bfd_byte *contents, - Elf_Internal_Rela *relocs, - Elf_Internal_Sym *local_syms, - asection **local_sections) -{ - struct elfNN_ia64_link_hash_table *ia64_info; - Elf_Internal_Shdr *symtab_hdr; - Elf_Internal_Rela *rel; - Elf_Internal_Rela *relend; - asection *srel; - bool ret_val =3D true; /* for non-fatal errors */ - bfd_vma gp_val; - - symtab_hdr =3D &elf_tdata (input_bfd)->symtab_hdr; - ia64_info =3D elfNN_ia64_hash_table (info); - if (ia64_info =3D=3D NULL) - return false; - - /* Infect various flags from the input section to the output section. */ - if (bfd_link_relocatable (info)) - { - bfd_vma flags; - - flags =3D elf_section_data(input_section)->this_hdr.sh_flags; - flags &=3D SHF_IA_64_NORECOV; - - elf_section_data(input_section->output_section) - ->this_hdr.sh_flags |=3D flags; - } - - gp_val =3D _bfd_get_gp_value (output_bfd); - srel =3D get_reloc_section (input_bfd, ia64_info, input_section, false); - - rel =3D relocs; - relend =3D relocs + input_section->reloc_count; - for (; rel < relend; ++rel) - { - struct elf_link_hash_entry *h; - struct elfNN_ia64_dyn_sym_info *dyn_i; - bfd_reloc_status_type r; - reloc_howto_type *howto; - unsigned long r_symndx; - Elf_Internal_Sym *sym; - unsigned int r_type; - bfd_vma value; - asection *sym_sec; - bfd_byte *hit_addr; - bool dynamic_symbol_p; - bool undef_weak_ref; - - r_type =3D ELFNN_R_TYPE (rel->r_info); - if (r_type > R_IA64_MAX_RELOC_CODE) - { - /* xgettext:c-format */ - _bfd_error_handler (_("%pB: unsupported relocation type %#x"), - input_bfd, (int) r_type); - bfd_set_error (bfd_error_bad_value); - ret_val =3D false; - continue; - } - - howto =3D ia64_elf_lookup_howto (r_type); - if (howto =3D=3D NULL) - { - ret_val =3D false; - continue; - } - - r_symndx =3D ELFNN_R_SYM (rel->r_info); - h =3D NULL; - sym =3D NULL; - sym_sec =3D NULL; - undef_weak_ref =3D false; - - if (r_symndx < symtab_hdr->sh_info) - { - /* Reloc against local symbol. */ - asection *msec; - sym =3D local_syms + r_symndx; - sym_sec =3D local_sections[r_symndx]; - msec =3D sym_sec; - value =3D _bfd_elf_rela_local_sym (output_bfd, sym, &msec, rel); - if (!bfd_link_relocatable (info) - && (sym_sec->flags & SEC_MERGE) !=3D 0 - && ELF_ST_TYPE (sym->st_info) =3D=3D STT_SECTION - && sym_sec->sec_info_type =3D=3D SEC_INFO_TYPE_MERGE) - { - struct elfNN_ia64_local_hash_entry *loc_h; - - loc_h =3D get_local_sym_hash (ia64_info, input_bfd, rel, false); - if (loc_h && ! loc_h->sec_merge_done) - { - struct elfNN_ia64_dyn_sym_info *dynent; - unsigned int count; - - for (count =3D loc_h->count, dynent =3D loc_h->info; - count !=3D 0; - count--, dynent++) - { - msec =3D sym_sec; - dynent->addend =3D - _bfd_merged_section_offset (output_bfd, &msec, - elf_section_data (msec)-> - sec_info, - sym->st_value - + dynent->addend); - dynent->addend -=3D sym->st_value; - dynent->addend +=3D msec->output_section->vma - + msec->output_offset - - sym_sec->output_section->vma - - sym_sec->output_offset; - } - - /* We may have introduced duplicated entries. We need - to remove them properly. */ - count =3D sort_dyn_sym_info (loc_h->info, loc_h->count); - if (count !=3D loc_h->count) - { - loc_h->count =3D count; - loc_h->sorted_count =3D count; - } - - loc_h->sec_merge_done =3D 1; - } - } - } - else - { - bool unresolved_reloc; - bool warned, ignored; - struct elf_link_hash_entry **sym_hashes =3D elf_sym_hashes (input_bfd); - - RELOC_FOR_GLOBAL_SYMBOL (info, input_bfd, input_section, rel, - r_symndx, symtab_hdr, sym_hashes, - h, sym_sec, value, - unresolved_reloc, warned, ignored); - - if (h->root.type =3D=3D bfd_link_hash_undefweak) - undef_weak_ref =3D true; - else if (warned || (ignored && bfd_link_executable (info))) - continue; - } - - if (sym_sec !=3D NULL && discarded_section (sym_sec)) - RELOC_AGAINST_DISCARDED_SECTION (info, input_bfd, input_section, - rel, 1, relend, howto, 0, contents); - - if (bfd_link_relocatable (info)) - continue; - - hit_addr =3D contents + rel->r_offset; - value +=3D rel->r_addend; - dynamic_symbol_p =3D elfNN_ia64_dynamic_symbol_p (h, info, r_type); - - switch (r_type) - { - case R_IA64_NONE: - case R_IA64_LDXMOV: - continue; - - case R_IA64_IMM14: - case R_IA64_IMM22: - case R_IA64_IMM64: - case R_IA64_DIR32MSB: - case R_IA64_DIR32LSB: - case R_IA64_DIR64MSB: - case R_IA64_DIR64LSB: - /* Install a dynamic relocation for this reloc. */ - if ((dynamic_symbol_p || bfd_link_pic (info)) - && r_symndx !=3D STN_UNDEF - && (input_section->flags & SEC_ALLOC) !=3D 0) - { - unsigned int dyn_r_type; - long dynindx; - bfd_vma addend; - - BFD_ASSERT (srel !=3D NULL); - - switch (r_type) - { - case R_IA64_IMM14: - case R_IA64_IMM22: - case R_IA64_IMM64: - /* ??? People shouldn't be doing non-pic code in - shared libraries nor dynamic executables. */ - _bfd_error_handler - /* xgettext:c-format */ - (_("%pB: non-pic code with imm relocation against dynamic symbol `%s= '"), - input_bfd, - h ? h->root.root.string - : bfd_elf_sym_name (input_bfd, symtab_hdr, sym, - sym_sec)); - ret_val =3D false; - continue; - - default: - break; - } - - /* If we don't need dynamic symbol lookup, find a - matching RELATIVE relocation. */ - dyn_r_type =3D r_type; - if (dynamic_symbol_p) - { - dynindx =3D h->dynindx; - addend =3D rel->r_addend; - value =3D 0; - } - else - { - switch (r_type) - { - case R_IA64_DIR32MSB: - dyn_r_type =3D R_IA64_REL32MSB; - break; - case R_IA64_DIR32LSB: - dyn_r_type =3D R_IA64_REL32LSB; - break; - case R_IA64_DIR64MSB: - dyn_r_type =3D R_IA64_REL64MSB; - break; - case R_IA64_DIR64LSB: - dyn_r_type =3D R_IA64_REL64LSB; - break; - - default: - break; - } - dynindx =3D 0; - addend =3D value; - } - - elfNN_ia64_install_dyn_reloc (output_bfd, info, input_section, - srel, rel->r_offset, dyn_r_type, - dynindx, addend); - } - /* Fall through. */ - - case R_IA64_LTV32MSB: - case R_IA64_LTV32LSB: - case R_IA64_LTV64MSB: - case R_IA64_LTV64LSB: - r =3D ia64_elf_install_value (hit_addr, value, r_type); - break; - - case R_IA64_GPREL22: - case R_IA64_GPREL64I: - case R_IA64_GPREL32MSB: - case R_IA64_GPREL32LSB: - case R_IA64_GPREL64MSB: - case R_IA64_GPREL64LSB: - if (dynamic_symbol_p) - { - _bfd_error_handler - /* xgettext:c-format */ - (_("%pB: @gprel relocation against dynamic symbol %s"), - input_bfd, - h ? h->root.root.string - : bfd_elf_sym_name (input_bfd, symtab_hdr, sym, - sym_sec)); - ret_val =3D false; - continue; - } - value -=3D gp_val; - r =3D ia64_elf_install_value (hit_addr, value, r_type); - break; - - case R_IA64_LTOFF22: - case R_IA64_LTOFF22X: - case R_IA64_LTOFF64I: - dyn_i =3D get_dyn_sym_info (ia64_info, h, input_bfd, rel, false); - value =3D set_got_entry (input_bfd, info, dyn_i, (h ? h->dynindx : -1), - rel->r_addend, value, R_IA64_DIRNNLSB); - value -=3D gp_val; - r =3D ia64_elf_install_value (hit_addr, value, r_type); - break; - - case R_IA64_PLTOFF22: - case R_IA64_PLTOFF64I: - case R_IA64_PLTOFF64MSB: - case R_IA64_PLTOFF64LSB: - dyn_i =3D get_dyn_sym_info (ia64_info, h, input_bfd, rel, false); - value =3D set_pltoff_entry (output_bfd, info, dyn_i, value, false); - value -=3D gp_val; - r =3D ia64_elf_install_value (hit_addr, value, r_type); - break; - - case R_IA64_FPTR64I: - case R_IA64_FPTR32MSB: - case R_IA64_FPTR32LSB: - case R_IA64_FPTR64MSB: - case R_IA64_FPTR64LSB: - dyn_i =3D get_dyn_sym_info (ia64_info, h, input_bfd, rel, false); - if (dyn_i->want_fptr) - { - if (!undef_weak_ref) - value =3D set_fptr_entry (output_bfd, info, dyn_i, value); - } - if (!dyn_i->want_fptr || bfd_link_pie (info)) - { - long dynindx; - unsigned int dyn_r_type =3D r_type; - bfd_vma addend =3D rel->r_addend; - - /* Otherwise, we expect the dynamic linker to create - the entry. */ - - if (dyn_i->want_fptr) - { - if (r_type =3D=3D R_IA64_FPTR64I) - { - /* We can't represent this without a dynamic symbol. - Adjust the relocation to be against an output - section symbol, which are always present in the - dynamic symbol table. */ - /* ??? People shouldn't be doing non-pic code in - shared libraries. Hork. */ - _bfd_error_handler - (_("%pB: linking non-pic code in a position independent executable"), - input_bfd); - ret_val =3D false; - continue; - } - dynindx =3D 0; - addend =3D value; - dyn_r_type =3D r_type + R_IA64_RELNNLSB - R_IA64_FPTRNNLSB; - } - else if (h) - { - if (h->dynindx !=3D -1) - dynindx =3D h->dynindx; - else - dynindx =3D (_bfd_elf_link_lookup_local_dynindx - (info, h->root.u.def.section->owner, - global_sym_index (h))); - value =3D 0; - } - else - { - dynindx =3D (_bfd_elf_link_lookup_local_dynindx - (info, input_bfd, (long) r_symndx)); - value =3D 0; - } - - elfNN_ia64_install_dyn_reloc (output_bfd, info, input_section, - srel, rel->r_offset, dyn_r_type, - dynindx, addend); - } - - r =3D ia64_elf_install_value (hit_addr, value, r_type); - break; - - case R_IA64_LTOFF_FPTR22: - case R_IA64_LTOFF_FPTR64I: - case R_IA64_LTOFF_FPTR32MSB: - case R_IA64_LTOFF_FPTR32LSB: - case R_IA64_LTOFF_FPTR64MSB: - case R_IA64_LTOFF_FPTR64LSB: - { - long dynindx; - - dyn_i =3D get_dyn_sym_info (ia64_info, h, input_bfd, rel, false); - if (dyn_i->want_fptr) - { - BFD_ASSERT (h =3D=3D NULL || h->dynindx =3D=3D -1); - if (!undef_weak_ref) - value =3D set_fptr_entry (output_bfd, info, dyn_i, value); - dynindx =3D -1; - } - else - { - /* Otherwise, we expect the dynamic linker to create - the entry. */ - if (h) - { - if (h->dynindx !=3D -1) - dynindx =3D h->dynindx; - else - dynindx =3D (_bfd_elf_link_lookup_local_dynindx - (info, h->root.u.def.section->owner, - global_sym_index (h))); - } - else - dynindx =3D (_bfd_elf_link_lookup_local_dynindx - (info, input_bfd, (long) r_symndx)); - value =3D 0; - } - - value =3D set_got_entry (output_bfd, info, dyn_i, dynindx, - rel->r_addend, value, R_IA64_FPTRNNLSB); - value -=3D gp_val; - r =3D ia64_elf_install_value (hit_addr, value, r_type); - } - break; - - case R_IA64_PCREL32MSB: - case R_IA64_PCREL32LSB: - case R_IA64_PCREL64MSB: - case R_IA64_PCREL64LSB: - /* Install a dynamic relocation for this reloc. */ - if (dynamic_symbol_p && r_symndx !=3D STN_UNDEF) - { - BFD_ASSERT (srel !=3D NULL); - - elfNN_ia64_install_dyn_reloc (output_bfd, info, input_section, - srel, rel->r_offset, r_type, - h->dynindx, rel->r_addend); - } - goto finish_pcrel; - - case R_IA64_PCREL21B: - case R_IA64_PCREL60B: - /* We should have created a PLT entry for any dynamic symbol. */ - dyn_i =3D NULL; - if (h) - dyn_i =3D get_dyn_sym_info (ia64_info, h, NULL, NULL, false); - - if (dyn_i && dyn_i->want_plt2) - { - /* Should have caught this earlier. */ - BFD_ASSERT (rel->r_addend =3D=3D 0); - - value =3D (ia64_info->root.splt->output_section->vma - + ia64_info->root.splt->output_offset - + dyn_i->plt2_offset); - } - else - { - /* Since there's no PLT entry, Validate that this is - locally defined. */ - BFD_ASSERT (undef_weak_ref || sym_sec->output_section !=3D NULL); - - /* If the symbol is undef_weak, we shouldn't be trying - to call it. There's every chance that we'd wind up - with an out-of-range fixup here. Don't bother setting - any value at all. */ - if (undef_weak_ref) - continue; - } - goto finish_pcrel; - - case R_IA64_PCREL21BI: - case R_IA64_PCREL21F: - case R_IA64_PCREL21M: - case R_IA64_PCREL22: - case R_IA64_PCREL64I: - /* The PCREL21BI reloc is specifically not intended for use with - dynamic relocs. PCREL21F and PCREL21M are used for speculation - fixup code, and thus probably ought not be dynamic. The - PCREL22 and PCREL64I relocs aren't emitted as dynamic relocs. */ - if (dynamic_symbol_p) - { - const char *msg; - - if (r_type =3D=3D R_IA64_PCREL21BI) - /* xgettext:c-format */ - msg =3D _("%pB: @internal branch to dynamic symbol %s"); - else if (r_type =3D=3D R_IA64_PCREL21F || r_type =3D=3D R_IA64_PCRE= L21M) - /* xgettext:c-format */ - msg =3D _("%pB: speculation fixup to dynamic symbol %s"); - else - /* xgettext:c-format */ - msg =3D _("%pB: @pcrel relocation against dynamic symbol %s"); - _bfd_error_handler (msg, input_bfd, - h ? h->root.root.string - : bfd_elf_sym_name (input_bfd, - symtab_hdr, - sym, - sym_sec)); - ret_val =3D false; - continue; - } - goto finish_pcrel; - - finish_pcrel: - /* Make pc-relative. */ - value -=3D (input_section->output_section->vma - + input_section->output_offset - + rel->r_offset) & ~ (bfd_vma) 0x3; - r =3D ia64_elf_install_value (hit_addr, value, r_type); - break; - - case R_IA64_SEGREL32MSB: - case R_IA64_SEGREL32LSB: - case R_IA64_SEGREL64MSB: - case R_IA64_SEGREL64LSB: - { - /* Find the segment that contains the output_section. */ - Elf_Internal_Phdr *p =3D _bfd_elf_find_segment_containing_section - (output_bfd, input_section->output_section); - - if (p =3D=3D NULL) - { - r =3D bfd_reloc_notsupported; - } - else - { - /* The VMA of the segment is the vaddr of the associated - program header. */ - if (value > p->p_vaddr) - value -=3D p->p_vaddr; - else - value =3D 0; - r =3D ia64_elf_install_value (hit_addr, value, r_type); - } - break; - } - - case R_IA64_SECREL32MSB: - case R_IA64_SECREL32LSB: - case R_IA64_SECREL64MSB: - case R_IA64_SECREL64LSB: - /* Make output-section relative to section where the symbol - is defined. PR 475 */ - if (sym_sec) - value -=3D sym_sec->output_section->vma; - r =3D ia64_elf_install_value (hit_addr, value, r_type); - break; - - case R_IA64_IPLTMSB: - case R_IA64_IPLTLSB: - /* Install a dynamic relocation for this reloc. */ - if ((dynamic_symbol_p || bfd_link_pic (info)) - && (input_section->flags & SEC_ALLOC) !=3D 0) - { - BFD_ASSERT (srel !=3D NULL); - - /* If we don't need dynamic symbol lookup, install two - RELATIVE relocations. */ - if (!dynamic_symbol_p) - { - unsigned int dyn_r_type; - - if (r_type =3D=3D R_IA64_IPLTMSB) - dyn_r_type =3D R_IA64_REL64MSB; - else - dyn_r_type =3D R_IA64_REL64LSB; - - elfNN_ia64_install_dyn_reloc (output_bfd, info, - input_section, - srel, rel->r_offset, - dyn_r_type, 0, value); - elfNN_ia64_install_dyn_reloc (output_bfd, info, - input_section, - srel, rel->r_offset + 8, - dyn_r_type, 0, gp_val); - } - else - elfNN_ia64_install_dyn_reloc (output_bfd, info, input_section, - srel, rel->r_offset, r_type, - h->dynindx, rel->r_addend); - } - - if (r_type =3D=3D R_IA64_IPLTMSB) - r_type =3D R_IA64_DIR64MSB; - else - r_type =3D R_IA64_DIR64LSB; - ia64_elf_install_value (hit_addr, value, r_type); - r =3D ia64_elf_install_value (hit_addr + 8, gp_val, r_type); - break; - - case R_IA64_TPREL14: - case R_IA64_TPREL22: - case R_IA64_TPREL64I: - if (elf_hash_table (info)->tls_sec =3D=3D NULL) - goto missing_tls_sec; - value -=3D elfNN_ia64_tprel_base (info); - r =3D ia64_elf_install_value (hit_addr, value, r_type); - break; - - case R_IA64_DTPREL14: - case R_IA64_DTPREL22: - case R_IA64_DTPREL64I: - case R_IA64_DTPREL32LSB: - case R_IA64_DTPREL32MSB: - case R_IA64_DTPREL64LSB: - case R_IA64_DTPREL64MSB: - if (elf_hash_table (info)->tls_sec =3D=3D NULL) - goto missing_tls_sec; - value -=3D elfNN_ia64_dtprel_base (info); - r =3D ia64_elf_install_value (hit_addr, value, r_type); - break; - - case R_IA64_LTOFF_TPREL22: - case R_IA64_LTOFF_DTPMOD22: - case R_IA64_LTOFF_DTPREL22: - { - int got_r_type; - long dynindx =3D h ? h->dynindx : -1; - bfd_vma r_addend =3D rel->r_addend; - - switch (r_type) - { - default: - case R_IA64_LTOFF_TPREL22: - if (!dynamic_symbol_p) - { - if (elf_hash_table (info)->tls_sec =3D=3D NULL) - goto missing_tls_sec; - if (!bfd_link_pic (info)) - value -=3D elfNN_ia64_tprel_base (info); - else - { - r_addend +=3D value - elfNN_ia64_dtprel_base (info); - dynindx =3D 0; - } - } - got_r_type =3D R_IA64_TPREL64LSB; - break; - case R_IA64_LTOFF_DTPMOD22: - if (!dynamic_symbol_p && !bfd_link_pic (info)) - value =3D 1; - got_r_type =3D R_IA64_DTPMOD64LSB; - break; - case R_IA64_LTOFF_DTPREL22: - if (!dynamic_symbol_p) - { - if (elf_hash_table (info)->tls_sec =3D=3D NULL) - goto missing_tls_sec; - value -=3D elfNN_ia64_dtprel_base (info); - } - got_r_type =3D R_IA64_DTPRELNNLSB; - break; - } - dyn_i =3D get_dyn_sym_info (ia64_info, h, input_bfd, rel, false); - value =3D set_got_entry (input_bfd, info, dyn_i, dynindx, r_addend, - value, got_r_type); - value -=3D gp_val; - r =3D ia64_elf_install_value (hit_addr, value, r_type); - } - break; - - default: - r =3D bfd_reloc_notsupported; - break; - } - - switch (r) - { - case bfd_reloc_ok: - break; - - case bfd_reloc_undefined: - /* This can happen for global table relative relocs if - __gp is undefined. This is a panic situation so we - don't try to continue. */ - (*info->callbacks->undefined_symbol) - (info, "__gp", input_bfd, input_section, rel->r_offset, 1); - return false; - - case bfd_reloc_notsupported: - { - const char *name; - - if (h) - name =3D h->root.root.string; - else - name =3D bfd_elf_sym_name (input_bfd, symtab_hdr, sym, - sym_sec); - (*info->callbacks->warning) (info, _("unsupported reloc"), - name, input_bfd, - input_section, rel->r_offset); - ret_val =3D false; - } - break; - - case bfd_reloc_dangerous: - case bfd_reloc_outofrange: - case bfd_reloc_overflow: - default: - missing_tls_sec: - { - const char *name; - - if (h) - name =3D h->root.root.string; - else - name =3D bfd_elf_sym_name (input_bfd, symtab_hdr, sym, - sym_sec); - - switch (r_type) - { - case R_IA64_TPREL14: - case R_IA64_TPREL22: - case R_IA64_TPREL64I: - case R_IA64_DTPREL14: - case R_IA64_DTPREL22: - case R_IA64_DTPREL64I: - case R_IA64_DTPREL32LSB: - case R_IA64_DTPREL32MSB: - case R_IA64_DTPREL64LSB: - case R_IA64_DTPREL64MSB: - case R_IA64_LTOFF_TPREL22: - case R_IA64_LTOFF_DTPMOD22: - case R_IA64_LTOFF_DTPREL22: - _bfd_error_handler - /* xgettext:c-format */ - (_("%pB: missing TLS section for relocation %s against `%s'" - " at %#" PRIx64 " in section `%pA'."), - input_bfd, howto->name, name, - (uint64_t) rel->r_offset, input_section); - break; - - case R_IA64_PCREL21B: - case R_IA64_PCREL21BI: - case R_IA64_PCREL21M: - case R_IA64_PCREL21F: - if (is_elf_hash_table (info->hash)) - { - /* Relaxtion is always performed for ELF output. - Overflow failures for those relocations mean - that the section is too big to relax. */ - _bfd_error_handler - /* xgettext:c-format */ - (_("%pB: Can't relax br (%s) to `%s' at %#" PRIx64 - " in section `%pA' with size %#" PRIx64 - " (> 0x1000000)."), - input_bfd, howto->name, name, (uint64_t) rel->r_offset, - input_section, (uint64_t) input_section->size); - break; - } - /* Fall through. */ - default: - (*info->callbacks->reloc_overflow) (info, - &h->root, - name, - howto->name, - (bfd_vma) 0, - input_bfd, - input_section, - rel->r_offset); - break; - } - - ret_val =3D false; - } - break; - } - } - - return ret_val; -} - -static bool -elfNN_ia64_finish_dynamic_symbol (bfd *output_bfd, - struct bfd_link_info *info, - struct elf_link_hash_entry *h, - Elf_Internal_Sym *sym) -{ - struct elfNN_ia64_link_hash_table *ia64_info; - struct elfNN_ia64_dyn_sym_info *dyn_i; - - ia64_info =3D elfNN_ia64_hash_table (info); - - dyn_i =3D get_dyn_sym_info (ia64_info, h, NULL, NULL, false); - - /* Fill in the PLT data, if required. */ - if (dyn_i && dyn_i->want_plt) - { - Elf_Internal_Rela outrel; - bfd_byte *loc; - asection *plt_sec; - bfd_vma plt_addr, pltoff_addr, gp_val, plt_index; - - gp_val =3D _bfd_get_gp_value (output_bfd); - - /* Initialize the minimal PLT entry. */ - - plt_index =3D (dyn_i->plt_offset - PLT_HEADER_SIZE) / PLT_MIN_ENTRY_= SIZE; - plt_sec =3D ia64_info->root.splt; - loc =3D plt_sec->contents + dyn_i->plt_offset; - - memcpy (loc, plt_min_entry, PLT_MIN_ENTRY_SIZE); - ia64_elf_install_value (loc, plt_index, R_IA64_IMM22); - ia64_elf_install_value (loc+2, -dyn_i->plt_offset, R_IA64_PCREL21B); - - plt_addr =3D (plt_sec->output_section->vma - + plt_sec->output_offset - + dyn_i->plt_offset); - pltoff_addr =3D set_pltoff_entry (output_bfd, info, dyn_i, plt_addr,= true); - - /* Initialize the FULL PLT entry, if needed. */ - if (dyn_i->want_plt2) - { - loc =3D plt_sec->contents + dyn_i->plt2_offset; - - memcpy (loc, plt_full_entry, PLT_FULL_ENTRY_SIZE); - ia64_elf_install_value (loc, pltoff_addr - gp_val, R_IA64_IMM22); - - /* Mark the symbol as undefined, rather than as defined in the - plt section. Leave the value alone. */ - /* ??? We didn't redefine it in adjust_dynamic_symbol in the - first place. But perhaps elflink.c did some for us. */ - if (!h->def_regular) - sym->st_shndx =3D SHN_UNDEF; - } - - /* Create the dynamic relocation. */ - outrel.r_offset =3D pltoff_addr; - if (bfd_little_endian (output_bfd)) - outrel.r_info =3D ELFNN_R_INFO (h->dynindx, R_IA64_IPLTLSB); - else - outrel.r_info =3D ELFNN_R_INFO (h->dynindx, R_IA64_IPLTMSB); - outrel.r_addend =3D 0; - - /* This is fun. In the .IA_64.pltoff section, we've got entries - that correspond both to real PLT entries, and those that - happened to resolve to local symbols but need to be created - to satisfy @pltoff relocations. The .rela.IA_64.pltoff - relocations for the real PLT should come at the end of the - section, so that they can be indexed by plt entry at runtime. - - We emitted all of the relocations for the non-PLT @pltoff - entries during relocate_section. So we can consider the - existing sec->reloc_count to be the base of the array of - PLT relocations. */ - - loc =3D ia64_info->rel_pltoff_sec->contents; - loc +=3D ((ia64_info->rel_pltoff_sec->reloc_count + plt_index) - * sizeof (ElfNN_External_Rela)); - bfd_elfNN_swap_reloca_out (output_bfd, &outrel, loc); - } - - /* Mark some specially defined symbols as absolute. */ - if (h =3D=3D ia64_info->root.hdynamic - || h =3D=3D ia64_info->root.hgot - || h =3D=3D ia64_info->root.hplt) - sym->st_shndx =3D SHN_ABS; - - return true; -} - -static bool -elfNN_ia64_finish_dynamic_sections (bfd *abfd, - struct bfd_link_info *info) -{ - struct elfNN_ia64_link_hash_table *ia64_info; - bfd *dynobj; - - ia64_info =3D elfNN_ia64_hash_table (info); - if (ia64_info =3D=3D NULL) - return false; - - dynobj =3D ia64_info->root.dynobj; - - if (ia64_info->root.dynamic_sections_created) - { - ElfNN_External_Dyn *dyncon, *dynconend; - asection *sdyn, *sgotplt; - bfd_vma gp_val; - - sdyn =3D bfd_get_linker_section (dynobj, ".dynamic"); - sgotplt =3D ia64_info->root.sgotplt; - BFD_ASSERT (sdyn !=3D NULL); - dyncon =3D (ElfNN_External_Dyn *) sdyn->contents; - dynconend =3D (ElfNN_External_Dyn *) (sdyn->contents + sdyn->size); - - gp_val =3D _bfd_get_gp_value (abfd); - - for (; dyncon < dynconend; dyncon++) - { - Elf_Internal_Dyn dyn; - - bfd_elfNN_swap_dyn_in (dynobj, dyncon, &dyn); - - switch (dyn.d_tag) - { - case DT_PLTGOT: - dyn.d_un.d_ptr =3D gp_val; - break; - - case DT_PLTRELSZ: - dyn.d_un.d_val =3D (ia64_info->minplt_entries - * sizeof (ElfNN_External_Rela)); - break; - - case DT_JMPREL: - /* See the comment above in finish_dynamic_symbol. */ - dyn.d_un.d_ptr =3D (ia64_info->rel_pltoff_sec->output_section->vma - + ia64_info->rel_pltoff_sec->output_offset - + (ia64_info->rel_pltoff_sec->reloc_count - * sizeof (ElfNN_External_Rela))); - break; - - case DT_IA_64_PLT_RESERVE: - dyn.d_un.d_ptr =3D (sgotplt->output_section->vma - + sgotplt->output_offset); - break; - } - - bfd_elfNN_swap_dyn_out (abfd, &dyn, dyncon); - } - - /* Initialize the PLT0 entry. */ - if (ia64_info->root.splt) - { - bfd_byte *loc =3D ia64_info->root.splt->contents; - bfd_vma pltres; - - memcpy (loc, plt_header, PLT_HEADER_SIZE); - - pltres =3D (sgotplt->output_section->vma - + sgotplt->output_offset - - gp_val); - - ia64_elf_install_value (loc+1, pltres, R_IA64_GPREL22); - } - } - - return true; -} -=0C -/* ELF file flag handling: */ - -/* Function to keep IA-64 specific file flags. */ -static bool -elfNN_ia64_set_private_flags (bfd *abfd, flagword flags) -{ - BFD_ASSERT (!elf_flags_init (abfd) - || elf_elfheader (abfd)->e_flags =3D=3D flags); - - elf_elfheader (abfd)->e_flags =3D flags; - elf_flags_init (abfd) =3D true; - return true; -} - -/* Merge backend specific data from an object file to the output - object file when linking. */ - -static bool -elfNN_ia64_merge_private_bfd_data (bfd *ibfd, struct bfd_link_info *info) -{ - bfd *obfd =3D info->output_bfd; - flagword out_flags; - flagword in_flags; - bool ok =3D true; - - /* FIXME: What should be checked when linking shared libraries? */ - if ((ibfd->flags & DYNAMIC) !=3D 0) - return true; - - if (!is_ia64_elf (ibfd) || !is_ia64_elf (obfd)) - return true; - - in_flags =3D elf_elfheader (ibfd)->e_flags; - out_flags =3D elf_elfheader (obfd)->e_flags; - - if (! elf_flags_init (obfd)) - { - elf_flags_init (obfd) =3D true; - elf_elfheader (obfd)->e_flags =3D in_flags; - - if (bfd_get_arch (obfd) =3D=3D bfd_get_arch (ibfd) - && bfd_get_arch_info (obfd)->the_default) - { - return bfd_set_arch_mach (obfd, bfd_get_arch (ibfd), - bfd_get_mach (ibfd)); - } - - return true; - } - - /* Check flag compatibility. */ - if (in_flags =3D=3D out_flags) - return true; - - /* Output has EF_IA_64_REDUCEDFP set only if all inputs have it set. */ - if (!(in_flags & EF_IA_64_REDUCEDFP) && (out_flags & EF_IA_64_REDUCEDFP)) - elf_elfheader (obfd)->e_flags &=3D ~EF_IA_64_REDUCEDFP; - - if ((in_flags & EF_IA_64_TRAPNIL) !=3D (out_flags & EF_IA_64_TRAPNIL)) - { - _bfd_error_handler - (_("%pB: linking trap-on-NULL-dereference with non-trapping files"), - ibfd); - - bfd_set_error (bfd_error_bad_value); - ok =3D false; - } - if ((in_flags & EF_IA_64_BE) !=3D (out_flags & EF_IA_64_BE)) - { - _bfd_error_handler - (_("%pB: linking big-endian files with little-endian files"), - ibfd); - - bfd_set_error (bfd_error_bad_value); - ok =3D false; - } - if ((in_flags & EF_IA_64_ABI64) !=3D (out_flags & EF_IA_64_ABI64)) - { - _bfd_error_handler - (_("%pB: linking 64-bit files with 32-bit files"), - ibfd); - - bfd_set_error (bfd_error_bad_value); - ok =3D false; - } - if ((in_flags & EF_IA_64_CONS_GP) !=3D (out_flags & EF_IA_64_CONS_GP)) - { - _bfd_error_handler - (_("%pB: linking constant-gp files with non-constant-gp files"), - ibfd); - - bfd_set_error (bfd_error_bad_value); - ok =3D false; - } - if ((in_flags & EF_IA_64_NOFUNCDESC_CONS_GP) - !=3D (out_flags & EF_IA_64_NOFUNCDESC_CONS_GP)) - { - _bfd_error_handler - (_("%pB: linking auto-pic files with non-auto-pic files"), - ibfd); - - bfd_set_error (bfd_error_bad_value); - ok =3D false; - } - - return ok; -} - -static bool -elfNN_ia64_print_private_bfd_data (bfd *abfd, void * ptr) -{ - FILE *file =3D (FILE *) ptr; - flagword flags =3D elf_elfheader (abfd)->e_flags; - - BFD_ASSERT (abfd !=3D NULL && ptr !=3D NULL); - - fprintf (file, "private flags =3D %s%s%s%s%s%s%s%s\n", - (flags & EF_IA_64_TRAPNIL) ? "TRAPNIL, " : "", - (flags & EF_IA_64_EXT) ? "EXT, " : "", - (flags & EF_IA_64_BE) ? "BE, " : "LE, ", - (flags & EF_IA_64_REDUCEDFP) ? "REDUCEDFP, " : "", - (flags & EF_IA_64_CONS_GP) ? "CONS_GP, " : "", - (flags & EF_IA_64_NOFUNCDESC_CONS_GP) ? "NOFUNCDESC_CONS_GP, " : "", - (flags & EF_IA_64_ABSOLUTE) ? "ABSOLUTE, " : "", - (flags & EF_IA_64_ABI64) ? "ABI64" : "ABI32"); - - _bfd_elf_print_private_bfd_data (abfd, ptr); - return true; -} - -static enum elf_reloc_type_class -elfNN_ia64_reloc_type_class (const struct bfd_link_info *info ATTRIBUTE_UN= USED, - const asection *rel_sec ATTRIBUTE_UNUSED, - const Elf_Internal_Rela *rela) -{ - switch ((int) ELFNN_R_TYPE (rela->r_info)) - { - case R_IA64_REL32MSB: - case R_IA64_REL32LSB: - case R_IA64_REL64MSB: - case R_IA64_REL64LSB: - return reloc_class_relative; - case R_IA64_IPLTMSB: - case R_IA64_IPLTLSB: - return reloc_class_plt; - case R_IA64_COPY: - return reloc_class_copy; - default: - return reloc_class_normal; - } -} - -static const struct bfd_elf_special_section elfNN_ia64_special_sections[] = =3D -{ - { STRING_COMMA_LEN (".sbss"), -1, SHT_NOBITS, SHF_ALLOC + SHF_WRITE += SHF_IA_64_SHORT }, - { STRING_COMMA_LEN (".sdata"), -1, SHT_PROGBITS, SHF_ALLOC + SHF_WRITE += SHF_IA_64_SHORT }, - { NULL, 0, 0, 0, 0 } -}; - -static bool -elfNN_ia64_object_p (bfd *abfd) -{ - asection *sec; - asection *group, *unwi, *unw; - flagword flags; - const char *name; - char *unwi_name, *unw_name; - size_t amt; - - if (abfd->flags & DYNAMIC) - return true; - - /* Flags for fake group section. */ - flags =3D (SEC_LINKER_CREATED | SEC_GROUP | SEC_LINK_ONCE - | SEC_EXCLUDE); - - /* We add a fake section group for each .gnu.linkonce.t.* section, - which isn't in a section group, and its unwind sections. */ - for (sec =3D abfd->sections; sec !=3D NULL; sec =3D sec->next) - { - if (elf_sec_group (sec) =3D=3D NULL - && ((sec->flags & (SEC_LINK_ONCE | SEC_CODE | SEC_GROUP)) - =3D=3D (SEC_LINK_ONCE | SEC_CODE)) - && startswith (sec->name, ".gnu.linkonce.t.")) - { - name =3D sec->name + 16; - - amt =3D strlen (name) + sizeof (".gnu.linkonce.ia64unwi."); - unwi_name =3D bfd_alloc (abfd, amt); - if (!unwi_name) - return false; - - strcpy (stpcpy (unwi_name, ".gnu.linkonce.ia64unwi."), name); - unwi =3D bfd_get_section_by_name (abfd, unwi_name); - - amt =3D strlen (name) + sizeof (".gnu.linkonce.ia64unw."); - unw_name =3D bfd_alloc (abfd, amt); - if (!unw_name) - return false; - - strcpy (stpcpy (unw_name, ".gnu.linkonce.ia64unw."), name); - unw =3D bfd_get_section_by_name (abfd, unw_name); - - /* We need to create a fake group section for it and its - unwind sections. */ - group =3D bfd_make_section_anyway_with_flags (abfd, name, - flags); - if (group =3D=3D NULL) - return false; - - /* Move the fake group section to the beginning. */ - bfd_section_list_remove (abfd, group); - bfd_section_list_prepend (abfd, group); - - elf_next_in_group (group) =3D sec; - - elf_group_name (sec) =3D name; - elf_next_in_group (sec) =3D sec; - elf_sec_group (sec) =3D group; - - if (unwi) - { - elf_group_name (unwi) =3D name; - elf_next_in_group (unwi) =3D sec; - elf_next_in_group (sec) =3D unwi; - elf_sec_group (unwi) =3D group; - } - - if (unw) - { - elf_group_name (unw) =3D name; - if (unwi) - { - elf_next_in_group (unw) =3D elf_next_in_group (unwi); - elf_next_in_group (unwi) =3D unw; - } - else - { - elf_next_in_group (unw) =3D sec; - elf_next_in_group (sec) =3D unw; - } - elf_sec_group (unw) =3D group; - } - - /* Fake SHT_GROUP section header. */ - elf_section_data (group)->this_hdr.bfd_section =3D group; - elf_section_data (group)->this_hdr.sh_type =3D SHT_GROUP; - } - } - return true; -} - -static bool -elfNN_ia64_hpux_vec (const bfd_target *vec) -{ - extern const bfd_target ia64_elfNN_hpux_be_vec; - return (vec =3D=3D &ia64_elfNN_hpux_be_vec); -} - -static bool -elfNN_hpux_init_file_header (bfd *abfd, struct bfd_link_info *info) -{ - Elf_Internal_Ehdr *i_ehdrp; - - if (!_bfd_elf_init_file_header (abfd, info)) - return false; - - i_ehdrp =3D elf_elfheader (abfd); - i_ehdrp->e_ident[EI_OSABI] =3D get_elf_backend_data (abfd)->elf_osabi; - i_ehdrp->e_ident[EI_ABIVERSION] =3D 1; - return true; -} - -static bool -elfNN_hpux_backend_section_from_bfd_section (bfd *abfd ATTRIBUTE_UNUSED, - asection *sec, int *retval) -{ - if (bfd_is_com_section (sec)) - { - *retval =3D SHN_IA_64_ANSI_COMMON; - return true; - } - return false; -} - -static void -elfNN_hpux_backend_symbol_processing (bfd *abfd ATTRIBUTE_UNUSED, - asymbol *asym) -{ - elf_symbol_type *elfsym =3D (elf_symbol_type *) asym; - - switch (elfsym->internal_elf_sym.st_shndx) - { - case SHN_IA_64_ANSI_COMMON: - asym->section =3D bfd_com_section_ptr; - asym->value =3D elfsym->internal_elf_sym.st_size; - asym->flags &=3D ~BSF_GLOBAL; - break; - } -} - -static void -ignore_errors (const char *fmt ATTRIBUTE_UNUSED, ...) -{ -} -=0C -#define TARGET_LITTLE_SYM ia64_elfNN_le_vec -#define TARGET_LITTLE_NAME "elfNN-ia64-little" -#define TARGET_BIG_SYM ia64_elfNN_be_vec -#define TARGET_BIG_NAME "elfNN-ia64-big" -#define ELF_ARCH bfd_arch_ia64 -#define ELF_TARGET_ID IA64_ELF_DATA -#define ELF_MACHINE_CODE EM_IA_64 -#define ELF_MACHINE_ALT1 1999 /* EAS2.3 */ -#define ELF_MACHINE_ALT2 1998 /* EAS2.2 */ -#define ELF_MAXPAGESIZE 0x10000 /* 64KB */ -#define ELF_COMMONPAGESIZE 0x4000 /* 16KB */ - -#define elf_backend_section_from_shdr \ - elfNN_ia64_section_from_shdr -#define elf_backend_section_flags \ - elfNN_ia64_section_flags -#define elf_backend_fake_sections \ - elfNN_ia64_fake_sections -#define elf_backend_final_write_processing \ - elfNN_ia64_final_write_processing -#define elf_backend_add_symbol_hook \ - elfNN_ia64_add_symbol_hook -#define elf_backend_additional_program_headers \ - elfNN_ia64_additional_program_headers -#define elf_backend_modify_segment_map \ - elfNN_ia64_modify_segment_map -#define elf_backend_modify_headers \ - elfNN_ia64_modify_headers -#define elf_info_to_howto \ - elfNN_ia64_info_to_howto - -#define bfd_elfNN_bfd_reloc_type_lookup \ - ia64_elf_reloc_type_lookup -#define bfd_elfNN_bfd_reloc_name_lookup \ - ia64_elf_reloc_name_lookup -#define bfd_elfNN_bfd_is_local_label_name \ - elfNN_ia64_is_local_label_name -#define bfd_elfNN_bfd_relax_section \ - elfNN_ia64_relax_section - -#define elf_backend_object_p \ - elfNN_ia64_object_p - -/* Stuff for the BFD linker: */ -#define bfd_elfNN_bfd_link_hash_table_create \ - elfNN_ia64_hash_table_create -#define elf_backend_create_dynamic_sections \ - elfNN_ia64_create_dynamic_sections -#define elf_backend_check_relocs \ - elfNN_ia64_check_relocs -#define elf_backend_adjust_dynamic_symbol \ - elfNN_ia64_adjust_dynamic_symbol -#define elf_backend_late_size_sections \ - elfNN_ia64_late_size_sections -#define elf_backend_omit_section_dynsym \ - _bfd_elf_omit_section_dynsym_all -#define elf_backend_relocate_section \ - elfNN_ia64_relocate_section -#define elf_backend_finish_dynamic_symbol \ - elfNN_ia64_finish_dynamic_symbol -#define elf_backend_finish_dynamic_sections \ - elfNN_ia64_finish_dynamic_sections -#define bfd_elfNN_bfd_final_link \ - elfNN_ia64_final_link - -#define bfd_elfNN_bfd_merge_private_bfd_data \ - elfNN_ia64_merge_private_bfd_data -#define bfd_elfNN_bfd_set_private_flags \ - elfNN_ia64_set_private_flags -#define bfd_elfNN_bfd_print_private_bfd_data \ - elfNN_ia64_print_private_bfd_data - -#define elf_backend_plt_readonly 1 -#define elf_backend_can_gc_sections 1 -#define elf_backend_want_plt_sym 0 -#define elf_backend_plt_alignment 5 -#define elf_backend_got_header_size 0 -#define elf_backend_want_got_plt 1 -#define elf_backend_may_use_rel_p 1 -#define elf_backend_may_use_rela_p 1 -#define elf_backend_default_use_rela_p 1 -#define elf_backend_want_dynbss 0 -#define elf_backend_copy_indirect_symbol elfNN_ia64_hash_copy_indirect -#define elf_backend_hide_symbol elfNN_ia64_hash_hide_symbol -#define elf_backend_fixup_symbol _bfd_elf_link_hash_fixup_symbol -#define elf_backend_reloc_type_class elfNN_ia64_reloc_type_class -#define elf_backend_rela_normal 1 -#define elf_backend_dtrel_excludes_plt 1 -#define elf_backend_special_sections elfNN_ia64_special_sections -#define elf_backend_default_execstack 0 - -/* FIXME: PR 290: The Intel C compiler generates SHT_IA_64_UNWIND with - SHF_LINK_ORDER. But it doesn't set the sh_link or sh_info fields. - We don't want to flood users with so many error messages. We turn - off the warning for now. It will be turned on later when the Intel - compiler is fixed. */ -#define elf_backend_link_order_error_handler ignore_errors - -#include "elfNN-target.h" - -/* HPUX-specific vectors. */ - -#undef TARGET_LITTLE_SYM -#undef TARGET_LITTLE_NAME -#undef TARGET_BIG_SYM -#define TARGET_BIG_SYM ia64_elfNN_hpux_be_vec -#undef TARGET_BIG_NAME -#define TARGET_BIG_NAME "elfNN-ia64-hpux-big" - -/* These are HP-UX specific functions. */ - -#undef elf_backend_init_file_header -#define elf_backend_init_file_header elfNN_hpux_init_file_header - -#undef elf_backend_section_from_bfd_section -#define elf_backend_section_from_bfd_section elfNN_hpux_backend_section_fr= om_bfd_section - -#undef elf_backend_symbol_processing -#define elf_backend_symbol_processing elfNN_hpux_backend_symbol_processing - -#undef elf_backend_want_p_paddr_set_to_zero -#define elf_backend_want_p_paddr_set_to_zero 1 - -#undef ELF_COMMONPAGESIZE -#undef ELF_OSABI -#define ELF_OSABI ELFOSABI_HPUX - -#undef elfNN_bed -#define elfNN_bed elfNN_ia64_hpux_bed - -#include "elfNN-target.h" diff --git a/bfd/elfxx-ia64.c b/bfd/elfxx-ia64.c deleted file mode 100644 index 643145e1654..00000000000 --- a/bfd/elfxx-ia64.c +++ /dev/null @@ -1,764 +0,0 @@ -/* IA-64 support for 64-bit ELF - Copyright (C) 1998-2024 Free Software Foundation, Inc. - Contributed by David Mosberger-Tang - - This file is part of BFD, the Binary File Descriptor library. - - This program is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - This program is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program; if not, write to the Free Software - Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, - MA 02110-1301, USA. */ - -#include "sysdep.h" -#include "bfd.h" -#include "libbfd.h" -#include "elf-bfd.h" -#include "opcode/ia64.h" -#include "elf/ia64.h" -#include "objalloc.h" -#include "hashtab.h" -#include "elfxx-ia64.h" - -/* THE RULES for all the stuff the linker creates -- - - GOT Entries created in response to LTOFF or LTOFF_FPTR - relocations. Dynamic relocs created for dynamic - symbols in an application; REL relocs for locals - in a shared library. - - FPTR The canonical function descriptor. Created for local - symbols in applications. Descriptors for dynamic symbols - and local symbols in shared libraries are created by - ld.so. Thus there are no dynamic relocs against these - objects. The FPTR relocs for such _are_ passed through - to the dynamic relocation tables. - - FULL_PLT Created for a PCREL21B relocation against a dynamic symbol. - Requires the creation of a PLTOFF entry. This does not - require any dynamic relocations. - - PLTOFF Created by PLTOFF relocations. For local symbols, this - is an alternate function descriptor, and in shared libraries - requires two REL relocations. Note that this cannot be - transformed into an FPTR relocation, since it must be in - range of the GP. For dynamic symbols, this is a function - descriptor for a MIN_PLT entry, and requires one IPLT reloc. - - MIN_PLT Created by PLTOFF entries against dynamic symbols. This - does not require dynamic relocations. */ - -/* ia64-specific relocation. */ - -#define NELEMS(a) ((int) (sizeof (a) / sizeof ((a)[0]))) - -/* Perform a relocation. Not much to do here as all the hard work is - done in elfNN_ia64_final_link_relocate. */ -static bfd_reloc_status_type -ia64_elf_reloc (bfd *abfd ATTRIBUTE_UNUSED, arelent *reloc, - asymbol *sym ATTRIBUTE_UNUSED, - void *data ATTRIBUTE_UNUSED, asection *input_section, - bfd *output_bfd, char **error_message) -{ - if (output_bfd) - { - reloc->address +=3D input_section->output_offset; - return bfd_reloc_ok; - } - - if (input_section->flags & SEC_DEBUGGING) - return bfd_reloc_continue; - - *error_message =3D "Unsupported call to ia64_elf_reloc"; - return bfd_reloc_notsupported; -} - -#define IA64_HOWTO(TYPE, NAME, SIZE, PCREL, IN) \ - HOWTO (TYPE, 0, SIZE, 0, PCREL, 0, complain_overflow_signed, \ - ia64_elf_reloc, NAME, false, 0, -1, IN) - -/* This table has to be sorted according to increasing number of the - TYPE field. */ -static reloc_howto_type ia64_howto_table[] =3D - { - IA64_HOWTO (R_IA64_NONE, "NONE", 0, false, true), - - IA64_HOWTO (R_IA64_IMM14, "IMM14", 1, false, true), - IA64_HOWTO (R_IA64_IMM22, "IMM22", 1, false, true), - IA64_HOWTO (R_IA64_IMM64, "IMM64", 1, false, true), - IA64_HOWTO (R_IA64_DIR32MSB, "DIR32MSB", 4, false, true), - IA64_HOWTO (R_IA64_DIR32LSB, "DIR32LSB", 4, false, true), - IA64_HOWTO (R_IA64_DIR64MSB, "DIR64MSB", 8, false, true), - IA64_HOWTO (R_IA64_DIR64LSB, "DIR64LSB", 8, false, true), - - IA64_HOWTO (R_IA64_GPREL22, "GPREL22", 1, false, true), - IA64_HOWTO (R_IA64_GPREL64I, "GPREL64I", 1, false, true), - IA64_HOWTO (R_IA64_GPREL32MSB, "GPREL32MSB", 4, false, true), - IA64_HOWTO (R_IA64_GPREL32LSB, "GPREL32LSB", 4, false, true), - IA64_HOWTO (R_IA64_GPREL64MSB, "GPREL64MSB", 8, false, true), - IA64_HOWTO (R_IA64_GPREL64LSB, "GPREL64LSB", 8, false, true), - - IA64_HOWTO (R_IA64_LTOFF22, "LTOFF22", 1, false, true), - IA64_HOWTO (R_IA64_LTOFF64I, "LTOFF64I", 1, false, true), - - IA64_HOWTO (R_IA64_PLTOFF22, "PLTOFF22", 1, false, true), - IA64_HOWTO (R_IA64_PLTOFF64I, "PLTOFF64I", 1, false, true), - IA64_HOWTO (R_IA64_PLTOFF64MSB, "PLTOFF64MSB", 8, false, true), - IA64_HOWTO (R_IA64_PLTOFF64LSB, "PLTOFF64LSB", 8, false, true), - - IA64_HOWTO (R_IA64_FPTR64I, "FPTR64I", 1, false, true), - IA64_HOWTO (R_IA64_FPTR32MSB, "FPTR32MSB", 4, false, true), - IA64_HOWTO (R_IA64_FPTR32LSB, "FPTR32LSB", 4, false, true), - IA64_HOWTO (R_IA64_FPTR64MSB, "FPTR64MSB", 8, false, true), - IA64_HOWTO (R_IA64_FPTR64LSB, "FPTR64LSB", 8, false, true), - - IA64_HOWTO (R_IA64_PCREL60B, "PCREL60B", 1, true, true), - IA64_HOWTO (R_IA64_PCREL21B, "PCREL21B", 1, true, true), - IA64_HOWTO (R_IA64_PCREL21M, "PCREL21M", 1, true, true), - IA64_HOWTO (R_IA64_PCREL21F, "PCREL21F", 1, true, true), - IA64_HOWTO (R_IA64_PCREL32MSB, "PCREL32MSB", 4, true, true), - IA64_HOWTO (R_IA64_PCREL32LSB, "PCREL32LSB", 4, true, true), - IA64_HOWTO (R_IA64_PCREL64MSB, "PCREL64MSB", 8, true, true), - IA64_HOWTO (R_IA64_PCREL64LSB, "PCREL64LSB", 8, true, true), - - IA64_HOWTO (R_IA64_LTOFF_FPTR22, "LTOFF_FPTR22", 1, false, true), - IA64_HOWTO (R_IA64_LTOFF_FPTR64I, "LTOFF_FPTR64I", 1, false, true), - IA64_HOWTO (R_IA64_LTOFF_FPTR32MSB, "LTOFF_FPTR32MSB", 4, false, true), - IA64_HOWTO (R_IA64_LTOFF_FPTR32LSB, "LTOFF_FPTR32LSB", 4, false, true), - IA64_HOWTO (R_IA64_LTOFF_FPTR64MSB, "LTOFF_FPTR64MSB", 8, false, true), - IA64_HOWTO (R_IA64_LTOFF_FPTR64LSB, "LTOFF_FPTR64LSB", 8, false, true), - - IA64_HOWTO (R_IA64_SEGREL32MSB, "SEGREL32MSB", 4, false, true), - IA64_HOWTO (R_IA64_SEGREL32LSB, "SEGREL32LSB", 4, false, true), - IA64_HOWTO (R_IA64_SEGREL64MSB, "SEGREL64MSB", 8, false, true), - IA64_HOWTO (R_IA64_SEGREL64LSB, "SEGREL64LSB", 8, false, true), - - IA64_HOWTO (R_IA64_SECREL32MSB, "SECREL32MSB", 4, false, true), - IA64_HOWTO (R_IA64_SECREL32LSB, "SECREL32LSB", 4, false, true), - IA64_HOWTO (R_IA64_SECREL64MSB, "SECREL64MSB", 8, false, true), - IA64_HOWTO (R_IA64_SECREL64LSB, "SECREL64LSB", 8, false, true), - - IA64_HOWTO (R_IA64_REL32MSB, "REL32MSB", 4, false, true), - IA64_HOWTO (R_IA64_REL32LSB, "REL32LSB", 4, false, true), - IA64_HOWTO (R_IA64_REL64MSB, "REL64MSB", 8, false, true), - IA64_HOWTO (R_IA64_REL64LSB, "REL64LSB", 8, false, true), - - IA64_HOWTO (R_IA64_LTV32MSB, "LTV32MSB", 4, false, true), - IA64_HOWTO (R_IA64_LTV32LSB, "LTV32LSB", 4, false, true), - IA64_HOWTO (R_IA64_LTV64MSB, "LTV64MSB", 8, false, true), - IA64_HOWTO (R_IA64_LTV64LSB, "LTV64LSB", 8, false, true), - - IA64_HOWTO (R_IA64_PCREL21BI, "PCREL21BI", 1, true, true), - IA64_HOWTO (R_IA64_PCREL22, "PCREL22", 1, true, true), - IA64_HOWTO (R_IA64_PCREL64I, "PCREL64I", 1, true, true), - - IA64_HOWTO (R_IA64_IPLTMSB, "IPLTMSB", 8, false, true), - IA64_HOWTO (R_IA64_IPLTLSB, "IPLTLSB", 8, false, true), - IA64_HOWTO (R_IA64_COPY, "COPY", 8, false, true), - IA64_HOWTO (R_IA64_LTOFF22X, "LTOFF22X", 1, false, true), - IA64_HOWTO (R_IA64_LDXMOV, "LDXMOV", 1, false, true), - - IA64_HOWTO (R_IA64_TPREL14, "TPREL14", 1, false, false), - IA64_HOWTO (R_IA64_TPREL22, "TPREL22", 1, false, false), - IA64_HOWTO (R_IA64_TPREL64I, "TPREL64I", 1, false, false), - IA64_HOWTO (R_IA64_TPREL64MSB, "TPREL64MSB", 8, false, false), - IA64_HOWTO (R_IA64_TPREL64LSB, "TPREL64LSB", 8, false, false), - IA64_HOWTO (R_IA64_LTOFF_TPREL22, "LTOFF_TPREL22", 1, false, false), - - IA64_HOWTO (R_IA64_DTPMOD64MSB, "DTPMOD64MSB", 8, false, false), - IA64_HOWTO (R_IA64_DTPMOD64LSB, "DTPMOD64LSB", 8, false, false), - IA64_HOWTO (R_IA64_LTOFF_DTPMOD22, "LTOFF_DTPMOD22", 1, false, false), - - IA64_HOWTO (R_IA64_DTPREL14, "DTPREL14", 1, false, false), - IA64_HOWTO (R_IA64_DTPREL22, "DTPREL22", 1, false, false), - IA64_HOWTO (R_IA64_DTPREL64I, "DTPREL64I", 1, false, false), - IA64_HOWTO (R_IA64_DTPREL32MSB, "DTPREL32MSB", 4, false, false), - IA64_HOWTO (R_IA64_DTPREL32LSB, "DTPREL32LSB", 4, false, false), - IA64_HOWTO (R_IA64_DTPREL64MSB, "DTPREL64MSB", 8, false, false), - IA64_HOWTO (R_IA64_DTPREL64LSB, "DTPREL64LSB", 8, false, false), - IA64_HOWTO (R_IA64_LTOFF_DTPREL22, "LTOFF_DTPREL22", 1, false, false), - }; - -static unsigned char elf_code_to_howto_index[R_IA64_MAX_RELOC_CODE + 1]; - -/* Given a BFD reloc type, return the matching HOWTO structure. */ - -reloc_howto_type * -ia64_elf_lookup_howto (unsigned int rtype) -{ - static bool inited =3D false; - int i; - - if (!inited) - { - inited =3D true; - - memset (elf_code_to_howto_index, 0xff, sizeof (elf_code_to_howto_ind= ex)); - for (i =3D 0; i < NELEMS (ia64_howto_table); ++i) - elf_code_to_howto_index[ia64_howto_table[i].type] =3D i; - } - - if (rtype > R_IA64_MAX_RELOC_CODE) - return NULL; - i =3D elf_code_to_howto_index[rtype]; - if (i >=3D NELEMS (ia64_howto_table)) - return NULL; - return ia64_howto_table + i; -} - -reloc_howto_type * -ia64_elf_reloc_type_lookup (bfd *abfd, - bfd_reloc_code_real_type bfd_code) -{ - unsigned int rtype; - - switch (bfd_code) - { - case BFD_RELOC_NONE: rtype =3D R_IA64_NONE; break; - - case BFD_RELOC_IA64_IMM14: rtype =3D R_IA64_IMM14; break; - case BFD_RELOC_IA64_IMM22: rtype =3D R_IA64_IMM22; break; - case BFD_RELOC_IA64_IMM64: rtype =3D R_IA64_IMM64; break; - - case BFD_RELOC_IA64_DIR32MSB: rtype =3D R_IA64_DIR32MSB; break; - case BFD_RELOC_IA64_DIR32LSB: rtype =3D R_IA64_DIR32LSB; break; - case BFD_RELOC_IA64_DIR64MSB: rtype =3D R_IA64_DIR64MSB; break; - case BFD_RELOC_IA64_DIR64LSB: rtype =3D R_IA64_DIR64LSB; break; - - case BFD_RELOC_IA64_GPREL22: rtype =3D R_IA64_GPREL22; break; - case BFD_RELOC_IA64_GPREL64I: rtype =3D R_IA64_GPREL64I; break; - case BFD_RELOC_IA64_GPREL32MSB: rtype =3D R_IA64_GPREL32MSB; break; - case BFD_RELOC_IA64_GPREL32LSB: rtype =3D R_IA64_GPREL32LSB; break; - case BFD_RELOC_IA64_GPREL64MSB: rtype =3D R_IA64_GPREL64MSB; break; - case BFD_RELOC_IA64_GPREL64LSB: rtype =3D R_IA64_GPREL64LSB; break; - - case BFD_RELOC_IA64_LTOFF22: rtype =3D R_IA64_LTOFF22; break; - case BFD_RELOC_IA64_LTOFF64I: rtype =3D R_IA64_LTOFF64I; break; - - case BFD_RELOC_IA64_PLTOFF22: rtype =3D R_IA64_PLTOFF22; break; - case BFD_RELOC_IA64_PLTOFF64I: rtype =3D R_IA64_PLTOFF64I; break; - case BFD_RELOC_IA64_PLTOFF64MSB: rtype =3D R_IA64_PLTOFF64MSB; break; - case BFD_RELOC_IA64_PLTOFF64LSB: rtype =3D R_IA64_PLTOFF64LSB; break; - case BFD_RELOC_IA64_FPTR64I: rtype =3D R_IA64_FPTR64I; break; - case BFD_RELOC_IA64_FPTR32MSB: rtype =3D R_IA64_FPTR32MSB; break; - case BFD_RELOC_IA64_FPTR32LSB: rtype =3D R_IA64_FPTR32LSB; break; - case BFD_RELOC_IA64_FPTR64MSB: rtype =3D R_IA64_FPTR64MSB; break; - case BFD_RELOC_IA64_FPTR64LSB: rtype =3D R_IA64_FPTR64LSB; break; - - case BFD_RELOC_IA64_PCREL21B: rtype =3D R_IA64_PCREL21B; break; - case BFD_RELOC_IA64_PCREL21BI: rtype =3D R_IA64_PCREL21BI; break; - case BFD_RELOC_IA64_PCREL21M: rtype =3D R_IA64_PCREL21M; break; - case BFD_RELOC_IA64_PCREL21F: rtype =3D R_IA64_PCREL21F; break; - case BFD_RELOC_IA64_PCREL22: rtype =3D R_IA64_PCREL22; break; - case BFD_RELOC_IA64_PCREL60B: rtype =3D R_IA64_PCREL60B; break; - case BFD_RELOC_IA64_PCREL64I: rtype =3D R_IA64_PCREL64I; break; - case BFD_RELOC_IA64_PCREL32MSB: rtype =3D R_IA64_PCREL32MSB; break; - case BFD_RELOC_IA64_PCREL32LSB: rtype =3D R_IA64_PCREL32LSB; break; - case BFD_RELOC_IA64_PCREL64MSB: rtype =3D R_IA64_PCREL64MSB; break; - case BFD_RELOC_IA64_PCREL64LSB: rtype =3D R_IA64_PCREL64LSB; break; - - case BFD_RELOC_IA64_LTOFF_FPTR22: rtype =3D R_IA64_LTOFF_FPTR22; break; - case BFD_RELOC_IA64_LTOFF_FPTR64I: rtype =3D R_IA64_LTOFF_FPTR64I; bre= ak; - case BFD_RELOC_IA64_LTOFF_FPTR32MSB: rtype =3D R_IA64_LTOFF_FPTR32MSB;= break; - case BFD_RELOC_IA64_LTOFF_FPTR32LSB: rtype =3D R_IA64_LTOFF_FPTR32LSB;= break; - case BFD_RELOC_IA64_LTOFF_FPTR64MSB: rtype =3D R_IA64_LTOFF_FPTR64MSB;= break; - case BFD_RELOC_IA64_LTOFF_FPTR64LSB: rtype =3D R_IA64_LTOFF_FPTR64LSB;= break; - - case BFD_RELOC_IA64_SEGREL32MSB: rtype =3D R_IA64_SEGREL32MSB; break; - case BFD_RELOC_IA64_SEGREL32LSB: rtype =3D R_IA64_SEGREL32LSB; break; - case BFD_RELOC_IA64_SEGREL64MSB: rtype =3D R_IA64_SEGREL64MSB; break; - case BFD_RELOC_IA64_SEGREL64LSB: rtype =3D R_IA64_SEGREL64LSB; break; - - case BFD_RELOC_IA64_SECREL32MSB: rtype =3D R_IA64_SECREL32MSB; break; - case BFD_RELOC_IA64_SECREL32LSB: rtype =3D R_IA64_SECREL32LSB; break; - case BFD_RELOC_IA64_SECREL64MSB: rtype =3D R_IA64_SECREL64MSB; break; - case BFD_RELOC_IA64_SECREL64LSB: rtype =3D R_IA64_SECREL64LSB; break; - - case BFD_RELOC_IA64_REL32MSB: rtype =3D R_IA64_REL32MSB; break; - case BFD_RELOC_IA64_REL32LSB: rtype =3D R_IA64_REL32LSB; break; - case BFD_RELOC_IA64_REL64MSB: rtype =3D R_IA64_REL64MSB; break; - case BFD_RELOC_IA64_REL64LSB: rtype =3D R_IA64_REL64LSB; break; - - case BFD_RELOC_IA64_LTV32MSB: rtype =3D R_IA64_LTV32MSB; break; - case BFD_RELOC_IA64_LTV32LSB: rtype =3D R_IA64_LTV32LSB; break; - case BFD_RELOC_IA64_LTV64MSB: rtype =3D R_IA64_LTV64MSB; break; - case BFD_RELOC_IA64_LTV64LSB: rtype =3D R_IA64_LTV64LSB; break; - - case BFD_RELOC_IA64_IPLTMSB: rtype =3D R_IA64_IPLTMSB; break; - case BFD_RELOC_IA64_IPLTLSB: rtype =3D R_IA64_IPLTLSB; break; - case BFD_RELOC_IA64_COPY: rtype =3D R_IA64_COPY; break; - case BFD_RELOC_IA64_LTOFF22X: rtype =3D R_IA64_LTOFF22X; break; - case BFD_RELOC_IA64_LDXMOV: rtype =3D R_IA64_LDXMOV; break; - - case BFD_RELOC_IA64_TPREL14: rtype =3D R_IA64_TPREL14; break; - case BFD_RELOC_IA64_TPREL22: rtype =3D R_IA64_TPREL22; break; - case BFD_RELOC_IA64_TPREL64I: rtype =3D R_IA64_TPREL64I; break; - case BFD_RELOC_IA64_TPREL64MSB: rtype =3D R_IA64_TPREL64MSB; break; - case BFD_RELOC_IA64_TPREL64LSB: rtype =3D R_IA64_TPREL64LSB; break; - case BFD_RELOC_IA64_LTOFF_TPREL22: rtype =3D R_IA64_LTOFF_TPREL22; bre= ak; - - case BFD_RELOC_IA64_DTPMOD64MSB: rtype =3D R_IA64_DTPMOD64MSB; break; - case BFD_RELOC_IA64_DTPMOD64LSB: rtype =3D R_IA64_DTPMOD64LSB; break; - case BFD_RELOC_IA64_LTOFF_DTPMOD22: rtype =3D R_IA64_LTOFF_DTPMOD22; b= reak; - - case BFD_RELOC_IA64_DTPREL14: rtype =3D R_IA64_DTPREL14; break; - case BFD_RELOC_IA64_DTPREL22: rtype =3D R_IA64_DTPREL22; break; - case BFD_RELOC_IA64_DTPREL64I: rtype =3D R_IA64_DTPREL64I; break; - case BFD_RELOC_IA64_DTPREL32MSB: rtype =3D R_IA64_DTPREL32MSB; break; - case BFD_RELOC_IA64_DTPREL32LSB: rtype =3D R_IA64_DTPREL32LSB; break; - case BFD_RELOC_IA64_DTPREL64MSB: rtype =3D R_IA64_DTPREL64MSB; break; - case BFD_RELOC_IA64_DTPREL64LSB: rtype =3D R_IA64_DTPREL64LSB; break; - case BFD_RELOC_IA64_LTOFF_DTPREL22: rtype =3D R_IA64_LTOFF_DTPREL22; b= reak; - - default: - /* xgettext:c-format */ - _bfd_error_handler (_("%pB: unsupported relocation type %#x"), - abfd, (int) bfd_code); - bfd_set_error (bfd_error_bad_value); - return NULL; - } - return ia64_elf_lookup_howto (rtype); -} - -reloc_howto_type * -ia64_elf_reloc_name_lookup (bfd *abfd ATTRIBUTE_UNUSED, - const char *r_name) -{ - unsigned int i; - - for (i =3D 0; - i < sizeof (ia64_howto_table) / sizeof (ia64_howto_table[0]); - i++) - if (ia64_howto_table[i].name !=3D NULL - && strcasecmp (ia64_howto_table[i].name, r_name) =3D=3D 0) - return &ia64_howto_table[i]; - - return NULL; -} - -#define BTYPE_SHIFT 6 -#define Y_SHIFT 26 -#define X6_SHIFT 27 -#define X4_SHIFT 27 -#define X3_SHIFT 33 -#define X2_SHIFT 31 -#define X_SHIFT 33 -#define OPCODE_SHIFT 37 - -#define OPCODE_BITS (0xfLL << OPCODE_SHIFT) -#define X6_BITS (0x3fLL << X6_SHIFT) -#define X4_BITS (0xfLL << X4_SHIFT) -#define X3_BITS (0x7LL << X3_SHIFT) -#define X2_BITS (0x3LL << X2_SHIFT) -#define X_BITS (0x1LL << X_SHIFT) -#define Y_BITS (0x1LL << Y_SHIFT) -#define BTYPE_BITS (0x7LL << BTYPE_SHIFT) -#define PREDICATE_BITS (0x3fLL) - -#define IS_NOP_B(i) \ - (((i) & (OPCODE_BITS | X6_BITS)) =3D=3D (2LL << OPCODE_SHIFT)) -#define IS_NOP_F(i) \ - (((i) & (OPCODE_BITS | X_BITS | X6_BITS | Y_BITS)) \ - =3D=3D (0x1LL << X6_SHIFT)) -#define IS_NOP_I(i) \ - (((i) & (OPCODE_BITS | X3_BITS | X6_BITS | Y_BITS)) \ - =3D=3D (0x1LL << X6_SHIFT)) -#define IS_NOP_M(i) \ - (((i) & (OPCODE_BITS | X3_BITS | X2_BITS | X4_BITS | Y_BITS)) \ - =3D=3D (0x1LL << X4_SHIFT)) -#define IS_BR_COND(i) \ - (((i) & (OPCODE_BITS | BTYPE_BITS)) =3D=3D (0x4LL << OPCODE_SHIFT)) -#define IS_BR_CALL(i) \ - (((i) & OPCODE_BITS) =3D=3D (0x5LL << OPCODE_SHIFT)) - -bool -ia64_elf_relax_br (bfd_byte *contents, bfd_vma off) -{ - unsigned int template_val, mlx; - bfd_vma t0, t1, s0, s1, s2, br_code; - long br_slot; - bfd_byte *hit_addr; - - hit_addr =3D (bfd_byte *) (contents + off); - br_slot =3D (intptr_t) hit_addr & 0x3; - hit_addr -=3D br_slot; - t0 =3D bfd_getl64 (hit_addr + 0); - t1 =3D bfd_getl64 (hit_addr + 8); - - /* Check if we can turn br into brl. A label is always at the start - of the bundle. Even if there are predicates on NOPs, we still - perform this optimization. */ - template_val =3D t0 & 0x1e; - s0 =3D (t0 >> 5) & 0x1ffffffffffLL; - s1 =3D ((t0 >> 46) | (t1 << 18)) & 0x1ffffffffffLL; - s2 =3D (t1 >> 23) & 0x1ffffffffffLL; - switch (br_slot) - { - case 0: - /* Check if slot 1 and slot 2 are NOPs. Possible template is - BBB. We only need to check nop.b. */ - if (!(IS_NOP_B (s1) && IS_NOP_B (s2))) - return false; - br_code =3D s0; - break; - case 1: - /* Check if slot 2 is NOP. Possible templates are MBB and BBB. - For BBB, slot 0 also has to be nop.b. */ - if (!((template_val =3D=3D 0x12 /* MBB */ - && IS_NOP_B (s2)) - || (template_val =3D=3D 0x16 /* BBB */ - && IS_NOP_B (s0) - && IS_NOP_B (s2)))) - return false; - br_code =3D s1; - break; - case 2: - /* Check if slot 1 is NOP. Possible templates are MIB, MBB, BBB, - MMB and MFB. For BBB, slot 0 also has to be nop.b. */ - if (!((template_val =3D=3D 0x10 /* MIB */ - && IS_NOP_I (s1)) - || (template_val =3D=3D 0x12 /* MBB */ - && IS_NOP_B (s1)) - || (template_val =3D=3D 0x16 /* BBB */ - && IS_NOP_B (s0) - && IS_NOP_B (s1)) - || (template_val =3D=3D 0x18 /* MMB */ - && IS_NOP_M (s1)) - || (template_val =3D=3D 0x1c /* MFB */ - && IS_NOP_F (s1)))) - return false; - br_code =3D s2; - break; - default: - /* It should never happen. */ - abort (); - } - - /* We can turn br.cond/br.call into brl.cond/brl.call. */ - if (!(IS_BR_COND (br_code) || IS_BR_CALL (br_code))) - return false; - - /* Turn br into brl by setting bit 40. */ - br_code |=3D 0x1LL << 40; - - /* Turn the old bundle into a MLX bundle with the same stop-bit - variety. */ - if (t0 & 0x1) - mlx =3D 0x5; - else - mlx =3D 0x4; - - if (template_val =3D=3D 0x16) - { - /* For BBB, we need to put nop.m in slot 0. We keep the original - predicate only if slot 0 isn't br. */ - if (br_slot =3D=3D 0) - t0 =3D 0LL; - else - t0 &=3D PREDICATE_BITS << 5; - t0 |=3D 0x1LL << (X4_SHIFT + 5); - } - else - { - /* Keep the original instruction in slot 0. */ - t0 &=3D 0x1ffffffffffLL << 5; - } - - t0 |=3D mlx; - - /* Put brl in slot 1. */ - t1 =3D br_code << 23; - - bfd_putl64 (t0, hit_addr); - bfd_putl64 (t1, hit_addr + 8); - return true; -} - -void -ia64_elf_relax_brl (bfd_byte *contents, bfd_vma off) -{ - int template_val; - bfd_byte *hit_addr; - bfd_vma t0, t1, i0, i1, i2; - - hit_addr =3D (bfd_byte *) (contents + off); - hit_addr -=3D (intptr_t) hit_addr & 0x3; - t0 =3D bfd_getl64 (hit_addr); - t1 =3D bfd_getl64 (hit_addr + 8); - - /* Keep the instruction in slot 0. */ - i0 =3D (t0 >> 5) & 0x1ffffffffffLL; - /* Use nop.b for slot 1. */ - i1 =3D 0x4000000000LL; - /* For slot 2, turn brl into br by masking out bit 40. */ - i2 =3D (t1 >> 23) & 0x0ffffffffffLL; - - /* Turn a MLX bundle into a MBB bundle with the same stop-bit - variety. */ - if (t0 & 0x1) - template_val =3D 0x13; - else - template_val =3D 0x12; - t0 =3D (i1 << 46) | (i0 << 5) | template_val; - t1 =3D (i2 << 23) | (i1 >> 18); - - bfd_putl64 (t0, hit_addr); - bfd_putl64 (t1, hit_addr + 8); -} - -void -ia64_elf_relax_ldxmov (bfd_byte *contents, bfd_vma off) -{ - int shift, r1, r3; - bfd_vma dword, insn; - - switch ((int)off & 0x3) - { - case 0: shift =3D 5; break; - case 1: shift =3D 14; off +=3D 3; break; - case 2: shift =3D 23; off +=3D 6; break; - default: - abort (); - } - - dword =3D bfd_getl64 (contents + off); - insn =3D (dword >> shift) & 0x1ffffffffffLL; - - r1 =3D (insn >> 6) & 127; - r3 =3D (insn >> 20) & 127; - if (r1 =3D=3D r3) - insn =3D 0x8000000; /* nop */ - else - insn =3D (insn & 0x7f01fff) | 0x10800000000LL; /* (qp) mov r1 =3D r3= */ - - dword &=3D ~(0x1ffffffffffLL << shift); - dword |=3D (insn << shift); - bfd_putl64 (dword, contents + off); -} -=0C -bfd_reloc_status_type -ia64_elf_install_value (bfd_byte *hit_addr, bfd_vma v, unsigned int r_type) -{ - const struct ia64_operand *op; - int bigendian =3D 0, shift =3D 0; - bfd_vma t0, t1, dword; - ia64_insn insn; - enum ia64_opnd opnd; - const char *err; - size_t size =3D 8; - uint64_t val =3D v; - - opnd =3D IA64_OPND_NIL; - switch (r_type) - { - case R_IA64_NONE: - case R_IA64_LDXMOV: - return bfd_reloc_ok; - - /* Instruction relocations. */ - - case R_IA64_IMM14: - case R_IA64_TPREL14: - case R_IA64_DTPREL14: - opnd =3D IA64_OPND_IMM14; - break; - - case R_IA64_PCREL21F: opnd =3D IA64_OPND_TGT25; break; - case R_IA64_PCREL21M: opnd =3D IA64_OPND_TGT25b; break; - case R_IA64_PCREL60B: opnd =3D IA64_OPND_TGT64; break; - case R_IA64_PCREL21B: - case R_IA64_PCREL21BI: - opnd =3D IA64_OPND_TGT25c; - break; - - case R_IA64_IMM22: - case R_IA64_GPREL22: - case R_IA64_LTOFF22: - case R_IA64_LTOFF22X: - case R_IA64_PLTOFF22: - case R_IA64_PCREL22: - case R_IA64_LTOFF_FPTR22: - case R_IA64_TPREL22: - case R_IA64_DTPREL22: - case R_IA64_LTOFF_TPREL22: - case R_IA64_LTOFF_DTPMOD22: - case R_IA64_LTOFF_DTPREL22: - opnd =3D IA64_OPND_IMM22; - break; - - case R_IA64_IMM64: - case R_IA64_GPREL64I: - case R_IA64_LTOFF64I: - case R_IA64_PLTOFF64I: - case R_IA64_PCREL64I: - case R_IA64_FPTR64I: - case R_IA64_LTOFF_FPTR64I: - case R_IA64_TPREL64I: - case R_IA64_DTPREL64I: - opnd =3D IA64_OPND_IMMU64; - break; - - /* Data relocations. */ - - case R_IA64_DIR32MSB: - case R_IA64_GPREL32MSB: - case R_IA64_FPTR32MSB: - case R_IA64_PCREL32MSB: - case R_IA64_LTOFF_FPTR32MSB: - case R_IA64_SEGREL32MSB: - case R_IA64_SECREL32MSB: - case R_IA64_LTV32MSB: - case R_IA64_DTPREL32MSB: - size =3D 4; bigendian =3D 1; - break; - - case R_IA64_DIR32LSB: - case R_IA64_GPREL32LSB: - case R_IA64_FPTR32LSB: - case R_IA64_PCREL32LSB: - case R_IA64_LTOFF_FPTR32LSB: - case R_IA64_SEGREL32LSB: - case R_IA64_SECREL32LSB: - case R_IA64_LTV32LSB: - case R_IA64_DTPREL32LSB: - size =3D 4; bigendian =3D 0; - break; - - case R_IA64_DIR64MSB: - case R_IA64_GPREL64MSB: - case R_IA64_PLTOFF64MSB: - case R_IA64_FPTR64MSB: - case R_IA64_PCREL64MSB: - case R_IA64_LTOFF_FPTR64MSB: - case R_IA64_SEGREL64MSB: - case R_IA64_SECREL64MSB: - case R_IA64_LTV64MSB: - case R_IA64_TPREL64MSB: - case R_IA64_DTPMOD64MSB: - case R_IA64_DTPREL64MSB: - size =3D 8; bigendian =3D 1; - break; - - case R_IA64_DIR64LSB: - case R_IA64_GPREL64LSB: - case R_IA64_PLTOFF64LSB: - case R_IA64_FPTR64LSB: - case R_IA64_PCREL64LSB: - case R_IA64_LTOFF_FPTR64LSB: - case R_IA64_SEGREL64LSB: - case R_IA64_SECREL64LSB: - case R_IA64_LTV64LSB: - case R_IA64_TPREL64LSB: - case R_IA64_DTPMOD64LSB: - case R_IA64_DTPREL64LSB: - size =3D 8; bigendian =3D 0; - break; - - /* Unsupported / Dynamic relocations. */ - default: - return bfd_reloc_notsupported; - } - - switch (opnd) - { - case IA64_OPND_IMMU64: - hit_addr -=3D (intptr_t) hit_addr & 0x3; - t0 =3D bfd_getl64 (hit_addr); - t1 =3D bfd_getl64 (hit_addr + 8); - - /* tmpl/s: bits 0.. 5 in t0 - slot 0: bits 5..45 in t0 - slot 1: bits 46..63 in t0, bits 0..22 in t1 - slot 2: bits 23..63 in t1 */ - - /* First, clear the bits that form the 64 bit constant. */ - t0 &=3D ~(0x3ffffULL << 46); - t1 &=3D ~(0x7fffffLL - | (( (0x07fLL << 13) | (0x1ffLL << 27) - | (0x01fLL << 22) | (0x001LL << 21) - | (0x001LL << 36)) << 23)); - - t0 |=3D ((val >> 22) & 0x03ffffLL) << 46; /* 18 lsbs of imm41 */ - t1 |=3D ((val >> 40) & 0x7fffffLL) << 0; /* 23 msbs of imm41 */ - t1 |=3D ( (((val >> 0) & 0x07f) << 13) /* imm7b */ - | (((val >> 7) & 0x1ff) << 27) /* imm9d */ - | (((val >> 16) & 0x01f) << 22) /* imm5c */ - | (((val >> 21) & 0x001) << 21) /* ic */ - | (((val >> 63) & 0x001) << 36)) << 23; /* i */ - - bfd_putl64 (t0, hit_addr); - bfd_putl64 (t1, hit_addr + 8); - break; - - case IA64_OPND_TGT64: - hit_addr -=3D (intptr_t) hit_addr & 0x3; - t0 =3D bfd_getl64 (hit_addr); - t1 =3D bfd_getl64 (hit_addr + 8); - - /* tmpl/s: bits 0.. 5 in t0 - slot 0: bits 5..45 in t0 - slot 1: bits 46..63 in t0, bits 0..22 in t1 - slot 2: bits 23..63 in t1 */ - - /* First, clear the bits that form the 64 bit constant. */ - t0 &=3D ~(0x3ffffULL << 46); - t1 &=3D ~(0x7fffffLL - | ((1LL << 36 | 0xfffffLL << 13) << 23)); - - val >>=3D 4; - t0 |=3D ((val >> 20) & 0xffffLL) << 2 << 46; /* 16 lsbs of imm39 */ - t1 |=3D ((val >> 36) & 0x7fffffLL) << 0; /* 23 msbs of imm39 */ - t1 |=3D ((((val >> 0) & 0xfffffLL) << 13) /* imm20b */ - | (((val >> 59) & 0x1LL) << 36)) << 23; /* i */ - - bfd_putl64 (t0, hit_addr); - bfd_putl64 (t1, hit_addr + 8); - break; - - default: - switch ((intptr_t) hit_addr & 0x3) - { - case 0: shift =3D 5; break; - case 1: shift =3D 14; hit_addr +=3D 3; break; - case 2: shift =3D 23; hit_addr +=3D 6; break; - case 3: return bfd_reloc_notsupported; /* shouldn't happen... */ - } - dword =3D bfd_getl64 (hit_addr); - insn =3D (dword >> shift) & 0x1ffffffffffLL; - - op =3D elf64_ia64_operands + opnd; - err =3D (*op->insert) (op, val, &insn); - if (err) - return bfd_reloc_overflow; - - dword &=3D ~(0x1ffffffffffULL << shift); - dword |=3D (insn << shift); - bfd_putl64 (dword, hit_addr); - break; - - case IA64_OPND_NIL: - /* A data relocation. */ - if (bigendian) - if (size =3D=3D 4) - bfd_putb32 (val, hit_addr); - else - bfd_putb64 (val, hit_addr); - else - if (size =3D=3D 4) - bfd_putl32 (val, hit_addr); - else - bfd_putl64 (val, hit_addr); - break; - } - - return bfd_reloc_ok; -} diff --git a/bfd/elfxx-ia64.h b/bfd/elfxx-ia64.h deleted file mode 100644 index cfede0a1d5d..00000000000 --- a/bfd/elfxx-ia64.h +++ /dev/null @@ -1,40 +0,0 @@ -/* IA-64 support for 64-bit ELF - Copyright (C) 1998-2024 Free Software Foundation, Inc. - Contributed by David Mosberger-Tang - - This file is part of BFD, the Binary File Descriptor library. - - This program is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - This program is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program; if not, write to the Free Software - Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, - MA 02110-1301, USA. */ - -reloc_howto_type *ia64_elf_reloc_type_lookup (bfd *, bfd_reloc_code_real_t= ype); - -reloc_howto_type *ia64_elf_reloc_name_lookup (bfd *, const char *); - -reloc_howto_type *ia64_elf_lookup_howto (unsigned int rtype); - -bool ia64_elf_relax_br (bfd_byte *contents, bfd_vma off); -void ia64_elf_relax_brl (bfd_byte *contents, bfd_vma off); -void ia64_elf_relax_ldxmov (bfd_byte *contents, bfd_vma off); - -bfd_reloc_status_type ia64_elf_install_value (bfd_byte *hit_addr, bfd_vma = v, - unsigned int r_type); - -/* IA64 Itanium code generation. Called from linker. */ -extern void bfd_elf32_ia64_after_parse - (int); - -extern void bfd_elf64_ia64_after_parse - (int); diff --git a/bfd/libbfd-in.h b/bfd/libbfd-in.h index f7f5773510b..1eae3c3788f 100644 --- a/bfd/libbfd-in.h +++ b/bfd/libbfd-in.h @@ -405,12 +405,8 @@ extern bfd *_bfd_vms_lib_get_imagelib_file (bfd *) ATTRIBUTE_HIDDEN; extern bfd_cleanup _bfd_vms_lib_alpha_archive_p (bfd *) ATTRIBUTE_HIDDEN; -extern bfd_cleanup _bfd_vms_lib_ia64_archive_p - (bfd *) ATTRIBUTE_HIDDEN; extern bool _bfd_vms_lib_alpha_mkarchive (bfd *) ATTRIBUTE_HIDDEN; -extern bool _bfd_vms_lib_ia64_mkarchive - (bfd *) ATTRIBUTE_HIDDEN; =20 /* Routines to use for BFD_JUMP_TABLE_SYMBOLS where there is no symbol support. Use BFD_JUMP_TABLE_SYMBOLS (_bfd_nosymbols). */ diff --git a/bfd/libbfd.h b/bfd/libbfd.h index 5e8ed9eeefe..d2f5f9cd5f2 100644 --- a/bfd/libbfd.h +++ b/bfd/libbfd.h @@ -411,12 +411,8 @@ extern bfd *_bfd_vms_lib_get_imagelib_file (bfd *) ATTRIBUTE_HIDDEN; extern bfd_cleanup _bfd_vms_lib_alpha_archive_p (bfd *) ATTRIBUTE_HIDDEN; -extern bfd_cleanup _bfd_vms_lib_ia64_archive_p - (bfd *) ATTRIBUTE_HIDDEN; extern bool _bfd_vms_lib_alpha_mkarchive (bfd *) ATTRIBUTE_HIDDEN; -extern bool _bfd_vms_lib_ia64_mkarchive - (bfd *) ATTRIBUTE_HIDDEN; =20 /* Routines to use for BFD_JUMP_TABLE_SYMBOLS where there is no symbol support. Use BFD_JUMP_TABLE_SYMBOLS (_bfd_nosymbols). */ diff --git a/bfd/makefile.vms b/bfd/makefile.vms index af793d62902..4637f9ab590 100644 --- a/bfd/makefile.vms +++ b/bfd/makefile.vms @@ -22,14 +22,6 @@ # . # =20 -ifeq ($(ARCH),IA64) -HOSTFILE=3Dalphavms.h -OBJS:=3Dcpu-ia64.obj,elfxx-ia64.obj,elf64-ia64-vms.obj,\ - vms-misc.obj,vms-lib.obj,elf-strtab.obj,corefile.obj,stabs.obj,\ - merge.obj,elf-eh-frame.obj,elflink.obj,elf-attrs.obj,dwarf1.obj,elf64.obj -DEFS=3DSELECT_VECS=3D"&ia64_elf64_vms_vec",\ - SELECT_ARCHITECTURES=3D"&bfd_ia64_arch","HAVE_ia64_elf64_vms_vec"=3D1 -endif ifeq ($(ARCH),ALPHA) HOSTFILE=3Dalphavms.h OBJS:=3Dvms-alpha.obj,vms-lib.obj,vms-misc.obj,cpu-alpha.obj diff --git a/bfd/peXXigen.c b/bfd/peXXigen.c index d73c5e6e059..9fb3a0de09f 100644 --- a/bfd/peXXigen.c +++ b/bfd/peXXigen.c @@ -82,8 +82,6 @@ PE/PEI targets are created. */ #if defined COFF_WITH_pex64 # include "coff/x86_64.h" -#elif defined COFF_WITH_pep -# include "coff/ia64.h" #elif defined COFF_WITH_peAArch64 # include "coff/aarch64.h" #elif defined COFF_WITH_peLoongArch64 diff --git a/bfd/pei-ia64.c b/bfd/pei-ia64.c deleted file mode 100644 index bfc2152418e..00000000000 --- a/bfd/pei-ia64.c +++ /dev/null @@ -1,38 +0,0 @@ -/* BFD back-end for HP/Intel IA-64 PE IMAGE COFF files. - Copyright (C) 1999-2024 Free Software Foundation, Inc. - Contributed by David Mosberger - - This implementation only supports objcopy to ouput IA-64 PE IMAGE COFF - files. - - This file is part of BFD, the Binary File Descriptor library. - - This program is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - This program is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program; if not, write to the Free Software - Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, - MA 02110-1301, USA. */ - -#include "sysdep.h" -#include "bfd.h" - -#define TARGET_SYM ia64_pei_vec -#define TARGET_NAME "pei-ia64" -#define COFF_IMAGE_WITH_PE -#define COFF_WITH_PE -#define COFF_WITH_pep -#define PCRELOFFSET true -#define TARGET_UNDERSCORE '_' -/* Long section names not allowed in executable images, only object files.= */ -#define COFF_LONG_SECTION_NAMES 0 - -#include "coff-ia64.c" diff --git a/bfd/targets.c b/bfd/targets.c index 0d5d73ba462..da98776f068 100644 --- a/bfd/targets.c +++ b/bfd/targets.c @@ -757,13 +757,6 @@ extern const bfd_target i386_pe_vec; extern const bfd_target i386_pe_big_vec; extern const bfd_target i386_pei_vec; extern const bfd_target iamcu_elf32_vec; -extern const bfd_target ia64_elf32_be_vec; -extern const bfd_target ia64_elf32_hpux_be_vec; -extern const bfd_target ia64_elf64_be_vec; -extern const bfd_target ia64_elf64_le_vec; -extern const bfd_target ia64_elf64_hpux_be_vec; -extern const bfd_target ia64_elf64_vms_vec; -extern const bfd_target ia64_pei_vec; extern const bfd_target ip2k_elf32_vec; extern const bfd_target iq2000_elf32_vec; extern const bfd_target kvx_elf32_vec; @@ -1113,18 +1106,6 @@ static const bfd_target * const _bfd_target_vector[]= =3D &bpf_elf64_le_vec, #endif =20 -#ifdef BFD64 -#if 0 - &ia64_elf32_be_vec, -#endif - &ia64_elf32_hpux_be_vec, - &ia64_elf64_be_vec, - &ia64_elf64_le_vec, - &ia64_elf64_hpux_be_vec, - &ia64_elf64_vms_vec, - &ia64_pei_vec, -#endif - &ip2k_elf32_vec, &iq2000_elf32_vec, =20 diff --git a/bfd/vms-lib.c b/bfd/vms-lib.c index c51476ac441..837abe31900 100644 --- a/bfd/vms-lib.c +++ b/bfd/vms-lib.c @@ -56,7 +56,6 @@ enum vms_lib_kind { vms_lib_vax, vms_lib_alpha, - vms_lib_ia64, vms_lib_txt }; =20 @@ -536,15 +535,6 @@ _bfd_vms_lib_archive_p (bfd *abfd, enum vms_lib_kind k= ind) return NULL; } break; - case vms_lib_ia64: - if ((lhd.type !=3D LBR__C_TYP_IOBJ && lhd.type !=3D LBR__C_TYP_ISHST= B) - || majorid !=3D LBR_ELFMAJORID - || lhd.nindex !=3D 2) - { - bfd_set_error (bfd_error_wrong_format); - return NULL; - } - break; case vms_lib_txt: if ((lhd.type !=3D LBR__C_TYP_TXT && lhd.type !=3D LBR__C_TYP_MLB @@ -588,10 +578,8 @@ _bfd_vms_lib_archive_p (bfd *abfd, enum vms_lib_kind k= ind) goto err; /* Only IA64 archives may have more entries in the index that what was declared. */ - if (nbr_ent !=3D tdata->artdata.symdef_count - && kind !=3D vms_lib_ia64) + if (nbr_ent !=3D tdata->artdata.symdef_count) goto err; - tdata->artdata.symdef_count =3D nbr_ent; } tdata->cache =3D bfd_zalloc (abfd, sizeof (bfd *) * tdata->nbr_modules); if (tdata->cache =3D=3D NULL) @@ -714,14 +702,6 @@ _bfd_vms_lib_alpha_archive_p (bfd *abfd) return _bfd_vms_lib_archive_p (abfd, vms_lib_alpha); } =20 -/* Standard function for ia64 libraries. */ - -bfd_cleanup -_bfd_vms_lib_ia64_archive_p (bfd *abfd) -{ - return _bfd_vms_lib_archive_p (abfd, vms_lib_ia64); -} - /* Standard function for text libraries. */ =20 static bfd_cleanup @@ -752,11 +732,6 @@ _bfd_vms_lib_mkarchive (bfd *abfd, enum vms_lib_kind k= ind) tdata->mhd_size =3D offsetof (struct vms_mhd, pad1); tdata->type =3D LBR__C_TYP_EOBJ; break; - case vms_lib_ia64: - tdata->ver =3D LBR_ELFMAJORID; - tdata->mhd_size =3D sizeof (struct vms_mhd); - tdata->type =3D LBR__C_TYP_IOBJ; - break; default: abort (); } @@ -776,12 +751,6 @@ _bfd_vms_lib_alpha_mkarchive (bfd *abfd) return _bfd_vms_lib_mkarchive (abfd, vms_lib_alpha); } =20 -bool -_bfd_vms_lib_ia64_mkarchive (bfd *abfd) -{ - return _bfd_vms_lib_mkarchive (abfd, vms_lib_ia64); -} - /* Find NAME in the symbol index. Return the index. */ =20 symindex @@ -1666,7 +1635,6 @@ get_idxlen (struct lib_index *idx, bool is_elfidx) VBN is the first vbn to be used, and will contain on return the last vb= n. Can be called with ABFD set to NULL just to size the index. If not null, TOPVBN will be assigned to the vbn of the root index tree. - IS_ELFIDX is true for elfidx (ie ia64) indexes layout. Return TRUE on success. */ =20 static bool @@ -2135,7 +2103,7 @@ _bfd_vms_lib_write_archive_contents (bfd *arch) unsigned int vbn; unsigned int mod_idx_vbn; unsigned int sym_idx_vbn; - bool is_elfidx =3D tdata->kind =3D=3D vms_lib_ia64; + bool is_elfidx =3D false; unsigned int max_keylen =3D is_elfidx ? MAX_EKEYLEN : MAX_KEYLEN; =20 /* Count the number of modules (and do a first sanity check). */ @@ -2340,9 +2308,6 @@ _bfd_vms_lib_write_archive_contents (bfd *arch) case vms_lib_alpha: saneid =3D LHD_SANEID3; break; - case vms_lib_ia64: - saneid =3D LHD_SANEID6; - break; default: abort (); } diff --git a/binutils/MAINTAINERS b/binutils/MAINTAINERS index dabb331c0d5..4ffa5443c68 100644 --- a/binutils/MAINTAINERS +++ b/binutils/MAINTAINERS @@ -93,7 +93,6 @@ responsibility among the other maintainers. H8300 Prafulla Thakare HPPA Dave Anglin HPPA elf64 Jeff Law [Basic maintainance only] - IA-64 Jim Wilson IQ2000 Stan Cox ix86 H.J. Lu ix86 COFF DJ Delorie diff --git a/binutils/Makefile.am b/binutils/Makefile.am index ad571b60546..36b87af6b54 100644 --- a/binutils/Makefile.am +++ b/binutils/Makefile.am @@ -126,8 +126,7 @@ AM_CPPFLAGS =3D -I. -I$(srcdir) -I../bfd -I$(BFDDIR) -I= $(INCDIR) \ HFILES =3D \ arsup.h binemul.h bucomm.h budbg.h \ coffgrok.h debug.h demanguse.h dlltool.h dwarf.h elfcomm.h \ - objdump.h sysdep.h unwind-ia64.h windres.h winduni.h windint.h \ - windmc.h + objdump.h sysdep.h windres.h winduni.h windint.h windmc.h =20 GENERATED_HFILES =3D arparse.h sysroff.h sysinfo.h defparse.h rcparse.h mc= parse.h BUILT_SOURCES =3D $(GENERATED_HFILES) @@ -144,7 +143,7 @@ CFILES =3D \ rclex.c rdcoff.c rddbg.c readelf.c rename.c \ resbin.c rescoff.c resrc.c resres.c \ size.c srconv.c stabs.c strings.c sysdump.c \ - syslex_wrap.c unwind-ia64.c elfedit.c version.c \ + syslex_wrap.c elfedit.c version.c \ windres.c winduni.c wrstabs.c \ windmc.c mclex.c =20 @@ -259,7 +258,7 @@ objcopy_SOURCES =3D objcopy.c not-strip.c rename.c $(WR= ITE_DEBUG_SRCS) $(BULIBS) =20 strings_SOURCES =3D strings.c $(BULIBS) =20 -readelf_SOURCES =3D readelf.c version.c unwind-ia64.c dwarf.c demanguse.c = $(ELFLIBS) +readelf_SOURCES =3D readelf.c version.c dwarf.c demanguse.c $(ELFLIBS) readelf_LDADD =3D $(LIBCTF_NOBFD) $(LIBINTL) $(LIBIBERTY) $(ZLIB) $(ZSTD= _LIBS) $(DEBUGINFOD_LIBS) $(MSGPACK_LIBS) $(LIBSFRAME) =20 elfedit_SOURCES =3D elfedit.c version.c $(ELFLIBS) diff --git a/binutils/Makefile.in b/binutils/Makefile.in index 67fa5b3b8d9..074e2d57e87 100644 --- a/binutils/Makefile.in +++ b/binutils/Makefile.in @@ -254,7 +254,7 @@ am_ranlib_OBJECTS =3D ar.$(OBJEXT) is-ranlib.$(OBJEXT) = arparse.$(OBJEXT) \ binemul.$(OBJEXT) emul_$(EMULATION).$(OBJEXT) $(am__objects_1) ranlib_OBJECTS =3D $(am_ranlib_OBJECTS) am_readelf_OBJECTS =3D readelf.$(OBJEXT) version.$(OBJEXT) \ - unwind-ia64.$(OBJEXT) dwarf.$(OBJEXT) demanguse.$(OBJEXT) \ + dwarf.$(OBJEXT) demanguse.$(OBJEXT) \ $(am__objects_2) readelf_OBJECTS =3D $(am_readelf_OBJECTS) @ENABLE_LIBCTF_TRUE@am__DEPENDENCIES_3 =3D ../libctf/libctf-nobfd.la @@ -707,8 +707,7 @@ AM_CPPFLAGS =3D -I. -I$(srcdir) -I../bfd -I$(BFDDIR) -I= $(INCDIR) \ HFILES =3D \ arsup.h binemul.h bucomm.h budbg.h \ coffgrok.h debug.h demanguse.h dlltool.h dwarf.h elfcomm.h \ - objdump.h sysdep.h unwind-ia64.h windres.h winduni.h windint.h \ - windmc.h + objdump.h sysdep.h windres.h winduni.h windint.h windmc.h =20 GENERATED_HFILES =3D arparse.h sysroff.h sysinfo.h defparse.h rcparse.h mc= parse.h BUILT_SOURCES =3D $(GENERATED_HFILES) @@ -724,7 +723,7 @@ CFILES =3D \ rclex.c rdcoff.c rddbg.c readelf.c rename.c \ resbin.c rescoff.c resrc.c resres.c \ size.c srconv.c stabs.c strings.c sysdump.c \ - syslex_wrap.c unwind-ia64.c elfedit.c version.c \ + syslex_wrap.c elfedit.c version.c \ windres.c winduni.c wrstabs.c \ windmc.c mclex.c =20 @@ -795,7 +794,7 @@ LDADD =3D $(BFDLIB) $(LIBIBERTY) $(LIBINTL) size_SOURCES =3D size.c $(BULIBS) objcopy_SOURCES =3D objcopy.c not-strip.c rename.c $(WRITE_DEBUG_SRCS) $(B= ULIBS) strings_SOURCES =3D strings.c $(BULIBS) -readelf_SOURCES =3D readelf.c version.c unwind-ia64.c dwarf.c demanguse.c = $(ELFLIBS) +readelf_SOURCES =3D readelf.c version.c dwarf.c demanguse.c $(ELFLIBS) readelf_LDADD =3D $(LIBCTF_NOBFD) $(LIBINTL) $(LIBIBERTY) $(ZLIB) $(ZSTD_L= IBS) $(DEBUGINFOD_LIBS) $(MSGPACK_LIBS) $(LIBSFRAME) elfedit_SOURCES =3D elfedit.c version.c $(ELFLIBS) elfedit_LDADD =3D $(LIBINTL) $(LIBIBERTY) @@ -1205,7 +1204,6 @@ distclean-compile: @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/strings.Po@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/sysdump.Po@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/syslex_wrap.Po@am__quote@ -@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/unwind-ia64.Po@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/version.Po@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/windmc.Po@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/windres.Po@am__quote@ diff --git a/binutils/NEWS b/binutils/NEWS index 5c31953575a..3b5c4631d8c 100644 --- a/binutils/NEWS +++ b/binutils/NEWS @@ -1,5 +1,7 @@ -*- text -*- =20 +* Remove Itanium (IA-64) architecture. + * Readelf now displays RELR relocations in full detail. =20 * Readelf now has a -j/--display-section option which takes the name or in= dex diff --git a/binutils/configure b/binutils/configure index 5d87b6b3e66..bf9e62193c5 100755 --- a/binutils/configure +++ b/binutils/configure @@ -5968,10 +5968,6 @@ haiku*) hpux10.20* | hpux11*) lt_cv_file_magic_cmd=3D/usr/bin/file case $host_cpu in - ia64*) - lt_cv_deplibs_check_method=3D'file_magic (s[0-9][0-9][0-9]|ELF-[0-9][0= -9]) shared object file - IA64' - lt_cv_file_magic_test_file=3D/usr/lib/hpux32/libc.so - ;; hppa*64*) lt_cv_deplibs_check_method=3D'file_magic (s[0-9][0-9][0-9]|ELF[ -][0-9= ][0-9])(-bit)?( [LM]SB)? shared object( file)?[, -]* PA-RISC [0-9]\.[0-9]' lt_cv_file_magic_test_file=3D/usr/lib/pa20_64/libc.sl @@ -6530,11 +6526,6 @@ aix*) cygwin* | mingw* | pw32* | cegcc*) symcode=3D'[ABCDGISTW]' ;; -hpux*) - if test "$host_cpu" =3D ia64; then - symcode=3D'[ABCDEGRST]' - fi - ;; irix* | nonstopux*) symcode=3D'[BCDEGRST]' ;; @@ -6565,7 +6556,7 @@ case `$NM -V 2>&1` in esac =20 # Transform an extracted symbol line into a proper C declaration. -# Some systems (esp. on ia64) link data and code symbols differently, +# Some systems link data and code symbols differently, # so use this general approach. lt_cv_sys_global_symbol_to_cdecl=3D"sed -n -e 's/^T .* \(.*\)$/extern int = \1();/p' -e 's/^$symcode* .* \(.*\)$/extern char \1;/p'" =20 @@ -6765,25 +6756,6 @@ test "x$enable_libtool_lock" !=3D xno && enable_libt= ool_lock=3Dyes # Some flags need to be propagated to the compiler or linker for good # libtool support. case $host in -ia64-*-hpux*) - # Find out which ABI we are using. - echo 'int i;' > conftest.$ac_ext - if { { eval echo "\"\$as_me\":${as_lineno-$LINENO}: \"$ac_compile\""; } = >&5 - (eval $ac_compile) 2>&5 - ac_status=3D$? - $as_echo "$as_me:${as_lineno-$LINENO}: \$? =3D $ac_status" >&5 - test $ac_status =3D 0; }; then - case `/usr/bin/file conftest.$ac_objext` in - *ELF-32*) - HPUX_IA64_MODE=3D"32" - ;; - *ELF-64*) - HPUX_IA64_MODE=3D"64" - ;; - esac - fi - rm -rf conftest* - ;; *-*-irix6*) # Find out which ABI we are using. echo '#line '$LINENO' "configure"' > conftest.$ac_ext @@ -8118,10 +8090,6 @@ $as_echo_n "checking for $compiler option to produce= PIC... " >&6; } case $host_os in aix*) # All AIX code is PIC. - if test "$host_cpu" =3D ia64; then - # AIX 5 now supports IA64 processor - lt_prog_compiler_static=3D'-Bstatic' - fi lt_prog_compiler_pic=3D'-fPIC' ;; =20 @@ -8218,12 +8186,7 @@ $as_echo_n "checking for $compiler option to produce= PIC... " >&6; } case $host_os in aix*) lt_prog_compiler_wl=3D'-Wl,' - if test "$host_cpu" =3D ia64; then - # AIX 5 now supports IA64 processor - lt_prog_compiler_static=3D'-Bstatic' - else - lt_prog_compiler_static=3D'-bnso -bI:/lib/syscalls.exp' - fi + lt_prog_compiler_static=3D'-bnso -bI:/lib/syscalls.exp' ;; =20 mingw* | cygwin* | pw32* | os2* | cegcc*) @@ -8237,7 +8200,7 @@ $as_echo_n "checking for $compiler option to produce = PIC... " >&6; } # PIC is the default for IA64 HP-UX and 64-bit HP-UX, but # not for PA HP-UX. case $host_cpu in - hppa*64*|ia64*) + hppa*64*) # +Z the default ;; *) @@ -8762,7 +8725,6 @@ $as_echo_n "checking whether the $compiler linker ($L= D) supports shared librarie case $host_os in aix[3-9]*) # On AIX/PPC, the GNU linker is very broken - if test "$host_cpu" !=3D ia64; then ld_shlibs=3Dno cat <<_LT_EOF 1>&2 =20 @@ -8774,7 +8736,6 @@ $as_echo_n "checking whether the $compiler linker ($L= D) supports shared librarie *** You will then need to restart the configuration process. =20 _LT_EOF - fi ;; =20 amigaos*) @@ -8870,10 +8831,6 @@ _LT_EOF # Portland Group f77 and f90 compilers whole_archive_flag_spec=3D'${wl}--whole-archive`for conv in $convenienc= e\"\"; do test -n \"$conv\" && new_convenience=3D\"$new_convenience,$conv\= "; done; func_echo_all \"$new_convenience\"` ${wl}--no-whole-archive' tmp_addflag=3D' $pic_flag -Mnomain' ;; - ecc*,ia64* | icc*,ia64*) # Intel C compiler on ia64 - tmp_addflag=3D' -i_dynamic' ;; - efc*,ia64* | ifort*,ia64*) # Intel Fortran compiler on ia64 - tmp_addflag=3D' -i_dynamic -nofor_main' ;; ifc* | ifort*) # Intel Fortran compiler tmp_addflag=3D' -nofor_main' ;; lf95*) # Lahey Fortran 8.1 @@ -9027,13 +8984,6 @@ _LT_EOF ;; =20 aix[4-9]*) - if test "$host_cpu" =3D ia64; then - # On IA64, the linker does run time linking by default, so we don't - # have to do anything special. - aix_use_runtimelinking=3Dno - exp_sym_flag=3D'-Bexport' - no_entry_flag=3D"" - else # If we're using GNU nm, then we don't want the "-C" option. # -C means demangle to AIX nm, but means don't demangle with GNU nm # Also, AIX nm treats weak defined symbols like other global @@ -9060,7 +9010,6 @@ _LT_EOF =20 exp_sym_flag=3D'-bexport' no_entry_flag=3D'-bnoentry' - fi =20 # When large executables or shared objects are built, AIX ld can # have problems creating the table of contents. If linking a library @@ -9103,17 +9052,11 @@ _LT_EOF fi else # not using gcc - if test "$host_cpu" =3D ia64; then - # VisualAge C++, Version 5.5 for AIX 5L for IA-64, Beta 3 Release - # chokes on -Wl,-G. The following line is correct: - shared_flag=3D'-G' - else if test "$aix_use_runtimelinking" =3D yes; then shared_flag=3D'${wl}-G' else shared_flag=3D'${wl}-bM:SRE' fi - fi fi =20 export_dynamic_flag_spec=3D'${wl}-bexpall' @@ -9159,11 +9102,6 @@ if test -z "$aix_libpath"; then aix_libpath=3D"/usr/= lib:/lib"; fi hardcode_libdir_flag_spec=3D'${wl}-blibpath:$libdir:'"$aix_libpath" archive_expsym_cmds=3D'$CC -o $output_objdir/$soname $libobjs $dep= libs '"\${wl}$no_entry_flag"' $compiler_flags `if test "x${allow_undefined_= flag}" !=3D "x"; then func_echo_all "${wl}${allow_undefined_flag}"; else :;= fi` '"\${wl}$exp_sym_flag:\$export_symbols $shared_flag" else - if test "$host_cpu" =3D ia64; then - hardcode_libdir_flag_spec=3D'${wl}-R $libdir:/usr/lib:/lib' - allow_undefined_flag=3D"-z nodefs" - archive_expsym_cmds=3D"\$CC $shared_flag"' -o $output_objdir/$soname $l= ibobjs $deplibs '"\${wl}$no_entry_flag"' $compiler_flags ${wl}${allow_undef= ined_flag} '"\${wl}$exp_sym_flag:\$export_symbols" - else # Determine the default libpath from the value encoded in an # empty executable. cat confdefs.h - <<_ACEOF >conftest.$ac_ext @@ -9211,7 +9149,6 @@ if test -z "$aix_libpath"; then aix_libpath=3D"/usr/l= ib:/lib"; fi archive_cmds_need_lc=3Dyes # This is similar to how AIX traditionally builds its shared libraries. archive_expsym_cmds=3D"\$CC $shared_flag"' -o $output_objdir/$soname $l= ibobjs $deplibs ${wl}-bnoentry $compiler_flags ${wl}-bE:$export_symbols${al= low_undefined_flag}~$AR $AR_FLAGS $output_objdir/$libname$release.a $output= _objdir/$soname' - fi fi ;; =20 @@ -9360,9 +9297,6 @@ if test -z "$aix_libpath"; then aix_libpath=3D"/usr/l= ib:/lib"; fi hppa*64*) archive_cmds=3D'$CC -shared ${wl}+h ${wl}$soname ${wl}+nodefaultrpath -= o $lib $libobjs $deplibs $compiler_flags' ;; - ia64*) - archive_cmds=3D'$CC -shared -fPIC ${wl}+h ${wl}$soname ${wl}+nodefaultr= path -o $lib $libobjs $deplibs $compiler_flags' - ;; *) archive_cmds=3D'$CC -shared -fPIC ${wl}+h ${wl}$soname ${wl}+b ${wl}$in= stall_libdir -o $lib $libobjs $deplibs $compiler_flags' ;; @@ -9372,9 +9306,6 @@ if test -z "$aix_libpath"; then aix_libpath=3D"/usr/l= ib:/lib"; fi hppa*64*) archive_cmds=3D'$CC -b ${wl}+h ${wl}$soname ${wl}+nodefaultrpath -o $li= b $libobjs $deplibs $compiler_flags' ;; - ia64*) - archive_cmds=3D'$CC -b ${wl}+h ${wl}$soname ${wl}+nodefaultrpath -o $li= b $libobjs $deplibs $compiler_flags' - ;; *) =20 # Older versions of the 11.00 compiler do not understand -b yet @@ -9424,7 +9355,7 @@ fi hardcode_libdir_separator=3D: =20 case $host_cpu in - hppa*64*|ia64*) + hppa*64*) hardcode_direct=3Dno hardcode_shlibpath_var=3Dno ;; @@ -10061,11 +9992,6 @@ aix[4-9]*) need_lib_prefix=3Dno need_version=3Dno hardcode_into_libs=3Dyes - if test "$host_cpu" =3D ia64; then - # AIX 5 supports IA64 - library_names_spec=3D'${libname}${release}${shared_ext}$major ${libnam= e}${release}${shared_ext}$versuffix $libname${shared_ext}' - shlibpath_var=3DLD_LIBRARY_PATH - else # With GCC up to 2.95.x, collect2 would create an import file # for dependence libraries. The import file would start with # the line `#! .'. This would cause the generated library to @@ -10097,7 +10023,6 @@ aix[4-9]*) soname_spec=3D'${libname}${release}${shared_ext}$major' fi shlibpath_var=3DLIBPATH - fi ;; =20 amigaos*) @@ -10274,21 +10199,6 @@ hpux9* | hpux10* | hpux11*) need_lib_prefix=3Dno need_version=3Dno case $host_cpu in - ia64*) - shrext_cmds=3D'.so' - hardcode_into_libs=3Dyes - dynamic_linker=3D"$host_os dld.so" - shlibpath_var=3DLD_LIBRARY_PATH - shlibpath_overrides_runpath=3Dyes # Unless +noenvvar is specified. - library_names_spec=3D'${libname}${release}${shared_ext}$versuffix ${li= bname}${release}${shared_ext}$major $libname${shared_ext}' - soname_spec=3D'${libname}${release}${shared_ext}$major' - if test "X$HPUX_IA64_MODE" =3D X32; then - sys_lib_search_path_spec=3D"/usr/lib/hpux32 /usr/local/lib/hpux32 /u= sr/local/lib" - else - sys_lib_search_path_spec=3D"/usr/lib/hpux64 /usr/local/lib/hpux64" - fi - sys_lib_dlsearch_path_spec=3D$sys_lib_search_path_spec - ;; hppa*64*) shrext_cmds=3D'.sl' hardcode_into_libs=3Dyes @@ -11379,7 +11289,7 @@ $as_echo_n "checking whether to build shared librar= ies... " >&6; } ;; =20 aix[4-9]*) - if test "$host_cpu" !=3D ia64 && test "$aix_use_runtimelinking" =3D no= ; then + if test "$aix_use_runtimelinking" =3D no ; then test "$enable_shared" =3D yes && enable_static=3Dno fi ;; diff --git a/binutils/configure.com b/binutils/configure.com index 41145101e04..3b467156a66 100644 --- a/binutils/configure.com +++ b/binutils/configure.com @@ -82,7 +82,6 @@ $ create config.h $! $! Add TARGET. $! -$ if arch .eqs. "ia64" then target =3D "elf64-ia64-vms" $ if arch .eqs. "alpha" then target =3D "vms-alpha" $ if arch .eqs. "vax" then target =3D "vms-vax" $! diff --git a/binutils/makefile.vms b/binutils/makefile.vms index 0f2cca59f6c..14b00863289 100644 --- a/binutils/makefile.vms +++ b/binutils/makefile.vms @@ -54,7 +54,7 @@ ADDR2LINEOBJS =3D $(ADDL_DEPS),addr2line.obj =20 OBJDUMPOBJS =3D objdump.obj,prdbg.obj,$(DEBUG_OBJS),$(ADDL_DEPS),$(OPCODES= _DEP) =20 -READELFOBJS =3D readelf.obj,dwarf.obj,unwind-ia64.obj,$(ADDL_DEPS) +READELFOBJS =3D readelf.obj,dwarf.obj,$(ADDL_DEPS) =20 all: config.h size.exe strings.exe objdump.exe nm.exe addr2line.exe =20 @@ -74,7 +74,7 @@ objdump.exe: $(OBJDUMPOBJS) link/exe=3D$@ objdump.obj,prdbg.obj,$(DEBUG_OBJS),$(ADDL_LIBS),$(OPCODES) =20 readelf.exe: $(READELFOBJS) - link/exe=3D$@ readelf.obj,dwarf.obj,unwind-ia64.obj,$(ADDL_LIBS) + link/exe=3D$@ readelf.obj,dwarf.obj,$(ADDL_LIBS) =20 config.h: $$ @configure diff --git a/binutils/readelf.c b/binutils/readelf.c index f8305b4715b..f98a7717e3c 100644 --- a/binutils/readelf.c +++ b/binutils/readelf.c @@ -119,7 +119,6 @@ #include "elf/i370.h" #include "elf/i860.h" #include "elf/i960.h" -#include "elf/ia64.h" #include "elf/ip2k.h" #include "elf/kvx.h" #include "elf/lm32.h" @@ -961,17 +960,6 @@ printable_section_name (Filedata * filedata, const Elf= _Internal_Shdr * sec) return buf_start; } =20 -/* Return TRUE if the current file is for IA-64 machine and OpenVMS ABI. - This OS has so many departures from the ELF standard that we test it at - many places. */ - -static inline bool -is_ia64_vms (Filedata * filedata) -{ - return filedata->file_header.e_machine =3D=3D EM_IA_64 - && filedata->file_header.e_ident[EI_OSABI] =3D=3D ELFOSABI_OPENVMS; -} - static const char * printable_section_name_from_index (Filedata * filedata, size_t ndx, @@ -1011,15 +999,6 @@ printable_section_name_from_index (Filedata * fileda= ta, return "LARGE_COM"; break; =20 - case EM_IA_64: - if (filedata->file_header.e_ident[EI_OSABI] =3D=3D ELFOSABI_HPUX - && ndx =3D=3D SHN_IA_64_ANSI_COMMON) - return "ANSI_COM"; - - if (is_ia64_vms (filedata) && ndx =3D=3D SHN_IA_64_VMS_SYMVEC) - return "VMS_SYMVEC"; - break; - default: break; } @@ -1216,7 +1195,6 @@ guess_is_rela (unsigned int e_machine) case EM_H8S: case EM_H8_300: case EM_H8_300H: - case EM_IA_64: case EM_IP2K: case EM_IP2K_OLD: case EM_IQ2000: @@ -2088,9 +2066,6 @@ dump_relocations (Filedata * filedata, case EM_PJ_OLD: rtype =3D elf_pj_reloc_type (type); break; - case EM_IA_64: - rtype =3D elf_ia64_reloc_type (type); - break; =20 case EM_KVX: rtype =3D elf_kvx_reloc_type (type); @@ -2574,47 +2549,6 @@ get_parisc_dynamic_type (unsigned long type) } } =20 -static const char * -get_ia64_dynamic_type (unsigned long type) -{ - switch (type) - { - case DT_IA_64_PLT_RESERVE: return "IA_64_PLT_RESERVE"; - case DT_IA_64_VMS_SUBTYPE: return "VMS_SUBTYPE"; - case DT_IA_64_VMS_IMGIOCNT: return "VMS_IMGIOCNT"; - case DT_IA_64_VMS_LNKFLAGS: return "VMS_LNKFLAGS"; - case DT_IA_64_VMS_VIR_MEM_BLK_SIZ: return "VMS_VIR_MEM_BLK_SIZ"; - case DT_IA_64_VMS_IDENT: return "VMS_IDENT"; - case DT_IA_64_VMS_NEEDED_IDENT: return "VMS_NEEDED_IDENT"; - case DT_IA_64_VMS_IMG_RELA_CNT: return "VMS_IMG_RELA_CNT"; - case DT_IA_64_VMS_SEG_RELA_CNT: return "VMS_SEG_RELA_CNT"; - case DT_IA_64_VMS_FIXUP_RELA_CNT: return "VMS_FIXUP_RELA_CNT"; - case DT_IA_64_VMS_FIXUP_NEEDED: return "VMS_FIXUP_NEEDED"; - case DT_IA_64_VMS_SYMVEC_CNT: return "VMS_SYMVEC_CNT"; - case DT_IA_64_VMS_XLATED: return "VMS_XLATED"; - case DT_IA_64_VMS_STACKSIZE: return "VMS_STACKSIZE"; - case DT_IA_64_VMS_UNWINDSZ: return "VMS_UNWINDSZ"; - case DT_IA_64_VMS_UNWIND_CODSEG: return "VMS_UNWIND_CODSEG"; - case DT_IA_64_VMS_UNWIND_INFOSEG: return "VMS_UNWIND_INFOSEG"; - case DT_IA_64_VMS_LINKTIME: return "VMS_LINKTIME"; - case DT_IA_64_VMS_SEG_NO: return "VMS_SEG_NO"; - case DT_IA_64_VMS_SYMVEC_OFFSET: return "VMS_SYMVEC_OFFSET"; - case DT_IA_64_VMS_SYMVEC_SEG: return "VMS_SYMVEC_SEG"; - case DT_IA_64_VMS_UNWIND_OFFSET: return "VMS_UNWIND_OFFSET"; - case DT_IA_64_VMS_UNWIND_SEG: return "VMS_UNWIND_SEG"; - case DT_IA_64_VMS_STRTAB_OFFSET: return "VMS_STRTAB_OFFSET"; - case DT_IA_64_VMS_SYSVER_OFFSET: return "VMS_SYSVER_OFFSET"; - case DT_IA_64_VMS_IMG_RELA_OFF: return "VMS_IMG_RELA_OFF"; - case DT_IA_64_VMS_SEG_RELA_OFF: return "VMS_SEG_RELA_OFF"; - case DT_IA_64_VMS_FIXUP_RELA_OFF: return "VMS_FIXUP_RELA_OFF"; - case DT_IA_64_VMS_PLTGOT_OFFSET: return "VMS_PLTGOT_OFFSET"; - case DT_IA_64_VMS_PLTGOT_SEG: return "VMS_PLTGOT_SEG"; - case DT_IA_64_VMS_FPMODE: return "VMS_FPMODE"; - default: - return NULL; - } -} - static const char * get_solaris_section_type (unsigned long type) { @@ -2867,9 +2801,6 @@ get_dynamic_type (Filedata * filedata, unsigned long = type) case EM_PPC64: result =3D get_ppc64_dynamic_type (type); break; - case EM_IA_64: - result =3D get_ia64_dynamic_type (type); - break; case EM_ALPHA: result =3D get_alpha_dynamic_type (type); break; @@ -2912,9 +2843,6 @@ get_dynamic_type (Filedata * filedata, unsigned long = type) case EM_PARISC: result =3D get_parisc_dynamic_type (type); break; - case EM_IA_64: - result =3D get_ia64_dynamic_type (type); - break; default: if (filedata->file_header.e_ident[EI_OSABI] =3D=3D ELFOSABI_SOLARIS) result =3D get_solaris_dynamic_type (type); @@ -3100,7 +3028,6 @@ get_machine_name (unsigned e_machine) case EM_H8S: return "Renesas H8S"; case EM_H8_500: return "Renesas H8/500"; /* 50 */ - case EM_IA_64: return "Intel IA-64"; case EM_MIPS_X: return "Stanford MIPS-X"; case EM_COLDFIRE: return "Motorola Coldfire"; case EM_68HC12: return "Motorola MC68HC12 Microcontroller"; @@ -3729,47 +3656,6 @@ decode_FRV_machine_flags (char *out, unsigned e_flag= s) return out; } =20 -static char * -decode_IA64_machine_flags (char *out, unsigned e_flags, Filedata *filedata) -{ - if ((e_flags & EF_IA_64_ABI64)) - out =3D stpcpy (out, ", 64-bit"); - else - out =3D stpcpy (out, ", 32-bit"); - if ((e_flags & EF_IA_64_REDUCEDFP)) - out =3D stpcpy (out, ", reduced fp model"); - if ((e_flags & EF_IA_64_NOFUNCDESC_CONS_GP)) - out =3D stpcpy (out, ", no function descriptors, constant gp"); - else if ((e_flags & EF_IA_64_CONS_GP)) - out =3D stpcpy (out, ", constant gp"); - if ((e_flags & EF_IA_64_ABSOLUTE)) - out =3D stpcpy (out, ", absolute"); - if (filedata->file_header.e_ident[EI_OSABI] =3D=3D ELFOSABI_OPENVMS) - { - if ((e_flags & EF_IA_64_VMS_LINKAGES)) - out =3D stpcpy (out, ", vms_linkages"); - switch ((e_flags & EF_IA_64_VMS_COMCOD)) - { - case EF_IA_64_VMS_COMCOD_SUCCESS: - break; - case EF_IA_64_VMS_COMCOD_WARNING: - out =3D stpcpy (out, ", warning"); - break; - case EF_IA_64_VMS_COMCOD_ERROR: - out =3D stpcpy (out, ", error"); - break; - case EF_IA_64_VMS_COMCOD_ABORT: - out =3D stpcpy (out, ", abort"); - break; - default: - warn (_("Unrecognised IA64 VMS Command Code: %x\n"), - e_flags & EF_IA_64_VMS_COMCOD); - out =3D stpcpy (out, ", "); - } - } - return out; -} - static char * decode_LOONGARCH_machine_flags (char *out, unsigned int e_flags) { @@ -5011,10 +4897,6 @@ get_machine_flags (Filedata * filedata, unsigned e_f= lags, unsigned e_machine) out =3D stpcpy (out, ", gnu calling convention"); break; =20 - case EM_IA_64: - out =3D decode_IA64_machine_flags (out, e_flags, filedata); - break; - case EM_VAX: if ((e_flags & EF_VAX_NONPIC)) out =3D stpcpy (out, ", non-PIC"); @@ -5213,17 +5095,6 @@ get_parisc_segment_type (unsigned long type) } } =20 -static const char * -get_ia64_segment_type (unsigned long type) -{ - switch (type) - { - case PT_IA_64_ARCHEXT: return "IA_64_ARCHEXT"; - case PT_IA_64_UNWIND: return "IA_64_UNWIND"; - default: return NULL; - } -} - static const char * get_tic6x_segment_type (unsigned long type) { @@ -5269,16 +5140,6 @@ get_hpux_segment_type (unsigned long type, unsigned = e_machine) default: return NULL; } =20 - if (e_machine =3D=3D EM_IA_64) - switch (type) - { - case PT_HP_TLS: return "HP_TLS"; - case PT_IA_64_HP_OPT_ANOT: return "HP_OPT_ANNOT"; - case PT_IA_64_HP_HSL_ANOT: return "HP_HSL_ANNOT"; - case PT_IA_64_HP_STACK: return "HP_STACK"; - default: return NULL; - } - return NULL; } =20 @@ -5347,9 +5208,6 @@ get_segment_type (Filedata * filedata, unsigned long = p_type) case EM_PARISC: result =3D get_parisc_segment_type (p_type); break; - case EM_IA_64: - result =3D get_ia64_segment_type (p_type); - break; case EM_TI_C6000: result =3D get_tic6x_segment_type (p_type); break; @@ -5486,31 +5344,6 @@ get_parisc_section_type_name (unsigned int sh_type) } } =20 -static const char * -get_ia64_section_type_name (Filedata * filedata, unsigned int sh_type) -{ - /* If the top 8 bits are 0x78 the next 8 are the os/abi ID. */ - if ((sh_type & 0xFF000000) =3D=3D SHT_IA_64_LOPSREG) - return get_osabi_name (filedata, (sh_type & 0x00FF0000) >> 16); - - switch (sh_type) - { - case SHT_IA_64_EXT: return "IA_64_EXT"; - case SHT_IA_64_UNWIND: return "IA_64_UNWIND"; - case SHT_IA_64_PRIORITY_INIT: return "IA_64_PRIORITY_INIT"; - case SHT_IA_64_VMS_TRACE: return "VMS_TRACE"; - case SHT_IA_64_VMS_TIE_SIGNATURES: return "VMS_TIE_SIGNATURES"; - case SHT_IA_64_VMS_DEBUG: return "VMS_DEBUG"; - case SHT_IA_64_VMS_DEBUG_STR: return "VMS_DEBUG_STR"; - case SHT_IA_64_VMS_LINKAGES: return "VMS_LINKAGES"; - case SHT_IA_64_VMS_SYMBOL_VECTOR: return "VMS_SYMBOL_VECTOR"; - case SHT_IA_64_VMS_FIXUP: return "VMS_FIXUP"; - default: - break; - } - return NULL; -} - static const char * get_x86_64_section_type_name (unsigned int sh_type) { @@ -5681,9 +5514,6 @@ get_section_type_name (Filedata * filedata, unsigned = int sh_type) case EM_PARISC: result =3D get_parisc_section_type_name (sh_type); break; - case EM_IA_64: - result =3D get_ia64_section_type_name (filedata, sh_type); - break; case EM_X86_64: case EM_L1OM: case EM_K1OM: @@ -5729,9 +5559,6 @@ get_section_type_name (Filedata * filedata, unsigned = int sh_type) { switch (filedata->file_header.e_machine) { - case EM_IA_64: - result =3D get_ia64_section_type_name (filedata, sh_type); - break; default: if (filedata->file_header.e_ident[EI_OSABI] =3D=3D ELFOSABI_SOLARIS) result =3D get_solaris_section_type (sh_type); @@ -6983,10 +6810,8 @@ process_program_headers (Filedata * filedata) sec =3D find_section (filedata, ".dynamic"); if (sec =3D=3D NULL || sec->sh_size =3D=3D 0) { - /* A corresponding .dynamic section is expected, but on - IA-64/OpenVMS it is OK for it to be missing. */ - if (!is_ia64_vms (filedata)) - error (_("no .dynamic section in the dynamic segment\n")); + /* A corresponding .dynamic section is expected. */ + error (_("no .dynamic section in the dynamic segment\n")); break; } =20 @@ -7606,24 +7431,6 @@ get_elf_section_flags (Filedata * filedata, uint64_t= sh_flags) sindex =3D -1; switch (filedata->file_header.e_machine) { - case EM_IA_64: - if (flag =3D=3D SHF_IA_64_SHORT) - sindex =3D 10; - else if (flag =3D=3D SHF_IA_64_NORECOV) - sindex =3D 11; - else if (filedata->file_header.e_ident[EI_OSABI] =3D=3D ELFOSABI_OPENV= MS) - switch (flag) - { - case SHF_IA_64_VMS_GLOBAL: sindex =3D 12; break; - case SHF_IA_64_VMS_OVERLAID: sindex =3D 13; break; - case SHF_IA_64_VMS_SHARED: sindex =3D 14; break; - case SHF_IA_64_VMS_VECTOR: sindex =3D 15; break; - case SHF_IA_64_VMS_ALLOC_64BIT: sindex =3D 16; break; - case SHF_IA_64_VMS_PROTECTED: sindex =3D 17; break; - default: break; - } - break; - case EM_386: case EM_IAMCU: case EM_X86_64: @@ -8910,194 +8717,6 @@ process_section_groups (Filedata * filedata) return true; } =20 -/* Data used to display dynamic fixups. */ - -struct ia64_vms_dynfixup -{ - uint64_t needed_ident; /* Library ident number. */ - uint64_t needed; /* Index in the dstrtab of the library name. */ - uint64_t fixup_needed; /* Index of the library. */ - uint64_t fixup_rela_cnt; /* Number of fixups. */ - uint64_t fixup_rela_off; /* Fixups offset in the dynamic segment. */ -}; - -/* Data used to display dynamic relocations. */ - -struct ia64_vms_dynimgrela -{ - uint64_t img_rela_cnt; /* Number of relocations. */ - uint64_t img_rela_off; /* Reloc offset in the dynamic segment. */ -}; - -/* Display IA-64 OpenVMS dynamic fixups (used to dynamically link a shared - library). */ - -static bool -dump_ia64_vms_dynamic_fixups (Filedata * filedata, - struct ia64_vms_dynfixup * fixup, - const char * strtab, - unsigned int strtab_sz) -{ - Elf64_External_VMS_IMAGE_FIXUP * imfs; - size_t i; - const char * lib_name; - - imfs =3D get_data (NULL, filedata, - filedata->dynamic_addr + fixup->fixup_rela_off, - sizeof (*imfs), fixup->fixup_rela_cnt, - _("dynamic section image fixups")); - if (!imfs) - return false; - - if (fixup->needed < strtab_sz) - lib_name =3D strtab + fixup->needed; - else - { - warn (_("corrupt library name index of %#" PRIx64 - " found in dynamic entry"), fixup->needed); - lib_name =3D "???"; - } - - printf (_("\nImage fixups for needed library #%" PRId64 - ": %s - ident: %" PRIx64 "\n"), - fixup->fixup_needed, lib_name, fixup->needed_ident); - printf - (_("Seg Offset Type SymVec DataT= ype\n")); - - for (i =3D 0; i < (size_t) fixup->fixup_rela_cnt; i++) - { - unsigned int type; - const char *rtype; - - printf ("%3u ", (unsigned) BYTE_GET (imfs [i].fixup_seg)); - printf ("%016" PRIx64 " ", BYTE_GET (imfs [i].fixup_offset)); - type =3D BYTE_GET (imfs [i].type); - rtype =3D elf_ia64_reloc_type (type); - if (rtype =3D=3D NULL) - printf ("0x%08x ", type); - else - printf ("%-32s ", rtype); - printf ("%6u ", (unsigned) BYTE_GET (imfs [i].symvec_index)); - printf ("0x%08x\n", (unsigned) BYTE_GET (imfs [i].data_type)); - } - - free (imfs); - return true; -} - -/* Display IA-64 OpenVMS dynamic relocations (used to relocate an image). = */ - -static bool -dump_ia64_vms_dynamic_relocs (Filedata * filedata, struct ia64_vms_dynimgr= ela *imgrela) -{ - Elf64_External_VMS_IMAGE_RELA *imrs; - size_t i; - - imrs =3D get_data (NULL, filedata, - filedata->dynamic_addr + imgrela->img_rela_off, - sizeof (*imrs), imgrela->img_rela_cnt, - _("dynamic section image relocations")); - if (!imrs) - return false; - - printf (_("\nImage relocs\n")); - printf - (_("Seg Offset Type Addend Seg= Sym Off\n")); - - for (i =3D 0; i < (size_t) imgrela->img_rela_cnt; i++) - { - unsigned int type; - const char *rtype; - - printf ("%3u ", (unsigned) BYTE_GET (imrs [i].rela_seg)); - printf ("%08" PRIx64 " ", BYTE_GET (imrs [i].rela_offset)); - type =3D BYTE_GET (imrs [i].type); - rtype =3D elf_ia64_reloc_type (type); - if (rtype =3D=3D NULL) - printf ("0x%08x ", type); - else - printf ("%-31s ", rtype); - print_vma (BYTE_GET (imrs [i].addend), FULL_HEX); - printf ("%3u ", (unsigned) BYTE_GET (imrs [i].sym_seg)); - printf ("%08" PRIx64 "\n", BYTE_GET (imrs [i].sym_offset)); - } - - free (imrs); - return true; -} - -/* Display IA-64 OpenVMS dynamic relocations and fixups. */ - -static bool -process_ia64_vms_dynamic_relocs (Filedata * filedata) -{ - struct ia64_vms_dynfixup fixup; - struct ia64_vms_dynimgrela imgrela; - Elf_Internal_Dyn *entry; - uint64_t strtab_off =3D 0; - uint64_t strtab_sz =3D 0; - char *strtab =3D NULL; - bool res =3D true; - - memset (&fixup, 0, sizeof (fixup)); - memset (&imgrela, 0, sizeof (imgrela)); - - /* Note: the order of the entries is specified by the OpenVMS specs. */ - for (entry =3D filedata->dynamic_section; - entry < filedata->dynamic_section + filedata->dynamic_nent; - entry++) - { - switch (entry->d_tag) - { - case DT_IA_64_VMS_STRTAB_OFFSET: - strtab_off =3D entry->d_un.d_val; - break; - case DT_STRSZ: - strtab_sz =3D entry->d_un.d_val; - if (strtab =3D=3D NULL) - strtab =3D get_data (NULL, filedata, - filedata->dynamic_addr + strtab_off, - 1, strtab_sz, _("dynamic string section")); - if (strtab =3D=3D NULL) - strtab_sz =3D 0; - break; - - case DT_IA_64_VMS_NEEDED_IDENT: - fixup.needed_ident =3D entry->d_un.d_val; - break; - case DT_NEEDED: - fixup.needed =3D entry->d_un.d_val; - break; - case DT_IA_64_VMS_FIXUP_NEEDED: - fixup.fixup_needed =3D entry->d_un.d_val; - break; - case DT_IA_64_VMS_FIXUP_RELA_CNT: - fixup.fixup_rela_cnt =3D entry->d_un.d_val; - break; - case DT_IA_64_VMS_FIXUP_RELA_OFF: - fixup.fixup_rela_off =3D entry->d_un.d_val; - if (! dump_ia64_vms_dynamic_fixups (filedata, &fixup, strtab, st= rtab_sz)) - res =3D false; - break; - case DT_IA_64_VMS_IMG_RELA_CNT: - imgrela.img_rela_cnt =3D entry->d_un.d_val; - break; - case DT_IA_64_VMS_IMG_RELA_OFF: - imgrela.img_rela_off =3D entry->d_un.d_val; - if (! dump_ia64_vms_dynamic_relocs (filedata, &imgrela)) - res =3D false; - break; - - default: - break; - } - } - - free (strtab); - - return res; -} - static struct { const char * name; @@ -9290,10 +8909,6 @@ process_relocs (Filedata * filedata) } } =20 - if (is_ia64_vms (filedata)) - if (process_ia64_vms_dynamic_relocs (filedata)) - has_dynamic_reloc =3D true; - if (! has_dynamic_reloc) { if (filedata->is_separate) @@ -9340,522 +8955,83 @@ process_relocs (Filedata * filedata) printf (_("\nThere are no relocations in linked file '%s'.\n"), filedata->file_name); else - printf (_("\nThere are no relocations in this file.\n")); - } - } - } - - return true; -} - -/* An absolute address consists of a section and an offset. If the - section is NULL, the offset itself is the address, otherwise, the - address equals to LOAD_ADDRESS(section) + offset. */ - -struct absaddr -{ - unsigned short section; - uint64_t offset; -}; - -/* Find the nearest symbol at or below ADDR. Returns the symbol - name, if found, and the offset from the symbol to ADDR. */ - -static void -find_symbol_for_address (Filedata *filedata, - Elf_Internal_Sym *symtab, - uint64_t nsyms, - const char *strtab, - uint64_t strtab_size, - struct absaddr addr, - const char **symname, - uint64_t *offset) -{ - uint64_t dist =3D 0x100000; - Elf_Internal_Sym * sym; - Elf_Internal_Sym * beg; - Elf_Internal_Sym * end; - Elf_Internal_Sym * best =3D NULL; - - REMOVE_ARCH_BITS (addr.offset); - beg =3D symtab; - end =3D symtab + nsyms; - - while (beg < end) - { - uint64_t value; - - sym =3D beg + (end - beg) / 2; - - value =3D sym->st_value; - REMOVE_ARCH_BITS (value); - - if (sym->st_name !=3D 0 - && (addr.section =3D=3D SHN_UNDEF || addr.section =3D=3D sym->st_shndx) - && addr.offset >=3D value - && addr.offset - value < dist) - { - best =3D sym; - dist =3D addr.offset - value; - if (!dist) - break; - } - - if (addr.offset < value) - end =3D sym; - else - beg =3D sym + 1; - } - - if (best) - { - *symname =3D (best->st_name >=3D strtab_size - ? _("") : strtab + best->st_name); - *offset =3D dist; - return; - } - - *symname =3D NULL; - *offset =3D addr.offset; -} - -/* Process the unwind section. */ - -#include "unwind-ia64.h" - -struct ia64_unw_table_entry -{ - struct absaddr start; - struct absaddr end; - struct absaddr info; -}; - -struct ia64_unw_aux_info -{ - struct ia64_unw_table_entry * table; /* Unwind table. */ - uint64_t table_len; /* Length of unwind table. */ - unsigned char * info; /* Unwind info. */ - uint64_t info_size; /* Size of unwind info. */ - uint64_t info_addr; /* Starting address of unwind i= nfo. */ - uint64_t seg_base; /* Starting address of segment. = */ - Elf_Internal_Sym * symtab; /* The symbol table. */ - uint64_t nsyms; /* Number of symbols. */ - Elf_Internal_Sym * funtab; /* Sorted table of STT_FUNC symbo= ls. */ - uint64_t nfuns; /* Number of entries in funtab. */ - char * strtab; /* The string table. */ - uint64_t strtab_size; /* Size of string table. */ -}; - -static bool -dump_ia64_unwind (Filedata * filedata, struct ia64_unw_aux_info * aux) -{ - struct ia64_unw_table_entry * tp; - size_t j, nfuns; - int in_body; - bool res =3D true; - - aux->funtab =3D xmalloc (aux->nsyms * sizeof (Elf_Internal_Sym)); - for (nfuns =3D 0, j =3D 0; j < aux->nsyms; j++) - if (aux->symtab[j].st_value && ELF_ST_TYPE (aux->symtab[j].st_info) = =3D=3D STT_FUNC) - aux->funtab[nfuns++] =3D aux->symtab[j]; - aux->nfuns =3D nfuns; - qsort (aux->funtab, aux->nfuns, sizeof (Elf_Internal_Sym), symcmp); - - for (tp =3D aux->table; tp < aux->table + aux->table_len; ++tp) - { - uint64_t stamp; - uint64_t offset; - const unsigned char * dp; - const unsigned char * head; - const unsigned char * end; - const char * procname; - - find_symbol_for_address (filedata, aux->funtab, aux->nfuns, aux->str= tab, - aux->strtab_size, tp->start, &procname, &offset); - - fputs ("\n<", stdout); - - if (procname) - { - fputs (procname, stdout); - - if (offset) - printf ("+%" PRIx64, offset); - } - - fputs (">: [", stdout); - print_vma (tp->start.offset, PREFIX_HEX); - fputc ('-', stdout); - print_vma (tp->end.offset, PREFIX_HEX); - printf ("], info at +0x%" PRIx64 "\n", - tp->info.offset - aux->seg_base); - - /* PR 17531: file: 86232b32. */ - if (aux->info =3D=3D NULL) - continue; - - offset =3D tp->info.offset; - if (tp->info.section) - { - if (tp->info.section >=3D filedata->file_header.e_shnum) - { - warn (_("Invalid section %u in table entry %td\n"), - tp->info.section, tp - aux->table); - res =3D false; - continue; - } - offset +=3D filedata->section_headers[tp->info.section].sh_addr; - } - offset -=3D aux->info_addr; - /* PR 17531: file: 0997b4d1. */ - if (offset >=3D aux->info_size - || aux->info_size - offset < 8) - { - warn (_("Invalid offset %" PRIx64 " in table entry %td\n"), - tp->info.offset, tp - aux->table); - res =3D false; - continue; - } - - head =3D aux->info + offset; - stamp =3D byte_get ((unsigned char *) head, sizeof (stamp)); - - printf (" v%u, flags=3D0x%lx (%s%s), len=3D%lu bytes\n", - (unsigned) UNW_VER (stamp), - (unsigned long) ((stamp & UNW_FLAG_MASK) >> 32), - UNW_FLAG_EHANDLER (stamp) ? " ehandler" : "", - UNW_FLAG_UHANDLER (stamp) ? " uhandler" : "", - (unsigned long) (eh_addr_size * UNW_LENGTH (stamp))); - - if (UNW_VER (stamp) !=3D 1) - { - printf (_("\tUnknown version.\n")); - continue; - } - - in_body =3D 0; - end =3D head + 8 + eh_addr_size * UNW_LENGTH (stamp); - /* PR 17531: file: 16ceda89. */ - if (end > aux->info + aux->info_size) - end =3D aux->info + aux->info_size; - for (dp =3D head + 8; dp < end;) - dp =3D unw_decode (dp, in_body, & in_body, end); - } - - free (aux->funtab); - - return res; -} - -static bool -slurp_ia64_unwind_table (Filedata * filedata, - struct ia64_unw_aux_info * aux, - Elf_Internal_Shdr * sec) -{ - uint64_t size, nrelas, i; - Elf_Internal_Phdr * seg; - struct ia64_unw_table_entry * tep; - Elf_Internal_Shdr * relsec; - Elf_Internal_Rela * rela; - Elf_Internal_Rela * rp; - unsigned char * table; - unsigned char * tp; - Elf_Internal_Sym * sym; - const char * relname; - - aux->table_len =3D 0; - - /* First, find the starting address of the segment that includes - this section: */ - - if (filedata->file_header.e_phnum) - { - if (! get_program_headers (filedata)) - return false; - - for (seg =3D filedata->program_headers; - seg < filedata->program_headers + filedata->file_header.e_phnum; - ++seg) - { - if (seg->p_type !=3D PT_LOAD) - continue; - - if (sec->sh_addr >=3D seg->p_vaddr - && (sec->sh_addr + sec->sh_size <=3D seg->p_vaddr + seg->p_memsz)) - { - aux->seg_base =3D seg->p_vaddr; - break; - } - } - } - - /* Second, build the unwind table from the contents of the unwind sectio= n: */ - size =3D sec->sh_size; - table =3D (unsigned char *) get_data (NULL, filedata, sec->sh_offset, 1,= size, - _("unwind table")); - if (!table) - return false; - - aux->table_len =3D size / (3 * eh_addr_size); - aux->table =3D (struct ia64_unw_table_entry *) - xcmalloc (aux->table_len, sizeof (aux->table[0])); - tep =3D aux->table; - - for (tp =3D table; tp <=3D table + size - (3 * eh_addr_size); ++tep) - { - tep->start.section =3D SHN_UNDEF; - tep->end.section =3D SHN_UNDEF; - tep->info.section =3D SHN_UNDEF; - tep->start.offset =3D byte_get (tp, eh_addr_size); tp +=3D eh_addr_s= ize; - tep->end.offset =3D byte_get (tp, eh_addr_size); tp +=3D eh_addr_s= ize; - tep->info.offset =3D byte_get (tp, eh_addr_size); tp +=3D eh_addr_s= ize; - tep->start.offset +=3D aux->seg_base; - tep->end.offset +=3D aux->seg_base; - tep->info.offset +=3D aux->seg_base; - } - free (table); - - /* Third, apply any relocations to the unwind table: */ - for (relsec =3D filedata->section_headers; - relsec < filedata->section_headers + filedata->file_header.e_shnum; - ++relsec) - { - if (relsec->sh_type !=3D SHT_RELA - || relsec->sh_info >=3D filedata->file_header.e_shnum - || filedata->section_headers + relsec->sh_info !=3D sec) - continue; - - if (!slurp_rela_relocs (filedata, relsec->sh_offset, relsec->sh_size, - & rela, & nrelas)) - { - free (aux->table); - aux->table =3D NULL; - aux->table_len =3D 0; - return false; - } - - for (rp =3D rela; rp < rela + nrelas; ++rp) - { - unsigned int sym_ndx; - unsigned int r_type =3D get_reloc_type (filedata, rp->r_info); - relname =3D elf_ia64_reloc_type (r_type); - - /* PR 17531: file: 9fa67536. */ - if (relname =3D=3D NULL) - { - warn (_("Skipping unknown relocation type: %u\n"), r_type); - continue; - } - - if (! startswith (relname, "R_IA64_SEGREL")) - { - warn (_("Skipping unexpected relocation type: %s\n"), relname); - continue; - } - - i =3D rp->r_offset / (3 * eh_addr_size); - - /* PR 17531: file: 5bc8d9bf. */ - if (i >=3D aux->table_len) - { - warn (_("Skipping reloc with overlarge offset: %#" PRIx64 "\n"), - i); - continue; - } - - sym_ndx =3D get_reloc_symindex (rp->r_info); - if (sym_ndx >=3D aux->nsyms) - { - warn (_("Skipping reloc with invalid symbol index: %u\n"), - sym_ndx); - continue; - } - sym =3D aux->symtab + sym_ndx; - - switch (rp->r_offset / eh_addr_size % 3) - { - case 0: - aux->table[i].start.section =3D sym->st_shndx; - aux->table[i].start.offset =3D rp->r_addend + sym->st_value; - break; - case 1: - aux->table[i].end.section =3D sym->st_shndx; - aux->table[i].end.offset =3D rp->r_addend + sym->st_value; - break; - case 2: - aux->table[i].info.section =3D sym->st_shndx; - aux->table[i].info.offset =3D rp->r_addend + sym->st_value; - break; - default: - break; - } - } - - free (rela); - } - - return true; -} - -static bool -ia64_process_unwind (Filedata * filedata) -{ - Elf_Internal_Shdr * sec; - Elf_Internal_Shdr * unwsec =3D NULL; - uint64_t i, unwcount =3D 0, unwstart =3D 0; - struct ia64_unw_aux_info aux; - bool res =3D true; - - memset (& aux, 0, sizeof (aux)); - - for (i =3D 0, sec =3D filedata->section_headers; i < filedata->file_head= er.e_shnum; ++i, ++sec) - { - if (sec->sh_type =3D=3D SHT_SYMTAB) - { - if (aux.symtab) - { - error (_("Multiple symbol tables encountered\n")); - free (aux.symtab); - aux.symtab =3D NULL; - free (aux.strtab); - aux.strtab =3D NULL; + printf (_("\nThere are no relocations in this file.\n")); } - if (!get_symtab (filedata, sec, &aux.symtab, &aux.nsyms, - &aux.strtab, &aux.strtab_size)) - return false; } - else if (sec->sh_type =3D=3D SHT_IA_64_UNWIND) - unwcount++; } =20 - if (!unwcount) - printf (_("\nThere are no unwind sections in this file.\n")); + return true; +} =20 - while (unwcount-- > 0) - { - const char *suffix; - size_t len, len2; +/* An absolute address consists of a section and an offset. If the + section is NULL, the offset itself is the address, otherwise, the + address equals to LOAD_ADDRESS(section) + offset. */ =20 - for (i =3D unwstart, sec =3D filedata->section_headers + unwstart, u= nwsec =3D NULL; - i < filedata->file_header.e_shnum; ++i, ++sec) - if (sec->sh_type =3D=3D SHT_IA_64_UNWIND) - { - unwsec =3D sec; - break; - } - /* We have already counted the number of SHT_IA64_UNWIND - sections so the loop above should never fail. */ - assert (unwsec !=3D NULL); +struct absaddr +{ + unsigned short section; + uint64_t offset; +}; =20 - unwstart =3D i + 1; - len =3D sizeof (ELF_STRING_ia64_unwind_once) - 1; +/* Find the nearest symbol at or below ADDR. Returns the symbol + name, if found, and the offset from the symbol to ADDR. */ =20 - if ((unwsec->sh_flags & SHF_GROUP) !=3D 0) - { - /* We need to find which section group it is in. */ - struct group_list * g; +static void +find_symbol_for_address (Filedata *filedata, + Elf_Internal_Sym *symtab, + uint64_t nsyms, + const char *strtab, + uint64_t strtab_size, + struct absaddr addr, + const char **symname, + uint64_t *offset) +{ + uint64_t dist =3D 0x100000; + Elf_Internal_Sym * sym; + Elf_Internal_Sym * beg; + Elf_Internal_Sym * end; + Elf_Internal_Sym * best =3D NULL; =20 - if (filedata->section_headers_groups =3D=3D NULL - || filedata->section_headers_groups[i] =3D=3D NULL) - i =3D filedata->file_header.e_shnum; - else - { - g =3D filedata->section_headers_groups[i]->root; + REMOVE_ARCH_BITS (addr.offset); + beg =3D symtab; + end =3D symtab + nsyms; =20 - for (; g !=3D NULL; g =3D g->next) - { - sec =3D filedata->section_headers + g->section_index; + while (beg < end) + { + uint64_t value; =20 - if (section_name_valid (filedata, sec) - && streq (section_name (filedata, sec), - ELF_STRING_ia64_unwind_info)) - break; - } + sym =3D beg + (end - beg) / 2; =20 - if (g =3D=3D NULL) - i =3D filedata->file_header.e_shnum; - } - } - else if (section_name_valid (filedata, unwsec) - && startswith (section_name (filedata, unwsec), - ELF_STRING_ia64_unwind_once)) - { - /* .gnu.linkonce.ia64unw.FOO -> .gnu.linkonce.ia64unwi.FOO. */ - len2 =3D sizeof (ELF_STRING_ia64_unwind_info_once) - 1; - suffix =3D section_name (filedata, unwsec) + len; - for (i =3D 0, sec =3D filedata->section_headers; - i < filedata->file_header.e_shnum; - ++i, ++sec) - if (section_name_valid (filedata, sec) - && startswith (section_name (filedata, sec), - ELF_STRING_ia64_unwind_info_once) - && streq (section_name (filedata, sec) + len2, suffix)) - break; - } - else - { - /* .IA_64.unwindFOO -> .IA_64.unwind_infoFOO - .IA_64.unwind or BAR -> .IA_64.unwind_info. */ - len =3D sizeof (ELF_STRING_ia64_unwind) - 1; - len2 =3D sizeof (ELF_STRING_ia64_unwind_info) - 1; - suffix =3D ""; - if (section_name_valid (filedata, unwsec) - && startswith (section_name (filedata, unwsec), - ELF_STRING_ia64_unwind)) - suffix =3D section_name (filedata, unwsec) + len; - for (i =3D 0, sec =3D filedata->section_headers; - i < filedata->file_header.e_shnum; - ++i, ++sec) - if (section_name_valid (filedata, sec) - && startswith (section_name (filedata, sec), - ELF_STRING_ia64_unwind_info) - && streq (section_name (filedata, sec) + len2, suffix)) - break; - } + value =3D sym->st_value; + REMOVE_ARCH_BITS (value); =20 - if (i =3D=3D filedata->file_header.e_shnum) + if (sym->st_name !=3D 0 + && (addr.section =3D=3D SHN_UNDEF || addr.section =3D=3D sym->st_shndx) + && addr.offset >=3D value + && addr.offset - value < dist) { - printf (_("\nCould not find unwind info section for ")); - - if (filedata->string_table =3D=3D NULL) - printf ("%d", unwsec->sh_name); - else - printf ("'%s'", printable_section_name (filedata, unwsec)); + best =3D sym; + dist =3D addr.offset - value; + if (!dist) + break; } - else - { - aux.info_addr =3D sec->sh_addr; - aux.info =3D (unsigned char *) get_data (NULL, filedata, sec->sh_offset= , 1, - sec->sh_size, - _("unwind info")); - aux.info_size =3D aux.info =3D=3D NULL ? 0 : sec->sh_size; - - printf (_("\nUnwind section ")); =20 - if (filedata->string_table =3D=3D NULL) - printf ("%d", unwsec->sh_name); - else - printf ("'%s'", printable_section_name (filedata, unwsec)); - - printf (_(" at offset %#" PRIx64 " contains %" PRIu64 " entries:\n"), - unwsec->sh_offset, - unwsec->sh_size / (3 * eh_addr_size)); - - if (slurp_ia64_unwind_table (filedata, & aux, unwsec) - && aux.table_len > 0) - dump_ia64_unwind (filedata, & aux); - - free ((char *) aux.table); - free ((char *) aux.info); - aux.table =3D NULL; - aux.info =3D NULL; - } + if (addr.offset < value) + end =3D sym; + else + beg =3D sym + 1; } =20 - free (aux.symtab); - free ((char *) aux.strtab); + if (best) + { + *symname =3D (best->st_name >=3D strtab_size + ? _("") : strtab + best->st_name); + *offset =3D dist; + return; + } =20 - return res; + *symname =3D NULL; + *offset =3D addr.offset; } =20 struct hppa_unw_table_entry @@ -11352,7 +10528,6 @@ process_unwind (Filedata * filedata) } handlers[] =3D { { EM_ARM, arm_process_unwind }, - { EM_IA_64, ia64_process_unwind }, { EM_PARISC, hppa_process_unwind }, { EM_TI_C6000, arm_process_unwind }, { EM_386, no_processor_specific_unwind }, @@ -11542,84 +10717,6 @@ dynamic_section_parisc_val (Elf_Internal_Dyn * ent= ry) #define INT64_MIN (-9223372036854775807LL - 1) #endif =20 -/* Display a VMS time in a human readable format. */ - -static void -print_vms_time (int64_t vmstime) -{ - struct tm *tm =3D NULL; - time_t unxtime; - - if (vmstime >=3D INT64_MIN + VMS_EPOCH_OFFSET) - { - vmstime =3D (vmstime - VMS_EPOCH_OFFSET) / VMS_GRANULARITY_FACTOR; - unxtime =3D vmstime; - if (unxtime =3D=3D vmstime) - tm =3D gmtime (&unxtime); - } - if (tm !=3D NULL) - printf ("%04u-%02u-%02uT%02u:%02u:%02u", - tm->tm_year + 1900, tm->tm_mon + 1, tm->tm_mday, - tm->tm_hour, tm->tm_min, tm->tm_sec); -} - -static void -dynamic_section_ia64_val (Elf_Internal_Dyn * entry) -{ - switch (entry->d_tag) - { - case DT_IA_64_PLT_RESERVE: - /* First 3 slots reserved. */ - print_vma (entry->d_un.d_ptr, PREFIX_HEX); - printf (" -- "); - print_vma (entry->d_un.d_ptr + (3 * 8), PREFIX_HEX); - break; - - case DT_IA_64_VMS_LINKTIME: - print_vms_time (entry->d_un.d_val); - break; - - case DT_IA_64_VMS_LNKFLAGS: - print_vma (entry->d_un.d_ptr, PREFIX_HEX); - if (entry->d_un.d_val & VMS_LF_CALL_DEBUG) - printf (" CALL_DEBUG"); - if (entry->d_un.d_val & VMS_LF_NOP0BUFS) - printf (" NOP0BUFS"); - if (entry->d_un.d_val & VMS_LF_P0IMAGE) - printf (" P0IMAGE"); - if (entry->d_un.d_val & VMS_LF_MKTHREADS) - printf (" MKTHREADS"); - if (entry->d_un.d_val & VMS_LF_UPCALLS) - printf (" UPCALLS"); - if (entry->d_un.d_val & VMS_LF_IMGSTA) - printf (" IMGSTA"); - if (entry->d_un.d_val & VMS_LF_INITIALIZE) - printf (" INITIALIZE"); - if (entry->d_un.d_val & VMS_LF_MAIN) - printf (" MAIN"); - if (entry->d_un.d_val & VMS_LF_EXE_INIT) - printf (" EXE_INIT"); - if (entry->d_un.d_val & VMS_LF_TBK_IN_IMG) - printf (" TBK_IN_IMG"); - if (entry->d_un.d_val & VMS_LF_DBG_IN_IMG) - printf (" DBG_IN_IMG"); - if (entry->d_un.d_val & VMS_LF_TBK_IN_DSF) - printf (" TBK_IN_DSF"); - if (entry->d_un.d_val & VMS_LF_DBG_IN_DSF) - printf (" DBG_IN_DSF"); - if (entry->d_un.d_val & VMS_LF_SIGNATURES) - printf (" SIGNATURES"); - if (entry->d_un.d_val & VMS_LF_REL_SEG_OFF) - printf (" REL_SEG_OFF"); - break; - - default: - print_vma (entry->d_un.d_ptr, PREFIX_HEX); - break; - } - putchar ('\n'); -} - static bool get_32bit_dynamic_section (Filedata * filedata) { @@ -12809,9 +11906,6 @@ the .dynstr section doesn't match the DT_STRTAB and= DT_STRSZ tags\n")); case EM_PARISC: dynamic_section_parisc_val (entry); break; - case EM_IA_64: - dynamic_section_ia64_val (entry); - break; default: print_vma (entry->d_un.d_val, PREFIX_HEX); putchar ('\n'); @@ -13580,73 +12674,6 @@ get_mips_symbol_other (unsigned int other) } } =20 -static const char * -get_ia64_symbol_other (Filedata * filedata, unsigned int other) -{ - if (is_ia64_vms (filedata)) - { - static char res[32]; - - res[0] =3D 0; - - /* Function types is for images and .STB files only. */ - switch (filedata->file_header.e_type) - { - case ET_DYN: - case ET_EXEC: - switch (VMS_ST_FUNC_TYPE (other)) - { - case VMS_SFT_CODE_ADDR: - strcat (res, " CA"); - break; - case VMS_SFT_SYMV_IDX: - strcat (res, " VEC"); - break; - case VMS_SFT_FD: - strcat (res, " FD"); - break; - case VMS_SFT_RESERVE: - strcat (res, " RSV"); - break; - default: - warn (_("Unrecognized IA64 VMS ST Function type: %d\n"), - VMS_ST_FUNC_TYPE (other)); - strcat (res, " "); - break; - } - break; - default: - break; - } - switch (VMS_ST_LINKAGE (other)) - { - case VMS_STL_IGNORE: - strcat (res, " IGN"); - break; - case VMS_STL_RESERVE: - strcat (res, " RSV"); - break; - case VMS_STL_STD: - strcat (res, " STD"); - break; - case VMS_STL_LNK: - strcat (res, " LNK"); - break; - default: - warn (_("Unrecognized IA64 VMS ST Linkage: %d\n"), - VMS_ST_LINKAGE (other)); - strcat (res, " "); - break; - } - - if (res[0] !=3D 0) - return res + 1; - else - return res; - } - return NULL; -} - static const char * get_ppc64_symbol_other (unsigned int other) { @@ -13707,9 +12734,6 @@ get_symbol_other (Filedata * filedata, unsigned int= other) case EM_MIPS: result =3D get_mips_symbol_other (other); break; - case EM_IA_64: - result =3D get_ia64_symbol_other (filedata, other); - break; case EM_PPC64: result =3D get_ppc64_symbol_other (other); break; @@ -15155,11 +14179,6 @@ is_32bit_abs_reloc (Filedata * filedata, unsigned = int reloc_type) case EM_H8_300: case EM_H8_300H: return reloc_type =3D=3D 1; /* R_H8_DIR32. */ - case EM_IA_64: - return (reloc_type =3D=3D 0x64 /* R_IA64_SECREL32MSB. */ - || reloc_type =3D=3D 0x65 /* R_IA64_SECREL32LSB. */ - || reloc_type =3D=3D 0x24 /* R_IA64_DIR32MSB. */ - || reloc_type =3D=3D 0x25 /* R_IA64_DIR32LSB. */); case EM_IP2K_OLD: case EM_IP2K: return reloc_type =3D=3D 2; /* R_IP2K_32. */ @@ -15390,9 +14409,6 @@ is_64bit_abs_reloc (Filedata * filedata, unsigned i= nt reloc_type) return reloc_type =3D=3D 5; /* R_ARC_64. */ case EM_ALPHA: return reloc_type =3D=3D 2; /* R_ALPHA_REFQUAD. */ - case EM_IA_64: - return (reloc_type =3D=3D 0x26 /* R_IA64_DIR64MSB. */ - || reloc_type =3D=3D 0x27 /* R_IA64_DIR64LSB. */); case EM_LOONGARCH: return reloc_type =3D=3D 2; /* R_LARCH_64 */ case EM_PARISC: @@ -15436,9 +14452,6 @@ is_64bit_pcrel_reloc (Filedata * filedata, unsigned= int reloc_type) return reloc_type =3D=3D 260; /* R_AARCH64_PREL64. */ case EM_ALPHA: return reloc_type =3D=3D 11; /* R_ALPHA_SREL64. */ - case EM_IA_64: - return (reloc_type =3D=3D 0x4e /* R_IA64_PCREL64MSB. */ - || reloc_type =3D=3D 0x4f /* R_IA64_PCREL64LSB. */); case EM_PARISC: return reloc_type =3D=3D 72; /* R_PARISC_PCREL64. */ case EM_PPC64: @@ -15788,7 +14801,6 @@ is_none_reloc (Filedata * filedata, unsigned int re= loc_type) case EM_ARM: /* R_ARM_NONE. */ case EM_CRIS: /* R_CRIS_NONE. */ case EM_FT32: /* R_FT32_NONE. */ - case EM_IA_64: /* R_IA64_NONE. */ case EM_K1OM: /* R_X86_64_NONE. */ case EM_KVX: /* R_KVX_NONE. */ case EM_L1OM: /* R_X86_64_NONE. */ @@ -16998,8 +16010,6 @@ get_build_id (void * data) end =3D (char *) enote + length; data_remaining =3D end - (char *) enote; =20 - if (!is_ia64_vms (filedata)) - { min_notesz =3D offsetof (Elf_External_Note, name); if (data_remaining < min_notesz) { @@ -17020,33 +16030,6 @@ malformed note encountered in section %s whilst sc= anning for build-id note\n"), inote.descpos =3D offset + (inote.descdata - (char *) enote); next =3D ((char *) enote + ELF_NOTE_NEXT_OFFSET (inote.namesz, inote.descsz, alig= n)); - } - else - { - Elf64_External_VMS_Note *vms_enote; - - /* PR binutils/15191 - Make sure that there is enough data to read. */ - min_notesz =3D offsetof (Elf64_External_VMS_Note, name); - if (data_remaining < min_notesz) - { - warn (_("\ -malformed note encountered in section %s whilst scanning for build-id note= \n"), - printable_section_name (filedata, shdr)); - free (enote); - continue; - } - data_remaining -=3D min_notesz; - - vms_enote =3D (Elf64_External_VMS_Note *) enote; - inote.type =3D BYTE_GET (vms_enote->type); - inote.namesz =3D BYTE_GET (vms_enote->namesz); - inote.namedata =3D vms_enote->name; - inote.descsz =3D BYTE_GET (vms_enote->descsz); - inote.descdata =3D inote.namedata + align_power (inote.namesz, 3= ); - inote.descpos =3D offset + (inote.descdata - (char *) enote); - next =3D inote.descdata + align_power (inote.descsz, 3); - } =20 /* Skip malformed notes. */ if ((size_t) (inote.descdata - inote.namedata) < inote.namesz @@ -21780,159 +20763,6 @@ print_fdo_note (Elf_Internal_Note * pnote) return false; } =20 -static const char * -get_ia64_vms_note_type (unsigned e_type) -{ - static char buff[64]; - - switch (e_type) - { - case NT_VMS_MHD: - return _("NT_VMS_MHD (module header)"); - case NT_VMS_LNM: - return _("NT_VMS_LNM (language name)"); - case NT_VMS_SRC: - return _("NT_VMS_SRC (source files)"); - case NT_VMS_TITLE: - return "NT_VMS_TITLE"; - case NT_VMS_EIDC: - return _("NT_VMS_EIDC (consistency check)"); - case NT_VMS_FPMODE: - return _("NT_VMS_FPMODE (FP mode)"); - case NT_VMS_LINKTIME: - return "NT_VMS_LINKTIME"; - case NT_VMS_IMGNAM: - return _("NT_VMS_IMGNAM (image name)"); - case NT_VMS_IMGID: - return _("NT_VMS_IMGID (image id)"); - case NT_VMS_LINKID: - return _("NT_VMS_LINKID (link id)"); - case NT_VMS_IMGBID: - return _("NT_VMS_IMGBID (build id)"); - case NT_VMS_GSTNAM: - return _("NT_VMS_GSTNAM (sym table name)"); - case NT_VMS_ORIG_DYN: - return "NT_VMS_ORIG_DYN"; - case NT_VMS_PATCHTIME: - return "NT_VMS_PATCHTIME"; - default: - snprintf (buff, sizeof (buff), _("Unknown note type: (0x%08x)"), e_t= ype); - return buff; - } -} - -static bool -print_ia64_vms_note (Elf_Internal_Note * pnote) -{ - unsigned int maxlen =3D pnote->descsz; - - if (maxlen < 2 || maxlen !=3D pnote->descsz) - goto desc_size_fail; - - switch (pnote->type) - { - case NT_VMS_MHD: - if (maxlen <=3D 36) - goto desc_size_fail; - - size_t l =3D strnlen (pnote->descdata + 34, maxlen - 34); - - printf (_(" Creation date : %.17s\n"), pnote->descdata); - printf (_(" Last patch date: %.17s\n"), pnote->descdata + 17); - if (l + 34 < maxlen) - { - printf (_(" Module name : %s\n"), pnote->descdata + 34); - if (l + 35 < maxlen) - printf (_(" Module version : %s\n"), pnote->descdata + 34 + l + 1); - else - printf (_(" Module version : \n")); - } - else - { - printf (_(" Module name : \n")); - printf (_(" Module version : \n")); - } - break; - - case NT_VMS_LNM: - printf (_(" Language: %.*s\n"), maxlen, pnote->descdata); - break; - - case NT_VMS_FPMODE: - printf (_(" Floating Point mode: ")); - if (maxlen < 8) - goto desc_size_fail; - /* FIXME: Generate an error if descsz > 8 ? */ - - printf ("0x%016" PRIx64 "\n", - byte_get ((unsigned char *) pnote->descdata, 8)); - break; - - case NT_VMS_LINKTIME: - printf (_(" Link time: ")); - if (maxlen < 8) - goto desc_size_fail; - /* FIXME: Generate an error if descsz > 8 ? */ - - print_vms_time (byte_get ((unsigned char *) pnote->descdata, 8)); - printf ("\n"); - break; - - case NT_VMS_PATCHTIME: - printf (_(" Patch time: ")); - if (maxlen < 8) - goto desc_size_fail; - /* FIXME: Generate an error if descsz > 8 ? */ - - print_vms_time (byte_get ((unsigned char *) pnote->descdata, 8)); - printf ("\n"); - break; - - case NT_VMS_ORIG_DYN: - if (maxlen < 34) - goto desc_size_fail; - - printf (_(" Major id: %u, minor id: %u\n"), - (unsigned) byte_get ((unsigned char *) pnote->descdata, 4), - (unsigned) byte_get ((unsigned char *) pnote->descdata + 4, 4)); - printf (_(" Last modified : ")); - print_vms_time (byte_get ((unsigned char *) pnote->descdata + 8, 8)); - printf (_("\n Link flags : ")); - printf ("0x%016" PRIx64 "\n", - byte_get ((unsigned char *) pnote->descdata + 16, 8)); - printf (_(" Header flags: 0x%08x\n"), - (unsigned) byte_get ((unsigned char *) pnote->descdata + 24, 4)); - printf (_(" Image id : %.*s\n"), maxlen - 32, pnote->descdata += 32); - break; - - case NT_VMS_IMGNAM: - printf (_(" Image name: %.*s\n"), maxlen, pnote->descdata); - break; - - case NT_VMS_GSTNAM: - printf (_(" Global symbol table name: %.*s\n"), maxlen, pnote->de= scdata); - break; - - case NT_VMS_IMGID: - printf (_(" Image id: %.*s\n"), maxlen, pnote->descdata); - break; - - case NT_VMS_LINKID: - printf (_(" Linker id: %.*s\n"), maxlen, pnote->descdata); - break; - - default: - return false; - } - - return true; - - desc_size_fail: - printf (_(" \n")); - error (_("corrupt IA64 note: data size is too small\n")); - return false; -} - struct build_attr_cache { Filedata *filedata; char *strtab; @@ -22684,10 +21514,6 @@ process_note (Elf_Internal_Note * pnote, name =3D "SPU"; } =20 - else if (startswith (pnote->namedata, "IPF/VMS")) - /* VMS/ia64-specific file notes. */ - nt =3D get_ia64_vms_note_type (pnote->type); - else if (startswith (pnote->namedata, "stapsdt")) nt =3D get_stapsdt_note_type (pnote->type); =20 @@ -22712,9 +21538,7 @@ process_note (Elf_Internal_Note * pnote, else printf (" 0x%08lx\t%s\n", pnote->descsz, nt); =20 - if (startswith (pnote->namedata, "IPF/VMS")) - return print_ia64_vms_note (pnote); - else if (startswith (pnote->namedata, "GNU")) + if (startswith (pnote->namedata, "GNU")) return print_gnu_note (filedata, pnote); else if (startswith (pnote->namedata, "stapsdt")) return print_stapsdt_note (pnote); @@ -22811,8 +21635,6 @@ process_notes_at (Filedata * filedata, char * temp =3D NULL; size_t data_remaining =3D end - (char *) external; =20 - if (!is_ia64_vms (filedata)) - { /* PR binutils/15191 Make sure that there is enough data to read. */ min_notesz =3D offsetof (Elf_External_Note, name); @@ -22837,35 +21659,6 @@ process_notes_at (Filedata * filedata, inote.descpos =3D offset + (inote.descdata - (char *) pnotes); next =3D ((char *) external + ELF_NOTE_NEXT_OFFSET (inote.namesz, inote.descsz, align)); - } - else - { - Elf64_External_VMS_Note *vms_external; - - /* PR binutils/15191 - Make sure that there is enough data to read. */ - min_notesz =3D offsetof (Elf64_External_VMS_Note, name); - if (data_remaining < min_notesz) - { - warn (ngettext ("Corrupt note: only %zd byte remains, " - "not enough for a full note\n", - "Corrupt note: only %zd bytes remain, " - "not enough for a full note\n", - data_remaining), - data_remaining); - break; - } - data_remaining -=3D min_notesz; - - vms_external =3D (Elf64_External_VMS_Note *) external; - inote.type =3D BYTE_GET (vms_external->type); - inote.namesz =3D BYTE_GET (vms_external->namesz); - inote.namedata =3D vms_external->name; - inote.descsz =3D BYTE_GET (vms_external->descsz); - inote.descdata =3D inote.namedata + align_power (inote.namesz, 3); - inote.descpos =3D offset + (inote.descdata - (char *) pnotes); - next =3D inote.descdata + align_power (inote.descsz, 3); - } =20 /* PR 17531: file: 3443835e. */ /* PR 17531: file: id:000000,sig:11,src:006986,op:havoc,rep:4. */ diff --git a/binutils/testsuite/binutils-all/nm.exp b/binutils/testsuite/bi= nutils-all/nm.exp index 8fe4ce85f03..d77ce4b4a15 100644 --- a/binutils/testsuite/binutils-all/nm.exp +++ b/binutils/testsuite/binutils-all/nm.exp @@ -158,7 +158,6 @@ if { [is_elf_format] || [istarget *-*-rdos*] || [istarget *-*-tpf*] || [istarget *-*-uclinux*] - || [istarget ia64-*-*vms*] || [istarget *-*-vxworks*] || [istarget wasm32-*-*] || [istarget bpf-*-*]} { @@ -251,7 +250,7 @@ if [is_elf_format] { setup_xfail "sh*-*-*" # The pre-compiled dwarf info in dw4.s is not compatible with the # ALPHA, HPPA, IA64 and MIPS targets. - setup_xfail "alpha*-*-*" "hppa*-*-*" "ia64*-*-*" "mips*-*-*" + setup_xfail "alpha*-*-*" "hppa*-*-*" "mips*-*-*" # Assembling the source file triggers an ICE in the FT32 assembler. # FIXME: Fix the ICE... setup_xfail "ft32-*-*" diff --git a/binutils/testsuite/binutils-all/objcopy.exp b/binutils/testsui= te/binutils-all/objcopy.exp index 8b432f3b48c..130efd1e7ac 100644 --- a/binutils/testsuite/binutils-all/objcopy.exp +++ b/binutils/testsuite/binutils-all/objcopy.exp @@ -1209,12 +1209,6 @@ proc objcopy_test_elf_common_symbols {} { } } =20 -# ia64 specific tests -if { ([istarget "ia64-*-elf*"] - || [istarget "ia64-*-linux*"]) } { - objcopy_test "ia64 link order" link-order.s object "" "" -} - # ELF specific tests set elf64 "" if [is_elf_format] { @@ -1292,8 +1286,7 @@ if [is_elf_format] { # supported by the target and ABI being tested. if { [istarget "aarch64*-*"] } { set reloc 259 - } elseif { [istarget "ia64*-*"] \ - || [istarget "m32r*-*"] \ + } elseif { [istarget "m32r*-*"] \ || [istarget "nds32*-*"] \ || [istarget "v850*-*"] } { set reloc 50 @@ -1342,7 +1335,6 @@ if [is_elf_format] { } run_dump_test "localize-hidden-1" run_dump_test "testranges" - run_dump_test "testranges-ia64" =20 run_dump_test "add-section" run_dump_test "add-symbol" diff --git a/binutils/testsuite/binutils-all/objdump.exp b/binutils/testsui= te/binutils-all/objdump.exp index 493e31b1281..7f3c99bea61 100644 --- a/binutils/testsuite/binutils-all/objdump.exp +++ b/binutils/testsuite/binutils-all/objdump.exp @@ -490,7 +490,6 @@ if { ![is_elf_format] } then { =20 if { ![is_elf_format] || [istarget "hppa64*-*-hpux*"] - || [istarget "ia64*-*-*"] || [istarget "mcore-*-*"] || [istarget "moxie-*-*"] } then { diff --git a/binutils/testsuite/binutils-all/testranges-ia64.d b/binutils/t= estsuite/binutils-all/testranges-ia64.d deleted file mode 100644 index e1e29e71632..00000000000 --- a/binutils/testsuite/binutils-all/testranges-ia64.d +++ /dev/null @@ -1,15 +0,0 @@ -#PROG: objcopy -#source: testranges-ia64.s -#readelf: -wR --wide -#name: unordered .debug_info references to .debug_ranges -#target: ia64-*-* - -Contents of the .debug_ranges section: - - Offset Begin End - 00000000 00000001 00000002 ? - 00000000 - 00000010 00000000 00000002 ? - 00000010 - -#pass diff --git a/binutils/testsuite/binutils-all/testranges-ia64.s b/binutils/t= estsuite/binutils-all/testranges-ia64.s deleted file mode 100644 index 9af6b634c1d..00000000000 --- a/binutils/testsuite/binutils-all/testranges-ia64.s +++ /dev/null @@ -1,57 +0,0 @@ -# Test .debug_info can reference .debug_ranges entries without ordering the -# offsets strictly as increasing. - - .text -start: - .byte 1 -sub: - .byte 2 -end: - - .section .debug_ranges,"",@progbits -range: - -range_sub: - data4.ua @secrel(sub), @secrel(end) - data4.ua 0, 0 /* range terminator */ - -range_cu: - data4.ua @secrel(start), @secrel(end) - data4.ua 0, 0 /* range terminator */ - - .section .debug_info,"",@progbits - data4.ua debugE - debugS /* Length of Compilation Unit Info */ -debugS: - .short 0x2 /* DWARF version number */ - data4.ua @secrel(abbrev0) /* Offset Into Abbrev. Section */ - .byte 0x4 /* Pointer Size (in bytes) */ - - .uleb128 0x1 /* (DIE (0xb) DW_TAG_compile_unit) */ - data4.ua range_cu - range /* DW_AT_ranges */ - - .uleb128 0x2 /* (DIE (0x6d) DW_TAG_subprogram) */ - .ascii "A\0" /* DW_AT_name */ - data4.ua range_sub - range /* DW_AT_ranges */ -debugE: - - .section .debug_abbrev,"",@progbits -abbrev0: - .uleb128 0x1 /* (abbrev code) */ - .uleb128 0x11 /* (TAG: DW_TAG_compile_unit) */ - .byte 0x0 /* DW_children_no */ - .uleb128 0x55 /* (DW_AT_ranges) */ - .uleb128 0x6 /* (DW_FORM_data4) */ - .byte 0x0 - .byte 0x0 - - .uleb128 0x2 /* (abbrev code) */ - .uleb128 0x2e /* (TAG: DW_TAG_subprogram) */ - .byte 0x0 /* DW_children_no */ - .uleb128 0x3 /* (DW_AT_name) */ - .uleb128 0x8 /* (DW_FORM_string) */ - .uleb128 0x55 /* (DW_AT_ranges) */ - .uleb128 0x6 /* (DW_FORM_data4) */ - .byte 0x0 - .byte 0x0 - - .byte 0x0 /* abbrevs terminator */ diff --git a/binutils/testsuite/binutils-all/testranges.d b/binutils/testsu= ite/binutils-all/testranges.d index dd2017557e7..32664fec50f 100644 --- a/binutils/testsuite/binutils-all/testranges.d +++ b/binutils/testsuite/binutils-all/testranges.d @@ -2,7 +2,6 @@ #source: testranges.s #readelf: -wR --wide #name: unordered .debug_info references to .debug_ranges -#notarget: ia64-*-* =20 Contents of the \.z?debug_ranges section: =20 diff --git a/binutils/testsuite/lib/binutils-common.exp b/binutils/testsuit= e/lib/binutils-common.exp index 2fca43bac48..bee9ee84040 100644 --- a/binutils/testsuite/lib/binutils-common.exp +++ b/binutils/testsuite/lib/binutils-common.exp @@ -54,8 +54,7 @@ proc is_elf_format {} { && ![istarget *-*-wasm32*] && ![istarget avr-*-*] && ![istarget hppa*64*-*-hpux*] - && ![istarget i?86-*-beos*] - && ![istarget ia64-*-hpux*] } { + && ![istarget i?86-*-beos*] } { return 0 } =20 diff --git a/binutils/unwind-ia64.c b/binutils/unwind-ia64.c deleted file mode 100644 index 086fac6cc12..00000000000 --- a/binutils/unwind-ia64.c +++ /dev/null @@ -1,1164 +0,0 @@ -/* unwind-ia64.c -- utility routines to dump IA-64 unwind info for readelf. - Copyright (C) 2000-2024 Free Software Foundation, Inc. - - Contributed by David Mosberger-Tang - - This file is part of GNU Binutils. - - This program is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3, or (at your option) - any later version. - - This program is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program; if not, write to the Free Software - Foundation, 51 Franklin Street - Fifth Floor, Boston, - MA 02110-1301, USA. */ - -#include "config.h" -#include "sysdep.h" -#include "unwind-ia64.h" - -#if __GNUC__ >=3D 2 -/* Define BFD64 here, even if our default architecture is 32 bit ELF - as this will allow us to read in and parse 64bit and 32bit ELF files. - Only do this if we believe that the compiler can support a 64 bit - data type. For now we only rely on GCC being able to do this. */ -#define BFD64 -#endif -#include "bfd.h" - -static bfd_vma unw_rlen =3D 0; - -static void unw_print_brmask (char *, unsigned int); -static void unw_print_grmask (char *, unsigned int); -static void unw_print_frmask (char *, unsigned int); -static void unw_print_abreg (char *, unsigned int); -static void unw_print_xyreg (char *, unsigned int, unsigned int); - -static void -unw_print_brmask (char *cp, unsigned int mask) -{ - int sep =3D 0; - int i; - - for (i =3D 0; mask && (i < 5); ++i) - { - if (mask & 1) - { - if (sep) - *cp++ =3D ','; - *cp++ =3D 'b'; - *cp++ =3D i + 1 + '0'; - sep =3D 1; - } - mask >>=3D 1; - } - *cp =3D '\0'; -} - -static void -unw_print_grmask (char *cp, unsigned int mask) -{ - int sep =3D 0; - int i; - - for (i =3D 0; i < 4; ++i) - { - if (mask & 1) - { - if (sep) - *cp++ =3D ','; - *cp++ =3D 'r'; - *cp++ =3D i + 4 + '0'; - sep =3D 1; - } - mask >>=3D 1; - } - *cp =3D '\0'; -} - -static void -unw_print_frmask (char *cp, unsigned int mask) -{ - int sep =3D 0; - int i; - - for (i =3D 0; i < 20; ++i) - { - if (mask & 1) - { - if (sep) - *cp++ =3D ','; - *cp++ =3D 'f'; - if (i < 4) - *cp++ =3D i + 2 + '0'; - else - { - *cp++ =3D (i + 2) / 10 + 1 + '0'; - *cp++ =3D (i + 2) % 10 + '0'; - } - sep =3D 1; - } - mask >>=3D 1; - } - *cp =3D '\0'; -} - -static void -unw_print_abreg (char *cp, unsigned int abreg) -{ - static const char * const special_reg[16] =3D - { - "pr", "psp", "@priunat", "rp", "ar.bsp", "ar.bspstore", "ar.rnat", - "ar.unat", "ar.fpsr", "ar.pfs", "ar.lc", - "Unknown11", "Unknown12", "Unknown13", "Unknown14", "Unknown15" - }; - - switch ((abreg >> 5) & 0x3) - { - case 0: /* gr */ - sprintf (cp, "r%u", (abreg & 0x1f)); - break; - - case 1: /* fr */ - sprintf (cp, "f%u", (abreg & 0x1f)); - break; - - case 2: /* br */ - sprintf (cp, "b%u", (abreg & 0x1f)); - break; - - case 3: /* special */ - strcpy (cp, special_reg[abreg & 0xf]); - break; - } -} - -static void -unw_print_xyreg (char *cp, unsigned int x, unsigned int ytreg) -{ - switch ((x << 1) | ((ytreg >> 7) & 1)) - { - case 0: /* gr */ - sprintf (cp, "r%u", (ytreg & 0x1f)); - break; - - case 1: /* fr */ - sprintf (cp, "f%u", (ytreg & 0x1f)); - break; - - case 2: /* br */ - sprintf (cp, "b%u", (ytreg & 0x1f)); - break; - - default: - strcpy (cp, "invalid"); - break; - } -} - -#define UNW_REG_BSP "bsp" -#define UNW_REG_BSPSTORE "bspstore" -#define UNW_REG_FPSR "fpsr" -#define UNW_REG_LC "lc" -#define UNW_REG_PFS "pfs" -#define UNW_REG_PR "pr" -#define UNW_REG_PSP "psp" -#define UNW_REG_RNAT "rnat" -#define UNW_REG_RP "rp" -#define UNW_REG_UNAT "unat" - -typedef bfd_vma unw_word; - -#define UNW_DEC_BAD_CODE(code) \ - printf (_("Unknown code 0x%02x\n"), code) - -#define UNW_DEC_PROLOGUE(fmt, body, rlen, arg) \ - do \ - { \ - unw_rlen =3D rlen; \ - *(int *)arg =3D body; \ - printf (" %s:%s(rlen=3D%lu)\n", \ - fmt, body ? "body" : "prologue", (unsigned long) rlen); \ - } \ - while (0) - -#define UNW_DEC_PROLOGUE_GR(fmt, rlen, mask, grsave, arg) \ - do \ - { \ - char regname[16], maskstr[64], *sep; \ - \ - unw_rlen =3D rlen; \ - *(int *)arg =3D 0; \ - \ - maskstr[0] =3D '\0'; \ - sep =3D ""; \ - if (mask & 0x8) \ - { \ - strcat (maskstr, "rp"); \ - sep =3D ","; \ - } \ - if (mask & 0x4) \ - { \ - strcat (maskstr, sep); \ - strcat (maskstr, "ar.pfs"); \ - sep =3D ","; \ - } \ - if (mask & 0x2) \ - { \ - strcat (maskstr, sep); \ - strcat (maskstr, "psp"); \ - sep =3D ","; \ - } \ - if (mask & 0x1) \ - { \ - strcat (maskstr, sep); \ - strcat (maskstr, "pr"); \ - } \ - sprintf (regname, "r%u", grsave); \ - printf (" %s:prologue_gr(mask=3D[%s],grsave=3D%s,rlen=3D%lu)\n", = \ - fmt, maskstr, regname, (unsigned long) rlen); \ - } \ - while (0) - -#define UNW_DEC_FR_MEM(fmt, frmask, arg) \ - do \ - { \ - char frstr[200]; \ - \ - unw_print_frmask (frstr, frmask); \ - printf ("\t%s:fr_mem(frmask=3D[%s])\n", fmt, frstr); \ - } \ - while (0) - -#define UNW_DEC_GR_MEM(fmt, grmask, arg) \ - do \ - { \ - char grstr[200]; \ - \ - unw_print_grmask (grstr, grmask); \ - printf ("\t%s:gr_mem(grmask=3D[%s])\n", fmt, grstr); \ - } \ - while (0) - -#define UNW_DEC_FRGR_MEM(fmt, grmask, frmask, arg) \ - do \ - { \ - char frstr[200], grstr[20]; \ - \ - unw_print_grmask (grstr, grmask); \ - unw_print_frmask (frstr, frmask); \ - printf ("\t%s:frgr_mem(grmask=3D[%s],frmask=3D[%s])\n", fmt, grstr, = frstr); \ - } \ - while (0) - -#define UNW_DEC_BR_MEM(fmt, brmask, arg) \ - do \ - { \ - char brstr[20]; \ - \ - unw_print_brmask (brstr, brmask); \ - printf ("\t%s:br_mem(brmask=3D[%s])\n", fmt, brstr); \ - } \ - while (0) - -#define UNW_DEC_BR_GR(fmt, brmask, gr, arg) \ - do \ - { \ - char brstr[20]; \ - \ - unw_print_brmask (brstr, brmask); \ - printf ("\t%s:br_gr(brmask=3D[%s],gr=3Dr%u)\n", fmt, brstr, gr); \ - } \ - while (0) - -#define UNW_DEC_REG_GR(fmt, src, dst, arg) \ - printf ("\t%s:%s_gr(reg=3Dr%u)\n", fmt, src, dst) - -#define UNW_DEC_RP_BR(fmt, dst, arg) \ - printf ("\t%s:rp_br(reg=3Db%u)\n", fmt, dst) - -#define UNW_DEC_REG_WHEN(fmt, reg, t, arg) \ - printf ("\t%s:%s_when(t=3D%lu)\n", fmt, reg, (unsigned long) t) - -#define UNW_DEC_REG_SPREL(fmt, reg, spoff, arg) \ - printf ("\t%s:%s_sprel(spoff=3D0x%lx)\n", \ - fmt, reg, 4*(unsigned long)spoff) - -#define UNW_DEC_REG_PSPREL(fmt, reg, pspoff, arg) \ - printf ("\t%s:%s_psprel(pspoff=3D0x10-0x%lx)\n", \ - fmt, reg, 4*(unsigned long)pspoff) - -#define UNW_DEC_GR_GR(fmt, grmask, gr, arg) \ - do \ - { \ - char grstr[20]; \ - \ - unw_print_grmask (grstr, grmask); \ - printf ("\t%s:gr_gr(grmask=3D[%s],r%u)\n", fmt, grstr, gr); \ - } \ - while (0) - -#define UNW_DEC_ABI(fmt, abi, context, arg) \ - do \ - { \ - static const char * const abiname[] =3D \ - { \ - "@svr4", "@hpux", "@nt" \ - }; \ - char buf[20]; \ - const char *abistr =3D buf; \ - \ - if (abi < 3) \ - abistr =3D abiname[abi]; \ - else \ - sprintf (buf, "0x%x", abi); \ - printf ("\t%s:unwabi(abi=3D%s,context=3D0x%02x)\n", \ - fmt, abistr, context); \ - } \ - while (0) - -#define UNW_DEC_PRIUNAT_GR(fmt, r, arg) \ - printf ("\t%s:priunat_gr(reg=3Dr%u)\n", fmt, r) - -#define UNW_DEC_PRIUNAT_WHEN_GR(fmt, t, arg) \ - printf ("\t%s:priunat_when_gr(t=3D%lu)\n", fmt, (unsigned long) t) - -#define UNW_DEC_PRIUNAT_WHEN_MEM(fmt, t, arg) \ - printf ("\t%s:priunat_when_mem(t=3D%lu)\n", fmt, (unsigned long) t) - -#define UNW_DEC_PRIUNAT_PSPREL(fmt, pspoff, arg) \ - printf ("\t%s:priunat_psprel(pspoff=3D0x10-0x%lx)\n", \ - fmt, 4*(unsigned long)pspoff) - -#define UNW_DEC_PRIUNAT_SPREL(fmt, spoff, arg) \ - printf ("\t%s:priunat_sprel(spoff=3D0x%lx)\n", \ - fmt, 4*(unsigned long)spoff) - -#define UNW_DEC_MEM_STACK_F(fmt, t, size, arg) \ - printf ("\t%s:mem_stack_f(t=3D%lu,size=3D%lu)\n", \ - fmt, (unsigned long) t, 16*(unsigned long)size) - -#define UNW_DEC_MEM_STACK_V(fmt, t, arg) \ - printf ("\t%s:mem_stack_v(t=3D%lu)\n", fmt, (unsigned long) t) - -#define UNW_DEC_SPILL_BASE(fmt, pspoff, arg) \ - printf ("\t%s:spill_base(pspoff=3D0x10-0x%lx)\n", \ - fmt, 4*(unsigned long)pspoff) - -#define UNW_DEC_SPILL_MASK(fmt, dp, arg, end) \ - do \ - { \ - static const char *spill_type =3D "-frb"; \ - unsigned const char *imaskp =3D dp; \ - unsigned char mask =3D 0; \ - bfd_vma insn =3D 0; \ - \ - /* PR 18420. */ \ - if ((dp + (unw_rlen / 4)) > end) \ - { \ - printf (_("\nERROR: unwind length too long (0x%lx > 0x%lx)\n\n"), \ - (long) (unw_rlen / 4), (long)(end - dp)); \ - /* FIXME: Should we reset unw_rlen ? */ \ - break; \ - } \ - printf ("\t%s:spill_mask(imask=3D[", fmt); \ - for (insn =3D 0; insn < unw_rlen; ++insn) \ - { \ - if ((insn % 4) =3D=3D 0) \ - mask =3D *imaskp++; \ - if (insn > 0 && (insn % 3) =3D=3D 0) \ - putchar (','); \ - putchar (spill_type[(mask >> (2 * (3 - (insn & 0x3)))) & 0x3]); \ - } \ - printf ("])\n"); \ - dp =3D imaskp; \ - } \ - while (0) - -#define UNW_DEC_SPILL_SPREL(fmt, t, abreg, spoff, arg) \ - do \ - { \ - char regname[20]; \ - \ - unw_print_abreg (regname, abreg); \ - printf ("\t%s:spill_sprel(reg=3D%s,t=3D%lu,spoff=3D0x%lx)\n", \ - fmt, regname, (unsigned long) t, 4*(unsigned long)off); \ - } \ - while (0) - -#define UNW_DEC_SPILL_PSPREL(fmt, t, abreg, pspoff, arg) \ - do \ - { \ - char regname[20]; \ - \ - unw_print_abreg (regname, abreg); \ - printf ("\t%s:spill_psprel(reg=3D%s,t=3D%lu,pspoff=3D0x10-0x%lx)\n",= \ - fmt, regname, (unsigned long) t, 4*(unsigned long)pspoff); \ - } \ - while (0) - -#define UNW_DEC_RESTORE(fmt, t, abreg, arg) \ - do \ - { \ - char regname[20]; \ - \ - unw_print_abreg (regname, abreg); \ - printf ("\t%s:restore(t=3D%lu,reg=3D%s)\n", \ - fmt, (unsigned long) t, regname); \ - } \ - while (0) - -#define UNW_DEC_SPILL_REG(fmt, t, abreg, x, ytreg, arg) \ - do \ - { \ - char abregname[20], tregname[20]; \ - \ - unw_print_abreg (abregname, abreg); \ - unw_print_xyreg (tregname, x, ytreg); \ - printf ("\t%s:spill_reg(t=3D%lu,reg=3D%s,treg=3D%s)\n", \ - fmt, (unsigned long) t, abregname, tregname); \ - } \ - while (0) - -#define UNW_DEC_SPILL_SPREL_P(fmt, qp, t, abreg, spoff, arg) \ - do \ - { \ - char regname[20]; \ - \ - unw_print_abreg (regname, abreg); \ - printf ("\t%s:spill_sprel_p(qp=3Dp%u,t=3D%lu,reg=3D%s,spoff=3D0x%lx)= \n", \ - fmt, qp, (unsigned long) t, regname, 4 * (unsigned long)spoff); = \ - } \ - while (0) - -#define UNW_DEC_SPILL_PSPREL_P(fmt, qp, t, abreg, pspoff, arg) \ - do \ - { \ - char regname[20]; \ - \ - unw_print_abreg (regname, abreg); \ - printf ("\t%s:spill_psprel_p(qp=3Dp%u,t=3D%lu,reg=3D%s,pspoff=3D0x10= -0x%lx)\n",\ - fmt, qp, (unsigned long) t, regname, 4*(unsigned long)pspoff);\ - } \ - while (0) - -#define UNW_DEC_RESTORE_P(fmt, qp, t, abreg, arg) \ - do \ - { \ - char regname[20]; \ - \ - unw_print_abreg (regname, abreg); \ - printf ("\t%s:restore_p(qp=3Dp%u,t=3D%lu,reg=3D%s)\n", \ - fmt, qp, (unsigned long) t, regname); \ - } \ - while (0) - -#define UNW_DEC_SPILL_REG_P(fmt, qp, t, abreg, x, ytreg, arg) \ - do \ - { \ - char regname[20], tregname[20]; \ - \ - unw_print_abreg (regname, abreg); \ - unw_print_xyreg (tregname, x, ytreg); \ - printf ("\t%s:spill_reg_p(qp=3Dp%u,t=3D%lu,reg=3D%s,treg=3D%s)\n", \ - fmt, qp, (unsigned long) t, regname, tregname); \ - } \ - while (0) - -#define UNW_DEC_LABEL_STATE(fmt, label, arg) \ - printf ("\t%s:label_state(label=3D%lu)\n", fmt, (unsigned long) label) - -#define UNW_DEC_COPY_STATE(fmt, label, arg) \ - printf ("\t%s:copy_state(label=3D%lu)\n", fmt, (unsigned long) label) - -#define UNW_DEC_EPILOGUE(fmt, t, ecount, arg) \ - printf ("\t%s:epilogue(t=3D%lu,ecount=3D%lu)\n", \ - fmt, (unsigned long) t, (unsigned long) ecount) - -/* - * Generic IA-64 unwind info decoder. - * - * This file is used both by the Linux kernel and objdump. Please - * keep the two copies of this file in sync (modulo differences in the - * prototypes...). - * - * You need to customize the decoder by defining the following - * macros/constants before including this file: - * - * Types: - * unw_word Unsigned integer type with at least 64 bits - * - * Register names: - * UNW_REG_BSP - * UNW_REG_BSPSTORE - * UNW_REG_FPSR - * UNW_REG_LC - * UNW_REG_PFS - * UNW_REG_PR - * UNW_REG_RNAT - * UNW_REG_PSP - * UNW_REG_RP - * UNW_REG_UNAT - * - * Decoder action macros: - * UNW_DEC_BAD_CODE(code) - * UNW_DEC_ABI(fmt,abi,context,arg) - * UNW_DEC_BR_GR(fmt,brmask,gr,arg) - * UNW_DEC_BR_MEM(fmt,brmask,arg) - * UNW_DEC_COPY_STATE(fmt,label,arg) - * UNW_DEC_EPILOGUE(fmt,t,ecount,arg) - * UNW_DEC_FRGR_MEM(fmt,grmask,frmask,arg) - * UNW_DEC_FR_MEM(fmt,frmask,arg) - * UNW_DEC_GR_GR(fmt,grmask,gr,arg) - * UNW_DEC_GR_MEM(fmt,grmask,arg) - * UNW_DEC_LABEL_STATE(fmt,label,arg) - * UNW_DEC_MEM_STACK_F(fmt,t,size,arg) - * UNW_DEC_MEM_STACK_V(fmt,t,arg) - * UNW_DEC_PRIUNAT_GR(fmt,r,arg) - * UNW_DEC_PRIUNAT_WHEN_GR(fmt,t,arg) - * UNW_DEC_PRIUNAT_WHEN_MEM(fmt,t,arg) - * UNW_DEC_PRIUNAT_WHEN_PSPREL(fmt,pspoff,arg) - * UNW_DEC_PRIUNAT_WHEN_SPREL(fmt,spoff,arg) - * UNW_DEC_PROLOGUE(fmt,body,rlen,arg) - * UNW_DEC_PROLOGUE_GR(fmt,rlen,mask,grsave,arg) - * UNW_DEC_REG_PSPREL(fmt,reg,pspoff,arg) - * UNW_DEC_REG_REG(fmt,src,dst,arg) - * UNW_DEC_REG_SPREL(fmt,reg,spoff,arg) - * UNW_DEC_REG_WHEN(fmt,reg,t,arg) - * UNW_DEC_RESTORE(fmt,t,abreg,arg) - * UNW_DEC_RESTORE_P(fmt,qp,t,abreg,arg) - * UNW_DEC_SPILL_BASE(fmt,pspoff,arg) - * UNW_DEC_SPILL_MASK(fmt,imaskp,arg) - * UNW_DEC_SPILL_PSPREL(fmt,t,abreg,pspoff,arg) - * UNW_DEC_SPILL_PSPREL_P(fmt,qp,t,abreg,pspoff,arg) - * UNW_DEC_SPILL_REG(fmt,t,abreg,x,ytreg,arg) - * UNW_DEC_SPILL_REG_P(fmt,qp,t,abreg,x,ytreg,arg) - * UNW_DEC_SPILL_SPREL(fmt,t,abreg,spoff,arg) - * UNW_DEC_SPILL_SPREL_P(fmt,qp,t,abreg,pspoff,arg) - */ - -static unw_word -unw_decode_uleb128 (const unsigned char **dpp, const unsigned char * end) -{ - unsigned shift =3D 0; - int status =3D 1; - unw_word byte, result =3D 0; - const unsigned char *bp =3D *dpp; - - while (bp < end) - { - byte =3D *bp++; - if (shift < sizeof (result) * 8) - { - result |=3D (byte & 0x7f) << shift; - if ((result >> shift) !=3D (byte & 0x7f)) - /* Overflow. */ - status |=3D 2; - shift +=3D 7; - } - else if ((byte & 0x7f) !=3D 0) - status |=3D 2; - - if ((byte & 0x80) =3D=3D 0) - { - status &=3D ~1; - break; - } - } - - *dpp =3D bp; - if (status !=3D 0) - printf (_("Bad uleb128\n")); - - return result; -} - -static const unsigned char * -unw_decode_x1 (const unsigned char *dp, unsigned int code ATTRIBUTE_UNUSED, - void *arg ATTRIBUTE_UNUSED, const unsigned char * end) -{ - unsigned char byte1, abreg; - unw_word t, off; - - if ((end - dp) < 3) - { - printf (_("\t\n")); - return end; - } - - byte1 =3D *dp++; - t =3D unw_decode_uleb128 (&dp, end); - off =3D unw_decode_uleb128 (&dp, end); - abreg =3D (byte1 & 0x7f); - if (byte1 & 0x80) - UNW_DEC_SPILL_SPREL ("X1", t, abreg, off, arg); - else - UNW_DEC_SPILL_PSPREL ("X1", t, abreg, off, arg); - return dp; -} - -static const unsigned char * -unw_decode_x2 (const unsigned char *dp, unsigned int code ATTRIBUTE_UNUSED, - void *arg ATTRIBUTE_UNUSED, const unsigned char * end) -{ - unsigned char byte1, byte2, abreg, x, ytreg; - unw_word t; - - if ((end - dp) < 3) - { - printf (_("\t\n")); - return end; - } - - byte1 =3D *dp++; - byte2 =3D *dp++; - t =3D unw_decode_uleb128 (&dp, end); - abreg =3D (byte1 & 0x7f); - ytreg =3D byte2; - x =3D (byte1 >> 7) & 1; - if ((byte1 & 0x80) =3D=3D 0 && ytreg =3D=3D 0) - UNW_DEC_RESTORE ("X2", t, abreg, arg); - else - UNW_DEC_SPILL_REG ("X2", t, abreg, x, ytreg, arg); - return dp; -} - -static const unsigned char * -unw_decode_x3 (const unsigned char *dp, unsigned int code ATTRIBUTE_UNUSED, - void *arg ATTRIBUTE_UNUSED, const unsigned char * end) -{ - unsigned char byte1, byte2, abreg, qp; - unw_word t, off; - - if ((end - dp) < 4) - { - printf (_("\t\n")); - return end; - } - - byte1 =3D *dp++; - byte2 =3D *dp++; - t =3D unw_decode_uleb128 (&dp, end); - off =3D unw_decode_uleb128 (&dp, end); - - qp =3D (byte1 & 0x3f); - abreg =3D (byte2 & 0x7f); - - if (byte1 & 0x80) - UNW_DEC_SPILL_SPREL_P ("X3", qp, t, abreg, off, arg); - else - UNW_DEC_SPILL_PSPREL_P ("X3", qp, t, abreg, off, arg); - return dp; -} - -static const unsigned char * -unw_decode_x4 (const unsigned char *dp, unsigned int code ATTRIBUTE_UNUSED, - void *arg ATTRIBUTE_UNUSED, const unsigned char * end) -{ - unsigned char byte1, byte2, byte3, qp, abreg, x, ytreg; - unw_word t; - - if ((end - dp) < 4) - { - printf (_("\t\n")); - return end; - } - - byte1 =3D *dp++; - byte2 =3D *dp++; - byte3 =3D *dp++; - t =3D unw_decode_uleb128 (&dp, end); - - qp =3D (byte1 & 0x3f); - abreg =3D (byte2 & 0x7f); - x =3D (byte2 >> 7) & 1; - ytreg =3D byte3; - - if ((byte2 & 0x80) =3D=3D 0 && byte3 =3D=3D 0) - UNW_DEC_RESTORE_P ("X4", qp, t, abreg, arg); - else - UNW_DEC_SPILL_REG_P ("X4", qp, t, abreg, x, ytreg, arg); - return dp; -} - -static const unsigned char * -unw_decode_r1 (const unsigned char *dp, unsigned int code, void *arg, - const unsigned char * end ATTRIBUTE_UNUSED) -{ - int body =3D (code & 0x20) !=3D 0; - unw_word rlen; - - rlen =3D (code & 0x1f); - UNW_DEC_PROLOGUE ("R1", body, rlen, arg); - return dp; -} - -static const unsigned char * -unw_decode_r2 (const unsigned char *dp, unsigned int code, void *arg, - const unsigned char * end) -{ - unsigned char byte1, mask, grsave; - unw_word rlen; - - if ((end - dp) < 2) - { - printf (_("\t\n")); - return end; - } - - byte1 =3D *dp++; - - mask =3D ((code & 0x7) << 1) | ((byte1 >> 7) & 1); - grsave =3D (byte1 & 0x7f); - rlen =3D unw_decode_uleb128 (& dp, end); - UNW_DEC_PROLOGUE_GR ("R2", rlen, mask, grsave, arg); - return dp; -} - -static const unsigned char * -unw_decode_r3 (const unsigned char *dp, unsigned int code, void *arg, - const unsigned char * end) -{ - unw_word rlen; - - rlen =3D unw_decode_uleb128 (& dp, end); - UNW_DEC_PROLOGUE ("R3", ((code & 0x3) =3D=3D 1), rlen, arg); - return dp; -} - -static const unsigned char * -unw_decode_p1 (const unsigned char *dp, unsigned int code, - void *arg ATTRIBUTE_UNUSED, - const unsigned char * end ATTRIBUTE_UNUSED) -{ - unsigned char brmask =3D (code & 0x1f); - - UNW_DEC_BR_MEM ("P1", brmask, arg); - return dp; -} - -static const unsigned char * -unw_decode_p2_p5 (const unsigned char *dp, unsigned int code, - void *arg ATTRIBUTE_UNUSED, - const unsigned char * end) -{ - if ((code & 0x10) =3D=3D 0) - { - unsigned char byte1; - - if ((end - dp) < 1) - { - printf (_("\t\n")); - return end; - } - - byte1 =3D *dp++; - - UNW_DEC_BR_GR ("P2", ((code & 0xf) << 1) | ((byte1 >> 7) & 1), - (byte1 & 0x7f), arg); - } - else if ((code & 0x08) =3D=3D 0) - { - unsigned char byte1, r, dst; - - if ((end - dp) < 1) - { - printf (_("\t\n")); - return end; - } - - byte1 =3D *dp++; - - r =3D ((code & 0x7) << 1) | ((byte1 >> 7) & 1); - dst =3D (byte1 & 0x7f); - switch (r) - { - case 0: - UNW_DEC_REG_GR ("P3", UNW_REG_PSP, dst, arg); - break; - case 1: - UNW_DEC_REG_GR ("P3", UNW_REG_RP, dst, arg); - break; - case 2: - UNW_DEC_REG_GR ("P3", UNW_REG_PFS, dst, arg); - break; - case 3: - UNW_DEC_REG_GR ("P3", UNW_REG_PR, dst, arg); - break; - case 4: - UNW_DEC_REG_GR ("P3", UNW_REG_UNAT, dst, arg); - break; - case 5: - UNW_DEC_REG_GR ("P3", UNW_REG_LC, dst, arg); - break; - case 6: - UNW_DEC_RP_BR ("P3", dst, arg); - break; - case 7: - UNW_DEC_REG_GR ("P3", UNW_REG_RNAT, dst, arg); - break; - case 8: - UNW_DEC_REG_GR ("P3", UNW_REG_BSP, dst, arg); - break; - case 9: - UNW_DEC_REG_GR ("P3", UNW_REG_BSPSTORE, dst, arg); - break; - case 10: - UNW_DEC_REG_GR ("P3", UNW_REG_FPSR, dst, arg); - break; - case 11: - UNW_DEC_PRIUNAT_GR ("P3", dst, arg); - break; - default: - UNW_DEC_BAD_CODE (r); - break; - } - } - else if ((code & 0x7) =3D=3D 0) - UNW_DEC_SPILL_MASK ("P4", dp, arg, end); - else if ((code & 0x7) =3D=3D 1) - { - unw_word grmask, frmask, byte1, byte2, byte3; - - if ((end - dp) < 3) - { - printf (_("\t\n")); - return end; - } - byte1 =3D *dp++; - byte2 =3D *dp++; - byte3 =3D *dp++; - grmask =3D ((byte1 >> 4) & 0xf); - frmask =3D ((byte1 & 0xf) << 16) | (byte2 << 8) | byte3; - UNW_DEC_FRGR_MEM ("P5", grmask, frmask, arg); - } - else - UNW_DEC_BAD_CODE (code); - - return dp; -} - -static const unsigned char * -unw_decode_p6 (const unsigned char *dp, unsigned int code, - void *arg ATTRIBUTE_UNUSED, - const unsigned char * end ATTRIBUTE_UNUSED) -{ - int gregs =3D (code & 0x10) !=3D 0; - unsigned char mask =3D (code & 0x0f); - - if (gregs) - UNW_DEC_GR_MEM ("P6", mask, arg); - else - UNW_DEC_FR_MEM ("P6", mask, arg); - return dp; -} - -static const unsigned char * -unw_decode_p7_p10 (const unsigned char *dp, unsigned int code, void *arg, - const unsigned char * end) -{ - unsigned char r, byte1, byte2; - unw_word t, size; - - if ((code & 0x10) =3D=3D 0) - { - r =3D (code & 0xf); - t =3D unw_decode_uleb128 (&dp, end); - switch (r) - { - case 0: - size =3D unw_decode_uleb128 (&dp, end); - UNW_DEC_MEM_STACK_F ("P7", t, size, arg); - break; - - case 1: - UNW_DEC_MEM_STACK_V ("P7", t, arg); - break; - case 2: - UNW_DEC_SPILL_BASE ("P7", t, arg); - break; - case 3: - UNW_DEC_REG_SPREL ("P7", UNW_REG_PSP, t, arg); - break; - case 4: - UNW_DEC_REG_WHEN ("P7", UNW_REG_RP, t, arg); - break; - case 5: - UNW_DEC_REG_PSPREL ("P7", UNW_REG_RP, t, arg); - break; - case 6: - UNW_DEC_REG_WHEN ("P7", UNW_REG_PFS, t, arg); - break; - case 7: - UNW_DEC_REG_PSPREL ("P7", UNW_REG_PFS, t, arg); - break; - case 8: - UNW_DEC_REG_WHEN ("P7", UNW_REG_PR, t, arg); - break; - case 9: - UNW_DEC_REG_PSPREL ("P7", UNW_REG_PR, t, arg); - break; - case 10: - UNW_DEC_REG_WHEN ("P7", UNW_REG_LC, t, arg); - break; - case 11: - UNW_DEC_REG_PSPREL ("P7", UNW_REG_LC, t, arg); - break; - case 12: - UNW_DEC_REG_WHEN ("P7", UNW_REG_UNAT, t, arg); - break; - case 13: - UNW_DEC_REG_PSPREL ("P7", UNW_REG_UNAT, t, arg); - break; - case 14: - UNW_DEC_REG_WHEN ("P7", UNW_REG_FPSR, t, arg); - break; - case 15: - UNW_DEC_REG_PSPREL ("P7", UNW_REG_FPSR, t, arg); - break; - default: - UNW_DEC_BAD_CODE (r); - break; - } - } - else - { - switch (code & 0xf) - { - case 0x0: /* p8 */ - { - if ((end - dp) < 2) - { - printf (_("\t\n")); - return end; - } - - r =3D *dp++; - t =3D unw_decode_uleb128 (&dp, end); - switch (r) - { - case 1: - UNW_DEC_REG_SPREL ("P8", UNW_REG_RP, t, arg); - break; - case 2: - UNW_DEC_REG_SPREL ("P8", UNW_REG_PFS, t, arg); - break; - case 3: - UNW_DEC_REG_SPREL ("P8", UNW_REG_PR, t, arg); - break; - case 4: - UNW_DEC_REG_SPREL ("P8", UNW_REG_LC, t, arg); - break; - case 5: - UNW_DEC_REG_SPREL ("P8", UNW_REG_UNAT, t, arg); - break; - case 6: - UNW_DEC_REG_SPREL ("P8", UNW_REG_FPSR, t, arg); - break; - case 7: - UNW_DEC_REG_WHEN ("P8", UNW_REG_BSP, t, arg); - break; - case 8: - UNW_DEC_REG_PSPREL ("P8", UNW_REG_BSP, t, arg); - break; - case 9: - UNW_DEC_REG_SPREL ("P8", UNW_REG_BSP, t, arg); - break; - case 10: - UNW_DEC_REG_WHEN ("P8", UNW_REG_BSPSTORE, t, arg); - break; - case 11: - UNW_DEC_REG_PSPREL ("P8", UNW_REG_BSPSTORE, t, arg); - break; - case 12: - UNW_DEC_REG_SPREL ("P8", UNW_REG_BSPSTORE, t, arg); - break; - case 13: - UNW_DEC_REG_WHEN ("P8", UNW_REG_RNAT, t, arg); - break; - case 14: - UNW_DEC_REG_PSPREL ("P8", UNW_REG_RNAT, t, arg); - break; - case 15: - UNW_DEC_REG_SPREL ("P8", UNW_REG_RNAT, t, arg); - break; - case 16: - UNW_DEC_PRIUNAT_WHEN_GR ("P8", t, arg); - break; - case 17: - UNW_DEC_PRIUNAT_PSPREL ("P8", t, arg); - break; - case 18: - UNW_DEC_PRIUNAT_SPREL ("P8", t, arg); - break; - case 19: - UNW_DEC_PRIUNAT_WHEN_MEM ("P8", t, arg); - break; - default: - UNW_DEC_BAD_CODE (r); - break; - } - } - break; - - case 0x1: - if ((end - dp) < 2) - { - printf (_("\t\n")); - return end; - } - - byte1 =3D *dp++; - byte2 =3D *dp++; - UNW_DEC_GR_GR ("P9", (byte1 & 0xf), (byte2 & 0x7f), arg); - break; - - case 0xf: /* p10 */ - if ((end - dp) < 2) - { - printf (_("\t\n")); - return end; - } - - byte1 =3D *dp++; - byte2 =3D *dp++; - UNW_DEC_ABI ("P10", byte1, byte2, arg); - break; - - case 0x9: - return unw_decode_x1 (dp, code, arg, end); - - case 0xa: - return unw_decode_x2 (dp, code, arg, end); - - case 0xb: - return unw_decode_x3 (dp, code, arg, end); - - case 0xc: - return unw_decode_x4 (dp, code, arg, end); - - default: - UNW_DEC_BAD_CODE (code); - break; - } - } - return dp; -} - -static const unsigned char * -unw_decode_b1 (const unsigned char *dp, unsigned int code, - void *arg ATTRIBUTE_UNUSED, - const unsigned char * end ATTRIBUTE_UNUSED) -{ - unw_word label =3D (code & 0x1f); - - if ((code & 0x20) !=3D 0) - UNW_DEC_COPY_STATE ("B1", label, arg); - else - UNW_DEC_LABEL_STATE ("B1", label, arg); - return dp; -} - -static const unsigned char * -unw_decode_b2 (const unsigned char *dp, unsigned int code, - void *arg ATTRIBUTE_UNUSED, - const unsigned char * end) -{ - unw_word t; - - t =3D unw_decode_uleb128 (& dp, end); - UNW_DEC_EPILOGUE ("B2", t, (code & 0x1f), arg); - return dp; -} - -static const unsigned char * -unw_decode_b3_x4 (const unsigned char *dp, unsigned int code, void *arg, - const unsigned char * end) -{ - unw_word t, ecount, label; - - if ((code & 0x10) =3D=3D 0) - { - t =3D unw_decode_uleb128 (&dp, end); - ecount =3D unw_decode_uleb128 (&dp, end); - UNW_DEC_EPILOGUE ("B3", t, ecount, arg); - } - else if ((code & 0x07) =3D=3D 0) - { - label =3D unw_decode_uleb128 (&dp, end); - if ((code & 0x08) !=3D 0) - UNW_DEC_COPY_STATE ("B4", label, arg); - else - UNW_DEC_LABEL_STATE ("B4", label, arg); - } - else - switch (code & 0x7) - { - case 1: - return unw_decode_x1 (dp, code, arg, end); - case 2: - return unw_decode_x2 (dp, code, arg, end); - case 3: - return unw_decode_x3 (dp, code, arg, end); - case 4: - return unw_decode_x4 (dp, code, arg, end); - default: - UNW_DEC_BAD_CODE (code); - break; - } - return dp; -} - -typedef const unsigned char *(*unw_decoder) - (const unsigned char *, unsigned int, void *, const unsigned char *); - -static const unw_decoder unw_decode_table[2][8] =3D - { - /* prologue table: */ - { - unw_decode_r1, /* 0 */ - unw_decode_r1, - unw_decode_r2, - unw_decode_r3, - unw_decode_p1, /* 4 */ - unw_decode_p2_p5, - unw_decode_p6, - unw_decode_p7_p10 - }, - { - unw_decode_r1, /* 0 */ - unw_decode_r1, - unw_decode_r2, - unw_decode_r3, - unw_decode_b1, /* 4 */ - unw_decode_b1, - unw_decode_b2, - unw_decode_b3_x4 - } - }; - -/* Decode one descriptor and return address of next descriptor. */ -const unsigned char * -unw_decode (const unsigned char *dp, int inside_body, - void *ptr_inside_body, const unsigned char * end) -{ - unw_decoder decoder; - unsigned char code; - - if ((end - dp) < 1) - { - printf (_("\t\n")); - return end; - } - - code =3D *dp++; - decoder =3D unw_decode_table[inside_body][code >> 5]; - return (*decoder) (dp, code, ptr_inside_body, end); -} diff --git a/binutils/unwind-ia64.h b/binutils/unwind-ia64.h deleted file mode 100644 index 61965e011bd..00000000000 --- a/binutils/unwind-ia64.h +++ /dev/null @@ -1,32 +0,0 @@ -/* unwind-ia64.h -- dump IA-64 unwind info. - Copyright (C) 2000-2024 Free Software Foundation, Inc. - Contributed by David Mosberger-Tang - - This file is part of GNU Binutils. - - This program is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3, or (at your option) - any later version. - - This program is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program; if not, write to the Free Software - Foundation, 51 Franklin Street - Fifth Floor, Boston, - MA 02110-1301, USA. */ - -#include "elf/ia64.h" -#include "ansidecl.h" - -#define UNW_VER(x) ((x) >> 48) -#define UNW_FLAG_MASK 0x0000ffff00000000LL -#define UNW_FLAG_OSMASK 0x0000f00000000000LL -#define UNW_FLAG_EHANDLER(x) ((x) & 0x0000000100000000LL) -#define UNW_FLAG_UHANDLER(x) ((x) & 0x0000000200000000LL) -#define UNW_LENGTH(x) ((x) & 0x00000000ffffffffLL) - -extern const unsigned char *unw_decode (const unsigned char *, int, void *= , const unsigned char *); diff --git a/config.guess b/config.guess index cdfc4392047..faeb058a5a3 100755 --- a/config.guess +++ b/config.guess @@ -618,14 +618,6 @@ EOF i*86:AIX:*:*) GUESS=3Di386-ibm-aix ;; - ia64:AIX:*:*) - if test -x /usr/bin/oslevel ; then - IBM_REV=3D`/usr/bin/oslevel` - else - IBM_REV=3D$UNAME_VERSION.$UNAME_RELEASE - fi - GUESS=3D$UNAME_MACHINE-ibm-aix$IBM_REV - ;; *:AIX:2:3) if grep bos325 /usr/include/stdio.h >/dev/null 2>&1; then set_cc_for_build @@ -770,10 +762,6 @@ EOF fi GUESS=3D$HP_ARCH-hp-hpux$HPUX_REV ;; - ia64:HP-UX:*:*) - HPUX_REV=3D`echo "$UNAME_RELEASE" | sed -e 's/[^.]*.[0B]*//'` - GUESS=3Dia64-hp-hpux$HPUX_REV - ;; 3050*:HI-UX:*:*) set_cc_for_build sed 's/^ //' << EOF > "$dummy.c" @@ -944,9 +932,6 @@ EOF authenticamd | genuineintel | EM64T) GUESS=3Dx86_64-unknown-interix$UNAME_RELEASE ;; - IA64) - GUESS=3Dia64-unknown-interix$UNAME_RELEASE - ;; esac ;; i*:UWIN*:*) GUESS=3D$UNAME_MACHINE-pc-uwin @@ -1060,9 +1045,6 @@ EOF i*86:Linux:*:*) GUESS=3D$UNAME_MACHINE-pc-linux-$LIBC ;; - ia64:Linux:*:*) - GUESS=3D$UNAME_MACHINE-unknown-linux-$LIBC - ;; k1om:Linux:*:*) GUESS=3D$UNAME_MACHINE-unknown-linux-$LIBC ;; @@ -1565,7 +1547,6 @@ EOF UNAME_MACHINE=3D`(uname -p) 2>/dev/null` case $UNAME_MACHINE in A*) GUESS=3Dalpha-dec-vms ;; - I*) GUESS=3Dia64-dec-vms ;; V*) GUESS=3Dvax-dec-vms ;; esac ;; *:XENIX:*:SysV) diff --git a/config.rpath b/config.rpath index 4dea75957c2..aa878254457 100755 --- a/config.rpath +++ b/config.rpath @@ -127,9 +127,7 @@ if test "$with_gnu_ld" =3D yes; then case "$host_os" in aix[3-9]*) # On AIX/PPC, the GNU linker is very broken - if test "$host_cpu" !=3D ia64; then - ld_shlibs=3Dno - fi + ld_shlibs=3Dno ;; amigaos*) hardcode_libdir_flag_spec=3D'-L$libdir' @@ -199,11 +197,6 @@ else fi ;; aix[4-9]*) - if test "$host_cpu" =3D ia64; then - # On IA64, the linker does run time linking by default, so we don't - # have to do anything special. - aix_use_runtimelinking=3Dno - else aix_use_runtimelinking=3Dno # Test if we are trying to use run time linking or normal # AIX style linking. If -brtl is somewhere in LDFLAGS, we @@ -216,7 +209,6 @@ else fi done esac - fi hardcode_direct=3Dyes hardcode_libdir_separator=3D':' if test "$GCC" =3D yes; then @@ -250,15 +242,7 @@ else fi rm -f conftest.c conftest # End _LT_AC_SYS_LIBPATH_AIX. - if test "$aix_use_runtimelinking" =3D yes; then - hardcode_libdir_flag_spec=3D'${wl}-blibpath:$libdir:'"$aix_libpath" - else - if test "$host_cpu" =3D ia64; then - hardcode_libdir_flag_spec=3D'${wl}-R $libdir:/usr/lib:/lib' - else - hardcode_libdir_flag_spec=3D'${wl}-blibpath:$libdir:'"$aix_libpa= th" - fi - fi + hardcode_libdir_flag_spec=3D'${wl}-blibpath:$libdir:'"$aix_libpath" ;; amigaos*) hardcode_libdir_flag_spec=3D'-L$libdir' @@ -312,13 +296,6 @@ else hardcode_libdir_separator=3D: hardcode_direct=3Dno ;; - ia64*) - hardcode_libdir_flag_spec=3D'-L$libdir' - hardcode_direct=3Dno - # hardcode_minus_L: Not really in the search PATH, - # but as the default location of the library. - hardcode_minus_L=3Dyes - ;; *) hardcode_libdir_flag_spec=3D'${wl}+b ${wl}$libdir' hardcode_libdir_separator=3D: @@ -451,9 +428,6 @@ case "$host_os" in ;; hpux9* | hpux10* | hpux11*) case "$host_cpu" in - ia64*) - shrext=3D.so - ;; hppa*64*) shrext=3D.sl ;; diff --git a/config.sub b/config.sub index defe52c0c87..d7a76e7a1af 100755 --- a/config.sub +++ b/config.sub @@ -1204,7 +1204,7 @@ case $cpu-$vendor in | h8300 | h8500 \ | hppa | hppa1.[01] | hppa2.0 | hppa2.0[nw] | hppa64 \ | hexagon \ - | i370 | i*86 | i860 | i960 | ia16 | ia64 \ + | i370 | i*86 | i860 | i960 \ | ip2k | iq2000 \ | k1om \ | kvx \ diff --git a/config/picflag.m4 b/config/picflag.m4 index 3f3ac744c96..7f43f4c553d 100644 --- a/config/picflag.m4 +++ b/config/picflag.m4 @@ -39,11 +39,6 @@ case "${$2}" in i[[34567]]86-pc-msdosdjgpp*) # DJGPP does not support shared libraries at all. ;; - ia64*-*-hpux*) - # On IA64 HP-UX, PIC is the default but the pic flag - # sets the default TLS model and affects inlining. - $1=3D-fPIC - ;; loongarch*-*-*) $1=3D-fpic ;; diff --git a/config/tcl.m4 b/config/tcl.m4 index 4542a4b23d7..95815bc4aea 100644 --- a/config/tcl.m4 +++ b/config/tcl.m4 @@ -1103,18 +1103,6 @@ dnl AC_CHECK_TOOL(AR, ar) fi fi =20 - if test "`uname -m`" =3D "ia64" ; then - # AIX-5 uses ELF style dynamic libraries on IA-64, but not PPC - SHLIB_LD=3D"/usr/ccs/bin/ld -G -z text" - # AIX-5 has dl* in libc.so - DL_LIBS=3D"" - if test "$GCC" =3D "yes" ; then - CC_SEARCH_FLAGS=3D'-Wl,-R,${LIB_RUNTIME_DIR}' - else - CC_SEARCH_FLAGS=3D'-R${LIB_RUNTIME_DIR}' - fi - LD_SEARCH_FLAGS=3D'-R ${LIB_RUNTIME_DIR}' - else if test "$GCC" =3D "yes" ; then SHLIB_LD=3D"gcc -shared" else @@ -1126,7 +1114,6 @@ dnl AC_CHECK_TOOL(AR, ar) LD_SEARCH_FLAGS=3D${CC_SEARCH_FLAGS} TCL_NEEDS_EXP_FILE=3D1 TCL_EXPORT_FILE_SUFFIX=3D'${VERSION}\$\{DBGX\}.exp' - fi =20 # AIX v<=3D4.1 has some different flags than 4.2+ if test "$system" =3D "AIX-4.1" -o "`uname -v`" -lt "4" ; then @@ -1204,11 +1191,7 @@ dnl AC_CHECK_TOOL(AR, ar) AC_DEFINE(_XOPEN_SOURCE_EXTENDED) # Use the XOPEN network library LIBS=3D"$LIBS -lxnet" # Use the XOPEN network library =20 - if test "`uname -m`" =3D "ia64" ; then - SHLIB_SUFFIX=3D".so" - else - SHLIB_SUFFIX=3D".sl" - fi + SHLIB_SUFFIX=3D".sl" AC_CHECK_LIB(dld, shl_load, tcl_ok=3Dyes, tcl_ok=3Dno) if test "$tcl_ok" =3D yes; then SHLIB_CFLAGS=3D"+z" diff --git a/config/unwind_ipinfo.m4 b/config/unwind_ipinfo.m4 index efc79903b77..c41d7051f01 100644 --- a/config/unwind_ipinfo.m4 +++ b/config/unwind_ipinfo.m4 @@ -11,14 +11,12 @@ AC_DEFUN([GCC_CHECK_UNWIND_GETIPINFO], [ # If system-libunwind was not specifically set, pick a default setting. if test x$with_system_libunwind =3D x; then case ${target} in - ia64-*-hpux*) with_system_libunwind=3Dyes ;; *) with_system_libunwind=3Dno ;; esac fi # Based on system-libunwind and target, do we have ipinfo? if test x$with_system_libunwind =3D xyes; then case ${target} in - ia64-*-*) have_unwind_getipinfo=3Dno ;; *) have_unwind_getipinfo=3Dyes ;; esac else diff --git a/configure b/configure index 6466b97f3ec..2b96ad2ae89 100755 --- a/configure +++ b/configure @@ -3578,9 +3578,6 @@ case "${target}" in hppa*-*-hpux*) noconfigdirs=3D"$noconfigdirs target-libffi" ;; - ia64*-*-*vms*) - noconfigdirs=3D"$noconfigdirs target-libffi" - ;; i[3456789]86-w64-mingw*) noconfigdirs=3D"$noconfigdirs target-libffi" ;; @@ -3918,18 +3915,6 @@ case "${target}" in i960-*-*) noconfigdirs=3D"$noconfigdirs gdb" ;; - ia64*-*-elf*) - # No gdb support yet. - noconfigdirs=3D"$noconfigdirs readline libgui itcl gdb" - ;; - ia64*-**-hpux*) - # No ld support yet. - noconfigdirs=3D"$noconfigdirs gdb libgui itcl ld" - ;; - ia64*-*-*vms*) - # No ld support yet. - noconfigdirs=3D"$noconfigdirs libgui itcl ld" - ;; i[3456789]86-w64-mingw*) ;; i[3456789]86-*-mingw*) diff --git a/configure.ac b/configure.ac index 1300a805fd8..5e841ca411b 100644 --- a/configure.ac +++ b/configure.ac @@ -808,9 +808,6 @@ case "${target}" in hppa*-*-hpux*) noconfigdirs=3D"$noconfigdirs target-libffi" ;; - ia64*-*-*vms*) - noconfigdirs=3D"$noconfigdirs target-libffi" - ;; i[[3456789]]86-w64-mingw*) noconfigdirs=3D"$noconfigdirs target-libffi" ;; @@ -1145,18 +1142,6 @@ case "${target}" in i960-*-*) noconfigdirs=3D"$noconfigdirs gdb" ;; - ia64*-*-elf*) - # No gdb support yet. - noconfigdirs=3D"$noconfigdirs readline libgui itcl gdb" - ;; - ia64*-**-hpux*) - # No ld support yet. - noconfigdirs=3D"$noconfigdirs gdb libgui itcl ld" - ;; - ia64*-*-*vms*) - # No ld support yet. - noconfigdirs=3D"$noconfigdirs libgui itcl ld" - ;; i[[3456789]]86-w64-mingw*) ;; i[[3456789]]86-*-mingw*) diff --git a/gas/Makefile.am b/gas/Makefile.am index 37ca0952f7e..b34caf17264 100644 --- a/gas/Makefile.am +++ b/gas/Makefile.am @@ -162,7 +162,6 @@ TARGET_CPU_CFILES =3D \ config/tc-ft32.c \ config/tc-h8300.c \ config/tc-hppa.c \ - config/tc-ia64.c \ config/tc-i386.c \ config/tc-ip2k.c \ config/tc-iq2000.c \ @@ -238,7 +237,6 @@ TARGET_CPU_HFILES =3D \ config/tc-ft32.h \ config/tc-h8300.h \ config/tc-hppa.h \ - config/tc-ia64.h \ config/tc-i386.h \ config/tc-ip2k.h \ config/tc-iq2000.h \ @@ -342,7 +340,6 @@ TARG_ENV_HFILES =3D \ config/te-hppa.h \ config/te-hppa64.h \ config/te-hppalinux64.h \ - config/te-ia64aix.h \ config/te-interix.h \ config/te-lynx.h \ config/te-macos.h \ diff --git a/gas/Makefile.in b/gas/Makefile.in index bc25765cb5b..f7b3721cfe3 100644 --- a/gas/Makefile.in +++ b/gas/Makefile.in @@ -661,7 +661,6 @@ TARGET_CPU_CFILES =3D \ config/tc-ft32.c \ config/tc-h8300.c \ config/tc-hppa.c \ - config/tc-ia64.c \ config/tc-i386.c \ config/tc-ip2k.c \ config/tc-iq2000.c \ @@ -737,7 +736,6 @@ TARGET_CPU_HFILES =3D \ config/tc-ft32.h \ config/tc-h8300.h \ config/tc-hppa.h \ - config/tc-ia64.h \ config/tc-i386.h \ config/tc-ip2k.h \ config/tc-iq2000.h \ @@ -841,7 +839,6 @@ TARG_ENV_HFILES =3D \ config/te-hppa.h \ config/te-hppa64.h \ config/te-hppalinux64.h \ - config/te-ia64aix.h \ config/te-interix.h \ config/te-lynx.h \ config/te-macos.h \ @@ -1143,8 +1140,6 @@ config/tc-h8300.$(OBJEXT): config/$(am__dirstamp) \ config/$(DEPDIR)/$(am__dirstamp) config/tc-hppa.$(OBJEXT): config/$(am__dirstamp) \ config/$(DEPDIR)/$(am__dirstamp) -config/tc-ia64.$(OBJEXT): config/$(am__dirstamp) \ - config/$(DEPDIR)/$(am__dirstamp) config/tc-i386.$(OBJEXT): config/$(am__dirstamp) \ config/$(DEPDIR)/$(am__dirstamp) config/tc-ip2k.$(OBJEXT): config/$(am__dirstamp) \ @@ -1410,7 +1405,6 @@ distclean-compile: @AMDEP_TRUE@@am__include@ @am__quote@config/$(DEPDIR)/tc-h8300.Po@am__quot= e@ @AMDEP_TRUE@@am__include@ @am__quote@config/$(DEPDIR)/tc-hppa.Po@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@config/$(DEPDIR)/tc-i386.Po@am__quote@ -@AMDEP_TRUE@@am__include@ @am__quote@config/$(DEPDIR)/tc-ia64.Po@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@config/$(DEPDIR)/tc-ip2k.Po@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@config/$(DEPDIR)/tc-iq2000.Po@am__quo= te@ @AMDEP_TRUE@@am__include@ @am__quote@config/$(DEPDIR)/tc-kvx.Po@am__quote@ diff --git a/gas/config/obj-coff-seh.c b/gas/config/obj-coff-seh.c index 4800b959751..20e40d3902f 100644 --- a/gas/config/obj-coff-seh.c +++ b/gas/config/obj-coff-seh.c @@ -214,9 +214,6 @@ seh_get_target_kind (void) /* FALL THROUGH. */ case bfd_arch_mips: return seh_kind_mips; - case bfd_arch_ia64: - /* Should return seh_kind_x64. But not implemented yet. */ - return seh_kind_unknown; default: break; } diff --git a/gas/config/tc-ia64.c b/gas/config/tc-ia64.c deleted file mode 100644 index a1b1e61408b..00000000000 --- a/gas/config/tc-ia64.c +++ /dev/null @@ -1,11982 +0,0 @@ -/* tc-ia64.c -- Assembler for the HP/Intel IA-64 architecture. - Copyright (C) 1998-2024 Free Software Foundation, Inc. - Contributed by David Mosberger-Tang - - This file is part of GAS, the GNU Assembler. - - GAS is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3, or (at your option) - any later version. - - GAS is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with GAS; see the file COPYING. If not, write to - the Free Software Foundation, 51 Franklin Street - Fifth Floor, - Boston, MA 02110-1301, USA. */ - -/* - TODO: - - - optional operands - - directives: - .eb - .estate - .lb - .popsection - .previous - .psr - .pushsection - - labels are wrong if automatic alignment is introduced - (e.g., checkout the second real10 definition in test-data.s) - - DV-related stuff: - .safe_across_calls and any other DV-related directives I don't - have documentation for. - verify mod-sched-brs reads/writes are checked/marked (and other - notes) - - */ - -#include "as.h" -#include "safe-ctype.h" -#include "dwarf2dbg.h" -#include "subsegs.h" - -#include "opcode/ia64.h" - -#include "elf/ia64.h" -#include "bfdver.h" -#include -#include - -#define NELEMS(a) ((int) (sizeof (a)/sizeof ((a)[0]))) - -/* Some systems define MIN in, e.g., param.h. */ -#undef MIN -#define MIN(a,b) ((a) < (b) ? (a) : (b)) - -#define NUM_SLOTS 4 -#define PREV_SLOT md.slot[(md.curr_slot + NUM_SLOTS - 1) % NUM_SLOTS] -#define CURR_SLOT md.slot[md.curr_slot] - -#define O_pseudo_fixup (O_max + 1) - -enum special_section - { - /* IA-64 ABI section pseudo-ops. */ - SPECIAL_SECTION_SBSS =3D 0, - SPECIAL_SECTION_SDATA, - SPECIAL_SECTION_RODATA, - SPECIAL_SECTION_COMMENT, - SPECIAL_SECTION_UNWIND, - SPECIAL_SECTION_UNWIND_INFO, - /* HPUX specific section pseudo-ops. */ - SPECIAL_SECTION_INIT_ARRAY, - SPECIAL_SECTION_FINI_ARRAY, - }; - -enum reloc_func - { - FUNC_DTP_MODULE, - FUNC_DTP_RELATIVE, - FUNC_FPTR_RELATIVE, - FUNC_GP_RELATIVE, - FUNC_LT_RELATIVE, - FUNC_LT_RELATIVE_X, - FUNC_PC_RELATIVE, - FUNC_PLT_RELATIVE, - FUNC_SEC_RELATIVE, - FUNC_SEG_RELATIVE, - FUNC_TP_RELATIVE, - FUNC_LTV_RELATIVE, - FUNC_LT_FPTR_RELATIVE, - FUNC_LT_DTP_MODULE, - FUNC_LT_DTP_RELATIVE, - FUNC_LT_TP_RELATIVE, - FUNC_IPLT_RELOC, -#ifdef TE_VMS - FUNC_SLOTCOUNT_RELOC, -#endif - }; - -enum reg_symbol - { - REG_GR =3D 0, - REG_FR =3D (REG_GR + 128), - REG_AR =3D (REG_FR + 128), - REG_CR =3D (REG_AR + 128), - REG_DAHR =3D (REG_CR + 128), - REG_P =3D (REG_DAHR + 8), - REG_BR =3D (REG_P + 64), - REG_IP =3D (REG_BR + 8), - REG_CFM, - REG_PR, - REG_PR_ROT, - REG_PSR, - REG_PSR_L, - REG_PSR_UM, - /* The following are pseudo-registers for use by gas only. */ - IND_CPUID, - IND_DBR, - IND_DTR, - IND_ITR, - IND_IBR, - IND_MSR, - IND_PKR, - IND_PMC, - IND_PMD, - IND_DAHR, - IND_RR, - /* The following pseudo-registers are used for unwind directives only:= */ - REG_PSP, - REG_PRIUNAT, - REG_NUM - }; - -enum dynreg_type - { - DYNREG_GR =3D 0, /* dynamic general purpose register */ - DYNREG_FR, /* dynamic floating point register */ - DYNREG_PR, /* dynamic predicate register */ - DYNREG_NUM_TYPES - }; - -enum operand_match_result - { - OPERAND_MATCH, - OPERAND_OUT_OF_RANGE, - OPERAND_MISMATCH - }; - -/* On the ia64, we can't know the address of a text label until the - instructions are packed into a bundle. To handle this, we keep - track of the list of labels that appear in front of each - instruction. */ -struct label_fix -{ - struct label_fix *next; - struct symbol *sym; - bool dw2_mark_labels; -}; - -#ifdef TE_VMS -/* An internally used relocation. */ -#define DUMMY_RELOC_IA64_SLOTCOUNT (BFD_RELOC_UNUSED + 1) -#endif - -/* This is the endianness of the current section. */ -extern int target_big_endian; - -/* This is the default endianness. */ -static int default_big_endian =3D TARGET_BYTES_BIG_ENDIAN; - -void (*ia64_number_to_chars) (char *, valueT, int); - -static void ia64_float_to_chars_bigendian (char *, LITTLENUM_TYPE *, int); -static void ia64_float_to_chars_littleendian (char *, LITTLENUM_TYPE *, in= t); - -static void (*ia64_float_to_chars) (char *, LITTLENUM_TYPE *, int); - -static htab_t alias_hash; -static htab_t alias_name_hash; -static htab_t secalias_hash; -static htab_t secalias_name_hash; - -/* List of chars besides those in app.c:symbol_chars that can start an - operand. Used to prevent the scrubber eating vital white-space. */ -const char ia64_symbol_chars[] =3D "@?"; - -/* Characters which always start a comment. */ -const char comment_chars[] =3D ""; - -/* Characters which start a comment at the beginning of a line. */ -const char line_comment_chars[] =3D "#"; - -/* Characters which may be used to separate multiple commands on a - single line. */ -const char line_separator_chars[] =3D ";{}"; - -/* Characters which are used to indicate an exponent in a floating - point number. */ -const char EXP_CHARS[] =3D "eE"; - -/* Characters which mean that a number is a floating point constant, - as in 0d1.0. */ -const char FLT_CHARS[] =3D "rRsSfFdDxXpP"; - -/* ia64-specific option processing: */ - -const char *md_shortopts =3D "m:N:x::"; - -struct option md_longopts[] =3D - { -#define OPTION_MCONSTANT_GP (OPTION_MD_BASE + 1) - {"mconstant-gp", no_argument, NULL, OPTION_MCONSTANT_GP}, -#define OPTION_MAUTO_PIC (OPTION_MD_BASE + 2) - {"mauto-pic", no_argument, NULL, OPTION_MAUTO_PIC} - }; - -size_t md_longopts_size =3D sizeof (md_longopts); - -static struct - { - htab_t pseudo_hash; /* pseudo opcode hash table */ - htab_t reg_hash; /* register name hash table */ - htab_t dynreg_hash; /* dynamic register hash table */ - htab_t const_hash; /* constant hash table */ - htab_t entry_hash; /* code entry hint hash table */ - - /* If X_op is !=3D O_absent, the register name for the instruction's - qualifying predicate. If NULL, p0 is assumed for instructions - that are predictable. */ - expressionS qp; - - /* Optimize for which CPU. */ - enum - { - itanium1, - itanium2 - } tune; - - /* What to do when hint.b is used. */ - enum - { - hint_b_error, - hint_b_warning, - hint_b_ok - } hint_b; - - unsigned int - manual_bundling : 1, - debug_dv: 1, - detect_dv: 1, - explicit_mode : 1, /* which mode we're in */ - default_explicit_mode : 1, /* which mode is the default */ - mode_explicitly_set : 1, /* was the current mode explicitly set= ? */ - auto_align : 1, - keep_pending_output : 1; - - /* What to do when something is wrong with unwind directives. */ - enum - { - unwind_check_warning, - unwind_check_error - } unwind_check; - - /* Each bundle consists of up to three instructions. We keep - track of four most recent instructions so we can correctly set - the end_of_insn_group for the last instruction in a bundle. */ - int curr_slot; - int num_slots_in_use; - struct slot - { - unsigned int - end_of_insn_group : 1, - manual_bundling_on : 1, - manual_bundling_off : 1, - loc_directive_seen : 1; - signed char user_template; /* user-selected template, if any */ - unsigned char qp_regno; /* qualifying predicate */ - /* This duplicates a good fraction of "struct fix" but we - can't use a "struct fix" instead since we can't call - fix_new_exp() until we know the address of the instruction. */ - int num_fixups; - struct insn_fix - { - bfd_reloc_code_real_type code; - enum ia64_opnd opnd; /* type of operand in need of fix */ - unsigned int is_pcrel : 1; /* is operand pc-relative? */ - expressionS expr; /* the value to be inserted */ - } - fixup[2]; /* at most two fixups per insn */ - struct ia64_opcode *idesc; - struct label_fix *label_fixups; - struct label_fix *tag_fixups; - struct unw_rec_list *unwind_record; /* Unwind directive. */ - expressionS opnd[6]; - const char *src_file; - unsigned int src_line; - struct dwarf2_line_info debug_line; - } - slot[NUM_SLOTS]; - - segT last_text_seg; - subsegT last_text_subseg; - - struct dynreg - { - struct dynreg *next; /* next dynamic register */ - const char *name; - unsigned short base; /* the base register number */ - unsigned short num_regs; /* # of registers in this set */ - } - *dynreg[DYNREG_NUM_TYPES], in, loc, out, rot; - - flagword flags; /* ELF-header flags */ - - struct mem_offset { - unsigned hint:1; /* is this hint currently valid? */ - bfd_vma offset; /* mem.offset offset */ - bfd_vma base; /* mem.offset base */ - } mem_offset; - - int path; /* number of alt. entry points seen */ - const char **entry_labels; /* labels of all alternate paths in - the current DV-checking block. */ - int maxpaths; /* size currently allocated for - entry_labels */ - - int pointer_size; /* size in bytes of a pointer */ - int pointer_size_shift; /* shift size of a pointer for alignment */ - - symbolS *indregsym[IND_RR - IND_CPUID + 1]; - } -md; - -/* These are not const, because they are modified to MMI for non-itanium1 - targets below. */ -/* MFI bundle of nops. */ -static unsigned char le_nop[16] =3D -{ - 0x0c, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, - 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x04, 0x00 -}; -/* MFI bundle of nops with stop-bit. */ -static unsigned char le_nop_stop[16] =3D -{ - 0x0d, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, - 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x04, 0x00 -}; - -/* application registers: */ - -#define AR_K0 0 -#define AR_K7 7 -#define AR_RSC 16 -#define AR_BSP 17 -#define AR_BSPSTORE 18 -#define AR_RNAT 19 -#define AR_FCR 21 -#define AR_EFLAG 24 -#define AR_CSD 25 -#define AR_SSD 26 -#define AR_CFLG 27 -#define AR_FSR 28 -#define AR_FIR 29 -#define AR_FDR 30 -#define AR_CCV 32 -#define AR_UNAT 36 -#define AR_FPSR 40 -#define AR_ITC 44 -#define AR_RUC 45 -#define AR_PFS 64 -#define AR_LC 65 -#define AR_EC 66 - -static const struct - { - const char *name; - unsigned int regnum; - } -ar[] =3D - { - {"ar.k0", AR_K0}, {"ar.k1", AR_K0 + 1}, - {"ar.k2", AR_K0 + 2}, {"ar.k3", AR_K0 + 3}, - {"ar.k4", AR_K0 + 4}, {"ar.k5", AR_K0 + 5}, - {"ar.k6", AR_K0 + 6}, {"ar.k7", AR_K7}, - {"ar.rsc", AR_RSC}, {"ar.bsp", AR_BSP}, - {"ar.bspstore", AR_BSPSTORE}, {"ar.rnat", AR_RNAT}, - {"ar.fcr", AR_FCR}, {"ar.eflag", AR_EFLAG}, - {"ar.csd", AR_CSD}, {"ar.ssd", AR_SSD}, - {"ar.cflg", AR_CFLG}, {"ar.fsr", AR_FSR}, - {"ar.fir", AR_FIR}, {"ar.fdr", AR_FDR}, - {"ar.ccv", AR_CCV}, {"ar.unat", AR_UNAT}, - {"ar.fpsr", AR_FPSR}, {"ar.itc", AR_ITC}, - {"ar.ruc", AR_RUC}, {"ar.pfs", AR_PFS}, - {"ar.lc", AR_LC}, {"ar.ec", AR_EC}, - }; - -/* control registers: */ - -#define CR_DCR 0 -#define CR_ITM 1 -#define CR_IVA 2 -#define CR_PTA 8 -#define CR_GPTA 9 -#define CR_IPSR 16 -#define CR_ISR 17 -#define CR_IIP 19 -#define CR_IFA 20 -#define CR_ITIR 21 -#define CR_IIPA 22 -#define CR_IFS 23 -#define CR_IIM 24 -#define CR_IHA 25 -#define CR_IIB0 26 -#define CR_IIB1 27 -#define CR_LID 64 -#define CR_IVR 65 -#define CR_TPR 66 -#define CR_EOI 67 -#define CR_IRR0 68 -#define CR_IRR3 71 -#define CR_ITV 72 -#define CR_PMV 73 -#define CR_CMCV 74 -#define CR_LRR0 80 -#define CR_LRR1 81 - -static const struct - { - const char *name; - unsigned int regnum; - } -cr[] =3D - { - {"cr.dcr", CR_DCR}, - {"cr.itm", CR_ITM}, - {"cr.iva", CR_IVA}, - {"cr.pta", CR_PTA}, - {"cr.gpta", CR_GPTA}, - {"cr.ipsr", CR_IPSR}, - {"cr.isr", CR_ISR}, - {"cr.iip", CR_IIP}, - {"cr.ifa", CR_IFA}, - {"cr.itir", CR_ITIR}, - {"cr.iipa", CR_IIPA}, - {"cr.ifs", CR_IFS}, - {"cr.iim", CR_IIM}, - {"cr.iha", CR_IHA}, - {"cr.iib0", CR_IIB0}, - {"cr.iib1", CR_IIB1}, - {"cr.lid", CR_LID}, - {"cr.ivr", CR_IVR}, - {"cr.tpr", CR_TPR}, - {"cr.eoi", CR_EOI}, - {"cr.irr0", CR_IRR0}, - {"cr.irr1", CR_IRR0 + 1}, - {"cr.irr2", CR_IRR0 + 2}, - {"cr.irr3", CR_IRR3}, - {"cr.itv", CR_ITV}, - {"cr.pmv", CR_PMV}, - {"cr.cmcv", CR_CMCV}, - {"cr.lrr0", CR_LRR0}, - {"cr.lrr1", CR_LRR1} - }; - -#define PSR_MFL 4 -#define PSR_IC 13 -#define PSR_DFL 18 -#define PSR_CPL 32 - -static const struct const_desc - { - const char *name; - valueT value; - } -const_bits[] =3D - { - /* PSR constant masks: */ - - /* 0: reserved */ - {"psr.be", ((valueT) 1) << 1}, - {"psr.up", ((valueT) 1) << 2}, - {"psr.ac", ((valueT) 1) << 3}, - {"psr.mfl", ((valueT) 1) << 4}, - {"psr.mfh", ((valueT) 1) << 5}, - /* 6-12: reserved */ - {"psr.ic", ((valueT) 1) << 13}, - {"psr.i", ((valueT) 1) << 14}, - {"psr.pk", ((valueT) 1) << 15}, - /* 16: reserved */ - {"psr.dt", ((valueT) 1) << 17}, - {"psr.dfl", ((valueT) 1) << 18}, - {"psr.dfh", ((valueT) 1) << 19}, - {"psr.sp", ((valueT) 1) << 20}, - {"psr.pp", ((valueT) 1) << 21}, - {"psr.di", ((valueT) 1) << 22}, - {"psr.si", ((valueT) 1) << 23}, - {"psr.db", ((valueT) 1) << 24}, - {"psr.lp", ((valueT) 1) << 25}, - {"psr.tb", ((valueT) 1) << 26}, - {"psr.rt", ((valueT) 1) << 27}, - /* 28-31: reserved */ - /* 32-33: cpl (current privilege level) */ - {"psr.is", ((valueT) 1) << 34}, - {"psr.mc", ((valueT) 1) << 35}, - {"psr.it", ((valueT) 1) << 36}, - {"psr.id", ((valueT) 1) << 37}, - {"psr.da", ((valueT) 1) << 38}, - {"psr.dd", ((valueT) 1) << 39}, - {"psr.ss", ((valueT) 1) << 40}, - /* 41-42: ri (restart instruction) */ - {"psr.ed", ((valueT) 1) << 43}, - {"psr.bn", ((valueT) 1) << 44}, - }; - -/* indirect register-sets/memory: */ - -static const struct - { - const char *name; - unsigned int regnum; - } -indirect_reg[] =3D - { - { "CPUID", IND_CPUID }, - { "cpuid", IND_CPUID }, - { "dbr", IND_DBR }, - { "dtr", IND_DTR }, - { "itr", IND_ITR }, - { "ibr", IND_IBR }, - { "msr", IND_MSR }, - { "pkr", IND_PKR }, - { "pmc", IND_PMC }, - { "pmd", IND_PMD }, - { "dahr", IND_DAHR }, - { "rr", IND_RR }, - }; - -/* Pseudo functions used to indicate relocation types (these functions - start with an at sign (@). */ -static struct - { - const char *name; - enum pseudo_type - { - PSEUDO_FUNC_NONE, - PSEUDO_FUNC_RELOC, - PSEUDO_FUNC_CONST, - PSEUDO_FUNC_REG, - PSEUDO_FUNC_FLOAT - } - type; - union - { - unsigned long ival; - symbolS *sym; - } - u; - } -pseudo_func[] =3D - { - /* reloc pseudo functions (these must come first!): */ - { "dtpmod", PSEUDO_FUNC_RELOC, { 0 } }, - { "dtprel", PSEUDO_FUNC_RELOC, { 0 } }, - { "fptr", PSEUDO_FUNC_RELOC, { 0 } }, - { "gprel", PSEUDO_FUNC_RELOC, { 0 } }, - { "ltoff", PSEUDO_FUNC_RELOC, { 0 } }, - { "ltoffx", PSEUDO_FUNC_RELOC, { 0 } }, - { "pcrel", PSEUDO_FUNC_RELOC, { 0 } }, - { "pltoff", PSEUDO_FUNC_RELOC, { 0 } }, - { "secrel", PSEUDO_FUNC_RELOC, { 0 } }, - { "segrel", PSEUDO_FUNC_RELOC, { 0 } }, - { "tprel", PSEUDO_FUNC_RELOC, { 0 } }, - { "ltv", PSEUDO_FUNC_RELOC, { 0 } }, - { NULL, 0, { 0 } }, /* placeholder for FUNC_LT_FPTR_RELATIVE */ - { NULL, 0, { 0 } }, /* placeholder for FUNC_LT_DTP_MODULE */ - { NULL, 0, { 0 } }, /* placeholder for FUNC_LT_DTP_RELATIVE */ - { NULL, 0, { 0 } }, /* placeholder for FUNC_LT_TP_RELATIVE */ - { "iplt", PSEUDO_FUNC_RELOC, { 0 } }, -#ifdef TE_VMS - { "slotcount", PSEUDO_FUNC_RELOC, { 0 } }, -#endif - - /* mbtype4 constants: */ - { "alt", PSEUDO_FUNC_CONST, { 0xa } }, - { "brcst", PSEUDO_FUNC_CONST, { 0x0 } }, - { "mix", PSEUDO_FUNC_CONST, { 0x8 } }, - { "rev", PSEUDO_FUNC_CONST, { 0xb } }, - { "shuf", PSEUDO_FUNC_CONST, { 0x9 } }, - - /* fclass constants: */ - { "nat", PSEUDO_FUNC_CONST, { 0x100 } }, - { "qnan", PSEUDO_FUNC_CONST, { 0x080 } }, - { "snan", PSEUDO_FUNC_CONST, { 0x040 } }, - { "pos", PSEUDO_FUNC_CONST, { 0x001 } }, - { "neg", PSEUDO_FUNC_CONST, { 0x002 } }, - { "zero", PSEUDO_FUNC_CONST, { 0x004 } }, - { "unorm", PSEUDO_FUNC_CONST, { 0x008 } }, - { "norm", PSEUDO_FUNC_CONST, { 0x010 } }, - { "inf", PSEUDO_FUNC_CONST, { 0x020 } }, - - { "natval", PSEUDO_FUNC_CONST, { 0x100 } }, /* old usage */ - - /* hint constants: */ - { "pause", PSEUDO_FUNC_CONST, { 0x0 } }, - { "priority", PSEUDO_FUNC_CONST, { 0x1 } }, - - /* tf constants: */ - { "clz", PSEUDO_FUNC_CONST, { 32 } }, - { "mpy", PSEUDO_FUNC_CONST, { 33 } }, - { "datahints", PSEUDO_FUNC_CONST, { 34 } }, - - /* unwind-related constants: */ - { "svr4", PSEUDO_FUNC_CONST, { ELFOSABI_NONE } }, - { "hpux", PSEUDO_FUNC_CONST, { ELFOSABI_HPUX } }, - { "nt", PSEUDO_FUNC_CONST, { 2 } }, /* conflicts w/ELFOSABI_NETBSD */ - { "linux", PSEUDO_FUNC_CONST, { ELFOSABI_GNU } }, - { "freebsd", PSEUDO_FUNC_CONST, { ELFOSABI_FREEBSD } }, - { "openvms", PSEUDO_FUNC_CONST, { ELFOSABI_OPENVMS } }, - { "nsk", PSEUDO_FUNC_CONST, { ELFOSABI_NSK } }, - - /* unwind-related registers: */ - { "priunat",PSEUDO_FUNC_REG, { REG_PRIUNAT } } - }; - -/* 41-bit nop opcodes (one per unit): */ -static const bfd_vma nop[IA64_NUM_UNITS] =3D - { - 0x0000000000LL, /* NIL =3D> break 0 */ - 0x0008000000LL, /* I-unit nop */ - 0x0008000000LL, /* M-unit nop */ - 0x4000000000LL, /* B-unit nop */ - 0x0008000000LL, /* F-unit nop */ - 0x0000000000LL, /* L-"unit" nop immediate */ - 0x0008000000LL, /* X-unit nop */ - }; - -/* Can't be `const' as it's passed to input routines (which have the - habit of setting temporary sentinels. */ -static char special_section_name[][20] =3D - { - {".sbss"}, {".sdata"}, {".rodata"}, {".comment"}, - {".IA_64.unwind"}, {".IA_64.unwind_info"}, - {".init_array"}, {".fini_array"} - }; - -/* The best template for a particular sequence of up to three - instructions: */ -#define N IA64_NUM_TYPES -static unsigned char best_template[N][N][N]; -#undef N - -/* Resource dependencies currently in effect */ -static struct rsrc { - int depind; /* dependency index */ - const struct ia64_dependency *dependency; /* actual dependency */ - unsigned specific:1, /* is this a specific bit/regno? */ - link_to_qp_branch:1; /* will a branch on the same QP clear i= t?*/ - int index; /* specific regno/bit within dependenc= y */ - int note; /* optional qualifying note (0 if none= ) */ -#define STATE_NONE 0 -#define STATE_STOP 1 -#define STATE_SRLZ 2 - int insn_srlz; /* current insn serialization state */ - int data_srlz; /* current data serialization state */ - int qp_regno; /* qualifying predicate for this usage= */ - const char *file; /* what file marked this depende= ncy */ - unsigned int line; /* what line marked this dependency */ - struct mem_offset mem_offset; /* optional memory offset hint */ - enum { CMP_NONE, CMP_OR, CMP_AND } cmp_type; /* OR or AND compare? */ - int path; /* corresponding code entry index */ -} *regdeps =3D NULL; -static int regdepslen =3D 0; -static int regdepstotlen =3D 0; -static const char *dv_mode[] =3D { "RAW", "WAW", "WAR" }; -static const char *dv_sem[] =3D { "none", "implied", "impliedf", - "data", "instr", "specific", "stop", "other" }; -static const char *dv_cmp_type[] =3D { "none", "OR", "AND" }; - -/* Current state of PR mutexation */ -static struct qpmutex { - valueT prmask; - int path; -} *qp_mutexes =3D NULL; /* QP mutex bitmasks */ -static int qp_mutexeslen =3D 0; -static int qp_mutexestotlen =3D 0; -static valueT qp_safe_across_calls =3D 0; - -/* Current state of PR implications */ -static struct qp_imply { - unsigned p1:6; - unsigned p2:6; - unsigned p2_branched:1; - int path; -} *qp_implies =3D NULL; -static int qp_implieslen =3D 0; -static int qp_impliestotlen =3D 0; - -/* Keep track of static GR values so that indirect register usage can - sometimes be tracked. */ -static struct gr { - unsigned known:1; - int path; - valueT value; -} gr_values[128] =3D { - { - 1, -#ifdef INT_MAX - INT_MAX, -#else - (((1 << (8 * sizeof(gr_values->path) - 2)) - 1) << 1) + 1, -#endif - 0 - } -}; - -/* Remember the alignment frag. */ -static fragS *align_frag; - -/* These are the routines required to output the various types of - unwind records. */ - -/* A slot_number is a frag address plus the slot index (0-2). We use the - frag address here so that if there is a section switch in the middle of - a function, then instructions emitted to a different section are not - counted. Since there may be more than one frag for a function, this - means we also need to keep track of which frag this address belongs to - so we can compute inter-frag distances. This also nicely solves the - problem with nops emitted for align directives, which can't easily be - counted, but can easily be derived from frag sizes. */ - -typedef struct unw_rec_list { - unwind_record r; - unsigned long slot_number; - fragS *slot_frag; - struct unw_rec_list *next; -} unw_rec_list; - -#define SLOT_NUM_NOT_SET (unsigned)-1 - -/* Linked list of saved prologue counts. A very poor - implementation of a map from label numbers to prologue counts. */ -typedef struct label_prologue_count -{ - struct label_prologue_count *next; - unsigned long label_number; - unsigned int prologue_count; -} label_prologue_count; - -typedef struct proc_pending -{ - symbolS *sym; - struct proc_pending *next; -} proc_pending; - -static struct -{ - /* Maintain a list of unwind entries for the current function. */ - unw_rec_list *list; - unw_rec_list *tail; - - /* Any unwind entries that should be attached to the current slot - that an insn is being constructed for. */ - unw_rec_list *current_entry; - - /* These are used to create the unwind table entry for this function. */ - proc_pending proc_pending; - symbolS *info; /* pointer to unwind info */ - symbolS *personality_routine; - segT saved_text_seg; - subsegT saved_text_subseg; - unsigned int force_unwind_entry : 1; /* force generation of unwind entry= ? */ - - /* TRUE if processing unwind directives in a prologue region. */ - unsigned int prologue : 1; - unsigned int prologue_mask : 4; - unsigned int prologue_gr : 7; - unsigned int body : 1; - unsigned int insn : 1; - unsigned int prologue_count; /* number of .prologues seen so far */ - /* Prologue counts at previous .label_state directives. */ - struct label_prologue_count * saved_prologue_counts; - - /* List of split up .save-s. */ - unw_p_record *pending_saves; -} unwind; - -/* The input value is a negated offset from psp, and specifies an address - psp - offset. The encoded value is psp + 16 - (4 * offset). Thus we - must add 16 and divide by 4 to get the encoded value. */ - -#define ENCODED_PSP_OFFSET(OFFSET) (((OFFSET) + 16) / 4) - -typedef void (*vbyte_func) (int, char *, char *); - -/* Forward declarations: */ -static void dot_alias (int); -static int parse_operand_and_eval (expressionS *, int); -static void emit_one_bundle (void); -static bfd_reloc_code_real_type ia64_gen_real_reloc_type (struct symbol *, - bfd_reloc_code_real_type); -static void insn_group_break (int, int, int); -static void add_qp_mutex (valueT); -static void add_qp_imply (int, int); -static void clear_qp_mutex (valueT); -static void clear_qp_implies (valueT, valueT); -static void print_dependency (const char *, int); -static void instruction_serialization (void); -static void data_serialization (void); -static void output_R3_format (vbyte_func, unw_record_type, unsigned long); -static void output_B3_format (vbyte_func, unsigned long, unsigned long); -static void output_B4_format (vbyte_func, unw_record_type, unsigned long); -static void free_saved_prologue_counts (void); - -/* Determine if application register REGNUM resides only in the integer - unit (as opposed to the memory unit). */ -static int -ar_is_only_in_integer_unit (int reg) -{ - reg -=3D REG_AR; - return reg >=3D 64 && reg <=3D 111; -} - -/* Determine if application register REGNUM resides only in the memory - unit (as opposed to the integer unit). */ -static int -ar_is_only_in_memory_unit (int reg) -{ - reg -=3D REG_AR; - return reg >=3D 0 && reg <=3D 47; -} - -/* Switch to section NAME and create section if necessary. It's - rather ugly that we have to manipulate input_line_pointer but I - don't see any other way to accomplish the same thing without - changing obj-elf.c (which may be the Right Thing, in the end). */ -static void -set_section (char *name) -{ - char *saved_input_line_pointer; - - saved_input_line_pointer =3D input_line_pointer; - input_line_pointer =3D name; - obj_elf_section (0); - input_line_pointer =3D saved_input_line_pointer; -} - -/* Map 's' to SHF_IA_64_SHORT. */ - -bfd_vma -ia64_elf_section_letter (int letter, const char **ptr_msg) -{ - if (letter =3D=3D 's') - return SHF_IA_64_SHORT; - else if (letter =3D=3D 'o') - return SHF_LINK_ORDER; -#ifdef TE_VMS - else if (letter =3D=3D 'O') - return SHF_IA_64_VMS_OVERLAID; - else if (letter =3D=3D 'g') - return SHF_IA_64_VMS_GLOBAL; -#endif - - *ptr_msg =3D _("bad .section directive: want a,o,s,w,x,M,S,G,T in string= "); - return -1; -} - -/* Map SHF_IA_64_SHORT to SEC_SMALL_DATA. */ - -flagword -ia64_elf_section_flags (flagword flags, - bfd_vma attr, - int type ATTRIBUTE_UNUSED) -{ - if (attr & SHF_IA_64_SHORT) - flags |=3D SEC_SMALL_DATA; - return flags; -} - -int -ia64_elf_section_type (const char *str, size_t len) -{ -#define STREQ(s) ((len =3D=3D sizeof (s) - 1) && (strncmp (str, s, sizeof = (s) - 1) =3D=3D 0)) - - if (STREQ (ELF_STRING_ia64_unwind_info)) - return SHT_PROGBITS; - - if (STREQ (ELF_STRING_ia64_unwind_info_once)) - return SHT_PROGBITS; - - if (STREQ (ELF_STRING_ia64_unwind)) - return SHT_IA_64_UNWIND; - - if (STREQ (ELF_STRING_ia64_unwind_once)) - return SHT_IA_64_UNWIND; - - if (STREQ ("unwind")) - return SHT_IA_64_UNWIND; - - return -1; -#undef STREQ -} - -static unsigned int -set_regstack (unsigned int ins, - unsigned int locs, - unsigned int outs, - unsigned int rots) -{ - /* Size of frame. */ - unsigned int sof; - - sof =3D ins + locs + outs; - if (sof > 96) - { - as_bad (_("Size of frame exceeds maximum of 96 registers")); - return 0; - } - if (rots > sof) - { - as_warn (_("Size of rotating registers exceeds frame size")); - return 0; - } - md.in.base =3D REG_GR + 32; - md.loc.base =3D md.in.base + ins; - md.out.base =3D md.loc.base + locs; - - md.in.num_regs =3D ins; - md.loc.num_regs =3D locs; - md.out.num_regs =3D outs; - md.rot.num_regs =3D rots; - return sof; -} - -void -ia64_flush_insns (void) -{ - struct label_fix *lfix; - segT saved_seg; - subsegT saved_subseg; - unw_rec_list *ptr; - bool mark; - - if (!md.last_text_seg) - return; - - saved_seg =3D now_seg; - saved_subseg =3D now_subseg; - - subseg_set (md.last_text_seg, md.last_text_subseg); - - while (md.num_slots_in_use > 0) - emit_one_bundle (); /* force out queued instructions */ - - /* In case there are labels following the last instruction, resolve - those now. */ - mark =3D false; - for (lfix =3D CURR_SLOT.label_fixups; lfix; lfix =3D lfix->next) - { - symbol_set_value_now (lfix->sym); - mark |=3D lfix->dw2_mark_labels; - } - if (mark) - { - dwarf2_where (&CURR_SLOT.debug_line); - CURR_SLOT.debug_line.flags |=3D DWARF2_FLAG_BASIC_BLOCK; - dwarf2_gen_line_info (frag_now_fix (), &CURR_SLOT.debug_line); - dwarf2_consume_line_info (); - } - CURR_SLOT.label_fixups =3D 0; - - for (lfix =3D CURR_SLOT.tag_fixups; lfix; lfix =3D lfix->next) - symbol_set_value_now (lfix->sym); - CURR_SLOT.tag_fixups =3D 0; - - /* In case there are unwind directives following the last instruction, - resolve those now. We only handle prologue, body, and endp directives - here. Give an error for others. */ - for (ptr =3D unwind.current_entry; ptr; ptr =3D ptr->next) - { - switch (ptr->r.type) - { - case prologue: - case prologue_gr: - case body: - case endp: - ptr->slot_number =3D (unsigned long) frag_more (0); - ptr->slot_frag =3D frag_now; - break; - - /* Allow any record which doesn't have a "t" field (i.e., - doesn't relate to a particular instruction). */ - case unwabi: - case br_gr: - case copy_state: - case fr_mem: - case frgr_mem: - case gr_gr: - case gr_mem: - case label_state: - case rp_br: - case spill_base: - case spill_mask: - /* nothing */ - break; - - default: - as_bad (_("Unwind directive not followed by an instruction.")); - break; - } - } - unwind.current_entry =3D NULL; - - subseg_set (saved_seg, saved_subseg); - - if (md.qp.X_op =3D=3D O_register) - as_bad (_("qualifying predicate not followed by instruction")); -} - -void -ia64_cons_align (int nbytes) -{ - if (md.auto_align) - { - int log; - for (log =3D 0; (nbytes & 1) !=3D 1; nbytes >>=3D 1) - log++; - - do_align (log, NULL, 0, 0); - } -} - -#ifdef TE_VMS - -/* .vms_common section, symbol, size, alignment */ - -static void -obj_elf_vms_common (int ignore ATTRIBUTE_UNUSED) -{ - const char *sec_name; - char *sym_name; - char c; - offsetT size; - offsetT cur_size; - offsetT temp; - symbolS *symbolP; - segT current_seg =3D now_seg; - subsegT current_subseg =3D now_subseg; - offsetT log_align; - - /* Section name. */ - sec_name =3D obj_elf_section_name (); - if (sec_name =3D=3D NULL) - return; - - /* Symbol name. */ - SKIP_WHITESPACE (); - if (*input_line_pointer =3D=3D ',') - { - input_line_pointer++; - SKIP_WHITESPACE (); - } - else - { - as_bad (_("expected ',' after section name")); - ignore_rest_of_line (); - return; - } - - c =3D get_symbol_name (&sym_name); - - if (input_line_pointer =3D=3D sym_name) - { - (void) restore_line_pointer (c); - as_bad (_("expected symbol name")); - ignore_rest_of_line (); - return; - } - - symbolP =3D symbol_find_or_make (sym_name); - (void) restore_line_pointer (c); - - if ((S_IS_DEFINED (symbolP) || symbol_equated_p (symbolP)) - && !S_IS_COMMON (symbolP)) - { - as_bad (_("Ignoring attempt to re-define symbol")); - ignore_rest_of_line (); - return; - } - - /* Symbol size. */ - SKIP_WHITESPACE (); - if (*input_line_pointer =3D=3D ',') - { - input_line_pointer++; - SKIP_WHITESPACE (); - } - else - { - as_bad (_("expected ',' after symbol name")); - ignore_rest_of_line (); - return; - } - - temp =3D get_absolute_expression (); - size =3D temp; - size &=3D ((offsetT) 2 << (stdoutput->arch_info->bits_per_address - 1)) = - 1; - if (temp !=3D size) - { - as_warn (_("size (%ld) out of range, ignored"), (long) temp); - ignore_rest_of_line (); - return; - } - - /* Alignment. */ - SKIP_WHITESPACE (); - if (*input_line_pointer =3D=3D ',') - { - input_line_pointer++; - SKIP_WHITESPACE (); - } - else - { - as_bad (_("expected ',' after symbol size")); - ignore_rest_of_line (); - return; - } - - log_align =3D get_absolute_expression (); - - demand_empty_rest_of_line (); - - obj_elf_change_section - (sec_name, SHT_NOBITS, - SHF_ALLOC | SHF_WRITE | SHF_IA_64_VMS_OVERLAID | SHF_IA_64_VMS_GLOBAL, - 0, NULL, true); - - S_SET_VALUE (symbolP, 0); - S_SET_SIZE (symbolP, size); - S_SET_EXTERNAL (symbolP); - S_SET_SEGMENT (symbolP, now_seg); - - symbol_get_bfdsym (symbolP)->flags |=3D BSF_OBJECT; - - record_alignment (now_seg, log_align); - - cur_size =3D bfd_section_size (now_seg); - if ((int) size > cur_size) - { - char *pfrag - =3D frag_var (rs_fill, 1, 1, (relax_substateT)0, NULL, - (valueT)size - (valueT)cur_size, NULL); - *pfrag =3D 0; - bfd_set_section_size (now_seg, size); - } - - /* Switch back to current segment. */ - subseg_set (current_seg, current_subseg); - -#ifdef md_elf_section_change_hook - md_elf_section_change_hook (); -#endif -} - -#endif /* TE_VMS */ - -/* Output COUNT bytes to a memory location. */ -static char *vbyte_mem_ptr =3D NULL; - -static void -output_vbyte_mem (int count, char *ptr, char *comment ATTRIBUTE_UNUSED) -{ - int x; - if (vbyte_mem_ptr =3D=3D NULL) - abort (); - - if (count =3D=3D 0) - return; - for (x =3D 0; x < count; x++) - *(vbyte_mem_ptr++) =3D ptr[x]; -} - -/* Count the number of bytes required for records. */ -static int vbyte_count =3D 0; -static void -count_output (int count, - char *ptr ATTRIBUTE_UNUSED, - char *comment ATTRIBUTE_UNUSED) -{ - vbyte_count +=3D count; -} - -static void -output_R1_format (vbyte_func f, unw_record_type rtype, int rlen) -{ - int r =3D 0; - char byte; - if (rlen > 0x1f) - { - output_R3_format (f, rtype, rlen); - return; - } - - if (rtype =3D=3D body) - r =3D 1; - else if (rtype !=3D prologue) - as_bad (_("record type is not valid")); - - byte =3D UNW_R1 | (r << 5) | (rlen & 0x1f); - (*f) (1, &byte, NULL); -} - -static void -output_R2_format (vbyte_func f, int mask, int grsave, unsigned long rlen) -{ - char bytes[20]; - int count =3D 2; - mask =3D (mask & 0x0f); - grsave =3D (grsave & 0x7f); - - bytes[0] =3D (UNW_R2 | (mask >> 1)); - bytes[1] =3D (((mask & 0x01) << 7) | grsave); - count +=3D output_leb128 (bytes + 2, rlen, 0); - (*f) (count, bytes, NULL); -} - -static void -output_R3_format (vbyte_func f, unw_record_type rtype, unsigned long rlen) -{ - int r =3D 0, count; - char bytes[20]; - if (rlen <=3D 0x1f) - { - output_R1_format (f, rtype, rlen); - return; - } - - if (rtype =3D=3D body) - r =3D 1; - else if (rtype !=3D prologue) - as_bad (_("record type is not valid")); - bytes[0] =3D (UNW_R3 | r); - count =3D output_leb128 (bytes + 1, rlen, 0); - (*f) (count + 1, bytes, NULL); -} - -static void -output_P1_format (vbyte_func f, int brmask) -{ - char byte; - byte =3D UNW_P1 | (brmask & 0x1f); - (*f) (1, &byte, NULL); -} - -static void -output_P2_format (vbyte_func f, int brmask, int gr) -{ - char bytes[2]; - brmask =3D (brmask & 0x1f); - bytes[0] =3D UNW_P2 | (brmask >> 1); - bytes[1] =3D (((brmask & 1) << 7) | gr); - (*f) (2, bytes, NULL); -} - -static void -output_P3_format (vbyte_func f, unw_record_type rtype, int reg) -{ - char bytes[2]; - int r =3D 0; - reg =3D (reg & 0x7f); - switch (rtype) - { - case psp_gr: - r =3D 0; - break; - case rp_gr: - r =3D 1; - break; - case pfs_gr: - r =3D 2; - break; - case preds_gr: - r =3D 3; - break; - case unat_gr: - r =3D 4; - break; - case lc_gr: - r =3D 5; - break; - case rp_br: - r =3D 6; - break; - case rnat_gr: - r =3D 7; - break; - case bsp_gr: - r =3D 8; - break; - case bspstore_gr: - r =3D 9; - break; - case fpsr_gr: - r =3D 10; - break; - case priunat_gr: - r =3D 11; - break; - default: - as_bad (_("Invalid record type for P3 format.")); - } - bytes[0] =3D (UNW_P3 | (r >> 1)); - bytes[1] =3D (((r & 1) << 7) | reg); - (*f) (2, bytes, NULL); -} - -static void -output_P4_format (vbyte_func f, unsigned char *imask, unsigned long imask_= size) -{ - imask[0] =3D UNW_P4; - (*f) (imask_size, (char *) imask, NULL); -} - -static void -output_P5_format (vbyte_func f, int grmask, unsigned long frmask) -{ - char bytes[4]; - grmask =3D (grmask & 0x0f); - - bytes[0] =3D UNW_P5; - bytes[1] =3D ((grmask << 4) | ((frmask & 0x000f0000) >> 16)); - bytes[2] =3D ((frmask & 0x0000ff00) >> 8); - bytes[3] =3D (frmask & 0x000000ff); - (*f) (4, bytes, NULL); -} - -static void -output_P6_format (vbyte_func f, unw_record_type rtype, int rmask) -{ - char byte; - int r =3D 0; - - if (rtype =3D=3D gr_mem) - r =3D 1; - else if (rtype !=3D fr_mem) - as_bad (_("Invalid record type for format P6")); - byte =3D (UNW_P6 | (r << 4) | (rmask & 0x0f)); - (*f) (1, &byte, NULL); -} - -static void -output_P7_format (vbyte_func f, - unw_record_type rtype, - unsigned long w1, - unsigned long w2) -{ - char bytes[20]; - int count =3D 1; - int r =3D 0; - count +=3D output_leb128 (bytes + 1, w1, 0); - switch (rtype) - { - case mem_stack_f: - r =3D 0; - count +=3D output_leb128 (bytes + count, w2 >> 4, 0); - break; - case mem_stack_v: - r =3D 1; - break; - case spill_base: - r =3D 2; - break; - case psp_sprel: - r =3D 3; - break; - case rp_when: - r =3D 4; - break; - case rp_psprel: - r =3D 5; - break; - case pfs_when: - r =3D 6; - break; - case pfs_psprel: - r =3D 7; - break; - case preds_when: - r =3D 8; - break; - case preds_psprel: - r =3D 9; - break; - case lc_when: - r =3D 10; - break; - case lc_psprel: - r =3D 11; - break; - case unat_when: - r =3D 12; - break; - case unat_psprel: - r =3D 13; - break; - case fpsr_when: - r =3D 14; - break; - case fpsr_psprel: - r =3D 15; - break; - default: - break; - } - bytes[0] =3D (UNW_P7 | r); - (*f) (count, bytes, NULL); -} - -static void -output_P8_format (vbyte_func f, unw_record_type rtype, unsigned long t) -{ - char bytes[20]; - int r =3D 0; - int count =3D 2; - bytes[0] =3D UNW_P8; - switch (rtype) - { - case rp_sprel: - r =3D 1; - break; - case pfs_sprel: - r =3D 2; - break; - case preds_sprel: - r =3D 3; - break; - case lc_sprel: - r =3D 4; - break; - case unat_sprel: - r =3D 5; - break; - case fpsr_sprel: - r =3D 6; - break; - case bsp_when: - r =3D 7; - break; - case bsp_psprel: - r =3D 8; - break; - case bsp_sprel: - r =3D 9; - break; - case bspstore_when: - r =3D 10; - break; - case bspstore_psprel: - r =3D 11; - break; - case bspstore_sprel: - r =3D 12; - break; - case rnat_when: - r =3D 13; - break; - case rnat_psprel: - r =3D 14; - break; - case rnat_sprel: - r =3D 15; - break; - case priunat_when_gr: - r =3D 16; - break; - case priunat_psprel: - r =3D 17; - break; - case priunat_sprel: - r =3D 18; - break; - case priunat_when_mem: - r =3D 19; - break; - default: - break; - } - bytes[1] =3D r; - count +=3D output_leb128 (bytes + 2, t, 0); - (*f) (count, bytes, NULL); -} - -static void -output_P9_format (vbyte_func f, int grmask, int gr) -{ - char bytes[3]; - bytes[0] =3D UNW_P9; - bytes[1] =3D (grmask & 0x0f); - bytes[2] =3D (gr & 0x7f); - (*f) (3, bytes, NULL); -} - -static void -output_P10_format (vbyte_func f, int abi, int context) -{ - char bytes[3]; - bytes[0] =3D UNW_P10; - bytes[1] =3D (abi & 0xff); - bytes[2] =3D (context & 0xff); - (*f) (3, bytes, NULL); -} - -static void -output_B1_format (vbyte_func f, unw_record_type rtype, unsigned long label) -{ - char byte; - int r =3D 0; - if (label > 0x1f) - { - output_B4_format (f, rtype, label); - return; - } - if (rtype =3D=3D copy_state) - r =3D 1; - else if (rtype !=3D label_state) - as_bad (_("Invalid record type for format B1")); - - byte =3D (UNW_B1 | (r << 5) | (label & 0x1f)); - (*f) (1, &byte, NULL); -} - -static void -output_B2_format (vbyte_func f, unsigned long ecount, unsigned long t) -{ - char bytes[20]; - int count =3D 1; - if (ecount > 0x1f) - { - output_B3_format (f, ecount, t); - return; - } - bytes[0] =3D (UNW_B2 | (ecount & 0x1f)); - count +=3D output_leb128 (bytes + 1, t, 0); - (*f) (count, bytes, NULL); -} - -static void -output_B3_format (vbyte_func f, unsigned long ecount, unsigned long t) -{ - char bytes[20]; - int count =3D 1; - if (ecount <=3D 0x1f) - { - output_B2_format (f, ecount, t); - return; - } - bytes[0] =3D UNW_B3; - count +=3D output_leb128 (bytes + 1, t, 0); - count +=3D output_leb128 (bytes + count, ecount, 0); - (*f) (count, bytes, NULL); -} - -static void -output_B4_format (vbyte_func f, unw_record_type rtype, unsigned long label) -{ - char bytes[20]; - int r =3D 0; - int count =3D 1; - if (label <=3D 0x1f) - { - output_B1_format (f, rtype, label); - return; - } - - if (rtype =3D=3D copy_state) - r =3D 1; - else if (rtype !=3D label_state) - as_bad (_("Invalid record type for format B1")); - - bytes[0] =3D (UNW_B4 | (r << 3)); - count +=3D output_leb128 (bytes + 1, label, 0); - (*f) (count, bytes, NULL); -} - -static char -format_ab_reg (int ab, int reg) -{ - int ret; - ab =3D (ab & 3); - reg =3D (reg & 0x1f); - ret =3D (ab << 5) | reg; - return ret; -} - -static void -output_X1_format (vbyte_func f, - unw_record_type rtype, - int ab, - int reg, - unsigned long t, - unsigned long w1) -{ - char bytes[20]; - int r =3D 0; - int count =3D 2; - bytes[0] =3D UNW_X1; - - if (rtype =3D=3D spill_sprel) - r =3D 1; - else if (rtype !=3D spill_psprel) - as_bad (_("Invalid record type for format X1")); - bytes[1] =3D ((r << 7) | format_ab_reg (ab, reg)); - count +=3D output_leb128 (bytes + 2, t, 0); - count +=3D output_leb128 (bytes + count, w1, 0); - (*f) (count, bytes, NULL); -} - -static void -output_X2_format (vbyte_func f, - int ab, - int reg, - int x, - int y, - int treg, - unsigned long t) -{ - char bytes[20]; - int count =3D 3; - bytes[0] =3D UNW_X2; - bytes[1] =3D (((x & 1) << 7) | format_ab_reg (ab, reg)); - bytes[2] =3D (((y & 1) << 7) | (treg & 0x7f)); - count +=3D output_leb128 (bytes + 3, t, 0); - (*f) (count, bytes, NULL); -} - -static void -output_X3_format (vbyte_func f, - unw_record_type rtype, - int qp, - int ab, - int reg, - unsigned long t, - unsigned long w1) -{ - char bytes[20]; - int r =3D 0; - int count =3D 3; - bytes[0] =3D UNW_X3; - - if (rtype =3D=3D spill_sprel_p) - r =3D 1; - else if (rtype !=3D spill_psprel_p) - as_bad (_("Invalid record type for format X3")); - bytes[1] =3D ((r << 7) | (qp & 0x3f)); - bytes[2] =3D format_ab_reg (ab, reg); - count +=3D output_leb128 (bytes + 3, t, 0); - count +=3D output_leb128 (bytes + count, w1, 0); - (*f) (count, bytes, NULL); -} - -static void -output_X4_format (vbyte_func f, - int qp, - int ab, - int reg, - int x, - int y, - int treg, - unsigned long t) -{ - char bytes[20]; - int count =3D 4; - bytes[0] =3D UNW_X4; - bytes[1] =3D (qp & 0x3f); - bytes[2] =3D (((x & 1) << 7) | format_ab_reg (ab, reg)); - bytes[3] =3D (((y & 1) << 7) | (treg & 0x7f)); - count +=3D output_leb128 (bytes + 4, t, 0); - (*f) (count, bytes, NULL); -} - -/* This function checks whether there are any outstanding .save-s and - discards them if so. */ - -static void -check_pending_save (void) -{ - if (unwind.pending_saves) - { - unw_rec_list *cur, *prev; - - as_warn (_("Previous .save incomplete")); - for (cur =3D unwind.list, prev =3D NULL; cur; ) - if (&cur->r.record.p =3D=3D unwind.pending_saves) - { - if (prev) - prev->next =3D cur->next; - else - unwind.list =3D cur->next; - if (cur =3D=3D unwind.tail) - unwind.tail =3D prev; - if (cur =3D=3D unwind.current_entry) - unwind.current_entry =3D cur->next; - /* Don't free the first discarded record, it's being used as - terminator for (currently) br_gr and gr_gr processing, and - also prevents leaving a dangling pointer to it in its - predecessor. */ - cur->r.record.p.grmask =3D 0; - cur->r.record.p.brmask =3D 0; - cur->r.record.p.frmask =3D 0; - prev =3D cur->r.record.p.next; - cur->r.record.p.next =3D NULL; - cur =3D prev; - break; - } - else - { - prev =3D cur; - cur =3D cur->next; - } - while (cur) - { - prev =3D cur; - cur =3D cur->r.record.p.next; - free (prev); - } - unwind.pending_saves =3D NULL; - } -} - -/* This function allocates a record list structure, and initializes fields= . */ - -static unw_rec_list * -alloc_record (unw_record_type t) -{ - unw_rec_list *ptr; - ptr =3D XNEW (unw_rec_list); - memset (ptr, 0, sizeof (*ptr)); - ptr->slot_number =3D SLOT_NUM_NOT_SET; - ptr->r.type =3D t; - return ptr; -} - -/* Dummy unwind record used for calculating the length of the last prologu= e or - body region. */ - -static unw_rec_list * -output_endp (void) -{ - unw_rec_list *ptr =3D alloc_record (endp); - return ptr; -} - -static unw_rec_list * -output_prologue (void) -{ - unw_rec_list *ptr =3D alloc_record (prologue); - return ptr; -} - -static unw_rec_list * -output_prologue_gr (unsigned int saved_mask, unsigned int reg) -{ - unw_rec_list *ptr =3D alloc_record (prologue_gr); - ptr->r.record.r.grmask =3D saved_mask; - ptr->r.record.r.grsave =3D reg; - return ptr; -} - -static unw_rec_list * -output_body (void) -{ - unw_rec_list *ptr =3D alloc_record (body); - return ptr; -} - -static unw_rec_list * -output_mem_stack_f (unsigned int size) -{ - unw_rec_list *ptr =3D alloc_record (mem_stack_f); - ptr->r.record.p.size =3D size; - return ptr; -} - -static unw_rec_list * -output_mem_stack_v (void) -{ - unw_rec_list *ptr =3D alloc_record (mem_stack_v); - return ptr; -} - -static unw_rec_list * -output_psp_gr (unsigned int gr) -{ - unw_rec_list *ptr =3D alloc_record (psp_gr); - ptr->r.record.p.r.gr =3D gr; - return ptr; -} - -static unw_rec_list * -output_psp_sprel (unsigned int offset) -{ - unw_rec_list *ptr =3D alloc_record (psp_sprel); - ptr->r.record.p.off.sp =3D offset / 4; - return ptr; -} - -static unw_rec_list * -output_rp_when (void) -{ - unw_rec_list *ptr =3D alloc_record (rp_when); - return ptr; -} - -static unw_rec_list * -output_rp_gr (unsigned int gr) -{ - unw_rec_list *ptr =3D alloc_record (rp_gr); - ptr->r.record.p.r.gr =3D gr; - return ptr; -} - -static unw_rec_list * -output_rp_br (unsigned int br) -{ - unw_rec_list *ptr =3D alloc_record (rp_br); - ptr->r.record.p.r.br =3D br; - return ptr; -} - -static unw_rec_list * -output_rp_psprel (unsigned int offset) -{ - unw_rec_list *ptr =3D alloc_record (rp_psprel); - ptr->r.record.p.off.psp =3D ENCODED_PSP_OFFSET (offset); - return ptr; -} - -static unw_rec_list * -output_rp_sprel (unsigned int offset) -{ - unw_rec_list *ptr =3D alloc_record (rp_sprel); - ptr->r.record.p.off.sp =3D offset / 4; - return ptr; -} - -static unw_rec_list * -output_pfs_when (void) -{ - unw_rec_list *ptr =3D alloc_record (pfs_when); - return ptr; -} - -static unw_rec_list * -output_pfs_gr (unsigned int gr) -{ - unw_rec_list *ptr =3D alloc_record (pfs_gr); - ptr->r.record.p.r.gr =3D gr; - return ptr; -} - -static unw_rec_list * -output_pfs_psprel (unsigned int offset) -{ - unw_rec_list *ptr =3D alloc_record (pfs_psprel); - ptr->r.record.p.off.psp =3D ENCODED_PSP_OFFSET (offset); - return ptr; -} - -static unw_rec_list * -output_pfs_sprel (unsigned int offset) -{ - unw_rec_list *ptr =3D alloc_record (pfs_sprel); - ptr->r.record.p.off.sp =3D offset / 4; - return ptr; -} - -static unw_rec_list * -output_preds_when (void) -{ - unw_rec_list *ptr =3D alloc_record (preds_when); - return ptr; -} - -static unw_rec_list * -output_preds_gr (unsigned int gr) -{ - unw_rec_list *ptr =3D alloc_record (preds_gr); - ptr->r.record.p.r.gr =3D gr; - return ptr; -} - -static unw_rec_list * -output_preds_psprel (unsigned int offset) -{ - unw_rec_list *ptr =3D alloc_record (preds_psprel); - ptr->r.record.p.off.psp =3D ENCODED_PSP_OFFSET (offset); - return ptr; -} - -static unw_rec_list * -output_preds_sprel (unsigned int offset) -{ - unw_rec_list *ptr =3D alloc_record (preds_sprel); - ptr->r.record.p.off.sp =3D offset / 4; - return ptr; -} - -static unw_rec_list * -output_fr_mem (unsigned int mask) -{ - unw_rec_list *ptr =3D alloc_record (fr_mem); - unw_rec_list *cur =3D ptr; - - ptr->r.record.p.frmask =3D mask; - unwind.pending_saves =3D &ptr->r.record.p; - for (;;) - { - unw_rec_list *prev =3D cur; - - /* Clear least significant set bit. */ - mask &=3D ~(mask & (~mask + 1)); - if (!mask) - return ptr; - cur =3D alloc_record (fr_mem); - cur->r.record.p.frmask =3D mask; - /* Retain only least significant bit. */ - prev->r.record.p.frmask ^=3D mask; - prev->r.record.p.next =3D cur; - } -} - -static unw_rec_list * -output_frgr_mem (unsigned int gr_mask, unsigned int fr_mask) -{ - unw_rec_list *ptr =3D alloc_record (frgr_mem); - unw_rec_list *cur =3D ptr; - - unwind.pending_saves =3D &cur->r.record.p; - cur->r.record.p.frmask =3D fr_mask; - while (fr_mask) - { - unw_rec_list *prev =3D cur; - - /* Clear least significant set bit. */ - fr_mask &=3D ~(fr_mask & (~fr_mask + 1)); - if (!gr_mask && !fr_mask) - return ptr; - cur =3D alloc_record (frgr_mem); - cur->r.record.p.frmask =3D fr_mask; - /* Retain only least significant bit. */ - prev->r.record.p.frmask ^=3D fr_mask; - prev->r.record.p.next =3D cur; - } - cur->r.record.p.grmask =3D gr_mask; - for (;;) - { - unw_rec_list *prev =3D cur; - - /* Clear least significant set bit. */ - gr_mask &=3D ~(gr_mask & (~gr_mask + 1)); - if (!gr_mask) - return ptr; - cur =3D alloc_record (frgr_mem); - cur->r.record.p.grmask =3D gr_mask; - /* Retain only least significant bit. */ - prev->r.record.p.grmask ^=3D gr_mask; - prev->r.record.p.next =3D cur; - } -} - -static unw_rec_list * -output_gr_gr (unsigned int mask, unsigned int reg) -{ - unw_rec_list *ptr =3D alloc_record (gr_gr); - unw_rec_list *cur =3D ptr; - - ptr->r.record.p.grmask =3D mask; - ptr->r.record.p.r.gr =3D reg; - unwind.pending_saves =3D &ptr->r.record.p; - for (;;) - { - unw_rec_list *prev =3D cur; - - /* Clear least significant set bit. */ - mask &=3D ~(mask & (~mask + 1)); - if (!mask) - return ptr; - cur =3D alloc_record (gr_gr); - cur->r.record.p.grmask =3D mask; - /* Indicate this record shouldn't be output. */ - cur->r.record.p.r.gr =3D REG_NUM; - /* Retain only least significant bit. */ - prev->r.record.p.grmask ^=3D mask; - prev->r.record.p.next =3D cur; - } -} - -static unw_rec_list * -output_gr_mem (unsigned int mask) -{ - unw_rec_list *ptr =3D alloc_record (gr_mem); - unw_rec_list *cur =3D ptr; - - ptr->r.record.p.grmask =3D mask; - unwind.pending_saves =3D &ptr->r.record.p; - for (;;) - { - unw_rec_list *prev =3D cur; - - /* Clear least significant set bit. */ - mask &=3D ~(mask & (~mask + 1)); - if (!mask) - return ptr; - cur =3D alloc_record (gr_mem); - cur->r.record.p.grmask =3D mask; - /* Retain only least significant bit. */ - prev->r.record.p.grmask ^=3D mask; - prev->r.record.p.next =3D cur; - } -} - -static unw_rec_list * -output_br_mem (unsigned int mask) -{ - unw_rec_list *ptr =3D alloc_record (br_mem); - unw_rec_list *cur =3D ptr; - - ptr->r.record.p.brmask =3D mask; - unwind.pending_saves =3D &ptr->r.record.p; - for (;;) - { - unw_rec_list *prev =3D cur; - - /* Clear least significant set bit. */ - mask &=3D ~(mask & (~mask + 1)); - if (!mask) - return ptr; - cur =3D alloc_record (br_mem); - cur->r.record.p.brmask =3D mask; - /* Retain only least significant bit. */ - prev->r.record.p.brmask ^=3D mask; - prev->r.record.p.next =3D cur; - } -} - -static unw_rec_list * -output_br_gr (unsigned int mask, unsigned int reg) -{ - unw_rec_list *ptr =3D alloc_record (br_gr); - unw_rec_list *cur =3D ptr; - - ptr->r.record.p.brmask =3D mask; - ptr->r.record.p.r.gr =3D reg; - unwind.pending_saves =3D &ptr->r.record.p; - for (;;) - { - unw_rec_list *prev =3D cur; - - /* Clear least significant set bit. */ - mask &=3D ~(mask & (~mask + 1)); - if (!mask) - return ptr; - cur =3D alloc_record (br_gr); - cur->r.record.p.brmask =3D mask; - /* Indicate this record shouldn't be output. */ - cur->r.record.p.r.gr =3D REG_NUM; - /* Retain only least significant bit. */ - prev->r.record.p.brmask ^=3D mask; - prev->r.record.p.next =3D cur; - } -} - -static unw_rec_list * -output_spill_base (unsigned int offset) -{ - unw_rec_list *ptr =3D alloc_record (spill_base); - ptr->r.record.p.off.psp =3D ENCODED_PSP_OFFSET (offset); - return ptr; -} - -static unw_rec_list * -output_unat_when (void) -{ - unw_rec_list *ptr =3D alloc_record (unat_when); - return ptr; -} - -static unw_rec_list * -output_unat_gr (unsigned int gr) -{ - unw_rec_list *ptr =3D alloc_record (unat_gr); - ptr->r.record.p.r.gr =3D gr; - return ptr; -} - -static unw_rec_list * -output_unat_psprel (unsigned int offset) -{ - unw_rec_list *ptr =3D alloc_record (unat_psprel); - ptr->r.record.p.off.psp =3D ENCODED_PSP_OFFSET (offset); - return ptr; -} - -static unw_rec_list * -output_unat_sprel (unsigned int offset) -{ - unw_rec_list *ptr =3D alloc_record (unat_sprel); - ptr->r.record.p.off.sp =3D offset / 4; - return ptr; -} - -static unw_rec_list * -output_lc_when (void) -{ - unw_rec_list *ptr =3D alloc_record (lc_when); - return ptr; -} - -static unw_rec_list * -output_lc_gr (unsigned int gr) -{ - unw_rec_list *ptr =3D alloc_record (lc_gr); - ptr->r.record.p.r.gr =3D gr; - return ptr; -} - -static unw_rec_list * -output_lc_psprel (unsigned int offset) -{ - unw_rec_list *ptr =3D alloc_record (lc_psprel); - ptr->r.record.p.off.psp =3D ENCODED_PSP_OFFSET (offset); - return ptr; -} - -static unw_rec_list * -output_lc_sprel (unsigned int offset) -{ - unw_rec_list *ptr =3D alloc_record (lc_sprel); - ptr->r.record.p.off.sp =3D offset / 4; - return ptr; -} - -static unw_rec_list * -output_fpsr_when (void) -{ - unw_rec_list *ptr =3D alloc_record (fpsr_when); - return ptr; -} - -static unw_rec_list * -output_fpsr_gr (unsigned int gr) -{ - unw_rec_list *ptr =3D alloc_record (fpsr_gr); - ptr->r.record.p.r.gr =3D gr; - return ptr; -} - -static unw_rec_list * -output_fpsr_psprel (unsigned int offset) -{ - unw_rec_list *ptr =3D alloc_record (fpsr_psprel); - ptr->r.record.p.off.psp =3D ENCODED_PSP_OFFSET (offset); - return ptr; -} - -static unw_rec_list * -output_fpsr_sprel (unsigned int offset) -{ - unw_rec_list *ptr =3D alloc_record (fpsr_sprel); - ptr->r.record.p.off.sp =3D offset / 4; - return ptr; -} - -static unw_rec_list * -output_priunat_when_gr (void) -{ - unw_rec_list *ptr =3D alloc_record (priunat_when_gr); - return ptr; -} - -static unw_rec_list * -output_priunat_when_mem (void) -{ - unw_rec_list *ptr =3D alloc_record (priunat_when_mem); - return ptr; -} - -static unw_rec_list * -output_priunat_gr (unsigned int gr) -{ - unw_rec_list *ptr =3D alloc_record (priunat_gr); - ptr->r.record.p.r.gr =3D gr; - return ptr; -} - -static unw_rec_list * -output_priunat_psprel (unsigned int offset) -{ - unw_rec_list *ptr =3D alloc_record (priunat_psprel); - ptr->r.record.p.off.psp =3D ENCODED_PSP_OFFSET (offset); - return ptr; -} - -static unw_rec_list * -output_priunat_sprel (unsigned int offset) -{ - unw_rec_list *ptr =3D alloc_record (priunat_sprel); - ptr->r.record.p.off.sp =3D offset / 4; - return ptr; -} - -static unw_rec_list * -output_bsp_when (void) -{ - unw_rec_list *ptr =3D alloc_record (bsp_when); - return ptr; -} - -static unw_rec_list * -output_bsp_gr (unsigned int gr) -{ - unw_rec_list *ptr =3D alloc_record (bsp_gr); - ptr->r.record.p.r.gr =3D gr; - return ptr; -} - -static unw_rec_list * -output_bsp_psprel (unsigned int offset) -{ - unw_rec_list *ptr =3D alloc_record (bsp_psprel); - ptr->r.record.p.off.psp =3D ENCODED_PSP_OFFSET (offset); - return ptr; -} - -static unw_rec_list * -output_bsp_sprel (unsigned int offset) -{ - unw_rec_list *ptr =3D alloc_record (bsp_sprel); - ptr->r.record.p.off.sp =3D offset / 4; - return ptr; -} - -static unw_rec_list * -output_bspstore_when (void) -{ - unw_rec_list *ptr =3D alloc_record (bspstore_when); - return ptr; -} - -static unw_rec_list * -output_bspstore_gr (unsigned int gr) -{ - unw_rec_list *ptr =3D alloc_record (bspstore_gr); - ptr->r.record.p.r.gr =3D gr; - return ptr; -} - -static unw_rec_list * -output_bspstore_psprel (unsigned int offset) -{ - unw_rec_list *ptr =3D alloc_record (bspstore_psprel); - ptr->r.record.p.off.psp =3D ENCODED_PSP_OFFSET (offset); - return ptr; -} - -static unw_rec_list * -output_bspstore_sprel (unsigned int offset) -{ - unw_rec_list *ptr =3D alloc_record (bspstore_sprel); - ptr->r.record.p.off.sp =3D offset / 4; - return ptr; -} - -static unw_rec_list * -output_rnat_when (void) -{ - unw_rec_list *ptr =3D alloc_record (rnat_when); - return ptr; -} - -static unw_rec_list * -output_rnat_gr (unsigned int gr) -{ - unw_rec_list *ptr =3D alloc_record (rnat_gr); - ptr->r.record.p.r.gr =3D gr; - return ptr; -} - -static unw_rec_list * -output_rnat_psprel (unsigned int offset) -{ - unw_rec_list *ptr =3D alloc_record (rnat_psprel); - ptr->r.record.p.off.psp =3D ENCODED_PSP_OFFSET (offset); - return ptr; -} - -static unw_rec_list * -output_rnat_sprel (unsigned int offset) -{ - unw_rec_list *ptr =3D alloc_record (rnat_sprel); - ptr->r.record.p.off.sp =3D offset / 4; - return ptr; -} - -static unw_rec_list * -output_unwabi (unsigned long abi, unsigned long context) -{ - unw_rec_list *ptr =3D alloc_record (unwabi); - ptr->r.record.p.abi =3D abi; - ptr->r.record.p.context =3D context; - return ptr; -} - -static unw_rec_list * -output_epilogue (unsigned long ecount) -{ - unw_rec_list *ptr =3D alloc_record (epilogue); - ptr->r.record.b.ecount =3D ecount; - return ptr; -} - -static unw_rec_list * -output_label_state (unsigned long label) -{ - unw_rec_list *ptr =3D alloc_record (label_state); - ptr->r.record.b.label =3D label; - return ptr; -} - -static unw_rec_list * -output_copy_state (unsigned long label) -{ - unw_rec_list *ptr =3D alloc_record (copy_state); - ptr->r.record.b.label =3D label; - return ptr; -} - -static unw_rec_list * -output_spill_psprel (unsigned int ab, - unsigned int reg, - unsigned int offset, - unsigned int predicate) -{ - unw_rec_list *ptr =3D alloc_record (predicate ? spill_psprel_p : spill_p= sprel); - ptr->r.record.x.ab =3D ab; - ptr->r.record.x.reg =3D reg; - ptr->r.record.x.where.pspoff =3D ENCODED_PSP_OFFSET (offset); - ptr->r.record.x.qp =3D predicate; - return ptr; -} - -static unw_rec_list * -output_spill_sprel (unsigned int ab, - unsigned int reg, - unsigned int offset, - unsigned int predicate) -{ - unw_rec_list *ptr =3D alloc_record (predicate ? spill_sprel_p : spill_sp= rel); - ptr->r.record.x.ab =3D ab; - ptr->r.record.x.reg =3D reg; - ptr->r.record.x.where.spoff =3D offset / 4; - ptr->r.record.x.qp =3D predicate; - return ptr; -} - -static unw_rec_list * -output_spill_reg (unsigned int ab, - unsigned int reg, - unsigned int targ_reg, - unsigned int xy, - unsigned int predicate) -{ - unw_rec_list *ptr =3D alloc_record (predicate ? spill_reg_p : spill_reg); - ptr->r.record.x.ab =3D ab; - ptr->r.record.x.reg =3D reg; - ptr->r.record.x.where.reg =3D targ_reg; - ptr->r.record.x.xy =3D xy; - ptr->r.record.x.qp =3D predicate; - return ptr; -} - -/* Given a unw_rec_list process the correct format with the - specified function. */ - -static void -process_one_record (unw_rec_list *ptr, vbyte_func f) -{ - unsigned int fr_mask, gr_mask; - - switch (ptr->r.type) - { - /* This is a dummy record that takes up no space in the output. */ - case endp: - break; - - case gr_mem: - case fr_mem: - case br_mem: - case frgr_mem: - /* These are taken care of by prologue/prologue_gr. */ - break; - - case prologue_gr: - case prologue: - if (ptr->r.type =3D=3D prologue_gr) - output_R2_format (f, ptr->r.record.r.grmask, - ptr->r.record.r.grsave, ptr->r.record.r.rlen); - else - output_R1_format (f, ptr->r.type, ptr->r.record.r.rlen); - - /* Output descriptor(s) for union of register spills (if any). */ - gr_mask =3D ptr->r.record.r.mask.gr_mem; - fr_mask =3D ptr->r.record.r.mask.fr_mem; - if (fr_mask) - { - if ((fr_mask & ~0xfUL) =3D=3D 0) - output_P6_format (f, fr_mem, fr_mask); - else - { - output_P5_format (f, gr_mask, fr_mask); - gr_mask =3D 0; - } - } - if (gr_mask) - output_P6_format (f, gr_mem, gr_mask); - if (ptr->r.record.r.mask.br_mem) - output_P1_format (f, ptr->r.record.r.mask.br_mem); - - /* output imask descriptor if necessary: */ - if (ptr->r.record.r.mask.i) - output_P4_format (f, ptr->r.record.r.mask.i, - ptr->r.record.r.imask_size); - break; - - case body: - output_R1_format (f, ptr->r.type, ptr->r.record.r.rlen); - break; - case mem_stack_f: - case mem_stack_v: - output_P7_format (f, ptr->r.type, ptr->r.record.p.t, - ptr->r.record.p.size); - break; - case psp_gr: - case rp_gr: - case pfs_gr: - case preds_gr: - case unat_gr: - case lc_gr: - case fpsr_gr: - case priunat_gr: - case bsp_gr: - case bspstore_gr: - case rnat_gr: - output_P3_format (f, ptr->r.type, ptr->r.record.p.r.gr); - break; - case rp_br: - output_P3_format (f, rp_br, ptr->r.record.p.r.br); - break; - case psp_sprel: - output_P7_format (f, psp_sprel, ptr->r.record.p.off.sp, 0); - break; - case rp_when: - case pfs_when: - case preds_when: - case unat_when: - case lc_when: - case fpsr_when: - output_P7_format (f, ptr->r.type, ptr->r.record.p.t, 0); - break; - case rp_psprel: - case pfs_psprel: - case preds_psprel: - case unat_psprel: - case lc_psprel: - case fpsr_psprel: - case spill_base: - output_P7_format (f, ptr->r.type, ptr->r.record.p.off.psp, 0); - break; - case rp_sprel: - case pfs_sprel: - case preds_sprel: - case unat_sprel: - case lc_sprel: - case fpsr_sprel: - case priunat_sprel: - case bsp_sprel: - case bspstore_sprel: - case rnat_sprel: - output_P8_format (f, ptr->r.type, ptr->r.record.p.off.sp); - break; - case gr_gr: - if (ptr->r.record.p.r.gr < REG_NUM) - { - const unw_rec_list *cur =3D ptr; - - gr_mask =3D cur->r.record.p.grmask; - while ((cur =3D cur->r.record.p.next) !=3D NULL) - gr_mask |=3D cur->r.record.p.grmask; - output_P9_format (f, gr_mask, ptr->r.record.p.r.gr); - } - break; - case br_gr: - if (ptr->r.record.p.r.gr < REG_NUM) - { - const unw_rec_list *cur =3D ptr; - - gr_mask =3D cur->r.record.p.brmask; - while ((cur =3D cur->r.record.p.next) !=3D NULL) - gr_mask |=3D cur->r.record.p.brmask; - output_P2_format (f, gr_mask, ptr->r.record.p.r.gr); - } - break; - case spill_mask: - as_bad (_("spill_mask record unimplemented.")); - break; - case priunat_when_gr: - case priunat_when_mem: - case bsp_when: - case bspstore_when: - case rnat_when: - output_P8_format (f, ptr->r.type, ptr->r.record.p.t); - break; - case priunat_psprel: - case bsp_psprel: - case bspstore_psprel: - case rnat_psprel: - output_P8_format (f, ptr->r.type, ptr->r.record.p.off.psp); - break; - case unwabi: - output_P10_format (f, ptr->r.record.p.abi, ptr->r.record.p.context); - break; - case epilogue: - output_B3_format (f, ptr->r.record.b.ecount, ptr->r.record.b.t); - break; - case label_state: - case copy_state: - output_B4_format (f, ptr->r.type, ptr->r.record.b.label); - break; - case spill_psprel: - output_X1_format (f, ptr->r.type, ptr->r.record.x.ab, - ptr->r.record.x.reg, ptr->r.record.x.t, - ptr->r.record.x.where.pspoff); - break; - case spill_sprel: - output_X1_format (f, ptr->r.type, ptr->r.record.x.ab, - ptr->r.record.x.reg, ptr->r.record.x.t, - ptr->r.record.x.where.spoff); - break; - case spill_reg: - output_X2_format (f, ptr->r.record.x.ab, ptr->r.record.x.reg, - ptr->r.record.x.xy >> 1, ptr->r.record.x.xy, - ptr->r.record.x.where.reg, ptr->r.record.x.t); - break; - case spill_psprel_p: - output_X3_format (f, ptr->r.type, ptr->r.record.x.qp, - ptr->r.record.x.ab, ptr->r.record.x.reg, - ptr->r.record.x.t, ptr->r.record.x.where.pspoff); - break; - case spill_sprel_p: - output_X3_format (f, ptr->r.type, ptr->r.record.x.qp, - ptr->r.record.x.ab, ptr->r.record.x.reg, - ptr->r.record.x.t, ptr->r.record.x.where.spoff); - break; - case spill_reg_p: - output_X4_format (f, ptr->r.record.x.qp, ptr->r.record.x.ab, - ptr->r.record.x.reg, ptr->r.record.x.xy >> 1, - ptr->r.record.x.xy, ptr->r.record.x.where.reg, - ptr->r.record.x.t); - break; - default: - as_bad (_("record_type_not_valid")); - break; - } -} - -/* Given a unw_rec_list list, process all the records with - the specified function. */ -static void -process_unw_records (unw_rec_list *list, vbyte_func f) -{ - unw_rec_list *ptr; - for (ptr =3D list; ptr; ptr =3D ptr->next) - process_one_record (ptr, f); -} - -/* Determine the size of a record list in bytes. */ -static int -calc_record_size (unw_rec_list *list) -{ - vbyte_count =3D 0; - process_unw_records (list, count_output); - return vbyte_count; -} - -/* Return the number of bits set in the input value. - Perhaps this has a better place... */ -#if __GNUC__ > 3 || (__GNUC__ =3D=3D 3 && __GNUC_MINOR__ >=3D 4) -# define popcount __builtin_popcount -#else -static int -popcount (unsigned x) -{ - static const unsigned char popcnt[16] =3D - { - 0, 1, 1, 2, - 1, 2, 2, 3, - 1, 2, 2, 3, - 2, 3, 3, 4 - }; - - if (x < NELEMS (popcnt)) - return popcnt[x]; - return popcnt[x % NELEMS (popcnt)] + popcount (x / NELEMS (popcnt)); -} -#endif - -/* Update IMASK bitmask to reflect the fact that one or more registers - of type TYPE are saved starting at instruction with index T. If N - bits are set in REGMASK, it is assumed that instructions T through - T+N-1 save these registers. - - TYPE values: - 0: no save - 1: instruction saves next fp reg - 2: instruction saves next general reg - 3: instruction saves next branch reg */ -static void -set_imask (unw_rec_list *region, - unsigned long regmask, - unsigned long t, - unsigned int type) -{ - unsigned char *imask; - unsigned long imask_size; - unsigned int i; - int pos; - - imask =3D region->r.record.r.mask.i; - imask_size =3D region->r.record.r.imask_size; - if (!imask) - { - imask_size =3D (region->r.record.r.rlen * 2 + 7) / 8 + 1; - imask =3D XCNEWVEC (unsigned char, imask_size); - - region->r.record.r.imask_size =3D imask_size; - region->r.record.r.mask.i =3D imask; - } - - i =3D (t / 4) + 1; - pos =3D 2 * (3 - t % 4); - while (regmask) - { - if (i >=3D imask_size) - { - as_bad (_("Ignoring attempt to spill beyond end of region")); - return; - } - - imask[i] |=3D (type & 0x3) << pos; - - regmask &=3D (regmask - 1); - pos -=3D 2; - if (pos < 0) - { - pos =3D 0; - ++i; - } - } -} - -/* Return the number of instruction slots from FIRST_ADDR to SLOT_ADDR. - SLOT_FRAG is the frag containing SLOT_ADDR, and FIRST_FRAG is the frag - containing FIRST_ADDR. If BEFORE_RELAX, then we use worst-case estimat= es - for frag sizes. */ - -static unsigned long -slot_index (unsigned long slot_addr, - fragS *slot_frag, - unsigned long first_addr, - fragS *first_frag, - int before_relax) -{ - unsigned long s_index =3D 0; - - /* First time we are called, the initial address and frag are invalid. = */ - if (first_addr =3D=3D 0) - return 0; - - /* If the two addresses are in different frags, then we need to add in - the remaining size of this frag, and then the entire size of intermed= iate - frags. */ - while (slot_frag !=3D first_frag) - { - unsigned long start_addr =3D (unsigned long) &first_frag->fr_literal; - - if (! before_relax) - { - /* We can get the final addresses only during and after - relaxation. */ - if (first_frag->fr_next && first_frag->fr_next->fr_address) - s_index +=3D 3 * ((first_frag->fr_next->fr_address - - first_frag->fr_address - - first_frag->fr_fix) >> 4); - } - else - /* We don't know what the final addresses will be. We try our - best to estimate. */ - switch (first_frag->fr_type) - { - default: - break; - - case rs_space: - as_fatal (_("Only constant space allocation is supported")); - break; - - case rs_align: - case rs_align_code: - case rs_align_test: - /* Take alignment into account. Assume the worst case - before relaxation. */ - s_index +=3D 3 * ((1 << first_frag->fr_offset) >> 4); - break; - - case rs_org: - if (first_frag->fr_symbol) - { - as_fatal (_("Only constant offsets are supported")); - break; - } - /* Fall through. */ - case rs_fill: - s_index +=3D 3 * (first_frag->fr_offset >> 4); - break; - } - - /* Add in the full size of the frag converted to instruction slots. = */ - s_index +=3D 3 * (first_frag->fr_fix >> 4); - /* Subtract away the initial part before first_addr. */ - s_index -=3D (3 * ((first_addr >> 4) - (start_addr >> 4)) - + ((first_addr & 0x3) - (start_addr & 0x3))); - - /* Move to the beginning of the next frag. */ - first_frag =3D first_frag->fr_next; - first_addr =3D (unsigned long) &first_frag->fr_literal; - - /* This can happen if there is section switching in the middle of a - function, causing the frag chain for the function to be broken. - It is too difficult to recover safely from this problem, so we just - exit with an error. */ - if (first_frag =3D=3D NULL) - as_fatal (_("Section switching in code is not supported.")); - } - - /* Add in the used part of the last frag. */ - s_index +=3D (3 * ((slot_addr >> 4) - (first_addr >> 4)) - + ((slot_addr & 0x3) - (first_addr & 0x3))); - return s_index; -} - -/* Optimize unwind record directives. */ - -static unw_rec_list * -optimize_unw_records (unw_rec_list *list) -{ - if (!list) - return NULL; - - /* If the only unwind record is ".prologue" or ".prologue" followed - by ".body", then we can optimize the unwind directives away. */ - if (list->r.type =3D=3D prologue - && (list->next->r.type =3D=3D endp - || (list->next->r.type =3D=3D body && list->next->next->r.type =3D=3D e= ndp))) - return NULL; - - return list; -} - -/* Given a complete record list, process any records which have - unresolved fields, (ie length counts for a prologue). After - this has been run, all necessary information should be available - within each record to generate an image. */ - -static void -fixup_unw_records (unw_rec_list *list, int before_relax) -{ - unw_rec_list *ptr, *region =3D 0; - unsigned long first_addr =3D 0, rlen =3D 0, t; - fragS *first_frag =3D 0; - - for (ptr =3D list; ptr; ptr =3D ptr->next) - { - if (ptr->slot_number =3D=3D SLOT_NUM_NOT_SET) - as_bad (_("Insn slot not set in unwind record.")); - t =3D slot_index (ptr->slot_number, ptr->slot_frag, - first_addr, first_frag, before_relax); - switch (ptr->r.type) - { - case prologue: - case prologue_gr: - case body: - { - unw_rec_list *last; - int size; - unsigned long last_addr =3D 0; - fragS *last_frag =3D NULL; - - first_addr =3D ptr->slot_number; - first_frag =3D ptr->slot_frag; - /* Find either the next body/prologue start, or the end of - the function, and determine the size of the region. */ - for (last =3D ptr->next; last !=3D NULL; last =3D last->next) - if (last->r.type =3D=3D prologue || last->r.type =3D=3D prologue_gr - || last->r.type =3D=3D body || last->r.type =3D=3D endp) - { - last_addr =3D last->slot_number; - last_frag =3D last->slot_frag; - break; - } - size =3D slot_index (last_addr, last_frag, first_addr, first_frag, - before_relax); - rlen =3D ptr->r.record.r.rlen =3D size; - if (ptr->r.type =3D=3D body) - /* End of region. */ - region =3D 0; - else - region =3D ptr; - break; - } - case epilogue: - if (t < rlen) - ptr->r.record.b.t =3D rlen - 1 - t; - else - /* This happens when a memory-stack-less procedure uses a - ".restore sp" directive at the end of a region to pop - the frame state. */ - ptr->r.record.b.t =3D 0; - break; - - case mem_stack_f: - case mem_stack_v: - case rp_when: - case pfs_when: - case preds_when: - case unat_when: - case lc_when: - case fpsr_when: - case priunat_when_gr: - case priunat_when_mem: - case bsp_when: - case bspstore_when: - case rnat_when: - ptr->r.record.p.t =3D t; - break; - - case spill_reg: - case spill_sprel: - case spill_psprel: - case spill_reg_p: - case spill_sprel_p: - case spill_psprel_p: - ptr->r.record.x.t =3D t; - break; - - case frgr_mem: - if (!region) - { - as_bad (_("frgr_mem record before region record!")); - return; - } - region->r.record.r.mask.fr_mem |=3D ptr->r.record.p.frmask; - region->r.record.r.mask.gr_mem |=3D ptr->r.record.p.grmask; - set_imask (region, ptr->r.record.p.frmask, t, 1); - set_imask (region, ptr->r.record.p.grmask, t, 2); - break; - case fr_mem: - if (!region) - { - as_bad (_("fr_mem record before region record!")); - return; - } - region->r.record.r.mask.fr_mem |=3D ptr->r.record.p.frmask; - set_imask (region, ptr->r.record.p.frmask, t, 1); - break; - case gr_mem: - if (!region) - { - as_bad (_("gr_mem record before region record!")); - return; - } - region->r.record.r.mask.gr_mem |=3D ptr->r.record.p.grmask; - set_imask (region, ptr->r.record.p.grmask, t, 2); - break; - case br_mem: - if (!region) - { - as_bad (_("br_mem record before region record!")); - return; - } - region->r.record.r.mask.br_mem |=3D ptr->r.record.p.brmask; - set_imask (region, ptr->r.record.p.brmask, t, 3); - break; - - case gr_gr: - if (!region) - { - as_bad (_("gr_gr record before region record!")); - return; - } - set_imask (region, ptr->r.record.p.grmask, t, 2); - break; - case br_gr: - if (!region) - { - as_bad (_("br_gr record before region record!")); - return; - } - set_imask (region, ptr->r.record.p.brmask, t, 3); - break; - - default: - break; - } - } -} - -/* Estimate the size of a frag before relaxing. We only have one type of = frag - to handle here, which is the unwind info frag. */ - -int -ia64_estimate_size_before_relax (fragS *frag, - asection *segtype ATTRIBUTE_UNUSED) -{ - unw_rec_list *list; - int len, size, pad; - - /* ??? This code is identical to the first part of ia64_convert_frag. */ - list =3D (unw_rec_list *) frag->fr_opcode; - fixup_unw_records (list, 0); - - len =3D calc_record_size (list); - /* pad to pointer-size boundary. */ - pad =3D len % md.pointer_size; - if (pad !=3D 0) - len +=3D md.pointer_size - pad; - /* Add 8 for the header. */ - size =3D len + 8; - /* Add a pointer for the personality offset. */ - if (frag->fr_offset) - size +=3D md.pointer_size; - - /* fr_var carries the max_chars that we created the fragment with. - We must, of course, have allocated enough memory earlier. */ - gas_assert (frag->fr_var >=3D size); - - return frag->fr_fix + size; -} - -/* This function converts a rs_machine_dependent variant frag into a - normal fill frag with the unwind image from the record list. */ -void -ia64_convert_frag (fragS *frag) -{ - unw_rec_list *list; - int len, size, pad; - valueT flag_value; - - /* ??? This code is identical to ia64_estimate_size_before_relax. */ - list =3D (unw_rec_list *) frag->fr_opcode; - fixup_unw_records (list, 0); - - len =3D calc_record_size (list); - /* pad to pointer-size boundary. */ - pad =3D len % md.pointer_size; - if (pad !=3D 0) - len +=3D md.pointer_size - pad; - /* Add 8 for the header. */ - size =3D len + 8; - /* Add a pointer for the personality offset. */ - if (frag->fr_offset) - size +=3D md.pointer_size; - - /* fr_var carries the max_chars that we created the fragment with. - We must, of course, have allocated enough memory earlier. */ - gas_assert (frag->fr_var >=3D size); - - /* Initialize the header area. fr_offset is initialized with - unwind.personality_routine. */ - if (frag->fr_offset) - { - if (md.flags & EF_IA_64_ABI64) - flag_value =3D (bfd_vma) 3 << 32; - else - /* 32-bit unwind info block. */ - flag_value =3D (bfd_vma) 0x1003 << 32; - } - else - flag_value =3D 0; - - md_number_to_chars (frag->fr_literal, - (((bfd_vma) 1 << 48) /* Version. */ - | flag_value /* U & E handler flags. */ - | (len / md.pointer_size)), /* Length. */ - 8); - - /* Skip the header. */ - vbyte_mem_ptr =3D frag->fr_literal + 8; - process_unw_records (list, output_vbyte_mem); - - /* Fill the padding bytes with zeros. */ - if (pad !=3D 0) - md_number_to_chars (frag->fr_literal + len + 8 - md.pointer_size + pad= , 0, - md.pointer_size - pad); - /* Fill the unwind personality with zeros. */ - if (frag->fr_offset) - md_number_to_chars (frag->fr_literal + size - md.pointer_size, 0, - md.pointer_size); - - frag->fr_fix +=3D size; - frag->fr_type =3D rs_fill; - frag->fr_var =3D 0; - frag->fr_offset =3D 0; -} - -static int -parse_predicate_and_operand (expressionS *e, unsigned *qp, const char *po) -{ - int sep =3D parse_operand_and_eval (e, ','); - - *qp =3D e->X_add_number - REG_P; - if (e->X_op !=3D O_register || *qp > 63) - { - as_bad (_("First operand to .%s must be a predicate"), po); - *qp =3D 0; - } - else if (*qp =3D=3D 0) - as_warn (_("Pointless use of p0 as first operand to .%s"), po); - if (sep =3D=3D ',') - sep =3D parse_operand_and_eval (e, ','); - else - e->X_op =3D O_absent; - return sep; -} - -static void -convert_expr_to_ab_reg (const expressionS *e, - unsigned int *ab, - unsigned int *regp, - const char *po, - int n) -{ - unsigned int reg =3D e->X_add_number; - - *ab =3D *regp =3D 0; /* Anything valid is good here. */ - - if (e->X_op !=3D O_register) - reg =3D REG_GR; /* Anything invalid is good here. */ - - if (reg >=3D (REG_GR + 4) && reg <=3D (REG_GR + 7)) - { - *ab =3D 0; - *regp =3D reg - REG_GR; - } - else if ((reg >=3D (REG_FR + 2) && reg <=3D (REG_FR + 5)) - || (reg >=3D (REG_FR + 16) && reg <=3D (REG_FR + 31))) - { - *ab =3D 1; - *regp =3D reg - REG_FR; - } - else if (reg >=3D (REG_BR + 1) && reg <=3D (REG_BR + 5)) - { - *ab =3D 2; - *regp =3D reg - REG_BR; - } - else - { - *ab =3D 3; - switch (reg) - { - case REG_PR: *regp =3D 0; break; - case REG_PSP: *regp =3D 1; break; - case REG_PRIUNAT: *regp =3D 2; break; - case REG_BR + 0: *regp =3D 3; break; - case REG_AR + AR_BSP: *regp =3D 4; break; - case REG_AR + AR_BSPSTORE: *regp =3D 5; break; - case REG_AR + AR_RNAT: *regp =3D 6; break; - case REG_AR + AR_UNAT: *regp =3D 7; break; - case REG_AR + AR_FPSR: *regp =3D 8; break; - case REG_AR + AR_PFS: *regp =3D 9; break; - case REG_AR + AR_LC: *regp =3D 10; break; - - default: - as_bad (_("Operand %d to .%s must be a preserved register"), n, po); - break; - } - } -} - -static void -convert_expr_to_xy_reg (const expressionS *e, - unsigned int *xy, - unsigned int *regp, - const char *po, - int n) -{ - unsigned int reg =3D e->X_add_number; - - *xy =3D *regp =3D 0; /* Anything valid is good here. */ - - if (e->X_op !=3D O_register) - reg =3D REG_GR; /* Anything invalid is good here. */ - - if (reg >=3D (REG_GR + 1) && reg <=3D (REG_GR + 127)) - { - *xy =3D 0; - *regp =3D reg - REG_GR; - } - else if (reg >=3D (REG_FR + 2) && reg <=3D (REG_FR + 127)) - { - *xy =3D 1; - *regp =3D reg - REG_FR; - } - else if (reg >=3D REG_BR && reg <=3D (REG_BR + 7)) - { - *xy =3D 2; - *regp =3D reg - REG_BR; - } - else - as_bad (_("Operand %d to .%s must be a writable register"), n, po); -} - -static void -dot_align (int arg) -{ - /* The current frag is an alignment frag. */ - align_frag =3D frag_now; - s_align_bytes (arg); -} - -static void -dot_radix (int dummy ATTRIBUTE_UNUSED) -{ - char *radix; - int ch; - - SKIP_WHITESPACE (); - - if (is_it_end_of_statement ()) - return; - ch =3D get_symbol_name (&radix); - ia64_canonicalize_symbol_name (radix); - if (strcasecmp (radix, "C")) - as_bad (_("Radix `%s' unsupported or invalid"), radix); - (void) restore_line_pointer (ch); - demand_empty_rest_of_line (); -} - -/* Helper function for .loc directives. If the assembler is not generating - line number info, then we need to remember which instructions have a .l= oc - directive, and only call dwarf2_gen_line_info for those instructions. = */ - -static void -dot_loc (int x) -{ - CURR_SLOT.loc_directive_seen =3D 1; - dwarf2_directive_loc (x); -} - -/* .sbss, .srodata etc. are macros that expand into ".section SECNAME". */ -static void -dot_special_section (int which) -{ - set_section ((char *) special_section_name[which]); -} - -/* Return -1 for warning and 0 for error. */ - -static int -unwind_diagnostic (const char * region, const char *directive) -{ - if (md.unwind_check =3D=3D unwind_check_warning) - { - as_warn (_(".%s outside of %s"), directive, region); - return -1; - } - else - { - as_bad (_(".%s outside of %s"), directive, region); - ignore_rest_of_line (); - return 0; - } -} - -/* Return 1 if a directive is in a procedure, -1 if a directive isn't in - a procedure but the unwind directive check is set to warning, 0 if - a directive isn't in a procedure and the unwind directive check is set - to error. */ - -static int -in_procedure (const char *directive) -{ - if (unwind.proc_pending.sym - && (!unwind.saved_text_seg || strcmp (directive, "endp") =3D=3D 0)) - return 1; - return unwind_diagnostic ("procedure", directive); -} - -/* Return 1 if a directive is in a prologue, -1 if a directive isn't in - a prologue but the unwind directive check is set to warning, 0 if - a directive isn't in a prologue and the unwind directive check is set - to error. */ - -static int -in_prologue (const char *directive) -{ - int in =3D in_procedure (directive); - - if (in > 0 && !unwind.prologue) - in =3D unwind_diagnostic ("prologue", directive); - check_pending_save (); - return in; -} - -/* Return 1 if a directive is in a body, -1 if a directive isn't in - a body but the unwind directive check is set to warning, 0 if - a directive isn't in a body and the unwind directive check is set - to error. */ - -static int -in_body (const char *directive) -{ - int in =3D in_procedure (directive); - - if (in > 0 && !unwind.body) - in =3D unwind_diagnostic ("body region", directive); - return in; -} - -static void -add_unwind_entry (unw_rec_list *ptr, int sep) -{ - if (ptr) - { - if (unwind.tail) - unwind.tail->next =3D ptr; - else - unwind.list =3D ptr; - unwind.tail =3D ptr; - - /* The current entry can in fact be a chain of unwind entries. */ - if (unwind.current_entry =3D=3D NULL) - unwind.current_entry =3D ptr; - } - - /* The current entry can in fact be a chain of unwind entries. */ - if (unwind.current_entry =3D=3D NULL) - unwind.current_entry =3D ptr; - - if (sep =3D=3D ',') - { - char *name; - /* Parse a tag permitted for the current directive. */ - int ch; - - SKIP_WHITESPACE (); - ch =3D get_symbol_name (&name); - /* FIXME: For now, just issue a warning that this isn't implemented.= */ - { - static int warned; - - if (!warned) - { - warned =3D 1; - as_warn (_("Tags on unwind pseudo-ops aren't supported, yet")); - } - } - (void) restore_line_pointer (ch); - } - if (sep !=3D NOT_A_CHAR) - demand_empty_rest_of_line (); -} - -static void -dot_fframe (int dummy ATTRIBUTE_UNUSED) -{ - expressionS e; - int sep; - - if (!in_prologue ("fframe")) - return; - - sep =3D parse_operand_and_eval (&e, ','); - - if (e.X_op !=3D O_constant) - { - as_bad (_("First operand to .fframe must be a constant")); - e.X_add_number =3D 0; - } - add_unwind_entry (output_mem_stack_f (e.X_add_number), sep); -} - -static void -dot_vframe (int dummy ATTRIBUTE_UNUSED) -{ - expressionS e; - unsigned reg; - int sep; - - if (!in_prologue ("vframe")) - return; - - sep =3D parse_operand_and_eval (&e, ','); - reg =3D e.X_add_number - REG_GR; - if (e.X_op !=3D O_register || reg > 127) - { - as_bad (_("First operand to .vframe must be a general register")); - reg =3D 0; - } - add_unwind_entry (output_mem_stack_v (), sep); - if (! (unwind.prologue_mask & 2)) - add_unwind_entry (output_psp_gr (reg), NOT_A_CHAR); - else if (reg !=3D unwind.prologue_gr - + (unsigned) popcount (unwind.prologue_mask & -(2 << 1))) - as_warn (_("Operand of .vframe contradicts .prologue")); -} - -static void -dot_vframesp (int psp) -{ - expressionS e; - int sep; - - if (psp) - as_warn (_(".vframepsp is meaningless, assuming .vframesp was meant")); - - if (!in_prologue ("vframesp")) - return; - - sep =3D parse_operand_and_eval (&e, ','); - if (e.X_op !=3D O_constant) - { - as_bad (_("Operand to .vframesp must be a constant (sp-relative offs= et)")); - e.X_add_number =3D 0; - } - add_unwind_entry (output_mem_stack_v (), sep); - add_unwind_entry (output_psp_sprel (e.X_add_number), NOT_A_CHAR); -} - -static void -dot_save (int dummy ATTRIBUTE_UNUSED) -{ - expressionS e1, e2; - unsigned reg1, reg2; - int sep; - - if (!in_prologue ("save")) - return; - - sep =3D parse_operand_and_eval (&e1, ','); - if (sep =3D=3D ',') - sep =3D parse_operand_and_eval (&e2, ','); - else - e2.X_op =3D O_absent; - - reg1 =3D e1.X_add_number; - /* Make sure it's a valid ar.xxx reg, OR its br0, aka 'rp'. */ - if (e1.X_op !=3D O_register) - { - as_bad (_("First operand to .save not a register")); - reg1 =3D REG_PR; /* Anything valid is good here. */ - } - reg2 =3D e2.X_add_number - REG_GR; - if (e2.X_op !=3D O_register || reg2 > 127) - { - as_bad (_("Second operand to .save not a valid register")); - reg2 =3D 0; - } - switch (reg1) - { - case REG_AR + AR_BSP: - add_unwind_entry (output_bsp_when (), sep); - add_unwind_entry (output_bsp_gr (reg2), NOT_A_CHAR); - break; - case REG_AR + AR_BSPSTORE: - add_unwind_entry (output_bspstore_when (), sep); - add_unwind_entry (output_bspstore_gr (reg2), NOT_A_CHAR); - break; - case REG_AR + AR_RNAT: - add_unwind_entry (output_rnat_when (), sep); - add_unwind_entry (output_rnat_gr (reg2), NOT_A_CHAR); - break; - case REG_AR + AR_UNAT: - add_unwind_entry (output_unat_when (), sep); - add_unwind_entry (output_unat_gr (reg2), NOT_A_CHAR); - break; - case REG_AR + AR_FPSR: - add_unwind_entry (output_fpsr_when (), sep); - add_unwind_entry (output_fpsr_gr (reg2), NOT_A_CHAR); - break; - case REG_AR + AR_PFS: - add_unwind_entry (output_pfs_when (), sep); - if (! (unwind.prologue_mask & 4)) - add_unwind_entry (output_pfs_gr (reg2), NOT_A_CHAR); - else if (reg2 !=3D unwind.prologue_gr - + (unsigned) popcount (unwind.prologue_mask & -(4 << 1))) - as_warn (_("Second operand of .save contradicts .prologue")); - break; - case REG_AR + AR_LC: - add_unwind_entry (output_lc_when (), sep); - add_unwind_entry (output_lc_gr (reg2), NOT_A_CHAR); - break; - case REG_BR: - add_unwind_entry (output_rp_when (), sep); - if (! (unwind.prologue_mask & 8)) - add_unwind_entry (output_rp_gr (reg2), NOT_A_CHAR); - else if (reg2 !=3D unwind.prologue_gr) - as_warn (_("Second operand of .save contradicts .prologue")); - break; - case REG_PR: - add_unwind_entry (output_preds_when (), sep); - if (! (unwind.prologue_mask & 1)) - add_unwind_entry (output_preds_gr (reg2), NOT_A_CHAR); - else if (reg2 !=3D unwind.prologue_gr - + (unsigned) popcount (unwind.prologue_mask & -(1 << 1))) - as_warn (_("Second operand of .save contradicts .prologue")); - break; - case REG_PRIUNAT: - add_unwind_entry (output_priunat_when_gr (), sep); - add_unwind_entry (output_priunat_gr (reg2), NOT_A_CHAR); - break; - default: - as_bad (_("First operand to .save not a valid register")); - add_unwind_entry (NULL, sep); - break; - } -} - -static void -dot_restore (int dummy ATTRIBUTE_UNUSED) -{ - expressionS e1; - unsigned long ecount; /* # of _additional_ regions to pop */ - int sep; - - if (!in_body ("restore")) - return; - - sep =3D parse_operand_and_eval (&e1, ','); - if (e1.X_op !=3D O_register || e1.X_add_number !=3D REG_GR + 12) - as_bad (_("First operand to .restore must be stack pointer (sp)")); - - if (sep =3D=3D ',') - { - expressionS e2; - - sep =3D parse_operand_and_eval (&e2, ','); - if (e2.X_op !=3D O_constant || e2.X_add_number < 0) - { - as_bad (_("Second operand to .restore must be a constant >=3D 0")); - e2.X_add_number =3D 0; - } - ecount =3D e2.X_add_number; - } - else - ecount =3D unwind.prologue_count - 1; - - if (ecount >=3D unwind.prologue_count) - { - as_bad (_("Epilogue count of %lu exceeds number of nested prologues = (%u)"), - ecount + 1, unwind.prologue_count); - ecount =3D 0; - } - - add_unwind_entry (output_epilogue (ecount), sep); - - if (ecount < unwind.prologue_count) - unwind.prologue_count -=3D ecount + 1; - else - unwind.prologue_count =3D 0; -} - -static void -dot_restorereg (int pred) -{ - unsigned int qp, ab, reg; - expressionS e; - int sep; - const char * const po =3D pred ? "restorereg.p" : "restorereg"; - - if (!in_procedure (po)) - return; - - if (pred) - sep =3D parse_predicate_and_operand (&e, &qp, po); - else - { - sep =3D parse_operand_and_eval (&e, ','); - qp =3D 0; - } - convert_expr_to_ab_reg (&e, &ab, ®, po, 1 + pred); - - add_unwind_entry (output_spill_reg (ab, reg, 0, 0, qp), sep); -} - -static const char *special_linkonce_name[] =3D - { - ".gnu.linkonce.ia64unw.", ".gnu.linkonce.ia64unwi." - }; - -static void -start_unwind_section (const segT text_seg, int sec_index) -{ - /* - Use a slightly ugly scheme to derive the unwind section names from - the text section name: - - text sect. unwind table sect. - name: name: comments: - ---------- ----------------- -------------------------------- - .text .IA_64.unwind - .text.foo .IA_64.unwind.text.foo - .foo .IA_64.unwind.foo - .gnu.linkonce.t.foo - .gnu.linkonce.ia64unw.foo - _info .IA_64.unwind_info gas issues error message (ditto) - _infoFOO .IA_64.unwind_infoFOO gas issues error message (ditto) - - This mapping is done so that: - - (a) An object file with unwind info only in .text will use - unwind section names .IA_64.unwind and .IA_64.unwind_info. - This follows the letter of the ABI and also ensures backwards - compatibility with older toolchains. - - (b) An object file with unwind info in multiple text sections - will use separate unwind sections for each text section. - This allows us to properly set the "sh_info" and "sh_link" - fields in SHT_IA_64_UNWIND as required by the ABI and also - lets GNU ld support programs with multiple segments - containing unwind info (as might be the case for certain - embedded applications). - - (c) An error is issued if there would be a name clash. - */ - - const char *text_name, *sec_text_name; - char *sec_name; - const char *prefix =3D special_section_name [sec_index]; - const char *suffix; - - sec_text_name =3D segment_name (text_seg); - text_name =3D sec_text_name; - if (startswith (text_name, "_info")) - { - as_bad (_("Illegal section name `%s' (causes unwind section name cla= sh)"), - text_name); - ignore_rest_of_line (); - return; - } - if (strcmp (text_name, ".text") =3D=3D 0) - text_name =3D ""; - - /* Build the unwind section name by appending the (possibly stripped) - text section name to the unwind prefix. */ - suffix =3D text_name; - if (startswith (text_name, ".gnu.linkonce.t.")) - { - prefix =3D special_linkonce_name [sec_index - SPECIAL_SECTION_UNWIND= ]; - suffix +=3D sizeof (".gnu.linkonce.t.") - 1; - } - - sec_name =3D concat (prefix, suffix, NULL); - - /* Handle COMDAT group. */ - if ((text_seg->flags & SEC_LINK_ONCE) !=3D 0 - && (elf_section_flags (text_seg) & SHF_GROUP) !=3D 0) - { - char *section; - const char *group_name =3D elf_group_name (text_seg); - - if (group_name =3D=3D NULL) - { - as_bad (_("Group section `%s' has no group signature"), - sec_text_name); - ignore_rest_of_line (); - free (sec_name); - return; - } - - /* We have to construct a fake section directive. */ - section =3D concat (sec_name, ",\"aG\",@progbits,", group_name, ",co= mdat", NULL); - set_section (section); - free (section); - } - else - { - set_section (sec_name); - bfd_set_section_flags (now_seg, SEC_LOAD | SEC_ALLOC | SEC_READONLY); - } - - elf_linked_to_section (now_seg) =3D text_seg; - free (sec_name); -} - -static void -generate_unwind_image (const segT text_seg) -{ - int size, pad; - unw_rec_list *list; - - /* Mark the end of the unwind info, so that we can compute the size of t= he - last unwind region. */ - add_unwind_entry (output_endp (), NOT_A_CHAR); - - /* Force out pending instructions, to make sure all unwind records have - a valid slot_number field. */ - ia64_flush_insns (); - - /* Generate the unwind record. */ - list =3D optimize_unw_records (unwind.list); - fixup_unw_records (list, 1); - size =3D calc_record_size (list); - - if (size > 0 || unwind.force_unwind_entry) - { - unwind.force_unwind_entry =3D 0; - /* pad to pointer-size boundary. */ - pad =3D size % md.pointer_size; - if (pad !=3D 0) - size +=3D md.pointer_size - pad; - /* Add 8 for the header. */ - size +=3D 8; - /* Add a pointer for the personality offset. */ - if (unwind.personality_routine) - size +=3D md.pointer_size; - } - - /* If there are unwind records, switch sections, and output the info. */ - if (size !=3D 0) - { - expressionS exp; - bfd_reloc_code_real_type reloc; - - start_unwind_section (text_seg, SPECIAL_SECTION_UNWIND_INFO); - - /* Make sure the section has 4 byte alignment for ILP32 and - 8 byte alignment for LP64. */ - frag_align (md.pointer_size_shift, 0, 0); - record_alignment (now_seg, md.pointer_size_shift); - - /* Set expression which points to start of unwind descriptor area. = */ - unwind.info =3D expr_build_dot (); - - frag_var (rs_machine_dependent, size, size, 0, 0, - (offsetT) (long) unwind.personality_routine, - (char *) list); - - /* Add the personality address to the image. */ - if (unwind.personality_routine !=3D 0) - { - exp.X_op =3D O_symbol; - exp.X_add_symbol =3D unwind.personality_routine; - exp.X_add_number =3D 0; - - if (md.flags & EF_IA_64_BE) - { - if (md.flags & EF_IA_64_ABI64) - reloc =3D BFD_RELOC_IA64_LTOFF_FPTR64MSB; - else - reloc =3D BFD_RELOC_IA64_LTOFF_FPTR32MSB; - } - else - { - if (md.flags & EF_IA_64_ABI64) - reloc =3D BFD_RELOC_IA64_LTOFF_FPTR64LSB; - else - reloc =3D BFD_RELOC_IA64_LTOFF_FPTR32LSB; - } - - fix_new_exp (frag_now, frag_now_fix () - md.pointer_size, - md.pointer_size, &exp, 0, reloc); - unwind.personality_routine =3D 0; - } - } - - free_saved_prologue_counts (); - unwind.list =3D unwind.tail =3D unwind.current_entry =3D NULL; -} - -static void -dot_handlerdata (int dummy ATTRIBUTE_UNUSED) -{ - if (!in_procedure ("handlerdata")) - return; - unwind.force_unwind_entry =3D 1; - - /* Remember which segment we're in so we can switch back after .endp */ - unwind.saved_text_seg =3D now_seg; - unwind.saved_text_subseg =3D now_subseg; - - /* Generate unwind info into unwind-info section and then leave that - section as the currently active one so dataXX directives go into - the language specific data area of the unwind info block. */ - generate_unwind_image (now_seg); - demand_empty_rest_of_line (); -} - -static void -dot_unwentry (int dummy ATTRIBUTE_UNUSED) -{ - if (!in_procedure ("unwentry")) - return; - unwind.force_unwind_entry =3D 1; - demand_empty_rest_of_line (); -} - -static void -dot_altrp (int dummy ATTRIBUTE_UNUSED) -{ - expressionS e; - unsigned reg; - - if (!in_prologue ("altrp")) - return; - - parse_operand_and_eval (&e, 0); - reg =3D e.X_add_number - REG_BR; - if (e.X_op !=3D O_register || reg > 7) - { - as_bad (_("First operand to .altrp not a valid branch register")); - reg =3D 0; - } - add_unwind_entry (output_rp_br (reg), 0); -} - -static void -dot_savemem (int psprel) -{ - expressionS e1, e2; - int sep; - int reg1, val; - const char * const po =3D psprel ? "savepsp" : "savesp"; - - if (!in_prologue (po)) - return; - - sep =3D parse_operand_and_eval (&e1, ','); - if (sep =3D=3D ',') - sep =3D parse_operand_and_eval (&e2, ','); - else - e2.X_op =3D O_absent; - - reg1 =3D e1.X_add_number; - val =3D e2.X_add_number; - - /* Make sure it's a valid ar.xxx reg, OR its br0, aka 'rp'. */ - if (e1.X_op !=3D O_register) - { - as_bad (_("First operand to .%s not a register"), po); - reg1 =3D REG_PR; /* Anything valid is good here. */ - } - if (e2.X_op !=3D O_constant) - { - as_bad (_("Second operand to .%s not a constant"), po); - val =3D 0; - } - - switch (reg1) - { - case REG_AR + AR_BSP: - add_unwind_entry (output_bsp_when (), sep); - add_unwind_entry ((psprel - ? output_bsp_psprel - : output_bsp_sprel) (val), NOT_A_CHAR); - break; - case REG_AR + AR_BSPSTORE: - add_unwind_entry (output_bspstore_when (), sep); - add_unwind_entry ((psprel - ? output_bspstore_psprel - : output_bspstore_sprel) (val), NOT_A_CHAR); - break; - case REG_AR + AR_RNAT: - add_unwind_entry (output_rnat_when (), sep); - add_unwind_entry ((psprel - ? output_rnat_psprel - : output_rnat_sprel) (val), NOT_A_CHAR); - break; - case REG_AR + AR_UNAT: - add_unwind_entry (output_unat_when (), sep); - add_unwind_entry ((psprel - ? output_unat_psprel - : output_unat_sprel) (val), NOT_A_CHAR); - break; - case REG_AR + AR_FPSR: - add_unwind_entry (output_fpsr_when (), sep); - add_unwind_entry ((psprel - ? output_fpsr_psprel - : output_fpsr_sprel) (val), NOT_A_CHAR); - break; - case REG_AR + AR_PFS: - add_unwind_entry (output_pfs_when (), sep); - add_unwind_entry ((psprel - ? output_pfs_psprel - : output_pfs_sprel) (val), NOT_A_CHAR); - break; - case REG_AR + AR_LC: - add_unwind_entry (output_lc_when (), sep); - add_unwind_entry ((psprel - ? output_lc_psprel - : output_lc_sprel) (val), NOT_A_CHAR); - break; - case REG_BR: - add_unwind_entry (output_rp_when (), sep); - add_unwind_entry ((psprel - ? output_rp_psprel - : output_rp_sprel) (val), NOT_A_CHAR); - break; - case REG_PR: - add_unwind_entry (output_preds_when (), sep); - add_unwind_entry ((psprel - ? output_preds_psprel - : output_preds_sprel) (val), NOT_A_CHAR); - break; - case REG_PRIUNAT: - add_unwind_entry (output_priunat_when_mem (), sep); - add_unwind_entry ((psprel - ? output_priunat_psprel - : output_priunat_sprel) (val), NOT_A_CHAR); - break; - default: - as_bad (_("First operand to .%s not a valid register"), po); - add_unwind_entry (NULL, sep); - break; - } -} - -static void -dot_saveg (int dummy ATTRIBUTE_UNUSED) -{ - expressionS e; - unsigned grmask; - int sep; - - if (!in_prologue ("save.g")) - return; - - sep =3D parse_operand_and_eval (&e, ','); - - grmask =3D e.X_add_number; - if (e.X_op !=3D O_constant - || e.X_add_number <=3D 0 - || e.X_add_number > 0xf) - { - as_bad (_("First operand to .save.g must be a positive 4-bit constan= t")); - grmask =3D 0; - } - - if (sep =3D=3D ',') - { - unsigned reg; - int n =3D popcount (grmask); - - parse_operand_and_eval (&e, 0); - reg =3D e.X_add_number - REG_GR; - if (e.X_op !=3D O_register || reg > 127) - { - as_bad (_("Second operand to .save.g must be a general register")); - reg =3D 0; - } - else if (reg > 128U - n) - { - as_bad (_("Second operand to .save.g must be the first of %d general re= gisters"), n); - reg =3D 0; - } - add_unwind_entry (output_gr_gr (grmask, reg), 0); - } - else - add_unwind_entry (output_gr_mem (grmask), 0); -} - -static void -dot_savef (int dummy ATTRIBUTE_UNUSED) -{ - expressionS e; - - if (!in_prologue ("save.f")) - return; - - parse_operand_and_eval (&e, 0); - - if (e.X_op !=3D O_constant - || e.X_add_number <=3D 0 - || e.X_add_number > 0xfffff) - { - as_bad (_("Operand to .save.f must be a positive 20-bit constant")); - e.X_add_number =3D 0; - } - add_unwind_entry (output_fr_mem (e.X_add_number), 0); -} - -static void -dot_saveb (int dummy ATTRIBUTE_UNUSED) -{ - expressionS e; - unsigned brmask; - int sep; - - if (!in_prologue ("save.b")) - return; - - sep =3D parse_operand_and_eval (&e, ','); - - brmask =3D e.X_add_number; - if (e.X_op !=3D O_constant - || e.X_add_number <=3D 0 - || e.X_add_number > 0x1f) - { - as_bad (_("First operand to .save.b must be a positive 5-bit constan= t")); - brmask =3D 0; - } - - if (sep =3D=3D ',') - { - unsigned reg; - int n =3D popcount (brmask); - - parse_operand_and_eval (&e, 0); - reg =3D e.X_add_number - REG_GR; - if (e.X_op !=3D O_register || reg > 127) - { - as_bad (_("Second operand to .save.b must be a general register")); - reg =3D 0; - } - else if (reg > 128U - n) - { - as_bad (_("Second operand to .save.b must be the first of %d general re= gisters"), n); - reg =3D 0; - } - add_unwind_entry (output_br_gr (brmask, reg), 0); - } - else - add_unwind_entry (output_br_mem (brmask), 0); -} - -static void -dot_savegf (int dummy ATTRIBUTE_UNUSED) -{ - expressionS e1, e2; - - if (!in_prologue ("save.gf")) - return; - - if (parse_operand_and_eval (&e1, ',') =3D=3D ',') - parse_operand_and_eval (&e2, 0); - else - e2.X_op =3D O_absent; - - if (e1.X_op !=3D O_constant - || e1.X_add_number < 0 - || e1.X_add_number > 0xf) - { - as_bad (_("First operand to .save.gf must be a non-negative 4-bit co= nstant")); - e1.X_op =3D O_absent; - e1.X_add_number =3D 0; - } - if (e2.X_op !=3D O_constant - || e2.X_add_number < 0 - || e2.X_add_number > 0xfffff) - { - as_bad (_("Second operand to .save.gf must be a non-negative 20-bit = constant")); - e2.X_op =3D O_absent; - e2.X_add_number =3D 0; - } - if (e1.X_op =3D=3D O_constant - && e2.X_op =3D=3D O_constant - && e1.X_add_number =3D=3D 0 - && e2.X_add_number =3D=3D 0) - as_bad (_("Operands to .save.gf may not be both zero")); - - add_unwind_entry (output_frgr_mem (e1.X_add_number, e2.X_add_number), 0); -} - -static void -dot_spill (int dummy ATTRIBUTE_UNUSED) -{ - expressionS e; - - if (!in_prologue ("spill")) - return; - - parse_operand_and_eval (&e, 0); - - if (e.X_op !=3D O_constant) - { - as_bad (_("Operand to .spill must be a constant")); - e.X_add_number =3D 0; - } - add_unwind_entry (output_spill_base (e.X_add_number), 0); -} - -static void -dot_spillreg (int pred) -{ - int sep; - unsigned int qp, ab, xy, reg, treg; - expressionS e; - const char * const po =3D pred ? "spillreg.p" : "spillreg"; - - if (!in_procedure (po)) - return; - - if (pred) - sep =3D parse_predicate_and_operand (&e, &qp, po); - else - { - sep =3D parse_operand_and_eval (&e, ','); - qp =3D 0; - } - convert_expr_to_ab_reg (&e, &ab, ®, po, 1 + pred); - - if (sep =3D=3D ',') - sep =3D parse_operand_and_eval (&e, ','); - else - e.X_op =3D O_absent; - convert_expr_to_xy_reg (&e, &xy, &treg, po, 2 + pred); - - add_unwind_entry (output_spill_reg (ab, reg, treg, xy, qp), sep); -} - -static void -dot_spillmem (int psprel) -{ - expressionS e; - int pred =3D (psprel < 0), sep; - unsigned int qp, ab, reg; - const char * po; - - if (pred) - { - psprel =3D ~psprel; - po =3D psprel ? "spillpsp.p" : "spillsp.p"; - } - else - po =3D psprel ? "spillpsp" : "spillsp"; - - if (!in_procedure (po)) - return; - - if (pred) - sep =3D parse_predicate_and_operand (&e, &qp, po); - else - { - sep =3D parse_operand_and_eval (&e, ','); - qp =3D 0; - } - convert_expr_to_ab_reg (&e, &ab, ®, po, 1 + pred); - - if (sep =3D=3D ',') - sep =3D parse_operand_and_eval (&e, ','); - else - e.X_op =3D O_absent; - if (e.X_op !=3D O_constant) - { - as_bad (_("Operand %d to .%s must be a constant"), 2 + pred, po); - e.X_add_number =3D 0; - } - - if (psprel) - add_unwind_entry (output_spill_psprel (ab, reg, e.X_add_number, qp), s= ep); - else - add_unwind_entry (output_spill_sprel (ab, reg, e.X_add_number, qp), se= p); -} - -static unsigned int -get_saved_prologue_count (unsigned long lbl) -{ - label_prologue_count *lpc =3D unwind.saved_prologue_counts; - - while (lpc !=3D NULL && lpc->label_number !=3D lbl) - lpc =3D lpc->next; - - if (lpc !=3D NULL) - return lpc->prologue_count; - - as_bad (_("Missing .label_state %ld"), lbl); - return 1; -} - -static void -save_prologue_count (unsigned long lbl, unsigned int count) -{ - label_prologue_count *lpc =3D unwind.saved_prologue_counts; - - while (lpc !=3D NULL && lpc->label_number !=3D lbl) - lpc =3D lpc->next; - - if (lpc !=3D NULL) - lpc->prologue_count =3D count; - else - { - label_prologue_count *new_lpc =3D XNEW (label_prologue_count); - - new_lpc->next =3D unwind.saved_prologue_counts; - new_lpc->label_number =3D lbl; - new_lpc->prologue_count =3D count; - unwind.saved_prologue_counts =3D new_lpc; - } -} - -static void -free_saved_prologue_counts (void) -{ - label_prologue_count *lpc =3D unwind.saved_prologue_counts; - label_prologue_count *next; - - while (lpc !=3D NULL) - { - next =3D lpc->next; - free (lpc); - lpc =3D next; - } - - unwind.saved_prologue_counts =3D NULL; -} - -static void -dot_label_state (int dummy ATTRIBUTE_UNUSED) -{ - expressionS e; - - if (!in_body ("label_state")) - return; - - parse_operand_and_eval (&e, 0); - if (e.X_op =3D=3D O_constant) - save_prologue_count (e.X_add_number, unwind.prologue_count); - else - { - as_bad (_("Operand to .label_state must be a constant")); - e.X_add_number =3D 0; - } - add_unwind_entry (output_label_state (e.X_add_number), 0); -} - -static void -dot_copy_state (int dummy ATTRIBUTE_UNUSED) -{ - expressionS e; - - if (!in_body ("copy_state")) - return; - - parse_operand_and_eval (&e, 0); - if (e.X_op =3D=3D O_constant) - unwind.prologue_count =3D get_saved_prologue_count (e.X_add_number); - else - { - as_bad (_("Operand to .copy_state must be a constant")); - e.X_add_number =3D 0; - } - add_unwind_entry (output_copy_state (e.X_add_number), 0); -} - -static void -dot_unwabi (int dummy ATTRIBUTE_UNUSED) -{ - expressionS e1, e2; - unsigned char sep; - - if (!in_prologue ("unwabi")) - return; - - sep =3D parse_operand_and_eval (&e1, ','); - if (sep =3D=3D ',') - parse_operand_and_eval (&e2, 0); - else - e2.X_op =3D O_absent; - - if (e1.X_op !=3D O_constant) - { - as_bad (_("First operand to .unwabi must be a constant")); - e1.X_add_number =3D 0; - } - - if (e2.X_op !=3D O_constant) - { - as_bad (_("Second operand to .unwabi must be a constant")); - e2.X_add_number =3D 0; - } - - add_unwind_entry (output_unwabi (e1.X_add_number, e2.X_add_number), 0); -} - -static void -dot_personality (int dummy ATTRIBUTE_UNUSED) -{ - char *name, *p, c; - - if (!in_procedure ("personality")) - return; - SKIP_WHITESPACE (); - c =3D get_symbol_name (&name); - p =3D input_line_pointer; - unwind.personality_routine =3D symbol_find_or_make (name); - unwind.force_unwind_entry =3D 1; - *p =3D c; - SKIP_WHITESPACE_AFTER_NAME (); - demand_empty_rest_of_line (); -} - -static void -dot_proc (int dummy ATTRIBUTE_UNUSED) -{ - char *name, *p, c; - symbolS *sym; - proc_pending *pending, *last_pending; - - if (unwind.proc_pending.sym) - { - (md.unwind_check =3D=3D unwind_check_warning - ? as_warn - : as_bad) (_("Missing .endp after previous .proc")); - while (unwind.proc_pending.next) - { - pending =3D unwind.proc_pending.next; - unwind.proc_pending.next =3D pending->next; - free (pending); - } - } - last_pending =3D NULL; - - /* Parse names of main and alternate entry points and mark them as - function symbols: */ - while (1) - { - SKIP_WHITESPACE (); - c =3D get_symbol_name (&name); - p =3D input_line_pointer; - if (!*name) - as_bad (_("Empty argument of .proc")); - else - { - sym =3D symbol_find_or_make (name); - if (S_IS_DEFINED (sym)) - as_bad (_("`%s' was already defined"), name); - else if (!last_pending) - { - unwind.proc_pending.sym =3D sym; - last_pending =3D &unwind.proc_pending; - } - else - { - pending =3D XNEW (proc_pending); - pending->sym =3D sym; - last_pending =3D last_pending->next =3D pending; - } - symbol_get_bfdsym (sym)->flags |=3D BSF_FUNCTION; - } - *p =3D c; - SKIP_WHITESPACE_AFTER_NAME (); - if (*input_line_pointer !=3D ',') - break; - ++input_line_pointer; - } - if (!last_pending) - { - unwind.proc_pending.sym =3D expr_build_dot (); - last_pending =3D &unwind.proc_pending; - } - last_pending->next =3D NULL; - demand_empty_rest_of_line (); - do_align (4, NULL, 0, 0); - - unwind.prologue =3D 0; - unwind.prologue_count =3D 0; - unwind.body =3D 0; - unwind.insn =3D 0; - unwind.list =3D unwind.tail =3D unwind.current_entry =3D NULL; - unwind.personality_routine =3D 0; -} - -static void -dot_body (int dummy ATTRIBUTE_UNUSED) -{ - if (!in_procedure ("body")) - return; - if (!unwind.prologue && !unwind.body && unwind.insn) - as_warn (_("Initial .body should precede any instructions")); - check_pending_save (); - - unwind.prologue =3D 0; - unwind.prologue_mask =3D 0; - unwind.body =3D 1; - - add_unwind_entry (output_body (), 0); -} - -static void -dot_prologue (int dummy ATTRIBUTE_UNUSED) -{ - unsigned mask =3D 0, grsave =3D 0; - - if (!in_procedure ("prologue")) - return; - if (unwind.prologue) - { - as_bad (_(".prologue within prologue")); - ignore_rest_of_line (); - return; - } - if (!unwind.body && unwind.insn) - as_warn (_("Initial .prologue should precede any instructions")); - - if (!is_it_end_of_statement ()) - { - expressionS e; - int n, sep =3D parse_operand_and_eval (&e, ','); - - if (e.X_op !=3D O_constant - || e.X_add_number < 0 - || e.X_add_number > 0xf) - as_bad (_("First operand to .prologue must be a positive 4-bit constant")= ); - else if (e.X_add_number =3D=3D 0) - as_warn (_("Pointless use of zero first operand to .prologue")); - else - mask =3D e.X_add_number; - - n =3D popcount (mask); - - if (sep =3D=3D ',') - parse_operand_and_eval (&e, 0); - else - e.X_op =3D O_absent; - - if (e.X_op =3D=3D O_constant - && e.X_add_number >=3D 0 - && e.X_add_number < 128) - { - if (md.unwind_check =3D=3D unwind_check_error) - as_warn (_("Using a constant as second operand to .prologue is deprec= ated")); - grsave =3D e.X_add_number; - } - else if (e.X_op !=3D O_register - || (grsave =3D e.X_add_number - REG_GR) > 127) - { - as_bad (_("Second operand to .prologue must be a general register")); - grsave =3D 0; - } - else if (grsave > 128U - n) - { - as_bad (_("Second operand to .prologue must be the first of %d general = registers"), n); - grsave =3D 0; - } - } - - if (mask) - add_unwind_entry (output_prologue_gr (mask, grsave), 0); - else - add_unwind_entry (output_prologue (), 0); - - unwind.prologue =3D 1; - unwind.prologue_mask =3D mask; - unwind.prologue_gr =3D grsave; - unwind.body =3D 0; - ++unwind.prologue_count; -} - -static void -dot_endp (int dummy ATTRIBUTE_UNUSED) -{ - expressionS e; - int bytes_per_address; - long where; - segT saved_seg; - subsegT saved_subseg; - proc_pending *pending; - int unwind_check =3D md.unwind_check; - - md.unwind_check =3D unwind_check_error; - if (!in_procedure ("endp")) - return; - md.unwind_check =3D unwind_check; - - if (unwind.saved_text_seg) - { - saved_seg =3D unwind.saved_text_seg; - saved_subseg =3D unwind.saved_text_subseg; - unwind.saved_text_seg =3D NULL; - } - else - { - saved_seg =3D now_seg; - saved_subseg =3D now_subseg; - } - - insn_group_break (1, 0, 0); - - /* If there wasn't a .handlerdata, we haven't generated an image yet. */ - if (!unwind.info) - generate_unwind_image (saved_seg); - - if (unwind.info || unwind.force_unwind_entry) - { - symbolS *proc_end; - - subseg_set (md.last_text_seg, md.last_text_subseg); - proc_end =3D expr_build_dot (); - - start_unwind_section (saved_seg, SPECIAL_SECTION_UNWIND); - - /* Make sure that section has 4 byte alignment for ILP32 and - 8 byte alignment for LP64. */ - record_alignment (now_seg, md.pointer_size_shift); - - /* Need space for 3 pointers for procedure start, procedure end, - and unwind info. */ - memset (frag_more (3 * md.pointer_size), 0, 3 * md.pointer_size); - where =3D frag_now_fix () - (3 * md.pointer_size); - bytes_per_address =3D bfd_arch_bits_per_address (stdoutput) / 8; - - /* Issue the values of a) Proc Begin, b) Proc End, c) Unwind Record= . */ - e.X_op =3D O_pseudo_fixup; - e.X_op_symbol =3D pseudo_func[FUNC_SEG_RELATIVE].u.sym; - e.X_add_number =3D 0; - if (!S_IS_LOCAL (unwind.proc_pending.sym) - && S_IS_DEFINED (unwind.proc_pending.sym)) - e.X_add_symbol - =3D symbol_temp_new (S_GET_SEGMENT (unwind.proc_pending.sym), - symbol_get_frag (unwind.proc_pending.sym), - S_GET_VALUE (unwind.proc_pending.sym)); - else - e.X_add_symbol =3D unwind.proc_pending.sym; - ia64_cons_fix_new (frag_now, where, bytes_per_address, &e, - BFD_RELOC_NONE); - - e.X_op =3D O_pseudo_fixup; - e.X_op_symbol =3D pseudo_func[FUNC_SEG_RELATIVE].u.sym; - e.X_add_number =3D 0; - e.X_add_symbol =3D proc_end; - ia64_cons_fix_new (frag_now, where + bytes_per_address, - bytes_per_address, &e, BFD_RELOC_NONE); - - if (unwind.info) - { - e.X_op =3D O_pseudo_fixup; - e.X_op_symbol =3D pseudo_func[FUNC_SEG_RELATIVE].u.sym; - e.X_add_number =3D 0; - e.X_add_symbol =3D unwind.info; - ia64_cons_fix_new (frag_now, where + (bytes_per_address * 2), - bytes_per_address, &e, BFD_RELOC_NONE); - } - } - subseg_set (saved_seg, saved_subseg); - - /* Set symbol sizes. */ - pending =3D &unwind.proc_pending; - if (S_GET_NAME (pending->sym)) - { - do - { - symbolS *sym =3D pending->sym; - - if (!S_IS_DEFINED (sym)) - as_bad (_("`%s' was not defined within procedure"), S_GET_NAME (sym)); - else if (S_GET_SIZE (sym) =3D=3D 0 - && symbol_get_obj (sym)->size =3D=3D NULL) - { - fragS *frag =3D symbol_get_frag (sym); - - if (frag) - { - if (frag =3D=3D frag_now && SEG_NORMAL (now_seg)) - S_SET_SIZE (sym, frag_now_fix () - S_GET_VALUE (sym)); - else - { - symbol_get_obj (sym)->size =3D XNEW (expressionS); - symbol_get_obj (sym)->size->X_op =3D O_subtract; - symbol_get_obj (sym)->size->X_add_symbol - =3D symbol_new (FAKE_LABEL_NAME, now_seg, - frag_now, frag_now_fix ()); - symbol_get_obj (sym)->size->X_op_symbol =3D sym; - symbol_get_obj (sym)->size->X_add_number =3D 0; - } - } - } - } while ((pending =3D pending->next) !=3D NULL); - } - - /* Parse names of main and alternate entry points. */ - while (1) - { - char *name, *p, c; - - SKIP_WHITESPACE (); - c =3D get_symbol_name (&name); - p =3D input_line_pointer; - if (!*name) - (md.unwind_check =3D=3D unwind_check_warning - ? as_warn - : as_bad) (_("Empty argument of .endp")); - else - { - symbolS *sym =3D symbol_find (name); - - for (pending =3D &unwind.proc_pending; pending; pending =3D pending->ne= xt) - { - if (sym =3D=3D pending->sym) - { - pending->sym =3D NULL; - break; - } - } - if (!sym || !pending) - as_warn (_("`%s' was not specified with previous .proc"), name); - } - *p =3D c; - SKIP_WHITESPACE_AFTER_NAME (); - if (*input_line_pointer !=3D ',') - break; - ++input_line_pointer; - } - demand_empty_rest_of_line (); - - /* Deliberately only checking for the main entry point here; the - language spec even says all arguments to .endp are ignored. */ - if (unwind.proc_pending.sym - && S_GET_NAME (unwind.proc_pending.sym) - && strcmp (S_GET_NAME (unwind.proc_pending.sym), FAKE_LABEL_NAME)) - as_warn (_("`%s' should be an operand to this .endp"), - S_GET_NAME (unwind.proc_pending.sym)); - while (unwind.proc_pending.next) - { - pending =3D unwind.proc_pending.next; - unwind.proc_pending.next =3D pending->next; - free (pending); - } - unwind.proc_pending.sym =3D unwind.info =3D NULL; -} - -static void -dot_template (int template_val) -{ - CURR_SLOT.user_template =3D template_val; -} - -static void -dot_regstk (int dummy ATTRIBUTE_UNUSED) -{ - int ins, locs, outs, rots; - - if (is_it_end_of_statement ()) - ins =3D locs =3D outs =3D rots =3D 0; - else - { - ins =3D get_absolute_expression (); - if (*input_line_pointer++ !=3D ',') - goto err; - locs =3D get_absolute_expression (); - if (*input_line_pointer++ !=3D ',') - goto err; - outs =3D get_absolute_expression (); - if (*input_line_pointer++ !=3D ',') - goto err; - rots =3D get_absolute_expression (); - } - set_regstack (ins, locs, outs, rots); - return; - - err: - as_bad (_("Comma expected")); - ignore_rest_of_line (); -} - -static void -dot_rot (int type) -{ - offsetT num_regs; - valueT num_alloced =3D 0; - struct dynreg **drpp, *dr; - int ch, base_reg =3D 0; - char *name, *start; - size_t len; - - switch (type) - { - case DYNREG_GR: base_reg =3D REG_GR + 32; break; - case DYNREG_FR: base_reg =3D REG_FR + 32; break; - case DYNREG_PR: base_reg =3D REG_P + 16; break; - default: break; - } - - /* First, remove existing names from hash table. */ - for (dr =3D md.dynreg[type]; dr && dr->num_regs; dr =3D dr->next) - { - str_hash_delete (md.dynreg_hash, dr->name); - /* FIXME: Free dr->name. */ - dr->num_regs =3D 0; - } - - drpp =3D &md.dynreg[type]; - while (1) - { - ch =3D get_symbol_name (&start); - len =3D strlen (ia64_canonicalize_symbol_name (start)); - *input_line_pointer =3D ch; - - SKIP_WHITESPACE_AFTER_NAME (); - if (*input_line_pointer !=3D '[') - { - as_bad (_("Expected '['")); - goto err; - } - ++input_line_pointer; /* skip '[' */ - - num_regs =3D get_absolute_expression (); - - if (*input_line_pointer++ !=3D ']') - { - as_bad (_("Expected ']'")); - goto err; - } - if (num_regs <=3D 0) - { - as_bad (_("Number of elements must be positive")); - goto err; - } - SKIP_WHITESPACE (); - - num_alloced +=3D num_regs; - switch (type) - { - case DYNREG_GR: - if (num_alloced > md.rot.num_regs) - { - as_bad (_("Used more than the declared %d rotating registers"), - md.rot.num_regs); - goto err; - } - break; - case DYNREG_FR: - if (num_alloced > 96) - { - as_bad (_("Used more than the available 96 rotating registers")); - goto err; - } - break; - case DYNREG_PR: - if (num_alloced > 48) - { - as_bad (_("Used more than the available 48 rotating registers")); - goto err; - } - break; - - default: - break; - } - - if (!*drpp) - *drpp =3D notes_calloc (1, sizeof (**drpp)); - - name =3D notes_memdup (start, len, len + 1); - - dr =3D *drpp; - dr->name =3D name; - dr->num_regs =3D num_regs; - dr->base =3D base_reg; - drpp =3D &dr->next; - base_reg +=3D num_regs; - - if (str_hash_insert (md.dynreg_hash, name, dr, 0) !=3D NULL) - { - as_bad (_("Attempt to redefine register set `%s'"), name); - goto err; - } - - if (*input_line_pointer !=3D ',') - break; - ++input_line_pointer; /* skip comma */ - SKIP_WHITESPACE (); - } - demand_empty_rest_of_line (); - return; - - err: - ignore_rest_of_line (); -} - -static void -dot_byteorder (int byteorder) -{ - segment_info_type *seginfo =3D seg_info (now_seg); - - if (byteorder =3D=3D -1) - { - if (seginfo->tc_segment_info_data.endian =3D=3D 0) - seginfo->tc_segment_info_data.endian =3D default_big_endian ? 1 : 2; - byteorder =3D seginfo->tc_segment_info_data.endian =3D=3D 1; - } - else - seginfo->tc_segment_info_data.endian =3D byteorder ? 1 : 2; - - if (target_big_endian !=3D byteorder) - { - target_big_endian =3D byteorder; - if (target_big_endian) - { - ia64_number_to_chars =3D number_to_chars_bigendian; - ia64_float_to_chars =3D ia64_float_to_chars_bigendian; - } - else - { - ia64_number_to_chars =3D number_to_chars_littleendian; - ia64_float_to_chars =3D ia64_float_to_chars_littleendian; - } - } -} - -static void -dot_psr (int dummy ATTRIBUTE_UNUSED) -{ - char *option; - int ch; - - while (1) - { - ch =3D get_symbol_name (&option); - if (strcmp (option, "lsb") =3D=3D 0) - md.flags &=3D ~EF_IA_64_BE; - else if (strcmp (option, "msb") =3D=3D 0) - md.flags |=3D EF_IA_64_BE; - else if (strcmp (option, "abi32") =3D=3D 0) - md.flags &=3D ~EF_IA_64_ABI64; - else if (strcmp (option, "abi64") =3D=3D 0) - md.flags |=3D EF_IA_64_ABI64; - else - as_bad (_("Unknown psr option `%s'"), option); - *input_line_pointer =3D ch; - - SKIP_WHITESPACE_AFTER_NAME (); - if (*input_line_pointer !=3D ',') - break; - - ++input_line_pointer; - SKIP_WHITESPACE (); - } - demand_empty_rest_of_line (); -} - -static void -dot_ln (int dummy ATTRIBUTE_UNUSED) -{ - new_logical_line (0, get_absolute_expression ()); - demand_empty_rest_of_line (); -} - -static void -cross_section (int ref, void (*builder) (int), int ua) -{ - char *start, *end; - int saved_auto_align; - unsigned int section_count; - const char *name; - - start =3D input_line_pointer; - name =3D obj_elf_section_name (); - if (name =3D=3D NULL) - return; - end =3D input_line_pointer; - if (*input_line_pointer !=3D ',') - { - as_bad (_("Comma expected after section name")); - ignore_rest_of_line (); - return; - } - *end =3D '\0'; - end =3D input_line_pointer + 1; /* skip comma */ - input_line_pointer =3D start; - md.keep_pending_output =3D 1; - section_count =3D bfd_count_sections (stdoutput); - obj_elf_section (0); - if (section_count !=3D bfd_count_sections (stdoutput)) - as_warn (_("Creating sections with .xdataN/.xrealN/.xstringZ is deprec= ated.")); - input_line_pointer =3D end; - saved_auto_align =3D md.auto_align; - if (ua) - md.auto_align =3D 0; - (*builder) (ref); - if (ua) - md.auto_align =3D saved_auto_align; - obj_elf_previous (0); - md.keep_pending_output =3D 0; -} - -static void -dot_xdata (int size) -{ - cross_section (size, cons, 0); -} - -/* Why doesn't float_cons() call md_cons_align() the way cons() does? */ - -static void -stmt_float_cons (int kind) -{ - size_t alignment; - - switch (kind) - { - case 'd': - alignment =3D 3; - break; - - case 'x': - case 'X': - alignment =3D 4; - break; - - case 'f': - default: - alignment =3D 2; - break; - } - do_align (alignment, NULL, 0, 0); - float_cons (kind); -} - -static void -stmt_cons_ua (int size) -{ - int saved_auto_align =3D md.auto_align; - - md.auto_align =3D 0; - cons (size); - md.auto_align =3D saved_auto_align; -} - -static void -dot_xfloat_cons (int kind) -{ - cross_section (kind, stmt_float_cons, 0); -} - -static void -dot_xstringer (int zero) -{ - cross_section (zero, stringer, 0); -} - -static void -dot_xdata_ua (int size) -{ - cross_section (size, cons, 1); -} - -static void -dot_xfloat_cons_ua (int kind) -{ - cross_section (kind, float_cons, 1); -} - -/* .reg.val ,value */ - -static void -dot_reg_val (int dummy ATTRIBUTE_UNUSED) -{ - expressionS reg; - - expression_and_evaluate (®); - if (reg.X_op !=3D O_register) - { - as_bad (_("Register name expected")); - ignore_rest_of_line (); - } - else if (*input_line_pointer++ !=3D ',') - { - as_bad (_("Comma expected")); - ignore_rest_of_line (); - } - else - { - valueT value =3D get_absolute_expression (); - int regno =3D reg.X_add_number; - if (regno <=3D REG_GR || regno > REG_GR + 127) - as_warn (_("Register value annotation ignored")); - else - { - gr_values[regno - REG_GR].known =3D 1; - gr_values[regno - REG_GR].value =3D value; - gr_values[regno - REG_GR].path =3D md.path; - } - } - demand_empty_rest_of_line (); -} - -/* - .serialize.data - .serialize.instruction - */ -static void -dot_serialize (int type) -{ - insn_group_break (0, 0, 0); - if (type) - instruction_serialization (); - else - data_serialization (); - insn_group_break (0, 0, 0); - demand_empty_rest_of_line (); -} - -/* select dv checking mode - .auto - .explicit - .default - - A stop is inserted when changing modes - */ - -static void -dot_dv_mode (int type) -{ - if (md.manual_bundling) - as_warn (_("Directive invalid within a bundle")); - - if (type =3D=3D 'E' || type =3D=3D 'A') - md.mode_explicitly_set =3D 0; - else - md.mode_explicitly_set =3D 1; - - md.detect_dv =3D 1; - switch (type) - { - case 'A': - case 'a': - if (md.explicit_mode) - insn_group_break (1, 0, 0); - md.explicit_mode =3D 0; - break; - case 'E': - case 'e': - if (!md.explicit_mode) - insn_group_break (1, 0, 0); - md.explicit_mode =3D 1; - break; - default: - case 'd': - if (md.explicit_mode !=3D md.default_explicit_mode) - insn_group_break (1, 0, 0); - md.explicit_mode =3D md.default_explicit_mode; - md.mode_explicitly_set =3D 0; - break; - } -} - -static void -print_prmask (valueT mask) -{ - int regno; - const char *comma =3D ""; - for (regno =3D 0; regno < 64; regno++) - { - if (mask & ((valueT) 1 << regno)) - { - fprintf (stderr, "%s p%d", comma, regno); - comma =3D ","; - } - } -} - -/* - .pred.rel.clear [p1 [,p2 [,...]]] (also .pred.rel "clear" or @clear) - .pred.rel.imply p1, p2 (also .pred.rel "imply" or @imply) - .pred.rel.mutex p1, p2 [,...] (also .pred.rel "mutex" or @mutex) - .pred.safe_across_calls p1 [, p2 [,...]] - */ - -static void -dot_pred_rel (int type) -{ - valueT mask =3D 0; - int count =3D 0; - int p1 =3D -1, p2 =3D -1; - - if (type =3D=3D 0) - { - if (*input_line_pointer =3D=3D '"') - { - int len; - char *form =3D demand_copy_C_string (&len); - - if (strcmp (form, "mutex") =3D=3D 0) - type =3D 'm'; - else if (strcmp (form, "clear") =3D=3D 0) - type =3D 'c'; - else if (strcmp (form, "imply") =3D=3D 0) - type =3D 'i'; - notes_free (form); - } - else if (*input_line_pointer =3D=3D '@') - { - char *form; - char c; - - ++input_line_pointer; - c =3D get_symbol_name (&form); - - if (strcmp (form, "mutex") =3D=3D 0) - type =3D 'm'; - else if (strcmp (form, "clear") =3D=3D 0) - type =3D 'c'; - else if (strcmp (form, "imply") =3D=3D 0) - type =3D 'i'; - (void) restore_line_pointer (c); - } - else - { - as_bad (_("Missing predicate relation type")); - ignore_rest_of_line (); - return; - } - if (type =3D=3D 0) - { - as_bad (_("Unrecognized predicate relation type")); - ignore_rest_of_line (); - return; - } - if (*input_line_pointer =3D=3D ',') - ++input_line_pointer; - SKIP_WHITESPACE (); - } - - while (1) - { - valueT bits =3D 1; - int sep, regno; - expressionS pr, *pr1, *pr2; - - sep =3D parse_operand_and_eval (&pr, ','); - if (pr.X_op =3D=3D O_register - && pr.X_add_number >=3D REG_P - && pr.X_add_number <=3D REG_P + 63) - { - regno =3D pr.X_add_number - REG_P; - bits <<=3D regno; - count++; - if (p1 =3D=3D -1) - p1 =3D regno; - else if (p2 =3D=3D -1) - p2 =3D regno; - } - else if (type !=3D 'i' - && pr.X_op =3D=3D O_subtract - && (pr1 =3D symbol_get_value_expression (pr.X_add_symbol)) - && pr1->X_op =3D=3D O_register - && pr1->X_add_number >=3D REG_P - && pr1->X_add_number <=3D REG_P + 63 - && (pr2 =3D symbol_get_value_expression (pr.X_op_symbol)) - && pr2->X_op =3D=3D O_register - && pr2->X_add_number >=3D REG_P - && pr2->X_add_number <=3D REG_P + 63) - { - /* It's a range. */ - int stop; - - regno =3D pr1->X_add_number - REG_P; - stop =3D pr2->X_add_number - REG_P; - if (regno >=3D stop) - { - as_bad (_("Bad register range")); - ignore_rest_of_line (); - return; - } - bits =3D ((bits << stop) << 1) - (bits << regno); - count +=3D stop - regno + 1; - } - else - { - as_bad (_("Predicate register expected")); - ignore_rest_of_line (); - return; - } - if (mask & bits) - as_warn (_("Duplicate predicate register ignored")); - mask |=3D bits; - if (sep !=3D ',') - break; - } - - switch (type) - { - case 'c': - if (count =3D=3D 0) - mask =3D ~(valueT) 0; - clear_qp_mutex (mask); - clear_qp_implies (mask, (valueT) 0); - break; - case 'i': - if (count !=3D 2 || p1 =3D=3D -1 || p2 =3D=3D -1) - as_bad (_("Predicate source and target required")); - else if (p1 =3D=3D 0 || p2 =3D=3D 0) - as_bad (_("Use of p0 is not valid in this context")); - else - add_qp_imply (p1, p2); - break; - case 'm': - if (count < 2) - { - as_bad (_("At least two PR arguments expected")); - break; - } - else if (mask & 1) - { - as_bad (_("Use of p0 is not valid in this context")); - break; - } - add_qp_mutex (mask); - break; - case 's': - /* note that we don't override any existing relations */ - if (count =3D=3D 0) - { - as_bad (_("At least one PR argument expected")); - break; - } - if (md.debug_dv) - { - fprintf (stderr, "Safe across calls: "); - print_prmask (mask); - fprintf (stderr, "\n"); - } - qp_safe_across_calls =3D mask; - break; - } - demand_empty_rest_of_line (); -} - -/* .entry label [, label [, ...]] - Hint to DV code that the given labels are to be considered entry points. - Otherwise, only global labels are considered entry points. */ - -static void -dot_entry (int dummy ATTRIBUTE_UNUSED) -{ - char *name; - int c; - symbolS *symbolP; - - do - { - c =3D get_symbol_name (&name); - symbolP =3D symbol_find_or_make (name); - - if (str_hash_insert (md.entry_hash, S_GET_NAME (symbolP), symbolP, 0= )) - as_bad (_("duplicate entry hint %s"), name); - - *input_line_pointer =3D c; - SKIP_WHITESPACE_AFTER_NAME (); - c =3D *input_line_pointer; - if (c =3D=3D ',') - { - input_line_pointer++; - SKIP_WHITESPACE (); - if (*input_line_pointer =3D=3D '\n') - c =3D '\n'; - } - } - while (c =3D=3D ','); - - demand_empty_rest_of_line (); -} - -/* .mem.offset offset, base - "base" is used to distinguish between offsets from a different base. */ - -static void -dot_mem_offset (int dummy ATTRIBUTE_UNUSED) -{ - md.mem_offset.hint =3D 1; - md.mem_offset.offset =3D get_absolute_expression (); - if (*input_line_pointer !=3D ',') - { - as_bad (_("Comma expected")); - ignore_rest_of_line (); - return; - } - ++input_line_pointer; - md.mem_offset.base =3D get_absolute_expression (); - demand_empty_rest_of_line (); -} - -/* ia64-specific pseudo-ops: */ -const pseudo_typeS md_pseudo_table[] =3D - { - { "radix", dot_radix, 0 }, - { "lcomm", s_lcomm_bytes, 1 }, - { "loc", dot_loc, 0 }, - { "sbss", dot_special_section, SPECIAL_SECTION_SBSS }, - { "sdata", dot_special_section, SPECIAL_SECTION_SDATA }, - { "rodata", dot_special_section, SPECIAL_SECTION_RODATA }, - { "comment", dot_special_section, SPECIAL_SECTION_COMMENT }, - { "ia_64.unwind", dot_special_section, SPECIAL_SECTION_UNWIND }, - { "ia_64.unwind_info", dot_special_section, SPECIAL_SECTION_UNWIND_INF= O }, - { "init_array", dot_special_section, SPECIAL_SECTION_INIT_ARRAY }, - { "fini_array", dot_special_section, SPECIAL_SECTION_FINI_ARRAY }, - { "proc", dot_proc, 0 }, - { "body", dot_body, 0 }, - { "prologue", dot_prologue, 0 }, - { "endp", dot_endp, 0 }, - - { "fframe", dot_fframe, 0 }, - { "vframe", dot_vframe, 0 }, - { "vframesp", dot_vframesp, 0 }, - { "vframepsp", dot_vframesp, 1 }, - { "save", dot_save, 0 }, - { "restore", dot_restore, 0 }, - { "restorereg", dot_restorereg, 0 }, - { "restorereg.p", dot_restorereg, 1 }, - { "handlerdata", dot_handlerdata, 0 }, - { "unwentry", dot_unwentry, 0 }, - { "altrp", dot_altrp, 0 }, - { "savesp", dot_savemem, 0 }, - { "savepsp", dot_savemem, 1 }, - { "save.g", dot_saveg, 0 }, - { "save.f", dot_savef, 0 }, - { "save.b", dot_saveb, 0 }, - { "save.gf", dot_savegf, 0 }, - { "spill", dot_spill, 0 }, - { "spillreg", dot_spillreg, 0 }, - { "spillsp", dot_spillmem, 0 }, - { "spillpsp", dot_spillmem, 1 }, - { "spillreg.p", dot_spillreg, 1 }, - { "spillsp.p", dot_spillmem, ~0 }, - { "spillpsp.p", dot_spillmem, ~1 }, - { "label_state", dot_label_state, 0 }, - { "copy_state", dot_copy_state, 0 }, - { "unwabi", dot_unwabi, 0 }, - { "personality", dot_personality, 0 }, - { "mii", dot_template, 0x0 }, - { "mli", dot_template, 0x2 }, /* old format, for compatibility */ - { "mlx", dot_template, 0x2 }, - { "mmi", dot_template, 0x4 }, - { "mfi", dot_template, 0x6 }, - { "mmf", dot_template, 0x7 }, - { "mib", dot_template, 0x8 }, - { "mbb", dot_template, 0x9 }, - { "bbb", dot_template, 0xb }, - { "mmb", dot_template, 0xc }, - { "mfb", dot_template, 0xe }, - { "align", dot_align, 0 }, - { "regstk", dot_regstk, 0 }, - { "rotr", dot_rot, DYNREG_GR }, - { "rotf", dot_rot, DYNREG_FR }, - { "rotp", dot_rot, DYNREG_PR }, - { "lsb", dot_byteorder, 0 }, - { "msb", dot_byteorder, 1 }, - { "psr", dot_psr, 0 }, - { "alias", dot_alias, 0 }, - { "secalias", dot_alias, 1 }, - { "ln", dot_ln, 0 }, /* source line info (for debugging) */ - - { "xdata1", dot_xdata, 1 }, - { "xdata2", dot_xdata, 2 }, - { "xdata4", dot_xdata, 4 }, - { "xdata8", dot_xdata, 8 }, - { "xdata16", dot_xdata, 16 }, - { "xreal4", dot_xfloat_cons, 'f' }, - { "xreal8", dot_xfloat_cons, 'd' }, - { "xreal10", dot_xfloat_cons, 'x' }, - { "xreal16", dot_xfloat_cons, 'X' }, - { "xstring", dot_xstringer, 8 + 0 }, - { "xstringz", dot_xstringer, 8 + 1 }, - - /* unaligned versions: */ - { "xdata2.ua", dot_xdata_ua, 2 }, - { "xdata4.ua", dot_xdata_ua, 4 }, - { "xdata8.ua", dot_xdata_ua, 8 }, - { "xdata16.ua", dot_xdata_ua, 16 }, - { "xreal4.ua", dot_xfloat_cons_ua, 'f' }, - { "xreal8.ua", dot_xfloat_cons_ua, 'd' }, - { "xreal10.ua", dot_xfloat_cons_ua, 'x' }, - { "xreal16.ua", dot_xfloat_cons_ua, 'X' }, - - /* annotations/DV checking support */ - { "entry", dot_entry, 0 }, - { "mem.offset", dot_mem_offset, 0 }, - { "pred.rel", dot_pred_rel, 0 }, - { "pred.rel.clear", dot_pred_rel, 'c' }, - { "pred.rel.imply", dot_pred_rel, 'i' }, - { "pred.rel.mutex", dot_pred_rel, 'm' }, - { "pred.safe_across_calls", dot_pred_rel, 's' }, - { "reg.val", dot_reg_val, 0 }, - { "serialize.data", dot_serialize, 0 }, - { "serialize.instruction", dot_serialize, 1 }, - { "auto", dot_dv_mode, 'a' }, - { "explicit", dot_dv_mode, 'e' }, - { "default", dot_dv_mode, 'd' }, - - /* ??? These are needed to make gas/testsuite/gas/elf/ehopt.s work. - IA-64 aligns data allocation pseudo-ops by default, so we have to - tell it that these ones are supposed to be unaligned. Long term, - should rewrite so that only IA-64 specific data allocation pseudo-o= ps - are aligned by default. */ - {"2byte", stmt_cons_ua, 2}, - {"4byte", stmt_cons_ua, 4}, - {"8byte", stmt_cons_ua, 8}, - -#ifdef TE_VMS - {"vms_common", obj_elf_vms_common, 0}, -#endif - - { NULL, 0, 0 } - }; - -static const struct pseudo_opcode - { - const char *name; - void (*handler) (int); - int arg; - } -pseudo_opcode[] =3D - { - /* these are more like pseudo-ops, but don't start with a dot */ - { "data1", cons, 1 }, - { "data2", cons, 2 }, - { "data4", cons, 4 }, - { "data8", cons, 8 }, - { "data16", cons, 16 }, - { "real4", stmt_float_cons, 'f' }, - { "real8", stmt_float_cons, 'd' }, - { "real10", stmt_float_cons, 'x' }, - { "real16", stmt_float_cons, 'X' }, - { "string", stringer, 8 + 0 }, - { "stringz", stringer, 8 + 1 }, - - /* unaligned versions: */ - { "data2.ua", stmt_cons_ua, 2 }, - { "data4.ua", stmt_cons_ua, 4 }, - { "data8.ua", stmt_cons_ua, 8 }, - { "data16.ua", stmt_cons_ua, 16 }, - { "real4.ua", float_cons, 'f' }, - { "real8.ua", float_cons, 'd' }, - { "real10.ua", float_cons, 'x' }, - { "real16.ua", float_cons, 'X' }, - }; - -/* Declare a register by creating a symbol for it and entering it in - the symbol table. */ - -static symbolS * -declare_register (const char *name, unsigned int regnum) -{ - symbolS *sym; - - sym =3D symbol_create (name, reg_section, &zero_address_frag, regnum); - - if (str_hash_insert (md.reg_hash, S_GET_NAME (sym), sym, 0) !=3D NULL) - as_fatal (_("duplicate %s"), name); - - return sym; -} - -static void -declare_register_set (const char *prefix, - unsigned int num_regs, - unsigned int base_regnum) -{ - char name[8]; - unsigned int i; - - for (i =3D 0; i < num_regs; ++i) - { - snprintf (name, sizeof (name), "%s%u", prefix, i); - declare_register (name, base_regnum + i); - } -} - -static unsigned int -operand_width (enum ia64_opnd opnd) -{ - const struct ia64_operand *odesc =3D &elf64_ia64_operands[opnd]; - unsigned int bits =3D 0; - int i; - - bits =3D 0; - for (i =3D 0; i < NELEMS (odesc->field) && odesc->field[i].bits; ++i) - bits +=3D odesc->field[i].bits; - - return bits; -} - -static enum operand_match_result -operand_match (const struct ia64_opcode *idesc, int res_index, expressionS= *e) -{ - enum ia64_opnd opnd =3D idesc->operands[res_index]; - int bits, relocatable =3D 0; - struct insn_fix *fix; - bfd_signed_vma val; - - switch (opnd) - { - /* constants: */ - - case IA64_OPND_AR_CCV: - if (e->X_op =3D=3D O_register && e->X_add_number =3D=3D REG_AR + 32) - return OPERAND_MATCH; - break; - - case IA64_OPND_AR_CSD: - if (e->X_op =3D=3D O_register && e->X_add_number =3D=3D REG_AR + 25) - return OPERAND_MATCH; - break; - - case IA64_OPND_AR_PFS: - if (e->X_op =3D=3D O_register && e->X_add_number =3D=3D REG_AR + 64) - return OPERAND_MATCH; - break; - - case IA64_OPND_GR0: - if (e->X_op =3D=3D O_register && e->X_add_number =3D=3D REG_GR + 0) - return OPERAND_MATCH; - break; - - case IA64_OPND_IP: - if (e->X_op =3D=3D O_register && e->X_add_number =3D=3D REG_IP) - return OPERAND_MATCH; - break; - - case IA64_OPND_PR: - if (e->X_op =3D=3D O_register && e->X_add_number =3D=3D REG_PR) - return OPERAND_MATCH; - break; - - case IA64_OPND_PR_ROT: - if (e->X_op =3D=3D O_register && e->X_add_number =3D=3D REG_PR_ROT) - return OPERAND_MATCH; - break; - - case IA64_OPND_PSR: - if (e->X_op =3D=3D O_register && e->X_add_number =3D=3D REG_PSR) - return OPERAND_MATCH; - break; - - case IA64_OPND_PSR_L: - if (e->X_op =3D=3D O_register && e->X_add_number =3D=3D REG_PSR_L) - return OPERAND_MATCH; - break; - - case IA64_OPND_PSR_UM: - if (e->X_op =3D=3D O_register && e->X_add_number =3D=3D REG_PSR_UM) - return OPERAND_MATCH; - break; - - case IA64_OPND_C1: - if (e->X_op =3D=3D O_constant) - { - if (e->X_add_number =3D=3D 1) - return OPERAND_MATCH; - else - return OPERAND_OUT_OF_RANGE; - } - break; - - case IA64_OPND_C8: - if (e->X_op =3D=3D O_constant) - { - if (e->X_add_number =3D=3D 8) - return OPERAND_MATCH; - else - return OPERAND_OUT_OF_RANGE; - } - break; - - case IA64_OPND_C16: - if (e->X_op =3D=3D O_constant) - { - if (e->X_add_number =3D=3D 16) - return OPERAND_MATCH; - else - return OPERAND_OUT_OF_RANGE; - } - break; - - /* register operands: */ - - case IA64_OPND_AR3: - if (e->X_op =3D=3D O_register && e->X_add_number >=3D REG_AR - && e->X_add_number < REG_AR + 128) - return OPERAND_MATCH; - break; - - case IA64_OPND_B1: - case IA64_OPND_B2: - if (e->X_op =3D=3D O_register && e->X_add_number >=3D REG_BR - && e->X_add_number < REG_BR + 8) - return OPERAND_MATCH; - break; - - case IA64_OPND_CR3: - if (e->X_op =3D=3D O_register && e->X_add_number >=3D REG_CR - && e->X_add_number < REG_CR + 128) - return OPERAND_MATCH; - break; - - case IA64_OPND_DAHR3: - if (e->X_op =3D=3D O_register && e->X_add_number >=3D REG_DAHR - && e->X_add_number < REG_DAHR + 8) - return OPERAND_MATCH; - break; - - case IA64_OPND_F1: - case IA64_OPND_F2: - case IA64_OPND_F3: - case IA64_OPND_F4: - if (e->X_op =3D=3D O_register && e->X_add_number >=3D REG_FR - && e->X_add_number < REG_FR + 128) - return OPERAND_MATCH; - break; - - case IA64_OPND_P1: - case IA64_OPND_P2: - if (e->X_op =3D=3D O_register && e->X_add_number >=3D REG_P - && e->X_add_number < REG_P + 64) - return OPERAND_MATCH; - break; - - case IA64_OPND_R1: - case IA64_OPND_R2: - case IA64_OPND_R3: - if (e->X_op =3D=3D O_register && e->X_add_number >=3D REG_GR - && e->X_add_number < REG_GR + 128) - return OPERAND_MATCH; - break; - - case IA64_OPND_R3_2: - if (e->X_op =3D=3D O_register && e->X_add_number >=3D REG_GR) - { - if (e->X_add_number < REG_GR + 4) - return OPERAND_MATCH; - else if (e->X_add_number < REG_GR + 128) - return OPERAND_OUT_OF_RANGE; - } - break; - - /* indirect operands: */ - case IA64_OPND_CPUID_R3: - case IA64_OPND_DBR_R3: - case IA64_OPND_DTR_R3: - case IA64_OPND_ITR_R3: - case IA64_OPND_IBR_R3: - case IA64_OPND_MSR_R3: - case IA64_OPND_PKR_R3: - case IA64_OPND_PMC_R3: - case IA64_OPND_PMD_R3: - case IA64_OPND_DAHR_R3: - case IA64_OPND_RR_R3: - if (e->X_op =3D=3D O_index && e->X_op_symbol - && (S_GET_VALUE (e->X_op_symbol) - IND_CPUID - =3D=3D opnd - IA64_OPND_CPUID_R3)) - return OPERAND_MATCH; - break; - - case IA64_OPND_MR3: - if (e->X_op =3D=3D O_index && !e->X_op_symbol) - return OPERAND_MATCH; - break; - - /* immediate operands: */ - case IA64_OPND_CNT2a: - case IA64_OPND_LEN4: - case IA64_OPND_LEN6: - bits =3D operand_width (idesc->operands[res_index]); - if (e->X_op =3D=3D O_constant) - { - if ((bfd_vma) (e->X_add_number - 1) < ((bfd_vma) 1 << bits)) - return OPERAND_MATCH; - else - return OPERAND_OUT_OF_RANGE; - } - break; - - case IA64_OPND_CNT2b: - if (e->X_op =3D=3D O_constant) - { - if ((bfd_vma) (e->X_add_number - 1) < 3) - return OPERAND_MATCH; - else - return OPERAND_OUT_OF_RANGE; - } - break; - - case IA64_OPND_CNT2c: - val =3D e->X_add_number; - if (e->X_op =3D=3D O_constant) - { - if ((val =3D=3D 0 || val =3D=3D 7 || val =3D=3D 15 || val =3D=3D 16)) - return OPERAND_MATCH; - else - return OPERAND_OUT_OF_RANGE; - } - break; - - case IA64_OPND_SOR: - /* SOR must be an integer multiple of 8 */ - if (e->X_op =3D=3D O_constant && e->X_add_number & 0x7) - return OPERAND_OUT_OF_RANGE; - /* Fall through. */ - case IA64_OPND_SOF: - case IA64_OPND_SOL: - if (e->X_op =3D=3D O_constant) - { - if ((bfd_vma) e->X_add_number <=3D 96) - return OPERAND_MATCH; - else - return OPERAND_OUT_OF_RANGE; - } - break; - - case IA64_OPND_IMMU62: - if (e->X_op =3D=3D O_constant) - { - if ((bfd_vma) e->X_add_number < ((bfd_vma) 1 << 62)) - return OPERAND_MATCH; - else - return OPERAND_OUT_OF_RANGE; - } - else - { - /* FIXME -- need 62-bit relocation type */ - as_bad (_("62-bit relocation not yet implemented")); - } - break; - - case IA64_OPND_IMMU64: - if (e->X_op =3D=3D O_symbol || e->X_op =3D=3D O_pseudo_fixup - || e->X_op =3D=3D O_subtract) - { - fix =3D CURR_SLOT.fixup + CURR_SLOT.num_fixups; - fix->code =3D BFD_RELOC_IA64_IMM64; - if (e->X_op !=3D O_subtract) - { - fix->code =3D ia64_gen_real_reloc_type (e->X_op_symbol, fix->code); - if (e->X_op =3D=3D O_pseudo_fixup) - e->X_op =3D O_symbol; - } - - fix->opnd =3D idesc->operands[res_index]; - fix->expr =3D *e; - fix->is_pcrel =3D 0; - ++CURR_SLOT.num_fixups; - return OPERAND_MATCH; - } - else if (e->X_op =3D=3D O_constant) - return OPERAND_MATCH; - break; - - case IA64_OPND_IMMU5b: - if (e->X_op =3D=3D O_constant) - { - val =3D e->X_add_number; - if (val >=3D 32 && val <=3D 63) - return OPERAND_MATCH; - else - return OPERAND_OUT_OF_RANGE; - } - break; - - case IA64_OPND_CCNT5: - case IA64_OPND_CNT5: - case IA64_OPND_CNT6: - case IA64_OPND_CPOS6a: - case IA64_OPND_CPOS6b: - case IA64_OPND_CPOS6c: - case IA64_OPND_IMMU2: - case IA64_OPND_IMMU7a: - case IA64_OPND_IMMU7b: - case IA64_OPND_IMMU16: - case IA64_OPND_IMMU19: - case IA64_OPND_IMMU21: - case IA64_OPND_IMMU24: - case IA64_OPND_MBTYPE4: - case IA64_OPND_MHTYPE8: - case IA64_OPND_POS6: - bits =3D operand_width (idesc->operands[res_index]); - if (e->X_op =3D=3D O_constant) - { - if ((bfd_vma) e->X_add_number < ((bfd_vma) 1 << bits)) - return OPERAND_MATCH; - else - return OPERAND_OUT_OF_RANGE; - } - break; - - case IA64_OPND_IMMU9: - bits =3D operand_width (idesc->operands[res_index]); - if (e->X_op =3D=3D O_constant) - { - if ((bfd_vma) e->X_add_number < ((bfd_vma) 1 << bits)) - { - int lobits =3D e->X_add_number & 0x3; - if (((bfd_vma) e->X_add_number & 0x3C) !=3D 0 && lobits =3D=3D 0) - e->X_add_number |=3D (bfd_vma) 0x3; - return OPERAND_MATCH; - } - else - return OPERAND_OUT_OF_RANGE; - } - break; - - case IA64_OPND_IMM44: - /* least 16 bits must be zero */ - if ((e->X_add_number & 0xffff) !=3D 0) - /* XXX technically, this is wrong: we should not be issuing warning - messages until we're sure this instruction pattern is going to - be used! */ - as_warn (_("lower 16 bits of mask ignored")); - - if (e->X_op =3D=3D O_constant) - { - if (((e->X_add_number >=3D 0 - && (bfd_vma) e->X_add_number < ((bfd_vma) 1 << 44)) - || (e->X_add_number < 0 - && (bfd_vma) -e->X_add_number <=3D ((bfd_vma) 1 << 44)))) - { - /* sign-extend */ - if (e->X_add_number >=3D 0 - && (e->X_add_number & ((bfd_vma) 1 << 43)) !=3D 0) - { - e->X_add_number |=3D ~(((bfd_vma) 1 << 44) - 1); - } - return OPERAND_MATCH; - } - else - return OPERAND_OUT_OF_RANGE; - } - break; - - case IA64_OPND_IMM17: - /* bit 0 is a don't care (pr0 is hardwired to 1) */ - if (e->X_op =3D=3D O_constant) - { - if (((e->X_add_number >=3D 0 - && (bfd_vma) e->X_add_number < ((bfd_vma) 1 << 17)) - || (e->X_add_number < 0 - && (bfd_vma) -e->X_add_number <=3D ((bfd_vma) 1 << 17)))) - { - /* sign-extend */ - if (e->X_add_number >=3D 0 - && (e->X_add_number & ((bfd_vma) 1 << 16)) !=3D 0) - { - e->X_add_number |=3D ~(((bfd_vma) 1 << 17) - 1); - } - return OPERAND_MATCH; - } - else - return OPERAND_OUT_OF_RANGE; - } - break; - - case IA64_OPND_IMM14: - case IA64_OPND_IMM22: - relocatable =3D 1; - /* Fall through. */ - case IA64_OPND_IMM1: - case IA64_OPND_IMM8: - case IA64_OPND_IMM8U4: - case IA64_OPND_IMM8M1: - case IA64_OPND_IMM8M1U4: - case IA64_OPND_IMM8M1U8: - case IA64_OPND_IMM9a: - case IA64_OPND_IMM9b: - bits =3D operand_width (idesc->operands[res_index]); - if (relocatable && (e->X_op =3D=3D O_symbol - || e->X_op =3D=3D O_subtract - || e->X_op =3D=3D O_pseudo_fixup)) - { - fix =3D CURR_SLOT.fixup + CURR_SLOT.num_fixups; - - if (idesc->operands[res_index] =3D=3D IA64_OPND_IMM14) - fix->code =3D BFD_RELOC_IA64_IMM14; - else - fix->code =3D BFD_RELOC_IA64_IMM22; - - if (e->X_op !=3D O_subtract) - { - fix->code =3D ia64_gen_real_reloc_type (e->X_op_symbol, fix->code); - if (e->X_op =3D=3D O_pseudo_fixup) - e->X_op =3D O_symbol; - } - - fix->opnd =3D idesc->operands[res_index]; - fix->expr =3D *e; - fix->is_pcrel =3D 0; - ++CURR_SLOT.num_fixups; - return OPERAND_MATCH; - } - else if (e->X_op !=3D O_constant - && ! (e->X_op =3D=3D O_big && opnd =3D=3D IA64_OPND_IMM8M1U8)) - return OPERAND_MISMATCH; - - if (opnd =3D=3D IA64_OPND_IMM8M1U4) - { - /* Zero is not valid for unsigned compares that take an adjusted - constant immediate range. */ - if (e->X_add_number =3D=3D 0) - return OPERAND_OUT_OF_RANGE; - - /* Sign-extend 32-bit unsigned numbers, so that the following range - checks will work. */ - val =3D e->X_add_number; - if ((val & (~(bfd_vma) 0 << 32)) =3D=3D 0) - val =3D (val ^ ((bfd_vma) 1 << 31)) - ((bfd_vma) 1 << 31); - - /* Check for 0x100000000. This is valid because - 0x100000000-1 is the same as ((uint32_t) -1). */ - if (val =3D=3D ((bfd_signed_vma) 1 << 32)) - return OPERAND_MATCH; - - val =3D val - 1; - } - else if (opnd =3D=3D IA64_OPND_IMM8M1U8) - { - /* Zero is not valid for unsigned compares that take an adjusted - constant immediate range. */ - if (e->X_add_number =3D=3D 0) - return OPERAND_OUT_OF_RANGE; - - /* Check for 0x10000000000000000. */ - if (e->X_op =3D=3D O_big) - { - if (generic_bignum[0] =3D=3D 0 - && generic_bignum[1] =3D=3D 0 - && generic_bignum[2] =3D=3D 0 - && generic_bignum[3] =3D=3D 0 - && generic_bignum[4] =3D=3D 1) - return OPERAND_MATCH; - else - return OPERAND_OUT_OF_RANGE; - } - else - val =3D e->X_add_number - 1; - } - else if (opnd =3D=3D IA64_OPND_IMM8M1) - val =3D e->X_add_number - 1; - else if (opnd =3D=3D IA64_OPND_IMM8U4) - { - /* Sign-extend 32-bit unsigned numbers, so that the following range - checks will work. */ - val =3D e->X_add_number; - if ((val & (~(bfd_vma) 0 << 32)) =3D=3D 0) - val =3D (val ^ ((bfd_vma) 1 << 31)) - ((bfd_vma) 1 << 31); - } - else - val =3D e->X_add_number; - - if ((val >=3D 0 && (bfd_vma) val < ((bfd_vma) 1 << (bits - 1))) - || (val < 0 && (bfd_vma) -val <=3D ((bfd_vma) 1 << (bits - 1)))) - return OPERAND_MATCH; - else - return OPERAND_OUT_OF_RANGE; - - case IA64_OPND_INC3: - /* +/- 1, 4, 8, 16 */ - val =3D e->X_add_number; - if (val < 0) - val =3D -val; - if (e->X_op =3D=3D O_constant) - { - if ((val =3D=3D 1 || val =3D=3D 4 || val =3D=3D 8 || val =3D=3D 16)) - return OPERAND_MATCH; - else - return OPERAND_OUT_OF_RANGE; - } - break; - - case IA64_OPND_TGT25: - case IA64_OPND_TGT25b: - case IA64_OPND_TGT25c: - case IA64_OPND_TGT64: - if (e->X_op =3D=3D O_symbol) - { - fix =3D CURR_SLOT.fixup + CURR_SLOT.num_fixups; - if (opnd =3D=3D IA64_OPND_TGT25) - fix->code =3D BFD_RELOC_IA64_PCREL21F; - else if (opnd =3D=3D IA64_OPND_TGT25b) - fix->code =3D BFD_RELOC_IA64_PCREL21M; - else if (opnd =3D=3D IA64_OPND_TGT25c) - fix->code =3D BFD_RELOC_IA64_PCREL21B; - else if (opnd =3D=3D IA64_OPND_TGT64) - fix->code =3D BFD_RELOC_IA64_PCREL60B; - else - abort (); - - fix->code =3D ia64_gen_real_reloc_type (e->X_op_symbol, fix->code); - fix->opnd =3D idesc->operands[res_index]; - fix->expr =3D *e; - fix->is_pcrel =3D 1; - ++CURR_SLOT.num_fixups; - return OPERAND_MATCH; - } - /* Fall through. */ - case IA64_OPND_TAG13: - case IA64_OPND_TAG13b: - switch (e->X_op) - { - case O_constant: - return OPERAND_MATCH; - - case O_symbol: - fix =3D CURR_SLOT.fixup + CURR_SLOT.num_fixups; - /* There are no external relocs for TAG13/TAG13b fields, so we - create a dummy reloc. This will not live past md_apply_fix. */ - fix->code =3D BFD_RELOC_UNUSED; - fix->code =3D ia64_gen_real_reloc_type (e->X_op_symbol, fix->code); - fix->opnd =3D idesc->operands[res_index]; - fix->expr =3D *e; - fix->is_pcrel =3D 1; - ++CURR_SLOT.num_fixups; - return OPERAND_MATCH; - - default: - break; - } - break; - - case IA64_OPND_LDXMOV: - fix =3D CURR_SLOT.fixup + CURR_SLOT.num_fixups; - fix->code =3D BFD_RELOC_IA64_LDXMOV; - fix->opnd =3D idesc->operands[res_index]; - fix->expr =3D *e; - fix->is_pcrel =3D 0; - ++CURR_SLOT.num_fixups; - return OPERAND_MATCH; - - case IA64_OPND_STRD5b: - if (e->X_op =3D=3D O_constant) - { - /* 5-bit signed scaled by 64 */ - if ((e->X_add_number <=3D ( 0xf << 6 )) - && (e->X_add_number >=3D -( 0x10 << 6 ))) - { - - /* Must be a multiple of 64 */ - if ((e->X_add_number & 0x3f) !=3D 0) - as_warn (_("stride must be a multiple of 64; lower 6 bits ignored= ")); - - e->X_add_number &=3D ~ 0x3f; - return OPERAND_MATCH; - } - else - return OPERAND_OUT_OF_RANGE; - } - break; - case IA64_OPND_CNT6a: - if (e->X_op =3D=3D O_constant) - { - /* 6-bit unsigned biased by 1 -- count 0 is meaningless */ - if ((e->X_add_number <=3D 64) - && (e->X_add_number > 0) ) - { - return OPERAND_MATCH; - } - else - return OPERAND_OUT_OF_RANGE; - } - break; - - default: - break; - } - return OPERAND_MISMATCH; -} - -static int -parse_operand (expressionS *e, int more) -{ - int sep =3D '\0'; - - memset (e, 0, sizeof (*e)); - e->X_op =3D O_absent; - SKIP_WHITESPACE (); - expression (e); - resolve_register (e); - sep =3D *input_line_pointer; - if (more && (sep =3D=3D ',' || sep =3D=3D more)) - ++input_line_pointer; - return sep; -} - -static int -parse_operand_and_eval (expressionS *e, int more) -{ - int sep =3D parse_operand (e, more); - resolve_expression (e); - return sep; -} - -static int -parse_operand_maybe_eval (expressionS *e, int more, enum ia64_opnd op) -{ - int sep =3D parse_operand (e, more); - switch (op) - { - case IA64_OPND_IMM14: - case IA64_OPND_IMM22: - case IA64_OPND_IMMU64: - case IA64_OPND_TGT25: - case IA64_OPND_TGT25b: - case IA64_OPND_TGT25c: - case IA64_OPND_TGT64: - case IA64_OPND_TAG13: - case IA64_OPND_TAG13b: - case IA64_OPND_LDXMOV: - break; - default: - resolve_expression (e); - break; - } - return sep; -} - -/* Returns the next entry in the opcode table that matches the one in - IDESC, and frees the entry in IDESC. If no matching entry is - found, NULL is returned instead. */ - -static struct ia64_opcode * -get_next_opcode (struct ia64_opcode *idesc) -{ - struct ia64_opcode *next =3D ia64_find_next_opcode (idesc); - ia64_free_opcode (idesc); - return next; -} - -/* Parse the operands for the opcode and find the opcode variant that - matches the specified operands, or NULL if no match is possible. */ - -static struct ia64_opcode * -parse_operands (struct ia64_opcode *idesc) -{ - int i =3D 0, highest_unmatched_operand, num_operands =3D 0, num_outputs = =3D 0; - int error_pos, out_of_range_pos, curr_out_of_range_pos, sep =3D 0; - int reg1, reg2; - char reg_class; - enum ia64_opnd expected_operand =3D IA64_OPND_NIL; - enum operand_match_result result; - char mnemonic[129]; - char *first_arg =3D 0, *end, *saved_input_pointer; - unsigned int sof; - - gas_assert (strlen (idesc->name) <=3D 128); - - strcpy (mnemonic, idesc->name); - if (idesc->operands[2] =3D=3D IA64_OPND_SOF - || idesc->operands[1] =3D=3D IA64_OPND_SOF) - { - /* To make the common idiom "alloc loc?=3Dar.pfs,0,1,0,0" work, we - can't parse the first operand until we have parsed the - remaining operands of the "alloc" instruction. */ - SKIP_WHITESPACE (); - first_arg =3D input_line_pointer; - end =3D strchr (input_line_pointer, '=3D'); - if (!end) - { - as_bad (_("Expected separator `=3D'")); - return 0; - } - input_line_pointer =3D end + 1; - ++i; - ++num_outputs; - } - - for (; ; ++i) - { - if (i < NELEMS (CURR_SLOT.opnd)) - { - enum ia64_opnd op =3D IA64_OPND_NIL; - if (i < NELEMS (idesc->operands)) - op =3D idesc->operands[i]; - sep =3D parse_operand_maybe_eval (CURR_SLOT.opnd + i, '=3D', op); - if (CURR_SLOT.opnd[i].X_op =3D=3D O_absent) - break; - } - else - { - expressionS dummy; - - sep =3D parse_operand (&dummy, '=3D'); - if (dummy.X_op =3D=3D O_absent) - break; - } - - ++num_operands; - - if (sep !=3D '=3D' && sep !=3D ',') - break; - - if (sep =3D=3D '=3D') - { - if (num_outputs > 0) - as_bad (_("Duplicate equal sign (=3D) in instruction")); - else - num_outputs =3D i + 1; - } - } - if (sep !=3D '\0') - { - as_bad (_("Illegal operand separator `%c'"), sep); - return 0; - } - - if (idesc->operands[2] =3D=3D IA64_OPND_SOF - || idesc->operands[1] =3D=3D IA64_OPND_SOF) - { - /* Map alloc r1=3Dar.pfs,i,l,o,r to alloc r1=3Dar.pfs,(i+l+o),(i+l),= r. - Note, however, that due to that mapping operand numbers in error - messages for any of the constant operands will not be correct. */ - know (strcmp (idesc->name, "alloc") =3D=3D 0); - /* The first operand hasn't been parsed/initialized, yet (but - num_operands intentionally doesn't account for that). */ - i =3D num_operands > 4 ? 2 : 1; -#define FORCE_CONST(n) (CURR_SLOT.opnd[n].X_op =3D=3D O_constant \ - ? CURR_SLOT.opnd[n].X_add_number \ - : 0) - sof =3D set_regstack (FORCE_CONST(i), - FORCE_CONST(i + 1), - FORCE_CONST(i + 2), - FORCE_CONST(i + 3)); -#undef FORCE_CONST - - /* now we can parse the first arg: */ - saved_input_pointer =3D input_line_pointer; - input_line_pointer =3D first_arg; - sep =3D parse_operand_maybe_eval (CURR_SLOT.opnd + 0, '=3D', - idesc->operands[0]); - if (sep !=3D '=3D') - --num_outputs; /* force error */ - input_line_pointer =3D saved_input_pointer; - - CURR_SLOT.opnd[i].X_add_number =3D sof; - if (CURR_SLOT.opnd[i + 1].X_op =3D=3D O_constant - && CURR_SLOT.opnd[i + 2].X_op =3D=3D O_constant) - CURR_SLOT.opnd[i + 1].X_add_number - =3D sof - CURR_SLOT.opnd[i + 2].X_add_number; - else - CURR_SLOT.opnd[i + 1].X_op =3D O_illegal; - CURR_SLOT.opnd[i + 2] =3D CURR_SLOT.opnd[i + 3]; - } - - highest_unmatched_operand =3D -4; - curr_out_of_range_pos =3D -1; - error_pos =3D 0; - for (; idesc; idesc =3D get_next_opcode (idesc)) - { - if (num_outputs !=3D idesc->num_outputs) - continue; /* mismatch in # of outputs */ - if (highest_unmatched_operand < 0) - highest_unmatched_operand |=3D 1; - if (num_operands > NELEMS (idesc->operands) - || (num_operands < NELEMS (idesc->operands) - && idesc->operands[num_operands]) - || (num_operands > 0 && !idesc->operands[num_operands - 1])) - continue; /* mismatch in number of arguments */ - if (highest_unmatched_operand < 0) - highest_unmatched_operand |=3D 2; - - CURR_SLOT.num_fixups =3D 0; - - /* Try to match all operands. If we see an out-of-range operand, - then continue trying to match the rest of the operands, since if - the rest match, then this idesc will give the best error message. */ - - out_of_range_pos =3D -1; - for (i =3D 0; i < num_operands && idesc->operands[i]; ++i) - { - result =3D operand_match (idesc, i, CURR_SLOT.opnd + i); - if (result !=3D OPERAND_MATCH) - { - if (result !=3D OPERAND_OUT_OF_RANGE) - break; - if (out_of_range_pos < 0) - /* remember position of the first out-of-range operand: */ - out_of_range_pos =3D i; - } - } - - /* If we did not match all operands, or if at least one operand was - out-of-range, then this idesc does not match. Keep track of which - idesc matched the most operands before failing. If we have two - idescs that failed at the same position, and one had an out-of-range - operand, then prefer the out-of-range operand. Thus if we have - "add r0=3D0x1000000,r1" we get an error saying the constant is out - of range instead of an error saying that the constant should have been - a register. */ - - if (i !=3D num_operands || out_of_range_pos >=3D 0) - { - if (i > highest_unmatched_operand - || (i =3D=3D highest_unmatched_operand - && out_of_range_pos > curr_out_of_range_pos)) - { - highest_unmatched_operand =3D i; - if (out_of_range_pos >=3D 0) - { - expected_operand =3D idesc->operands[out_of_range_pos]; - error_pos =3D out_of_range_pos; - } - else - { - expected_operand =3D idesc->operands[i]; - error_pos =3D i; - } - curr_out_of_range_pos =3D out_of_range_pos; - } - continue; - } - - break; - } - if (!idesc) - { - if (expected_operand) - as_bad (_("Operand %u of `%s' should be %s"), - error_pos + 1, mnemonic, - elf64_ia64_operands[expected_operand].desc); - else if (highest_unmatched_operand < 0 && !(highest_unmatched_operan= d & 1)) - as_bad (_("Wrong number of output operands")); - else if (highest_unmatched_operand < 0 && !(highest_unmatched_operan= d & 2)) - as_bad (_("Wrong number of input operands")); - else - as_bad (_("Operand mismatch")); - return 0; - } - - /* Check that the instruction doesn't use - - r0, f0, or f1 as output operands - - the same predicate twice as output operands - - r0 as address of a base update load or store - - the same GR as output and address of a base update load - - two even- or two odd-numbered FRs as output operands of a floating - point parallel load. - At most two (conflicting) output (or output-like) operands can exist, - (floating point parallel loads have three outputs, but the base regis= ter, - if updated, cannot conflict with the actual outputs). */ - reg2 =3D reg1 =3D -1; - for (i =3D 0; i < num_operands; ++i) - { - int regno =3D 0; - - reg_class =3D 0; - switch (idesc->operands[i]) - { - case IA64_OPND_R1: - case IA64_OPND_R2: - case IA64_OPND_R3: - if (i < num_outputs) - { - if (CURR_SLOT.opnd[i].X_add_number =3D=3D REG_GR) - reg_class =3D 'r'; - else if (reg1 < 0) - reg1 =3D CURR_SLOT.opnd[i].X_add_number; - else if (reg2 < 0) - reg2 =3D CURR_SLOT.opnd[i].X_add_number; - } - break; - case IA64_OPND_P1: - case IA64_OPND_P2: - if (i < num_outputs) - { - if (reg1 < 0) - reg1 =3D CURR_SLOT.opnd[i].X_add_number; - else if (reg2 < 0) - reg2 =3D CURR_SLOT.opnd[i].X_add_number; - } - break; - case IA64_OPND_F1: - case IA64_OPND_F2: - case IA64_OPND_F3: - case IA64_OPND_F4: - if (i < num_outputs) - { - if (CURR_SLOT.opnd[i].X_add_number >=3D REG_FR - && CURR_SLOT.opnd[i].X_add_number <=3D REG_FR + 1) - { - reg_class =3D 'f'; - regno =3D CURR_SLOT.opnd[i].X_add_number - REG_FR; - } - else if (reg1 < 0) - reg1 =3D CURR_SLOT.opnd[i].X_add_number; - else if (reg2 < 0) - reg2 =3D CURR_SLOT.opnd[i].X_add_number; - } - break; - case IA64_OPND_MR3: - if (idesc->flags & IA64_OPCODE_POSTINC) - { - if (CURR_SLOT.opnd[i].X_add_number =3D=3D REG_GR) - reg_class =3D 'm'; - else if (reg1 < 0) - reg1 =3D CURR_SLOT.opnd[i].X_add_number; - else if (reg2 < 0) - reg2 =3D CURR_SLOT.opnd[i].X_add_number; - } - break; - default: - break; - } - switch (reg_class) - { - case 0: - break; - default: - as_warn (_("Invalid use of `%c%d' as output operand"), reg_class, regno= ); - break; - case 'm': - as_warn (_("Invalid use of `r%d' as base update address operand"), regn= o); - break; - } - } - if (reg1 =3D=3D reg2) - { - if (reg1 >=3D REG_GR && reg1 <=3D REG_GR + 127) - { - reg1 -=3D REG_GR; - reg_class =3D 'r'; - } - else if (reg1 >=3D REG_P && reg1 <=3D REG_P + 63) - { - reg1 -=3D REG_P; - reg_class =3D 'p'; - } - else if (reg1 >=3D REG_FR && reg1 <=3D REG_FR + 127) - { - reg1 -=3D REG_FR; - reg_class =3D 'f'; - } - else - reg_class =3D 0; - if (reg_class) - as_warn (_("Invalid duplicate use of `%c%d'"), reg_class, reg1); - } - else if (((reg1 >=3D REG_FR && reg1 <=3D REG_FR + 31 - && reg2 >=3D REG_FR && reg2 <=3D REG_FR + 31) - || (reg1 >=3D REG_FR + 32 && reg1 <=3D REG_FR + 127 - && reg2 >=3D REG_FR + 32 && reg2 <=3D REG_FR + 127)) - && ! ((reg1 ^ reg2) & 1)) - as_warn (_("Invalid simultaneous use of `f%d' and `f%d'"), - reg1 - REG_FR, reg2 - REG_FR); - else if ((reg1 >=3D REG_FR && reg1 <=3D REG_FR + 31 - && reg2 >=3D REG_FR + 32 && reg2 <=3D REG_FR + 127) - || (reg1 >=3D REG_FR + 32 && reg1 <=3D REG_FR + 127 - && reg2 >=3D REG_FR && reg2 <=3D REG_FR + 31)) - as_warn (_("Dangerous simultaneous use of `f%d' and `f%d'"), - reg1 - REG_FR, reg2 - REG_FR); - return idesc; -} - -static void -build_insn (struct slot *slot, bfd_vma *insnp) -{ - const struct ia64_operand *odesc, *o2desc; - struct ia64_opcode *idesc =3D slot->idesc; - bfd_vma insn; - bfd_signed_vma val; - const char *err; - int i; - - insn =3D idesc->opcode | slot->qp_regno; - - for (i =3D 0; i < NELEMS (idesc->operands) && idesc->operands[i]; ++i) - { - if (slot->opnd[i].X_op =3D=3D O_register - || slot->opnd[i].X_op =3D=3D O_constant - || slot->opnd[i].X_op =3D=3D O_index) - val =3D slot->opnd[i].X_add_number; - else if (slot->opnd[i].X_op =3D=3D O_big) - { - /* This must be the value 0x10000000000000000. */ - gas_assert (idesc->operands[i] =3D=3D IA64_OPND_IMM8M1U8); - val =3D 0; - } - else - val =3D 0; - - switch (idesc->operands[i]) - { - case IA64_OPND_IMMU64: - *insnp++ =3D (val >> 22) & 0x1ffffffffffLL; - insn |=3D (((val & 0x7f) << 13) | (((val >> 7) & 0x1ff) << 27) - | (((val >> 16) & 0x1f) << 22) | (((val >> 21) & 0x1) << 21) - | (((val >> 63) & 0x1) << 36)); - continue; - - case IA64_OPND_IMMU62: - val &=3D 0x3fffffffffffffffULL; - if (val !=3D slot->opnd[i].X_add_number) - as_warn (_("Value truncated to 62 bits")); - *insnp++ =3D (val >> 21) & 0x1ffffffffffLL; - insn |=3D (((val & 0xfffff) << 6) | (((val >> 20) & 0x1) << 36)); - continue; - - case IA64_OPND_TGT64: - val >>=3D 4; - *insnp++ =3D ((val >> 20) & 0x7fffffffffLL) << 2; - insn |=3D ((((val >> 59) & 0x1) << 36) - | (((val >> 0) & 0xfffff) << 13)); - continue; - - case IA64_OPND_AR3: - val -=3D REG_AR; - break; - - case IA64_OPND_B1: - case IA64_OPND_B2: - val -=3D REG_BR; - break; - - case IA64_OPND_CR3: - val -=3D REG_CR; - break; - - case IA64_OPND_DAHR3: - val -=3D REG_DAHR; - break; - - case IA64_OPND_F1: - case IA64_OPND_F2: - case IA64_OPND_F3: - case IA64_OPND_F4: - val -=3D REG_FR; - break; - - case IA64_OPND_P1: - case IA64_OPND_P2: - val -=3D REG_P; - break; - - case IA64_OPND_R1: - case IA64_OPND_R2: - case IA64_OPND_R3: - case IA64_OPND_R3_2: - case IA64_OPND_CPUID_R3: - case IA64_OPND_DBR_R3: - case IA64_OPND_DTR_R3: - case IA64_OPND_ITR_R3: - case IA64_OPND_IBR_R3: - case IA64_OPND_MR3: - case IA64_OPND_MSR_R3: - case IA64_OPND_PKR_R3: - case IA64_OPND_PMC_R3: - case IA64_OPND_PMD_R3: - case IA64_OPND_DAHR_R3: - case IA64_OPND_RR_R3: - val -=3D REG_GR; - break; - - default: - break; - } - - odesc =3D elf64_ia64_operands + idesc->operands[i]; - err =3D (*odesc->insert) (odesc, val, &insn); - if (err) - as_bad_where (slot->src_file, slot->src_line, - _("Bad operand value: %s"), err); - if (idesc->flags & IA64_OPCODE_PSEUDO) - { - if ((idesc->flags & IA64_OPCODE_F2_EQ_F3) - && odesc =3D=3D elf64_ia64_operands + IA64_OPND_F3) - { - o2desc =3D elf64_ia64_operands + IA64_OPND_F2; - (*o2desc->insert) (o2desc, val, &insn); - } - if ((idesc->flags & IA64_OPCODE_LEN_EQ_64MCNT) - && (odesc =3D=3D elf64_ia64_operands + IA64_OPND_CPOS6a - || odesc =3D=3D elf64_ia64_operands + IA64_OPND_POS6)) - { - o2desc =3D elf64_ia64_operands + IA64_OPND_LEN6; - (*o2desc->insert) (o2desc, 64 - val, &insn); - } - } - } - *insnp =3D insn; -} - -static void -emit_one_bundle (void) -{ - int manual_bundling_off =3D 0, manual_bundling =3D 0; - enum ia64_unit required_unit, insn_unit =3D 0; - enum ia64_insn_type type[3], insn_type; - unsigned int template_val, orig_template; - bfd_vma insn[3] =3D { -1, -1, -1 }; - struct ia64_opcode *idesc; - int end_of_insn_group =3D 0, user_template =3D -1; - int n, i, j, first, curr, last_slot; - bfd_vma t0 =3D 0, t1 =3D 0; - struct label_fix *lfix; - bool mark_label; - struct insn_fix *ifix; - char mnemonic[16]; - fixS *fix; - char *f; - int addr_mod; - - first =3D (md.curr_slot + NUM_SLOTS - md.num_slots_in_use) % NUM_SLOTS; - know (first >=3D 0 && first < NUM_SLOTS); - n =3D MIN (3, md.num_slots_in_use); - - /* Determine template: user user_template if specified, best match - otherwise: */ - - if (md.slot[first].user_template >=3D 0) - user_template =3D template_val =3D md.slot[first].user_template; - else - { - /* Auto select appropriate template. */ - memset (type, 0, sizeof (type)); - curr =3D first; - for (i =3D 0; i < n; ++i) - { - if (md.slot[curr].label_fixups && i !=3D 0) - break; - type[i] =3D md.slot[curr].idesc->type; - curr =3D (curr + 1) % NUM_SLOTS; - } - template_val =3D best_template[type[0]][type[1]][type[2]]; - } - - /* initialize instructions with appropriate nops: */ - for (i =3D 0; i < 3; ++i) - insn[i] =3D nop[ia64_templ_desc[template_val].exec_unit[i]]; - - f =3D frag_more (16); - - /* Check to see if this bundle is at an offset that is a multiple of 16-= bytes - from the start of the frag. */ - addr_mod =3D frag_now_fix () & 15; - if (frag_now->has_code && frag_now->insn_addr !=3D addr_mod) - as_bad (_("instruction address is not a multiple of 16")); - frag_now->insn_addr =3D addr_mod; - frag_now->has_code =3D 1; - - /* now fill in slots with as many insns as possible: */ - curr =3D first; - idesc =3D md.slot[curr].idesc; - end_of_insn_group =3D 0; - last_slot =3D -1; - for (i =3D 0; i < 3 && md.num_slots_in_use > 0; ++i) - { - /* If we have unwind records, we may need to update some now. */ - unw_rec_list *ptr =3D md.slot[curr].unwind_record; - unw_rec_list *end_ptr =3D NULL; - - if (ptr) - { - /* Find the last prologue/body record in the list for the current - insn, and set the slot number for all records up to that point. - This needs to be done now, because prologue/body records refer to - the current point, not the point after the instruction has been - issued. This matters because there may have been nops emitted - meanwhile. Any non-prologue non-body record followed by a - prologue/body record must also refer to the current point. */ - unw_rec_list *last_ptr; - - for (j =3D 1; end_ptr =3D=3D NULL && j < md.num_slots_in_use; ++j) - end_ptr =3D md.slot[(curr + j) % NUM_SLOTS].unwind_record; - for (last_ptr =3D NULL; ptr !=3D end_ptr; ptr =3D ptr->next) - if (ptr->r.type =3D=3D prologue || ptr->r.type =3D=3D prologue_gr - || ptr->r.type =3D=3D body) - last_ptr =3D ptr; - if (last_ptr) - { - /* Make last_ptr point one after the last prologue/body - record. */ - last_ptr =3D last_ptr->next; - for (ptr =3D md.slot[curr].unwind_record; ptr !=3D last_ptr; - ptr =3D ptr->next) - { - ptr->slot_number =3D (unsigned long) f + i; - ptr->slot_frag =3D frag_now; - } - /* Remove the initialized records, so that we won't accidentally - update them again if we insert a nop and continue. */ - md.slot[curr].unwind_record =3D last_ptr; - } - } - - manual_bundling_off =3D md.slot[curr].manual_bundling_off; - if (md.slot[curr].manual_bundling_on) - { - if (curr =3D=3D first) - manual_bundling =3D 1; - else - break; /* Need to start a new bundle. */ - } - - /* If this instruction specifies a template, then it must be the fir= st - instruction of a bundle. */ - if (curr !=3D first && md.slot[curr].user_template >=3D 0) - break; - - if (idesc->flags & IA64_OPCODE_SLOT2) - { - if (manual_bundling && !manual_bundling_off) - { - as_bad_where (md.slot[curr].src_file, md.slot[curr].src_line, - _("`%s' must be last in bundle"), idesc->name); - if (i < 2) - manual_bundling =3D -1; /* Suppress meaningless post-loop errors. */ - } - i =3D 2; - } - if (idesc->flags & IA64_OPCODE_LAST) - { - int required_slot; - unsigned int required_template; - - /* If we need a stop bit after an M slot, our only choice is - template 5 (M;;MI). If we need a stop bit after a B - slot, our only choice is to place it at the end of the - bundle, because the only available templates are MIB, - MBB, BBB, MMB, and MFB. We don't handle anything other - than M and B slots because these are the only kind of - instructions that can have the IA64_OPCODE_LAST bit set. */ - required_template =3D template_val; - switch (idesc->type) - { - case IA64_TYPE_M: - required_slot =3D 0; - required_template =3D 5; - break; - - case IA64_TYPE_B: - required_slot =3D 2; - break; - - default: - as_bad_where (md.slot[curr].src_file, md.slot[curr].src_line, - _("Internal error: don't know how to force %s to end of instruction= group"), - idesc->name); - required_slot =3D i; - break; - } - if (manual_bundling - && (i > required_slot - || (required_slot =3D=3D 2 && !manual_bundling_off) - || (user_template >=3D 0 - /* Changing from MMI to M;MI is OK. */ - && (template_val ^ required_template) > 1))) - { - as_bad_where (md.slot[curr].src_file, md.slot[curr].src_line, - _("`%s' must be last in instruction group"), - idesc->name); - if (i < 2 && required_slot =3D=3D 2 && !manual_bundling_off) - manual_bundling =3D -1; /* Suppress meaningless post-loop errors. */ - } - if (required_slot < i) - /* Can't fit this instruction. */ - break; - - i =3D required_slot; - if (required_template !=3D template_val) - { - /* If we switch the template, we need to reset the NOPs - after slot i. The slot-types of the instructions ahead - of i never change, so we don't need to worry about - changing NOPs in front of this slot. */ - for (j =3D i; j < 3; ++j) - insn[j] =3D nop[ia64_templ_desc[required_template].exec_unit[j]]; - - /* We just picked a template that includes the stop bit in the - middle, so we don't need another one emitted later. */ - md.slot[curr].end_of_insn_group =3D 0; - } - template_val =3D required_template; - } - if (curr !=3D first && md.slot[curr].label_fixups) - { - if (manual_bundling) - { - as_bad_where (md.slot[curr].src_file, md.slot[curr].src_line, - _("Label must be first in a bundle")); - manual_bundling =3D -1; /* Suppress meaningless post-loop errors. = */ - } - /* This insn must go into the first slot of a bundle. */ - break; - } - - if (end_of_insn_group && md.num_slots_in_use >=3D 1) - { - /* We need an instruction group boundary in the middle of a - bundle. See if we can switch to an other template with - an appropriate boundary. */ - - orig_template =3D template_val; - if (i =3D=3D 1 && (user_template =3D=3D 4 - || (user_template < 0 - && (ia64_templ_desc[template_val].exec_unit[0] - =3D=3D IA64_UNIT_M)))) - { - template_val =3D 5; - end_of_insn_group =3D 0; - } - else if (i =3D=3D 2 && (user_template =3D=3D 0 - || (user_template < 0 - && (ia64_templ_desc[template_val].exec_unit[1] - =3D=3D IA64_UNIT_I))) - /* This test makes sure we don't switch the template if - the next instruction is one that needs to be first in - an instruction group. Since all those instructions are - in the M group, there is no way such an instruction can - fit in this bundle even if we switch the template. The - reason we have to check for this is that otherwise we - may end up generating "MI;;I M.." which has the deadly - effect that the second M instruction is no longer the - first in the group! --davidm 99/12/16 */ - && (idesc->flags & IA64_OPCODE_FIRST) =3D=3D 0) - { - template_val =3D 1; - end_of_insn_group =3D 0; - } - else if (i =3D=3D 1 - && user_template =3D=3D 0 - && !(idesc->flags & IA64_OPCODE_FIRST)) - /* Use the next slot. */ - continue; - else if (curr !=3D first) - /* can't fit this insn */ - break; - - if (template_val !=3D orig_template) - /* if we switch the template, we need to reset the NOPs - after slot i. The slot-types of the instructions ahead - of i never change, so we don't need to worry about - changing NOPs in front of this slot. */ - for (j =3D i; j < 3; ++j) - insn[j] =3D nop[ia64_templ_desc[template_val].exec_unit[j]]; - } - required_unit =3D ia64_templ_desc[template_val].exec_unit[i]; - - /* resolve dynamic opcodes such as "break", "hint", and "nop": */ - if (idesc->type =3D=3D IA64_TYPE_DYN) - { - enum ia64_opnd opnd1, opnd2; - - if ((strcmp (idesc->name, "nop") =3D=3D 0) - || (strcmp (idesc->name, "break") =3D=3D 0)) - insn_unit =3D required_unit; - else if (strcmp (idesc->name, "hint") =3D=3D 0) - { - insn_unit =3D required_unit; - if (required_unit =3D=3D IA64_UNIT_B) - { - switch (md.hint_b) - { - case hint_b_ok: - break; - case hint_b_warning: - as_warn (_("hint in B unit may be treated as nop")); - break; - case hint_b_error: - /* When manual bundling is off and there is no - user template, we choose a different unit so - that hint won't go into the current slot. We - will fill the current bundle with nops and - try to put hint into the next bundle. */ - if (!manual_bundling && user_template < 0) - insn_unit =3D IA64_UNIT_I; - else - as_bad (_("hint in B unit can't be used")); - break; - } - } - } - else if (strcmp (idesc->name, "chk.s") =3D=3D 0 - || strcmp (idesc->name, "mov") =3D=3D 0) - { - insn_unit =3D IA64_UNIT_M; - if (required_unit =3D=3D IA64_UNIT_I - || (required_unit =3D=3D IA64_UNIT_F && template_val =3D=3D 6)) - insn_unit =3D IA64_UNIT_I; - } - else - as_fatal (_("emit_one_bundle: unexpected dynamic op")); - - snprintf (mnemonic, sizeof (mnemonic), "%s.%c", - idesc->name, "?imbfxx"[insn_unit]); - opnd1 =3D idesc->operands[0]; - opnd2 =3D idesc->operands[1]; - ia64_free_opcode (idesc); - idesc =3D ia64_find_opcode (mnemonic); - /* moves to/from ARs have collisions */ - if (opnd1 =3D=3D IA64_OPND_AR3 || opnd2 =3D=3D IA64_OPND_AR3) - { - while (idesc !=3D NULL - && (idesc->operands[0] !=3D opnd1 - || idesc->operands[1] !=3D opnd2)) - idesc =3D get_next_opcode (idesc); - } - md.slot[curr].idesc =3D idesc; - } - else - { - insn_type =3D idesc->type; - insn_unit =3D IA64_UNIT_NIL; - switch (insn_type) - { - case IA64_TYPE_A: - if (required_unit =3D=3D IA64_UNIT_I || required_unit =3D=3D IA64_U= NIT_M) - insn_unit =3D required_unit; - break; - case IA64_TYPE_X: insn_unit =3D IA64_UNIT_L; break; - case IA64_TYPE_I: insn_unit =3D IA64_UNIT_I; break; - case IA64_TYPE_M: insn_unit =3D IA64_UNIT_M; break; - case IA64_TYPE_B: insn_unit =3D IA64_UNIT_B; break; - case IA64_TYPE_F: insn_unit =3D IA64_UNIT_F; break; - default: break; - } - } - - if (insn_unit !=3D required_unit) - continue; /* Try next slot. */ - - /* Now is a good time to fix up the labels for this insn. */ - mark_label =3D false; - for (lfix =3D md.slot[curr].label_fixups; lfix; lfix =3D lfix->next) - { - S_SET_VALUE (lfix->sym, frag_now_fix () - 16); - symbol_set_frag (lfix->sym, frag_now); - mark_label |=3D lfix->dw2_mark_labels; - } - for (lfix =3D md.slot[curr].tag_fixups; lfix; lfix =3D lfix->next) - { - S_SET_VALUE (lfix->sym, frag_now_fix () - 16 + i); - symbol_set_frag (lfix->sym, frag_now); - } - - if (debug_type =3D=3D DEBUG_DWARF2 - || md.slot[curr].loc_directive_seen - || mark_label) - { - bfd_vma addr =3D frag_now->fr_address + frag_now_fix () - 16 + i; - - md.slot[curr].loc_directive_seen =3D 0; - if (mark_label) - md.slot[curr].debug_line.flags |=3D DWARF2_FLAG_BASIC_BLOCK; - - dwarf2_gen_line_info (addr, &md.slot[curr].debug_line); - } - - build_insn (md.slot + curr, insn + i); - - ptr =3D md.slot[curr].unwind_record; - if (ptr) - { - /* Set slot numbers for all remaining unwind records belonging to the - current insn. There can not be any prologue/body unwind records - here. */ - for (; ptr !=3D end_ptr; ptr =3D ptr->next) - { - ptr->slot_number =3D (unsigned long) f + i; - ptr->slot_frag =3D frag_now; - } - md.slot[curr].unwind_record =3D NULL; - } - - for (j =3D 0; j < md.slot[curr].num_fixups; ++j) - { - unsigned long where; - - ifix =3D md.slot[curr].fixup + j; - where =3D frag_now_fix () - 16 + i; -#ifdef TE_HPUX - /* Relocations for instructions specify the slot in the - bottom two bits of r_offset. The IA64 HP-UX linker - expects PCREL60B relocations to specify slot 2 of an - instruction. gas generates PCREL60B against slot 1. */ - if (ifix->code =3D=3D BFD_RELOC_IA64_PCREL60B) - { - know (i =3D=3D 1); - ++where; - } -#endif - - fix =3D fix_new_exp (frag_now, where, 8, - &ifix->expr, ifix->is_pcrel, ifix->code); - fix->tc_fix_data.opnd =3D ifix->opnd; - fix->fx_file =3D md.slot[curr].src_file; - fix->fx_line =3D md.slot[curr].src_line; - } - - end_of_insn_group =3D md.slot[curr].end_of_insn_group; - - /* This adjustment to "i" must occur after the fix, otherwise the fix - is assigned to the wrong slot, and the VMS linker complains. */ - if (required_unit =3D=3D IA64_UNIT_L) - { - know (i =3D=3D 1); - /* skip one slot for long/X-unit instructions */ - ++i; - } - --md.num_slots_in_use; - last_slot =3D i; - - /* clear slot: */ - ia64_free_opcode (md.slot[curr].idesc); - memset (md.slot + curr, 0, sizeof (md.slot[curr])); - md.slot[curr].user_template =3D -1; - - if (manual_bundling_off) - { - manual_bundling =3D 0; - break; - } - curr =3D (curr + 1) % NUM_SLOTS; - idesc =3D md.slot[curr].idesc; - } - - /* A user template was specified, but the first following instruction did - not fit. This can happen with or without manual bundling. */ - if (md.num_slots_in_use > 0 && last_slot < 0) - { - as_bad_where (md.slot[curr].src_file, md.slot[curr].src_line, - _("`%s' does not fit into %s template"), - idesc->name, ia64_templ_desc[template_val].name); - /* Drop first insn so we don't livelock. */ - --md.num_slots_in_use; - know (curr =3D=3D first); - ia64_free_opcode (md.slot[curr].idesc); - memset (md.slot + curr, 0, sizeof (md.slot[curr])); - md.slot[curr].user_template =3D -1; - } - else if (manual_bundling > 0) - { - if (md.num_slots_in_use > 0) - { - if (last_slot >=3D 2) - as_bad_where (md.slot[curr].src_file, md.slot[curr].src_line, - _("`%s' does not fit into bundle"), idesc->name); - else - { - const char *where; - - if (template_val =3D=3D 2) - where =3D "X slot"; - else if (last_slot =3D=3D 0) - where =3D "slots 2 or 3"; - else - where =3D "slot 3"; - as_bad_where (md.slot[curr].src_file, md.slot[curr].src_line, - _("`%s' can't go in %s of %s template"), - idesc->name, where, ia64_templ_desc[template_val].name); - } - } - else - as_bad_where (md.slot[curr].src_file, md.slot[curr].src_line, - _("Missing '}' at end of file")); - } - - know (md.num_slots_in_use < NUM_SLOTS); - - t0 =3D end_of_insn_group | (template_val << 1) | (insn[0] << 5) | (insn[= 1] << 46); - t1 =3D ((insn[1] >> 18) & 0x7fffff) | (insn[2] << 23); - - number_to_chars_littleendian (f + 0, t0, 8); - number_to_chars_littleendian (f + 8, t1, 8); -} - -int -md_parse_option (int c, const char *arg) -{ - - switch (c) - { - /* Switches from the Intel assembler. */ - case 'm': - if (strcmp (arg, "ilp64") =3D=3D 0 - || strcmp (arg, "lp64") =3D=3D 0 - || strcmp (arg, "p64") =3D=3D 0) - { - md.flags |=3D EF_IA_64_ABI64; - } - else if (strcmp (arg, "ilp32") =3D=3D 0) - { - md.flags &=3D ~EF_IA_64_ABI64; - } - else if (strcmp (arg, "le") =3D=3D 0) - { - md.flags &=3D ~EF_IA_64_BE; - default_big_endian =3D 0; - } - else if (strcmp (arg, "be") =3D=3D 0) - { - md.flags |=3D EF_IA_64_BE; - default_big_endian =3D 1; - } - else if (startswith (arg, "unwind-check=3D")) - { - arg +=3D 13; - if (strcmp (arg, "warning") =3D=3D 0) - md.unwind_check =3D unwind_check_warning; - else if (strcmp (arg, "error") =3D=3D 0) - md.unwind_check =3D unwind_check_error; - else - return 0; - } - else if (startswith (arg, "hint.b=3D")) - { - arg +=3D 7; - if (strcmp (arg, "ok") =3D=3D 0) - md.hint_b =3D hint_b_ok; - else if (strcmp (arg, "warning") =3D=3D 0) - md.hint_b =3D hint_b_warning; - else if (strcmp (arg, "error") =3D=3D 0) - md.hint_b =3D hint_b_error; - else - return 0; - } - else if (startswith (arg, "tune=3D")) - { - arg +=3D 5; - if (strcmp (arg, "itanium1") =3D=3D 0) - md.tune =3D itanium1; - else if (strcmp (arg, "itanium2") =3D=3D 0) - md.tune =3D itanium2; - else - return 0; - } - else - return 0; - break; - - case 'N': - if (strcmp (arg, "so") =3D=3D 0) - { - /* Suppress signon message. */ - } - else if (strcmp (arg, "pi") =3D=3D 0) - { - /* Reject privileged instructions. FIXME */ - } - else if (strcmp (arg, "us") =3D=3D 0) - { - /* Allow union of signed and unsigned range. FIXME */ - } - else if (strcmp (arg, "close_fcalls") =3D=3D 0) - { - /* Do not resolve global function calls. */ - } - else - return 0; - break; - - case 'C': - /* temp[=3D"prefix"] Insert temporary labels into the object file - symbol table prefixed by "prefix". - Default prefix is ":temp:". - */ - break; - - case 'a': - /* indirect=3D Assume unannotated indirect branches behavior - according to -- - exit: branch out from the current context (default) - labels: all labels in context may be branch targets - */ - if (!startswith (arg, "indirect=3D")) - return 0; - break; - - case 'x': - /* -X conflicts with an ignored option, use -x instead */ - md.detect_dv =3D 1; - if (!arg || strcmp (arg, "explicit") =3D=3D 0) - { - /* set default mode to explicit */ - md.default_explicit_mode =3D 1; - break; - } - else if (strcmp (arg, "auto") =3D=3D 0) - { - md.default_explicit_mode =3D 0; - } - else if (strcmp (arg, "none") =3D=3D 0) - { - md.detect_dv =3D 0; - } - else if (strcmp (arg, "debug") =3D=3D 0) - { - md.debug_dv =3D 1; - } - else if (strcmp (arg, "debugx") =3D=3D 0) - { - md.default_explicit_mode =3D 1; - md.debug_dv =3D 1; - } - else if (strcmp (arg, "debugn") =3D=3D 0) - { - md.debug_dv =3D 1; - md.detect_dv =3D 0; - } - else - { - as_bad (_("Unrecognized option '-x%s'"), arg); - } - break; - - case 'S': - /* nops Print nops statistics. */ - break; - - /* GNU specific switches for gcc. */ - case OPTION_MCONSTANT_GP: - md.flags |=3D EF_IA_64_CONS_GP; - break; - - case OPTION_MAUTO_PIC: - md.flags |=3D EF_IA_64_NOFUNCDESC_CONS_GP; - break; - - default: - return 0; - } - - return 1; -} - -void -md_show_usage (FILE *stream) -{ - fputs (_("\ -IA-64 options:\n\ - --mconstant-gp mark output file as using the constant-GP model\n\ - (sets ELF header flag EF_IA_64_CONS_GP)\n\ - --mauto-pic mark output file as using the constant-GP model\n\ - without function descriptors (sets ELF header flag\n\ - EF_IA_64_NOFUNCDESC_CONS_GP)\n\ - -milp32|-milp64|-mlp64|-mp64 select data model (default -mlp64)\n\ - -mle | -mbe select little- or big-endian byte order (default -mle)\n\ - -mtune=3D[itanium1|itanium2]\n\ - tune for a specific CPU (default -mtune=3Ditanium2)\n\ - -munwind-check=3D[warning|error]\n\ - unwind directive check (default -munwind-check=3Dwarning)\n\ - -mhint.b=3D[ok|warning|error]\n\ - hint.b check (default -mhint.b=3Derror)\n\ - -x | -xexplicit turn on dependency violation checking\n"), stream); - /* Note for translators: "automagically" can be translated as "automatic= ally" here. */ - fputs (_("\ - -xauto automagically remove dependency violations (default)\n\ - -xnone turn off dependency violation checking\n\ - -xdebug debug dependency violation checker\n\ - -xdebugn debug dependency violation checker but turn off\n\ - dependency violation checking\n\ - -xdebugx debug dependency violation checker and turn on\n\ - dependency violation checking\n"), - stream); -} - -void -ia64_after_parse_args (void) -{ - if (debug_type =3D=3D DEBUG_STABS) - as_fatal (_("--gstabs is not supported for ia64")); -} - -/* Return true if TYPE fits in TEMPL at SLOT. */ - -static int -match (int templ, int type, int slot) -{ - enum ia64_unit unit; - int result; - - unit =3D ia64_templ_desc[templ].exec_unit[slot]; - switch (type) - { - case IA64_TYPE_DYN: result =3D 1; break; /* for nop and break */ - case IA64_TYPE_A: - result =3D (unit =3D=3D IA64_UNIT_I || unit =3D=3D IA64_UNIT_M); - break; - case IA64_TYPE_X: result =3D (unit =3D=3D IA64_UNIT_L); break; - case IA64_TYPE_I: result =3D (unit =3D=3D IA64_UNIT_I); break; - case IA64_TYPE_M: result =3D (unit =3D=3D IA64_UNIT_M); break; - case IA64_TYPE_B: result =3D (unit =3D=3D IA64_UNIT_B); break; - case IA64_TYPE_F: result =3D (unit =3D=3D IA64_UNIT_F); break; - default: result =3D 0; break; - } - return result; -} - -/* For Itanium 1, add a bit of extra goodness if a nop of type F or B woul= d fit - in TEMPL at SLOT. For Itanium 2, add a bit of extra goodness if a nop = of - type M or I would fit in TEMPL at SLOT. */ - -static inline int -extra_goodness (int templ, int slot) -{ - switch (md.tune) - { - case itanium1: - if (slot =3D=3D 1 && match (templ, IA64_TYPE_F, slot)) - return 2; - else if (slot =3D=3D 2 && match (templ, IA64_TYPE_B, slot)) - return 1; - else - return 0; - break; - case itanium2: - if (match (templ, IA64_TYPE_M, slot) - || match (templ, IA64_TYPE_I, slot)) - /* Favor M- and I-unit NOPs. We definitely want to avoid - F-unit and B-unit may cause split-issue or less-than-optimal - branch-prediction. */ - return 2; - else - return 0; - break; - default: - abort (); - return 0; - } -} - -/* This function is called once, at assembler startup time. It sets - up all the tables, etc. that the MD part of the assembler will need - that can be determined before arguments are parsed. */ -void -md_begin (void) -{ - int i, j, k, t, goodness, best, ok; - - md.auto_align =3D 1; - md.explicit_mode =3D md.default_explicit_mode; - - bfd_set_section_alignment (text_section, 4); - - /* Make sure function pointers get initialized. */ - target_big_endian =3D -1; - dot_byteorder (default_big_endian); - - alias_hash =3D str_htab_create (); - alias_name_hash =3D str_htab_create (); - secalias_hash =3D str_htab_create (); - secalias_name_hash =3D str_htab_create (); - - pseudo_func[FUNC_DTP_MODULE].u.sym =3D - symbol_new (".", undefined_section, - &zero_address_frag, FUNC_DTP_MODULE); - - pseudo_func[FUNC_DTP_RELATIVE].u.sym =3D - symbol_new (".", undefined_section, - &zero_address_frag, FUNC_DTP_RELATIVE); - - pseudo_func[FUNC_FPTR_RELATIVE].u.sym =3D - symbol_new (".", undefined_section, - &zero_address_frag, FUNC_FPTR_RELATIVE); - - pseudo_func[FUNC_GP_RELATIVE].u.sym =3D - symbol_new (".", undefined_section, - &zero_address_frag, FUNC_GP_RELATIVE); - - pseudo_func[FUNC_LT_RELATIVE].u.sym =3D - symbol_new (".", undefined_section, - &zero_address_frag, FUNC_LT_RELATIVE); - - pseudo_func[FUNC_LT_RELATIVE_X].u.sym =3D - symbol_new (".", undefined_section, - &zero_address_frag, FUNC_LT_RELATIVE_X); - - pseudo_func[FUNC_PC_RELATIVE].u.sym =3D - symbol_new (".", undefined_section, - &zero_address_frag, FUNC_PC_RELATIVE); - - pseudo_func[FUNC_PLT_RELATIVE].u.sym =3D - symbol_new (".", undefined_section, - &zero_address_frag, FUNC_PLT_RELATIVE); - - pseudo_func[FUNC_SEC_RELATIVE].u.sym =3D - symbol_new (".", undefined_section, - &zero_address_frag, FUNC_SEC_RELATIVE); - - pseudo_func[FUNC_SEG_RELATIVE].u.sym =3D - symbol_new (".", undefined_section, - &zero_address_frag, FUNC_SEG_RELATIVE); - - pseudo_func[FUNC_TP_RELATIVE].u.sym =3D - symbol_new (".", undefined_section, - &zero_address_frag, FUNC_TP_RELATIVE); - - pseudo_func[FUNC_LTV_RELATIVE].u.sym =3D - symbol_new (".", undefined_section, - &zero_address_frag, FUNC_LTV_RELATIVE); - - pseudo_func[FUNC_LT_FPTR_RELATIVE].u.sym =3D - symbol_new (".", undefined_section, - &zero_address_frag, FUNC_LT_FPTR_RELATIVE); - - pseudo_func[FUNC_LT_DTP_MODULE].u.sym =3D - symbol_new (".", undefined_section, - &zero_address_frag, FUNC_LT_DTP_MODULE); - - pseudo_func[FUNC_LT_DTP_RELATIVE].u.sym =3D - symbol_new (".", undefined_section, - &zero_address_frag, FUNC_LT_DTP_RELATIVE); - - pseudo_func[FUNC_LT_TP_RELATIVE].u.sym =3D - symbol_new (".", undefined_section, - &zero_address_frag, FUNC_LT_TP_RELATIVE); - - pseudo_func[FUNC_IPLT_RELOC].u.sym =3D - symbol_new (".", undefined_section, - &zero_address_frag, FUNC_IPLT_RELOC); - -#ifdef TE_VMS - pseudo_func[FUNC_SLOTCOUNT_RELOC].u.sym =3D - symbol_new (".", undefined_section, - &zero_address_frag, FUNC_SLOTCOUNT_RELOC); -#endif - - if (md.tune !=3D itanium1) - { - /* Convert MFI NOPs bundles into MMI NOPs bundles. */ - le_nop[0] =3D 0x8; - le_nop_stop[0] =3D 0x9; - } - - /* Compute the table of best templates. We compute goodness as a - base 4 value, in which each match counts for 3. Match-failures - result in NOPs and we use extra_goodness() to pick the execution - units that are best suited for issuing the NOP. */ - for (i =3D 0; i < IA64_NUM_TYPES; ++i) - for (j =3D 0; j < IA64_NUM_TYPES; ++j) - for (k =3D 0; k < IA64_NUM_TYPES; ++k) - { - best =3D 0; - for (t =3D 0; t < NELEMS (ia64_templ_desc); ++t) - { - goodness =3D 0; - if (match (t, i, 0)) - { - if (match (t, j, 1)) - { - if ((t =3D=3D 2 && j =3D=3D IA64_TYPE_X) || match (t, k, 2)) - goodness =3D 3 + 3 + 3; - else - goodness =3D 3 + 3 + extra_goodness (t, 2); - } - else if (match (t, j, 2)) - goodness =3D 3 + 3 + extra_goodness (t, 1); - else - { - goodness =3D 3; - goodness +=3D extra_goodness (t, 1); - goodness +=3D extra_goodness (t, 2); - } - } - else if (match (t, i, 1)) - { - if ((t =3D=3D 2 && i =3D=3D IA64_TYPE_X) || match (t, j, 2)) - goodness =3D 3 + 3; - else - goodness =3D 3 + extra_goodness (t, 2); - } - else if (match (t, i, 2)) - goodness =3D 3 + extra_goodness (t, 1); - - if (goodness > best) - { - best =3D goodness; - best_template[i][j][k] =3D t; - } - } - } - -#ifdef DEBUG_TEMPLATES - /* For debugging changes to the best_template calculations. We don't ca= re - about combinations with invalid instructions, so start the loops at 1= . */ - for (i =3D 0; i < IA64_NUM_TYPES; ++i) - for (j =3D 0; j < IA64_NUM_TYPES; ++j) - for (k =3D 0; k < IA64_NUM_TYPES; ++k) - { - char type_letter[IA64_NUM_TYPES] =3D { 'n', 'a', 'i', 'm', 'b', 'f', - 'x', 'd' }; - fprintf (stderr, "%c%c%c %s\n", type_letter[i], type_letter[j], - type_letter[k], - ia64_templ_desc[best_template[i][j][k]].name); - } -#endif - - for (i =3D 0; i < NUM_SLOTS; ++i) - md.slot[i].user_template =3D -1; - - md.pseudo_hash =3D str_htab_create (); - for (i =3D 0; i < NELEMS (pseudo_opcode); ++i) - if (str_hash_insert (md.pseudo_hash, pseudo_opcode[i].name, - pseudo_opcode + i, 0) !=3D NULL) - as_fatal (_("duplicate %s"), pseudo_opcode[i].name); - - md.reg_hash =3D str_htab_create (); - md.dynreg_hash =3D str_htab_create (); - md.const_hash =3D str_htab_create (); - md.entry_hash =3D str_htab_create (); - - /* general registers: */ - declare_register_set ("r", 128, REG_GR); - declare_register ("gp", REG_GR + 1); - declare_register ("sp", REG_GR + 12); - declare_register ("tp", REG_GR + 13); - declare_register_set ("ret", 4, REG_GR + 8); - - /* floating point registers: */ - declare_register_set ("f", 128, REG_FR); - declare_register_set ("farg", 8, REG_FR + 8); - declare_register_set ("fret", 8, REG_FR + 8); - - /* branch registers: */ - declare_register_set ("b", 8, REG_BR); - declare_register ("rp", REG_BR + 0); - - /* predicate registers: */ - declare_register_set ("p", 64, REG_P); - declare_register ("pr", REG_PR); - declare_register ("pr.rot", REG_PR_ROT); - - /* application registers: */ - declare_register_set ("ar", 128, REG_AR); - for (i =3D 0; i < NELEMS (ar); ++i) - declare_register (ar[i].name, REG_AR + ar[i].regnum); - - /* control registers: */ - declare_register_set ("cr", 128, REG_CR); - for (i =3D 0; i < NELEMS (cr); ++i) - declare_register (cr[i].name, REG_CR + cr[i].regnum); - - /* dahr registers: */ - declare_register_set ("dahr", 8, REG_DAHR); - - declare_register ("ip", REG_IP); - declare_register ("cfm", REG_CFM); - declare_register ("psr", REG_PSR); - declare_register ("psr.l", REG_PSR_L); - declare_register ("psr.um", REG_PSR_UM); - - for (i =3D 0; i < NELEMS (indirect_reg); ++i) - { - unsigned int regnum =3D indirect_reg[i].regnum; - - md.indregsym[regnum - IND_CPUID] =3D declare_register (indirect_reg[= i].name, regnum); - } - - /* pseudo-registers used to specify unwind info: */ - declare_register ("psp", REG_PSP); - - for (i =3D 0; i < NELEMS (const_bits); ++i) - if (str_hash_insert (md.const_hash, const_bits[i].name, const_bits + i= , 0)) - as_fatal (_("duplicate %s"), const_bits[i].name); - - /* Set the architecture and machine depending on defaults and command li= ne - options. */ - if (md.flags & EF_IA_64_ABI64) - ok =3D bfd_set_arch_mach (stdoutput, bfd_arch_ia64, bfd_mach_ia64_elf6= 4); - else - ok =3D bfd_set_arch_mach (stdoutput, bfd_arch_ia64, bfd_mach_ia64_elf3= 2); - - if (! ok) - as_warn (_("Could not set architecture and machine")); - - /* Set the pointer size and pointer shift size depending on md.flags */ - - if (md.flags & EF_IA_64_ABI64) - { - md.pointer_size =3D 8; /* pointers are 8 bytes */ - md.pointer_size_shift =3D 3; /* alignment is 8 bytes =3D 2^2 */ - } - else - { - md.pointer_size =3D 4; /* pointers are 4 bytes */ - md.pointer_size_shift =3D 2; /* alignment is 4 bytes =3D 2^2 */ - } - - md.mem_offset.hint =3D 0; - md.path =3D 0; - md.maxpaths =3D 0; - md.entry_labels =3D NULL; -} - -/* Set the default options in md. Cannot do this in md_begin because - that is called after md_parse_option which is where we set the - options in md based on command line options. */ - -void -ia64_init (int argc ATTRIBUTE_UNUSED, char **argv ATTRIBUTE_UNUSED) -{ - md.flags =3D MD_FLAGS_DEFAULT; -#ifndef TE_VMS - /* Don't turn on dependency checking for VMS, doesn't work. */ - md.detect_dv =3D 1; -#endif - /* FIXME: We should change it to unwind_check_error someday. */ - md.unwind_check =3D unwind_check_warning; - md.hint_b =3D hint_b_error; - md.tune =3D itanium2; -} - -/* Return a string for the target object file format. */ - -const char * -ia64_target_format (void) -{ - if (OUTPUT_FLAVOR =3D=3D bfd_target_elf_flavour) - { - if (md.flags & EF_IA_64_BE) - { - if (md.flags & EF_IA_64_ABI64) -#if defined(TE_AIX50) - return "elf64-ia64-aix-big"; -#elif defined(TE_HPUX) - return "elf64-ia64-hpux-big"; -#else - return "elf64-ia64-big"; -#endif - else -#if defined(TE_AIX50) - return "elf32-ia64-aix-big"; -#elif defined(TE_HPUX) - return "elf32-ia64-hpux-big"; -#else - return "elf32-ia64-big"; -#endif - } - else - { - if (md.flags & EF_IA_64_ABI64) -#if defined (TE_AIX50) - return "elf64-ia64-aix-little"; -#elif defined (TE_VMS) - { - md.flags |=3D EF_IA_64_ARCHVER_1; - return "elf64-ia64-vms"; - } -#else - return "elf64-ia64-little"; -#endif - else -#ifdef TE_AIX50 - return "elf32-ia64-aix-little"; -#else - return "elf32-ia64-little"; -#endif - } - } - else - return "unknown-format"; -} - -void -ia64_md_finish (void) -{ - /* terminate insn group upon reaching end of file: */ - insn_group_break (1, 0, 0); - - /* emits slots we haven't written yet: */ - ia64_flush_insns (); - - bfd_set_private_flags (stdoutput, md.flags); - - md.mem_offset.hint =3D 0; -} - -void -ia64_start_line (void) -{ - static int first; - - if (!first) { - /* Make sure we don't reference input_line_pointer[-1] when that's - not valid. */ - first =3D 1; - return; - } - - if (md.qp.X_op =3D=3D O_register) - as_bad (_("qualifying predicate not followed by instruction")); - md.qp.X_op =3D O_absent; - - if (ignore_input ()) - return; - - if (input_line_pointer[0] =3D=3D ';' && input_line_pointer[-1] =3D=3D ';= ') - { - if (md.detect_dv && !md.explicit_mode) - { - static int warned; - - if (!warned) - { - warned =3D 1; - as_warn (_("Explicit stops are ignored in auto mode")); - } - } - else - insn_group_break (1, 0, 0); - } - else if (input_line_pointer[-1] =3D=3D '{') - { - if (md.manual_bundling) - as_warn (_("Found '{' when manual bundling is already turned on")); - else - CURR_SLOT.manual_bundling_on =3D 1; - md.manual_bundling =3D 1; - - /* Bundling is only acceptable in explicit mode - or when in default automatic mode. */ - if (md.detect_dv && !md.explicit_mode) - { - if (!md.mode_explicitly_set - && !md.default_explicit_mode) - dot_dv_mode ('E'); - else - as_warn (_("Found '{' after explicit switch to automatic mode")); - } - } - else if (input_line_pointer[-1] =3D=3D '}') - { - if (!md.manual_bundling) - as_warn (_("Found '}' when manual bundling is off")); - else - PREV_SLOT.manual_bundling_off =3D 1; - md.manual_bundling =3D 0; - - /* switch back to automatic mode, if applicable */ - if (md.detect_dv - && md.explicit_mode - && !md.mode_explicitly_set - && !md.default_explicit_mode) - dot_dv_mode ('A'); - } -} - -/* This is a hook for ia64_frob_label, so that it can distinguish tags from - labels. */ -static int defining_tag =3D 0; - -int -ia64_unrecognized_line (int ch) -{ - switch (ch) - { - case '(': - expression_and_evaluate (&md.qp); - if (*input_line_pointer++ !=3D ')') - { - as_bad (_("Expected ')'")); - return 0; - } - if (md.qp.X_op !=3D O_register) - { - as_bad (_("Qualifying predicate expected")); - return 0; - } - if (md.qp.X_add_number < REG_P || md.qp.X_add_number >=3D REG_P + 64) - { - as_bad (_("Predicate register expected")); - return 0; - } - return 1; - - case '[': - { - char *s; - char c; - symbolS *tag; - int temp; - - if (md.qp.X_op =3D=3D O_register) - { - as_bad (_("Tag must come before qualifying predicate.")); - return 0; - } - - /* This implements just enough of read_a_source_file in read.c to - recognize labels. */ - if (is_name_beginner (*input_line_pointer)) - { - c =3D get_symbol_name (&s); - } - else if (LOCAL_LABELS_FB - && ISDIGIT (*input_line_pointer)) - { - temp =3D 0; - while (ISDIGIT (*input_line_pointer)) - temp =3D (temp * 10) + *input_line_pointer++ - '0'; - fb_label_instance_inc (temp); - s =3D fb_label_name (temp, 0); - c =3D *input_line_pointer; - } - else - { - s =3D NULL; - c =3D '\0'; - } - if (c !=3D ':') - { - /* Put ':' back for error messages' sake. */ - *input_line_pointer++ =3D ':'; - as_bad (_("Expected ':'")); - return 0; - } - - defining_tag =3D 1; - tag =3D colon (s); - defining_tag =3D 0; - /* Put ':' back for error messages' sake. */ - *input_line_pointer++ =3D ':'; - if (*input_line_pointer++ !=3D ']') - { - as_bad (_("Expected ']'")); - return 0; - } - if (! tag) - { - as_bad (_("Tag name expected")); - return 0; - } - return 1; - } - - default: - break; - } - - /* Not a valid line. */ - return 0; -} - -void -ia64_frob_label (struct symbol *sym) -{ - struct label_fix *fix; - - /* Tags need special handling since they are not bundle breaks like - labels. */ - if (defining_tag) - { - fix =3D XOBNEW (¬es, struct label_fix); - fix->sym =3D sym; - fix->next =3D CURR_SLOT.tag_fixups; - fix->dw2_mark_labels =3D false; - CURR_SLOT.tag_fixups =3D fix; - - return; - } - - if (bfd_section_flags (now_seg) & SEC_CODE) - { - md.last_text_seg =3D now_seg; - md.last_text_subseg =3D now_subseg; - fix =3D XOBNEW (¬es, struct label_fix); - fix->sym =3D sym; - fix->next =3D CURR_SLOT.label_fixups; - fix->dw2_mark_labels =3D dwarf2_loc_mark_labels; - CURR_SLOT.label_fixups =3D fix; - - /* Keep track of how many code entry points we've seen. */ - if (md.path =3D=3D md.maxpaths) - { - md.maxpaths +=3D 20; - md.entry_labels =3D XRESIZEVEC (const char *, md.entry_labels, - md.maxpaths); - } - md.entry_labels[md.path++] =3D S_GET_NAME (sym); - } -} - -#ifdef TE_HPUX -/* The HP-UX linker will give unresolved symbol errors for symbols - that are declared but unused. This routine removes declared, - unused symbols from an object. */ -int -ia64_frob_symbol (struct symbol *sym) -{ - if ((S_GET_SEGMENT (sym) =3D=3D bfd_und_section_ptr && ! symbol_used_p (= sym) && - ELF_ST_VISIBILITY (S_GET_OTHER (sym)) =3D=3D STV_DEFAULT) - || (S_GET_SEGMENT (sym) =3D=3D bfd_abs_section_ptr - && ! S_IS_EXTERNAL (sym))) - return 1; - return 0; -} -#endif - -void -ia64_flush_pending_output (void) -{ - if (!md.keep_pending_output - && bfd_section_flags (now_seg) & SEC_CODE) - { - /* ??? This causes many unnecessary stop bits to be emitted. - Unfortunately, it isn't clear if it is safe to remove this. */ - insn_group_break (1, 0, 0); - ia64_flush_insns (); - } -} - -/* Do ia64-specific expression optimization. All that's done here is - to transform index expressions that are either due to the indexing - of rotating registers or due to the indexing of indirect register - sets. */ -int -ia64_optimize_expr (expressionS *l, operatorT op, expressionS *r) -{ - if (op !=3D O_index) - return 0; - resolve_expression (l); - if (l->X_op =3D=3D O_register) - { - unsigned num_regs =3D l->X_add_number >> 16; - - resolve_expression (r); - if (num_regs) - { - /* Left side is a .rotX-allocated register. */ - if (r->X_op !=3D O_constant) - { - as_bad (_("Rotating register index must be a non-negative constant"= )); - r->X_add_number =3D 0; - } - else if ((valueT) r->X_add_number >=3D num_regs) - { - as_bad (_("Index out of range 0..%u"), num_regs - 1); - r->X_add_number =3D 0; - } - l->X_add_number =3D (l->X_add_number & 0xffff) + r->X_add_number; - return 1; - } - else if (l->X_add_number >=3D IND_CPUID && l->X_add_number <=3D IND_= RR) - { - if (r->X_op !=3D O_register - || r->X_add_number < REG_GR - || r->X_add_number > REG_GR + 127) - { - as_bad (_("Indirect register index must be a general register")); - r->X_add_number =3D REG_GR; - } - l->X_op =3D O_index; - l->X_op_symbol =3D md.indregsym[l->X_add_number - IND_CPUID]; - l->X_add_number =3D r->X_add_number; - return 1; - } - } - as_bad (_("Index can only be applied to rotating or indirect registers")= ); - /* Fall back to some register use of which has as little as possible - side effects, to minimize subsequent error messages. */ - l->X_op =3D O_register; - l->X_add_number =3D REG_GR + 3; - return 1; -} - -int -ia64_parse_name (char *name, expressionS *e, char *nextcharP) -{ - struct const_desc *cdesc; - struct dynreg *dr =3D 0; - unsigned int idx; - struct symbol *sym; - char *end; - - if (*name =3D=3D '@') - { - enum pseudo_type pseudo_type =3D PSEUDO_FUNC_NONE; - - /* Find what relocation pseudo-function we're dealing with. */ - for (idx =3D 0; idx < NELEMS (pseudo_func); ++idx) - if (pseudo_func[idx].name - && pseudo_func[idx].name[0] =3D=3D name[1] - && strcmp (pseudo_func[idx].name + 1, name + 2) =3D=3D 0) - { - pseudo_type =3D pseudo_func[idx].type; - break; - } - switch (pseudo_type) - { - case PSEUDO_FUNC_RELOC: - end =3D input_line_pointer; - if (*nextcharP !=3D '(') - { - as_bad (_("Expected '('")); - break; - } - /* Skip '('. */ - ++input_line_pointer; - expression (e); - if (*input_line_pointer !=3D ')') - { - as_bad (_("Missing ')'")); - goto done; - } - /* Skip ')'. */ - ++input_line_pointer; -#ifdef TE_VMS - if (idx =3D=3D FUNC_SLOTCOUNT_RELOC) - { - /* @slotcount can accept any expression. Canonicalize. */ - e->X_add_symbol =3D make_expr_symbol (e); - e->X_op =3D O_symbol; - e->X_add_number =3D 0; - } -#endif - if (e->X_op !=3D O_symbol) - { - if (e->X_op !=3D O_pseudo_fixup) - { - as_bad (_("Not a symbolic expression")); - goto done; - } - if (idx !=3D FUNC_LT_RELATIVE) - { - as_bad (_("Illegal combination of relocation functions")); - goto done; - } - switch (S_GET_VALUE (e->X_op_symbol)) - { - case FUNC_FPTR_RELATIVE: - idx =3D FUNC_LT_FPTR_RELATIVE; break; - case FUNC_DTP_MODULE: - idx =3D FUNC_LT_DTP_MODULE; break; - case FUNC_DTP_RELATIVE: - idx =3D FUNC_LT_DTP_RELATIVE; break; - case FUNC_TP_RELATIVE: - idx =3D FUNC_LT_TP_RELATIVE; break; - default: - as_bad (_("Illegal combination of relocation functions")); - goto done; - } - } - /* Make sure gas doesn't get rid of local symbols that are used - in relocs. */ - e->X_op =3D O_pseudo_fixup; - e->X_op_symbol =3D pseudo_func[idx].u.sym; - done: - *nextcharP =3D *input_line_pointer; - break; - - case PSEUDO_FUNC_CONST: - e->X_op =3D O_constant; - e->X_add_number =3D pseudo_func[idx].u.ival; - break; - - case PSEUDO_FUNC_REG: - e->X_op =3D O_register; - e->X_add_number =3D pseudo_func[idx].u.ival; - break; - - default: - return 0; - } - return 1; - } - - /* first see if NAME is a known register name: */ - sym =3D str_hash_find (md.reg_hash, name); - if (sym) - { - e->X_op =3D O_register; - e->X_add_number =3D S_GET_VALUE (sym); - return 1; - } - - cdesc =3D str_hash_find (md.const_hash, name); - if (cdesc) - { - e->X_op =3D O_constant; - e->X_add_number =3D cdesc->value; - return 1; - } - - /* check for inN, locN, or outN: */ - idx =3D 0; - switch (name[0]) - { - case 'i': - if (name[1] =3D=3D 'n' && ISDIGIT (name[2])) - { - dr =3D &md.in; - idx =3D 2; - } - break; - - case 'l': - if (name[1] =3D=3D 'o' && name[2] =3D=3D 'c' && ISDIGIT (name[3])) - { - dr =3D &md.loc; - idx =3D 3; - } - break; - - case 'o': - if (name[1] =3D=3D 'u' && name[2] =3D=3D 't' && ISDIGIT (name[3])) - { - dr =3D &md.out; - idx =3D 3; - } - break; - - default: - break; - } - - /* Ignore register numbers with leading zeroes, except zero itself. */ - if (dr && (name[idx] !=3D '0' || name[idx + 1] =3D=3D '\0')) - { - unsigned long regnum; - - /* The name is inN, locN, or outN; parse the register number. */ - regnum =3D strtoul (name + idx, &end, 10); - if (end > name + idx && *end =3D=3D '\0' && regnum < 96) - { - if (regnum >=3D dr->num_regs) - { - if (!dr->num_regs) - as_bad (_("No current frame")); - else - as_bad (_("Register number out of range 0..%u"), - dr->num_regs - 1); - regnum =3D 0; - } - e->X_op =3D O_register; - e->X_add_number =3D dr->base + regnum; - return 1; - } - } - - end =3D xstrdup (name); - name =3D ia64_canonicalize_symbol_name (end); - if ((dr =3D str_hash_find (md.dynreg_hash, name))) - { - /* We've got ourselves the name of a rotating register set. - Store the base register number in the low 16 bits of - X_add_number and the size of the register set in the top 16 - bits. */ - e->X_op =3D O_register; - e->X_add_number =3D dr->base | (dr->num_regs << 16); - free (end); - return 1; - } - free (end); - return 0; -} - -/* Remove the '#' suffix that indicates a symbol as opposed to a register.= */ - -char * -ia64_canonicalize_symbol_name (char *name) -{ - size_t len =3D strlen (name), full =3D len; - - while (len > 0 && name[len - 1] =3D=3D '#') - --len; - if (len <=3D 0) - { - if (full > 0) - as_bad (_("Standalone `#' is illegal")); - } - else if (len < full - 1) - as_warn (_("Redundant `#' suffix operators")); - name[len] =3D '\0'; - return name; -} - -/* Return true if idesc is a conditional branch instruction. This excludes - the modulo scheduled branches, and br.ia. Mod-sched branches are exclu= ded - because they always read/write resources regardless of the value of the - qualifying predicate. br.ia must always use p0, and hence is always - taken. Thus this function returns true for branches which can fall - through, and which use no resources if they do fall through. */ - -static int -is_conditional_branch (struct ia64_opcode *idesc) -{ - /* br is a conditional branch. Everything that starts with br. except - br.ia, br.c{loop,top,exit}, and br.w{top,exit} is a conditional branc= h. - Everything that starts with brl is a conditional branch. */ - return (idesc->name[0] =3D=3D 'b' && idesc->name[1] =3D=3D 'r' - && (idesc->name[2] =3D=3D '\0' - || (idesc->name[2] =3D=3D '.' && idesc->name[3] !=3D 'i' - && idesc->name[3] !=3D 'c' && idesc->name[3] !=3D 'w') - || idesc->name[2] =3D=3D 'l' - /* br.cond, br.call, br.clr */ - || (idesc->name[2] =3D=3D '.' && idesc->name[3] =3D=3D 'c' - && (idesc->name[4] =3D=3D 'a' || idesc->name[4] =3D=3D 'o' - || (idesc->name[4] =3D=3D 'l' && idesc->name[5] =3D=3D 'r'))))); -} - -/* Return whether the given opcode is a taken branch. If there's any doub= t, - returns zero. */ - -static int -is_taken_branch (struct ia64_opcode *idesc) -{ - return ((is_conditional_branch (idesc) && CURR_SLOT.qp_regno =3D=3D 0) - || startswith (idesc->name, "br.ia")); -} - -/* Return whether the given opcode is an interruption or rfi. If there's = any - doubt, returns zero. */ - -static int -is_interruption_or_rfi (struct ia64_opcode *idesc) -{ - if (strcmp (idesc->name, "rfi") =3D=3D 0) - return 1; - return 0; -} - -/* Returns the index of the given dependency in the opcode's list of chks,= or - -1 if there is no dependency. */ - -static int -depends_on (int depind, struct ia64_opcode *idesc) -{ - int i; - const struct ia64_opcode_dependency *dep =3D idesc->dependencies; - for (i =3D 0; i < dep->nchks; i++) - { - if (depind =3D=3D DEP (dep->chks[i])) - return i; - } - return -1; -} - -/* Determine a set of specific resources used for a particular resource - class. Returns the number of specific resources identified For those - cases which are not determinable statically, the resource returned is - marked nonspecific. - - Meanings of value in 'NOTE': - 1) only read/write when the register number is explicitly encoded in the - insn. - 2) only read CFM when accessing a rotating GR, FR, or PR. mov pr only - accesses CFM when qualifying predicate is in the rotating region. - 3) general register value is used to specify an indirect register; not - determinable statically. - 4) only read the given resource when bits 7:0 of the indirect index - register value does not match the register number of the resource; not - determinable statically. - 5) all rules are implementation specific. - 6) only when both the index specified by the reader and the index speci= fied - by the writer have the same value in bits 63:61; not determinable - statically. - 7) only access the specified resource when the corresponding mask bit is - set - 8) PSR.dfh is only read when these insns reference FR32-127. PSR.dfl is - only read when these insns reference FR2-31 - 9) PSR.mfl is only written when these insns write FR2-31. PSR.mfh is o= nly - written when these insns write FR32-127 - 10) The PSR.bn bit is only accessed when one of GR16-31 is specified in= the - instruction - 11) The target predicates are written independently of PR[qp], but sour= ce - registers are only read if PR[qp] is true. Since the state of PR[qp] - cannot statically be determined, all source registers are marked used. - 12) This insn only reads the specified predicate register when that - register is the PR[qp]. - 13) This reference to ld-c only applies to the GR whose value is loaded - with data returned from memory, not the post-incremented address regist= er. - 14) The RSE resource includes the implementation-specific RSE internal - state resources. At least one (and possibly more) of these resources a= re - read by each instruction listed in IC:rse-readers. At least one (and - possibly more) of these resources are written by each insn listed in - IC:rse-writers. - 15+16) Represents reserved instructions, which the assembler does not - generate. - 17) CR[TPR] has a RAW dependency only between mov-to-CR-TPR and - mov-to-PSR-l or ssm instructions that set PSR.i, PSR.pp or PSR.up. - - Memory resources (i.e. locations in memory) are *not* marked or tracked= by - this code; there are no dependency violations based on memory access. -*/ - -#define MAX_SPECS 256 -#define DV_CHK 1 -#define DV_REG 0 - -static int -specify_resource (const struct ia64_dependency *dep, - struct ia64_opcode *idesc, - /* is this a DV chk or a DV reg? */ - int type, - /* returned specific resources */ - struct rsrc specs[MAX_SPECS], - /* resource note for this insn's usage */ - int note, - /* which execution path to examine */ - int path) -{ - int count =3D 0; - int i; - int rsrc_write =3D 0; - struct rsrc tmpl; - - if (dep->mode =3D=3D IA64_DV_WAW - || (dep->mode =3D=3D IA64_DV_RAW && type =3D=3D DV_REG) - || (dep->mode =3D=3D IA64_DV_WAR && type =3D=3D DV_CHK)) - rsrc_write =3D 1; - - /* template for any resources we identify */ - tmpl.dependency =3D dep; - tmpl.note =3D note; - tmpl.insn_srlz =3D tmpl.data_srlz =3D 0; - tmpl.qp_regno =3D CURR_SLOT.qp_regno; - tmpl.link_to_qp_branch =3D 1; - tmpl.mem_offset.hint =3D 0; - tmpl.mem_offset.offset =3D 0; - tmpl.mem_offset.base =3D 0; - tmpl.specific =3D 1; - tmpl.index =3D -1; - tmpl.cmp_type =3D CMP_NONE; - tmpl.depind =3D 0; - tmpl.file =3D NULL; - tmpl.line =3D 0; - tmpl.path =3D 0; - -#define UNHANDLED \ -as_warn (_("Unhandled dependency %s for %s (%s), note %d"), \ -dep->name, idesc->name, (rsrc_write?"write":"read"), note) -#define KNOWN(REG) (gr_values[REG].known && gr_values[REG].path >=3D path) - - /* we don't need to track these */ - if (dep->semantics =3D=3D IA64_DVS_NONE) - return 0; - - switch (dep->specifier) - { - case IA64_RS_AR_K: - if (note =3D=3D 1) - { - if (idesc->operands[!rsrc_write] =3D=3D IA64_OPND_AR3) - { - int regno =3D CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_AR; - if (regno >=3D 0 && regno <=3D 7) - { - specs[count] =3D tmpl; - specs[count++].index =3D regno; - } - } - } - else if (note =3D=3D 0) - { - for (i =3D 0; i < 8; i++) - { - specs[count] =3D tmpl; - specs[count++].index =3D i; - } - } - else - { - UNHANDLED; - } - break; - - case IA64_RS_AR_UNAT: - /* This is a mov =3DAR or mov AR=3D instruction. */ - if (idesc->operands[!rsrc_write] =3D=3D IA64_OPND_AR3) - { - int regno =3D CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_AR; - if (regno =3D=3D AR_UNAT) - { - specs[count++] =3D tmpl; - } - } - else - { - /* This is a spill/fill, or other instruction that modifies the - unat register. */ - - /* Unless we can determine the specific bits used, mark the whole - thing; bits 8:3 of the memory address indicate the bit used in - UNAT. The .mem.offset hint may be used to eliminate a small - subset of conflicts. */ - specs[count] =3D tmpl; - if (md.mem_offset.hint) - { - if (md.debug_dv) - fprintf (stderr, " Using hint for spill/fill\n"); - /* The index isn't actually used, just set it to something - approximating the bit index. */ - specs[count].index =3D (md.mem_offset.offset >> 3) & 0x3F; - specs[count].mem_offset.hint =3D 1; - specs[count].mem_offset.offset =3D md.mem_offset.offset; - specs[count++].mem_offset.base =3D md.mem_offset.base; - } - else - { - specs[count++].specific =3D 0; - } - } - break; - - case IA64_RS_AR: - if (note =3D=3D 1) - { - if (idesc->operands[!rsrc_write] =3D=3D IA64_OPND_AR3) - { - int regno =3D CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_AR; - if ((regno >=3D 8 && regno <=3D 15) - || (regno >=3D 20 && regno <=3D 23) - || (regno >=3D 31 && regno <=3D 39) - || (regno >=3D 41 && regno <=3D 47) - || (regno >=3D 67 && regno <=3D 111)) - { - specs[count] =3D tmpl; - specs[count++].index =3D regno; - } - } - } - else - { - UNHANDLED; - } - break; - - case IA64_RS_ARb: - if (note =3D=3D 1) - { - if (idesc->operands[!rsrc_write] =3D=3D IA64_OPND_AR3) - { - int regno =3D CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_AR; - if ((regno >=3D 48 && regno <=3D 63) - || (regno >=3D 112 && regno <=3D 127)) - { - specs[count] =3D tmpl; - specs[count++].index =3D regno; - } - } - } - else if (note =3D=3D 0) - { - for (i =3D 48; i < 64; i++) - { - specs[count] =3D tmpl; - specs[count++].index =3D i; - } - for (i =3D 112; i < 128; i++) - { - specs[count] =3D tmpl; - specs[count++].index =3D i; - } - } - else - { - UNHANDLED; - } - break; - - case IA64_RS_BR: - if (note !=3D 1) - { - UNHANDLED; - } - else - { - if (rsrc_write) - { - for (i =3D 0; i < idesc->num_outputs; i++) - if (idesc->operands[i] =3D=3D IA64_OPND_B1 - || idesc->operands[i] =3D=3D IA64_OPND_B2) - { - specs[count] =3D tmpl; - specs[count++].index =3D - CURR_SLOT.opnd[i].X_add_number - REG_BR; - } - } - else - { - for (i =3D idesc->num_outputs; i < NELEMS (idesc->operands); i++) - if (idesc->operands[i] =3D=3D IA64_OPND_B1 - || idesc->operands[i] =3D=3D IA64_OPND_B2) - { - specs[count] =3D tmpl; - specs[count++].index =3D - CURR_SLOT.opnd[i].X_add_number - REG_BR; - } - } - } - break; - - case IA64_RS_CPUID: /* four or more registers */ - if (note =3D=3D 3) - { - if (idesc->operands[!rsrc_write] =3D=3D IA64_OPND_CPUID_R3) - { - int regno =3D CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_GR; - if (regno >=3D 0 && regno < NELEMS (gr_values) - && KNOWN (regno)) - { - specs[count] =3D tmpl; - specs[count++].index =3D gr_values[regno].value & 0xFF; - } - else - { - specs[count] =3D tmpl; - specs[count++].specific =3D 0; - } - } - } - else - { - UNHANDLED; - } - break; - - case IA64_RS_DBR: /* four or more registers */ - if (note =3D=3D 3) - { - if (idesc->operands[!rsrc_write] =3D=3D IA64_OPND_DBR_R3) - { - int regno =3D CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_GR; - if (regno >=3D 0 && regno < NELEMS (gr_values) - && KNOWN (regno)) - { - specs[count] =3D tmpl; - specs[count++].index =3D gr_values[regno].value & 0xFF; - } - else - { - specs[count] =3D tmpl; - specs[count++].specific =3D 0; - } - } - } - else if (note =3D=3D 0 && !rsrc_write) - { - specs[count] =3D tmpl; - specs[count++].specific =3D 0; - } - else - { - UNHANDLED; - } - break; - - case IA64_RS_IBR: /* four or more registers */ - if (note =3D=3D 3) - { - if (idesc->operands[!rsrc_write] =3D=3D IA64_OPND_IBR_R3) - { - int regno =3D CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_GR; - if (regno >=3D 0 && regno < NELEMS (gr_values) - && KNOWN (regno)) - { - specs[count] =3D tmpl; - specs[count++].index =3D gr_values[regno].value & 0xFF; - } - else - { - specs[count] =3D tmpl; - specs[count++].specific =3D 0; - } - } - } - else - { - UNHANDLED; - } - break; - - case IA64_RS_MSR: - if (note =3D=3D 5) - { - /* These are implementation specific. Force all references to - conflict with all other references. */ - specs[count] =3D tmpl; - specs[count++].specific =3D 0; - } - else - { - UNHANDLED; - } - break; - - case IA64_RS_PKR: /* 16 or more registers */ - if (note =3D=3D 3 || note =3D=3D 4) - { - if (idesc->operands[!rsrc_write] =3D=3D IA64_OPND_PKR_R3) - { - int regno =3D CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_GR; - if (regno >=3D 0 && regno < NELEMS (gr_values) - && KNOWN (regno)) - { - if (note =3D=3D 3) - { - specs[count] =3D tmpl; - specs[count++].index =3D gr_values[regno].value & 0xFF; - } - else - for (i =3D 0; i < NELEMS (gr_values); i++) - { - /* Uses all registers *except* the one in R3. */ - if ((unsigned)i !=3D (gr_values[regno].value & 0xFF)) - { - specs[count] =3D tmpl; - specs[count++].index =3D i; - } - } - } - else - { - specs[count] =3D tmpl; - specs[count++].specific =3D 0; - } - } - } - else if (note =3D=3D 0) - { - /* probe et al. */ - specs[count] =3D tmpl; - specs[count++].specific =3D 0; - } - break; - - case IA64_RS_PMC: /* four or more registers */ - if (note =3D=3D 3) - { - if (idesc->operands[!rsrc_write] =3D=3D IA64_OPND_PMC_R3 - || (!rsrc_write && idesc->operands[1] =3D=3D IA64_OPND_PMD_R3)) - - { - int reg_index =3D ((idesc->operands[1] =3D=3D IA64_OPND_R3 && !rsrc= _write) - ? 1 : !rsrc_write); - int regno =3D CURR_SLOT.opnd[reg_index].X_add_number - REG_GR; - if (regno >=3D 0 && regno < NELEMS (gr_values) - && KNOWN (regno)) - { - specs[count] =3D tmpl; - specs[count++].index =3D gr_values[regno].value & 0xFF; - } - else - { - specs[count] =3D tmpl; - specs[count++].specific =3D 0; - } - } - } - else - { - UNHANDLED; - } - break; - - case IA64_RS_PMD: /* four or more registers */ - if (note =3D=3D 3) - { - if (idesc->operands[!rsrc_write] =3D=3D IA64_OPND_PMD_R3) - { - int regno =3D CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_GR; - if (regno >=3D 0 && regno < NELEMS (gr_values) - && KNOWN (regno)) - { - specs[count] =3D tmpl; - specs[count++].index =3D gr_values[regno].value & 0xFF; - } - else - { - specs[count] =3D tmpl; - specs[count++].specific =3D 0; - } - } - } - else - { - UNHANDLED; - } - break; - - case IA64_RS_RR: /* eight registers */ - if (note =3D=3D 6) - { - if (idesc->operands[!rsrc_write] =3D=3D IA64_OPND_RR_R3) - { - int regno =3D CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_GR; - if (regno >=3D 0 && regno < NELEMS (gr_values) - && KNOWN (regno)) - { - specs[count] =3D tmpl; - specs[count++].index =3D (gr_values[regno].value >> 61) & 0x7; - } - else - { - specs[count] =3D tmpl; - specs[count++].specific =3D 0; - } - } - } - else if (note =3D=3D 0 && !rsrc_write) - { - specs[count] =3D tmpl; - specs[count++].specific =3D 0; - } - else - { - UNHANDLED; - } - break; - - case IA64_RS_CR_IRR: - if (note =3D=3D 0) - { - /* handle mov-from-CR-IVR; it's a read that writes CR[IRR] */ - int regno =3D CURR_SLOT.opnd[1].X_add_number - REG_CR; - if (rsrc_write - && idesc->operands[1] =3D=3D IA64_OPND_CR3 - && regno =3D=3D CR_IVR) - { - for (i =3D 0; i < 4; i++) - { - specs[count] =3D tmpl; - specs[count++].index =3D CR_IRR0 + i; - } - } - } - else if (note =3D=3D 1) - { - int regno =3D CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_CR; - if (idesc->operands[!rsrc_write] =3D=3D IA64_OPND_CR3 - && regno >=3D CR_IRR0 - && regno <=3D CR_IRR3) - { - specs[count] =3D tmpl; - specs[count++].index =3D regno; - } - } - else - { - UNHANDLED; - } - break; - - case IA64_RS_CR_IIB: - if (note !=3D 0) - { - UNHANDLED; - } - else - { - int regno =3D CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_CR; - if (idesc->operands[!rsrc_write] =3D=3D IA64_OPND_CR3 - && (regno =3D=3D CR_IIB0 || regno =3D=3D CR_IIB1)) - { - specs[count] =3D tmpl; - specs[count++].index =3D regno; - } - } - break; - - case IA64_RS_CR_LRR: - if (note !=3D 1) - { - UNHANDLED; - } - else - { - int regno =3D CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_CR; - if (idesc->operands[!rsrc_write] =3D=3D IA64_OPND_CR3 - && (regno =3D=3D CR_LRR0 || regno =3D=3D CR_LRR1)) - { - specs[count] =3D tmpl; - specs[count++].index =3D regno; - } - } - break; - - case IA64_RS_CR: - if (note =3D=3D 1) - { - if (idesc->operands[!rsrc_write] =3D=3D IA64_OPND_CR3) - { - specs[count] =3D tmpl; - specs[count++].index =3D - CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_CR; - } - } - else - { - UNHANDLED; - } - break; - - case IA64_RS_DAHR: - if (note =3D=3D 0) - { - if (idesc->operands[!rsrc_write] =3D=3D IA64_OPND_DAHR3) - { - specs[count] =3D tmpl; - specs[count++].index =3D - CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_DAHR; - } - } - else - { - UNHANDLED; - } - break; - - case IA64_RS_FR: - case IA64_RS_FRb: - if (note !=3D 1) - { - UNHANDLED; - } - else if (rsrc_write) - { - if (dep->specifier =3D=3D IA64_RS_FRb - && idesc->operands[0] =3D=3D IA64_OPND_F1) - { - specs[count] =3D tmpl; - specs[count++].index =3D CURR_SLOT.opnd[0].X_add_number - REG_FR; - } - } - else - { - for (i =3D idesc->num_outputs; i < NELEMS (idesc->operands); i++) - { - if (idesc->operands[i] =3D=3D IA64_OPND_F2 - || idesc->operands[i] =3D=3D IA64_OPND_F3 - || idesc->operands[i] =3D=3D IA64_OPND_F4) - { - specs[count] =3D tmpl; - specs[count++].index =3D - CURR_SLOT.opnd[i].X_add_number - REG_FR; - } - } - } - break; - - case IA64_RS_GR: - if (note =3D=3D 13) - { - /* This reference applies only to the GR whose value is loaded with - data returned from memory. */ - specs[count] =3D tmpl; - specs[count++].index =3D CURR_SLOT.opnd[0].X_add_number - REG_GR; - } - else if (note =3D=3D 1) - { - if (rsrc_write) - { - for (i =3D 0; i < idesc->num_outputs; i++) - if (idesc->operands[i] =3D=3D IA64_OPND_R1 - || idesc->operands[i] =3D=3D IA64_OPND_R2 - || idesc->operands[i] =3D=3D IA64_OPND_R3) - { - specs[count] =3D tmpl; - specs[count++].index =3D - CURR_SLOT.opnd[i].X_add_number - REG_GR; - } - if (idesc->flags & IA64_OPCODE_POSTINC) - for (i =3D 0; i < NELEMS (idesc->operands); i++) - if (idesc->operands[i] =3D=3D IA64_OPND_MR3) - { - specs[count] =3D tmpl; - specs[count++].index =3D - CURR_SLOT.opnd[i].X_add_number - REG_GR; - } - } - else - { - /* Look for anything that reads a GR. */ - for (i =3D 0; i < NELEMS (idesc->operands); i++) - { - if (idesc->operands[i] =3D=3D IA64_OPND_MR3 - || idesc->operands[i] =3D=3D IA64_OPND_CPUID_R3 - || idesc->operands[i] =3D=3D IA64_OPND_DBR_R3 - || idesc->operands[i] =3D=3D IA64_OPND_IBR_R3 - || idesc->operands[i] =3D=3D IA64_OPND_MSR_R3 - || idesc->operands[i] =3D=3D IA64_OPND_PKR_R3 - || idesc->operands[i] =3D=3D IA64_OPND_PMC_R3 - || idesc->operands[i] =3D=3D IA64_OPND_PMD_R3 - || idesc->operands[i] =3D=3D IA64_OPND_DAHR_R3 - || idesc->operands[i] =3D=3D IA64_OPND_RR_R3 - || ((i >=3D idesc->num_outputs) - && (idesc->operands[i] =3D=3D IA64_OPND_R1 - || idesc->operands[i] =3D=3D IA64_OPND_R2 - || idesc->operands[i] =3D=3D IA64_OPND_R3 - /* addl source register. */ - || idesc->operands[i] =3D=3D IA64_OPND_R3_2))) - { - specs[count] =3D tmpl; - specs[count++].index =3D - CURR_SLOT.opnd[i].X_add_number - REG_GR; - } - } - } - } - else - { - UNHANDLED; - } - break; - - /* This is the same as IA64_RS_PRr, except that the register range is - from 1 - 15, and there are no rotating register reads/writes here. */ - case IA64_RS_PR: - if (note =3D=3D 0) - { - for (i =3D 1; i < 16; i++) - { - specs[count] =3D tmpl; - specs[count++].index =3D i; - } - } - else if (note =3D=3D 7) - { - valueT mask =3D 0; - /* Mark only those registers indicated by the mask. */ - if (rsrc_write) - { - mask =3D CURR_SLOT.opnd[2].X_add_number; - for (i =3D 1; i < 16; i++) - if (mask & ((valueT) 1 << i)) - { - specs[count] =3D tmpl; - specs[count++].index =3D i; - } - } - else - { - UNHANDLED; - } - } - else if (note =3D=3D 11) /* note 11 implies note 1 as well */ - { - if (rsrc_write) - { - for (i =3D 0; i < idesc->num_outputs; i++) - { - if (idesc->operands[i] =3D=3D IA64_OPND_P1 - || idesc->operands[i] =3D=3D IA64_OPND_P2) - { - int regno =3D CURR_SLOT.opnd[i].X_add_number - REG_P; - if (regno >=3D 1 && regno < 16) - { - specs[count] =3D tmpl; - specs[count++].index =3D regno; - } - } - } - } - else - { - UNHANDLED; - } - } - else if (note =3D=3D 12) - { - if (CURR_SLOT.qp_regno >=3D 1 && CURR_SLOT.qp_regno < 16) - { - specs[count] =3D tmpl; - specs[count++].index =3D CURR_SLOT.qp_regno; - } - } - else if (note =3D=3D 1) - { - if (rsrc_write) - { - int p1 =3D CURR_SLOT.opnd[0].X_add_number - REG_P; - int p2 =3D CURR_SLOT.opnd[1].X_add_number - REG_P; - int or_andcm =3D strstr (idesc->name, "or.andcm") !=3D NULL; - int and_orcm =3D strstr (idesc->name, "and.orcm") !=3D NULL; - - if ((idesc->operands[0] =3D=3D IA64_OPND_P1 - || idesc->operands[0] =3D=3D IA64_OPND_P2) - && p1 >=3D 1 && p1 < 16) - { - specs[count] =3D tmpl; - specs[count].cmp_type =3D - (or_andcm ? CMP_OR : (and_orcm ? CMP_AND : CMP_NONE)); - specs[count++].index =3D p1; - } - if ((idesc->operands[1] =3D=3D IA64_OPND_P1 - || idesc->operands[1] =3D=3D IA64_OPND_P2) - && p2 >=3D 1 && p2 < 16) - { - specs[count] =3D tmpl; - specs[count].cmp_type =3D - (or_andcm ? CMP_AND : (and_orcm ? CMP_OR : CMP_NONE)); - specs[count++].index =3D p2; - } - } - else - { - if (CURR_SLOT.qp_regno >=3D 1 && CURR_SLOT.qp_regno < 16) - { - specs[count] =3D tmpl; - specs[count++].index =3D CURR_SLOT.qp_regno; - } - if (idesc->operands[1] =3D=3D IA64_OPND_PR) - { - for (i =3D 1; i < 16; i++) - { - specs[count] =3D tmpl; - specs[count++].index =3D i; - } - } - } - } - else - { - UNHANDLED; - } - break; - - /* This is the general case for PRs. IA64_RS_PR and IA64_RS_PR63 are - simplified cases of this. */ - case IA64_RS_PRr: - if (note =3D=3D 0) - { - for (i =3D 16; i < 63; i++) - { - specs[count] =3D tmpl; - specs[count++].index =3D i; - } - } - else if (note =3D=3D 7) - { - valueT mask =3D 0; - /* Mark only those registers indicated by the mask. */ - if (rsrc_write - && idesc->operands[0] =3D=3D IA64_OPND_PR) - { - mask =3D CURR_SLOT.opnd[2].X_add_number; - if (mask & ((valueT) 1 << 16)) - for (i =3D 16; i < 63; i++) - { - specs[count] =3D tmpl; - specs[count++].index =3D i; - } - } - else if (rsrc_write - && idesc->operands[0] =3D=3D IA64_OPND_PR_ROT) - { - for (i =3D 16; i < 63; i++) - { - specs[count] =3D tmpl; - specs[count++].index =3D i; - } - } - else - { - UNHANDLED; - } - } - else if (note =3D=3D 11) /* note 11 implies note 1 as well */ - { - if (rsrc_write) - { - for (i =3D 0; i < idesc->num_outputs; i++) - { - if (idesc->operands[i] =3D=3D IA64_OPND_P1 - || idesc->operands[i] =3D=3D IA64_OPND_P2) - { - int regno =3D CURR_SLOT.opnd[i].X_add_number - REG_P; - if (regno >=3D 16 && regno < 63) - { - specs[count] =3D tmpl; - specs[count++].index =3D regno; - } - } - } - } - else - { - UNHANDLED; - } - } - else if (note =3D=3D 12) - { - if (CURR_SLOT.qp_regno >=3D 16 && CURR_SLOT.qp_regno < 63) - { - specs[count] =3D tmpl; - specs[count++].index =3D CURR_SLOT.qp_regno; - } - } - else if (note =3D=3D 1) - { - if (rsrc_write) - { - int p1 =3D CURR_SLOT.opnd[0].X_add_number - REG_P; - int p2 =3D CURR_SLOT.opnd[1].X_add_number - REG_P; - int or_andcm =3D strstr (idesc->name, "or.andcm") !=3D NULL; - int and_orcm =3D strstr (idesc->name, "and.orcm") !=3D NULL; - - if ((idesc->operands[0] =3D=3D IA64_OPND_P1 - || idesc->operands[0] =3D=3D IA64_OPND_P2) - && p1 >=3D 16 && p1 < 63) - { - specs[count] =3D tmpl; - specs[count].cmp_type =3D - (or_andcm ? CMP_OR : (and_orcm ? CMP_AND : CMP_NONE)); - specs[count++].index =3D p1; - } - if ((idesc->operands[1] =3D=3D IA64_OPND_P1 - || idesc->operands[1] =3D=3D IA64_OPND_P2) - && p2 >=3D 16 && p2 < 63) - { - specs[count] =3D tmpl; - specs[count].cmp_type =3D - (or_andcm ? CMP_AND : (and_orcm ? CMP_OR : CMP_NONE)); - specs[count++].index =3D p2; - } - } - else - { - if (CURR_SLOT.qp_regno >=3D 16 && CURR_SLOT.qp_regno < 63) - { - specs[count] =3D tmpl; - specs[count++].index =3D CURR_SLOT.qp_regno; - } - if (idesc->operands[1] =3D=3D IA64_OPND_PR) - { - for (i =3D 16; i < 63; i++) - { - specs[count] =3D tmpl; - specs[count++].index =3D i; - } - } - } - } - else - { - UNHANDLED; - } - break; - - case IA64_RS_PSR: - /* Verify that the instruction is using the PSR bit indicated in - dep->regindex. */ - if (note =3D=3D 0) - { - if (idesc->operands[!rsrc_write] =3D=3D IA64_OPND_PSR_UM) - { - if (dep->regindex < 6) - { - specs[count++] =3D tmpl; - } - } - else if (idesc->operands[!rsrc_write] =3D=3D IA64_OPND_PSR) - { - if (dep->regindex < 32 - || dep->regindex =3D=3D 35 - || dep->regindex =3D=3D 36 - || (!rsrc_write && dep->regindex =3D=3D PSR_CPL)) - { - specs[count++] =3D tmpl; - } - } - else if (idesc->operands[!rsrc_write] =3D=3D IA64_OPND_PSR_L) - { - if (dep->regindex < 32 - || dep->regindex =3D=3D 35 - || dep->regindex =3D=3D 36 - || (rsrc_write && dep->regindex =3D=3D PSR_CPL)) - { - specs[count++] =3D tmpl; - } - } - else - { - /* Several PSR bits have very specific dependencies. */ - switch (dep->regindex) - { - default: - specs[count++] =3D tmpl; - break; - case PSR_IC: - if (rsrc_write) - { - specs[count++] =3D tmpl; - } - else - { - /* Only certain CR accesses use PSR.ic */ - if (idesc->operands[0] =3D=3D IA64_OPND_CR3 - || idesc->operands[1] =3D=3D IA64_OPND_CR3) - { - int reg_index =3D - ((idesc->operands[0] =3D=3D IA64_OPND_CR3) - ? 0 : 1); - int regno =3D - CURR_SLOT.opnd[reg_index].X_add_number - REG_CR; - - switch (regno) - { - default: - break; - case CR_ITIR: - case CR_IFS: - case CR_IIM: - case CR_IIP: - case CR_IPSR: - case CR_ISR: - case CR_IFA: - case CR_IHA: - case CR_IIB0: - case CR_IIB1: - case CR_IIPA: - specs[count++] =3D tmpl; - break; - } - } - } - break; - case PSR_CPL: - if (rsrc_write) - { - specs[count++] =3D tmpl; - } - else - { - /* Only some AR accesses use cpl */ - if (idesc->operands[0] =3D=3D IA64_OPND_AR3 - || idesc->operands[1] =3D=3D IA64_OPND_AR3) - { - int reg_index =3D - ((idesc->operands[0] =3D=3D IA64_OPND_AR3) - ? 0 : 1); - int regno =3D - CURR_SLOT.opnd[reg_index].X_add_number - REG_AR; - - if (regno =3D=3D AR_ITC - || regno =3D=3D AR_RUC - || (reg_index =3D=3D 0 - && (regno =3D=3D AR_RSC - || (regno >=3D AR_K0 - && regno <=3D AR_K7)))) - { - specs[count++] =3D tmpl; - } - } - else - { - specs[count++] =3D tmpl; - } - break; - } - } - } - } - else if (note =3D=3D 7) - { - valueT mask =3D 0; - if (idesc->operands[0] =3D=3D IA64_OPND_IMMU24) - { - mask =3D CURR_SLOT.opnd[0].X_add_number; - } - else - { - UNHANDLED; - } - if (mask & ((valueT) 1 << dep->regindex)) - { - specs[count++] =3D tmpl; - } - } - else if (note =3D=3D 8) - { - int min =3D dep->regindex =3D=3D PSR_DFL ? 2 : 32; - int max =3D dep->regindex =3D=3D PSR_DFL ? 31 : 127; - /* dfh is read on FR32-127; dfl is read on FR2-31 */ - for (i =3D 0; i < NELEMS (idesc->operands); i++) - { - if (idesc->operands[i] =3D=3D IA64_OPND_F1 - || idesc->operands[i] =3D=3D IA64_OPND_F2 - || idesc->operands[i] =3D=3D IA64_OPND_F3 - || idesc->operands[i] =3D=3D IA64_OPND_F4) - { - int reg =3D CURR_SLOT.opnd[i].X_add_number - REG_FR; - if (reg >=3D min && reg <=3D max) - { - specs[count++] =3D tmpl; - } - } - } - } - else if (note =3D=3D 9) - { - int min =3D dep->regindex =3D=3D PSR_MFL ? 2 : 32; - int max =3D dep->regindex =3D=3D PSR_MFL ? 31 : 127; - /* mfh is read on writes to FR32-127; mfl is read on writes to - FR2-31 */ - for (i =3D 0; i < idesc->num_outputs; i++) - { - if (idesc->operands[i] =3D=3D IA64_OPND_F1) - { - int reg =3D CURR_SLOT.opnd[i].X_add_number - REG_FR; - if (reg >=3D min && reg <=3D max) - { - specs[count++] =3D tmpl; - } - } - } - } - else if (note =3D=3D 10) - { - for (i =3D 0; i < NELEMS (idesc->operands); i++) - { - if (idesc->operands[i] =3D=3D IA64_OPND_R1 - || idesc->operands[i] =3D=3D IA64_OPND_R2 - || idesc->operands[i] =3D=3D IA64_OPND_R3) - { - int regno =3D CURR_SLOT.opnd[i].X_add_number - REG_GR; - if (regno >=3D 16 && regno <=3D 31) - { - specs[count++] =3D tmpl; - } - } - } - } - else - { - UNHANDLED; - } - break; - - case IA64_RS_AR_FPSR: - if (idesc->operands[!rsrc_write] =3D=3D IA64_OPND_AR3) - { - int regno =3D CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_AR; - if (regno =3D=3D AR_FPSR) - { - specs[count++] =3D tmpl; - } - } - else - { - specs[count++] =3D tmpl; - } - break; - - case IA64_RS_ARX: - /* Handle all AR[REG] resources */ - if (note =3D=3D 0 || note =3D=3D 1) - { - int regno =3D CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_AR; - if (idesc->operands[!rsrc_write] =3D=3D IA64_OPND_AR3 - && regno =3D=3D dep->regindex) - { - specs[count++] =3D tmpl; - } - /* other AR[REG] resources may be affected by AR accesses */ - else if (idesc->operands[0] =3D=3D IA64_OPND_AR3) - { - /* AR[] writes */ - regno =3D CURR_SLOT.opnd[0].X_add_number - REG_AR; - switch (dep->regindex) - { - default: - break; - case AR_BSP: - case AR_RNAT: - if (regno =3D=3D AR_BSPSTORE) - { - specs[count++] =3D tmpl; - } - /* Fall through. */ - case AR_RSC: - if (!rsrc_write && - (regno =3D=3D AR_BSPSTORE - || regno =3D=3D AR_RNAT)) - { - specs[count++] =3D tmpl; - } - break; - } - } - else if (idesc->operands[1] =3D=3D IA64_OPND_AR3) - { - /* AR[] reads */ - regno =3D CURR_SLOT.opnd[1].X_add_number - REG_AR; - switch (dep->regindex) - { - default: - break; - case AR_RSC: - if (regno =3D=3D AR_BSPSTORE || regno =3D=3D AR_RNAT) - { - specs[count++] =3D tmpl; - } - break; - } - } - else - { - specs[count++] =3D tmpl; - } - } - else - { - UNHANDLED; - } - break; - - case IA64_RS_CRX: - /* Handle all CR[REG] resources. - ??? FIXME: The rule 17 isn't really handled correctly. */ - if (note =3D=3D 0 || note =3D=3D 1 || note =3D=3D 17) - { - if (idesc->operands[!rsrc_write] =3D=3D IA64_OPND_CR3) - { - int regno =3D CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_CR; - if (regno =3D=3D dep->regindex) - { - specs[count++] =3D tmpl; - } - else if (!rsrc_write) - { - /* Reads from CR[IVR] affect other resources. */ - if (regno =3D=3D CR_IVR) - { - if ((dep->regindex >=3D CR_IRR0 - && dep->regindex <=3D CR_IRR3) - || dep->regindex =3D=3D CR_TPR) - { - specs[count++] =3D tmpl; - } - } - } - } - else - { - specs[count++] =3D tmpl; - } - } - else - { - UNHANDLED; - } - break; - - case IA64_RS_INSERVICE: - /* look for write of EOI (67) or read of IVR (65) */ - if ((idesc->operands[0] =3D=3D IA64_OPND_CR3 - && CURR_SLOT.opnd[0].X_add_number - REG_CR =3D=3D CR_EOI) - || (idesc->operands[1] =3D=3D IA64_OPND_CR3 - && CURR_SLOT.opnd[1].X_add_number - REG_CR =3D=3D CR_IVR)) - { - specs[count++] =3D tmpl; - } - break; - - case IA64_RS_GR0: - if (note =3D=3D 1) - { - specs[count++] =3D tmpl; - } - else - { - UNHANDLED; - } - break; - - case IA64_RS_CFM: - if (note !=3D 2) - { - specs[count++] =3D tmpl; - } - else - { - /* Check if any of the registers accessed are in the rotating region. - mov to/from pr accesses CFM only when qp_regno is in the rotating - region */ - for (i =3D 0; i < NELEMS (idesc->operands); i++) - { - if (idesc->operands[i] =3D=3D IA64_OPND_R1 - || idesc->operands[i] =3D=3D IA64_OPND_R2 - || idesc->operands[i] =3D=3D IA64_OPND_R3) - { - int num =3D CURR_SLOT.opnd[i].X_add_number - REG_GR; - /* Assumes that md.rot.num_regs is always valid */ - if (md.rot.num_regs > 0 - && num > 31 - && num < 31 + md.rot.num_regs) - { - specs[count] =3D tmpl; - specs[count++].specific =3D 0; - } - } - else if (idesc->operands[i] =3D=3D IA64_OPND_F1 - || idesc->operands[i] =3D=3D IA64_OPND_F2 - || idesc->operands[i] =3D=3D IA64_OPND_F3 - || idesc->operands[i] =3D=3D IA64_OPND_F4) - { - int num =3D CURR_SLOT.opnd[i].X_add_number - REG_FR; - if (num > 31) - { - specs[count] =3D tmpl; - specs[count++].specific =3D 0; - } - } - else if (idesc->operands[i] =3D=3D IA64_OPND_P1 - || idesc->operands[i] =3D=3D IA64_OPND_P2) - { - int num =3D CURR_SLOT.opnd[i].X_add_number - REG_P; - if (num > 15) - { - specs[count] =3D tmpl; - specs[count++].specific =3D 0; - } - } - } - if (CURR_SLOT.qp_regno > 15) - { - specs[count] =3D tmpl; - specs[count++].specific =3D 0; - } - } - break; - - /* This is the same as IA64_RS_PRr, except simplified to account for - the fact that there is only one register. */ - case IA64_RS_PR63: - if (note =3D=3D 0) - { - specs[count++] =3D tmpl; - } - else if (note =3D=3D 7) - { - valueT mask =3D 0; - if (idesc->operands[2] =3D=3D IA64_OPND_IMM17) - mask =3D CURR_SLOT.opnd[2].X_add_number; - if (mask & ((valueT) 1 << 63)) - specs[count++] =3D tmpl; - } - else if (note =3D=3D 11) - { - if ((idesc->operands[0] =3D=3D IA64_OPND_P1 - && CURR_SLOT.opnd[0].X_add_number - REG_P =3D=3D 63) - || (idesc->operands[1] =3D=3D IA64_OPND_P2 - && CURR_SLOT.opnd[1].X_add_number - REG_P =3D=3D 63)) - { - specs[count++] =3D tmpl; - } - } - else if (note =3D=3D 12) - { - if (CURR_SLOT.qp_regno =3D=3D 63) - { - specs[count++] =3D tmpl; - } - } - else if (note =3D=3D 1) - { - if (rsrc_write) - { - int p1 =3D CURR_SLOT.opnd[0].X_add_number - REG_P; - int p2 =3D CURR_SLOT.opnd[1].X_add_number - REG_P; - int or_andcm =3D strstr (idesc->name, "or.andcm") !=3D NULL; - int and_orcm =3D strstr (idesc->name, "and.orcm") !=3D NULL; - - if (p1 =3D=3D 63 - && (idesc->operands[0] =3D=3D IA64_OPND_P1 - || idesc->operands[0] =3D=3D IA64_OPND_P2)) - { - specs[count] =3D tmpl; - specs[count++].cmp_type =3D - (or_andcm ? CMP_OR : (and_orcm ? CMP_AND : CMP_NONE)); - } - if (p2 =3D=3D 63 - && (idesc->operands[1] =3D=3D IA64_OPND_P1 - || idesc->operands[1] =3D=3D IA64_OPND_P2)) - { - specs[count] =3D tmpl; - specs[count++].cmp_type =3D - (or_andcm ? CMP_AND : (and_orcm ? CMP_OR : CMP_NONE)); - } - } - else - { - if (CURR_SLOT.qp_regno =3D=3D 63) - { - specs[count++] =3D tmpl; - } - } - } - else - { - UNHANDLED; - } - break; - - case IA64_RS_RSE: - /* FIXME we can identify some individual RSE written resources, but = RSE - read resources have not yet been completely identified, so for now - treat RSE as a single resource */ - if (startswith (idesc->name, "mov")) - { - if (rsrc_write) - { - if (idesc->operands[0] =3D=3D IA64_OPND_AR3 - && CURR_SLOT.opnd[0].X_add_number - REG_AR =3D=3D AR_BSPSTORE) - { - specs[count++] =3D tmpl; - } - } - else - { - if (idesc->operands[0] =3D=3D IA64_OPND_AR3) - { - if (CURR_SLOT.opnd[0].X_add_number - REG_AR =3D=3D AR_BSPSTORE - || CURR_SLOT.opnd[0].X_add_number - REG_AR =3D=3D AR_RNAT) - { - specs[count++] =3D tmpl; - } - } - else if (idesc->operands[1] =3D=3D IA64_OPND_AR3) - { - if (CURR_SLOT.opnd[1].X_add_number - REG_AR =3D=3D AR_BSP - || CURR_SLOT.opnd[1].X_add_number - REG_AR =3D=3D AR_BSPSTORE - || CURR_SLOT.opnd[1].X_add_number - REG_AR =3D=3D AR_RNAT) - { - specs[count++] =3D tmpl; - } - } - } - } - else - { - specs[count++] =3D tmpl; - } - break; - - case IA64_RS_ANY: - /* FIXME -- do any of these need to be non-specific? */ - specs[count++] =3D tmpl; - break; - - default: - as_bad (_("Unrecognized dependency specifier %d\n"), dep->specifier); - break; - } - - return count; -} - -/* Clear branch flags on marked resources. This breaks the link between t= he - QP of the marking instruction and a subsequent branch on the same QP. = */ - -static void -clear_qp_branch_flag (valueT mask) -{ - int i; - for (i =3D 0; i < regdepslen; i++) - { - valueT bit =3D ((valueT) 1 << regdeps[i].qp_regno); - if ((bit & mask) !=3D 0) - { - regdeps[i].link_to_qp_branch =3D 0; - } - } -} - -/* MASK contains 2 and only 2 PRs which are mutually exclusive. Remove - any mutexes which contain one of the PRs and create new ones when - needed. */ - -static int -update_qp_mutex (valueT mask) -{ - int i; - int add =3D 0; - - i =3D 0; - while (i < qp_mutexeslen) - { - if ((qp_mutexes[i].prmask & mask) !=3D 0) - { - /* If it destroys and creates the same mutex, do nothing. */ - if (qp_mutexes[i].prmask =3D=3D mask - && qp_mutexes[i].path =3D=3D md.path) - { - i++; - add =3D -1; - } - else - { - int keep =3D 0; - - if (md.debug_dv) - { - fprintf (stderr, " Clearing mutex relation"); - print_prmask (qp_mutexes[i].prmask); - fprintf (stderr, "\n"); - } - - /* Deal with the old mutex with more than 3+ PRs only if - the new mutex on the same execution path with it. - - FIXME: The 3+ mutex support is incomplete. - dot_pred_rel () may be a better place to fix it. */ - if (qp_mutexes[i].path =3D=3D md.path) - { - /* If it is a proper subset of the mutex, create a - new mutex. */ - if (add =3D=3D 0 - && (qp_mutexes[i].prmask & mask) =3D=3D mask) - add =3D 1; - - qp_mutexes[i].prmask &=3D ~mask; - if (qp_mutexes[i].prmask & (qp_mutexes[i].prmask - 1)) - { - /* Modify the mutex if there are more than one - PR left. */ - keep =3D 1; - i++; - } - } - - if (keep =3D=3D 0) - /* Remove the mutex. */ - qp_mutexes[i] =3D qp_mutexes[--qp_mutexeslen]; - } - } - else - ++i; - } - - if (add =3D=3D 1) - add_qp_mutex (mask); - - return add; -} - -/* Remove any mutexes which contain any of the PRs indicated in the mask. - - Any changes to a PR clears the mutex relations which include that PR. = */ - -static void -clear_qp_mutex (valueT mask) -{ - int i; - - i =3D 0; - while (i < qp_mutexeslen) - { - if ((qp_mutexes[i].prmask & mask) !=3D 0) - { - if (md.debug_dv) - { - fprintf (stderr, " Clearing mutex relation"); - print_prmask (qp_mutexes[i].prmask); - fprintf (stderr, "\n"); - } - qp_mutexes[i] =3D qp_mutexes[--qp_mutexeslen]; - } - else - ++i; - } -} - -/* Clear implies relations which contain PRs in the given masks. - P1_MASK indicates the source of the implies relation, while P2_MASK - indicates the implied PR. */ - -static void -clear_qp_implies (valueT p1_mask, valueT p2_mask) -{ - int i; - - i =3D 0; - while (i < qp_implieslen) - { - if ((((valueT) 1 << qp_implies[i].p1) & p1_mask) !=3D 0 - || (((valueT) 1 << qp_implies[i].p2) & p2_mask) !=3D 0) - { - if (md.debug_dv) - fprintf (stderr, "Clearing implied relation PR%d->PR%d\n", - qp_implies[i].p1, qp_implies[i].p2); - qp_implies[i] =3D qp_implies[--qp_implieslen]; - } - else - ++i; - } -} - -/* Add the PRs specified to the list of implied relations. */ - -static void -add_qp_imply (int p1, int p2) -{ - valueT mask; - valueT bit; - int i; - - /* p0 is not meaningful here. */ - if (p1 =3D=3D 0 || p2 =3D=3D 0) - abort (); - - if (p1 =3D=3D p2) - return; - - /* If it exists already, ignore it. */ - for (i =3D 0; i < qp_implieslen; i++) - { - if (qp_implies[i].p1 =3D=3D p1 - && qp_implies[i].p2 =3D=3D p2 - && qp_implies[i].path =3D=3D md.path - && !qp_implies[i].p2_branched) - return; - } - - if (qp_implieslen =3D=3D qp_impliestotlen) - { - qp_impliestotlen +=3D 20; - qp_implies =3D XRESIZEVEC (struct qp_imply, qp_implies, qp_impliesto= tlen); - } - if (md.debug_dv) - fprintf (stderr, " Registering PR%d implies PR%d\n", p1, p2); - qp_implies[qp_implieslen].p1 =3D p1; - qp_implies[qp_implieslen].p2 =3D p2; - qp_implies[qp_implieslen].path =3D md.path; - qp_implies[qp_implieslen++].p2_branched =3D 0; - - /* Add in the implied transitive relations; for everything that p2 impli= es, - make p1 imply that, too; for everything that implies p1, make it impl= y p2 - as well. */ - for (i =3D 0; i < qp_implieslen; i++) - { - if (qp_implies[i].p1 =3D=3D p2) - add_qp_imply (p1, qp_implies[i].p2); - if (qp_implies[i].p2 =3D=3D p1) - add_qp_imply (qp_implies[i].p1, p2); - } - /* Add in mutex relations implied by this implies relation; for each mut= ex - relation containing p2, duplicate it and replace p2 with p1. */ - bit =3D (valueT) 1 << p1; - mask =3D (valueT) 1 << p2; - for (i =3D 0; i < qp_mutexeslen; i++) - { - if (qp_mutexes[i].prmask & mask) - add_qp_mutex ((qp_mutexes[i].prmask & ~mask) | bit); - } -} - -/* Add the PRs specified in the mask to the mutex list; this means that on= ly - one of the PRs can be true at any time. PR0 should never be included in - the mask. */ - -static void -add_qp_mutex (valueT mask) -{ - if (mask & 0x1) - abort (); - - if (qp_mutexeslen =3D=3D qp_mutexestotlen) - { - qp_mutexestotlen +=3D 20; - qp_mutexes =3D XRESIZEVEC (struct qpmutex, qp_mutexes, qp_mutexestot= len); - } - if (md.debug_dv) - { - fprintf (stderr, " Registering mutex on"); - print_prmask (mask); - fprintf (stderr, "\n"); - } - qp_mutexes[qp_mutexeslen].path =3D md.path; - qp_mutexes[qp_mutexeslen++].prmask =3D mask; -} - -static int -has_suffix_p (const char *name, const char *suffix) -{ - size_t namelen =3D strlen (name); - size_t sufflen =3D strlen (suffix); - - if (namelen <=3D sufflen) - return 0; - return strcmp (name + namelen - sufflen, suffix) =3D=3D 0; -} - -static void -clear_register_values (void) -{ - int i; - if (md.debug_dv) - fprintf (stderr, " Clearing register values\n"); - for (i =3D 1; i < NELEMS (gr_values); i++) - gr_values[i].known =3D 0; -} - -/* Keep track of register values/changes which affect DV tracking. - - optimization note: should add a flag to classes of insns where otherwis= e we - have to examine a group of strings to identify them. */ - -static void -note_register_values (struct ia64_opcode *idesc) -{ - valueT qp_changemask =3D 0; - int i; - - /* Invalidate values for registers being written to. */ - for (i =3D 0; i < idesc->num_outputs; i++) - { - if (idesc->operands[i] =3D=3D IA64_OPND_R1 - || idesc->operands[i] =3D=3D IA64_OPND_R2 - || idesc->operands[i] =3D=3D IA64_OPND_R3) - { - int regno =3D CURR_SLOT.opnd[i].X_add_number - REG_GR; - if (regno > 0 && regno < NELEMS (gr_values)) - gr_values[regno].known =3D 0; - } - else if (idesc->operands[i] =3D=3D IA64_OPND_R3_2) - { - int regno =3D CURR_SLOT.opnd[i].X_add_number - REG_GR; - if (regno > 0 && regno < 4) - gr_values[regno].known =3D 0; - } - else if (idesc->operands[i] =3D=3D IA64_OPND_P1 - || idesc->operands[i] =3D=3D IA64_OPND_P2) - { - int regno =3D CURR_SLOT.opnd[i].X_add_number - REG_P; - qp_changemask |=3D (valueT) 1 << regno; - } - else if (idesc->operands[i] =3D=3D IA64_OPND_PR) - { - if (idesc->operands[2] & (valueT) 0x10000) - qp_changemask =3D ~(valueT) 0x1FFFF | idesc->operands[2]; - else - qp_changemask =3D idesc->operands[2]; - break; - } - else if (idesc->operands[i] =3D=3D IA64_OPND_PR_ROT) - { - if (idesc->operands[1] & ((valueT) 1 << 43)) - qp_changemask =3D -((valueT) 1 << 44) | idesc->operands[1]; - else - qp_changemask =3D idesc->operands[1]; - qp_changemask &=3D ~(valueT) 0xFFFF; - break; - } - } - - /* Always clear qp branch flags on any PR change. */ - /* FIXME there may be exceptions for certain compares. */ - clear_qp_branch_flag (qp_changemask); - - /* Invalidate rotating registers on insns which affect RRBs in CFM. */ - if (idesc->flags & IA64_OPCODE_MOD_RRBS) - { - qp_changemask |=3D ~(valueT) 0xFFFF; - if (strcmp (idesc->name, "clrrrb.pr") !=3D 0) - { - for (i =3D 32; i < 32 + md.rot.num_regs; i++) - gr_values[i].known =3D 0; - } - clear_qp_mutex (qp_changemask); - clear_qp_implies (qp_changemask, qp_changemask); - } - /* After a call, all register values are undefined, except those marked - as "safe". */ - else if (startswith (idesc->name, "br.call") - || startswith (idesc->name, "brl.call")) - { - /* FIXME keep GR values which are marked as "safe_across_calls" */ - clear_register_values (); - clear_qp_mutex (~qp_safe_across_calls); - clear_qp_implies (~qp_safe_across_calls, ~qp_safe_across_calls); - clear_qp_branch_flag (~qp_safe_across_calls); - } - else if (is_interruption_or_rfi (idesc) - || is_taken_branch (idesc)) - { - clear_register_values (); - clear_qp_mutex (~(valueT) 0); - clear_qp_implies (~(valueT) 0, ~(valueT) 0); - } - /* Look for mutex and implies relations. */ - else if ((idesc->operands[0] =3D=3D IA64_OPND_P1 - || idesc->operands[0] =3D=3D IA64_OPND_P2) - && (idesc->operands[1] =3D=3D IA64_OPND_P1 - || idesc->operands[1] =3D=3D IA64_OPND_P2)) - { - int p1 =3D CURR_SLOT.opnd[0].X_add_number - REG_P; - int p2 =3D CURR_SLOT.opnd[1].X_add_number - REG_P; - valueT p1mask =3D (p1 !=3D 0) ? (valueT) 1 << p1 : 0; - valueT p2mask =3D (p2 !=3D 0) ? (valueT) 1 << p2 : 0; - - /* If both PRs are PR0, we can't really do anything. */ - if (p1 =3D=3D 0 && p2 =3D=3D 0) - { - if (md.debug_dv) - fprintf (stderr, " Ignoring PRs due to inclusion of p0\n"); - } - /* In general, clear mutexes and implies which include P1 or P2, - with the following exceptions. */ - else if (has_suffix_p (idesc->name, ".or.andcm") - || has_suffix_p (idesc->name, ".and.orcm")) - { - clear_qp_implies (p2mask, p1mask); - } - else if (has_suffix_p (idesc->name, ".andcm") - || has_suffix_p (idesc->name, ".and")) - { - clear_qp_implies (0, p1mask | p2mask); - } - else if (has_suffix_p (idesc->name, ".orcm") - || has_suffix_p (idesc->name, ".or")) - { - clear_qp_mutex (p1mask | p2mask); - clear_qp_implies (p1mask | p2mask, 0); - } - else - { - int added =3D 0; - - clear_qp_implies (p1mask | p2mask, p1mask | p2mask); - - /* If one of the PRs is PR0, we call clear_qp_mutex. */ - if (p1 =3D=3D 0 || p2 =3D=3D 0) - clear_qp_mutex (p1mask | p2mask); - else - added =3D update_qp_mutex (p1mask | p2mask); - - if (CURR_SLOT.qp_regno =3D=3D 0 - || has_suffix_p (idesc->name, ".unc")) - { - if (added =3D=3D 0 && p1 && p2) - add_qp_mutex (p1mask | p2mask); - if (CURR_SLOT.qp_regno !=3D 0) - { - if (p1) - add_qp_imply (p1, CURR_SLOT.qp_regno); - if (p2) - add_qp_imply (p2, CURR_SLOT.qp_regno); - } - } - } - } - /* Look for mov imm insns into GRs. */ - else if (idesc->operands[0] =3D=3D IA64_OPND_R1 - && (idesc->operands[1] =3D=3D IA64_OPND_IMM22 - || idesc->operands[1] =3D=3D IA64_OPND_IMMU64) - && CURR_SLOT.opnd[1].X_op =3D=3D O_constant - && (strcmp (idesc->name, "mov") =3D=3D 0 - || strcmp (idesc->name, "movl") =3D=3D 0)) - { - int regno =3D CURR_SLOT.opnd[0].X_add_number - REG_GR; - if (regno > 0 && regno < NELEMS (gr_values)) - { - gr_values[regno].known =3D 1; - gr_values[regno].value =3D CURR_SLOT.opnd[1].X_add_number; - gr_values[regno].path =3D md.path; - if (md.debug_dv) - fprintf (stderr, " Know gr%d =3D %" PRIx64 "\n", - regno, gr_values[regno].value); - } - } - /* Look for dep.z imm insns. */ - else if (idesc->operands[0] =3D=3D IA64_OPND_R1 - && idesc->operands[1] =3D=3D IA64_OPND_IMM8 - && strcmp (idesc->name, "dep.z") =3D=3D 0) - { - int regno =3D CURR_SLOT.opnd[0].X_add_number - REG_GR; - if (regno > 0 && regno < NELEMS (gr_values)) - { - valueT value =3D CURR_SLOT.opnd[1].X_add_number; - - if (CURR_SLOT.opnd[3].X_add_number < 64) - value &=3D ((valueT)1 << CURR_SLOT.opnd[3].X_add_number) - 1; - value <<=3D CURR_SLOT.opnd[2].X_add_number; - gr_values[regno].known =3D 1; - gr_values[regno].value =3D value; - gr_values[regno].path =3D md.path; - if (md.debug_dv) - fprintf (stderr, " Know gr%d =3D %" PRIx64 "\n", - regno, gr_values[regno].value); - } - } - else - { - clear_qp_mutex (qp_changemask); - clear_qp_implies (qp_changemask, qp_changemask); - } -} - -/* Return whether the given predicate registers are currently mutex. */ - -static int -qp_mutex (int p1, int p2, int path) -{ - int i; - valueT mask; - - if (p1 !=3D p2) - { - mask =3D ((valueT) 1 << p1) | (valueT) 1 << p2; - for (i =3D 0; i < qp_mutexeslen; i++) - { - if (qp_mutexes[i].path >=3D path - && (qp_mutexes[i].prmask & mask) =3D=3D mask) - return 1; - } - } - return 0; -} - -/* Return whether the given resource is in the given insn's list of chks - Return 1 if the conflict is absolutely determined, 2 if it's a potential - conflict. */ - -static int -resources_match (struct rsrc *rs, - struct ia64_opcode *idesc, - int note, - int qp_regno, - int path) -{ - struct rsrc specs[MAX_SPECS]; - int count; - - /* If the marked resource's qp_regno and the given qp_regno are mutex, - we don't need to check. One exception is note 11, which indicates th= at - target predicates are written regardless of PR[qp]. */ - if (qp_mutex (rs->qp_regno, qp_regno, path) - && note !=3D 11) - return 0; - - count =3D specify_resource (rs->dependency, idesc, DV_CHK, specs, note, = path); - while (count-- > 0) - { - /* UNAT checking is a bit more specific than other resources */ - if (rs->dependency->specifier =3D=3D IA64_RS_AR_UNAT - && specs[count].mem_offset.hint - && rs->mem_offset.hint) - { - if (rs->mem_offset.base =3D=3D specs[count].mem_offset.base) - { - if (((rs->mem_offset.offset >> 3) & 0x3F) =3D=3D - ((specs[count].mem_offset.offset >> 3) & 0x3F)) - return 1; - else - continue; - } - } - - /* Skip apparent PR write conflicts where both writes are an AND or = both - writes are an OR. */ - if (rs->dependency->specifier =3D=3D IA64_RS_PR - || rs->dependency->specifier =3D=3D IA64_RS_PRr - || rs->dependency->specifier =3D=3D IA64_RS_PR63) - { - if (specs[count].cmp_type !=3D CMP_NONE - && specs[count].cmp_type =3D=3D rs->cmp_type) - { - if (md.debug_dv) - fprintf (stderr, " %s on parallel compare allowed (PR%d)\n", - dv_mode[rs->dependency->mode], - rs->dependency->specifier !=3D IA64_RS_PR63 ? - specs[count].index : 63); - continue; - } - if (md.debug_dv) - fprintf (stderr, - " %s on parallel compare conflict %s vs %s on PR%d\n", - dv_mode[rs->dependency->mode], - dv_cmp_type[rs->cmp_type], - dv_cmp_type[specs[count].cmp_type], - rs->dependency->specifier !=3D IA64_RS_PR63 ? - specs[count].index : 63); - - } - - /* If either resource is not specific, conservatively assume a confl= ict - */ - if (!specs[count].specific || !rs->specific) - return 2; - else if (specs[count].index =3D=3D rs->index) - return 1; - } - - return 0; -} - -/* Indicate an instruction group break; if INSERT_STOP is non-zero, then - insert a stop to create the break. Update all resource dependencies - appropriately. If QP_REGNO is non-zero, only apply the break to resour= ces - which use the same QP_REGNO and have the link_to_qp_branch flag set. - If SAVE_CURRENT is non-zero, don't affect resources marked by the curre= nt - instruction. */ - -static void -insn_group_break (int insert_stop, int qp_regno, int save_current) -{ - int i; - - if (insert_stop && md.num_slots_in_use > 0) - PREV_SLOT.end_of_insn_group =3D 1; - - if (md.debug_dv) - { - fprintf (stderr, " Insn group break%s", - (insert_stop ? " (w/stop)" : "")); - if (qp_regno !=3D 0) - fprintf (stderr, " effective for QP=3D%d", qp_regno); - fprintf (stderr, "\n"); - } - - i =3D 0; - while (i < regdepslen) - { - const struct ia64_dependency *dep =3D regdeps[i].dependency; - - if (qp_regno !=3D 0 - && regdeps[i].qp_regno !=3D qp_regno) - { - ++i; - continue; - } - - if (save_current - && CURR_SLOT.src_file =3D=3D regdeps[i].file - && CURR_SLOT.src_line =3D=3D regdeps[i].line) - { - ++i; - continue; - } - - /* clear dependencies which are automatically cleared by a stop, or - those that have reached the appropriate state of insn serialization */ - if (dep->semantics =3D=3D IA64_DVS_IMPLIED - || dep->semantics =3D=3D IA64_DVS_IMPLIEDF - || regdeps[i].insn_srlz =3D=3D STATE_SRLZ) - { - print_dependency ("Removing", i); - regdeps[i] =3D regdeps[--regdepslen]; - } - else - { - if (dep->semantics =3D=3D IA64_DVS_DATA - || dep->semantics =3D=3D IA64_DVS_INSTR - || dep->semantics =3D=3D IA64_DVS_SPECIFIC) - { - if (regdeps[i].insn_srlz =3D=3D STATE_NONE) - regdeps[i].insn_srlz =3D STATE_STOP; - if (regdeps[i].data_srlz =3D=3D STATE_NONE) - regdeps[i].data_srlz =3D STATE_STOP; - } - ++i; - } - } -} - -/* Add the given resource usage spec to the list of active dependencies. = */ - -static void -mark_resource (struct ia64_opcode *idesc ATTRIBUTE_UNUSED, - const struct ia64_dependency *dep ATTRIBUTE_UNUSED, - struct rsrc *spec, - int depind, - int path) -{ - if (regdepslen =3D=3D regdepstotlen) - { - regdepstotlen +=3D 20; - regdeps =3D XRESIZEVEC (struct rsrc, regdeps, regdepstotlen); - } - - regdeps[regdepslen] =3D *spec; - regdeps[regdepslen].depind =3D depind; - regdeps[regdepslen].path =3D path; - regdeps[regdepslen].file =3D CURR_SLOT.src_file; - regdeps[regdepslen].line =3D CURR_SLOT.src_line; - - print_dependency ("Adding", regdepslen); - - ++regdepslen; -} - -static void -print_dependency (const char *action, int depind) -{ - if (md.debug_dv) - { - fprintf (stderr, " %s %s '%s'", - action, dv_mode[(regdeps[depind].dependency)->mode], - (regdeps[depind].dependency)->name); - if (regdeps[depind].specific && regdeps[depind].index >=3D 0) - fprintf (stderr, " (%d)", regdeps[depind].index); - if (regdeps[depind].mem_offset.hint) - fprintf (stderr, " %" PRIx64 "+%" PRIx64, - regdeps[depind].mem_offset.base, - regdeps[depind].mem_offset.offset); - fprintf (stderr, "\n"); - } -} - -static void -instruction_serialization (void) -{ - int i; - if (md.debug_dv) - fprintf (stderr, " Instruction serialization\n"); - for (i =3D 0; i < regdepslen; i++) - if (regdeps[i].insn_srlz =3D=3D STATE_STOP) - regdeps[i].insn_srlz =3D STATE_SRLZ; -} - -static void -data_serialization (void) -{ - int i =3D 0; - if (md.debug_dv) - fprintf (stderr, " Data serialization\n"); - while (i < regdepslen) - { - if (regdeps[i].data_srlz =3D=3D STATE_STOP - /* Note: as of 991210, all "other" dependencies are cleared by a - data serialization. This might change with new tables */ - || (regdeps[i].dependency)->semantics =3D=3D IA64_DVS_OTHER) - { - print_dependency ("Removing", i); - regdeps[i] =3D regdeps[--regdepslen]; - } - else - ++i; - } -} - -/* Insert stops and serializations as needed to avoid DVs. */ - -static void -remove_marked_resource (struct rsrc *rs) -{ - switch (rs->dependency->semantics) - { - case IA64_DVS_SPECIFIC: - if (md.debug_dv) - fprintf (stderr, "Implementation-specific, assume worst case...\n"); - /* Fall through. */ - case IA64_DVS_INSTR: - if (md.debug_dv) - fprintf (stderr, "Inserting instr serialization\n"); - if (rs->insn_srlz < STATE_STOP) - insn_group_break (1, 0, 0); - if (rs->insn_srlz < STATE_SRLZ) - { - struct slot oldslot =3D CURR_SLOT; - /* Manually jam a srlz.i insn into the stream */ - memset (&CURR_SLOT, 0, sizeof (CURR_SLOT)); - CURR_SLOT.user_template =3D -1; - CURR_SLOT.idesc =3D ia64_find_opcode ("srlz.i"); - instruction_serialization (); - md.curr_slot =3D (md.curr_slot + 1) % NUM_SLOTS; - if (++md.num_slots_in_use >=3D NUM_SLOTS) - emit_one_bundle (); - CURR_SLOT =3D oldslot; - } - insn_group_break (1, 0, 0); - break; - case IA64_DVS_OTHER: /* as of rev2 (991220) of the DV tables, all - "other" types of DV are eliminated - by a data serialization */ - case IA64_DVS_DATA: - if (md.debug_dv) - fprintf (stderr, "Inserting data serialization\n"); - if (rs->data_srlz < STATE_STOP) - insn_group_break (1, 0, 0); - { - struct slot oldslot =3D CURR_SLOT; - /* Manually jam a srlz.d insn into the stream */ - memset (&CURR_SLOT, 0, sizeof (CURR_SLOT)); - CURR_SLOT.user_template =3D -1; - CURR_SLOT.idesc =3D ia64_find_opcode ("srlz.d"); - data_serialization (); - md.curr_slot =3D (md.curr_slot + 1) % NUM_SLOTS; - if (++md.num_slots_in_use >=3D NUM_SLOTS) - emit_one_bundle (); - CURR_SLOT =3D oldslot; - } - break; - case IA64_DVS_IMPLIED: - case IA64_DVS_IMPLIEDF: - if (md.debug_dv) - fprintf (stderr, "Inserting stop\n"); - insn_group_break (1, 0, 0); - break; - default: - break; - } -} - -/* Check the resources used by the given opcode against the current depend= ency - list. - - The check is run once for each execution path encountered. In this cas= e, - a unique execution path is the sequence of instructions following a code - entry point, e.g. the following has three execution paths, one starting - at L0, one at L1, and one at L2. - - L0: nop - L1: add - L2: add - br.ret -*/ - -static void -check_dependencies (struct ia64_opcode *idesc) -{ - const struct ia64_opcode_dependency *opdeps =3D idesc->dependencies; - int path; - int i; - - /* Note that the number of marked resources may change within the - loop if in auto mode. */ - i =3D 0; - while (i < regdepslen) - { - struct rsrc *rs =3D ®deps[i]; - const struct ia64_dependency *dep =3D rs->dependency; - int chkind; - int note; - int start_over =3D 0; - - if (dep->semantics =3D=3D IA64_DVS_NONE - || (chkind =3D depends_on (rs->depind, idesc)) =3D=3D -1) - { - ++i; - continue; - } - - note =3D NOTE (opdeps->chks[chkind]); - - /* Check this resource against each execution path seen thus far. */ - for (path =3D 0; path <=3D md.path; path++) - { - int matchtype; - - /* If the dependency wasn't on the path being checked, ignore it. */ - if (rs->path < path) - continue; - - /* If the QP for this insn implies a QP which has branched, don't - bother checking. Ed. NOTE: I don't think this check is terribly - useful; what's the point of generating code which will only be - reached if its QP is zero? - This code was specifically inserted to handle the following code, - based on notes from Intel's DV checking code, where p1 implies p2. - - mov r4 =3D 2 - (p2) br.cond L - (p1) mov r4 =3D 7 - */ - if (CURR_SLOT.qp_regno !=3D 0) - { - int skip =3D 0; - int implies; - for (implies =3D 0; implies < qp_implieslen; implies++) - { - if (qp_implies[implies].path >=3D path - && qp_implies[implies].p1 =3D=3D CURR_SLOT.qp_regno - && qp_implies[implies].p2_branched) - { - skip =3D 1; - break; - } - } - if (skip) - continue; - } - - if ((matchtype =3D resources_match (rs, idesc, note, - CURR_SLOT.qp_regno, path)) !=3D 0) - { - char msg[1024]; - char pathmsg[256] =3D ""; - char indexmsg[256] =3D ""; - int certain =3D (matchtype =3D=3D 1 && CURR_SLOT.qp_regno =3D=3D 0); - - if (path !=3D 0) - snprintf (pathmsg, sizeof (pathmsg), - " when entry is at label '%s'", - md.entry_labels[path - 1]); - if (matchtype =3D=3D 1 && rs->index >=3D 0) - snprintf (indexmsg, sizeof (indexmsg), - ", specific resource number is %d", - rs->index); - snprintf (msg, sizeof (msg), - "Use of '%s' %s %s dependency '%s' (%s)%s%s", - idesc->name, - (certain ? "violates" : "may violate"), - dv_mode[dep->mode], dep->name, - dv_sem[dep->semantics], - pathmsg, indexmsg); - - if (md.explicit_mode) - { - as_warn ("%s", msg); - if (path < md.path) - as_warn (_("Only the first path encountering the conflict is reporte= d")); - as_warn_where (rs->file, rs->line, - _("This is the location of the conflicting usage")); - /* Don't bother checking other paths, to avoid duplicating - the same warning */ - break; - } - else - { - if (md.debug_dv) - fprintf (stderr, "%s @ %s:%d\n", msg, rs->file, rs->line); - - remove_marked_resource (rs); - - /* since the set of dependencies has changed, start over */ - /* FIXME -- since we're removing dvs as we go, we - probably don't really need to start over... */ - start_over =3D 1; - break; - } - } - } - if (start_over) - i =3D 0; - else - ++i; - } -} - -/* Register new dependencies based on the given opcode. */ - -static void -mark_resources (struct ia64_opcode *idesc) -{ - int i; - const struct ia64_opcode_dependency *opdeps =3D idesc->dependencies; - int add_only_qp_reads =3D 0; - - /* A conditional branch only uses its resources if it is taken; if it is - taken, we stop following that path. The other branch types effective= ly - *always* write their resources. If it's not taken, register only QP - reads. */ - if (is_conditional_branch (idesc) || is_interruption_or_rfi (idesc)) - { - add_only_qp_reads =3D 1; - } - - if (md.debug_dv) - fprintf (stderr, "Registering '%s' resource usage\n", idesc->name); - - for (i =3D 0; i < opdeps->nregs; i++) - { - const struct ia64_dependency *dep; - struct rsrc specs[MAX_SPECS]; - int note; - int path; - int count; - - dep =3D ia64_find_dependency (opdeps->regs[i]); - note =3D NOTE (opdeps->regs[i]); - - if (add_only_qp_reads - && !(dep->mode =3D=3D IA64_DV_WAR - && (dep->specifier =3D=3D IA64_RS_PR - || dep->specifier =3D=3D IA64_RS_PRr - || dep->specifier =3D=3D IA64_RS_PR63))) - continue; - - count =3D specify_resource (dep, idesc, DV_REG, specs, note, md.path= ); - - while (count-- > 0) - { - mark_resource (idesc, dep, &specs[count], - DEP (opdeps->regs[i]), md.path); - } - - /* The execution path may affect register values, which may in turn - affect which indirect-access resources are accessed. */ - switch (dep->specifier) - { - default: - break; - case IA64_RS_CPUID: - case IA64_RS_DBR: - case IA64_RS_IBR: - case IA64_RS_MSR: - case IA64_RS_PKR: - case IA64_RS_PMC: - case IA64_RS_PMD: - case IA64_RS_RR: - for (path =3D 0; path < md.path; path++) - { - count =3D specify_resource (dep, idesc, DV_REG, specs, note, path); - while (count-- > 0) - mark_resource (idesc, dep, &specs[count], - DEP (opdeps->regs[i]), path); - } - break; - } - } -} - -/* Remove dependencies when they no longer apply. */ - -static void -update_dependencies (struct ia64_opcode *idesc) -{ - int i; - - if (strcmp (idesc->name, "srlz.i") =3D=3D 0) - { - instruction_serialization (); - } - else if (strcmp (idesc->name, "srlz.d") =3D=3D 0) - { - data_serialization (); - } - else if (is_interruption_or_rfi (idesc) - || is_taken_branch (idesc)) - { - /* Although technically the taken branch doesn't clear dependencies - which require a srlz.[id], we don't follow the branch; the next - instruction is assumed to start with a clean slate. */ - regdepslen =3D 0; - md.path =3D 0; - } - else if (is_conditional_branch (idesc) - && CURR_SLOT.qp_regno !=3D 0) - { - int is_call =3D strstr (idesc->name, ".call") !=3D NULL; - - for (i =3D 0; i < qp_implieslen; i++) - { - /* If the conditional branch's predicate is implied by the predicate - in an existing dependency, remove that dependency. */ - if (qp_implies[i].p2 =3D=3D CURR_SLOT.qp_regno) - { - int depind =3D 0; - /* Note that this implied predicate takes a branch so that if - a later insn generates a DV but its predicate implies this - one, we can avoid the false DV warning. */ - qp_implies[i].p2_branched =3D 1; - while (depind < regdepslen) - { - if (regdeps[depind].qp_regno =3D=3D qp_implies[i].p1) - { - print_dependency ("Removing", depind); - regdeps[depind] =3D regdeps[--regdepslen]; - } - else - ++depind; - } - } - } - /* Any marked resources which have this same predicate should be - cleared, provided that the QP hasn't been modified between the - marking instruction and the branch. */ - if (is_call) - { - insn_group_break (0, CURR_SLOT.qp_regno, 1); - } - else - { - i =3D 0; - while (i < regdepslen) - { - if (regdeps[i].qp_regno =3D=3D CURR_SLOT.qp_regno - && regdeps[i].link_to_qp_branch - && (regdeps[i].file !=3D CURR_SLOT.src_file - || regdeps[i].line !=3D CURR_SLOT.src_line)) - { - /* Treat like a taken branch */ - print_dependency ("Removing", i); - regdeps[i] =3D regdeps[--regdepslen]; - } - else - ++i; - } - } - } -} - -/* Examine the current instruction for dependency violations. */ - -static int -check_dv (struct ia64_opcode *idesc) -{ - if (md.debug_dv) - { - fprintf (stderr, "Checking %s for violations (line %d, %d/%d)\n", - idesc->name, CURR_SLOT.src_line, - idesc->dependencies->nchks, - idesc->dependencies->nregs); - } - - /* Look through the list of currently marked resources; if the current - instruction has the dependency in its chks list which uses that resou= rce, - check against the specific resources used. */ - check_dependencies (idesc); - - /* Look up the instruction's regdeps (RAW writes, WAW writes, and WAR re= ads), - then add them to the list of marked resources. */ - mark_resources (idesc); - - /* There are several types of dependency semantics, and each has its own - requirements for being cleared - - Instruction serialization (insns separated by interruption, rfi, or - writer + srlz.i + reader, all in separate groups) clears DVS_INSTR. - - Data serialization (instruction serialization, or writer + srlz.d + - reader, where writer and srlz.d are in separate groups) clears - DVS_DATA. (This also clears DVS_OTHER, but that is not guaranteed to - always be the case). - - Instruction group break (groups separated by stop, taken branch, - interruption or rfi) clears DVS_IMPLIED and DVS_IMPLIEDF. - */ - update_dependencies (idesc); - - /* Sometimes, knowing a register value allows us to avoid giving a false= DV - warning. Keep track of as many as possible that are useful. */ - note_register_values (idesc); - - /* We don't need or want this anymore. */ - md.mem_offset.hint =3D 0; - - return 0; -} - -/* Translate one line of assembly. Pseudo ops and labels do not show - here. */ -void -md_assemble (char *str) -{ - char *saved_input_line_pointer, *temp; - const char *mnemonic; - const struct pseudo_opcode *pdesc; - struct ia64_opcode *idesc; - unsigned char qp_regno; - unsigned int flags; - int ch; - - saved_input_line_pointer =3D input_line_pointer; - input_line_pointer =3D str; - - /* extract the opcode (mnemonic): */ - - ch =3D get_symbol_name (&temp); - mnemonic =3D temp; - pdesc =3D (struct pseudo_opcode *) str_hash_find (md.pseudo_hash, mnemon= ic); - if (pdesc) - { - (void) restore_line_pointer (ch); - (*pdesc->handler) (pdesc->arg); - goto done; - } - - /* Find the instruction descriptor matching the arguments. */ - - idesc =3D ia64_find_opcode (mnemonic); - (void) restore_line_pointer (ch); - if (!idesc) - { - as_bad (_("Unknown opcode `%s'"), mnemonic); - goto done; - } - - idesc =3D parse_operands (idesc); - if (!idesc) - goto done; - - /* Handle the dynamic ops we can handle now: */ - if (idesc->type =3D=3D IA64_TYPE_DYN) - { - if (strcmp (idesc->name, "add") =3D=3D 0) - { - if (CURR_SLOT.opnd[2].X_op =3D=3D O_register - && CURR_SLOT.opnd[2].X_add_number < 4) - mnemonic =3D "addl"; - else - mnemonic =3D "adds"; - ia64_free_opcode (idesc); - idesc =3D ia64_find_opcode (mnemonic); - } - else if (strcmp (idesc->name, "mov") =3D=3D 0) - { - enum ia64_opnd opnd1, opnd2; - int rop; - - opnd1 =3D idesc->operands[0]; - opnd2 =3D idesc->operands[1]; - if (opnd1 =3D=3D IA64_OPND_AR3) - rop =3D 0; - else if (opnd2 =3D=3D IA64_OPND_AR3) - rop =3D 1; - else - abort (); - if (CURR_SLOT.opnd[rop].X_op =3D=3D O_register) - { - if (ar_is_only_in_integer_unit (CURR_SLOT.opnd[rop].X_add_number)) - mnemonic =3D "mov.i"; - else if (ar_is_only_in_memory_unit (CURR_SLOT.opnd[rop].X_add_numbe= r)) - mnemonic =3D "mov.m"; - else - rop =3D -1; - } - else - abort (); - if (rop >=3D 0) - { - ia64_free_opcode (idesc); - idesc =3D ia64_find_opcode (mnemonic); - while (idesc !=3D NULL - && (idesc->operands[0] !=3D opnd1 - || idesc->operands[1] !=3D opnd2)) - idesc =3D get_next_opcode (idesc); - } - } - } - else if (strcmp (idesc->name, "mov.i") =3D=3D 0 - || strcmp (idesc->name, "mov.m") =3D=3D 0) - { - enum ia64_opnd opnd1, opnd2; - int rop; - - opnd1 =3D idesc->operands[0]; - opnd2 =3D idesc->operands[1]; - if (opnd1 =3D=3D IA64_OPND_AR3) - rop =3D 0; - else if (opnd2 =3D=3D IA64_OPND_AR3) - rop =3D 1; - else - abort (); - if (CURR_SLOT.opnd[rop].X_op =3D=3D O_register) - { - char unit =3D 'a'; - if (ar_is_only_in_integer_unit (CURR_SLOT.opnd[rop].X_add_number)) - unit =3D 'i'; - else if (ar_is_only_in_memory_unit (CURR_SLOT.opnd[rop].X_add_number)) - unit =3D 'm'; - if (unit !=3D 'a' && unit !=3D idesc->name [4]) - as_bad (_("AR %d can only be accessed by %c-unit"), - (int) (CURR_SLOT.opnd[rop].X_add_number - REG_AR), - TOUPPER (unit)); - } - } - else if (strcmp (idesc->name, "hint.b") =3D=3D 0) - { - switch (md.hint_b) - { - case hint_b_ok: - break; - case hint_b_warning: - as_warn (_("hint.b may be treated as nop")); - break; - case hint_b_error: - as_bad (_("hint.b shouldn't be used")); - break; - } - } - - qp_regno =3D 0; - if (md.qp.X_op =3D=3D O_register) - { - qp_regno =3D md.qp.X_add_number - REG_P; - md.qp.X_op =3D O_absent; - } - - flags =3D idesc->flags; - - if ((flags & IA64_OPCODE_FIRST) !=3D 0) - { - /* The alignment frag has to end with a stop bit only if the - next instruction after the alignment directive has to be - the first instruction in an instruction group. */ - if (align_frag) - { - while (align_frag->fr_type !=3D rs_align_code) - { - align_frag =3D align_frag->fr_next; - if (!align_frag) - break; - } - /* align_frag can be NULL if there are directives in - between. */ - if (align_frag && align_frag->fr_next =3D=3D frag_now) - align_frag->tc_frag_data =3D 1; - } - - insn_group_break (1, 0, 0); - } - align_frag =3D NULL; - - if ((flags & IA64_OPCODE_NO_PRED) !=3D 0 && qp_regno !=3D 0) - { - as_bad (_("`%s' cannot be predicated"), idesc->name); - goto done; - } - - /* Build the instruction. */ - CURR_SLOT.qp_regno =3D qp_regno; - CURR_SLOT.idesc =3D idesc; - CURR_SLOT.src_file =3D as_where (&CURR_SLOT.src_line); - dwarf2_where (&CURR_SLOT.debug_line); - dwarf2_consume_line_info (); - - /* Add unwind entries, if there are any. */ - if (unwind.current_entry) - { - CURR_SLOT.unwind_record =3D unwind.current_entry; - unwind.current_entry =3D NULL; - } - if (unwind.pending_saves) - { - if (unwind.pending_saves->next) - { - /* Attach the next pending save to the next slot so that its - slot number will get set correctly. */ - add_unwind_entry (unwind.pending_saves->next, NOT_A_CHAR); - unwind.pending_saves =3D &unwind.pending_saves->next->r.record.p; - } - else - unwind.pending_saves =3D NULL; - } - if (unwind.proc_pending.sym && S_IS_DEFINED (unwind.proc_pending.sym)) - unwind.insn =3D 1; - - /* Check for dependency violations. */ - if (md.detect_dv) - check_dv (idesc); - - md.curr_slot =3D (md.curr_slot + 1) % NUM_SLOTS; - if (++md.num_slots_in_use >=3D NUM_SLOTS) - emit_one_bundle (); - - if ((flags & IA64_OPCODE_LAST) !=3D 0) - insn_group_break (1, 0, 0); - - md.last_text_seg =3D now_seg; - md.last_text_subseg =3D now_subseg; - - done: - input_line_pointer =3D saved_input_line_pointer; -} - -/* Called when symbol NAME cannot be found in the symbol table. - Should be used for dynamic valued symbols only. */ - -symbolS * -md_undefined_symbol (char *name ATTRIBUTE_UNUSED) -{ - return 0; -} - -/* Called for any expression that can not be recognized. When the - function is called, `input_line_pointer' will point to the start of - the expression. */ - -void -md_operand (expressionS *e) -{ - switch (*input_line_pointer) - { - case '[': - ++input_line_pointer; - expression_and_evaluate (e); - if (*input_line_pointer !=3D ']') - { - as_bad (_("Closing bracket missing")); - goto err; - } - else - { - if (e->X_op !=3D O_register - || e->X_add_number < REG_GR - || e->X_add_number > REG_GR + 127) - { - as_bad (_("Index must be a general register")); - e->X_add_number =3D REG_GR; - } - - ++input_line_pointer; - e->X_op =3D O_index; - } - break; - - default: - break; - } - return; - - err: - ignore_rest_of_line (); -} - -/* Return 1 if it's OK to adjust a reloc by replacing the symbol with - a section symbol plus some offset. For relocs involving @fptr(), - directives we don't want such adjustments since we need to have the - original symbol's name in the reloc. */ -int -ia64_fix_adjustable (fixS *fix) -{ - /* Prevent all adjustments to global symbols */ - if (S_IS_EXTERNAL (fix->fx_addsy) || S_IS_WEAK (fix->fx_addsy)) - return 0; - - switch (fix->fx_r_type) - { - case BFD_RELOC_IA64_FPTR64I: - case BFD_RELOC_IA64_FPTR32MSB: - case BFD_RELOC_IA64_FPTR32LSB: - case BFD_RELOC_IA64_FPTR64MSB: - case BFD_RELOC_IA64_FPTR64LSB: - case BFD_RELOC_IA64_LTOFF_FPTR22: - case BFD_RELOC_IA64_LTOFF_FPTR64I: - return 0; - default: - break; - } - - return 1; -} - -int -ia64_force_relocation (fixS *fix) -{ - switch (fix->fx_r_type) - { - case BFD_RELOC_IA64_FPTR64I: - case BFD_RELOC_IA64_FPTR32MSB: - case BFD_RELOC_IA64_FPTR32LSB: - case BFD_RELOC_IA64_FPTR64MSB: - case BFD_RELOC_IA64_FPTR64LSB: - - case BFD_RELOC_IA64_LTOFF22: - case BFD_RELOC_IA64_LTOFF64I: - case BFD_RELOC_IA64_LTOFF_FPTR22: - case BFD_RELOC_IA64_LTOFF_FPTR64I: - case BFD_RELOC_IA64_PLTOFF22: - case BFD_RELOC_IA64_PLTOFF64I: - case BFD_RELOC_IA64_PLTOFF64MSB: - case BFD_RELOC_IA64_PLTOFF64LSB: - - case BFD_RELOC_IA64_LTOFF22X: - case BFD_RELOC_IA64_LDXMOV: - return 1; - - default: - break; - } - - return generic_force_reloc (fix); -} - -/* Decide from what point a pc-relative relocation is relative to, - relative to the pc-relative fixup. Er, relatively speaking. */ -long -ia64_pcrel_from_section (fixS *fix, segT sec) -{ - unsigned long off =3D fix->fx_frag->fr_address + fix->fx_where; - - if (bfd_section_flags (sec) & SEC_CODE) - off &=3D ~0xfUL; - - return off; -} - - -/* Used to emit section-relative relocs for the dwarf2 debug data. */ -void -ia64_dwarf2_emit_offset (symbolS *symbol, unsigned int size) -{ - expressionS exp; - - exp.X_op =3D O_pseudo_fixup; - exp.X_op_symbol =3D pseudo_func[FUNC_SEC_RELATIVE].u.sym; - exp.X_add_number =3D 0; - exp.X_add_symbol =3D symbol; - emit_expr (&exp, size); -} - -/* This is called whenever some data item (not an instruction) needs a - fixup. We pick the right reloc code depending on the byteorder - currently in effect. */ -void -ia64_cons_fix_new (fragS *f, int where, int nbytes, expressionS *exp, - bfd_reloc_code_real_type code) -{ - fixS *fix; - - switch (nbytes) - { - /* There are no reloc for 8 and 16 bit quantities, but we allow - them here since they will work fine as long as the expression - is fully defined at the end of the pass over the source file. */ - case 1: code =3D BFD_RELOC_8; break; - case 2: code =3D BFD_RELOC_16; break; - case 4: - if (target_big_endian) - code =3D BFD_RELOC_IA64_DIR32MSB; - else - code =3D BFD_RELOC_IA64_DIR32LSB; - break; - - case 8: - /* In 32-bit mode, data8 could mean function descriptors too. */ - if (exp->X_op =3D=3D O_pseudo_fixup - && exp->X_op_symbol - && S_GET_VALUE (exp->X_op_symbol) =3D=3D FUNC_IPLT_RELOC - && !(md.flags & EF_IA_64_ABI64)) - { - if (target_big_endian) - code =3D BFD_RELOC_IA64_IPLTMSB; - else - code =3D BFD_RELOC_IA64_IPLTLSB; - exp->X_op =3D O_symbol; - break; - } - else - { - if (target_big_endian) - code =3D BFD_RELOC_IA64_DIR64MSB; - else - code =3D BFD_RELOC_IA64_DIR64LSB; - break; - } - - case 16: - if (exp->X_op =3D=3D O_pseudo_fixup - && exp->X_op_symbol - && S_GET_VALUE (exp->X_op_symbol) =3D=3D FUNC_IPLT_RELOC) - { - if (target_big_endian) - code =3D BFD_RELOC_IA64_IPLTMSB; - else - code =3D BFD_RELOC_IA64_IPLTLSB; - exp->X_op =3D O_symbol; - break; - } - /* FALLTHRU */ - - default: - as_bad (_("Unsupported fixup size %d"), nbytes); - ignore_rest_of_line (); - return; - } - - if (exp->X_op =3D=3D O_pseudo_fixup) - { - exp->X_op =3D O_symbol; - code =3D ia64_gen_real_reloc_type (exp->X_op_symbol, code); - /* ??? If code unchanged, unsupported. */ - } - - fix =3D fix_new_exp (f, where, nbytes, exp, 0, code); - /* We need to store the byte order in effect in case we're going - to fix an 8 or 16 bit relocation (for which there no real - relocs available). See md_apply_fix(). */ - fix->tc_fix_data.bigendian =3D target_big_endian; -} - -/* Return the actual relocation we wish to associate with the pseudo - reloc described by SYM and R_TYPE. SYM should be one of the - symbols in the pseudo_func array, or NULL. */ - -static bfd_reloc_code_real_type -ia64_gen_real_reloc_type (struct symbol *sym, bfd_reloc_code_real_type r_t= ype) -{ - bfd_reloc_code_real_type newr =3D 0; - const char *type =3D NULL, *suffix =3D ""; - - if (sym =3D=3D NULL) - { - return r_type; - } - - switch (S_GET_VALUE (sym)) - { - case FUNC_FPTR_RELATIVE: - switch (r_type) - { - case BFD_RELOC_IA64_IMM64: newr =3D BFD_RELOC_IA64_FPTR64I; break; - case BFD_RELOC_IA64_DIR32MSB: newr =3D BFD_RELOC_IA64_FPTR32MSB; break; - case BFD_RELOC_IA64_DIR32LSB: newr =3D BFD_RELOC_IA64_FPTR32LSB; break; - case BFD_RELOC_IA64_DIR64MSB: newr =3D BFD_RELOC_IA64_FPTR64MSB; break; - case BFD_RELOC_IA64_DIR64LSB: newr =3D BFD_RELOC_IA64_FPTR64LSB; break; - default: type =3D "FPTR"; break; - } - break; - - case FUNC_GP_RELATIVE: - switch (r_type) - { - case BFD_RELOC_IA64_IMM22: newr =3D BFD_RELOC_IA64_GPREL22; break; - case BFD_RELOC_IA64_IMM64: newr =3D BFD_RELOC_IA64_GPREL64I; break; - case BFD_RELOC_IA64_DIR32MSB: newr =3D BFD_RELOC_IA64_GPREL32MSB; break; - case BFD_RELOC_IA64_DIR32LSB: newr =3D BFD_RELOC_IA64_GPREL32LSB; break; - case BFD_RELOC_IA64_DIR64MSB: newr =3D BFD_RELOC_IA64_GPREL64MSB; break; - case BFD_RELOC_IA64_DIR64LSB: newr =3D BFD_RELOC_IA64_GPREL64LSB; break; - default: type =3D "GPREL"; break; - } - break; - - case FUNC_LT_RELATIVE: - switch (r_type) - { - case BFD_RELOC_IA64_IMM22: newr =3D BFD_RELOC_IA64_LTOFF22; break; - case BFD_RELOC_IA64_IMM64: newr =3D BFD_RELOC_IA64_LTOFF64I; break; - default: type =3D "LTOFF"; break; - } - break; - - case FUNC_LT_RELATIVE_X: - switch (r_type) - { - case BFD_RELOC_IA64_IMM22: newr =3D BFD_RELOC_IA64_LTOFF22X; break; - default: type =3D "LTOFF"; suffix =3D "X"; break; - } - break; - - case FUNC_PC_RELATIVE: - switch (r_type) - { - case BFD_RELOC_IA64_IMM22: newr =3D BFD_RELOC_IA64_PCREL22; break; - case BFD_RELOC_IA64_IMM64: newr =3D BFD_RELOC_IA64_PCREL64I; break; - case BFD_RELOC_IA64_DIR32MSB: newr =3D BFD_RELOC_IA64_PCREL32MSB; break; - case BFD_RELOC_IA64_DIR32LSB: newr =3D BFD_RELOC_IA64_PCREL32LSB; break; - case BFD_RELOC_IA64_DIR64MSB: newr =3D BFD_RELOC_IA64_PCREL64MSB; break; - case BFD_RELOC_IA64_DIR64LSB: newr =3D BFD_RELOC_IA64_PCREL64LSB; break; - default: type =3D "PCREL"; break; - } - break; - - case FUNC_PLT_RELATIVE: - switch (r_type) - { - case BFD_RELOC_IA64_IMM22: newr =3D BFD_RELOC_IA64_PLTOFF22; break; - case BFD_RELOC_IA64_IMM64: newr =3D BFD_RELOC_IA64_PLTOFF64I; break; - case BFD_RELOC_IA64_DIR64MSB: newr =3D BFD_RELOC_IA64_PLTOFF64MSB;break; - case BFD_RELOC_IA64_DIR64LSB: newr =3D BFD_RELOC_IA64_PLTOFF64LSB;break; - default: type =3D "PLTOFF"; break; - } - break; - - case FUNC_SEC_RELATIVE: - switch (r_type) - { - case BFD_RELOC_IA64_DIR32MSB: newr =3D BFD_RELOC_IA64_SECREL32MSB;break; - case BFD_RELOC_IA64_DIR32LSB: newr =3D BFD_RELOC_IA64_SECREL32LSB;break; - case BFD_RELOC_IA64_DIR64MSB: newr =3D BFD_RELOC_IA64_SECREL64MSB;break; - case BFD_RELOC_IA64_DIR64LSB: newr =3D BFD_RELOC_IA64_SECREL64LSB;break; - default: type =3D "SECREL"; break; - } - break; - - case FUNC_SEG_RELATIVE: - switch (r_type) - { - case BFD_RELOC_IA64_DIR32MSB: newr =3D BFD_RELOC_IA64_SEGREL32MSB;break; - case BFD_RELOC_IA64_DIR32LSB: newr =3D BFD_RELOC_IA64_SEGREL32LSB;break; - case BFD_RELOC_IA64_DIR64MSB: newr =3D BFD_RELOC_IA64_SEGREL64MSB;break; - case BFD_RELOC_IA64_DIR64LSB: newr =3D BFD_RELOC_IA64_SEGREL64LSB;break; - default: type =3D "SEGREL"; break; - } - break; - - case FUNC_LTV_RELATIVE: - switch (r_type) - { - case BFD_RELOC_IA64_DIR32MSB: newr =3D BFD_RELOC_IA64_LTV32MSB; break; - case BFD_RELOC_IA64_DIR32LSB: newr =3D BFD_RELOC_IA64_LTV32LSB; break; - case BFD_RELOC_IA64_DIR64MSB: newr =3D BFD_RELOC_IA64_LTV64MSB; break; - case BFD_RELOC_IA64_DIR64LSB: newr =3D BFD_RELOC_IA64_LTV64LSB; break; - default: type =3D "LTV"; break; - } - break; - - case FUNC_LT_FPTR_RELATIVE: - switch (r_type) - { - case BFD_RELOC_IA64_IMM22: - newr =3D BFD_RELOC_IA64_LTOFF_FPTR22; break; - case BFD_RELOC_IA64_IMM64: - newr =3D BFD_RELOC_IA64_LTOFF_FPTR64I; break; - case BFD_RELOC_IA64_DIR32MSB: - newr =3D BFD_RELOC_IA64_LTOFF_FPTR32MSB; break; - case BFD_RELOC_IA64_DIR32LSB: - newr =3D BFD_RELOC_IA64_LTOFF_FPTR32LSB; break; - case BFD_RELOC_IA64_DIR64MSB: - newr =3D BFD_RELOC_IA64_LTOFF_FPTR64MSB; break; - case BFD_RELOC_IA64_DIR64LSB: - newr =3D BFD_RELOC_IA64_LTOFF_FPTR64LSB; break; - default: - type =3D "LTOFF_FPTR"; break; - } - break; - - case FUNC_TP_RELATIVE: - switch (r_type) - { - case BFD_RELOC_IA64_IMM14: newr =3D BFD_RELOC_IA64_TPREL14; break; - case BFD_RELOC_IA64_IMM22: newr =3D BFD_RELOC_IA64_TPREL22; break; - case BFD_RELOC_IA64_IMM64: newr =3D BFD_RELOC_IA64_TPREL64I; break; - case BFD_RELOC_IA64_DIR64MSB: newr =3D BFD_RELOC_IA64_TPREL64MSB; break; - case BFD_RELOC_IA64_DIR64LSB: newr =3D BFD_RELOC_IA64_TPREL64LSB; break; - default: type =3D "TPREL"; break; - } - break; - - case FUNC_LT_TP_RELATIVE: - switch (r_type) - { - case BFD_RELOC_IA64_IMM22: - newr =3D BFD_RELOC_IA64_LTOFF_TPREL22; break; - default: - type =3D "LTOFF_TPREL"; break; - } - break; - - case FUNC_DTP_MODULE: - switch (r_type) - { - case BFD_RELOC_IA64_DIR64MSB: - newr =3D BFD_RELOC_IA64_DTPMOD64MSB; break; - case BFD_RELOC_IA64_DIR64LSB: - newr =3D BFD_RELOC_IA64_DTPMOD64LSB; break; - default: - type =3D "DTPMOD"; break; - } - break; - - case FUNC_LT_DTP_MODULE: - switch (r_type) - { - case BFD_RELOC_IA64_IMM22: - newr =3D BFD_RELOC_IA64_LTOFF_DTPMOD22; break; - default: - type =3D "LTOFF_DTPMOD"; break; - } - break; - - case FUNC_DTP_RELATIVE: - switch (r_type) - { - case BFD_RELOC_IA64_DIR32MSB: - newr =3D BFD_RELOC_IA64_DTPREL32MSB; break; - case BFD_RELOC_IA64_DIR32LSB: - newr =3D BFD_RELOC_IA64_DTPREL32LSB; break; - case BFD_RELOC_IA64_DIR64MSB: - newr =3D BFD_RELOC_IA64_DTPREL64MSB; break; - case BFD_RELOC_IA64_DIR64LSB: - newr =3D BFD_RELOC_IA64_DTPREL64LSB; break; - case BFD_RELOC_IA64_IMM14: - newr =3D BFD_RELOC_IA64_DTPREL14; break; - case BFD_RELOC_IA64_IMM22: - newr =3D BFD_RELOC_IA64_DTPREL22; break; - case BFD_RELOC_IA64_IMM64: - newr =3D BFD_RELOC_IA64_DTPREL64I; break; - default: - type =3D "DTPREL"; break; - } - break; - - case FUNC_LT_DTP_RELATIVE: - switch (r_type) - { - case BFD_RELOC_IA64_IMM22: - newr =3D BFD_RELOC_IA64_LTOFF_DTPREL22; break; - default: - type =3D "LTOFF_DTPREL"; break; - } - break; - - case FUNC_IPLT_RELOC: - switch (r_type) - { - case BFD_RELOC_IA64_IPLTMSB: return r_type; - case BFD_RELOC_IA64_IPLTLSB: return r_type; - default: type =3D "IPLT"; break; - } - break; - -#ifdef TE_VMS - case FUNC_SLOTCOUNT_RELOC: - return DUMMY_RELOC_IA64_SLOTCOUNT; -#endif - - default: - abort (); - } - - if (newr) - return newr; - else - { - int width; - - if (!type) - abort (); - switch (r_type) - { - case BFD_RELOC_IA64_DIR32MSB: width =3D 32; suffix =3D "MSB"; break; - case BFD_RELOC_IA64_DIR32LSB: width =3D 32; suffix =3D "LSB"; break; - case BFD_RELOC_IA64_DIR64MSB: width =3D 64; suffix =3D "MSB"; break; - case BFD_RELOC_IA64_DIR64LSB: width =3D 64; suffix =3D "LSB"; break; - case BFD_RELOC_UNUSED: width =3D 13; break; - case BFD_RELOC_IA64_IMM14: width =3D 14; break; - case BFD_RELOC_IA64_IMM22: width =3D 22; break; - case BFD_RELOC_IA64_IMM64: width =3D 64; suffix =3D "I"; break; - default: abort (); - } - - /* This should be an error, but since previously there wasn't any - diagnostic here, don't make it fail because of this for now. */ - as_warn (_("Cannot express %s%d%s relocation"), type, width, suffix); - return r_type; - } -} - -/* Here is where generate the appropriate reloc for pseudo relocation - functions. */ -void -ia64_validate_fix (fixS *fix) -{ - switch (fix->fx_r_type) - { - case BFD_RELOC_IA64_FPTR64I: - case BFD_RELOC_IA64_FPTR32MSB: - case BFD_RELOC_IA64_FPTR64LSB: - case BFD_RELOC_IA64_LTOFF_FPTR22: - case BFD_RELOC_IA64_LTOFF_FPTR64I: - if (fix->fx_offset !=3D 0) - as_bad_where (fix->fx_file, fix->fx_line, - _("No addend allowed in @fptr() relocation")); - break; - default: - break; - } -} - -static void -fix_insn (fixS *fix, const struct ia64_operand *odesc, valueT value) -{ - bfd_vma insn[3], t0, t1, control_bits; - const char *err; - char *fixpos; - long slot; - - slot =3D fix->fx_where & 0x3; - fixpos =3D fix->fx_frag->fr_literal + (fix->fx_where - slot); - - /* Bundles are always in little-endian byte order */ - t0 =3D bfd_getl64 (fixpos); - t1 =3D bfd_getl64 (fixpos + 8); - control_bits =3D t0 & 0x1f; - insn[0] =3D (t0 >> 5) & 0x1ffffffffffLL; - insn[1] =3D ((t0 >> 46) & 0x3ffff) | ((t1 & 0x7fffff) << 18); - insn[2] =3D (t1 >> 23) & 0x1ffffffffffLL; - - err =3D NULL; - if (odesc - elf64_ia64_operands =3D=3D IA64_OPND_IMMU64) - { - insn[1] =3D (value >> 22) & 0x1ffffffffffLL; - insn[2] |=3D (((value & 0x7f) << 13) - | (((value >> 7) & 0x1ff) << 27) - | (((value >> 16) & 0x1f) << 22) - | (((value >> 21) & 0x1) << 21) - | (((value >> 63) & 0x1) << 36)); - } - else if (odesc - elf64_ia64_operands =3D=3D IA64_OPND_IMMU62) - { - if (value & ~0x3fffffffffffffffULL) - err =3D _("integer operand out of range"); - insn[1] =3D (value >> 21) & 0x1ffffffffffLL; - insn[2] |=3D (((value & 0xfffff) << 6) | (((value >> 20) & 0x1) << 3= 6)); - } - else if (odesc - elf64_ia64_operands =3D=3D IA64_OPND_TGT64) - { - value >>=3D 4; - insn[1] =3D ((value >> 20) & 0x7fffffffffLL) << 2; - insn[2] |=3D ((((value >> 59) & 0x1) << 36) - | (((value >> 0) & 0xfffff) << 13)); - } - else - err =3D (*odesc->insert) (odesc, value, insn + slot); - - if (err) - as_bad_where (fix->fx_file, fix->fx_line, "%s", err); - - t0 =3D control_bits | (insn[0] << 5) | (insn[1] << 46); - t1 =3D ((insn[1] >> 18) & 0x7fffff) | (insn[2] << 23); - number_to_chars_littleendian (fixpos + 0, t0, 8); - number_to_chars_littleendian (fixpos + 8, t1, 8); -} - -/* Attempt to simplify or even eliminate a fixup. The return value is - ignored; perhaps it was once meaningful, but now it is historical. - To indicate that a fixup has been eliminated, set FIXP->FX_DONE. - - If fixp->fx_addsy is non-NULL, we'll have to generate a reloc entry - (if possible). */ - -void -md_apply_fix (fixS *fix, valueT *valP, segT seg ATTRIBUTE_UNUSED) -{ - char *fixpos; - valueT value =3D *valP; - - fixpos =3D fix->fx_frag->fr_literal + fix->fx_where; - - if (fix->fx_pcrel) - { - switch (fix->fx_r_type) - { - case BFD_RELOC_IA64_PCREL21B: break; - case BFD_RELOC_IA64_PCREL21BI: break; - case BFD_RELOC_IA64_PCREL21F: break; - case BFD_RELOC_IA64_PCREL21M: break; - case BFD_RELOC_IA64_PCREL60B: break; - case BFD_RELOC_IA64_PCREL22: break; - case BFD_RELOC_IA64_PCREL64I: break; - case BFD_RELOC_IA64_PCREL32MSB: break; - case BFD_RELOC_IA64_PCREL32LSB: break; - case BFD_RELOC_IA64_PCREL64MSB: break; - case BFD_RELOC_IA64_PCREL64LSB: break; - default: - fix->fx_r_type =3D ia64_gen_real_reloc_type (pseudo_func[FUNC_PC_RELATIVE= ].u.sym, - fix->fx_r_type); - break; - } - } - if (fix->fx_addsy) - { - switch ((unsigned) fix->fx_r_type) - { - case BFD_RELOC_UNUSED: - /* This must be a TAG13 or TAG13b operand. There are no external - relocs defined for them, so we must give an error. */ - as_bad_where (fix->fx_file, fix->fx_line, - _("%s must have a constant value"), - elf64_ia64_operands[fix->tc_fix_data.opnd].desc); - fix->fx_done =3D 1; - return; - - case BFD_RELOC_IA64_TPREL14: - case BFD_RELOC_IA64_TPREL22: - case BFD_RELOC_IA64_TPREL64I: - case BFD_RELOC_IA64_LTOFF_TPREL22: - case BFD_RELOC_IA64_LTOFF_DTPMOD22: - case BFD_RELOC_IA64_DTPREL14: - case BFD_RELOC_IA64_DTPREL22: - case BFD_RELOC_IA64_DTPREL64I: - case BFD_RELOC_IA64_LTOFF_DTPREL22: - S_SET_THREAD_LOCAL (fix->fx_addsy); - break; - -#ifdef TE_VMS - case DUMMY_RELOC_IA64_SLOTCOUNT: - as_bad_where (fix->fx_file, fix->fx_line, - _("cannot resolve @slotcount parameter")); - fix->fx_done =3D 1; - return; -#endif - - default: - break; - } - } - else if (fix->tc_fix_data.opnd =3D=3D IA64_OPND_NIL) - { -#ifdef TE_VMS - if (fix->fx_r_type =3D=3D DUMMY_RELOC_IA64_SLOTCOUNT) - { - /* For @slotcount, convert an addresses difference to a slots - difference. */ - valueT v; - - v =3D (value >> 4) * 3; - switch (value & 0x0f) - { - case 0: - case 1: - case 2: - v +=3D value & 0x0f; - break; - case 0x0f: - v +=3D 2; - break; - case 0x0e: - v +=3D 1; - break; - default: - as_bad (_("invalid @slotcount value")); - } - value =3D v; - } -#endif - - if (fix->tc_fix_data.bigendian) - number_to_chars_bigendian (fixpos, value, fix->fx_size); - else - number_to_chars_littleendian (fixpos, value, fix->fx_size); - fix->fx_done =3D 1; - } - else - { - fix_insn (fix, elf64_ia64_operands + fix->tc_fix_data.opnd, value); - fix->fx_done =3D 1; - } -} - -/* Generate the BFD reloc to be stuck in the object file from the - fixup used internally in the assembler. */ - -arelent * -tc_gen_reloc (asection *sec ATTRIBUTE_UNUSED, fixS *fixp) -{ - arelent *reloc; - - reloc =3D XNEW (arelent); - reloc->sym_ptr_ptr =3D XNEW (asymbol *); - *reloc->sym_ptr_ptr =3D symbol_get_bfdsym (fixp->fx_addsy); - reloc->address =3D fixp->fx_frag->fr_address + fixp->fx_where; - reloc->addend =3D fixp->fx_offset; - reloc->howto =3D bfd_reloc_type_lookup (stdoutput, fixp->fx_r_type); - - if (!reloc->howto) - { - as_bad_where (fixp->fx_file, fixp->fx_line, - _("Cannot represent %s relocation in object file"), - bfd_get_reloc_code_name (fixp->fx_r_type)); - free (reloc); - return NULL; - } - return reloc; -} - -/* Turn a string in input_line_pointer into a floating point constant - of type TYPE, and store the appropriate bytes in *LIT. The number - of LITTLENUMS emitted is stored in *SIZE. An error message is - returned, or NULL on OK. */ - -const char * -md_atof (int type, char *lit, int *size) -{ - LITTLENUM_TYPE words[MAX_LITTLENUMS]; - char *t; - int prec; - - switch (type) - { - /* IEEE floats */ - case 'f': - case 'F': - case 's': - case 'S': - prec =3D 2; - break; - - case 'd': - case 'D': - case 'r': - case 'R': - prec =3D 4; - break; - - case 'x': - case 'X': - case 'p': - case 'P': - prec =3D 5; - break; - - default: - *size =3D 0; - return _("Unrecognized or unsupported floating point constant"); - } - t =3D atof_ieee (input_line_pointer, type, words); - if (t) - input_line_pointer =3D t; - - (*ia64_float_to_chars) (lit, words, prec); - - if (type =3D=3D 'X') - { - /* It is 10 byte floating point with 6 byte padding. */ - memset (&lit [10], 0, 6); - *size =3D 8 * sizeof (LITTLENUM_TYPE); - } - else - *size =3D prec * sizeof (LITTLENUM_TYPE); - - return NULL; -} - -/* Handle ia64 specific semantics of the align directive. */ - -void -ia64_md_do_align (int n ATTRIBUTE_UNUSED, - const char *fill ATTRIBUTE_UNUSED, - int len ATTRIBUTE_UNUSED, - int max ATTRIBUTE_UNUSED) -{ - if (subseg_text_p (now_seg)) - ia64_flush_insns (); -} - -/* This is called from HANDLE_ALIGN in write.c. Fill in the contents - of an rs_align_code fragment. */ - -void -ia64_handle_align (fragS *fragp) -{ - int bytes; - char *p; - const unsigned char *nop_type; - - if (fragp->fr_type !=3D rs_align_code) - return; - - /* Check if this frag has to end with a stop bit. */ - nop_type =3D fragp->tc_frag_data ? le_nop_stop : le_nop; - - bytes =3D fragp->fr_next->fr_address - fragp->fr_address - fragp->fr_fix; - p =3D fragp->fr_literal + fragp->fr_fix; - - /* If no paddings are needed, we check if we need a stop bit. */ - if (!bytes && fragp->tc_frag_data) - { - if (fragp->fr_fix < 16) -#if 1 - /* FIXME: It won't work with - .align 16 - alloc r32=3Dar.pfs,1,2,4,0 - */ - ; -#else - as_bad_where (fragp->fr_file, fragp->fr_line, - _("Can't add stop bit to mark end of instruction group")); -#endif - else - /* Bundles are always in little-endian byte order. Make sure - the previous bundle has the stop bit. */ - *(p - 16) |=3D 1; - } - - /* Make sure we are on a 16-byte boundary, in case someone has been - putting data into a text section. */ - if (bytes & 15) - { - int fix =3D bytes & 15; - memset (p, 0, fix); - p +=3D fix; - bytes -=3D fix; - fragp->fr_fix +=3D fix; - } - - /* Instruction bundles are always little-endian. */ - memcpy (p, nop_type, 16); - fragp->fr_var =3D 16; -} - -static void -ia64_float_to_chars_bigendian (char *lit, LITTLENUM_TYPE *words, - int prec) -{ - while (prec--) - { - number_to_chars_bigendian (lit, (long) (*words++), - sizeof (LITTLENUM_TYPE)); - lit +=3D sizeof (LITTLENUM_TYPE); - } -} - -static void -ia64_float_to_chars_littleendian (char *lit, LITTLENUM_TYPE *words, - int prec) -{ - while (prec--) - { - number_to_chars_littleendian (lit, (long) (words[prec]), - sizeof (LITTLENUM_TYPE)); - lit +=3D sizeof (LITTLENUM_TYPE); - } -} - -void -ia64_elf_section_change_hook (void) -{ - if (elf_section_type (now_seg) =3D=3D SHT_IA_64_UNWIND - && elf_linked_to_section (now_seg) =3D=3D NULL) - elf_linked_to_section (now_seg) =3D text_section; - dot_byteorder (-1); -} - -/* Check if a label should be made global. */ -void -ia64_check_label (symbolS *label) -{ - if (*input_line_pointer =3D=3D ':') - { - S_SET_EXTERNAL (label); - input_line_pointer++; - } -} - -/* Used to remember where .alias and .secalias directives are seen. We - will rename symbol and section names when we are about to output - the relocatable file. */ -struct alias -{ - const char *file; /* The file where the directive is seen. */ - unsigned int line; /* The line number the directive is at. */ - const char *name; /* The original name of the symbol. */ -}; - -/* Called for .alias and .secalias directives. If SECTION is 1, it is - .secalias. Otherwise, it is .alias. */ -static void -dot_alias (int section) -{ - char *name, *alias; - char delim; - char *end_name; - int len; - struct alias *h; - const char *a; - htab_t ahash, nhash; - const char *kind; - - delim =3D get_symbol_name (&name); - end_name =3D input_line_pointer; - *end_name =3D delim; - - if (name =3D=3D end_name) - { - as_bad (_("expected symbol name")); - ignore_rest_of_line (); - return; - } - - SKIP_WHITESPACE_AFTER_NAME (); - - if (*input_line_pointer !=3D ',') - { - *end_name =3D 0; - as_bad (_("expected comma after \"%s\""), name); - *end_name =3D delim; - ignore_rest_of_line (); - return; - } - - input_line_pointer++; - *end_name =3D 0; - ia64_canonicalize_symbol_name (name); - - /* We call demand_copy_C_string to check if alias string is valid. - There should be a closing `"' and no `\0' in the string. */ - alias =3D demand_copy_C_string (&len); - if (alias =3D=3D NULL) - { - ignore_rest_of_line (); - return; - } - - /* Make a copy of name string. */ - name =3D notes_strdup (name); - - if (section) - { - kind =3D "section"; - ahash =3D secalias_hash; - nhash =3D secalias_name_hash; - } - else - { - kind =3D "symbol"; - ahash =3D alias_hash; - nhash =3D alias_name_hash; - } - - /* Check if alias has been used before. */ - - h =3D (struct alias *) str_hash_find (ahash, alias); - if (h) - { - if (strcmp (h->name, name)) - as_bad (_("`%s' is already the alias of %s `%s'"), - alias, kind, h->name); - notes_free (alias); - goto out; - } - - /* Check if name already has an alias. */ - a =3D (const char *) str_hash_find (nhash, name); - if (a) - { - if (strcmp (a, alias)) - as_bad (_("%s `%s' already has an alias `%s'"), kind, name, a); - notes_free (alias); - goto out; - } - - h =3D notes_alloc (sizeof (*h)); - h->file =3D as_where (&h->line); - h->name =3D name; - - str_hash_insert (ahash, alias, h, 0); - str_hash_insert (nhash, name, alias, 0); - -out: - demand_empty_rest_of_line (); -} - -/* It renames the original symbol name to its alias. */ -static int -do_alias (void **slot, void *arg ATTRIBUTE_UNUSED) -{ - string_tuple_t *tuple =3D *((string_tuple_t **) slot); - struct alias *h =3D (struct alias *) tuple->value; - symbolS *sym =3D symbol_find (h->name); - - if (sym =3D=3D NULL) - { -#ifdef TE_VMS - /* Uses .alias extensively to alias CRTL functions to same with - decc$ prefix. Sometimes function gets optimized away and a - warning results, which should be suppressed. */ - if (!startswith (tuple->key, "decc$")) -#endif - as_warn_where (h->file, h->line, - _("symbol `%s' aliased to `%s' is not used"), - h->name, tuple->key); - } - else - S_SET_NAME (sym, (char *) tuple->key); - - return 1; -} - -/* Called from write_object_file. */ -void -ia64_adjust_symtab (void) -{ - htab_traverse_noresize (alias_hash, do_alias, NULL); -} - -/* It renames the original section name to its alias. */ -static int -do_secalias (void **slot, void *arg ATTRIBUTE_UNUSED) -{ - string_tuple_t *tuple =3D *((string_tuple_t **) slot); - struct alias *h =3D (struct alias *) tuple->value; - segT sec =3D bfd_get_section_by_name (stdoutput, h->name); - - if (sec =3D=3D NULL) - as_warn_where (h->file, h->line, - _("section `%s' aliased to `%s' is not used"), - h->name, tuple->key); - else - sec->name =3D tuple->key; - - return 1; -} - -/* Called from write_object_file. */ -void -ia64_frob_file (void) -{ - htab_traverse_noresize (secalias_hash, do_secalias, NULL); -} - -#ifdef TE_VMS -#define NT_VMS_MHD 1 -#define NT_VMS_LNM 2 - -/* Integrity VMS 8.x identifies it's ELF modules with a standard ELF - .note section. */ - -/* Manufacture a VMS-like time string. */ -static void -get_vms_time (char *Now) -{ - char *pnt; - time_t timeb; - - time (&timeb); - pnt =3D ctime (&timeb); - pnt[3] =3D 0; - pnt[7] =3D 0; - pnt[10] =3D 0; - pnt[16] =3D 0; - pnt[24] =3D 0; - sprintf (Now, "%2s-%3s-%s %s", pnt + 8, pnt + 4, pnt + 20, pnt + 11); -} - -void -ia64_vms_note (void) -{ - char *p; - asection *seg =3D now_seg; - subsegT subseg =3D now_subseg; - asection *secp =3D NULL; - char *bname; - char buf [256]; - symbolS *sym; - - /* Create the .note section. */ - - secp =3D subseg_new (".note", 0); - bfd_set_section_flags (secp, SEC_HAS_CONTENTS | SEC_READONLY); - - /* Module header note (MHD). */ - bname =3D xstrdup (lbasename (out_file_name)); - if ((p =3D strrchr (bname, '.'))) - *p =3D '\0'; - - /* VMS note header is 24 bytes long. */ - p =3D frag_more (8 + 8 + 8); - number_to_chars_littleendian (p + 0, 8, 8); - number_to_chars_littleendian (p + 8, 40 + strlen (bname), 8); - number_to_chars_littleendian (p + 16, NT_VMS_MHD, 8); - - p =3D frag_more (8); - strcpy (p, "IPF/VMS"); - - p =3D frag_more (17 + 17 + strlen (bname) + 1 + 5); - get_vms_time (p); - strcpy (p + 17, "24-FEB-2005 15:00"); - p +=3D 17 + 17; - strcpy (p, bname); - p +=3D strlen (bname) + 1; - free (bname); - strcpy (p, "V1.0"); - - frag_align (3, 0, 0); - - /* Language processor name note. */ - sprintf (buf, "GNU assembler version %s (%s) using BFD version %s", - VERSION, TARGET_ALIAS, BFD_VERSION_STRING); - - p =3D frag_more (8 + 8 + 8); - number_to_chars_littleendian (p + 0, 8, 8); - number_to_chars_littleendian (p + 8, strlen (buf) + 1, 8); - number_to_chars_littleendian (p + 16, NT_VMS_LNM, 8); - - p =3D frag_more (8); - strcpy (p, "IPF/VMS"); - - p =3D frag_more (strlen (buf) + 1); - strcpy (p, buf); - - frag_align (3, 0, 0); - - secp =3D subseg_new (".vms_display_name_info", 0); - bfd_set_section_flags (secp, SEC_HAS_CONTENTS | SEC_READONLY); - - /* This symbol should be passed on the command line and be variable - according to language. */ - sym =3D symbol_new ("__gnat_vms_display_name@gnat_demangler_rtl", - absolute_section, &zero_address_frag, 0); - symbol_table_insert (sym); - symbol_get_bfdsym (sym)->flags |=3D BSF_DEBUGGING | BSF_DYNAMIC; - - p =3D frag_more (4); - /* Format 3 of VMS demangler Spec. */ - number_to_chars_littleendian (p, 3, 4); - - p =3D frag_more (4); - /* Place holder for symbol table index of above symbol. */ - number_to_chars_littleendian (p, -1, 4); - - frag_align (3, 0, 0); - - /* We probably can't restore the current segment, for there likely - isn't one yet... */ - if (seg && subseg) - subseg_set (seg, subseg); -} - -#endif /* TE_VMS */ diff --git a/gas/config/tc-ia64.h b/gas/config/tc-ia64.h deleted file mode 100644 index 8ab05373f6e..00000000000 --- a/gas/config/tc-ia64.h +++ /dev/null @@ -1,331 +0,0 @@ -/* tc-ia64.h -- Header file for tc-ia64.c. - Copyright (C) 1998-2024 Free Software Foundation, Inc. - Contributed by David Mosberger-Tang - - This file is part of GAS, the GNU Assembler. - - GAS is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3, or (at your option) - any later version. - - GAS is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with GAS; see the file COPYING. If not, write to - the Free Software Foundation, 51 Franklin Street - Fifth Floor, - Boston, MA 02110-1301, USA. */ - -#include "opcode/ia64.h" -#include "elf/ia64.h" - -#define TC_IA64 - -/* Linux is little endian by default. HPUX is big endian by default. */ -#ifdef TE_HPUX -#define TARGET_BYTES_BIG_ENDIAN 1 -#define MD_FLAGS_DEFAULT EF_IA_64_BE -#else -#define TARGET_BYTES_BIG_ENDIAN 0 -#define MD_FLAGS_DEFAULT EF_IA_64_ABI64 -#endif /* TE_HPUX */ - -extern void (*ia64_number_to_chars) (char *, valueT, int); -#define md_number_to_chars (*ia64_number_to_chars) - -extern void ia64_elf_section_change_hook (void); -#define md_elf_section_change_hook ia64_elf_section_change_hook - -/* We record the endian for this section. 0 means default, 1 means - big endian and 2 means little endian. */ -struct ia64_segment_info_type -{ - unsigned int endian : 2; -}; - -#define TC_SEGMENT_INFO_TYPE struct ia64_segment_info_type - -extern void ia64_adjust_symtab (void); -#define tc_adjust_symtab() ia64_adjust_symtab () - -extern void ia64_frob_file (void); -#define tc_frob_file() ia64_frob_file () - -/* We need to set the default object file format in ia64_init and not in - md_begin. This is because parse_args is called before md_begin, and we - do not want md_begin to wipe out the flag settings set by options parse= d in - md_parse_args. */ - -#define HOST_SPECIAL_INIT ia64_init -extern void ia64_init (int, char **); - -#define TARGET_FORMAT ia64_target_format() -extern const char *ia64_target_format (void); - -#define TARGET_ARCH bfd_arch_ia64 -#define DOUBLESLASH_LINE_COMMENTS /* allow //-style comments */ - -#define NEED_LITERAL_POOL /* need gp literal pool */ -#define RELOC_REQUIRES_SYMBOL -#define DIFF_EXPR_OK /* foo-. gets turned into PC relative relocs */ -#define NEED_INDEX_OPERATOR /* [ ] is index operator */ - -#define QUOTES_IN_INSN /* allow `string "foo;bar"' */ -#define LEX_AT (LEX_NAME|LEX_BEGIN_NAME) /* allow `@' inside name */ -#define LEX_QM (LEX_NAME|LEX_BEGIN_NAME) /* allow `?' inside name */ -#define LEX_HASH LEX_END_NAME /* allow `#' ending a name */ - -#define TC_PREDICATE_START_CHAR '(' -#define TC_PREDICATE_END_CHAR ')' - -extern const char ia64_symbol_chars[]; -#define tc_symbol_chars ia64_symbol_chars - -#define SUB_SEGMENT_ALIGN(SEG, FRCHAIN) 0 - -struct ia64_fix - { - int bigendian; /* byte order at fix location */ - enum ia64_opnd opnd; - }; - -extern void ia64_md_finish (void); -extern void ia64_start_line (void); -extern int ia64_unrecognized_line (int); -extern void ia64_frob_label (struct symbol *); -#ifdef TE_HPUX -extern int ia64_frob_symbol (struct symbol *); -#endif -extern void ia64_flush_pending_output (void); -extern int ia64_parse_name (char *, expressionS *, char *); -extern int ia64_optimize_expr (expressionS *, operatorT, expressionS *); -extern void ia64_cons_align (int); -extern void ia64_flush_insns (void); -extern int ia64_fix_adjustable (struct fix *); -extern int ia64_force_relocation (struct fix *); -extern void ia64_cons_fix_new (fragS *, int, int, expressionS *, - bfd_reloc_code_real_type); -extern void ia64_validate_fix (struct fix *); -extern char * ia64_canonicalize_symbol_name (char *); -extern bfd_vma ia64_elf_section_letter (int, const char **); -extern flagword ia64_elf_section_flags (flagword, bfd_vma, int); -extern int ia64_elf_section_type (const char *, size_t); -extern long ia64_pcrel_from_section (struct fix *, segT); -extern void ia64_md_do_align (int, const char *, int, int); -extern void ia64_handle_align (fragS *); -extern void ia64_after_parse_args (void); -extern void ia64_dwarf2_emit_offset (symbolS *, unsigned int); -extern void ia64_check_label (symbolS *); -extern int ia64_estimate_size_before_relax (fragS *, asection *); -extern void ia64_convert_frag (fragS *); - -#define md_finish() ia64_md_finish () -#define md_start_line_hook() ia64_start_line () -#define tc_unrecognized_line(ch) ia64_unrecognized_line (ch) -#define tc_frob_label(s) ia64_frob_label (s) -#ifdef TE_HPUX -#define tc_frob_symbol(s,p) p |=3D ia64_frob_symbol (s) -#endif /* TE_HPUX */ -#define md_flush_pending_output() ia64_flush_pending_output () -#define md_parse_name(s,e,m,c) ia64_parse_name (s, e, c) -#define md_register_arithmetic 0 -#define tc_canonicalize_symbol_name(s) ia64_canonicalize_symbol_name (s) -#define tc_canonicalize_section_name(s) ia64_canonicalize_symbol_name (s) -#define md_optimize_expr(l,o,r) ia64_optimize_expr (l, o, r) -#define md_cons_align(n) ia64_cons_align (n) -#define TC_FORCE_RELOCATION(f) ia64_force_relocation (f) -#define tc_fix_adjustable(f) ia64_fix_adjustable (f) -#define MD_APPLY_SYM_VALUE(FIX) 0 -#define md_convert_frag(b,s,f) ia64_convert_frag (f) -#define md_create_long_jump(p,f,t,fr,s) as_fatal ("ia64_create_long_jump") -#define md_create_short_jump(p,f,t,fr,s) \ - as_fatal ("ia64_create_short_jump") -#define md_estimate_size_before_relax(f,s) \ - ia64_estimate_size_before_relax(f,s) -#define md_elf_section_letter ia64_elf_section_letter -#define md_elf_section_flags ia64_elf_section_flags -#define TC_FIX_TYPE struct ia64_fix -#define TC_INIT_FIX_DATA(f) { f->tc_fix_data.opnd =3D 0; } -#define TC_CONS_FIX_NEW(f,o,l,e,r) ia64_cons_fix_new (f, o, l, e, r) -#define TC_VALIDATE_FIX(fix,seg,skip) ia64_validate_fix (fix) -#define MD_PCREL_FROM_SECTION(fix,sec) ia64_pcrel_from_section (fix, sec) -#define md_section_align(seg,size) (size) -#define md_do_align(n,f,l,m,j) ia64_md_do_align (n,f,l,m) -#define HANDLE_ALIGN(f) ia64_handle_align (f) -#define md_elf_section_type(str,len) ia64_elf_section_type (str, len) -#define md_after_parse_args() ia64_after_parse_args () -#define TC_DWARF2_EMIT_OFFSET ia64_dwarf2_emit_offset -#define tc_check_label(l) ia64_check_label (l) -#ifdef TE_VMS -#define tc_init_after_args() ia64_vms_note () -void ia64_vms_note (void); -#endif - -/* Record if an alignment frag should end with a stop bit. */ -#define TC_FRAG_TYPE int -#define TC_FRAG_INIT(FRAGP, MAX_BYTES) do {(FRAGP)->tc_frag_data =3D 0;}wh= ile (0) - -/* Give an error if a frag containing code is not aligned to a 16 byte - boundary. */ -#define md_frag_check(FRAGP) \ - if ((FRAGP)->has_code \ - && (((FRAGP)->fr_address + (FRAGP)->insn_addr) & 15) !=3D 0) \ - as_bad_where ((FRAGP)->fr_file, (FRAGP)->fr_line, \ - _("instruction address is not a multiple of 16")); - -#define MAX_MEM_FOR_RS_ALIGN_CODE (15 + 16) - -#define WORKING_DOT_WORD /* don't do broken word processing for now */ - -#define DWARF2_LINE_MIN_INSN_LENGTH 1 /* so slot-multipliers can be 1 */ - -/* This is the information required for unwind records in an ia64 - object file. This is required by GAS and the compiler runtime. */ - -/* These are the starting point masks for the various types of - unwind records. To create a record of type R3 for instance, one - starts by using the value UNW_R3 and or-ing in any other required value= s. - These values are also unique (in context), so they can be used to ident= ify - the various record types as well. UNW_Bx and some UNW_Px do have the - same value, but Px can only occur in a prologue context, and Bx in - a body context. */ - -#define UNW_R1 0x00 -#define UNW_R2 0x40 -#define UNW_R3 0x60 -#define UNW_P1 0x80 -#define UNW_P2 0xA0 -#define UNW_P3 0xB0 -#define UNW_P4 0xB8 -#define UNW_P5 0xB9 -#define UNW_P6 0xC0 -#define UNW_P7 0xE0 -#define UNW_P8 0xF0 -#define UNW_P9 0xF1 -#define UNW_P10 0xFF -#define UNW_X1 0xF9 -#define UNW_X2 0xFA -#define UNW_X3 0xFB -#define UNW_X4 0xFC -#define UNW_B1 0x80 -#define UNW_B2 0xC0 -#define UNW_B3 0xE0 -#define UNW_B4 0xF0 - -/* These are all the various types of unwind records. */ - -typedef enum -{ - prologue, prologue_gr, body, mem_stack_f, mem_stack_v, psp_gr, psp_sprel, - rp_when, rp_gr, rp_br, rp_psprel, rp_sprel, pfs_when, pfs_gr, pfs_psprel, - pfs_sprel, preds_when, preds_gr, preds_psprel, preds_sprel, - fr_mem, frgr_mem, gr_gr, gr_mem, br_mem, br_gr, spill_base, spill_mask, - unat_when, unat_gr, unat_psprel, unat_sprel, lc_when, lc_gr, lc_psprel, - lc_sprel, fpsr_when, fpsr_gr, fpsr_psprel, fpsr_sprel, - priunat_when_gr, priunat_when_mem, priunat_gr, priunat_psprel, - priunat_sprel, bsp_when, bsp_gr, bsp_psprel, bsp_sprel, bspstore_when, - bspstore_gr, bspstore_psprel, bspstore_sprel, rnat_when, rnat_gr, - rnat_psprel, rnat_sprel, epilogue, label_state, copy_state, - spill_psprel, spill_sprel, spill_reg, spill_psprel_p, spill_sprel_p, - spill_reg_p, unwabi, endp -} unw_record_type; - -/* These structures declare the fields that can be used in each of the - 4 record formats, R, P, B and X. */ - -typedef struct unw_r_record -{ - unsigned long rlen; - unsigned short grmask; - unsigned short grsave; - /* masks to represent the union of save.g, save.f, save.b, and - save.gf: */ - unsigned long imask_size; - struct - { - unsigned char *i; - unsigned int fr_mem; - unsigned char gr_mem; - unsigned char br_mem; - } mask; -} unw_r_record; - -typedef struct unw_p_record -{ - struct unw_rec_list *next; - unsigned long t; - unsigned long size; - union - { - unsigned long sp; - unsigned long psp; - } off; - union - { - unsigned short gr; - unsigned short br; - } r; - unsigned char grmask; - unsigned char brmask; - unsigned int frmask; - unsigned char abi; - unsigned char context; -} unw_p_record; - -typedef struct unw_b_record -{ - unsigned long t; - unsigned long label; - unsigned short ecount; -} unw_b_record; - -typedef struct unw_x_record -{ - unsigned long t; - union - { - unsigned long spoff; - unsigned long pspoff; - unsigned int reg; - } where; - unsigned short reg; - unsigned short qp; - unsigned short ab; /* Value of the AB field.. */ - unsigned short xy; /* Value of the XY field.. */ -} unw_x_record; - -/* This structure is used to determine the specific record type and - its fields. */ -typedef struct unwind_record -{ - unw_record_type type; - union { - unw_r_record r; - unw_p_record p; - unw_b_record b; - unw_x_record x; - } record; -} unwind_record; - -/* This expression evaluates to true if the relocation is for a local - object for which we still want to do the relocation at runtime. - False if we are willing to perform this relocation while building - the .o file. */ - -/* If the reloc type is BFD_RELOC_UNUSED, then this is for a TAG13/TAG13b = field - which has no external reloc, so we must resolve the value now. */ - -#define TC_FORCE_RELOCATION_LOCAL(FIX) \ - ((FIX)->fx_r_type !=3D BFD_RELOC_UNUSED \ - && (GENERIC_FORCE_RELOCATION_LOCAL (FIX) \ - || (FIX)->fx_r_type =3D=3D BFD_RELOC_IA64_PLTOFF22)) - -/* VMS backtraces expect dwarf version 3. */ -#ifdef TE_VMS -#define DWARF2_VERSION (dwarf_level < 3 ? 3 : dwarf_level) -#endif - -#define md_single_noop_insn "nop 0" diff --git a/gas/config/te-ia64aix.h b/gas/config/te-ia64aix.h deleted file mode 100644 index ff33f7ee58f..00000000000 --- a/gas/config/te-ia64aix.h +++ /dev/null @@ -1,23 +0,0 @@ -/* Copyright (C) 2007-2024 Free Software Foundation, Inc. - - This file is part of GAS, the GNU Assembler. - - GAS is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as - published by the Free Software Foundation; either version 3, - or (at your option) any later version. - - GAS is distributed in the hope that it will be useful, but - WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See - the GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with GAS; see the file COPYING. If not, write to the Free - Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA - 02110-1301, USA. */ - -#define TE_AIX50 -#define LOCAL_LABELS_FB 1 - -#include "obj-format.h" diff --git a/gas/configure b/gas/configure index e6811fe73bd..091722b55d4 100755 --- a/gas/configure +++ b/gas/configure @@ -5662,10 +5662,6 @@ haiku*) hpux10.20* | hpux11*) lt_cv_file_magic_cmd=3D/usr/bin/file case $host_cpu in - ia64*) - lt_cv_deplibs_check_method=3D'file_magic (s[0-9][0-9][0-9]|ELF-[0-9][0= -9]) shared object file - IA64' - lt_cv_file_magic_test_file=3D/usr/lib/hpux32/libc.so - ;; hppa*64*) lt_cv_deplibs_check_method=3D'file_magic (s[0-9][0-9][0-9]|ELF[ -][0-9= ][0-9])(-bit)?( [LM]SB)? shared object( file)?[, -]* PA-RISC [0-9]\.[0-9]' lt_cv_file_magic_test_file=3D/usr/lib/pa20_64/libc.sl @@ -6224,11 +6220,6 @@ aix*) cygwin* | mingw* | pw32* | cegcc*) symcode=3D'[ABCDGISTW]' ;; -hpux*) - if test "$host_cpu" =3D ia64; then - symcode=3D'[ABCDEGRST]' - fi - ;; irix* | nonstopux*) symcode=3D'[BCDEGRST]' ;; @@ -6259,7 +6250,7 @@ case `$NM -V 2>&1` in esac =20 # Transform an extracted symbol line into a proper C declaration. -# Some systems (esp. on ia64) link data and code symbols differently, +# Some systems link data and code symbols differently, # so use this general approach. lt_cv_sys_global_symbol_to_cdecl=3D"sed -n -e 's/^T .* \(.*\)$/extern int = \1();/p' -e 's/^$symcode* .* \(.*\)$/extern char \1;/p'" =20 @@ -6459,25 +6450,6 @@ test "x$enable_libtool_lock" !=3D xno && enable_libt= ool_lock=3Dyes # Some flags need to be propagated to the compiler or linker for good # libtool support. case $host in -ia64-*-hpux*) - # Find out which ABI we are using. - echo 'int i;' > conftest.$ac_ext - if { { eval echo "\"\$as_me\":${as_lineno-$LINENO}: \"$ac_compile\""; } = >&5 - (eval $ac_compile) 2>&5 - ac_status=3D$? - $as_echo "$as_me:${as_lineno-$LINENO}: \$? =3D $ac_status" >&5 - test $ac_status =3D 0; }; then - case `/usr/bin/file conftest.$ac_objext` in - *ELF-32*) - HPUX_IA64_MODE=3D"32" - ;; - *ELF-64*) - HPUX_IA64_MODE=3D"64" - ;; - esac - fi - rm -rf conftest* - ;; *-*-irix6*) # Find out which ABI we are using. echo '#line '$LINENO' "configure"' > conftest.$ac_ext @@ -7812,10 +7784,6 @@ $as_echo_n "checking for $compiler option to produce= PIC... " >&6; } case $host_os in aix*) # All AIX code is PIC. - if test "$host_cpu" =3D ia64; then - # AIX 5 now supports IA64 processor - lt_prog_compiler_static=3D'-Bstatic' - fi lt_prog_compiler_pic=3D'-fPIC' ;; =20 @@ -7912,12 +7880,7 @@ $as_echo_n "checking for $compiler option to produce= PIC... " >&6; } case $host_os in aix*) lt_prog_compiler_wl=3D'-Wl,' - if test "$host_cpu" =3D ia64; then - # AIX 5 now supports IA64 processor - lt_prog_compiler_static=3D'-Bstatic' - else - lt_prog_compiler_static=3D'-bnso -bI:/lib/syscalls.exp' - fi + lt_prog_compiler_static=3D'-bnso -bI:/lib/syscalls.exp' ;; =20 mingw* | cygwin* | pw32* | os2* | cegcc*) @@ -7931,7 +7894,7 @@ $as_echo_n "checking for $compiler option to produce = PIC... " >&6; } # PIC is the default for IA64 HP-UX and 64-bit HP-UX, but # not for PA HP-UX. case $host_cpu in - hppa*64*|ia64*) + hppa*64*) # +Z the default ;; *) @@ -8456,7 +8419,6 @@ $as_echo_n "checking whether the $compiler linker ($L= D) supports shared librarie case $host_os in aix[3-9]*) # On AIX/PPC, the GNU linker is very broken - if test "$host_cpu" !=3D ia64; then ld_shlibs=3Dno cat <<_LT_EOF 1>&2 =20 @@ -8468,7 +8430,6 @@ $as_echo_n "checking whether the $compiler linker ($L= D) supports shared librarie *** You will then need to restart the configuration process. =20 _LT_EOF - fi ;; =20 amigaos*) @@ -8564,10 +8525,6 @@ _LT_EOF # Portland Group f77 and f90 compilers whole_archive_flag_spec=3D'${wl}--whole-archive`for conv in $convenienc= e\"\"; do test -n \"$conv\" && new_convenience=3D\"$new_convenience,$conv\= "; done; func_echo_all \"$new_convenience\"` ${wl}--no-whole-archive' tmp_addflag=3D' $pic_flag -Mnomain' ;; - ecc*,ia64* | icc*,ia64*) # Intel C compiler on ia64 - tmp_addflag=3D' -i_dynamic' ;; - efc*,ia64* | ifort*,ia64*) # Intel Fortran compiler on ia64 - tmp_addflag=3D' -i_dynamic -nofor_main' ;; ifc* | ifort*) # Intel Fortran compiler tmp_addflag=3D' -nofor_main' ;; lf95*) # Lahey Fortran 8.1 @@ -8721,13 +8678,6 @@ _LT_EOF ;; =20 aix[4-9]*) - if test "$host_cpu" =3D ia64; then - # On IA64, the linker does run time linking by default, so we don't - # have to do anything special. - aix_use_runtimelinking=3Dno - exp_sym_flag=3D'-Bexport' - no_entry_flag=3D"" - else # If we're using GNU nm, then we don't want the "-C" option. # -C means demangle to AIX nm, but means don't demangle with GNU nm # Also, AIX nm treats weak defined symbols like other global @@ -8754,7 +8704,6 @@ _LT_EOF =20 exp_sym_flag=3D'-bexport' no_entry_flag=3D'-bnoentry' - fi =20 # When large executables or shared objects are built, AIX ld can # have problems creating the table of contents. If linking a library @@ -8797,17 +8746,11 @@ _LT_EOF fi else # not using gcc - if test "$host_cpu" =3D ia64; then - # VisualAge C++, Version 5.5 for AIX 5L for IA-64, Beta 3 Release - # chokes on -Wl,-G. The following line is correct: - shared_flag=3D'-G' - else if test "$aix_use_runtimelinking" =3D yes; then shared_flag=3D'${wl}-G' else shared_flag=3D'${wl}-bM:SRE' fi - fi fi =20 export_dynamic_flag_spec=3D'${wl}-bexpall' @@ -8853,11 +8796,6 @@ if test -z "$aix_libpath"; then aix_libpath=3D"/usr/= lib:/lib"; fi hardcode_libdir_flag_spec=3D'${wl}-blibpath:$libdir:'"$aix_libpath" archive_expsym_cmds=3D'$CC -o $output_objdir/$soname $libobjs $dep= libs '"\${wl}$no_entry_flag"' $compiler_flags `if test "x${allow_undefined_= flag}" !=3D "x"; then func_echo_all "${wl}${allow_undefined_flag}"; else :;= fi` '"\${wl}$exp_sym_flag:\$export_symbols $shared_flag" else - if test "$host_cpu" =3D ia64; then - hardcode_libdir_flag_spec=3D'${wl}-R $libdir:/usr/lib:/lib' - allow_undefined_flag=3D"-z nodefs" - archive_expsym_cmds=3D"\$CC $shared_flag"' -o $output_objdir/$soname $l= ibobjs $deplibs '"\${wl}$no_entry_flag"' $compiler_flags ${wl}${allow_undef= ined_flag} '"\${wl}$exp_sym_flag:\$export_symbols" - else # Determine the default libpath from the value encoded in an # empty executable. cat confdefs.h - <<_ACEOF >conftest.$ac_ext @@ -8905,7 +8843,6 @@ if test -z "$aix_libpath"; then aix_libpath=3D"/usr/l= ib:/lib"; fi archive_cmds_need_lc=3Dyes # This is similar to how AIX traditionally builds its shared libraries. archive_expsym_cmds=3D"\$CC $shared_flag"' -o $output_objdir/$soname $l= ibobjs $deplibs ${wl}-bnoentry $compiler_flags ${wl}-bE:$export_symbols${al= low_undefined_flag}~$AR $AR_FLAGS $output_objdir/$libname$release.a $output= _objdir/$soname' - fi fi ;; =20 @@ -9054,9 +8991,6 @@ if test -z "$aix_libpath"; then aix_libpath=3D"/usr/l= ib:/lib"; fi hppa*64*) archive_cmds=3D'$CC -shared ${wl}+h ${wl}$soname ${wl}+nodefaultrpath -= o $lib $libobjs $deplibs $compiler_flags' ;; - ia64*) - archive_cmds=3D'$CC -shared -fPIC ${wl}+h ${wl}$soname ${wl}+nodefaultr= path -o $lib $libobjs $deplibs $compiler_flags' - ;; *) archive_cmds=3D'$CC -shared -fPIC ${wl}+h ${wl}$soname ${wl}+b ${wl}$in= stall_libdir -o $lib $libobjs $deplibs $compiler_flags' ;; @@ -9066,9 +9000,6 @@ if test -z "$aix_libpath"; then aix_libpath=3D"/usr/l= ib:/lib"; fi hppa*64*) archive_cmds=3D'$CC -b ${wl}+h ${wl}$soname ${wl}+nodefaultrpath -o $li= b $libobjs $deplibs $compiler_flags' ;; - ia64*) - archive_cmds=3D'$CC -b ${wl}+h ${wl}$soname ${wl}+nodefaultrpath -o $li= b $libobjs $deplibs $compiler_flags' - ;; *) =20 # Older versions of the 11.00 compiler do not understand -b yet @@ -9118,7 +9049,7 @@ fi hardcode_libdir_separator=3D: =20 case $host_cpu in - hppa*64*|ia64*) + hppa*64*) hardcode_direct=3Dno hardcode_shlibpath_var=3Dno ;; @@ -9755,11 +9686,6 @@ aix[4-9]*) need_lib_prefix=3Dno need_version=3Dno hardcode_into_libs=3Dyes - if test "$host_cpu" =3D ia64; then - # AIX 5 supports IA64 - library_names_spec=3D'${libname}${release}${shared_ext}$major ${libnam= e}${release}${shared_ext}$versuffix $libname${shared_ext}' - shlibpath_var=3DLD_LIBRARY_PATH - else # With GCC up to 2.95.x, collect2 would create an import file # for dependence libraries. The import file would start with # the line `#! .'. This would cause the generated library to @@ -9791,7 +9717,6 @@ aix[4-9]*) soname_spec=3D'${libname}${release}${shared_ext}$major' fi shlibpath_var=3DLIBPATH - fi ;; =20 amigaos*) @@ -9968,21 +9893,6 @@ hpux9* | hpux10* | hpux11*) need_lib_prefix=3Dno need_version=3Dno case $host_cpu in - ia64*) - shrext_cmds=3D'.so' - hardcode_into_libs=3Dyes - dynamic_linker=3D"$host_os dld.so" - shlibpath_var=3DLD_LIBRARY_PATH - shlibpath_overrides_runpath=3Dyes # Unless +noenvvar is specified. - library_names_spec=3D'${libname}${release}${shared_ext}$versuffix ${li= bname}${release}${shared_ext}$major $libname${shared_ext}' - soname_spec=3D'${libname}${release}${shared_ext}$major' - if test "X$HPUX_IA64_MODE" =3D X32; then - sys_lib_search_path_spec=3D"/usr/lib/hpux32 /usr/local/lib/hpux32 /u= sr/local/lib" - else - sys_lib_search_path_spec=3D"/usr/lib/hpux64 /usr/local/lib/hpux64" - fi - sys_lib_dlsearch_path_spec=3D$sys_lib_search_path_spec - ;; hppa*64*) shrext_cmds=3D'.sl' hardcode_into_libs=3Dyes @@ -11073,7 +10983,7 @@ $as_echo_n "checking whether to build shared librar= ies... " >&6; } ;; =20 aix[4-9]*) - if test "$host_cpu" !=3D ia64 && test "$aix_use_runtimelinking" =3D no= ; then + if test "$aix_use_runtimelinking" =3D no ; then test "$enable_shared" =3D yes && enable_static=3Dno fi ;; diff --git a/gas/configure.com b/gas/configure.com index c5b6fc5683c..8efbe9b565e 100644 --- a/gas/configure.com +++ b/gas/configure.com @@ -29,13 +29,6 @@ $ env =3D "generic" $ target_alias =3D "alpha-dec-openvms" $ target_canonical =3D "alpha-dec-openvms" $ endif -$ if arch.eqs."ia64" -$ then -$ format =3D "elf" -$ env =3D "vms" -$ target_alias =3D "ia64-openvms" -$ target_canonical =3D "ia64-unknown-openvms" -$ endif $! $! $ write sys$output "Generate targ-cpu.[ch]" @@ -244,15 +237,6 @@ $ write sys$output "CFLAGS=3D",CFLAGS $! $EOD $! -$ if arch.eqs."ia64" -$ then -$ open/append outfile build.com -$ write outfile "$ write sys$output ""Compiling te-vms.c""" -$ write outfile "$ cc 'CFLAGS /obj=3Dte-vms.obj [.config]te-vms.c + " +- - "sys$library:sys$lib_c.tlb/lib" -$ write outfile "$ AS_OBJS=3DAS_OBJS + "",te-vms.obj""" -$ close outfile -$ endif $! $ append sys$input build.com $DECK diff --git a/gas/configure.tgt b/gas/configure.tgt index 7c66734e362..7a873521705 100644 --- a/gas/configure.tgt +++ b/gas/configure.tgt @@ -63,7 +63,6 @@ case ${cpu} in hppa*) cpu_type=3Dhppa ;; i[3-7]86) cpu_type=3Di386 arch=3Di386;; ia16) cpu_type=3Di386 arch=3Di386;; - ia64) cpu_type=3Dia64 ;; ip2k) cpu_type=3Dip2k endian=3Dbig ;; iq2000) cpu_type=3Diq2000 endian=3Dbig ;; kvx) cpu_type=3Dkvx endian=3Dlittle ;; @@ -270,13 +269,6 @@ case ${generic_target} in =20 ia16-*-elf*) fmt=3Delf ;; =20 - ia64-*-elf*) fmt=3Delf ;; - ia64-*-*vms*) fmt=3Delf em=3Dvms ;; - ia64-*-aix*) fmt=3Delf em=3Dia64aix ;; - ia64-*-linux-*) fmt=3Delf em=3Dlinux ;; - ia64-*-hpux*) fmt=3Delf em=3Dhpux ;; - ia64-*-netbsd*) fmt=3Delf em=3Dnbsd ;; - ip2k-*-*) fmt=3Delf ;; =20 iq2000-*-elf) fmt=3Delf ;; @@ -452,7 +444,7 @@ case ${generic_target} in esac =20 case ${cpu_type} in - aarch64 | alpha | arm | csky | i386 | ia64 | kvx | microblaze | mips | n= s32k | \ + aarch64 | alpha | arm | csky | i386 | kvx | microblaze | mips | ns32k | \ or1k | or1knd | pdp11 | ppc | riscv | sh | sparc | z80 | z8k | loongarch) bfd_gas=3Dyes ;; diff --git a/gas/doc/as.texi b/gas/doc/as.texi index 42db11e91da..999ababfb4d 100644 --- a/gas/doc/as.texi +++ b/gas/doc/as.texi @@ -380,17 +380,6 @@ gcc(1), ld(1), and the Info entries for @file{binutils= } and @file{ld}. [@b{--32}|@b{--x32}|@b{--64}] [@b{-n}] [@b{-march}=3D@var{CPU}[+@var{EXTENSION}@dots{}]] [@b{-mtune}=3D@var{CP= U}] @end ifset -@ifset IA64 - -@emph{Target IA-64 options:} - [@b{-mconstant-gp}|@b{-mauto-pic}] - [@b{-milp32}|@b{-milp64}|@b{-mlp64}|@b{-mp64}] - [@b{-mle}|@b{mbe}] - [@b{-mtune=3Ditanium1}|@b{-mtune=3Ditanium2}] - [@b{-munwind-check=3Dwarning}|@b{-munwind-check=3Derror}] - [@b{-mhint.b=3Dok}|@b{-mhint.b=3Dwarning}|@b{-mhint.b=3Derror}] - [@b{-x}|@b{-xexplicit}] [@b{-xauto}] [@b{-xdebug}] -@end ifset @ifset IP2K =20 @emph{Target IP2K options:} @@ -8086,9 +8075,6 @@ subject, see the hardware manufacturer's manual. @ifset I80386 * i386-Dependent:: Intel 80386 and AMD x86-64 Dependent Featu= res @end ifset -@ifset IA64 -* IA-64-Dependent:: Intel IA-64 Dependent Features -@end ifset @ifset IP2K * IP2K-Dependent:: IP2K Dependent Features @end ifset @@ -8310,10 +8296,6 @@ family. @include c-i386.texi @end ifset =20 -@ifset IA64 -@include c-ia64.texi -@end ifset - @ifset IP2K @include c-ip2k.texi @end ifset diff --git a/gas/doc/c-ia64.texi b/gas/doc/c-ia64.texi deleted file mode 100644 index 1f1855340dd..00000000000 --- a/gas/doc/c-ia64.texi +++ /dev/null @@ -1,201 +0,0 @@ -@c Copyright (C) 2002-2024 Free Software Foundation, Inc. -@c Contributed by David Mosberger-Tang -@c This is part of the GAS manual. -@c For copying conditions, see the file as.texinfo. - -@ifset GENERIC -@page -@node IA-64-Dependent -@chapter IA-64 Dependent Features -@end ifset - -@ifclear GENERIC -@node Machine Dependencies -@chapter IA-64 Dependent Features -@end ifclear - -@cindex IA-64 support -@menu -* IA-64 Options:: Options -* IA-64 Syntax:: Syntax -@c * IA-64 Floating Point:: Floating Point // to be written -@c * IA-64 Directives:: IA-64 Machine Directives // to be written -* IA-64 Opcodes:: Opcodes -@end menu - -@node IA-64 Options -@section Options -@cindex IA-64 options -@cindex options for IA-64 - -@table @option -@cindex @code{-mconstant-gp} command-line option, IA-64 - -@item -mconstant-gp -This option instructs the assembler to mark the resulting object file -as using the ``constant GP'' model. With this model, it is assumed -that the entire program uses a single global pointer (GP) value. Note -that this option does not in any fashion affect the machine code -emitted by the assembler. All it does is turn on the EF_IA_64_CONS_GP -flag in the ELF file header. - -@item -mauto-pic -This option instructs the assembler to mark the resulting object file -as using the ``constant GP without function descriptor'' data model. -This model is like the ``constant GP'' model, except that it -additionally does away with function descriptors. What this means is -that the address of a function refers directly to the function's code -entry-point. Normally, such an address would refer to a function -descriptor, which contains both the code entry-point and the GP-value -needed by the function. Note that this option does not in any fashion -affect the machine code emitted by the assembler. All it does is -turn on the EF_IA_64_NOFUNCDESC_CONS_GP flag in the ELF file header. - -@item -milp32 -@itemx -milp64 -@itemx -mlp64 -@itemx -mp64 -These options select the data model. The assembler defaults to @code{-mlp= 64} -(LP64 data model). - -@item -mle -@itemx -mbe -These options select the byte order. The @code{-mle} option selects littl= e-endian -byte order (default) and @code{-mbe} selects big-endian byte order. Note = that -IA-64 machine code always uses little-endian byte order. - -@item -mtune=3Ditanium1 -@itemx -mtune=3Ditanium2 -Tune for a particular IA-64 CPU, @var{itanium1} or @var{itanium2}. The -default is @var{itanium2}. - -@item -munwind-check=3Dwarning -@itemx -munwind-check=3Derror -These options control what the assembler will do when performing -consistency checks on unwind directives. @code{-munwind-check=3Dwarning} -will make the assembler issue a warning when an unwind directive check -fails. This is the default. @code{-munwind-check=3Derror} will make the -assembler issue an error when an unwind directive check fails. - -@item -mhint.b=3Dok -@itemx -mhint.b=3Dwarning -@itemx -mhint.b=3Derror -These options control what the assembler will do when the @samp{hint.b} -instruction is used. @code{-mhint.b=3Dok} will make the assembler accept -@samp{hint.b}. @code{-mint.b=3Dwarning} will make the assembler issue a -warning when @samp{hint.b} is used. @code{-mhint.b=3Derror} will make -the assembler treat @samp{hint.b} as an error, which is the default. - -@item -x -@itemx -xexplicit -These options turn on dependency violation checking. - -@item -xauto -This option instructs the assembler to automatically insert stop bits wher= e necessary -to remove dependency violations. This is the default mode. - -@item -xnone -This option turns off dependency violation checking. - -@item -xdebug -This turns on debug output intended to help tracking down bugs in the depe= ndency -violation checker. - -@item -xdebugn -This is a shortcut for -xnone -xdebug. - -@item -xdebugx -This is a shortcut for -xexplicit -xdebug. - -@end table - -@cindex IA-64 Syntax -@node IA-64 Syntax -@section Syntax -The assembler syntax closely follows the IA-64 Assembly Language -Reference Guide. - -@menu -* IA-64-Chars:: Special Characters -* IA-64-Regs:: Register Names -* IA-64-Bits:: Bit Names -* IA-64-Relocs:: Relocations -@end menu - -@node IA-64-Chars -@subsection Special Characters - -@cindex line comment character, IA-64 -@cindex IA-64 line comment character -@samp{//} is the line comment token. - -@cindex line separator, IA-64 -@cindex statement separator, IA-64 -@cindex IA-64 line separator -@samp{;} can be used instead of a newline to separate statements. - -@node IA-64-Regs -@subsection Register Names -@cindex IA-64 registers -@cindex register names, IA-64 - -The 128 integer registers are referred to as @samp{r@var{n}}. -The 128 floating-point registers are referred to as @samp{f@var{n}}. -The 128 application registers are referred to as @samp{ar@var{n}}. -The 128 control registers are referred to as @samp{cr@var{n}}. -The 64 one-bit predicate registers are referred to as @samp{p@var{n}}. -The 8 branch registers are referred to as @samp{b@var{n}}. -In addition, the assembler defines a number of aliases: -@samp{gp} (@samp{r1}), @samp{sp} (@samp{r12}), @samp{rp} (@samp{b0}), -@samp{ret0} (@samp{r8}), @samp{ret1} (@samp{r9}), @samp{ret2} (@samp{r10}), -@samp{ret3} (@samp{r9}), @samp{farg@var{n}} (@samp{f8+@var{n}}), and -@samp{fret@var{n}} (@samp{f8+@var{n}}). - -For convenience, the assembler also defines aliases for all named applicat= ion -and control registers. For example, @samp{ar.bsp} refers to the register -backing store pointer (@samp{ar17}). Similarly, @samp{cr.eoi} refers to -the end-of-interrupt register (@samp{cr67}). - -@node IA-64-Bits -@subsection IA-64 Processor-Status-Register (PSR) Bit Names -@cindex IA-64 Processor-status-Register bit names -@cindex PSR bits -@cindex bit names, IA-64 - -The assembler defines bit masks for each of the bits in the IA-64 -processor status register. For example, @samp{psr.ic} corresponds to -a value of 0x2000. These masks are primarily intended for use with -the @samp{ssm}/@samp{sum} and @samp{rsm}/@samp{rum} -instructions, but they can be used anywhere else where an integer -constant is expected. - -@node IA-64-Relocs -@subsection Relocations -@cindex IA-64 relocations - -In addition to the standard IA-64 relocations, the following relocations a= re -implemented by @code{@value{AS}}: - -@table @code -@item @@slotcount(@var{V}) -Convert the address offset @var{V} into a slot count. This pseudo -function is available only on VMS. The expression @var{V} must be -known at assembly time: it can't reference undefined symbols or symbols in -different sections. -@end table - -@node IA-64 Opcodes -@section Opcodes -For detailed information on the IA-64 machine instruction set, see the -@c Attempt to work around a very overfull hbox. -@iftex -IA-64 Assembly Language Reference Guide available at -@smallfonts -@example -http://developer.intel.com/design/itanium/arch_spec.htm -@end example -@textfonts -@end iftex -@ifnottex -@uref{http://developer.intel.com/design/itanium/arch_spec.htm,IA-64 Archit= ecture Handbook}. -@end ifnottex diff --git a/gas/testsuite/gas/all/gas.exp b/gas/testsuite/gas/all/gas.exp index b9ff43997cb..5ee850fd774 100644 --- a/gas/testsuite/gas/all/gas.exp +++ b/gas/testsuite/gas/all/gas.exp @@ -495,9 +495,6 @@ switch -glob $target_triplet { or1k*-*-* { set nop_type 2 } - ia64-*-* { - set nop_type 1 - } default { set nop_type 0 } diff --git a/gas/testsuite/gas/all/local-label-overflow.d b/gas/testsuite/g= as/all/local-label-overflow.d index e0895daa3e5..5426b7912c9 100644 --- a/gas/testsuite/gas/all/local-label-overflow.d +++ b/gas/testsuite/gas/all/local-label-overflow.d @@ -3,4 +3,4 @@ # Some hppa targets support local labels, others don't. It's a pain to # enumerate all the combinations so just don't run the test for hppa. #notarget: hppa*-*-* -#xfail: ia64-*-vms mmix-*-* sh-*-pe +#xfail: mmix-*-* sh-*-pe diff --git a/gas/testsuite/gas/elf/bad-bss.d b/gas/testsuite/gas/elf/bad-bs= s.d index 24a2c620d73..283af0b4bfc 100644 --- a/gas/testsuite/gas/elf/bad-bss.d +++ b/gas/testsuite/gas/elf/bad-bss.d @@ -1,4 +1,4 @@ #name: bad .bss / .struct data allocation directives #source: bss.s #error_output: bad-bss.err -#target: i?86-*-* x86_64-*-* ia64-*-* arm-*-* aarch64-*-* kvx-*-* +#target: i?86-*-* x86_64-*-* arm-*-* aarch64-*-* kvx-*-* diff --git a/gas/testsuite/gas/elf/bss.d b/gas/testsuite/gas/elf/bss.d index 7edba655b9c..780b0b8eeb6 100644 --- a/gas/testsuite/gas/elf/bss.d +++ b/gas/testsuite/gas/elf/bss.d @@ -2,7 +2,7 @@ #as: --defsym okay=3D1 #warning: Warning: zero assumed #readelf: -sSW -#target: i?86-*-* x86_64-*-* ia64-*-* arm-*-* aarch64-*-* kvx-*-* +#target: i?86-*-* x86_64-*-* arm-*-* aarch64-*-* kvx-*-* =20 There are [1-9][0-9]* section headers, starting at offset 0x[0-9a-f]*: =20 diff --git a/gas/testsuite/gas/elf/elf.exp b/gas/testsuite/gas/elf/elf.exp index c828c3af25c..3fc737aa7fa 100644 --- a/gas/testsuite/gas/elf/elf.exp +++ b/gas/testsuite/gas/elf/elf.exp @@ -365,10 +365,6 @@ if { [is_elf_format] } then { # hpux has a non-standard common directive. if { ![istarget "*-*-hpux*"] } then { switch -glob $target_triplet { - ia64-*-* { - run_dump_test "common3a" { { as "--defsym lcomm_align=3D1" } } - run_dump_test "common3b" { { as "--defsym lcomm_align=3D1" } } - } default { run_dump_test "common3a" run_dump_test "common3b" diff --git a/gas/testsuite/gas/elf/file.s b/gas/testsuite/gas/elf/file.s index 7718cc7c785..7248f4df4ec 100644 --- a/gas/testsuite/gas/elf/file.s +++ b/gas/testsuite/gas/elf/file.s @@ -1,9 +1,6 @@ # delta (m68k sub-target) .file "~tilde" =20 - # ia64 - .file "hash#" - # m68k .ifdef m86k .opt nocase diff --git a/gas/testsuite/gas/ia64/alias-ilp32.d b/gas/testsuite/gas/ia64/= alias-ilp32.d deleted file mode 100644 index fb760008e9f..00000000000 --- a/gas/testsuite/gas/ia64/alias-ilp32.d +++ /dev/null @@ -1,28 +0,0 @@ -#readelf: -Ss -#name: ia64 alias and secalias (ilp32) -#as: -milp32 -#source: alias.s - -There are 8 section headers, starting at offset .*: - -Section Headers: - +\[Nr\] +Name +Type +Addr +Off +Size +ES +Flg +Lk +Inf +Al - +\[ 0\] +NULL +00000000 000000 000000 00 +0 +0 +0 - +\[ 1\] .text +PROGBITS +00000000 000040 000000 00 +AX +0 +0 16 - +\[ 2\] .data +PROGBITS +00000000 000040 000000 00 +WA +0 +0 +1 - +\[ 3\] .bss +NOBITS +00000000 000040 000000 00 +WA +0 +0 +1 - +\[ 4\] 1234 +PROGBITS +00000000 000040 000005 00 +WA +0 +0 +1 - +\[ 5\] .symtab +SYMTAB +00000000 [0-9a-f]+ 000060 10 +6 +6 +4 - +\[ 6\] .strtab +STRTAB +00000000 [0-9a-f]+ 000006 00 +0 +0 +1 - +\[ 7\] .shstrtab +STRTAB +00000000 [0-9a-f]+ 000031 00 +0 +0 +1 -Key to Flags: -#... - -Symbol table '.symtab' contains 6 entries: - +Num: +Value +Size +Type +Bind +Vis +Ndx +Name - +0: 00000000 +0 +NOTYPE +LOCAL +DEFAULT +UND=20 - +1: 00000000 +0 +SECTION +LOCAL +DEFAULT +1.* - +2: 00000000 +0 +SECTION +LOCAL +DEFAULT +2.* - +3: 00000000 +0 +SECTION +LOCAL +DEFAULT +3.* - +4: 00000000 +0 +SECTION +LOCAL +DEFAULT +4.* - +5: 00000000 +0 +NOTYPE +LOCAL +DEFAULT +4 "@D" diff --git a/gas/testsuite/gas/ia64/alias.d b/gas/testsuite/gas/ia64/alias.d deleted file mode 100644 index 762f5c8f015..00000000000 --- a/gas/testsuite/gas/ia64/alias.d +++ /dev/null @@ -1,35 +0,0 @@ -#readelf: -Ss -#name: ia64 alias and secalias - -There are 8 section headers, starting at offset .*: - -Section Headers: - +\[Nr\] +Name +Type +Address +Offset - +Size +EntSize +Flags +Link +Info +Align - +\[ 0\] +NULL +0000000000000000 +00000000 - +0000000000000000 +0000000000000000 +0 +0 +0 - +\[ 1\] \.text +PROGBITS +0000000000000000 +00000040 - +0000000000000000 +0000000000000000 +AX +0 +0 +16 - +\[ 2\] \.data +PROGBITS +0000000000000000 +00000040 - +0000000000000000 +0000000000000000 +WA +0 +0 +1 - +\[ 3\] \.bss +NOBITS +0000000000000000 +00000040 - +0000000000000000 +0000000000000000 +WA +0 +0 +1 - +\[ 4\] 1234 +PROGBITS +0000000000000000 +00000040 - +0000000000000005 +0000000000000000 +WA +0 +0 +1 - +\[ 5\] \.symtab +SYMTAB +0000000000000000 .* - +0000000000000090 +0000000000000018 +6 +6 +8 - +\[ 6\] \.strtab +STRTAB +0000000000000000 .* - +0000000000000006 +0000000000000000 +0 +0 +1 - +\[ 7\] \.shstrtab +STRTAB +0000000000000000 +[0-9a-f]+ - +0000000000000031 +0000000000000000 +0 +0 +1 -Key to Flags: -#... - -Symbol table '\.symtab' contains 6 entries: - +Num: +Value +Size +Type +Bind +Vis +Ndx +Name - +0: 0000000000000000 +0 +NOTYPE +LOCAL +DEFAULT +UND=20 - +1: 0000000000000000 +0 +SECTION +LOCAL +DEFAULT +1.* - +2: 0000000000000000 +0 +SECTION +LOCAL +DEFAULT +2.* - +3: 0000000000000000 +0 +SECTION +LOCAL +DEFAULT +3.* - +4: 0000000000000000 +0 +SECTION +LOCAL +DEFAULT +4.* - +5: 0000000000000000 +0 +NOTYPE +LOCAL +DEFAULT +4 "@D" diff --git a/gas/testsuite/gas/ia64/alias.s b/gas/testsuite/gas/ia64/alias.s deleted file mode 100644 index 9ac18014fa6..00000000000 --- a/gas/testsuite/gas/ia64/alias.s +++ /dev/null @@ -1,11 +0,0 @@ - .section .foo,"aw","progbits" - .secalias .foo,"1234" - .secalias .foo,"1234" - .alias foo, "\"\80\84\"" - .alias foo, "\"\80\84\"" -foo: - stringz "\"\80\84\"" - .secalias .foo,"1234" - .secalias .foo,"1234" - .alias foo, "\"\80\84\"" - .alias foo, "\"\80\84\"" diff --git a/gas/testsuite/gas/ia64/align.d b/gas/testsuite/gas/ia64/align.d deleted file mode 100644 index ef4f61e42d5..00000000000 --- a/gas/testsuite/gas/ia64/align.d +++ /dev/null @@ -1,7 +0,0 @@ -#objdump: -s -j .data -#name: ia64 align - -.*: +file format .* - -Contents of section .data: - 0000 ff[ ]+.[ ]+ diff --git a/gas/testsuite/gas/ia64/align.s b/gas/testsuite/gas/ia64/align.s deleted file mode 100644 index 310ec61e88a..00000000000 --- a/gas/testsuite/gas/ia64/align.s +++ /dev/null @@ -1,3 +0,0 @@ - .data - .align 256 - .byte -1 diff --git a/gas/testsuite/gas/ia64/alloc.l b/gas/testsuite/gas/ia64/alloc.l deleted file mode 100644 index 42a866a1830..00000000000 --- a/gas/testsuite/gas/ia64/alloc.l +++ /dev/null @@ -1,11 +0,0 @@ -# Currently in the error messages the operand numbers for the constants -# aren't correct, which is why the patterns only check for ranges. -.*: Assembler messages: -.*:7: Error: Operand [345] of .alloc. should be .* -.*:8: Error: Operand [345] of .alloc. should be .* -.*:9: Error: Operand [345] of .alloc. should be .* -.*:10: Error: Operand [56] of .alloc. should be .* -.*:11: Error: Operand [234] of .alloc. should be .* -.*:12: Error: Operand [234] of .alloc. should be .* -.*:13: Error: Operand [234] of .alloc. should be .* -.*:14: Error: Operand [45] of .alloc. should be .* diff --git a/gas/testsuite/gas/ia64/alloc.s b/gas/testsuite/gas/ia64/alloc.s deleted file mode 100644 index 0fcdb848b35..00000000000 --- a/gas/testsuite/gas/ia64/alloc.s +++ /dev/null @@ -1,14 +0,0 @@ -// Make sure error messages on 'alloc' don't needlessly refer to operand 1 -// (which gets parsed late) when only one of the other operands is wrong. - - .text - -alloc: - alloc r2 =3D ar.pfs, x, 0, 0, 0 - alloc r2 =3D ar.pfs, 0, x, 0, 0 - alloc r2 =3D ar.pfs, 0, 0, x, 0 - alloc r2 =3D ar.pfs, 0, 0, 0, x - alloc r3 =3D x, 0, 0, 0 - alloc r3 =3D 0, x, 0, 0 - alloc r3 =3D 0, 0, x, 0 - alloc r3 =3D 0, 0, 0, x diff --git a/gas/testsuite/gas/ia64/bundling.d b/gas/testsuite/gas/ia64/bun= dling.d deleted file mode 100644 index 2ddece1f03f..00000000000 --- a/gas/testsuite/gas/ia64/bundling.d +++ /dev/null @@ -1,14 +0,0 @@ -# objdump: -d -# name: ia64 explicit bundling - -.*: +file format .* - -Disassembly of section \.text: - -0+0 <_start>: -[[:space:]]*[[:xdigit:]]*:[[:space:][:xdigit:]]+\[MII] nop\.m 0x0 -[[:space:]]*[[:xdigit:]]*:[[:space:][:xdigit:]]+nop\.i 0x0;; -[[:space:]]*[[:xdigit:]]*:[[:space:][:xdigit:]]+mov\.i r31=3Dar\.lc;; -[[:space:]]*[[:xdigit:]]*:[[:space:][:xdigit:]]+\[..B] nop\.. 0x0 -[[:space:]]*[[:xdigit:]]*:[[:space:][:xdigit:]]+nop\.. 0x0 -[[:space:]]*[[:xdigit:]]*:[[:space:][:xdigit:]]+br\.ret\.sptk\.few b0;; diff --git a/gas/testsuite/gas/ia64/bundling.s b/gas/testsuite/gas/ia64/bun= dling.s deleted file mode 100644 index 23a987d47f0..00000000000 --- a/gas/testsuite/gas/ia64/bundling.s +++ /dev/null @@ -1,15 +0,0 @@ -.explicit -.proc _start -_start: - .prologue -{.mii - nop.m 0 - ;; - .save ar.lc, r31 - mov r31 =3D ar.lc -} ;; - .body -{.mfb - br.ret.sptk rp -} ;; -.endp _start diff --git a/gas/testsuite/gas/ia64/dependency-1.d b/gas/testsuite/gas/ia64= /dependency-1.d deleted file mode 100644 index 5fee46007c4..00000000000 --- a/gas/testsuite/gas/ia64/dependency-1.d +++ /dev/null @@ -1,17 +0,0 @@ -# as: -xexplicit -# objdump: -d -# name: IA64 read-before-write dependency - -# Note - this test is based on a bug reported here: -# http://sources.redhat.com/ml/bug-gnu-utils/2003-03/msg00270.html -# With follows up on the binutils mailing list here: -# http://sources.redhat.com/ml/binutils/2003-04/msg00162.html - -.*: +file format .* - -Disassembly of section \.text: - -0+000 : - 0:.*0b 40 00 40 10 18.*\[MMI\].*ldfs f8=3D\[r32\];; - 6:.*00 40 84 30 33 00.*stfd \[r33\]=3Df8 - c:.*00 00 04 00.*nop\.i 0x0;; diff --git a/gas/testsuite/gas/ia64/dependency-1.s b/gas/testsuite/gas/ia64= /dependency-1.s deleted file mode 100644 index 7ffa0817eff..00000000000 --- a/gas/testsuite/gas/ia64/dependency-1.s +++ /dev/null @@ -1,7 +0,0 @@ - .text - .auto - .align 32 -=20 -foo: - ldfs f8=3D[r32] - stfd [r33]=3Df8 diff --git a/gas/testsuite/gas/ia64/dv-branch.d b/gas/testsuite/gas/ia64/dv= -branch.d deleted file mode 100644 index e8fa52e8ee9..00000000000 --- a/gas/testsuite/gas/ia64/dv-branch.d +++ /dev/null @@ -1,15 +0,0 @@ -# as: -xexplicit -# objdump: -d -# name ia64 dv-branch - -.*: +file format .* - -Disassembly of section \.text: - -0+000 <\.text>: - 0: d0 08 00 10 18 90 \[MIB\] \(p06\) ld8 r1=3D\[r8\] - 6: 61 10 04 80 03 03 \(p06\) mov b6=3Dr2 - c: 68 00 80 10 \(p06\) br\.call\.sptk\.many b0=3Db6 - 10: 11 08 00 3c 00 21 \[MIB\] mov r1=3Dr30 - 16: 00 00 00 02 00 03 nop\.i 0x0 - 1c: f0 ff ff 48 \(p06\) br\.cond\.sptk\.few 0x0;; diff --git a/gas/testsuite/gas/ia64/dv-branch.s b/gas/testsuite/gas/ia64/dv= -branch.s deleted file mode 100644 index 09c5141764f..00000000000 --- a/gas/testsuite/gas/ia64/dv-branch.s +++ /dev/null @@ -1,16 +0,0 @@ -// -// Verify DV detection on branch variations -//=09=09=09 -.text - .explicit - // example from rth -3:=09=09 - { .mib -(p6) ld8 gp =3D [ret0] -(p6) mov b6 =3D r2 -(p6) br.call.sptk.many b0 =3D b6 // if taken, clears b6/r2 usage - } - { .mib - mov gp =3D r30 -(p6) br.sptk.few 3b - }=20=20 diff --git a/gas/testsuite/gas/ia64/dv-entry-err.l b/gas/testsuite/gas/ia64= /dv-entry-err.l deleted file mode 100644 index f7b1f728047..00000000000 --- a/gas/testsuite/gas/ia64/dv-entry-err.l +++ /dev/null @@ -1,3 +0,0 @@ -.*: Assembler messages: -.*:14: Warning: Use of 'mov' .* WAW dependency 'GR%, % in 1 - 127' \(impli= edf\) when entry is at label 'L', specific resource number is 5 -.*:13: Warning: This is the location of the conflicting usage diff --git a/gas/testsuite/gas/ia64/dv-entry-err.s b/gas/testsuite/gas/ia64= /dv-entry-err.s deleted file mode 100644 index 7cd5b41bba4..00000000000 --- a/gas/testsuite/gas/ia64/dv-entry-err.s +++ /dev/null @@ -1,15 +0,0 @@ -// -// Verify DV detection on multiple paths -//=09=09=09 -.text - .explicit -// WAW on r4 is avoided on both paths -// WAW on r5 is avoided on path 0 (from top) but not path 1 (from L) - cmp.eq p1, p2 =3D r1, r2 - cmp.eq p3, p4 =3D r3, r0;; -(p1) mov r4 =3D 2 -L:=09 -(p2) mov r4 =3D 5 -(p3) mov r5 =3D r7 -(p4) mov r5 =3D r8 - diff --git a/gas/testsuite/gas/ia64/dv-imply.d b/gas/testsuite/gas/ia64/dv-= imply.d deleted file mode 100644 index 30ae379672f..00000000000 --- a/gas/testsuite/gas/ia64/dv-imply.d +++ /dev/null @@ -1,45 +0,0 @@ -# as: -xexplicit -mtune=3Ditanium1 -# objdump: -d -# name ia64 dv-mutex - -.*: +file format .* - -Disassembly of section \.text: - -0+000 : - 0: 3c 20 08 00 00 24 \[MFB\] \(p01\) mov r4=3D2 - 6: 00 00 00 02 00 01 nop\.f 0x0 - c: c0 00 00 40 \(p02\) br\.cond\.sptk\.few c0 - 10: 1d 20 1c 00 00 24 \[MFB\] mov r4=3D7 - 16: 00 00 00 02 00 00 nop\.f 0x0 - 1c: 00 00 20 00 rfi;; - 20: 1c 20 08 00 00 24 \[MFB\] mov r4=3D2 - 26: 00 00 00 02 00 01 nop\.f 0x0 - 2c: a0 00 00 40 \(p02\) br\.cond\.sptk\.few c0 - 30: 3d 20 1c 00 00 24 \[MFB\] \(p01\) mov r4=3D7 - 36: 00 00 00 02 00 00 nop\.f 0x0 - 3c: 00 00 20 00 rfi;; - 40: 6a 08 06 04 02 78 \[MMI\] \(p03\) cmp\.eq\.unc p1,p2=3Dr1,r2;; - 46: 40 10 00 00 48 00 \(p01\) mov r4=3D2 - 4c: 00 00 04 00 nop\.i 0x0 - 50: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 56: 00 00 00 02 80 01 nop\.f 0x0 - 5c: 70 00 00 40 \(p03\) br\.cond\.sptk\.few c0 - 60: 1d 20 1c 00 00 24 \[MFB\] mov r4=3D7 - 66: 00 00 00 02 00 00 nop\.f 0x0 - 6c: 00 00 20 00 rfi;; - 70: 62 08 06 04 02 38 \[MII\] \(p03\) cmp\.eq\.unc p1,p2=3Dr1,r2 - 76: 30 28 18 88 e8 80 cmp\.eq\.or p3,p4=3Dr5,r6;; - 7c: 20 00 00 90 \(p01\) mov r4=3D2 - 80: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 86: 00 00 00 02 80 01 nop\.f 0x0 - 8c: 40 00 00 40 \(p03\) br\.cond\.sptk\.few c0 - 90: 1d 20 1c 00 00 24 \[MFB\] mov r4=3D7 - 96: 00 00 00 02 00 00 nop\.f 0x0 - 9c: 00 00 20 00 rfi;; - a0: 10 08 16 0c 42 70 \[MIB\] cmp\.ne\.and p1,p2=3Dr5,r6 - a6: 40 10 00 00 c8 01 \(p01\) mov r4=3D2 - ac: 20 00 00 40 \(p03\) br\.cond\.sptk\.few c0 - b0: 1d 20 1c 00 00 24 \[MFB\] mov r4=3D7 - b6: 00 00 00 02 00 00 nop\.f 0x0 - bc: 00 00 20 00 rfi;; diff --git a/gas/testsuite/gas/ia64/dv-imply.s b/gas/testsuite/gas/ia64/dv-= imply.s deleted file mode 100644 index 52561780438..00000000000 --- a/gas/testsuite/gas/ia64/dv-imply.s +++ /dev/null @@ -1,44 +0,0 @@ -//=09 -// Test various implies relations=09 -//=09 -.text -// User-supplied hint=09 - .pred.rel.imply p1, p2 -(p1) mov r4 =3D 2 -(p2) br.cond.sptk L - mov r4 =3D 7 - rfi=09 -=09 -// Symmetric to previous example - .pred.rel.imply p1, p2 - mov r4 =3D 2 -(p2) br.cond.sptk L -(p1) mov r4 =3D 7=09 - rfi - -// Verify that the implies relationship caused by the unconditional compar= e=20 -// prevents RAW on r4.=20=20 -(p3) cmp.eq.unc p1, p2 =3D r1, r2;; // p1,p2 imply p3 -(p1) mov r4 =3D 2 -(p3) br.cond.sptk L=09 - mov r4 =3D 7 - rfi -=09 -// An instance of cmp.rel.or should not affect an implies relation. -(p3) cmp.eq.unc p1, p2 =3D r1, r2 // p1,p2 imply p3 - cmp.eq.or p3, p4 =3D r5, r6;; // doesn't affect implies rel -(p1) mov r4 =3D 2 -(p3) br.cond.sptk L=09 - mov r4 =3D 7 - rfi -=09 -// An instance of cmp.rel.and only affects imply targets - .pred.rel.imply p1,p3 - cmp.ne.and p1, p2 =3D r5, r6 // doesn't affect imply source -(p1) mov r4 =3D 2 -(p3) br.cond.sptk L=09 - mov r4 =3D 7 - rfi -=09 -// FIXME -- add tests for and.orcm and or.andcm=09 -L:=09 diff --git a/gas/testsuite/gas/ia64/dv-mutex-err.l b/gas/testsuite/gas/ia64= /dv-mutex-err.l deleted file mode 100644 index 17960be1255..00000000000 --- a/gas/testsuite/gas/ia64/dv-mutex-err.l +++ /dev/null @@ -1,13 +0,0 @@ -.*: Assembler messages: -.*:9: Warning: Use of 'ld8' .* RAW dependency 'GR%, % in 1 - 127' \(implie= df\), specific resource number is 26 -.*:9: Warning: Only the first path encountering the conflict is reported -.*:8: Warning: This is the location of the conflicting usage -.*:14: Warning: Use of 'mov' may violate WAW dependency 'GR%, % in 1 - 127= ' \(impliedf\), specific resource number is 4 -.*:14: Warning: Only the first path encountering the conflict is reported -.*:13: Warning: This is the location of the conflicting usage -.*:20: Warning: Use of 'mov' may violate WAW dependency 'GR%, % in 1 - 127= ' \(impliedf\), specific resource number is 4 -.*:19: Warning: This is the location of the conflicting usage -.*:26: Warning: Use of 'mov' may violate WAW dependency 'GR%, % in 1 - 127= ' \(impliedf\), specific resource number is 4 -.*:25: Warning: This is the location of the conflicting usage -.*:32: Warning: Use of 'mov' may violate WAW dependency 'GR%, % in 1 - 127= ' \(impliedf\), specific resource number is 4 -.*:31: Warning: This is the location of the conflicting usage diff --git a/gas/testsuite/gas/ia64/dv-mutex-err.s b/gas/testsuite/gas/ia64= /dv-mutex-err.s deleted file mode 100644 index dc391990cb3..00000000000 --- a/gas/testsuite/gas/ia64/dv-mutex-err.s +++ /dev/null @@ -1,33 +0,0 @@ -//=09 -// Test mutex relation handling=09 -//=09 -.text - .explicit -start:=09 - cmp.eq p6, p0 =3D r29, r0 - add r26 =3D r26, r29 - ld8 r29 =3D [r26] - - .pred.rel.mutex p1, p2 - cmp.eq p0, p1 =3D r1, r2;; -(p1) mov r4 =3D 2 -(p2) mov r4 =3D 4 - rfi - - .pred.rel.mutex p1, p2 -(p3) cmp.eq p0, p1 =3D r1, r2;; -(p1) mov r4 =3D 2 -(p2) mov r4 =3D 4 - rfi - - .pred.rel.mutex p1, p2 - cmp.eq p2, p3 =3D r1, r2;; -(p1) mov r4 =3D 2 -(p2) mov r4 =3D 4 - rfi - - .pred.rel.mutex p1, p2 -(p3) cmp.eq p2, p3 =3D r1, r2;; -(p1) mov r4 =3D 2 -(p2) mov r4 =3D 4 - rfi diff --git a/gas/testsuite/gas/ia64/dv-mutex.d b/gas/testsuite/gas/ia64/dv-= mutex.d deleted file mode 100644 index 66ea0fd03d8..00000000000 --- a/gas/testsuite/gas/ia64/dv-mutex.d +++ /dev/null @@ -1,39 +0,0 @@ -# as: -xexplicit -mtune=3Ditanium1 -# objdump: -d -# name ia64 dv-mutex - -.*: +file format .* - -Disassembly of section \.text: - -0+000 : - 0: 20 20 08 00 00 a4 \[MII\] \(p01\) mov r4=3D2 - 6: 40 28 00 00 c8 81 \(p02\) mov r4=3D5 - c: 70 00 00 90 \(p03\) mov r4=3D7 - 10: 1d 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 16: 00 00 00 02 00 00 nop\.f 0x0 - 1c: 00 00 20 00 rfi;; - 20: 0a 08 04 04 02 78 \[MMI\] cmp\.eq p1,p2=3Dr1,r2;; - 26: 40 10 00 00 48 81 \(p01\) mov r4=3D2 - 2c: 40 00 00 90 \(p02\) mov r4=3D4 - 30: 1d 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 36: 00 00 00 02 00 00 nop\.f 0x0 - 3c: 00 00 20 00 rfi;; - 40: 6a 08 06 04 02 78 \[MMI\] \(p03\) cmp\.eq\.unc p1,p2=3Dr1,r2;; - 46: 40 10 00 00 48 81 \(p01\) mov r4=3D2 - 4c: 40 00 00 90 \(p02\) mov r4=3D4 - 50: 1d 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 56: 00 00 00 02 00 00 nop\.f 0x0 - 5c: 00 00 20 00 rfi;; - 60: 0a 08 04 04 02 78 \[MMI\] cmp\.eq p1,p2=3Dr1,r2;; - 66: 40 10 00 00 48 81 \(p01\) mov r4=3D2 - 6c: 40 00 00 90 \(p02\) mov r4=3D4 - 70: 1d 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 76: 00 00 00 02 00 00 nop\.f 0x0 - 7c: 00 00 20 00 rfi;; - 80: 6a 08 04 04 02 78 \[MMI\] \(p03\) cmp\.eq p1,p2=3Dr1,r2;; - 86: 40 10 00 00 48 81 \(p01\) mov r4=3D2 - 8c: 40 00 00 90 \(p02\) mov r4=3D4 - 90: 1d 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 96: 00 00 00 02 00 00 nop\.f 0x0 - 9c: 00 00 20 00 rfi;; diff --git a/gas/testsuite/gas/ia64/dv-mutex.s b/gas/testsuite/gas/ia64/dv-= mutex.s deleted file mode 100644 index c1841df9dfc..00000000000 --- a/gas/testsuite/gas/ia64/dv-mutex.s +++ /dev/null @@ -1,36 +0,0 @@ -//=09 -// Test mutex relation handling=09 -//=09 -.text -start:=09 -// user annotation=09 - .pred.rel.mutex p1, p2, p3 -(p1) mov r4 =3D 2 -(p2) mov r4 =3D 5 -(p3) mov r4 =3D 7 - rfi - -// non-predicated compares generate a mutex - cmp.eq p1, p2 =3D r1, r2;; -(p1) mov r4 =3D 2 -(p2) mov r4 =3D 4 - rfi - -// unconditional compares generate a mutex -(p3) cmp.eq.unc p1, p2 =3D r1, r2;; -(p1) mov r4 =3D 2 -(p2) mov r4 =3D 4 - rfi - -// non-predicated compares don't remove mutex - cmp.eq p1, p2 =3D r1, r2;; -(p1) mov r4 =3D 2 -(p2) mov r4 =3D 4 - rfi - -// predicated compares don't remove mutex -(p3) cmp.eq p1, p2 =3D r1, r2;; -(p1) mov r4 =3D 2 -(p2) mov r4 =3D 4 - rfi -L:=09 diff --git a/gas/testsuite/gas/ia64/dv-raw-err.l b/gas/testsuite/gas/ia64/d= v-raw-err.l deleted file mode 100644 index 036fa3e1edf..00000000000 --- a/gas/testsuite/gas/ia64/dv-raw-err.l +++ /dev/null @@ -1,309 +0,0 @@ -.*: Assembler messages: -.*:10: Warning: Use of 'mov\.m' violates RAW dependency 'AR\[BSP\]' \(impl= iedf\) -.*:9: Warning: This is the location of the conflicting usage -.*:10: Warning: Use of 'mov\.m' violates RAW dependency 'RSE' \(impliedf\) -.*:9: Warning: This is the location of the conflicting usage -.*:15: Warning: Use of 'mov\.m' violates RAW dependency 'AR\[BSPSTORE\]' \= (impliedf\) -.*:14: Warning: This is the location of the conflicting usage -.*:15: Warning: Use of 'mov\.m' violates RAW dependency 'RSE' \(impliedf\) -.*:14: Warning: This is the location of the conflicting usage -.*:20: Warning: Use of 'cmpxchg8\.acq' violates RAW dependency 'AR\[CCV\]'= \(impliedf\) -.*:19: Warning: This is the location of the conflicting usage -.*:25: Warning: Use of 'mov\.i' violates RAW dependency 'AR\[EC\]' \(impli= edf\) -.*:24: Warning: This is the location of the conflicting usage -.*:30: Warning: Use of 'fpcmp\.eq\.s0' violates RAW dependency 'AR\[FPSR\]= \.sf0\.controls' \(impliedf\) -.*:29: Warning: This is the location of the conflicting usage -.*:35: Warning: Use of 'fpcmp\.eq\.s1' violates RAW dependency 'AR\[FPSR\]= \.sf1\.controls' \(impliedf\) -.*:34: Warning: This is the location of the conflicting usage -.*:40: Warning: Use of 'fpcmp\.eq\.s2' violates RAW dependency 'AR\[FPSR\]= \.sf2\.controls' \(impliedf\) -.*:39: Warning: This is the location of the conflicting usage -.*:45: Warning: Use of 'fpcmp\.eq\.s3' violates RAW dependency 'AR\[FPSR\]= \.sf3\.controls' \(impliedf\) -.*:44: Warning: This is the location of the conflicting usage -.*:50: Warning: Use of 'fchkf\.s0' violates RAW dependency 'AR\[FPSR\]\.sf= 0\.flags' \(impliedf\) -.*:49: Warning: This is the location of the conflicting usage -.*:55: Warning: Use of 'fchkf\.s1' violates RAW dependency 'AR\[FPSR\]\.sf= 1\.flags' \(impliedf\) -.*:54: Warning: This is the location of the conflicting usage -.*:60: Warning: Use of 'fchkf\.s2' violates RAW dependency 'AR\[FPSR\]\.sf= 2\.flags' \(impliedf\) -.*:59: Warning: This is the location of the conflicting usage -.*:65: Warning: Use of 'fchkf\.s3' violates RAW dependency 'AR\[FPSR\]\.sf= 3\.flags' \(impliedf\) -.*:64: Warning: This is the location of the conflicting usage -.*:70: Warning: Use of 'fcmp\.eq\.s3' violates RAW dependency 'AR\[FPSR\]\= .sf3\.controls' \(impliedf\) -.*:69: Warning: This is the location of the conflicting usage -.*:70: Warning: Use of 'fcmp\.eq\.s3' violates RAW dependency 'AR\[FPSR\]\= .traps' \(impliedf\) -.*:69: Warning: This is the location of the conflicting usage -.*:70: Warning: Use of 'fcmp\.eq\.s3' violates RAW dependency 'AR\[FPSR\]\= .rv' \(impliedf\) -.*:69: Warning: This is the location of the conflicting usage -.*:70: Warning: Use of 'fcmp\.eq\.s3' violates WAW dependency 'AR\[FPSR\]\= .sf3\.flags' \(impliedf\) -.*:69: Warning: This is the location of the conflicting usage -.*:75: Warning: Use of 'mov\.m' violates RAW dependency 'AR\[ITC\]' \(impl= iedf\) -.*:74: Warning: This is the location of the conflicting usage -.*:80: Warning: Use of 'mov\.m' violates RAW dependency 'AR\[RUC\]' \(impl= iedf\) -.*:79: Warning: This is the location of the conflicting usage -.*:85: Warning: Use of 'br\.ia\.sptk' violates RAW dependency 'AR\[K%\], %= in[ ]*0[ ]+- 7' \(impliedf\), specific resource number is 1 -.*:84: Warning: This is the location of the conflicting usage -.*:90: Warning: Use of 'mov\.i' violates RAW dependency 'AR\[LC\]' \(impli= edf\) -.*:89: Warning: This is the location of the conflicting usage -.*:95: Warning: Use of 'epc' violates RAW dependency 'AR\[PFS\]' \(implied= f\) -.*:94: Warning: This is the location of the conflicting usage -.*:99: Warning: Use of 'mov\.m' violates RAW dependency 'AR\[RNAT\]' \(imp= liedf\) -.*:98: Warning: This is the location of the conflicting usage -.*:99: Warning: Use of 'mov\.m' violates RAW dependency 'RSE' \(impliedf\) -.*:98: Warning: This is the location of the conflicting usage -.*:104: Warning: Use of 'mov\.m' violates RAW dependency 'AR\[RSC\]' \(imp= liedf\) -.*:103: Warning: This is the location of the conflicting usage -.*:109: Warning: Use of 'ld8\.fill' may violate RAW dependency 'AR\[UNAT\]= \{%\}, % in[ ]*0[ ]+- 63' \(impliedf\) -.*:108: Warning: This is the location of the conflicting usage -.*:116: Warning: Use of 'mov' violates RAW dependency 'BR%, % in[ ]*0[ ]= +- 7' \(impliedf\), specific resource number is 0 -.*:115: Warning: This is the location of the conflicting usage -.*:121: Warning: Use of 'fadd' may violate RAW dependency 'CFM' \(impliedf= \) -.*:120: Warning: This is the location of the conflicting usage -.*:126: Warning: Use of 'mov' violates RAW dependency 'CR\[CMCV\]' \(data\) -.*:125: Warning: This is the location of the conflicting usage -.*:131: Warning: Use of 'ld8\.s' violates RAW dependency 'CR\[DCR\]' \(dat= a\) -.*:130: Warning: This is the location of the conflicting usage -.*:138: Warning: Use of 'thash' violates RAW dependency 'CR\[GPTA\]' \(dat= a\) -.*:137: Warning: This is the location of the conflicting usage -.*:144: Warning: Use of 'itc\.i' violates RAW dependency 'CR\[IFA\]' \(imp= lied\) -.*:143: Warning: This is the location of the conflicting usage -.*:149: Warning: Use of 'mov' violates RAW dependency 'CR\[IFS\]' \(data\) -.*:148: Warning: This is the location of the conflicting usage -.*:154: Warning: Use of 'mov' violates RAW dependency 'CR\[IHA\]' \(data\) -.*:153: Warning: This is the location of the conflicting usage -.*:159: Warning: Use of 'mov' violates RAW dependency 'CR\[IIB%\], % in[ = ]*0[ ]+- 1' \(data\), specific resource number is 26 -.*:158: Warning: This is the location of the conflicting usage -.*:163: Warning: Use of 'mov' violates RAW dependency 'CR\[IIB%\], % in[ = ]*0[ ]+- 1' \(data\), specific resource number is 27 -.*:162: Warning: This is the location of the conflicting usage -.*:168: Warning: Use of 'mov' violates RAW dependency 'CR\[IIM\]' \(data\) -.*:167: Warning: This is the location of the conflicting usage -.*:173: Warning: Use of 'rfi' violates RAW dependency 'CR\[IIP\]' \(implie= d\) -.*:172: Warning: This is the location of the conflicting usage -.*:178: Warning: Use of 'mov' violates RAW dependency 'CR\[IIPA\]' \(data\) -.*:177: Warning: This is the location of the conflicting usage -.*:183: Warning: Use of 'rfi' violates RAW dependency 'CR\[IPSR\]' \(impli= ed\) -.*:182: Warning: This is the location of the conflicting usage -.*:188: Warning: Use of 'mov' violates RAW dependency 'CR\[IRR%\], % in[ = ]*0[ ]+- 3' \(data\), specific resource number is 68 -.*:187: Warning: This is the location of the conflicting usage -.*:193: Warning: Use of 'mov' violates RAW dependency 'CR\[ISR\]' \(data\) -.*:192: Warning: This is the location of the conflicting usage -.*:198: Warning: Use of 'itc\.d' violates RAW dependency 'CR\[ITIR\]' \(im= plied\) -.*:197: Warning: This is the location of the conflicting usage -.*:203: Warning: Use of 'mov' violates RAW dependency 'CR\[ITM\]' \(data\) -.*:202: Warning: This is the location of the conflicting usage -.*:208: Warning: Use of 'mov' violates RAW dependency 'CR\[ITV\]' \(data\) -.*:207: Warning: This is the location of the conflicting usage -.*:215: Warning: Use of 'mov' violates RAW dependency 'CR\[IVA\]' \(instr\) -.*:214: Warning: This is the location of the conflicting usage -.*:220: Warning: Use of 'mov' violates RAW dependency 'CR\[LID\]' \(other\) -.*:219: Warning: This is the location of the conflicting usage -.*:226: Warning: Use of 'mov' violates RAW dependency 'CR\[LRR%\], % in[ = ]*0[ ]+- 1' \(data\), specific resource number is 80 -.*:225: Warning: This is the location of the conflicting usage -.*:231: Warning: Use of 'mov' violates RAW dependency 'CR\[PMV\]' \(data\) -.*:230: Warning: This is the location of the conflicting usage -.*:236: Warning: Use of 'thash' violates RAW dependency 'CR\[PTA\]' \(data= \) -.*:235: Warning: This is the location of the conflicting usage -.*:241: Warning: Use of 'mov' violates RAW dependency 'CR\[TPR\]' \(data\) -.*:240: Warning: This is the location of the conflicting usage -.*:245: Warning: Use of 'mov' violates RAW dependency 'CR\[TPR\]' \(other\) -.*:244: Warning: This is the location of the conflicting usage -.*:251: Warning: Use of 'mov' may violate RAW dependency 'DBR\#' \(implied= f\) -.*:250: Warning: This is the location of the conflicting usage -.*:255: Warning: Use of 'probe\.r' may violate RAW dependency 'DBR\#' \(da= ta\) -.*:254: Warning: This is the location of the conflicting usage -.*:261: Warning: Use of 'fc' violates RAW dependency 'DTC' \(data\) -.*:260: Warning: This is the location of the conflicting usage -.*:265: Warning: Use of 'ptc\.e' violates RAW dependency 'DTC' \(impliedf\) -.*:264: Warning: This is the location of the conflicting usage -.*:265: Warning: Use of 'ptc\.e' violates WAW dependency 'DTC' \(impliedf\) -.*:264: Warning: This is the location of the conflicting usage -.*:265: Warning: Use of 'ptc\.e' violates WAW dependency 'ITC' \(impliedf\) -.*:264: Warning: This is the location of the conflicting usage -.*:276: Warning: Use of 'tak' violates RAW dependency 'DTC' \(data\) -.*:275: Warning: This is the location of the conflicting usage -.*:276: Warning: Use of 'tak' violates RAW dependency 'DTR' \(data\) -.*:275: Warning: This is the location of the conflicting usage -.*:280: Warning: Use of 'tpa' violates RAW dependency 'DTC' \(data\) -.*:279: Warning: This is the location of the conflicting usage -.*:280: Warning: Use of 'tpa' violates RAW dependency 'DTR' \(data\) -.*:279: Warning: This is the location of the conflicting usage -.*:289: Warning: Use of 'mov' violates RAW dependency 'FR%, % in[ ]*2[ ]= +- 127' \(impliedf\), specific resource number is 4 -.*:288: Warning: This is the location of the conflicting usage -.*:297: Warning: Use of 'mov' violates RAW dependency 'GR%, % in[ ]*1[ ]= +- 127' \(impliedf\), specific resource number is 3 -.*:296: Warning: This is the location of the conflicting usage -.*:302: Warning: Use of 'mov' may violate RAW dependency 'IBR\#' \(implied= f\) -.*:301: Warning: This is the location of the conflicting usage -.*:307: Warning: Use of 'mov' violates RAW dependency 'InService\*' \(data= \) -.*:306: Warning: This is the location of the conflicting usage -.*:307: Warning: Use of 'mov' violates WAW dependency 'InService\*' \(othe= r\) -.*:306: Warning: This is the location of the conflicting usage -.*:311: Warning: Use of 'mov' violates RAW dependency 'InService\*' \(impl= iedf\) -.*:310: Warning: This is the location of the conflicting usage -.*:311: Warning: Use of 'mov' violates WAW dependency 'CR\[IRR%\], % in[ = ]*0[ ]+- 3' \(impliedf\), specific resource number is 71 -.*:310: Warning: This is the location of the conflicting usage -.*:311: Warning: Use of 'mov' violates WAW dependency 'CR\[IRR%\], % in[ = ]*0[ ]+- 3' \(impliedf\), specific resource number is 70 -.*:310: Warning: This is the location of the conflicting usage -.*:311: Warning: Use of 'mov' violates WAW dependency 'CR\[IRR%\], % in[ = ]*0[ ]+- 3' \(impliedf\), specific resource number is 69 -.*:310: Warning: This is the location of the conflicting usage -.*:311: Warning: Use of 'mov' violates WAW dependency 'CR\[IRR%\], % in[ = ]*0[ ]+- 3' \(impliedf\), specific resource number is 68 -.*:310: Warning: This is the location of the conflicting usage -.*:311: Warning: Use of 'mov' violates WAW dependency 'InService\*' \(othe= r\) -.*:310: Warning: This is the location of the conflicting usage -.*:313: Warning: Use of 'mov' violates WAW dependency 'InService\*' \(othe= r\) -.*:311: Warning: This is the location of the conflicting usage -.*:313: Warning: Use of 'mov' violates WAW dependency 'InService\*' \(othe= r\) -.*:310: Warning: This is the location of the conflicting usage -.*:314: Warning: Use of 'mov' violates WAW dependency 'InService\*' \(othe= r\) -.*:311: Warning: This is the location of the conflicting usage -.*:314: Warning: Use of 'mov' violates WAW dependency 'InService\*' \(othe= r\) -.*:310: Warning: This is the location of the conflicting usage -.*:314: Warning: Use of 'mov' violates RAW dependency 'InService\*' \(impl= iedf\) -.*:313: Warning: This is the location of the conflicting usage -.*:314: Warning: Use of 'mov' violates WAW dependency 'CR\[EOI\]' \(other\) -.*:313: Warning: This is the location of the conflicting usage -.*:314: Warning: Use of 'mov' violates WAW dependency 'InService\*' \(othe= r\) -.*:313: Warning: This is the location of the conflicting usage -.*:319: Warning: Use of 'epc' violates RAW dependency 'ITC' \(instr\) -.*:318: Warning: This is the location of the conflicting usage -.*:328: Warning: Use of 'epc' violates RAW dependency 'ITC' \(instr\) -.*:327: Warning: This is the location of the conflicting usage -.*:328: Warning: Use of 'epc' violates RAW dependency 'ITR' \(instr\) -.*:327: Warning: This is the location of the conflicting usage -.*:335: Warning: Use of 'probe\.r' may violate RAW dependency 'PKR\#' \(da= ta\) -.*:334: Warning: This is the location of the conflicting usage -.*:339: Warning: Use of 'mov' may violate RAW dependency 'PKR\#' \(data\) -.*:338: Warning: This is the location of the conflicting usage -.*:339: Warning: Use of 'mov' may violate RAW dependency 'PKR\#' \(implied= f\) -.*:338: Warning: This is the location of the conflicting usage -.*:345: Warning: Use of 'mov' may violate RAW dependency 'PMC\#' \(implied= f\) -.*:344: Warning: This is the location of the conflicting usage -.*:349: Warning: Use of 'mov' may violate RAW dependency 'PMC\#' \(other\) -.*:348: Warning: This is the location of the conflicting usage -.*:355: Warning: Use of 'mov' may violate RAW dependency 'PMD\#' \(implied= f\) -.*:354: Warning: This is the location of the conflicting usage -.*:360: Warning: Use of 'add' may violate RAW dependency 'PR%, % in[ ]*1[= ]+- 15' \(impliedf\), specific resource number is 1 -.*:359: Warning: This is the location of the conflicting usage -.*:363: Warning: Use of 'add' may violate RAW dependency 'PR%, % in[ ]*1[= ]+- 15' \(impliedf\), specific resource number is 2 -.*:362: Warning: This is the location of the conflicting usage -.*:366: Warning: Use of 'br\.cond\.sptk' may violate RAW dependency 'PR%, = % in[ ]*1[ ]+- 15' \(impliedf\), specific resource number is 5 -.*:365: Warning: This is the location of the conflicting usage -.*:374: Warning: Use of 'add' may violate RAW dependency 'CFM' \(impliedf\) -.*:373: Warning: This is the location of the conflicting usage -.*:374: Warning: Use of 'add' may violate RAW dependency 'PR63' \(impliedf= \) -.*:373: Warning: This is the location of the conflicting usage -.*:377: Warning: Use of 'add' may violate RAW dependency 'PR63' \(impliedf= \) -.*:376: Warning: This is the location of the conflicting usage -.*:385: Warning: Use of 'ld8' violates RAW dependency 'PSR\.ac' \(implied\) -.*:384: Warning: This is the location of the conflicting usage -.*:390: Warning: Use of 'ld8' violates RAW dependency 'PSR\.be' \(implied\) -.*:389: Warning: This is the location of the conflicting usage -.*:403: Warning: Use of 'st8' violates RAW dependency 'PSR\.cpl' \(implied= \) -.*:402: Warning: This is the location of the conflicting usage -.*:406: Warning: Use of 'mov\.m' violates RAW dependency 'PSR\.cpl' \(impl= ied\) -.*:405: Warning: This is the location of the conflicting usage -.*:409: Warning: Use of 'mov\.m' violates RAW dependency 'PSR\.cpl' \(impl= ied\) -.*:408: Warning: This is the location of the conflicting usage -.*:412: Warning: Use of 'mov\.m' violates RAW dependency 'PSR\.cpl' \(impl= ied\) -.*:411: Warning: This is the location of the conflicting usage -.*:415: Warning: Use of 'mov\.m' violates RAW dependency 'PSR\.cpl' \(impl= ied\) -.*:414: Warning: This is the location of the conflicting usage -.*:418: Warning: Use of 'mov\.m' violates RAW dependency 'PSR\.cpl' \(impl= ied\) -.*:417: Warning: This is the location of the conflicting usage -.*:421: Warning: Use of 'mov\.m' violates RAW dependency 'PSR\.cpl' \(impl= ied\) -.*:420: Warning: This is the location of the conflicting usage -.*:424: Warning: Use of 'mov' violates RAW dependency 'PSR\.cpl' \(implied= \) -.*:423: Warning: This is the location of the conflicting usage -.*:433: Warning: Use of 'mov' violates RAW dependency 'PSR\.cpl' \(implied= \) -.*:432: Warning: This is the location of the conflicting usage -.*:436: Warning: Use of 'mov' violates RAW dependency 'PSR\.cpl' \(implied= \) -.*:435: Warning: This is the location of the conflicting usage -.*:442: Warning: Use of 'ld8' violates RAW dependency 'PSR\.ac' \(data\) -.*:441: Warning: This is the location of the conflicting usage -.*:442: Warning: Use of 'ld8' violates RAW dependency 'PSR\.be' \(data\) -.*:441: Warning: This is the location of the conflicting usage -.*:442: Warning: Use of 'ld8' violates RAW dependency 'PSR\.db' \(data\) -.*:441: Warning: This is the location of the conflicting usage -.*:442: Warning: Use of 'ld8' violates RAW dependency 'PSR\.dt' \(data\) -.*:441: Warning: This is the location of the conflicting usage -.*:442: Warning: Use of 'ld8' violates RAW dependency 'PSR\.pk' \(data\) -.*:441: Warning: This is the location of the conflicting usage -.*:450: Warning: Use of 'mov' violates RAW dependency 'PSR\.dfh' \(data\) -.*:449: Warning: This is the location of the conflicting usage -.*:450: Warning: Use of 'mov' violates WAW dependency 'PSR\.mfh' \(implied= f\) -.*:449: Warning: This is the location of the conflicting usage -.*:456: Warning: Use of 'mov' violates RAW dependency 'PSR\.dfl' \(data\) -.*:455: Warning: This is the location of the conflicting usage -.*:456: Warning: Use of 'mov' violates WAW dependency 'PSR\.mfl' \(implied= f\) -.*:455: Warning: This is the location of the conflicting usage -.*:462: Warning: Use of 'mov' violates RAW dependency 'PSR\.di' \(impliedf= \) -.*:461: Warning: This is the location of the conflicting usage -.*:467: Warning: Use of 'ld8' violates RAW dependency 'PSR\.dt' \(data\) -.*:466: Warning: This is the location of the conflicting usage -.*:473: Warning: Use of 'mov' violates RAW dependency 'PSR\.i' \(impliedf\) -.*:472: Warning: This is the location of the conflicting usage -.*:479: Warning: Use of 'mov' violates RAW dependency 'PSR\.ic' \(impliedf= \) -.*:478: Warning: This is the location of the conflicting usage -.*:483: Warning: Use of 'mov' violates RAW dependency 'PSR\.ic' \(data\) -.*:482: Warning: This is the location of the conflicting usage -.*:496: Warning: Use of 'br\.ret\.sptk' violates RAW dependency 'PSR\.lp' = \(data\) -.*:495: Warning: This is the location of the conflicting usage -.*:496: Warning: Use of 'br\.ret\.sptk' violates RAW dependency 'PSR\.tb' = \(data\) -.*:495: Warning: This is the location of the conflicting usage -.*:502: Warning: Use of 'mov' violates RAW dependency 'PSR\.mfh' \(implied= f\) -.*:501: Warning: This is the location of the conflicting usage -.*:507: Warning: Use of 'mov' violates RAW dependency 'PSR\.mfl' \(implied= f\) -.*:506: Warning: This is the location of the conflicting usage -.*:512: Warning: Use of 'ld8' violates RAW dependency 'PSR\.pk' \(data\) -.*:511: Warning: This is the location of the conflicting usage -.*:515: Warning: Use of 'mov' violates RAW dependency 'PSR\.pk' \(impliedf= \) -.*:514: Warning: This is the location of the conflicting usage -.*:520: Warning: Use of 'mov' violates RAW dependency 'PSR\.pp' \(impliedf= \) -.*:519: Warning: This is the location of the conflicting usage -.*:526: Warning: Use of 'flushrs' violates RAW dependency 'PSR\.rt' \(data= \) -.*:525: Warning: This is the location of the conflicting usage -.*:532: Warning: Use of 'mov\.m' violates RAW dependency 'PSR\.si' \(data\) -.*:531: Warning: This is the location of the conflicting usage -.*:535: Warning: Use of 'mov\.m' violates RAW dependency 'PSR\.si' \(data\) -.*:531: Warning: This is the location of the conflicting usage -.*:535: Warning: Use of 'mov\.m' violates RAW dependency 'PSR\.si' \(data\) -.*:534: Warning: This is the location of the conflicting usage -.*:543: Warning: Use of 'mov' violates RAW dependency 'PSR\.sp' \(data\) -.*:542: Warning: This is the location of the conflicting usage -.*:546: Warning: Use of 'rum' violates RAW dependency 'PSR\.sp' \(data\) -.*:542: Warning: This is the location of the conflicting usage -.*:546: Warning: Use of 'rum' violates RAW dependency 'PSR\.sp' \(data\) -.*:545: Warning: This is the location of the conflicting usage -.*:555: Warning: Use of 'chk\.s' violates RAW dependency 'PSR\.tb' \(data\) -.*:554: Warning: This is the location of the conflicting usage -.*:560: Warning: Use of 'mov' violates RAW dependency 'PSR\.up' \(impliedf= \) -.*:559: Warning: This is the location of the conflicting usage -.*:566: Warning: Use of 'ld8' may violate RAW dependency 'RR\#' \(data\) -.*:565: Warning: This is the location of the conflicting usage -.*:569: Warning: Use of 'mov' may violate RAW dependency 'RR\#' \(impliedf= \) -.*:568: Warning: This is the location of the conflicting usage -.*:578: Warning: Use of 'addl' violates RAW dependency 'GR%, % in[ ]*1[ = ]+- 127' \(impliedf\), specific resource number is 2 -.*:577: Warning: This is the location of the conflicting usage -.*:582: Warning: Use of 'mov' violates RAW dependency 'GR%, % in[ ]*1[ ]= +- 127' \(impliedf\), specific resource number is 32 -.*:581: Warning: This is the location of the conflicting usage -.*:587: Warning: Use of 'add' may violate RAW dependency 'PR%, % in[ ]*16= [ ]+- 62' \(impliedf\), specific resource number is 21 -.*:586: Warning: This is the location of the conflicting usage -.*:590: Warning: Use of 'add' may violate RAW dependency 'PR%, % in[ ]*16= [ ]+- 62' \(impliedf\), specific resource number is 22 -.*:589: Warning: This is the location of the conflicting usage -.*:593: Warning: Use of 'add' may violate RAW dependency 'PR%, % in[ ]*16= [ ]+- 62' \(impliedf\), specific resource number is 23 -.*:592: Warning: This is the location of the conflicting usage -.*:596: Warning: Use of 'br\.cond\.sptk' may violate RAW dependency 'PR%, = % in[ ]*16[ ]+- 62' \(impliedf\), specific resource number is 25 -.*:595: Warning: This is the location of the conflicting usage -.*:604: Warning: Use of 'adds' violates RAW dependency 'GR%, % in[ ]*1[ = ]+- 127' \(impliedf\), specific resource number is 6 -.*:603: Warning: This is the location of the conflicting usage -.*:607: Warning: Use of 'adds' violates RAW dependency 'GR%, % in[ ]*1[ = ]+- 127' \(impliedf\), specific resource number is 6 -.*:606: Warning: This is the location of the conflicting usage -.*:610: Warning: Use of 'add' violates RAW dependency 'GR%, % in[ ]*1[ ]= +- 127' \(impliedf\), specific resource number is 6 -.*:609: Warning: This is the location of the conflicting usage -.*:613: Warning: Use of 'ld8' violates RAW dependency 'GR%, % in[ ]*1[ ]= +- 127' \(impliedf\), specific resource number is 6 -.*:612: Warning: This is the location of the conflicting usage -.*:613: Warning: Use of 'ld8' violates WAW dependency 'GR%, % in[ ]*1[ ]= +- 127' \(impliedf\), specific resource number is 6 -.*:612: Warning: This is the location of the conflicting usage -.*:616: Warning: Use of 'ldfd' violates RAW dependency 'GR%, % in[ ]*1[ = ]+- 127' \(impliedf\), specific resource number is 6 -.*:615: Warning: This is the location of the conflicting usage -.*:616: Warning: Use of 'ldfd' violates WAW dependency 'GR%, % in[ ]*1[ = ]+- 127' \(impliedf\), specific resource number is 6 -.*:615: Warning: This is the location of the conflicting usage -.*:624: Warning: Use of 'ld8' violates RAW dependency 'PSR\.vm' \(implied\) -.*:623: Warning: This is the location of the conflicting usage diff --git a/gas/testsuite/gas/ia64/dv-raw-err.s b/gas/testsuite/gas/ia64/d= v-raw-err.s deleted file mode 100644 index d671040515a..00000000000 --- a/gas/testsuite/gas/ia64/dv-raw-err.s +++ /dev/null @@ -1,625 +0,0 @@ -//=09 -// Detect RAW violations. Cases taken from DV tables. -// This test is by no means complete but tries to hit the things that are= =20 -// likely to be missed. -//=09 -.text - .explicit -// AR[BSP] - mov ar.bspstore =3D r0 - mov r1 =3D ar.bsp - ;; - -// AR[BSPSTORE]=09 - mov ar.bspstore =3D r2 - mov r3 =3D ar.bspstore - ;; -=09 -// AR[CCV] - mov ar.ccv =3D r4 - cmpxchg8.acq r5 =3D [r6],r7,ar.ccv - ;; -=09 -// AR[EC]=09 - br.wtop.sptk L - mov r8 =3D ar.ec - ;; - -// AR[FPSR].sf0.controls=20 - fsetc.s0 0x7f, 0x0f - fpcmp.eq.s0 f2 =3D f3, f4 - ;; - -// AR[FPSR].sf1.controls - fsetc.s1 0x7f, 0x0f - fpcmp.eq.s1 f2 =3D f3, f4 - ;; - -// AR[FPSR].sf2.controls - fsetc.s2 0x7f, 0x0f - fpcmp.eq.s2 f2 =3D f3, f4 - ;; - -// AR[FPSR].sf3.controls - fsetc.s3 0x7f, 0x0f - fpcmp.eq.s3 f2 =3D f3, f4 - ;; - -// AR[FPSR].sf0.flags - fpcmp.eq.s0 f2 =3D f3, f4 - fchkf.s0 L - ;; - -// AR[FPSR].sf1.flags - fpcmp.eq.s1 f2 =3D f3, f4 - fchkf.s1 L - ;; - -// AR[FPSR].sf2.flags - fpcmp.eq.s2 f2 =3D f3, f4 - fchkf.s2 L - ;; - -// AR[FPSR].sf3.flags - fpcmp.eq.s3 f2 =3D f3, f4 - fchkf.s3 L - ;; - -// AR[FPSR].traps/rv - mov ar.fpsr =3D r0 - fcmp.eq.s3 p1, p2 =3D f5, f6 - ;; - -// AR[ITC] - mov ar.itc =3D r1 - mov r2 =3D ar.itc - ;; - -// AR[RUC] - mov ar.ruc =3D r1 - mov r2 =3D ar.ruc - ;; - -// AR[K] - mov ar.k1 =3D r3 - br.ia.sptk b0 - ;; -=09 -// AR[LC] - br.cloop.sptk L - mov r4 =3D ar.lc - ;; -=09 -// AR[PFS] - mov ar.pfs =3D r5 - epc - -// AR[RNAT]=09 - mov ar.bspstore =3D r8 - mov r9 =3D ar.rnat=09 - ;; -=09 -// AR[RSC] - mov ar.rsc =3D r10 - mov r11 =3D ar.rnat - ;;=09 -=09 -// AR[UNAT]=09 - mov ar.unat =3D r12 - ld8.fill r13 =3D [r14] - ;; -=09 -// AR% - -// BR% - mov b0 =3D r0 - mov r2 =3D b0 - ;; -=09 -// CFM=09 - br.wtop.sptk L - fadd f2 =3D f1, f32 // read from rotating register region - ;; -=09 -// CR[CMCV] - mov cr.cmcv =3D r1 - mov r2 =3D cr.cmcv=09 - ;; - -// CR[DCR] - mov cr.dcr =3D r3 - ld8.s r4 =3D [r5] - ;; - -// CR[EOI] -=09 -// CR[GPTA] - mov cr.gpta =3D r6 - thash r7 =3D r8 - ;; - srlz.d - -// CR[IFA] - mov cr.ifa =3D r9 - itc.i r10 - ;; - -// CR[IFS] - mov cr.ifs =3D r11 - mov r12 =3D cr.ifs - ;; - -// CR[IHA] - mov cr.iha =3D r13 - mov r14 =3D cr.iha - ;; - -// CR[IIB%] - mov cr.iib0 =3D r15 - mov r16 =3D cr.iib0 - ;; - - mov cr.iib1 =3D r15 - mov r16 =3D cr.iib1 - ;; - -// CR[IIM] - mov cr.iim =3D r15 - mov r16 =3D cr.iim - ;; - -// CR[IIP]=20 - mov cr.iip =3D r17 - rfi - ;; - -// CR[IIPA] - mov cr.iipa =3D r19 - mov r20 =3D cr.iipa - ;; - -// CR[IPSR] - mov cr.ipsr =3D r21 - rfi - ;; - -// CR[IRR%] - mov r22 =3D cr.ivr - mov r23 =3D cr.irr0 - ;; -=09 -// CR[ISR] - mov cr.isr =3D r24 - mov r25 =3D cr.isr - ;;=09 -=09 -// CR[ITIR] - mov cr.itir =3D r26 - itc.d r27 - ;;=09 -=09 -// CR[ITM] - mov cr.itm =3D r28 - mov r29 =3D cr.itm - ;;=09 -=09 -// CR[ITV] - mov cr.itv =3D r0 - mov r1 =3D cr.itv - ;;=09 -=09 -// CR[IVR] (all writes are implicit in other resource usage) -=09 -// CR[IVA] - mov cr.iva =3D r0 - mov r1 =3D cr.iva - ;;=09 -=09 -// CR[LID] - mov cr.lid =3D r0 - mov r1 =3D cr.lid - ;;=09 - srlz.d -=09 -// CR[LRR%] - mov cr.lrr0 =3D r0 - mov r1 =3D cr.lrr0 - ;; -=09 -// CR[PMV] - mov cr.pmv =3D r0 - mov r1 =3D cr.pmv - ;; -=09 -// CR[PTA] - mov cr.pta =3D r0 - thash r1 =3D r2 - ;; -=09 -// CR[TPR] - mov cr.tpr =3D r0 - mov r1 =3D cr.ivr // data - ;; - srlz.d - mov cr.tpr =3D r2 - mov psr.l =3D r3 // other - ;; - srlz.d -=09 -// DBR#=20 - mov dbr[r0] =3D r1 - mov r2 =3D dbr[r3] - ;;=09 - srlz.d - mov dbr[r4] =3D r5 - probe.r r6 =3D r7, r8 - ;; - srlz.d -=09 -// DTC - ptc.e r0 - fc r1 - ;; - srlz.d - itr.i itr[r2] =3D r3 - ptc.e r4 - ;; -=09 -// DTC_LIMIT/ITC_LIMIT=20 - ptc.g r0, r1 // NOTE: GAS automatically emits stops after=20 - ptc.ga r2, r3 // ptc.g/ptc.ga, so this conflict is no=20=20=20=20=20 - ;; // longer possible in GAS-generated assembly - srlz.d - -// DTR - itr.d dtr[r0] =3D r1 - tak r2 =3D r3 - ;; - srlz.d - ptr.d r4, r5 - tpa r6 =3D r7 - ;; - srlz.d -=09 -// FR% - ldfs.c.clr f2 =3D [r1] - mov f3 =3D f2 // no DV here - ;; - mov f4 =3D f5 - mov f6 =3D f4 - ;; - -// GR% - ld8.c.clr r1 =3D [r1] // no DV here - mov r2 =3D r0=09=09 - ;; - mov r3 =3D r4 - mov r5 =3D r3 - ;; - -// IBR# - mov ibr[r0] =3D r1 - mov r2 =3D ibr[r3] - ;; - -// InService=09=09 - mov cr.eoi =3D r0 - mov r1 =3D cr.ivr - ;; - srlz.d - mov r2 =3D cr.ivr - mov r3 =3D cr.ivr // several DVs - ;; - mov cr.eoi =3D r4 - mov cr.eoi =3D r5 - ;; -=09 -// ITC=09=09 - ptc.e r0 - epc - ;; - srlz.i - ;; -=09 -// ITC_LIMIT (see DTC_LIMIT) -=09 -// ITR=09 - itr.i itr[r0] =3D r1 - epc - ;; - srlz.i - ;; -=09 -// PKR# - mov pkr[r0] =3D r1 - probe.r r2 =3D r3, r4 - ;; - srlz.d - mov pkr[r5] =3D r6 - mov r7 =3D pkr[r8] - ;; - srlz.d -=09 -// PMC# - mov pmc[r0] =3D r1 - mov r2 =3D pmc[r3] - ;; - srlz.d - mov pmc[r4] =3D r5 - mov r6 =3D pmd[r7] - ;; - srlz.d -=09 -// PMD# - mov pmd[r0] =3D r1 - mov r2 =3D pmd[r3] - ;; -=09 -// PR%, 1 - 15 - cmp.eq p1, p2 =3D r0, r1 // pr-writer/pr-reader-nobr-nomovpr -(p1) add r2 =3D r3, r4=09 - ;; - mov pr =3D r5, 0xffff // mov-to-pr-allreg/pr-reader-nobr-nomovpr -(p2) add r6 =3D r7, r8=09 - ;; - fcmp.eq p5, p6 =3D f2, f3 // pr-writer-fp/pr-reader-br -(p5) br.cond.sptk b0 - ;; - cmp.eq p7, p8 =3D r11, r12 -(p7) br.cond.sptk b1 // no DV here - ;; -=09 -// PR63 - br.wtop.sptk L -(p63) add r3 =3D r1, r2 - ;; - fcmp.eq p62, p63 =3D f2, f3 -(p63) add r3 =3D r4, r5=09 - ;; - cmp.eq p62, p63 =3D r6, r7 // no DV here -(p63) br.cond.sptk b0 - ;;=09 - -// PSR.ac - rum (1<<3) - ld8 r2 =3D [r1] - ;; - -// PSR.be - rum (1<<1) - ld8 r2 =3D [r1] - ;; -=09 -// PSR.bn - bsw.0 - mov r1 =3D r15 // no DV here, since gr < 16 - ;; - bsw.1 // GAS automatically emits a stop after bsw.n - mov r1 =3D r16 // so this conflict is avoided=20=20=20=20=20=20=20=20=20= =20=20=20=20=20=20 - ;; -=09 -// PSR.cpl - epc - st8 [r0] =3D r1 - ;; - epc - mov r2 =3D ar.itc - ;; - epc - mov ar.itc =3D r3 - ;; - epc - mov r2 =3D ar.ruc - ;; - epc - mov ar.ruc =3D r3 - ;; - epc - mov ar.rsc =3D r4 - ;; - epc - mov ar.k0 =3D r5 - ;; - epc - mov r6 =3D pmd[r7] - ;; - epc - mov ar.bsp =3D r8 // no DV here - ;; - epc - mov r9 =3D ar.bsp // no DV here - ;; - epc - mov cr.ifa =3D r10 // any mov-to/from-cr is a DV - ;; - epc - mov r11 =3D cr.eoi // any mov-to/from-cr is a DV - ;; - -// PSR.da (rfi is the only writer) -// PSR.db (also ac,be,dt,pk) - mov psr.l =3D r0 - ld8 r1 =3D [r2] - ;; - srlz.d - -// PSR.dd (rfi is the only writer) -=09 -// PSR.dfh - mov psr.l =3D r0 - mov f64 =3D f65 - ;; - srlz.d - -// PSR.dfl - mov psr.l =3D r0 - mov f3 =3D f4=09 - ;; - srlz.d -=09 -// PSR.di - rsm (1<<22) - mov r1 =3D psr - ;; - -// PSR.dt - rsm (1<<17) - ld8 r1 =3D [r1] - ;; -=09 -// PSR.ed (rfi is the only writer) -// PSR.i - ssm (1<<14) - mov r1 =3D psr - ;; -=09 -// PSR.ia (no DV semantics) -// PSR.ic - ssm (1<<13) - mov r1 =3D psr - ;; - srlz.d - rsm (1<<13) - mov r1 =3D cr.itir - ;; - srlz.d - rsm (1<<13) - mov r1 =3D cr.irr0 // no DV here - ;; - srlz.d - -// PSR.id (rfi is the only writer) -// PSR.is (br.ia and rfi are the only writers) -// PSR.it (rfi is the only writer) -// PSR.lp - mov psr.l =3D r0 - br.ret.sptk b0 - ;; - -// PSR.mc (rfi is the only writer) -// PSR.mfh - mov f32 =3D f33 - mov r1 =3D psr - ;; - -// PSR.mfl - mov f2 =3D f3 - mov r1 =3D psr - ;; - -// PSR.pk - rsm (1<<15) - ld8 r1 =3D [r1] - ;; - rsm (1<<15) - mov r2 =3D psr - ;; - -// PSR.pp - rsm (1<<21) - mov r1 =3D psr - ;; - -// PSR.ri (no DV semantics) -// PSR.rt - mov psr.l =3D r0 - flushrs - ;; - srlz.d - -// PSR.si - rsm (1<<23) - mov r1 =3D ar.itc - ;; - rsm (1<<23) - mov r1 =3D ar.ruc - ;; - ssm (1<<23) - mov r1 =3D ar.ec // no DV here - ;; - -// PSR.sp - ssm (1<<20) - mov r1 =3D pmd[r1] - ;; - ssm (1<<20) - rum 0xff - ;; - ssm (1<<20) - mov r1 =3D rr[r1] - ;; - -// PSR.ss (rfi is the only writer) -// PSR.tb - mov psr.l =3D r0 - chk.s r0, L - ;; - -// PSR.up - rsm (1<<2) - mov r1 =3D psr.um - ;; - srlz.d - -// RR# - mov rr[r0] =3D r1 - ld8 r2 =3D [r0] // data - ;; - mov rr[r4] =3D r5 - mov r6 =3D rr[r7] // impliedf - ;; - srlz.d - ;; -// RSE -=09 -// GR%, additional cases -// addl - mov r2 =3D r32 - addl r3 =3D 12345, r2 // impliedf, IA64_OPND_R3_2 - ;; -// postinc - ld8 r2 =3D [r32], 8 - mov r8 =3D r32 // impliedf - ;; - -// PR%, 16 - 62 - cmp.eq p21, p22 =3D r0, r1 // pr-writer/pr-reader-nobr-nomovpr -(p21) add r2 =3D r3, r4=09 - ;; - mov pr =3D r5, 0x1ffff // mov-to-pr-allreg/pr-reader-nobr-nomovpr -(p22) add r6 =3D r7, r8=09 - ;; - mov pr.rot =3D 0xffff0000 // mov-to-pr-rotreg/pr-reader-nobr-nomovpr -(p23) add r9 =3D r10, r11 - ;; - fcmp.eq p25, p26 =3D f2, f3 // pr-writer-fp/pr-reader-br -(p25) br.cond.sptk b0 - ;; - cmp.eq p27, p28 =3D r11, r12 -(p27) br.cond.sptk b1 // no DV here - ;; -=09 -// postinc - st8 [r6] =3D r8, 16 - add r7 =3D 8, r6 // impliedf - ;; - ldfd f14 =3D [r6], 16 - add r7 =3D 8, r6 // impliedf - ;; - stfd [r6] =3D f14, 16 - add r7 =3D r8, r6 - ;; - add r6 =3D 8, r7 - ld8 r8 =3D [r6], 16 // impliedf, WAW - ;; - add r6 =3D 8, r7 - ldfd f14 =3D [r6], 16 // impliedf, WAW - ;; - -L: - br.ret.sptk rp - -// PSR.vm. New in SDM 2.2 - vmsw.0 - ld8 r2 =3D [r1] - ;; diff --git a/gas/testsuite/gas/ia64/dv-safe.d b/gas/testsuite/gas/ia64/dv-s= afe.d deleted file mode 100644 index c1da4a4c308..00000000000 --- a/gas/testsuite/gas/ia64/dv-safe.d +++ /dev/null @@ -1,21 +0,0 @@ -# as: -xexplicit -mtune=3Ditanium1 -# objdump: -d -# name ia64 dv-safe - -.*: +file format .* - -Disassembly of section \.text: - -0+000 : - 0: 02 08 04 04 02 38 \[MII\] cmp\.eq p1,p2=3Dr1,r2 - 6: 30 18 10 08 70 00 cmp\.eq p3,p4=3Dr3,r4;; - c: 00 00 04 00 nop\.i 0x0 - 10: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 16: 00 00 00 02 80 21 nop\.f 0x0 - 1c: 30 00 00 50 \(p03\) br\.call\.sptk\.few b1=3D40 - 20: 20 20 08 00 00 a4 \[MII\] \(p01\) mov r4=3D2 - 26: 40 28 00 00 c8 a1 \(p02\) mov r4=3D5 - 2c: 00 30 00 84 \(p03\) mov r5=3Dr6 - 30: 9d 28 00 0e 00 21 \[MFB\] \(p04\) mov r5=3Dr7 - 36: 00 00 00 02 00 00 nop\.f 0x0 - 3c: 00 00 00 20 nop\.b 0x0;; diff --git a/gas/testsuite/gas/ia64/dv-safe.s b/gas/testsuite/gas/ia64/dv-s= afe.s deleted file mode 100644 index 5d92e6313ad..00000000000 --- a/gas/testsuite/gas/ia64/dv-safe.s +++ /dev/null @@ -1,19 +0,0 @@ -//=09 -// Test predicate safety across calls -//=09 -.text -start:=09 -// user annotation=09 - .pred.safe_across_calls p1-p4 - .pred.safe_across_calls p1,p2,p3,p4 - .pred.safe_across_calls p1-p2,p3-p4 - .pred.safe_across_calls p1-p3,p4 - cmp.eq p1, p2 =3D r1, r2 - cmp.eq p3, p4 =3D r3, r4 ;; -=09 -(p3) br.call.sptk b1 =3D L -(p1) mov r4 =3D 2 -(p2) mov r4 =3D 5 -(p3) mov r5 =3D r6 -(p4) mov r5 =3D r7 -L:=09 diff --git a/gas/testsuite/gas/ia64/dv-srlz.d b/gas/testsuite/gas/ia64/dv-s= rlz.d deleted file mode 100644 index bf9caa48e6f..00000000000 --- a/gas/testsuite/gas/ia64/dv-srlz.d +++ /dev/null @@ -1,24 +0,0 @@ -# as: -xauto -mtune=3Ditanium1 -# objdump: -d -# name ia64 dv-srlz - -.*: +file format .* - -Disassembly of section \.text: - -0+000 : - 0: 0a 00 00 02 34 04 \[MMI\] ptc\.e r1;; - 6: 00 00 00 60 00 00 srlz\.d - c: 00 00 04 00 nop\.i 0x0 - 10: 1d 08 00 04 18 10 \[MFB\] ld8 r1=3D\[r2\] - 16: 00 00 00 02 00 00 nop\.f 0x0 - 1c: 00 00 20 00 rfi;; - 20: 0b 00 00 02 34 04 \[MMI\] ptc\.e r1;; - 26: 00 00 00 62 00 00 srlz\.i - 2c: 00 00 04 00 nop\.i 0x0;; - 30: 17 00 00 00 10 00 \[BBB\] epc - 36: 00 00 00 00 10 00 nop\.b 0x0 - 3c: 00 00 00 20 nop\.b 0x0;; - 40: 1d 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 46: 00 00 00 02 00 00 nop\.f 0x0 - 4c: 00 00 20 00 rfi;; diff --git a/gas/testsuite/gas/ia64/dv-srlz.s b/gas/testsuite/gas/ia64/dv-s= rlz.s deleted file mode 100644 index 273e51b9f5e..00000000000 --- a/gas/testsuite/gas/ia64/dv-srlz.s +++ /dev/null @@ -1,13 +0,0 @@ -// -// Auto-insertion of instruction and data serialization -//=09=09=09 -.text -start:=09=09 -// Requires data serialization=09 - ptc.e r1 - ld8 r1 =3D [r2] - rfi -// Requires instruction serialization - ptc.e r1 - epc - rfi diff --git a/gas/testsuite/gas/ia64/dv-war-err.l b/gas/testsuite/gas/ia64/d= v-war-err.l deleted file mode 100644 index 27103cdf409..00000000000 --- a/gas/testsuite/gas/ia64/dv-war-err.l +++ /dev/null @@ -1,3 +0,0 @@ -.*: Assembler messages: -.*:8: Warning: Use of 'br.wtop.sptk' .* WAR dependency 'PR63' \(stop\) -.*:7: Warning: This is the location of the conflicting usage diff --git a/gas/testsuite/gas/ia64/dv-war-err.s b/gas/testsuite/gas/ia64/d= v-war-err.s deleted file mode 100644 index a226e96581e..00000000000 --- a/gas/testsuite/gas/ia64/dv-war-err.s +++ /dev/null @@ -1,9 +0,0 @@ -//=09 -// Detect WAR violations. Cases taken from DV tables. -//=09 -.text - .explicit -// PR63 -(p63) br.cond.sptk b0 - br.wtop.sptk L=09 -L:=09 diff --git a/gas/testsuite/gas/ia64/dv-waw-err.l b/gas/testsuite/gas/ia64/d= v-waw-err.l deleted file mode 100644 index 761bc363bb1..00000000000 --- a/gas/testsuite/gas/ia64/dv-waw-err.l +++ /dev/null @@ -1,395 +0,0 @@ -.*: Assembler messages: -.*:8: Warning: Use of 'mov\.m' violates WAW dependency 'AR\[BSP\]' \(impli= edf\) -.*:7: Warning: This is the location of the conflicting usage -.*:12: Warning: Use of 'mov\.m' violates WAW dependency 'AR\[BSP\]' \(impl= iedf\) -.*:11: Warning: This is the location of the conflicting usage -.*:12: Warning: Use of 'mov\.m' violates WAW dependency 'AR\[BSPSTORE\]' \= (impliedf\) -.*:11: Warning: This is the location of the conflicting usage -.*:12: Warning: Use of 'mov\.m' violates WAW dependency 'AR\[RNAT\]' \(imp= liedf\) -.*:11: Warning: This is the location of the conflicting usage -.*:12: Warning: Use of 'mov\.m' violates RAW dependency 'RSE' \(impliedf\) -.*:11: Warning: This is the location of the conflicting usage -.*:12: Warning: Use of 'mov\.m' violates WAW dependency 'RSE' \(impliedf\) -.*:11: Warning: This is the location of the conflicting usage -.*:17: Warning: Use of 'mov\.m' violates WAW dependency 'AR\[CCV\]' \(impl= iedf\) -.*:16: Warning: This is the location of the conflicting usage -.*:22: Warning: Use of 'mov\.i' violates WAW dependency 'AR\[EC\]' \(impli= edf\) -.*:21: Warning: This is the location of the conflicting usage -.*:27: Warning: Use of 'fsetc\.s0' violates RAW dependency 'AR\[FPSR\]\.sf= 0\.controls' \(impliedf\) -.*:26: Warning: This is the location of the conflicting usage -.*:27: Warning: Use of 'fsetc\.s0' violates WAW dependency 'AR\[FPSR\]\.sf= 0\.controls' \(impliedf\) -.*:26: Warning: This is the location of the conflicting usage -.*:32: Warning: Use of 'fsetc\.s1' violates RAW dependency 'AR\[FPSR\]\.sf= 0\.controls' \(impliedf\) -.*:31: Warning: This is the location of the conflicting usage -.*:32: Warning: Use of 'fsetc\.s1' violates WAW dependency 'AR\[FPSR\]\.sf= 1\.controls' \(impliedf\) -.*:31: Warning: This is the location of the conflicting usage -.*:37: Warning: Use of 'fsetc\.s2' violates RAW dependency 'AR\[FPSR\]\.sf= 0\.controls' \(impliedf\) -.*:36: Warning: This is the location of the conflicting usage -.*:37: Warning: Use of 'fsetc\.s2' violates WAW dependency 'AR\[FPSR\]\.sf= 2\.controls' \(impliedf\) -.*:36: Warning: This is the location of the conflicting usage -.*:42: Warning: Use of 'fsetc\.s3' violates RAW dependency 'AR\[FPSR\]\.sf= 0\.controls' \(impliedf\) -.*:41: Warning: This is the location of the conflicting usage -.*:42: Warning: Use of 'fsetc\.s3' violates WAW dependency 'AR\[FPSR\]\.sf= 3\.controls' \(impliedf\) -.*:41: Warning: This is the location of the conflicting usage -.*:50: Warning: Use of 'fclrf\.s0' violates WAW dependency 'AR\[FPSR\]\.sf= 0\.flags' \(impliedf\) -.*:49: Warning: This is the location of the conflicting usage -.*:58: Warning: Use of 'fclrf\.s1' violates WAW dependency 'AR\[FPSR\]\.sf= 1\.flags' \(impliedf\) -.*:57: Warning: This is the location of the conflicting usage -.*:66: Warning: Use of 'fclrf\.s2' violates WAW dependency 'AR\[FPSR\]\.sf= 2\.flags' \(impliedf\) -.*:65: Warning: This is the location of the conflicting usage -.*:74: Warning: Use of 'fclrf\.s3' violates WAW dependency 'AR\[FPSR\]\.sf= 3\.flags' \(impliedf\) -.*:73: Warning: This is the location of the conflicting usage -.*:79: Warning: Use of 'mov\.m' violates WAW dependency 'AR\[FPSR\]\.sf0\.= controls' \(impliedf\) -.*:78: Warning: This is the location of the conflicting usage -.*:79: Warning: Use of 'mov\.m' violates WAW dependency 'AR\[FPSR\]\.sf1\.= controls' \(impliedf\) -.*:78: Warning: This is the location of the conflicting usage -.*:79: Warning: Use of 'mov\.m' violates WAW dependency 'AR\[FPSR\]\.sf2\.= controls' \(impliedf\) -.*:78: Warning: This is the location of the conflicting usage -.*:79: Warning: Use of 'mov\.m' violates WAW dependency 'AR\[FPSR\]\.sf3\.= controls' \(impliedf\) -.*:78: Warning: This is the location of the conflicting usage -.*:79: Warning: Use of 'mov\.m' violates WAW dependency 'AR\[FPSR\]\.sf0\.= flags' \(impliedf\) -.*:78: Warning: This is the location of the conflicting usage -.*:79: Warning: Use of 'mov\.m' violates WAW dependency 'AR\[FPSR\]\.sf0\.= flags' \(impliedf\) -.*:78: Warning: This is the location of the conflicting usage -.*:79: Warning: Use of 'mov\.m' violates WAW dependency 'AR\[FPSR\]\.sf1\.= flags' \(impliedf\) -.*:78: Warning: This is the location of the conflicting usage -.*:79: Warning: Use of 'mov\.m' violates WAW dependency 'AR\[FPSR\]\.sf1\.= flags' \(impliedf\) -.*:78: Warning: This is the location of the conflicting usage -.*:79: Warning: Use of 'mov\.m' violates WAW dependency 'AR\[FPSR\]\.sf2\.= flags' \(impliedf\) -.*:78: Warning: This is the location of the conflicting usage -.*:79: Warning: Use of 'mov\.m' violates WAW dependency 'AR\[FPSR\]\.sf2\.= flags' \(impliedf\) -.*:78: Warning: This is the location of the conflicting usage -.*:79: Warning: Use of 'mov\.m' violates WAW dependency 'AR\[FPSR\]\.sf3\.= flags' \(impliedf\) -.*:78: Warning: This is the location of the conflicting usage -.*:79: Warning: Use of 'mov\.m' violates WAW dependency 'AR\[FPSR\]\.sf3\.= flags' \(impliedf\) -.*:78: Warning: This is the location of the conflicting usage -.*:79: Warning: Use of 'mov\.m' violates WAW dependency 'AR\[FPSR\]\.rv' \= (impliedf\) -.*:78: Warning: This is the location of the conflicting usage -.*:79: Warning: Use of 'mov\.m' violates WAW dependency 'AR\[FPSR\]\.traps= ' \(impliedf\) -.*:78: Warning: This is the location of the conflicting usage -.*:84: Warning: Use of 'mov\.m' violates WAW dependency 'AR\[ITC\]' \(impl= iedf\) -.*:83: Warning: This is the location of the conflicting usage -.*:89: Warning: Use of 'mov\.m' violates WAW dependency 'AR\[RUC\]' \(impl= iedf\) -.*:88: Warning: This is the location of the conflicting usage -.*:94: Warning: Use of 'mov\.m' violates WAW dependency 'AR\[K%\], % in[ = ]*0[ ]+- 7' \(impliedf\), specific resource number is 2 -.*:93: Warning: This is the location of the conflicting usage -.*:99: Warning: Use of 'mov\.i' violates WAW dependency 'AR\[LC\]' \(impli= edf\) -.*:98: Warning: This is the location of the conflicting usage -.*:104: Warning: Use of 'br\.call\.sptk' violates WAW dependency 'AR\[PFS\= ]' \(impliedf\) -.*:103: Warning: This is the location of the conflicting usage -.*:109: Warning: Use of 'mov\.m' violates WAW dependency 'AR\[RNAT\]' \(im= pliedf\) -.*:108: Warning: This is the location of the conflicting usage -.*:114: Warning: Use of 'mov\.m' violates WAW dependency 'AR\[RSC\]' \(imp= liedf\) -.*:113: Warning: This is the location of the conflicting usage -.*:119: Warning: Use of 'st8\.spill' may violate WAW dependency 'AR\[UNAT\= ]\{%\}, % in[ ]*0[ ]+- 63' \(impliedf\) -.*:118: Warning: This is the location of the conflicting usage -.*:124: Warning: Use of 'mov' violates WAW dependency 'AR%, % in[ ]*48[ = ]+- 63, 112-127' \(impliedf\), specific resource number is 48 -.*:123: Warning: This is the location of the conflicting usage -.*:129: Warning: Use of 'mov' violates WAW dependency 'BR%, % in[ ]*0[ ]= +- 7' \(impliedf\), specific resource number is 1 -.*:128: Warning: This is the location of the conflicting usage -.*:134: Warning: Use of 'br\.wtop\.sptk' violates RAW dependency 'AR\[EC\]= ' \(impliedf\) -.*:133: Warning: This is the location of the conflicting usage -.*:134: Warning: Use of 'br\.wtop\.sptk' violates RAW dependency 'CFM' \(i= mpliedf\) -.*:133: Warning: This is the location of the conflicting usage -.*:134: Warning: Use of 'br\.wtop\.sptk' violates WAW dependency 'AR\[EC\]= ' \(impliedf\) -.*:133: Warning: This is the location of the conflicting usage -.*:134: Warning: Use of 'br\.wtop\.sptk' violates WAW dependency 'CFM' \(i= mpliedf\) -.*:133: Warning: This is the location of the conflicting usage -.*:134: Warning: Use of 'br\.wtop\.sptk' violates WAW dependency 'PR63' \(= impliedf\) -.*:133: Warning: This is the location of the conflicting usage -.*:134: Warning: Use of 'br\.wtop\.sptk' violates WAW dependency 'PR63' \(= impliedf\) -.*:133: Warning: This is the location of the conflicting usage -.*:139: Warning: Use of 'mov' violates WAW dependency 'CR\[CMCV\]' \(impli= edf\) -.*:138: Warning: This is the location of the conflicting usage -.*:144: Warning: Use of 'mov' violates WAW dependency 'CR\[DCR\]' \(implie= df\) -.*:143: Warning: This is the location of the conflicting usage -.*:149: Warning: Use of 'mov' violates RAW dependency 'InService\*' \(impl= iedf\) -.*:148: Warning: This is the location of the conflicting usage -.*:149: Warning: Use of 'mov' violates WAW dependency 'CR\[EOI\]' \(other\) -.*:148: Warning: This is the location of the conflicting usage -.*:149: Warning: Use of 'mov' violates WAW dependency 'InService\*' \(othe= r\) -.*:148: Warning: This is the location of the conflicting usage -.*:155: Warning: Use of 'mov' violates WAW dependency 'CR\[GPTA\]' \(impli= edf\) -.*:154: Warning: This is the location of the conflicting usage -.*:160: Warning: Use of 'mov' violates WAW dependency 'CR\[IFA\]' \(implie= df\) -.*:159: Warning: This is the location of the conflicting usage -.*:165: Warning: Use of 'cover' violates WAW dependency 'CR\[IFS\]' \(impl= iedf\) -.*:164: Warning: This is the location of the conflicting usage -.*:170: Warning: Use of 'mov' violates WAW dependency 'CR\[IHA\]' \(implie= df\) -.*:169: Warning: This is the location of the conflicting usage -.*:175: Warning: Use of 'mov' violates WAW dependency 'CR\[IIB%\], % in[ = ]*0[ ]+- 1' \(impliedf\), specific resource number is 26 -.*:174: Warning: This is the location of the conflicting usage -.*:179: Warning: Use of 'mov' violates WAW dependency 'CR\[IIB%\], % in[ = ]*0[ ]+- 1' \(impliedf\), specific resource number is 27 -.*:178: Warning: This is the location of the conflicting usage -.*:184: Warning: Use of 'mov' violates WAW dependency 'CR\[IIM\]' \(implie= df\) -.*:183: Warning: This is the location of the conflicting usage -.*:189: Warning: Use of 'mov' violates WAW dependency 'CR\[IIP\]' \(implie= df\) -.*:188: Warning: This is the location of the conflicting usage -.*:194: Warning: Use of 'mov' violates WAW dependency 'CR\[IIPA\]' \(impli= edf\) -.*:193: Warning: This is the location of the conflicting usage -.*:199: Warning: Use of 'mov' violates WAW dependency 'CR\[IPSR\]' \(impli= edf\) -.*:198: Warning: This is the location of the conflicting usage -.*:204: Warning: Use of 'mov' violates RAW dependency 'InService\*' \(impl= iedf\) -.*:203: Warning: This is the location of the conflicting usage -.*:204: Warning: Use of 'mov' violates WAW dependency 'CR\[IRR%\], % in[ = ]*0[ ]+- 3' \(impliedf\), specific resource number is 71 -.*:203: Warning: This is the location of the conflicting usage -.*:204: Warning: Use of 'mov' violates WAW dependency 'CR\[IRR%\], % in[ = ]*0[ ]+- 3' \(impliedf\), specific resource number is 70 -.*:203: Warning: This is the location of the conflicting usage -.*:204: Warning: Use of 'mov' violates WAW dependency 'CR\[IRR%\], % in[ = ]*0[ ]+- 3' \(impliedf\), specific resource number is 69 -.*:203: Warning: This is the location of the conflicting usage -.*:204: Warning: Use of 'mov' violates WAW dependency 'CR\[IRR%\], % in[ = ]*0[ ]+- 3' \(impliedf\), specific resource number is 68 -.*:203: Warning: This is the location of the conflicting usage -.*:204: Warning: Use of 'mov' violates WAW dependency 'InService\*' \(othe= r\) -.*:203: Warning: This is the location of the conflicting usage -.*:209: Warning: Use of 'mov' violates WAW dependency 'CR\[ISR\]' \(implie= df\) -.*:208: Warning: This is the location of the conflicting usage -.*:214: Warning: Use of 'mov' violates WAW dependency 'CR\[ITIR\]' \(impli= edf\) -.*:213: Warning: This is the location of the conflicting usage -.*:219: Warning: Use of 'mov' violates WAW dependency 'CR\[ITM\]' \(implie= df\) -.*:218: Warning: This is the location of the conflicting usage -.*:224: Warning: Use of 'mov' violates WAW dependency 'CR\[ITV\]' \(implie= df\) -.*:223: Warning: This is the location of the conflicting usage -.*:229: Warning: Use of 'mov' violates WAW dependency 'CR\[IVA\]' \(implie= df\) -.*:228: Warning: This is the location of the conflicting usage -.*:236: Warning: Use of 'mov' violates WAW dependency 'CR\[LID\]' \(other\) -.*:235: Warning: This is the location of the conflicting usage -.*:244: Warning: Use of 'mov' violates WAW dependency 'CR\[LRR%\], % in[ = ]*0[ ]+- 1' \(impliedf\), specific resource number is 80 -.*:243: Warning: This is the location of the conflicting usage -.*:249: Warning: Use of 'mov' violates WAW dependency 'CR\[PMV\]' \(implie= df\) -.*:248: Warning: This is the location of the conflicting usage -.*:254: Warning: Use of 'mov' violates WAW dependency 'CR\[PTA\]' \(implie= df\) -.*:253: Warning: This is the location of the conflicting usage -.*:259: Warning: Use of 'mov' violates WAW dependency 'CR\[TPR\]' \(implie= df\) -.*:258: Warning: This is the location of the conflicting usage -.*:264: Warning: Use of 'mov' may violate WAW dependency 'DBR\#' \(implied= f\) -.*:263: Warning: This is the location of the conflicting usage -.*:273: Warning: Use of 'itc\.i' violates RAW dependency 'DTC' \(impliedf\) -.*:272: Warning: This is the location of the conflicting usage -.*:273: Warning: Use of 'itc\.i' violates RAW dependency 'ITC' \(impliedf\) -.*:272: Warning: This is the location of the conflicting usage -.*:273: Warning: Use of 'itc\.i' violates WAW dependency 'DTC' \(impliedf\) -.*:272: Warning: This is the location of the conflicting usage -.*:273: Warning: Use of 'itc\.i' violates WAW dependency 'ITC' \(impliedf\) -.*:272: Warning: This is the location of the conflicting usage -.*:285: Warning: Use of 'ptr\.d' violates RAW dependency 'DTC' \(impliedf\) -.*:284: Warning: This is the location of the conflicting usage -.*:285: Warning: Use of 'ptr\.d' violates RAW dependency 'DTR' \(impliedf\) -.*:284: Warning: This is the location of the conflicting usage -.*:285: Warning: Use of 'ptr\.d' violates RAW dependency 'ITC' \(impliedf\) -.*:284: Warning: This is the location of the conflicting usage -.*:285: Warning: Use of 'ptr\.d' violates WAW dependency 'DTC' \(impliedf\) -.*:284: Warning: This is the location of the conflicting usage -.*:285: Warning: Use of 'ptr\.d' violates WAW dependency 'DTR' \(impliedf\) -.*:284: Warning: This is the location of the conflicting usage -.*:285: Warning: Use of 'ptr\.d' violates WAW dependency 'ITC' \(impliedf\) -.*:284: Warning: This is the location of the conflicting usage -.*:291: Warning: Use of 'ldfs\.c\.clr' violates WAW dependency 'FR%, % in[= ]*2[ ]+- 127' \(impliedf\), specific resource number is 3 -.*:290: Warning: This is the location of the conflicting usage -.*:296: Warning: Use of 'ld8\.c\.clr' violates WAW dependency 'GR%, % in[ = ]*1[ ]+- 127' \(impliedf\), specific resource number is 2 -.*:295: Warning: This is the location of the conflicting usage -.*:301: Warning: Use of 'mov' may violate WAW dependency 'IBR\#' \(implied= f\) -.*:300: Warning: This is the location of the conflicting usage -.*:306: Warning: Use of 'mov' violates RAW dependency 'InService\*' \(data= \) -.*:305: Warning: This is the location of the conflicting usage -.*:306: Warning: Use of 'mov' violates WAW dependency 'InService\*' \(othe= r\) -.*:305: Warning: This is the location of the conflicting usage -.*:312: Warning: Use of 'itc\.i' violates RAW dependency 'DTC' \(impliedf\) -.*:311: Warning: This is the location of the conflicting usage -.*:312: Warning: Use of 'itc\.i' violates RAW dependency 'ITC' \(impliedf\) -.*:311: Warning: This is the location of the conflicting usage -.*:312: Warning: Use of 'itc\.i' violates WAW dependency 'DTC' \(impliedf\) -.*:311: Warning: This is the location of the conflicting usage -.*:312: Warning: Use of 'itc\.i' violates WAW dependency 'ITC' \(impliedf\) -.*:311: Warning: This is the location of the conflicting usage -.*:319: Warning: Use of 'ptr\.i' violates RAW dependency 'DTC' \(impliedf\) -.*:318: Warning: This is the location of the conflicting usage -.*:319: Warning: Use of 'ptr\.i' violates RAW dependency 'ITC' \(impliedf\) -.*:318: Warning: This is the location of the conflicting usage -.*:319: Warning: Use of 'ptr\.i' violates RAW dependency 'ITR' \(impliedf\) -.*:318: Warning: This is the location of the conflicting usage -.*:319: Warning: Use of 'ptr\.i' violates WAW dependency 'DTC' \(impliedf\) -.*:318: Warning: This is the location of the conflicting usage -.*:319: Warning: Use of 'ptr\.i' violates WAW dependency 'ITC' \(impliedf\) -.*:318: Warning: This is the location of the conflicting usage -.*:319: Warning: Use of 'ptr\.i' violates WAW dependency 'ITR' \(impliedf\) -.*:318: Warning: This is the location of the conflicting usage -.*:331: Warning: Use of 'mov' violates WAW dependency 'PKR\#' \(impliedf\)= , specific resource number is 1 -.*:330: Warning: This is the location of the conflicting usage -.*:336: Warning: Use of 'mov' may violate WAW dependency 'PMC\#' \(implied= f\) -.*:335: Warning: This is the location of the conflicting usage -.*:341: Warning: Use of 'mov' may violate WAW dependency 'PMD\#' \(implied= f\) -.*:340: Warning: This is the location of the conflicting usage -.*:346: Warning: Use of 'cmp\.eq' violates WAW dependency 'PR%, % in[ ]*1= [ ]+- 15' \(impliedf\), specific resource number is 1 -.*:345: Warning: This is the location of the conflicting usage -.*:346: Warning: Use of 'cmp\.eq' violates WAW dependency 'PR%, % in[ ]*1= [ ]+- 15' \(impliedf\), specific resource number is 1 -.*:345: Warning: This is the location of the conflicting usage -.*:349: Warning: Use of 'fcmp\.eq' violates WAW dependency 'PR%, % in[ ]*= 1[ ]+- 15' \(impliedf\), specific resource number is 1 -.*:348: Warning: This is the location of the conflicting usage -.*:349: Warning: Use of 'fcmp\.eq' violates WAW dependency 'PR%, % in[ ]*= 1[ ]+- 15' \(impliedf\), specific resource number is 1 -.*:348: Warning: This is the location of the conflicting usage -.*:352: Warning: Use of 'cmp\.eq\.or' violates WAW dependency 'PR%, % in[ = ]*1[ ]+- 15' \(impliedf\), specific resource number is 1 -.*:351: Warning: This is the location of the conflicting usage -.*:355: Warning: Use of 'cmp\.eq\.and' violates WAW dependency 'PR%, % in[= ]*1[ ]+- 15' \(impliedf\), specific resource number is 1 -.*:354: Warning: This is the location of the conflicting usage -.*:366: Warning: Use of 'br\.wtop\.sptk' violates RAW dependency 'AR\[EC\]= ' \(impliedf\) -.*:365: Warning: This is the location of the conflicting usage -.*:366: Warning: Use of 'br\.wtop\.sptk' violates RAW dependency 'CFM' \(i= mpliedf\) -.*:365: Warning: This is the location of the conflicting usage -.*:366: Warning: Use of 'br\.wtop\.sptk' violates WAW dependency 'AR\[EC\]= ' \(impliedf\) -.*:365: Warning: This is the location of the conflicting usage -.*:366: Warning: Use of 'br\.wtop\.sptk' violates WAW dependency 'CFM' \(i= mpliedf\) -.*:365: Warning: This is the location of the conflicting usage -.*:366: Warning: Use of 'br\.wtop\.sptk' violates WAW dependency 'PR63' \(= impliedf\) -.*:365: Warning: This is the location of the conflicting usage -.*:366: Warning: Use of 'br\.wtop\.sptk' violates WAW dependency 'PR63' \(= impliedf\) -.*:365: Warning: This is the location of the conflicting usage -.*:369: Warning: Use of 'cmp\.eq' violates WAW dependency 'PR63' \(implied= f\) -.*:368: Warning: This is the location of the conflicting usage -.*:369: Warning: Use of 'cmp\.eq' violates WAW dependency 'PR63' \(implied= f\) -.*:368: Warning: This is the location of the conflicting usage -.*:372: Warning: Use of 'fcmp\.eq' violates WAW dependency 'PR63' \(implie= df\) -.*:371: Warning: This is the location of the conflicting usage -.*:372: Warning: Use of 'fcmp\.eq' violates WAW dependency 'PR63' \(implie= df\) -.*:371: Warning: This is the location of the conflicting usage -.*:375: Warning: Use of 'cmp\.eq\.or' violates WAW dependency 'PR63' \(imp= liedf\) -.*:374: Warning: This is the location of the conflicting usage -.*:378: Warning: Use of 'cmp\.eq\.and' violates WAW dependency 'PR63' \(im= pliedf\) -.*:377: Warning: This is the location of the conflicting usage -.*:389: Warning: Use of 'rum' violates WAW dependency 'PSR\.ac' \(impliedf= \) -.*:388: Warning: This is the location of the conflicting usage -.*:394: Warning: Use of 'rum' violates WAW dependency 'PSR\.be' \(impliedf= \) -.*:393: Warning: This is the location of the conflicting usage -.*:404: Warning: Use of 'br\.ret\.sptk' violates WAW dependency 'PSR\.cpl'= \(impliedf\) -.*:403: Warning: This is the location of the conflicting usage -.*:410: Warning: Use of 'mov' violates WAW dependency 'PSR\.ac' \(impliedf= \) -.*:409: Warning: This is the location of the conflicting usage -.*:410: Warning: Use of 'mov' violates WAW dependency 'PSR\.be' \(impliedf= \) -.*:409: Warning: This is the location of the conflicting usage -.*:410: Warning: Use of 'mov' violates WAW dependency 'PSR\.db' \(impliedf= \) -.*:409: Warning: This is the location of the conflicting usage -.*:410: Warning: Use of 'mov' violates WAW dependency 'PSR\.dfh' \(implied= f\) -.*:409: Warning: This is the location of the conflicting usage -.*:410: Warning: Use of 'mov' violates WAW dependency 'PSR\.dfl' \(implied= f\) -.*:409: Warning: This is the location of the conflicting usage -.*:410: Warning: Use of 'mov' violates WAW dependency 'PSR\.di' \(impliedf= \) -.*:409: Warning: This is the location of the conflicting usage -.*:410: Warning: Use of 'mov' violates WAW dependency 'PSR\.dt' \(impliedf= \) -.*:409: Warning: This is the location of the conflicting usage -.*:410: Warning: Use of 'mov' violates WAW dependency 'PSR\.i' \(impliedf\) -.*:409: Warning: This is the location of the conflicting usage -.*:410: Warning: Use of 'mov' violates WAW dependency 'PSR\.ic' \(impliedf= \) -.*:409: Warning: This is the location of the conflicting usage -.*:410: Warning: Use of 'mov' violates WAW dependency 'PSR\.lp' \(impliedf= \) -.*:409: Warning: This is the location of the conflicting usage -.*:410: Warning: Use of 'mov' violates WAW dependency 'PSR\.mfh' \(implied= f\) -.*:409: Warning: This is the location of the conflicting usage -.*:410: Warning: Use of 'mov' violates WAW dependency 'PSR\.mfh' \(implied= f\) -.*:409: Warning: This is the location of the conflicting usage -.*:410: Warning: Use of 'mov' violates WAW dependency 'PSR\.mfl' \(implied= f\) -.*:409: Warning: This is the location of the conflicting usage -.*:410: Warning: Use of 'mov' violates WAW dependency 'PSR\.mfl' \(implied= f\) -.*:409: Warning: This is the location of the conflicting usage -.*:410: Warning: Use of 'mov' violates WAW dependency 'PSR\.pk' \(impliedf= \) -.*:409: Warning: This is the location of the conflicting usage -.*:410: Warning: Use of 'mov' violates WAW dependency 'PSR\.pp' \(impliedf= \) -.*:409: Warning: This is the location of the conflicting usage -.*:410: Warning: Use of 'mov' violates WAW dependency 'PSR\.rt' \(impliedf= \) -.*:409: Warning: This is the location of the conflicting usage -.*:410: Warning: Use of 'mov' violates WAW dependency 'PSR\.si' \(impliedf= \) -.*:409: Warning: This is the location of the conflicting usage -.*:410: Warning: Use of 'mov' violates WAW dependency 'PSR\.sp' \(impliedf= \) -.*:409: Warning: This is the location of the conflicting usage -.*:410: Warning: Use of 'mov' violates WAW dependency 'PSR\.tb' \(impliedf= \) -.*:409: Warning: This is the location of the conflicting usage -.*:410: Warning: Use of 'mov' violates WAW dependency 'PSR\.up' \(impliedf= \) -.*:409: Warning: This is the location of the conflicting usage -.*:418: Warning: Use of 'ssm' violates WAW dependency 'PSR\.dfh' \(implied= f\) -.*:417: Warning: This is the location of the conflicting usage -.*:424: Warning: Use of 'ssm' violates WAW dependency 'PSR\.dfl' \(implied= f\) -.*:423: Warning: This is the location of the conflicting usage -.*:430: Warning: Use of 'rsm' violates WAW dependency 'PSR\.di' \(impliedf= \) -.*:429: Warning: This is the location of the conflicting usage -.*:435: Warning: Use of 'rsm' violates WAW dependency 'PSR\.dt' \(impliedf= \) -.*:434: Warning: This is the location of the conflicting usage -.*:441: Warning: Use of 'ssm' violates WAW dependency 'PSR\.i' \(impliedf\) -.*:440: Warning: This is the location of the conflicting usage -.*:447: Warning: Use of 'ssm' violates WAW dependency 'PSR\.ic' \(impliedf= \) -.*:446: Warning: This is the location of the conflicting usage -.*:458: Warning: Use of 'mov' violates RAW dependency 'PSR\.mfh' \(implied= f\) -.*:457: Warning: This is the location of the conflicting usage -.*:461: Warning: Use of 'ssm' violates WAW dependency 'PSR\.mfh' \(implied= f\) -.*:460: Warning: This is the location of the conflicting usage -.*:461: Warning: Use of 'ssm' violates WAW dependency 'PSR\.mfh' \(implied= f\) -.*:460: Warning: This is the location of the conflicting usage -.*:464: Warning: Use of 'mov' violates WAW dependency 'PSR\.mfh' \(implied= f\) -.*:463: Warning: This is the location of the conflicting usage -.*:464: Warning: Use of 'mov' violates WAW dependency 'PSR\.mfh' \(implied= f\) -.*:463: Warning: This is the location of the conflicting usage -.*:467: Warning: Use of 'rum' violates WAW dependency 'PSR\.mfh' \(implied= f\) -.*:466: Warning: This is the location of the conflicting usage -.*:467: Warning: Use of 'rum' violates WAW dependency 'PSR\.mfh' \(implied= f\) -.*:466: Warning: This is the location of the conflicting usage -.*:475: Warning: Use of 'mov' violates RAW dependency 'PSR\.mfl' \(implied= f\) -.*:474: Warning: This is the location of the conflicting usage -.*:478: Warning: Use of 'ssm' violates WAW dependency 'PSR\.mfl' \(implied= f\) -.*:477: Warning: This is the location of the conflicting usage -.*:478: Warning: Use of 'ssm' violates WAW dependency 'PSR\.mfl' \(implied= f\) -.*:477: Warning: This is the location of the conflicting usage -.*:481: Warning: Use of 'mov' violates WAW dependency 'PSR\.mfl' \(implied= f\) -.*:480: Warning: This is the location of the conflicting usage -.*:481: Warning: Use of 'mov' violates WAW dependency 'PSR\.mfl' \(implied= f\) -.*:480: Warning: This is the location of the conflicting usage -.*:484: Warning: Use of 'rum' violates WAW dependency 'PSR\.mfl' \(implied= f\) -.*:483: Warning: This is the location of the conflicting usage -.*:484: Warning: Use of 'rum' violates WAW dependency 'PSR\.mfl' \(implied= f\) -.*:483: Warning: This is the location of the conflicting usage -.*:492: Warning: Use of 'rsm' violates WAW dependency 'PSR\.pk' \(impliedf= \) -.*:491: Warning: This is the location of the conflicting usage -.*:497: Warning: Use of 'rsm' violates WAW dependency 'PSR\.pp' \(impliedf= \) -.*:496: Warning: This is the location of the conflicting usage -.*:505: Warning: Use of 'ssm' violates WAW dependency 'PSR\.si' \(impliedf= \) -.*:504: Warning: This is the location of the conflicting usage -.*:510: Warning: Use of 'rsm' violates WAW dependency 'PSR\.sp' \(impliedf= \) -.*:509: Warning: This is the location of the conflicting usage -.*:519: Warning: Use of 'rsm' violates WAW dependency 'PSR\.up' \(impliedf= \) -.*:518: Warning: This is the location of the conflicting usage -.*:522: Warning: Use of 'mov' violates WAW dependency 'PSR\.up' \(impliedf= \) -.*:521: Warning: This is the location of the conflicting usage -.*:527: Warning: Use of 'mov' violates WAW dependency 'RR\#' \(impliedf\),= specific resource number is 7 -.*:526: Warning: This is the location of the conflicting usage -.*:550: Warning: Use of 'cmp\.eq\.and\.orcm' violates WAW dependency 'PR%,= % in[ ]*1[ ]+- 15' \(impliedf\), specific resource number is 7 -.*:549: Warning: This is the location of the conflicting usage -.*:550: Warning: Use of 'cmp\.eq\.and\.orcm' violates WAW dependency 'PR%,= % in[ ]*1[ ]+- 15' \(impliedf\), specific resource number is 6 -.*:549: Warning: This is the location of the conflicting usage -.*:550: Warning: Use of 'cmp\.eq\.and\.orcm' violates WAW dependency 'PR%,= % in[ ]*1[ ]+- 15' \(impliedf\), specific resource number is 7 -.*:549: Warning: This is the location of the conflicting usage -.*:550: Warning: Use of 'cmp\.eq\.and\.orcm' violates WAW dependency 'PR%,= % in[ ]*1[ ]+- 15' \(impliedf\), specific resource number is 6 -.*:549: Warning: This is the location of the conflicting usage -.*:553: Warning: Use of 'cmp\.eq\.and\.orcm' violates WAW dependency 'PR%,= % in[ ]*1[ ]+- 15' \(impliedf\), specific resource number is 7 -.*:552: Warning: This is the location of the conflicting usage -.*:553: Warning: Use of 'cmp\.eq\.and\.orcm' violates WAW dependency 'PR%,= % in[ ]*1[ ]+- 15' \(impliedf\), specific resource number is 7 -.*:552: Warning: This is the location of the conflicting usage -.*:553: Warning: Use of 'cmp\.eq\.and\.orcm' violates WAW dependency 'PR63= ' \(impliedf\) -.*:552: Warning: This is the location of the conflicting usage -.*:553: Warning: Use of 'cmp\.eq\.and\.orcm' violates WAW dependency 'PR63= ' \(impliedf\) -.*:552: Warning: This is the location of the conflicting usage -.*:556: Warning: Use of 'cmp\.eq\.and\.orcm' violates WAW dependency 'PR%,= % in[ ]*1[ ]+- 15' \(impliedf\), specific resource number is 6 -.*:555: Warning: This is the location of the conflicting usage -.*:556: Warning: Use of 'cmp\.eq\.and\.orcm' violates WAW dependency 'PR%,= % in[ ]*1[ ]+- 15' \(impliedf\), specific resource number is 6 -.*:555: Warning: This is the location of the conflicting usage -.*:556: Warning: Use of 'cmp\.eq\.and\.orcm' violates WAW dependency 'PR63= ' \(impliedf\) -.*:555: Warning: This is the location of the conflicting usage -.*:556: Warning: Use of 'cmp\.eq\.and\.orcm' violates WAW dependency 'PR63= ' \(impliedf\) -.*:555: Warning: This is the location of the conflicting usage -.*:561: Warning: Use of 'cmp\.eq' violates WAW dependency 'PR%, % in[ ]*1= 6[ ]+- 62' \(impliedf\), specific resource number is 21 -.*:560: Warning: This is the location of the conflicting usage -.*:561: Warning: Use of 'cmp\.eq' violates WAW dependency 'PR%, % in[ ]*1= 6[ ]+- 62' \(impliedf\), specific resource number is 21 -.*:560: Warning: This is the location of the conflicting usage -.*:564: Warning: Use of 'fcmp\.eq' violates WAW dependency 'PR%, % in[ ]*= 16[ ]+- 62' \(impliedf\), specific resource number is 21 -.*:563: Warning: This is the location of the conflicting usage -.*:564: Warning: Use of 'fcmp\.eq' violates WAW dependency 'PR%, % in[ ]*= 16[ ]+- 62' \(impliedf\), specific resource number is 21 -.*:563: Warning: This is the location of the conflicting usage -.*:567: Warning: Use of 'cmp\.eq\.or' violates WAW dependency 'PR%, % in[ = ]*16[ ]+- 62' \(impliedf\), specific resource number is 21 -.*:566: Warning: This is the location of the conflicting usage -.*:570: Warning: Use of 'cmp\.eq\.and' violates WAW dependency 'PR%, % in[= ]*16[ ]+- 62' \(impliedf\), specific resource number is 21 -.*:569: Warning: This is the location of the conflicting usage diff --git a/gas/testsuite/gas/ia64/dv-waw-err.s b/gas/testsuite/gas/ia64/d= v-waw-err.s deleted file mode 100644 index 7d8c0f29396..00000000000 --- a/gas/testsuite/gas/ia64/dv-waw-err.s +++ /dev/null @@ -1,581 +0,0 @@ -//=09 -// Detect WAW violations. Cases taken from DV tables. -//=09 -.text - .explicit -// AR[BSP] - mov ar.bsp =3D r0 - mov ar.bsp =3D r1 - ;; -// AR[BSPSTORE]=09 - mov ar.bspstore =3D r2 - mov ar.bspstore =3D r3 - ;; -=09 -// AR[CCV] - mov ar.ccv =3D r4 - mov ar.ccv =3D r4 - ;; -=09 -// AR[EC]=09 - br.wtop.sptk L - mov ar.ec =3D r0 - ;; - -// AR[FPSR].sf0.controls=20 - mov ar.fpsr =3D r0 - fsetc.s0 0x7f, 0x0f - ;; - -// AR[FPSR].sf1.controls - mov ar.fpsr =3D r0 - fsetc.s1 0x7f, 0x0f - ;; - -// AR[FPSR].sf2.controls - mov ar.fpsr =3D r0 - fsetc.s2 0x7f, 0x0f - ;; - -// AR[FPSR].sf3.controls - mov ar.fpsr =3D r0 - fsetc.s3 0x7f, 0x0f - ;; - -// AR[FPSR].sf0.flags - fcmp.eq.s0 p1, p2 =3D f3, f4 - fcmp.eq.s0 p3, p4 =3D f3, f4 // no DV here - ;; - fcmp.eq.s0 p1, p2 =3D f3, f4 - fclrf.s0 - ;; - -// AR[FPSR].sf1.flags - fcmp.eq.s1 p1, p2 =3D f3, f4 - fcmp.eq.s1 p3, p4 =3D f3, f4 // no DV here - ;; - fcmp.eq.s1 p1, p2 =3D f3, f4 - fclrf.s1 - ;; - -// AR[FPSR].sf2.flags - fcmp.eq.s2 p1, p2 =3D f3, f4 - fcmp.eq.s2 p3, p4 =3D f3, f4 // no DV here - ;; - fcmp.eq.s2 p1, p2 =3D f3, f4 - fclrf.s2 - ;; - -// AR[FPSR].sf3.flags - fcmp.eq.s3 p1, p2 =3D f3, f4 - fcmp.eq.s3 p3, p4 =3D f3, f4 // no DV here - ;; - fcmp.eq.s3 p1, p2 =3D f3, f4 - fclrf.s3 - ;; - -// AR[FPSR].traps/rv plus all controls/flags - mov ar.fpsr =3D r0 - mov ar.fpsr =3D r0 - ;; - -// AR[ITC] - mov ar.itc =3D r1 - mov ar.itc =3D r1 - ;; - -// AR[RUC] - mov ar.ruc =3D r1 - mov ar.ruc =3D r1 - ;; - -// AR[K] - mov ar.k2 =3D r3 - mov ar.k2 =3D r3 - ;; -=09 -// AR[LC] - br.cloop.sptk L - mov ar.lc =3D r0 - ;; -=09 -// AR[PFS] - mov ar.pfs =3D r0 - br.call.sptk b0 =3D L - ;; - -// AR[RNAT] (see also AR[BSPSTORE]) - mov ar.rnat =3D r8 - mov ar.rnat =3D r8 - ;; -=09 -// AR[RSC] - mov ar.rsc =3D r10 - mov ar.rsc =3D r10 - ;;=09 -=09 -// AR[UNAT]=09 - mov ar.unat =3D r12 - st8.spill [r0] =3D r1 - ;; -=09 -// AR% - mov ar48 =3D r0 - mov ar48 =3D r0 - ;; - -// BR% - mov b1 =3D r0 - mov b1 =3D r1 - ;; -=09 -// CFM (and others) - br.wtop.sptk L - br.wtop.sptk L - ;; -=09 -// CR[CMCV] - mov cr.cmcv =3D r1 - mov cr.cmcv =3D r2 - ;; - -// CR[DCR] - mov cr.dcr =3D r3 - mov cr.dcr =3D r3 - ;; - -// CR[EOI] (and InService) - mov cr.eoi =3D r0 - mov cr.eoi =3D r0 - ;; - srlz.d -=09 -// CR[GPTA] - mov cr.gpta =3D r6 - mov cr.gpta =3D r7 - ;; - -// CR[IFA] - mov cr.ifa =3D r9 - mov cr.ifa =3D r10 - ;; - -// CR[IFS] - mov cr.ifs =3D r11 - cover - ;; - -// CR[IHA] - mov cr.iha =3D r13 - mov cr.iha =3D r14 - ;; - -// CR[IIB%] - mov cr.iib0 =3D r15 - mov cr.iib0 =3D r16 - ;; - - mov cr.iib1 =3D r15 - mov cr.iib1 =3D r16 - ;; - -// CR[IIM] - mov cr.iim =3D r15 - mov cr.iim =3D r16 - ;; - -// CR[IIP]=20 - mov cr.iip =3D r17 - mov cr.iip =3D r17 - ;; - -// CR[IIPA] - mov cr.iipa =3D r19 - mov cr.iipa =3D r20 - ;; - -// CR[IPSR] - mov cr.ipsr =3D r21 - mov cr.ipsr =3D r22 - ;; - -// CR[IRR%] (and others) - mov r2 =3D cr.ivr - mov r3 =3D cr.ivr - ;; -=09 -// CR[ISR] - mov cr.isr =3D r24 - mov cr.isr =3D r25 - ;;=09 -=09 -// CR[ITIR] - mov cr.itir =3D r26 - mov cr.itir =3D r27 - ;;=09 -=09 -// CR[ITM] - mov cr.itm =3D r28 - mov cr.itm =3D r29 - ;;=09 -=09 -// CR[ITV] - mov cr.itv =3D r0 - mov cr.itv =3D r1 - ;;=09 -=09 -// CR[IVA] - mov cr.iva =3D r0 - mov cr.iva =3D r1 - ;;=09 -=09 -// CR[IVR] (no explicit writers) -=09 -// CR[LID] - mov cr.lid =3D r0 - mov cr.lid =3D r1 - ;; -=09 -// CR[LRR%] - mov cr.lrr0 =3D r0 - mov cr.lrr1 =3D r0 // no DV here - ;; - mov cr.lrr0 =3D r0 - mov cr.lrr0 =3D r0 - ;; -=09 -// CR[PMV] - mov cr.pmv =3D r0 - mov cr.pmv =3D r1 - ;; -=09 -// CR[PTA] - mov cr.pta =3D r0 - mov cr.pta =3D r1 - ;; -=09 -// CR[TPR] - mov cr.tpr =3D r0 - mov cr.tpr =3D r1 - ;; -=09 -// DBR#=20 - mov dbr[r1] =3D r1 - mov dbr[r1] =3D r2 - ;; - srlz.d -=09 -// DTC - ptc.e r0 - ptc.e r1 // no DVs here - ;; - ptc.e r0 // (and others) - itc.i r0 - ;; - srlz.d -=09 -// DTC_LIMIT - ptc.g r0, r1 // NOTE: GAS automatically emits stops after=20 - ptc.ga r2, r3 // ptc.g/ptc.ga, so this conflict is no=20=20=20=20=20 - ;; // longer possible in GAS-generated assembly - srlz.d -=09 -// DTR=20 - itr.d dtr[r0] =3D r1 // (and others) - ptr.d r2, r3 - ;; - srlz.d -=09 -// FR% - mov f3 =3D f2 - ldfs.c.clr f3 =3D [r1] - ;; - -// GR% - mov r2 =3D r0=09=09 - ld8.c.clr r2 =3D [r1] - ;; - -// IBR# - mov ibr[r0] =3D r2 - mov ibr[r1] =3D r2 - ;; - -// InService=09=09 - mov cr.eoi =3D r0 - mov r1 =3D cr.ivr - ;; - srlz.d -=09 -// ITC=09=09 - ptc.e r0 - itc.i r1 - ;; - srlz.i - ;; -=09 -// ITR=09 - itr.i itr[r0] =3D r1 - ptr.i r2, r3 - ;; - srlz.i - ;; -=09 -// PKR# - .reg.val r1, 0x1 - .reg.val r2, ~0x1 - mov pkr[r1] =3D r1 - mov pkr[r2] =3D r1 // no DV here - ;; - mov pkr[r1] =3D r1 - mov pkr[r1] =3D r1 - ;; -=09 -// PMC# - mov pmc[r3] =3D r1 - mov pmc[r4] =3D r1 - ;; -=09 -// PMD# - mov pmd[r3] =3D r1 - mov pmd[r4] =3D r1 - ;; -=09 -// PR%, 1 - 15 - cmp.eq p1, p0 =3D r0, r1 - cmp.eq p1, p0 =3D r2, r3 - ;; - fcmp.eq p1, p2 =3D f2, f3 - fcmp.eq p1, p3 =3D f2, f3 - ;; - cmp.eq.and p1, p2 =3D r0, r1 - cmp.eq.or p1, p3 =3D r2, r3 - ;; - cmp.eq.or p1, p3 =3D r2, r3 - cmp.eq.and p1, p2 =3D r0, r1 - ;; - cmp.eq.and p1, p2 =3D r0, r1 - cmp.eq.and p1, p3 =3D r2, r3 // no DV here - ;; - cmp.eq.or p1, p2 =3D r0, r1 - cmp.eq.or p1, p3 =3D r2, r3 // no DV here - ;; -=09 -// PR63 - br.wtop.sptk L - br.wtop.sptk L - ;; - cmp.eq p63, p0 =3D r0, r1 - cmp.eq p63, p0 =3D r2, r3 - ;; - fcmp.eq p63, p2 =3D f2, f3 - fcmp.eq p63, p3 =3D f2, f3 - ;; - cmp.eq.and p63, p2 =3D r0, r1 - cmp.eq.or p63, p3 =3D r2, r3 - ;; - cmp.eq.or p63, p3 =3D r2, r3 - cmp.eq.and p63, p2 =3D r0, r1 - ;; - cmp.eq.and p63, p2 =3D r0, r1 - cmp.eq.and p63, p3 =3D r2, r3 // no DV here - ;; - cmp.eq.or p63, p2 =3D r0, r1 - cmp.eq.or p63, p3 =3D r2, r3 // no DV here - ;; - -// PSR.ac - rum (1<<3) - rum (1<<3) - ;; - -// PSR.be - rum (1<<1) - rum (1<<1) - ;; -=09 -// PSR.bn - bsw.0 // GAS automatically emits a stop after bsw.n - bsw.0 // so this conflict is avoided=20=20=20=20=20=20=20=20=20=20=20= =20=20=20=20 - ;; - -// PSR.cpl - epc - br.ret.sptk b0 - ;; - -// PSR.da (rfi is the only writer) -// PSR.db (and others) - mov psr.l =3D r0 - mov psr.l =3D r1 - ;; - srlz.d - -// PSR.dd (rfi is the only writer) -=09 -// PSR.dfh - ssm (1<<19) - ssm (1<<19) - ;; - srlz.d - -// PSR.dfl - ssm (1<<18) - ssm (1<<18) - ;; - srlz.d -=09 -// PSR.di - rsm (1<<22) - rsm (1<<22) - ;; - -// PSR.dt - rsm (1<<17) - rsm (1<<17) - ;; -=09 -// PSR.ed (rfi is the only writer) -// PSR.i - ssm (1<<14) - ssm (1<<14) - ;; -=09 -// PSR.ia (no DV semantics) -// PSR.ic - ssm (1<<13) - ssm (1<<13) - ;; - -// PSR.id (rfi is the only writer) -// PSR.is (br.ia and rfi are the only writers) -// PSR.it (rfi is the only writer) -// PSR.lp (see PSR.db) - -// PSR.mc (rfi is the only writer) -// PSR.mfh - mov f32 =3D f33 - mov r10 =3D psr - ;; - ssm (1<<5) - ssm (1<<5) - ;; - ssm (1<<5) - mov psr.um =3D r10 - ;; - rum (1<<5) - rum (1<<5) - ;; - mov f32 =3D f33 - mov f34 =3D f35 // no DV here - ;; - -// PSR.mfl - mov f2 =3D f3 - mov r10 =3D psr - ;; - ssm (1<<4) - ssm (1<<4) - ;; - ssm (1<<4) - mov psr.um =3D r10 - ;; - rum (1<<4) - rum (1<<4) - ;; - mov f2 =3D f3 - mov f4 =3D f5 // no DV here - ;; - -// PSR.pk - rsm (1<<15) - rsm (1<<15) - ;; - -// PSR.pp - rsm (1<<21) - rsm (1<<21) - ;; - -// PSR.ri (no DV semantics) -// PSR.rt (see PSR.db) - -// PSR.si - rsm (1<<23) - ssm (1<<23) - ;; - -// PSR.sp - ssm (1<<20) - rsm (1<<20) - ;; - srlz.d - -// PSR.ss (rfi is the only writer) -// PSR.tb (see PSR.db) - -// PSR.up - rsm (1<<2) - rsm (1<<2) - ;; - rum (1<<2) - mov psr.um =3D r0 - ;; - -// RR# - mov rr[r2] =3D r1 - mov rr[r2] =3D r3 - ;; - -// PR, additional cases (or.andcm and and.orcm interaction) - cmp.eq.or.andcm p6, p7 =3D 1, r32 - cmp.eq.or.andcm p6, p7 =3D 5, r36 // no DV here - ;; - cmp.eq.and.orcm p6, p7 =3D 1, r32 - cmp.eq.and.orcm p6, p7 =3D 5, r36 // no DV here - ;; - cmp.eq.or.andcm p63, p7 =3D 1, r32 - cmp.eq.or.andcm p63, p7 =3D 5, r36 // no DV here - ;; - cmp.eq.or.andcm p6, p63 =3D 1, r32 - cmp.eq.or.andcm p6, p63 =3D 5, r36 // no DV here - ;; - cmp.eq.and.orcm p63, p7 =3D 1, r32 - cmp.eq.and.orcm p63, p7 =3D 5, r36 // no DV here - ;; - cmp.eq.and.orcm p6, p63 =3D 1, r32 - cmp.eq.and.orcm p6, p63 =3D 5, r36 // no DV here - ;; - cmp.eq.or.andcm p6, p7 =3D 1, r32 - cmp.eq.and.orcm p6, p7 =3D 5, r36=09 - ;; - cmp.eq.or.andcm p63, p7 =3D 1, r32 - cmp.eq.and.orcm p63, p7 =3D 5, r36=09 - ;; - cmp.eq.or.andcm p6, p63 =3D 1, r32 - cmp.eq.and.orcm p6, p63 =3D 5, r36=09 - ;; - -// PR%, 16 - 62 - cmp.eq p21, p0 =3D r0, r1 - cmp.eq p21, p0 =3D r2, r3 - ;; - fcmp.eq p21, p22 =3D f2, f3 - fcmp.eq p21, p23 =3D f2, f3 - ;; - cmp.eq.and p21, p22 =3D r0, r1 - cmp.eq.or p21, p23 =3D r2, r3 - ;; - cmp.eq.or p21, p23 =3D r2, r3 - cmp.eq.and p21, p22 =3D r0, r1 - ;; - cmp.eq.and p21, p22 =3D r0, r1 - cmp.eq.and p21, p23 =3D r2, r3 // no DV here - ;; - cmp.eq.or p21, p22 =3D r0, r1 - cmp.eq.or p21, p23 =3D r2, r3 // no DV here - ;; - -// RSE - -L: diff --git a/gas/testsuite/gas/ia64/fixup-dump.pl b/gas/testsuite/gas/ia64/= fixup-dump.pl deleted file mode 100644 index 73c218b2bee..00000000000 --- a/gas/testsuite/gas/ia64/fixup-dump.pl +++ /dev/null @@ -1,12 +0,0 @@ -print "# objdump: -d\n"; -print "# name: ia64 $ARGV[0]\n"; -shift; - -while (<>) { - if (/.*file format.*/) { - $_ =3D ".*: +file format .*\n"; - } else { - s/([][().])/\\$1/g; - } - print; -} diff --git a/gas/testsuite/gas/ia64/forward.d b/gas/testsuite/gas/ia64/forw= ard.d deleted file mode 100644 index 66aecde6a95..00000000000 --- a/gas/testsuite/gas/ia64/forward.d +++ /dev/null @@ -1,15 +0,0 @@ -# as: -xexplicit -# objdump: -d -# name ia64 forward references - -.*: +file format .* - -Disassembly of section \.text: - -0+ <_start>: -[[:space:]]*[[:xdigit:]]*:[[:space:][:xdigit:]]+\[MIB\][[:space:]]+alloc r= 31=3Dar.pfs,12,6,8 -[[:space:]]*[[:xdigit:]]*:[[:space:][:xdigit:]]+[[:space:]]+dep.z r2=3D1,5= ,7 -[[:space:]]*[[:xdigit:]]*:[[:space:][:xdigit:]]+\(p0?6\)[[:space:]]+br.con= d.sptk.few 0+ <_start>;; -[[:space:]]*[[:xdigit:]]*:[[:space:][:xdigit:]]+\[MIB\][[:space:]]+alloc r= 31=3Dar.pfs,0,0,0 -[[:space:]]*[[:xdigit:]]*:[[:space:][:xdigit:]]+[[:space:]]+dep.z r3=3D-1,= 1,1 -[[:space:]]*[[:xdigit:]]*:[[:space:][:xdigit:]]+\(p0?7\)[[:space:]]+br(\.c= ond)?\.sptk(\.few)? [[:xdigit:]]+0 <.*>;; diff --git a/gas/testsuite/gas/ia64/forward.s b/gas/testsuite/gas/ia64/forw= ard.s deleted file mode 100644 index fc2590b778c..00000000000 --- a/gas/testsuite/gas/ia64/forward.s +++ /dev/null @@ -1,27 +0,0 @@ -two =3D=3D 2*one -one =3D 1 -three =3D=3D 3*one -four =3D 4*one - -RA =3D=3D rA -rA =3D r2 - -PA =3D=3D pA -pA =3D p6 - - .text -_start: - alloc r31 =3D one + 1, two + 2, three + 3, four + 4 - dep.z RA =3D one, two + 3, three + 4 -(PA) br.sptk _start - ;; - -one =3D -1 -rA =3D r3 -pA =3D p7 - -.L1: - alloc r31 =3D one + 1, two + 2, three + 3, four - 4 - dep.z RA =3D one, two + 3, three + 4 -(PA) br.sptk .L1 - ;; diff --git a/gas/testsuite/gas/ia64/global.d b/gas/testsuite/gas/ia64/globa= l.d deleted file mode 100644 index f6346373f2b..00000000000 --- a/gas/testsuite/gas/ia64/global.d +++ /dev/null @@ -1,10 +0,0 @@ -#readelf: --syms -#name: ia64 global label - -Symbol table '.symtab' contains 5 entries: - +Num: +Value +Size +Type +Bind +Vis +Ndx +Name - +0: 0+0 +0 +NOTYPE +LOCAL +DEFAULT +UND=20 - +1: 0+0 +0 +SECTION +LOCAL +DEFAULT +1.* - +2: 0+0 +0 +SECTION +LOCAL +DEFAULT +2.* - +3: 0+0 +0 +SECTION +LOCAL +DEFAULT +3.* - +4: 0+0 +0 +NOTYPE +GLOBAL +DEFAULT +2 foo diff --git a/gas/testsuite/gas/ia64/global.s b/gas/testsuite/gas/ia64/globa= l.s deleted file mode 100644 index 9ad702c3715..00000000000 --- a/gas/testsuite/gas/ia64/global.s +++ /dev/null @@ -1,3 +0,0 @@ - .data -foo:: - data1 0 diff --git a/gas/testsuite/gas/ia64/group-1.d b/gas/testsuite/gas/ia64/grou= p-1.d deleted file mode 100644 index a04a5ccf46e..00000000000 --- a/gas/testsuite/gas/ia64/group-1.d +++ /dev/null @@ -1,32 +0,0 @@ -#readelf: -Sg -#name: ia64 group - -There are 9 section headers, starting at offset .*: - -Section Headers: - \[Nr\] Name Type Address Offset - Size EntSize Flags Link Info Align - \[ 0\] NULL 0000000000000000 00000000 - 0000000000000000 0000000000000000 0 0 0 - \[ 1\] \.group GROUP 0000000000000000 00000040 - 0000000000000008 0000000000000004 6 6 4 - \[ 2\] \.text PROGBITS 0000000000000000 00000050 - 0000000000000000 0000000000000000 AX 0 0 16 - \[ 3\] \.data PROGBITS 0000000000000000 00000050 - 0000000000000000 0000000000000000 WA 0 0 1 - \[ 4\] \.bss NOBITS 0000000000000000 00000050 - 0000000000000000 0000000000000000 WA 0 0 1 - \[ 5\] \.text PROGBITS 0000000000000000 00000050 - 0000000000000010 0000000000000000 AXG 0 0 16 - \[ 6\] \.symtab SYMTAB 0000000000000000 .* - 00000000000000c0 0000000000000018 7 8 8 - \[ 7\] \.strtab STRTAB 0000000000000000 .* - 000000000000000[7c] 0000000000000000 0 0 1 - \[ 8\] \.shstrtab STRTAB 0000000000000000 [0-9a-f]+ - 0000000000000033 0000000000000000 0 0 1 -Key to Flags: -#... - -COMDAT group section \[ 1\] `\.group' \[\._foo\] contains 1 sections: - \[Index\] Name - \[ 5\] \.text diff --git a/gas/testsuite/gas/ia64/group-1.s b/gas/testsuite/gas/ia64/grou= p-1.s deleted file mode 100644 index ed7f64f9315..00000000000 --- a/gas/testsuite/gas/ia64/group-1.s +++ /dev/null @@ -1,10 +0,0 @@ - .section .text,"axG",@progbits,._foo,comdat - .proc _foo# -_foo: - (p6) br.cond.dptk .L37 -.L48: -.L70: -.L37: -.L77: -.L74: - .endp _foo# diff --git a/gas/testsuite/gas/ia64/group-2.d b/gas/testsuite/gas/ia64/grou= p-2.d deleted file mode 100644 index 52a313a7d6f..00000000000 --- a/gas/testsuite/gas/ia64/group-2.d +++ /dev/null @@ -1,42 +0,0 @@ -#readelf: -Sg -T -#as: -x -#name: ia64 unwind group - -There are 12 section headers, starting at offset .*: - -Section Headers: - \[Nr\] Name Type Address Offset - Size EntSize Flags Link Info Align - \[ 0\] NULL 0000000000000000 00000000 - 0000000000000000 0000000000000000 0 0 0 - \[ 1\] \.group GROUP 0000000000000000 00000040 - 0000000000000014 0000000000000004 9 5 4 - \[ 2\] \.text PROGBITS 0000000000000000 00000060 - 0000000000000000 0000000000000000 AX 0 0 16 - \[ 3\] \.data PROGBITS 0000000000000000 00000060 - 0000000000000000 0000000000000000 WA 0 0 1 - \[ 4\] \.bss NOBITS 0000000000000000 00000060 - 0000000000000000 0000000000000000 WA 0 0 1 - \[ 5\] \.gnu\.linkonce\.t\.f PROGBITS 0000000000000000 00000060 - 0000000000000000 0000000000000000 AXG 0 0 16 - \[ 6\] \.gnu\.linkonce\.ia6 PROGBITS 0000000000000000 00000060 - 0000000000000010 0000000000000000 AG 0 0 8 - \[ 7\] \.gnu\.linkonce\.ia6 IA_64_UNWIND 0000000000000000 00000070 - 0000000000000018 0000000000000000 ALG 5 5 8 - \[ 8\] \.rela\.gnu\.linkonc RELA 0000000000000000 .* - 0000000000000048 0000000000000018 IG 9 7 8 - \[ 9\] \.symtab SYMTAB 0000000000000000 .* - 00000000000000d8 0000000000000018 10 9 8 - \[10\] \.strtab STRTAB 0000000000000000 .* - 0000000000000005 0000000000000000 0 0 1 - \[11\] \.shstrtab STRTAB 0000000000000000 [0-9a-f]+ - 0000000000000081 0000000000000000 0 0 1 -Key to Flags: -#... - -COMDAT group section \[ 1\] `\.group' \[foo\] contains 4 sections: - \[Index\] Name - \[ 5\] \.gnu\.linkonce\.t\.foo - \[ 6\] \.gnu\.linkonce\.ia64unwi\.foo - \[ 7\] \.gnu\.linkonce\.ia64unw\.foo - \[ 8\] \.rela\.gnu\.linkonce\.ia64unw\.foo diff --git a/gas/testsuite/gas/ia64/group-2.s b/gas/testsuite/gas/ia64/grou= p-2.s deleted file mode 100644 index 6b6b9fc0edf..00000000000 --- a/gas/testsuite/gas/ia64/group-2.s +++ /dev/null @@ -1,6 +0,0 @@ - .section .gnu.linkonce.t.foo,"axG",@progbits,foo,comdat - .proc foo# -foo: - .prologue 12, r33 - ;; - .endp foo# diff --git a/gas/testsuite/gas/ia64/hint.b-err.l b/gas/testsuite/gas/ia64/h= int.b-err.l deleted file mode 100644 index 86d8b5e52bd..00000000000 --- a/gas/testsuite/gas/ia64/hint.b-err.l +++ /dev/null @@ -1,3 +0,0 @@ -.*: Assembler messages: -.*:1: Error: hint.b shouldn't be used -.*:2: Error: hint.b shouldn't be used diff --git a/gas/testsuite/gas/ia64/hint.b-err.s b/gas/testsuite/gas/ia64/h= int.b-err.s deleted file mode 100644 index 75f7a6522fb..00000000000 --- a/gas/testsuite/gas/ia64/hint.b-err.s +++ /dev/null @@ -1,2 +0,0 @@ - hint.b @pause - hint.b 0x1ffff diff --git a/gas/testsuite/gas/ia64/hint.b-warn.l b/gas/testsuite/gas/ia64/= hint.b-warn.l deleted file mode 100644 index 1c5f0be537c..00000000000 --- a/gas/testsuite/gas/ia64/hint.b-warn.l +++ /dev/null @@ -1,3 +0,0 @@ -.*: Assembler messages: -.*:1: Warning: hint.b may be treated as nop -.*:2: Warning: hint.b may be treated as nop diff --git a/gas/testsuite/gas/ia64/hint.b-warn.s b/gas/testsuite/gas/ia64/= hint.b-warn.s deleted file mode 100644 index 75f7a6522fb..00000000000 --- a/gas/testsuite/gas/ia64/hint.b-warn.s +++ /dev/null @@ -1,2 +0,0 @@ - hint.b @pause - hint.b 0x1ffff diff --git a/gas/testsuite/gas/ia64/ia64.exp b/gas/testsuite/gas/ia64/ia64.= exp deleted file mode 100644 index 832e14635ad..00000000000 --- a/gas/testsuite/gas/ia64/ia64.exp +++ /dev/null @@ -1,118 +0,0 @@ -# Copyright (C) 2012-2024 Free Software Foundation, Inc. - -# This program is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; either version 3 of the License, or -# (at your option) any later version. -#=20 -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -#=20 -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-130= 1, USA.=20=20 - -# -# ia64 tests -# -if [istarget "ia64-*"] then { - - run_dump_test "regs" - run_dump_test "opc-a" - run_list_test "opc-a-err" "" - run_dump_test "opc-b" - run_dump_test "opc-f" - run_dump_test "opc-i" - run_dump_test "opc-m" - run_dump_test "opc-x" - run_dump_test "psn" - run_dump_test "pseudo" - run_dump_test "nop_x" - run_dump_test "mov-ar" - run_list_test "operands" "" - run_list_test "reg-err" "" - - run_list_test "dv-raw-err" "" - run_list_test "dv-waw-err" "" - run_list_test "dv-war-err" "" - run_list_test "dv-entry-err" "" - run_list_test "dv-mutex-err" "" - run_dump_test "dv-branch" - run_dump_test "dv-imply" - run_dump_test "dv-mutex" - gas_test "pred-rel.s" "" "" ".pred.rel alternative forms" - run_dump_test "dv-safe" - run_dump_test "dv-srlz" - run_list_test "regval" "" - run_dump_test "tls" - run_dump_test "ldxmov-1" - run_list_test "ldxmov-2" "" - run_dump_test "ltoff22x-1" - run_dump_test "ltoff22x-2" - run_dump_test "ltoff22x-3" - run_dump_test "ltoff22x-4" - run_dump_test "ltoff22x-5" - - run_dump_test "nostkreg" - run_list_test "invalid-ar" "" - - run_dump_test "nostkreg" - run_list_test "invalid-ar" "" - - run_dump_test "dependency-1" - - run_dump_test "reloc" - run_dump_test "reloc-mlx" - run_list_test "reloc-bad" "" - run_dump_test "pcrel" - - run_dump_test "real" - run_dump_test "align" - run_dump_test "order" - run_dump_test "global" - if [istarget "ia64-*-hpux*"] then { - run_dump_test "secname-ilp32" - run_dump_test "unwind-ilp32" - run_dump_test "alias-ilp32" - run_dump_test "xdata-ilp32" - run_dump_test "reloc-uw-ilp32" - } else { - run_dump_test "secname" - run_dump_test "unwind" - run_dump_test "alias" - run_dump_test "xdata" - run_dump_test "reloc-uw" - run_dump_test "group-1" - run_dump_test "group-2" - } - - run_list_test "alloc" "" - run_dump_test "bundling" - run_dump_test "forward" - run_list_test "index" "" - run_list_test "label" "" - run_list_test "last" "" - run_list_test "no-fit" "" - run_list_test "pound" "-al" - run_list_test "proc" "-munwind-check=3Derror" - run_list_test "radix" "" - run_list_test "rotX" "" - run_list_test "slot2" "" - run_dump_test "strange" - run_list_test "unwind-bad" "" - run_list_test "unwind-err" "-munwind-check=3Derror" - run_dump_test "unwind-ok" - run_dump_test "operand-or" - run_list_test "hint.b-err" "" - run_list_test "hint.b-warn" "-mhint.b=3Dwarning" - - if [istarget "ia64-*-*vms*"] then { - run_dump_test "slotcount" - } - - if { [istarget "ia64-*-elf*"] || [istarget "ia64-*-linux*"] } { - run_dump_test "pr13167" - } -} diff --git a/gas/testsuite/gas/ia64/index.l b/gas/testsuite/gas/ia64/index.l deleted file mode 100644 index 41af9fdec2f..00000000000 --- a/gas/testsuite/gas/ia64/index.l +++ /dev/null @@ -1,42 +0,0 @@ -.*: Assembler messages: -.*.s:6: Error: [Ii]ndex must be a general register -.*.s:7: Error: [Ii]ndex must be a general register -.*.s:8: Error: [Ii]ndex must be a general register -.*.s:9: Error: [Ii]ndex must be a general register -.*.s:13: Error: [Ii]ndirect register index must be a general register -.*.s:14: Error: [Ii]ndirect register index must be a general register -.*.s:15: Error: [Ii]ndirect register index must be a general register -.*.s:16: Error: [Ii]ndirect register index must be a general register -.*.s:20: Error: [Ii]ndex can only be applied to rotating or indirect regis= ters -.*.s:21: Error: [Ii]ndex can only be applied to rotating or indirect regis= ters -.*.s:22: Error: [Ii]ndex can only be applied to rotating or indirect regis= ters -.*.s:23: Error: [Ii]ndex can only be applied to rotating or indirect regis= ters -.*.s:24: Error: [Ii]ndex can only be applied to rotating or indirect regis= ters -.*.s:25: Error: [Ii]ndex can only be applied to rotating or indirect regis= ters -.*.s:27: Error: [Ii]ndex can only be applied to rotating or indirect regis= ters -.*.s:28: Error: [Ii]ndex can only be applied to rotating or indirect regis= ters -.*.s:29: Error: [Ii]ndex can only be applied to rotating or indirect regis= ters -.*.s:30: Error: [Ii]ndex can only be applied to rotating or indirect regis= ters -.*.s:31: Error: [Ii]ndex can only be applied to rotating or indirect regis= ters -.*.s:32: Error: [Ii]ndex can only be applied to rotating or indirect regis= ters -.*.s:37: Error: [Rr]otating register index must be a non-negative constant -.*.s:39: Error: [Ii]ndex out of range 0\.\.[[:digit:]]+ -.*.s:40: Error: [Rr]otating register index must be a non-negative constant -.*.s:41: Error: [Rr]otating register index must be a non-negative constant -.*.s:42: Error: [Rr]otating register index must be a non-negative constant -.*.s:44: Error: [Ii]ndirect register index must be a general register -.*.s:45: Error: [Ii]ndirect register index must be a general register -.*.s:46: Error: [Ii]ndirect register index must be a general register -.*.s:47: Error: [Ii]ndirect register index must be a general register -.*.s:51: Error: [Ii]ndex can only be applied to rotating or indirect regis= ters -.*.s:52: Error: [Ii]ndex can only be applied to rotating or indirect regis= ters -.*.s:53: Error: [Ii]ndex can only be applied to rotating or indirect regis= ters -.*.s:54: Error: [Ii]ndex can only be applied to rotating or indirect regis= ters -.*.s:55: Error: [Ii]ndex can only be applied to rotating or indirect regis= ters -.*.s:56: Error: [Ii]ndex can only be applied to rotating or indirect regis= ters -.*.s:58: Error: [Ii]ndex can only be applied to rotating or indirect regis= ters -.*.s:59: Error: [Ii]ndex can only be applied to rotating or indirect regis= ters -.*.s:60: Error: [Ii]ndex can only be applied to rotating or indirect regis= ters -.*.s:61: Error: [Ii]ndex can only be applied to rotating or indirect regis= ters -.*.s:62: Error: [Ii]ndex can only be applied to rotating or indirect regis= ters -.*.s:63: Error: [Ii]ndex can only be applied to rotating or indirect regis= ters diff --git a/gas/testsuite/gas/ia64/index.s b/gas/testsuite/gas/ia64/index.s deleted file mode 100644 index 0a5d9f1ad1e..00000000000 --- a/gas/testsuite/gas/ia64/index.s +++ /dev/null @@ -1,63 +0,0 @@ -z =3D=3D zero -zero =3D=3D r0 - -.text -_start: - ld8 r2 =3D [ar.lc] - ld8 r3 =3D [1] - ld8 r4 =3D [-1] - ld8 r5 =3D [xyz] - ld8 r6 =3D [zero] - ld8 r7 =3D [z] - - mov r2 =3D cpuid[ar.lc] - mov r3 =3D cpuid[1] - mov r4 =3D cpuid[-1] - mov r5 =3D cpuid[xyz] - mov r6 =3D cpuid[zero] - mov r7 =3D cpuid[z] - - mov r2 =3D b0[ar.lc] - mov r3 =3D b0[1] - mov r4 =3D b0[-1] - mov r5 =3D b0[xyz] - mov r6 =3D b0[zero] - mov r7 =3D b0[z] - - mov r2 =3D xyz[ar.lc] - mov r3 =3D xyz[1] - mov r4 =3D xyz[-1] - mov r5 =3D xyz[xyz] - mov r6 =3D xyz[zero] - mov r7 =3D xyz[z] - -.regstk 0, 8, 0, 8 -.rotr reg[8] - - mov r2 =3D reg[ar.lc] - mov r3 =3D reg[1] - mov r4 =3D reg[-1] - mov r5 =3D reg[xyz] - mov r6 =3D reg[zero] - mov r7 =3D reg[z] - - mov r2 =3D cpuid[ar.lc] - mov r3 =3D cpuid[1] - mov r4 =3D cpuid[-1] - mov r5 =3D cpuid[xyz] - mov r6 =3D cpuid[zero] - mov r7 =3D cpuid[z] - - mov r2 =3D b0[ar.lc] - mov r3 =3D b0[1] - mov r4 =3D b0[-1] - mov r5 =3D b0[xyz] - mov r6 =3D b0[zero] - mov r7 =3D b0[z] - - mov r2 =3D xyz[ar.lc] - mov r3 =3D xyz[1] - mov r4 =3D xyz[-1] - mov r5 =3D xyz[xyz] - mov r6 =3D xyz[zero] - mov r7 =3D xyz[z] diff --git a/gas/testsuite/gas/ia64/invalid-ar.l b/gas/testsuite/gas/ia64/i= nvalid-ar.l deleted file mode 100644 index c7dda9b0445..00000000000 --- a/gas/testsuite/gas/ia64/invalid-ar.l +++ /dev/null @@ -1,125 +0,0 @@ -.*: Assembler messages: -.*:2: Error: AR 0 can only be accessed by M-unit -.*:3: Error: AR 1 can only be accessed by M-unit -.*:4: Error: AR 2 can only be accessed by M-unit -.*:5: Error: AR 3 can only be accessed by M-unit -.*:6: Error: AR 4 can only be accessed by M-unit -.*:7: Error: AR 5 can only be accessed by M-unit -.*:8: Error: AR 6 can only be accessed by M-unit -.*:9: Error: AR 7 can only be accessed by M-unit -.*:10: Error: AR 8 can only be accessed by M-unit -.*:11: Error: AR 9 can only be accessed by M-unit -.*:12: Error: AR 10 can only be accessed by M-unit -.*:13: Error: AR 11 can only be accessed by M-unit -.*:14: Error: AR 12 can only be accessed by M-unit -.*:15: Error: AR 13 can only be accessed by M-unit -.*:16: Error: AR 14 can only be accessed by M-unit -.*:17: Error: AR 15 can only be accessed by M-unit -.*:18: Error: AR 16 can only be accessed by M-unit -.*:19: Error: AR 17 can only be accessed by M-unit -.*:20: Error: AR 18 can only be accessed by M-unit -.*:21: Error: AR 19 can only be accessed by M-unit -.*:22: Error: AR 20 can only be accessed by M-unit -.*:23: Error: AR 21 can only be accessed by M-unit -.*:24: Error: AR 22 can only be accessed by M-unit -.*:25: Error: AR 23 can only be accessed by M-unit -.*:26: Error: AR 24 can only be accessed by M-unit -.*:27: Error: AR 25 can only be accessed by M-unit -.*:28: Error: AR 26 can only be accessed by M-unit -.*:29: Error: AR 27 can only be accessed by M-unit -.*:30: Error: AR 28 can only be accessed by M-unit -.*:31: Error: AR 29 can only be accessed by M-unit -.*:32: Error: AR 30 can only be accessed by M-unit -.*:33: Error: AR 31 can only be accessed by M-unit -.*:34: Error: AR 32 can only be accessed by M-unit -.*:35: Error: AR 33 can only be accessed by M-unit -.*:36: Error: AR 34 can only be accessed by M-unit -.*:37: Error: AR 35 can only be accessed by M-unit -.*:38: Error: AR 36 can only be accessed by M-unit -.*:39: Error: AR 37 can only be accessed by M-unit -.*:40: Error: AR 38 can only be accessed by M-unit -.*:41: Error: AR 39 can only be accessed by M-unit -.*:42: Error: AR 40 can only be accessed by M-unit -.*:43: Error: AR 41 can only be accessed by M-unit -.*:44: Error: AR 42 can only be accessed by M-unit -.*:45: Error: AR 43 can only be accessed by M-unit -.*:46: Error: AR 44 can only be accessed by M-unit -.*:47: Error: AR 45 can only be accessed by M-unit -.*:48: Error: AR 46 can only be accessed by M-unit -.*:49: Error: AR 47 can only be accessed by M-unit -.*:54: Error: AR 64 can only be accessed by I-unit -.*:55: Error: AR 65 can only be accessed by I-unit -.*:56: Error: AR 66 can only be accessed by I-unit -.*:57: Error: AR 67 can only be accessed by I-unit -.*:58: Error: AR 68 can only be accessed by I-unit -.*:59: Error: AR 69 can only be accessed by I-unit -.*:60: Error: AR 70 can only be accessed by I-unit -.*:61: Error: AR 71 can only be accessed by I-unit -.*:62: Error: AR 72 can only be accessed by I-unit -.*:63: Error: AR 73 can only be accessed by I-unit -.*:64: Error: AR 74 can only be accessed by I-unit -.*:65: Error: AR 75 can only be accessed by I-unit -.*:66: Error: AR 76 can only be accessed by I-unit -.*:67: Error: AR 77 can only be accessed by I-unit -.*:68: Error: AR 78 can only be accessed by I-unit -.*:69: Error: AR 79 can only be accessed by I-unit -.*:70: Error: AR 80 can only be accessed by I-unit -.*:71: Error: AR 81 can only be accessed by I-unit -.*:72: Error: AR 82 can only be accessed by I-unit -.*:73: Error: AR 83 can only be accessed by I-unit -.*:74: Error: AR 84 can only be accessed by I-unit -.*:75: Error: AR 85 can only be accessed by I-unit -.*:76: Error: AR 86 can only be accessed by I-unit -.*:77: Error: AR 87 can only be accessed by I-unit -.*:78: Error: AR 88 can only be accessed by I-unit -.*:79: Error: AR 89 can only be accessed by I-unit -.*:80: Error: AR 90 can only be accessed by I-unit -.*:81: Error: AR 91 can only be accessed by I-unit -.*:82: Error: AR 92 can only be accessed by I-unit -.*:83: Error: AR 93 can only be accessed by I-unit -.*:84: Error: AR 94 can only be accessed by I-unit -.*:85: Error: AR 95 can only be accessed by I-unit -.*:86: Error: AR 96 can only be accessed by I-unit -.*:87: Error: AR 97 can only be accessed by I-unit -.*:88: Error: AR 98 can only be accessed by I-unit -.*:89: Error: AR 99 can only be accessed by I-unit -.*:90: Error: AR 100 can only be accessed by I-unit -.*:91: Error: AR 101 can only be accessed by I-unit -.*:92: Error: AR 102 can only be accessed by I-unit -.*:93: Error: AR 103 can only be accessed by I-unit -.*:94: Error: AR 104 can only be accessed by I-unit -.*:95: Error: AR 105 can only be accessed by I-unit -.*:96: Error: AR 106 can only be accessed by I-unit -.*:97: Error: AR 107 can only be accessed by I-unit -.*:98: Error: AR 108 can only be accessed by I-unit -.*:99: Error: AR 109 can only be accessed by I-unit -.*:100: Error: AR 110 can only be accessed by I-unit -.*:101: Error: AR 111 can only be accessed by I-unit -.*:106: Error: AR 0 can only be accessed by M-unit -.*:107: Error: AR 1 can only be accessed by M-unit -.*:108: Error: AR 2 can only be accessed by M-unit -.*:109: Error: AR 3 can only be accessed by M-unit -.*:110: Error: AR 4 can only be accessed by M-unit -.*:111: Error: AR 5 can only be accessed by M-unit -.*:112: Error: AR 6 can only be accessed by M-unit -.*:113: Error: AR 7 can only be accessed by M-unit -.*:114: Error: AR 16 can only be accessed by M-unit -.*:115: Error: AR 17 can only be accessed by M-unit -.*:116: Error: AR 18 can only be accessed by M-unit -.*:117: Error: AR 19 can only be accessed by M-unit -.*:118: Error: AR 21 can only be accessed by M-unit -.*:119: Error: AR 24 can only be accessed by M-unit -.*:120: Error: AR 25 can only be accessed by M-unit -.*:121: Error: AR 26 can only be accessed by M-unit -.*:122: Error: AR 27 can only be accessed by M-unit -.*:123: Error: AR 28 can only be accessed by M-unit -.*:124: Error: AR 29 can only be accessed by M-unit -.*:125: Error: AR 30 can only be accessed by M-unit -.*:126: Error: AR 32 can only be accessed by M-unit -.*:127: Error: AR 36 can only be accessed by M-unit -.*:128: Error: AR 40 can only be accessed by M-unit -.*:129: Error: AR 44 can only be accessed by M-unit -.*:130: Error: AR 45 can only be accessed by M-unit -.*:133: Error: AR 64 can only be accessed by I-unit -.*:134: Error: AR 65 can only be accessed by I-unit -.*:135: Error: AR 66 can only be accessed by I-unit diff --git a/gas/testsuite/gas/ia64/invalid-ar.s b/gas/testsuite/gas/ia64/i= nvalid-ar.s deleted file mode 100644 index 9dc19bf8054..00000000000 --- a/gas/testsuite/gas/ia64/invalid-ar.s +++ /dev/null @@ -1,135 +0,0 @@ -// AR 0 to AR 47 can be accessed only by M unit. - mov.i r1 =3D ar0 - mov.i r1 =3D ar1 - mov.i r1 =3D ar2 - mov.i r1 =3D ar3 - mov.i r1 =3D ar4 - mov.i r1 =3D ar5 - mov.i r1 =3D ar6 - mov.i r1 =3D ar7 - mov.i r1 =3D ar8 - mov.i r1 =3D ar9 - mov.i r1 =3D ar10 - mov.i r1 =3D ar11 - mov.i r1 =3D ar12 - mov.i r1 =3D ar13 - mov.i r1 =3D ar14 - mov.i r1 =3D ar15 - mov.i r1 =3D ar16 - mov.i r1 =3D ar17 - mov.i r1 =3D ar18 - mov.i r1 =3D ar19 - mov.i r1 =3D ar20 - mov.i r1 =3D ar21 - mov.i r1 =3D ar22 - mov.i r1 =3D ar23 - mov.i r1 =3D ar24 - mov.i r1 =3D ar25 - mov.i r1 =3D ar26 - mov.i r1 =3D ar27 - mov.i r1 =3D ar28 - mov.i r1 =3D ar29 - mov.i r1 =3D ar30 - mov.i r1 =3D ar31 - mov.i r1 =3D ar32 - mov.i r1 =3D ar33 - mov.i r1 =3D ar34 - mov.i r1 =3D ar35 - mov.i r1 =3D ar36 - mov.i r1 =3D ar37 - mov.i r1 =3D ar38 - mov.i r1 =3D ar39 - mov.i r1 =3D ar40 - mov.i r1 =3D ar41 - mov.i r1 =3D ar42 - mov.i r1 =3D ar43 - mov.i r1 =3D ar44 - mov.i r1 =3D ar45 - mov.i r1 =3D ar46 - mov.i r1 =3D ar47 - -// AR 48 to 63 can be accessed by I or M units. - -// AR 64 to AR 111 can be accessed only by I unit. - mov.m r1 =3D ar64 - mov.m r1 =3D ar65 - mov.m r1 =3D ar66 - mov.m r1 =3D ar67 - mov.m r1 =3D ar68 - mov.m r1 =3D ar69 - mov.m r1 =3D ar70 - mov.m r1 =3D ar71 - mov.m r1 =3D ar72 - mov.m r1 =3D ar73 - mov.m r1 =3D ar74 - mov.m r1 =3D ar75 - mov.m r1 =3D ar76 - mov.m r1 =3D ar77 - mov.m r1 =3D ar78 - mov.m r1 =3D ar79 - mov.m r1 =3D ar80 - mov.m r1 =3D ar81 - mov.m r1 =3D ar82 - mov.m r1 =3D ar83 - mov.m r1 =3D ar84 - mov.m r1 =3D ar85 - mov.m r1 =3D ar86 - mov.m r1 =3D ar87 - mov.m r1 =3D ar88 - mov.m r1 =3D ar89 - mov.m r1 =3D ar90 - mov.m r1 =3D ar91 - mov.m r1 =3D ar92 - mov.m r1 =3D ar93 - mov.m r1 =3D ar94 - mov.m r1 =3D ar95 - mov.m r1 =3D ar96 - mov.m r1 =3D ar97 - mov.m r1 =3D ar98 - mov.m r1 =3D ar99 - mov.m r1 =3D ar100 - mov.m r1 =3D ar101 - mov.m r1 =3D ar102 - mov.m r1 =3D ar103 - mov.m r1 =3D ar104 - mov.m r1 =3D ar105 - mov.m r1 =3D ar106 - mov.m r1 =3D ar107 - mov.m r1 =3D ar108 - mov.m r1 =3D ar109 - mov.m r1 =3D ar110 - mov.m r1 =3D ar111 - -// AR 112 to 127 can be accessed by I or M units. - -// AR K0 to AR ITC can be accessed only by M unit. - mov.i r1 =3D ar.k0 - mov.i r1 =3D ar.k1 - mov.i r1 =3D ar.k2 - mov.i r1 =3D ar.k3 - mov.i r1 =3D ar.k4 - mov.i r1 =3D ar.k5 - mov.i r1 =3D ar.k6 - mov.i r1 =3D ar.k7 - mov.i r1 =3D ar.rsc - mov.i r1 =3D ar.bsp - mov.i r1 =3D ar.bspstore - mov.i r1 =3D ar.rnat - mov.i r1 =3D ar.fcr - mov.i r1 =3D ar.eflag - mov.i r1 =3D ar.csd - mov.i r1 =3D ar.ssd - mov.i r1 =3D ar.cflg - mov.i r1 =3D ar.fsr - mov.i r1 =3D ar.fir - mov.i r1 =3D ar.fdr - mov.i r1 =3D ar.ccv - mov.i r1 =3D ar.unat - mov.i r1 =3D ar.fpsr - mov.i r1 =3D ar.itc - mov.i r1 =3D ar.ruc - -// AR PFS, LC and EC can be accessed only by I unit. - mov.m r1 =3D ar.pfs - mov.m r1 =3D ar.lc - mov.m r1 =3D ar.ec diff --git a/gas/testsuite/gas/ia64/label.l b/gas/testsuite/gas/ia64/label.l deleted file mode 100644 index 89eba5926e7..00000000000 --- a/gas/testsuite/gas/ia64/label.l +++ /dev/null @@ -1,3 +0,0 @@ -.*: Assembler messages: -.*:12: Error: Label must be first in a bundle -.*:19: Error: Label must be first in a bundle diff --git a/gas/testsuite/gas/ia64/label.s b/gas/testsuite/gas/ia64/label.s deleted file mode 100644 index dbe5c38ec95..00000000000 --- a/gas/testsuite/gas/ia64/label.s +++ /dev/null @@ -1,26 +0,0 @@ -.explicit -start: -{.mii -label0: - nop 0 - nop 0 - nop 0 -} -{.mii - nop 0 -label1: - nop 0 - nop 0 -} -{.mii - nop 0 - nop 0 -label2: - nop 0 -} -{.mii - nop 0 - nop 0 - nop 0 -label3: -} diff --git a/gas/testsuite/gas/ia64/last.l b/gas/testsuite/gas/ia64/last.l deleted file mode 100644 index 946b4d2e080..00000000000 --- a/gas/testsuite/gas/ia64/last.l +++ /dev/null @@ -1,3 +0,0 @@ -.*: Assembler messages: -.*:4: Error: .* must be last in instruction group -.*:10: Error: .* must be last in instruction group diff --git a/gas/testsuite/gas/ia64/last.s b/gas/testsuite/gas/ia64/last.s deleted file mode 100644 index d7b0de0b00a..00000000000 --- a/gas/testsuite/gas/ia64/last.s +++ /dev/null @@ -1,12 +0,0 @@ -.explicit -_start: -{.mib - itc.d r0 -} ;; -{.mib - cover -} ;; -{.mbb - cover - nop 0 -} ;; diff --git a/gas/testsuite/gas/ia64/ldxmov-1.d b/gas/testsuite/gas/ia64/ldx= mov-1.d deleted file mode 100644 index 0676d10cdd8..00000000000 --- a/gas/testsuite/gas/ia64/ldxmov-1.d +++ /dev/null @@ -1,19 +0,0 @@ -#as: -mtune=3Ditanium1 -#objdump: -dr -#name: ia64 ldxmov-1 - -.*: +file format .* - -Disassembly of section \.text: - -0+000 <\.text>: - 0: 18 10 00 06 18 10 \[MMB\] ld8 r2=3D\[r3\] - 0: LDXMOV foo - 1: LDXMOV \.data - 6: 40 00 14 30 20 00 ld8 r4=3D\[r5\] - c: 00 00 00 20 nop\.b 0x0 - 10: 19 30 00 0e 18 10 \[MMB\] ld8 r6=3D\[r7\] - 10: LDXMOV foo\+0x64 - 11: LDXMOV \.data\+0x64 - 16: 80 00 24 30 20 00 ld8 r8=3D\[r9\] - 1c: 00 00 00 20 nop.b 0x0;; diff --git a/gas/testsuite/gas/ia64/ldxmov-1.s b/gas/testsuite/gas/ia64/ldx= mov-1.s deleted file mode 100644 index ab501024768..00000000000 --- a/gas/testsuite/gas/ia64/ldxmov-1.s +++ /dev/null @@ -1,8 +0,0 @@ - .text - ld8.mov r2 =3D [r3], foo# - ld8.mov r4 =3D [r5], bar# - ld8.mov r6 =3D [r7], foo# + 100 - ld8.mov r8 =3D [r9], bar# + 100 -=09 - .data -bar: diff --git a/gas/testsuite/gas/ia64/ldxmov-2.l b/gas/testsuite/gas/ia64/ldx= mov-2.l deleted file mode 100644 index 1334cf47b92..00000000000 --- a/gas/testsuite/gas/ia64/ldxmov-2.l +++ /dev/null @@ -1,5 +0,0 @@ -.*: Assembler messages: -.*:5: Warning: Use of 'ld8.mov' violates RAW dependency .*number is 2 -.*:4: Warning: This is the location of the conflicting usage -.*:8: Warning: Use of 'mov' violates RAW dependency .*number is 2 -.*:7: Warning: This is the location of the conflicting usage diff --git a/gas/testsuite/gas/ia64/ldxmov-2.s b/gas/testsuite/gas/ia64/ldx= mov-2.s deleted file mode 100644 index 991de1b00ad..00000000000 --- a/gas/testsuite/gas/ia64/ldxmov-2.s +++ /dev/null @@ -1,8 +0,0 @@ - .text - .explicit - - mov r2 =3D r0 - ld8.mov r3 =3D [r2], foo# - ;; - ld8.mov r2 =3D [r0], foo# - mov r3 =3D r2 diff --git a/gas/testsuite/gas/ia64/ltoff22x-1.d b/gas/testsuite/gas/ia64/l= toff22x-1.d deleted file mode 100644 index 94b2a20867b..00000000000 --- a/gas/testsuite/gas/ia64/ltoff22x-1.d +++ /dev/null @@ -1,10 +0,0 @@ -# objdump: -r -# name: ia64 ltoff22x-1 - -.*: +file format .* - -RELOCATION RECORDS FOR \[\.text\]: -OFFSET +TYPE +VALUE -0+000 LTOFF22X foo - - diff --git a/gas/testsuite/gas/ia64/ltoff22x-1.s b/gas/testsuite/gas/ia64/l= toff22x-1.s deleted file mode 100644 index d7be940c7bd..00000000000 --- a/gas/testsuite/gas/ia64/ltoff22x-1.s +++ /dev/null @@ -1,4 +0,0 @@ - .text - addl r3 =3D @ltoffx(foo#), gp - nop.i 0 - nop.i 0 diff --git a/gas/testsuite/gas/ia64/ltoff22x-2.d b/gas/testsuite/gas/ia64/l= toff22x-2.d deleted file mode 100644 index a16ddf376ed..00000000000 --- a/gas/testsuite/gas/ia64/ltoff22x-2.d +++ /dev/null @@ -1,11 +0,0 @@ -# objdump: -r -# name: ia64 ltoff22x-2 - -.*: +file format .* - -RELOCATION RECORDS FOR \[\.text\]: -OFFSET +TYPE +VALUE -0+000 LTOFF22X foo -0+010 LDXMOV foo - - diff --git a/gas/testsuite/gas/ia64/ltoff22x-2.s b/gas/testsuite/gas/ia64/l= toff22x-2.s deleted file mode 100644 index cbd27f2819c..00000000000 --- a/gas/testsuite/gas/ia64/ltoff22x-2.s +++ /dev/null @@ -1,13 +0,0 @@ - .global foo# - foo# =3D bar# - .global bar# - .data -bar: - data4 0 - .text - addl r3 =3D @ltoffx(foo#), gp - nop.i 0 - nop.i 0 - ld8.mov r3 =3D [r3], foo# - nop.i 0 - nop.i 0 diff --git a/gas/testsuite/gas/ia64/ltoff22x-3.d b/gas/testsuite/gas/ia64/l= toff22x-3.d deleted file mode 100644 index e30551e6fd3..00000000000 --- a/gas/testsuite/gas/ia64/ltoff22x-3.d +++ /dev/null @@ -1,11 +0,0 @@ -# objdump: -r -# name: ia64 ltoff22x-3 - -.*: +file format .* - -RELOCATION RECORDS FOR \[\.text\]: -OFFSET +TYPE +VALUE -0+000 LTOFF22X foo -0+010 LDXMOV foo - - diff --git a/gas/testsuite/gas/ia64/ltoff22x-3.s b/gas/testsuite/gas/ia64/l= toff22x-3.s deleted file mode 100644 index f0ebd10258e..00000000000 --- a/gas/testsuite/gas/ia64/ltoff22x-3.s +++ /dev/null @@ -1,13 +0,0 @@ - .global bar# - .data -bar: - data4 0 - .global foo# - foo# =3D bar# - .text - addl r3 =3D @ltoffx(foo#), gp - nop.i 0 - nop.i 0 - ld8.mov r3 =3D [r3], foo# - nop.i 0 - nop.i 0 diff --git a/gas/testsuite/gas/ia64/ltoff22x-4.d b/gas/testsuite/gas/ia64/l= toff22x-4.d deleted file mode 100644 index 29f17b8951a..00000000000 --- a/gas/testsuite/gas/ia64/ltoff22x-4.d +++ /dev/null @@ -1,11 +0,0 @@ -# objdump: -r -# name: ia64 ltoff22x-4 - -.*: +file format .* - -RELOCATION RECORDS FOR \[\.text\]: -OFFSET +TYPE +VALUE -0+000 LTOFF22X foo -0+010 LDXMOV foo - - diff --git a/gas/testsuite/gas/ia64/ltoff22x-4.s b/gas/testsuite/gas/ia64/l= toff22x-4.s deleted file mode 100644 index fa43f34682d..00000000000 --- a/gas/testsuite/gas/ia64/ltoff22x-4.s +++ /dev/null @@ -1,13 +0,0 @@ - .text - addl r3 =3D @ltoffx(foo#), gp - nop.i 0 - nop.i 0 - ld8.mov r3 =3D [r3], foo# - nop.i 0 - nop.i 0 - .global foo# - foo# =3D bar# - .global bar# - .data -bar: - data4 0 diff --git a/gas/testsuite/gas/ia64/ltoff22x-5.d b/gas/testsuite/gas/ia64/l= toff22x-5.d deleted file mode 100644 index e9016cd62b5..00000000000 --- a/gas/testsuite/gas/ia64/ltoff22x-5.d +++ /dev/null @@ -1,11 +0,0 @@ -# objdump: -r -# name: ia64 ltoff22x-5 - -.*: +file format .* - -RELOCATION RECORDS FOR \[\.text\]: -OFFSET +TYPE +VALUE -0+000 LTOFF22X foo -0+010 LDXMOV foo - - diff --git a/gas/testsuite/gas/ia64/ltoff22x-5.s b/gas/testsuite/gas/ia64/l= toff22x-5.s deleted file mode 100644 index a6c5137b96f..00000000000 --- a/gas/testsuite/gas/ia64/ltoff22x-5.s +++ /dev/null @@ -1,13 +0,0 @@ - .text - addl r3 =3D @ltoffx(foo#), gp - nop.i 0 - nop.i 0 - ld8.mov r3 =3D [r3], foo# - nop.i 0 - nop.i 0 - .global bar# - .data -bar: - data4 0 - .global foo# - foo# =3D bar# diff --git a/gas/testsuite/gas/ia64/mov-ar.d b/gas/testsuite/gas/ia64/mov-a= r.d deleted file mode 100644 index ec7cb61548b..00000000000 --- a/gas/testsuite/gas/ia64/mov-ar.d +++ /dev/null @@ -1,26 +0,0 @@ -# objdump: -d -# name: ia64 app reg moves - -.*: +file format .* - -Disassembly of section \.text: - -0+0 <_start>: -[[:space:]]*[[:xdigit:]]*:[[:space:][:xdigit:]]+\[MFI\][[:space:]]+mov\.m = ar.k0=3Dr0 -[[:space:]]*[[:xdigit:]]*:[[:space:][:xdigit:]]+nop\.f 0x0 -[[:space:]]*[[:xdigit:]]*:[[:space:][:xdigit:]]+mov\.i ar127=3Dr0;; -[[:space:]]*[[:xdigit:]]*:[[:space:][:xdigit:]]+\[MFI\][[:space:]]+mov\.m = ar47=3Dr0 -[[:space:]]*[[:xdigit:]]*:[[:space:][:xdigit:]]+nop\.f 0x0 -[[:space:]]*[[:xdigit:]]*:[[:space:][:xdigit:]]+mov\.i ar112=3Dr0;; -[[:space:]]*[[:xdigit:]]*:[[:space:][:xdigit:]]+\[MFI\][[:space:]]+mov\.m = ar48=3Dr0 -[[:space:]]*[[:xdigit:]]*:[[:space:][:xdigit:]]+nop\.f 0x0 -[[:space:]]*[[:xdigit:]]*:[[:space:][:xdigit:]]+mov\.i ar111=3Dr0;; -[[:space:]]*[[:xdigit:]]*:[[:space:][:xdigit:]]+\[MFI\][[:space:]]+mov\.m = ar63=3Dr0 -[[:space:]]*[[:xdigit:]]*:[[:space:][:xdigit:]]+nop\.f 0x0 -[[:space:]]*[[:xdigit:]]*:[[:space:][:xdigit:]]+mov\.i ar.pfs=3Dr0;; -[[:space:]]*[[:xdigit:]]*:[[:space:][:xdigit:]]+\[MFI\][[:space:]]+mov\.m = ar112=3Dr0 -[[:space:]]*[[:xdigit:]]*:[[:space:][:xdigit:]]+nop\.f 0x0 -[[:space:]]*[[:xdigit:]]*:[[:space:][:xdigit:]]+mov\.i ar63=3Dr0;; -[[:space:]]*[[:xdigit:]]*:[[:space:][:xdigit:]]+\[MFI\][[:space:]]+mov\.m = ar127=3Dr0 -[[:space:]]*[[:xdigit:]]*:[[:space:][:xdigit:]]+nop\.f 0x0 -[[:space:]]*[[:xdigit:]]*:[[:space:][:xdigit:]]+mov\.i ar48=3Dr0;; diff --git a/gas/testsuite/gas/ia64/mov-ar.s b/gas/testsuite/gas/ia64/mov-a= r.s deleted file mode 100644 index 79780d940bc..00000000000 --- a/gas/testsuite/gas/ia64/mov-ar.s +++ /dev/null @@ -1,21 +0,0 @@ -.explicit -_start: -{.mfi - mov ar0 =3D r0 - mov ar127 =3D r0 -} ;; {.mfi - mov ar47 =3D r0 - mov ar112 =3D r0 -} ;; {.mfi - mov ar48 =3D r0 - mov ar111 =3D r0 -} ;; {.mfi - mov ar63 =3D r0 - mov ar64 =3D r0 -} ;; {.mfi - mov ar112 =3D r0 - mov ar63 =3D r0 -} ;; {.mfi - mov ar127 =3D r0 - mov ar48 =3D r0 -} ;; diff --git a/gas/testsuite/gas/ia64/no-fit.l b/gas/testsuite/gas/ia64/no-fi= t.l deleted file mode 100644 index 1dec89c8673..00000000000 --- a/gas/testsuite/gas/ia64/no-fit.l +++ /dev/null @@ -1,8 +0,0 @@ -.*: Assembler messages: -.*:5: Error: .nop\.i.[[:space:]]+[^23]*[[:space:]]+MFB[[:space:]]+.* -.*:8: Error: .nop\.f.[[:space:]]+[^23]*[[:space:]]+MLX[[:space:]]+.* -.*:12: Error: .nop\.i.[[:space:]]+.*[[:space:]]+2[[:space:]]+.*[[:space:]]= +3[[:space:]]+.*[[:space:]]+MFB[[:space:]]+.* -.*:17: Error: .nop\.i.[[:space:]]+[^2]*[[:space:]]+3[[:space:]]+.*[[:space= :]]+MFB[[:space:]]+.* -.*:21: Error: .nop\.f.[[:space:]]+.*[[:space:]]+X[[:space:]]+.*[[:space:]]= +MLX[[:space:]]+.* -.*:27: Error: .nop.[[:space:]]+[^23M]* -.*:32: Error: .nop.[[:space:]]+[^23M]* diff --git a/gas/testsuite/gas/ia64/no-fit.s b/gas/testsuite/gas/ia64/no-fi= t.s deleted file mode 100644 index dc992a5ef8e..00000000000 --- a/gas/testsuite/gas/ia64/no-fit.s +++ /dev/null @@ -1,33 +0,0 @@ -.explicit -.text -_start: -{.mfb - nop.i 0 -} -{.mlx - nop.f 0 -} -{.mfb - nop.m 0 - nop.i 0 -} -{.mfb - nop.m 0 - nop.f 0 - nop.i 0 -} -{.mlx - nop.m 0 - nop.f 0 -} -{.mfb - nop 0 - nop 0 - nop 0 - nop 0 -} -{.mlx - nop 0 - nop 0 - nop 0 -} diff --git a/gas/testsuite/gas/ia64/nop_x.d b/gas/testsuite/gas/ia64/nop_x.d deleted file mode 100644 index add14148857..00000000000 --- a/gas/testsuite/gas/ia64/nop_x.d +++ /dev/null @@ -1,11 +0,0 @@ -# objdump: -d -# name: ia64 nop.x pseudo - -.*: +file format .* - -Disassembly of section \.text: - -0+0 <_start>: -[[:space:]]*[[:xdigit:]]*:[[:space:][:xdigit:]]+\[MLX][[:space:]]+nop.m 0x0 -[[:space:]]*[[:xdigit:]]*:[[:space:][:xdigit:]]+nop.x 0x0;; -[[:space:]]*[[:xdigit:]]*:[[:space:][:xdigit:]]+ diff --git a/gas/testsuite/gas/ia64/nop_x.s b/gas/testsuite/gas/ia64/nop_x.s deleted file mode 100644 index 61265b39fd7..00000000000 --- a/gas/testsuite/gas/ia64/nop_x.s +++ /dev/null @@ -1,6 +0,0 @@ -.explicit -_start: -{.mlx - nop 0 - nop 0 -} ;; diff --git a/gas/testsuite/gas/ia64/nostkreg.d b/gas/testsuite/gas/ia64/nos= tkreg.d deleted file mode 100644 index e1eee70b597..00000000000 --- a/gas/testsuite/gas/ia64/nostkreg.d +++ /dev/null @@ -1,16 +0,0 @@ -#objdump: -dr -#name: ia64 not stacked registers - -.*: +file format .* - -Disassembly of section \.text: - -0+000 <_start>: -[[:space:]]*[[:xdigit:]]+:[[:space:][:xdigit:]]+\[M[IM]I\][[:space:]]+mov[= [:space:]]+r5=3D0 -[[:space:]]+0:[[:space:]]+IMM22[[:space:]]+in00 -[[:space:]]+1:[[:space:]]+IMM22[[:space:]]+loc96 -[[:space:]]*[[:xdigit:]]+:[[:space:][:xdigit:]]+mov[[:space:]]+r6=3D0 -[[:space:]]*[[:xdigit:]]+:[[:space:][:xdigit:]]+mov[[:space:]]+r7=3Dr32 -[[:space:]]*[[:xdigit:]]+:[[:space:][:xdigit:]]+\[M[IM]B\][[:space:]]+mov[= [:space:]]+r8=3Dr34 -[[:space:]]*[[:xdigit:]]+:[[:space:][:xdigit:]]+mov[[:space:]]+r9=3Dr36 -[[:space:]]*[[:xdigit:]]+:[[:space:][:xdigit:]]+br\.ret\.sptk\.few[[:space= :]]+(b0|rp);; diff --git a/gas/testsuite/gas/ia64/nostkreg.s b/gas/testsuite/gas/ia64/nos= tkreg.s deleted file mode 100644 index ecdba2bd0cc..00000000000 --- a/gas/testsuite/gas/ia64/nostkreg.s +++ /dev/null @@ -1,9 +0,0 @@ -_start: - mov r5 =3D in00 - mov r6 =3D loc96 - .regstk 2, 6, 2, 8 - .rotr in0I[2], loc1L[2], out2O[2] - mov r7 =3D in0I[0] - mov r8 =3D loc1L[0] - mov r9 =3D out2O[0] - br.ret.sptk rp diff --git a/gas/testsuite/gas/ia64/opc-a-err.l b/gas/testsuite/gas/ia64/op= c-a-err.l deleted file mode 100644 index 167659fe4a3..00000000000 --- a/gas/testsuite/gas/ia64/opc-a-err.l +++ /dev/null @@ -1,18 +0,0 @@ -.*: Assembler messages: -.*:1: Error: Operand 2 of `adds' should be a 14-bit .* -.*:2: Error: Operand 2 of `adds' should be a 14-bit .* -.*:4: Error: Operand 2 of `addl' should be a 22-bit .* -.*:5: Error: Operand 2 of `addl' should be a 22-bit .* -.*:6: Error: Operand 3 of `addl' should be a general register r0-r3 -.*:8: Error: Operand 2 of `sub' should be .* -.*:9: Error: Operand 2 of `sub' should be .* -.*:11: Error: Operand 2 of `and' should be .* -.*:12: Error: Operand 2 of `and' should be .* -.*:14: Error: Operand 2 of `or' should be .* -.*:15: Error: Operand 2 of `or' should be .* -.*:17: Error: Operand 2 of `xor' should be .* -.*:18: Error: Operand 2 of `xor' should be .* -.*:20: Error: Operand 2 of `andcm' should be .* -.*:21: Error: Operand 2 of `andcm' should be .* -.*:23: Error: Operand [34] of `cmp4.lt.or' should be r0 -.*:24: Error: Operand [34] of `cmp4.lt.or' should be r0 diff --git a/gas/testsuite/gas/ia64/opc-a-err.s b/gas/testsuite/gas/ia64/op= c-a-err.s deleted file mode 100644 index 136fb26b819..00000000000 --- a/gas/testsuite/gas/ia64/opc-a-err.s +++ /dev/null @@ -1,24 +0,0 @@ - adds r25 =3D -0x2001, r10 - adds r26 =3D 0x2000, r10 - - addl r37 =3D -0x200001, r1 - addl r38 =3D 0x200000, r1 - addl r30 =3D 0, r10 - - sub r2 =3D 128, r3 - sub r3 =3D -129, r4 - - and r8 =3D 129, r9 - and r3 =3D -129, r4 -=09 - or r8 =3D 129, r9 - or r3 =3D -129, r4 -=09 - xor r8 =3D 129, r9 - xor r3 =3D -129, r4 -=09 - andcm r8 =3D 129, r9 - andcm r3 =3D -129, r4 - - cmp4.lt.or p2, p3 =3D r1, r4 - cmp4.lt.or p2, p3 =3D 1, r4 diff --git a/gas/testsuite/gas/ia64/opc-a.d b/gas/testsuite/gas/ia64/opc-a.d deleted file mode 100644 index ed599bd266d..00000000000 --- a/gas/testsuite/gas/ia64/opc-a.d +++ /dev/null @@ -1,363 +0,0 @@ -# as: -xnone -# objdump: -d -# name: ia64 opc-a - -.*: +file format .* - -Disassembly of section \.text: - -0+000 <_start>: - 0: 00 28 9b cf 00 60 \[MII\] add r101=3Dr102,r103 - 6: 80 4e ab 01 40 60 \(p01\) add r104=3Dr105,r106 - c: cd 6e 07 80 add r107=3Dr108,r109,1 - 10: 40 70 bf e1 01 20 \[MII\] \(p02\) add r110=3Dr111,r112,1 - 16: 40 01 28 00 c2 a0 mov r20=3Dr10 - 1c: 12 50 00 84 \(p01\) adds r21=3D1,r10 - 20: 00 b0 fc 15 3f 23 \[MII\] adds r22=3D-1,r10 - 26: 70 01 28 00 46 01 adds r23=3D-8192,r10 - 2c: f3 57 fc 84 \(p02\) adds r24=3D8191,r10 - 30: 00 f0 00 02 00 24 \[MII\] addl r30=3D0,r1 - 36: f0 09 04 00 c8 00 addl r31=3D1,r1 - 3c: f4 ef ff 9f \(p01\) addl r32=3D-1,r1 - 40: 00 08 01 fa c0 27 \[MII\] addl r33=3D-8192,r1 - 46: 20 fa 07 7e 48 60 addl r34=3D8191,r1 - 4c: 04 08 00 98 addl r35=3D-2097152,r1 - 50: 00 20 fd fb ff 25 \[MII\] addl r36=3D2097151,r1 - 56: b0 00 28 00 42 80 mov r11=3Dr10 - 5c: 41 53 90 84 adds r12=3D4660,r10 - 60: 00 68 d0 02 24 24 \[MII\] addl r13=3D4660,r1 - 66: e0 28 16 8c 48 80 addl r14=3D74565,r1 - 6c: 32 50 20 80 addp4 r20=3Dr3,r10 - 70: 20 a8 04 14 80 21 \[MII\] \(p01\) addp4 r21=3D1,r10 - 76: 60 f9 2b 7e 47 a0 addp4 r22=3D-1,r10 - 7c: 6c 3e 17 80 sub r101=3Dr102,r103 - 80: 40 70 bf e1 04 20 \[MII\] \(p02\) sub r110=3Dr111,r112,1 - 86: 80 07 0c 4a 40 20 sub r120=3D0,r3 - 8c: 1f 18 94 80 sub r121=3D1,r3 - 90: 00 d0 ff 07 25 22 \[MII\] sub r122=3D-1,r3 - 96: b0 07 0c 4a 44 80 sub r123=3D-128,r3 - 9c: ff 1f 94 80 sub r124=3D127,r3 - a0: 00 40 24 14 0c e0 \[MII\] and r8=3Dr9,r10 - a6: b0 00 30 58 44 02 \(p03\) and r11=3D-128,r12 - ac: 91 50 38 80 \(p04\) or r8=3Dr9,r10 - b0: 00 58 00 18 2e 22 \[MII\] or r11=3D-128,r12 - b6: 80 48 28 1e 40 60 xor r8=3Dr9,r10 - bc: 01 60 bc 88 xor r11=3D-128,r12 - c0: 00 40 24 14 0d 20 \[MII\] andcm r8=3Dr9,r10 - c6: b0 00 30 5a 44 00 andcm r11=3D-128,r12 - cc: e1 f9 40 80 shladd r8=3Dr30,1,r31 - d0: 00 48 78 3e 11 20 \[MII\] shladd r9=3Dr30,2,r31 - d6: a0 f0 7c 24 40 60 shladd r10=3Dr30,3,r31 - dc: e1 f9 4c 80 shladd r11=3Dr30,4,r31 - e0: 00 40 78 3e 18 20 \[MII\] shladdp4 r8=3Dr30,1,r31 - e6: 90 f0 7c 32 40 40 shladdp4 r9=3Dr30,2,r31 - ec: e1 f9 68 80 shladdp4 r10=3Dr30,3,r31 - f0: 00 58 78 3e 1b 20 \[MII\] shladdp4 r11=3Dr30,4,r31 - f6: a0 f0 7c 00 41 60 padd1 r10=3Dr30,r31 - fc: e1 f9 04 82 padd1\.sss r11=3Dr30,r31 - 100: 00 60 78 3e 83 20 \[MII\] padd1\.uus r12=3Dr30,r31 - 106: d0 f0 7c 04 41 c0 padd1\.uuu r13=3Dr30,r31 - 10c: e1 f9 00 83 padd2 r14=3Dr30,r31 - 110: 00 78 78 3e c1 20 \[MII\] padd2\.sss r15=3Dr30,r31 - 116: 00 f1 7c 86 41 20 padd2\.uus r16=3Dr30,r31 - 11c: e2 f9 08 83 padd2\.uuu r17=3Dr30,r31 - 120: 00 90 78 3e 80 22 \[MII\] padd4 r18=3Dr30,r31 - 126: a0 f0 7c 08 41 60 psub1 r10=3Dr30,r31 - 12c: e1 f9 14 82 psub1\.sss r11=3Dr30,r31 - 130: 00 60 78 3e 87 20 \[MII\] psub1\.uus r12=3Dr30,r31 - 136: d0 f0 7c 0c 41 c0 psub1\.uuu r13=3Dr30,r31 - 13c: e1 f9 10 83 psub2 r14=3Dr30,r31 - 140: 00 78 78 3e c5 20 \[MII\] psub2\.sss r15=3Dr30,r31 - 146: 00 f1 7c 8e 41 20 psub2\.uus r16=3Dr30,r31 - 14c: e2 f9 18 83 psub2\.uuu r17=3Dr30,r31 - 150: 00 90 78 3e 84 22 \[MII\] psub4 r18=3Dr30,r31 - 156: a0 f0 7c 14 41 40 pavg1 r10=3Dr30,r31 - 15c: e1 f9 2c 82 pavg1\.raz r10=3Dr30,r31 - 160: 00 50 78 3e ca 20 \[MII\] pavg2 r10=3Dr30,r31 - 166: a0 f0 7c 96 41 40 pavg2\.raz r10=3Dr30,r31 - 16c: e1 f9 38 82 pavgsub1 r10=3Dr30,r31 - 170: 00 50 78 3e ce 20 \[MII\] pavgsub2 r10=3Dr30,r31 - 176: a0 f0 7c 48 41 40 pcmp1\.eq r10=3Dr30,r31 - 17c: e1 f9 90 83 pcmp2\.eq r10=3Dr30,r31 - 180: 00 50 78 3e a4 22 \[MII\] pcmp4\.eq r10=3Dr30,r31 - 186: a0 f0 7c 4a 41 40 pcmp1\.gt r10=3Dr30,r31 - 18c: e1 f9 94 83 pcmp2\.gt r10=3Dr30,r31 - 190: 00 50 78 3e a5 22 \[MII\] pcmp4\.gt r10=3Dr30,r31 - 196: a0 58 30 a0 41 40 pshladd2 r10=3Dr11,1,r12 - 19c: b1 60 48 83 pshladd2 r10=3Dr11,3,r12 - 1a0: 00 50 2c 18 d8 20 \[MII\] pshradd2 r10=3Dr11,1,r12 - 1a6: a0 58 30 b2 41 40 pshradd2 r10=3Dr11,2,r12 - 1ac: 30 20 0c e0 cmp\.eq p2,p3=3Dr3,r4 - 1b0: 00 10 0c 08 03 39 \[MII\] cmp\.eq p2,p3=3D3,r4 - 1b6: 30 18 10 04 70 60 cmp\.eq p3,p2=3Dr3,r4 - 1bc: 30 20 08 e4 cmp\.eq p3,p2=3D3,r4 - 1c0: 00 10 0c 08 03 30 \[MII\] cmp\.lt p2,p3=3Dr3,r4 - 1c6: 20 18 10 06 62 60 cmp\.lt p2,p3=3D3,r4 - 1cc: 40 18 08 c0 cmp\.lt p3,p2=3Dr4,r3 - 1d0: 00 10 08 08 03 31 \[MII\] cmp\.lt p2,p3=3D2,r4 - 1d6: 20 20 0c 06 60 60 cmp\.lt p2,p3=3Dr4,r3 - 1dc: 20 20 08 c4 cmp\.lt p3,p2=3D2,r4 - 1e0: 00 18 0c 08 02 30 \[MII\] cmp\.lt p3,p2=3Dr3,r4 - 1e6: 30 18 10 04 62 40 cmp\.lt p3,p2=3D3,r4 - 1ec: 30 20 0c d0 cmp\.ltu p2,p3=3Dr3,r4 - 1f0: 00 10 0c 08 03 35 \[MII\] cmp\.ltu p2,p3=3D3,r4 - 1f6: 30 20 0c 04 68 40 cmp\.ltu p3,p2=3Dr4,r3 - 1fc: 20 20 0c d4 cmp\.ltu p2,p3=3D2,r4 - 200: 00 10 10 06 03 34 \[MII\] cmp\.ltu p2,p3=3Dr4,r3 - 206: 30 10 10 04 6a 60 cmp\.ltu p3,p2=3D2,r4 - 20c: 30 20 08 d0 cmp\.ltu p3,p2=3Dr3,r4 - 210: 00 18 0c 08 02 35 \[MII\] cmp\.ltu p3,p2=3D3,r4 - 216: 20 1c 10 06 70 40 cmp\.eq\.unc p2,p3=3Dr3,r4 - 21c: 38 20 0c e4 cmp\.eq\.unc p2,p3=3D3,r4 - 220: 00 18 0e 08 02 38 \[MII\] cmp\.eq\.unc p3,p2=3Dr3,r4 - 226: 30 1c 10 04 72 40 cmp\.eq\.unc p3,p2=3D3,r4 - 22c: 38 20 0c c0 cmp\.lt\.unc p2,p3=3Dr3,r4 - 230: 00 10 0e 08 03 31 \[MII\] cmp\.lt\.unc p2,p3=3D3,r4 - 236: 30 24 0c 04 60 40 cmp\.lt\.unc p3,p2=3Dr4,r3 - 23c: 28 20 0c c4 cmp\.lt\.unc p2,p3=3D2,r4 - 240: 00 10 12 06 03 30 \[MII\] cmp\.lt\.unc p2,p3=3Dr4,r3 - 246: 30 14 10 04 62 60 cmp\.lt\.unc p3,p2=3D2,r4 - 24c: 38 20 08 c0 cmp\.lt\.unc p3,p2=3Dr3,r4 - 250: 00 18 0e 08 02 31 \[MII\] cmp\.lt\.unc p3,p2=3D3,r4 - 256: 20 1c 10 06 68 40 cmp\.ltu\.unc p2,p3=3Dr3,r4 - 25c: 38 20 0c d4 cmp\.ltu\.unc p2,p3=3D3,r4 - 260: 00 18 12 06 02 34 \[MII\] cmp\.ltu\.unc p3,p2=3Dr4,r3 - 266: 20 14 10 06 6a 40 cmp\.ltu\.unc p2,p3=3D2,r4 - 26c: 48 18 0c d0 cmp\.ltu\.unc p2,p3=3Dr4,r3 - 270: 00 18 0a 08 02 35 \[MII\] cmp\.ltu\.unc p3,p2=3D2,r4 - 276: 30 1c 10 04 68 60 cmp\.ltu\.unc p3,p2=3Dr3,r4 - 27c: 38 20 08 d4 cmp\.ltu\.unc p3,p2=3D3,r4 - 280: 00 10 0c 08 43 30 \[MII\] cmp\.eq\.and p2,p3=3Dr3,r4 - 286: 20 18 10 86 62 40 cmp\.eq\.and p2,p3=3D3,r4 - 28c: 30 20 0c d1 cmp\.eq\.or p2,p3=3Dr3,r4 - 290: 00 10 0c 08 43 35 \[MII\] cmp\.eq\.or p2,p3=3D3,r4 - 296: 20 18 10 86 70 40 cmp\.eq\.or\.andcm p2,p3=3Dr3,r4 - 29c: 30 20 0c e5 cmp\.eq\.or\.andcm p2,p3=3D3,r4 - 2a0: 00 10 0e 08 43 34 \[MII\] cmp\.ne\.or p2,p3=3Dr3,r4 - 2a6: 20 1c 10 86 6a 40 cmp\.ne\.or p2,p3=3D3,r4 - 2ac: 38 20 0c c1 cmp\.ne\.and p2,p3=3Dr3,r4 - 2b0: 00 10 0e 08 43 31 \[MII\] cmp\.ne\.and p2,p3=3D3,r4 - 2b6: 30 1c 10 84 70 60 cmp\.ne\.or\.andcm p3,p2=3Dr3,r4 - 2bc: 38 20 08 e5 cmp\.ne\.or\.andcm p3,p2=3D3,r4 - 2c0: 00 10 0e 08 43 30 \[MII\] cmp\.ne\.and p2,p3=3Dr3,r4 - 2c6: 20 1c 10 86 62 40 cmp\.ne\.and p2,p3=3D3,r4 - 2cc: 38 20 0c d1 cmp\.ne\.or p2,p3=3Dr3,r4 - 2d0: 00 10 0e 08 43 35 \[MII\] cmp\.ne\.or p2,p3=3D3,r4 - 2d6: 20 1c 10 86 70 40 cmp\.ne\.or\.andcm p2,p3=3Dr3,r4 - 2dc: 38 20 0c e5 cmp\.ne\.or\.andcm p2,p3=3D3,r4 - 2e0: 00 10 0c 08 43 34 \[MII\] cmp\.eq\.or p2,p3=3Dr3,r4 - 2e6: 20 18 10 86 6a 40 cmp\.eq\.or p2,p3=3D3,r4 - 2ec: 30 20 0c c1 cmp\.eq\.and p2,p3=3Dr3,r4 - 2f0: 00 10 0c 08 43 31 \[MII\] cmp\.eq\.and p2,p3=3D3,r4 - 2f6: 30 18 10 84 70 60 cmp\.eq\.or\.andcm p3,p2=3Dr3,r4 - 2fc: 30 20 08 e5 cmp\.eq\.or\.andcm p3,p2=3D3,r4 - 300: 00 10 00 08 43 30 \[MII\] cmp\.eq\.and p2,p3=3Dr0,r4 - 306: 20 20 00 86 60 40 cmp\.eq\.and p2,p3=3Dr4,r0 - 30c: 00 20 0c d1 cmp\.eq\.or p2,p3=3Dr0,r4 - 310: 00 10 10 00 43 34 \[MII\] cmp\.eq\.or p2,p3=3Dr4,r0 - 316: 20 00 10 86 70 40 cmp\.eq\.or\.andcm p2,p3=3Dr0,r4 - 31c: 40 00 0c e1 cmp\.eq\.or\.andcm p2,p3=3Dr4,r0 - 320: 00 10 02 08 43 34 \[MII\] cmp\.ne\.or p2,p3=3Dr0,r4 - 326: 20 24 00 86 68 40 cmp\.ne\.or p2,p3=3Dr4,r0 - 32c: 08 20 0c c1 cmp\.ne\.and p2,p3=3Dr0,r4 - 330: 00 10 12 00 43 30 \[MII\] cmp\.ne\.and p2,p3=3Dr4,r0 - 336: 30 04 10 84 70 60 cmp\.ne\.or\.andcm p3,p2=3Dr0,r4 - 33c: 48 00 08 e1 cmp\.ne\.or\.andcm p3,p2=3Dr4,r0 - 340: 00 10 02 08 43 30 \[MII\] cmp\.ne\.and p2,p3=3Dr0,r4 - 346: 20 24 00 86 60 40 cmp\.ne\.and p2,p3=3Dr4,r0 - 34c: 08 20 0c d1 cmp\.ne\.or p2,p3=3Dr0,r4 - 350: 00 10 12 00 43 34 \[MII\] cmp\.ne\.or p2,p3=3Dr4,r0 - 356: 20 04 10 86 70 40 cmp\.ne\.or\.andcm p2,p3=3Dr0,r4 - 35c: 48 00 0c e1 cmp\.ne\.or\.andcm p2,p3=3Dr4,r0 - 360: 00 10 00 08 43 34 \[MII\] cmp\.eq\.or p2,p3=3Dr0,r4 - 366: 20 20 00 86 68 40 cmp\.eq\.or p2,p3=3Dr4,r0 - 36c: 00 20 0c c1 cmp\.eq\.and p2,p3=3Dr0,r4 - 370: 00 10 10 00 43 30 \[MII\] cmp\.eq\.and p2,p3=3Dr4,r0 - 376: 30 00 10 84 70 60 cmp\.eq\.or\.andcm p3,p2=3Dr0,r4 - 37c: 40 00 08 e1 cmp\.eq\.or\.andcm p3,p2=3Dr4,r0 - 380: 00 10 02 08 43 32 \[MII\] cmp\.lt\.and p2,p3=3Dr0,r4 - 386: 20 00 10 06 64 40 cmp\.gt\.and p2,p3=3Dr0,r4 - 38c: 08 20 0c d9 cmp\.lt\.or p2,p3=3Dr0,r4 - 390: 00 10 00 08 03 36 \[MII\] cmp\.gt\.or p2,p3=3Dr0,r4 - 396: 20 04 10 86 74 40 cmp\.lt\.or\.andcm p2,p3=3Dr0,r4 - 39c: 00 20 0c e8 cmp\.gt\.or\.andcm p2,p3=3Dr0,r4 - 3a0: 00 10 00 08 43 36 \[MII\] cmp\.ge\.or p2,p3=3Dr0,r4 - 3a6: 20 04 10 06 6c 40 cmp\.le\.or p2,p3=3Dr0,r4 - 3ac: 00 20 0c c9 cmp\.ge\.and p2,p3=3Dr0,r4 - 3b0: 00 10 02 08 03 32 \[MII\] cmp\.le\.and p2,p3=3Dr0,r4 - 3b6: 30 00 10 84 74 60 cmp\.ge\.or\.andcm p3,p2=3Dr0,r4 - 3bc: 08 20 08 e8 cmp\.le\.or\.andcm p3,p2=3Dr0,r4 - 3c0: 00 10 02 08 03 32 \[MII\] cmp\.le\.and p2,p3=3Dr0,r4 - 3c6: 20 00 10 86 64 40 cmp\.ge\.and p2,p3=3Dr0,r4 - 3cc: 08 20 0c d8 cmp\.le\.or p2,p3=3Dr0,r4 - 3d0: 00 10 00 08 43 36 \[MII\] cmp\.ge\.or p2,p3=3Dr0,r4 - 3d6: 20 04 10 06 74 40 cmp\.le\.or\.andcm p2,p3=3Dr0,r4 - 3dc: 00 20 0c e9 cmp\.ge\.or\.andcm p2,p3=3Dr0,r4 - 3e0: 00 10 00 08 03 36 \[MII\] cmp\.gt\.or p2,p3=3Dr0,r4 - 3e6: 20 04 10 86 6c 40 cmp\.lt\.or p2,p3=3Dr0,r4 - 3ec: 00 20 0c c8 cmp\.gt\.and p2,p3=3Dr0,r4 - 3f0: 00 10 02 08 43 32 \[MII\] cmp\.lt\.and p2,p3=3Dr0,r4 - 3f6: 30 00 10 04 74 60 cmp\.gt\.or\.andcm p3,p2=3Dr0,r4 - 3fc: 08 20 08 e9 cmp\.lt\.or\.andcm p3,p2=3Dr0,r4 - 400: 00 10 00 08 03 32 \[MII\] cmp\.gt\.and p2,p3=3Dr0,r4 - 406: 20 04 10 86 64 40 cmp\.lt\.and p2,p3=3Dr0,r4 - 40c: 00 20 0c d8 cmp\.gt\.or p2,p3=3Dr0,r4 - 410: 00 10 02 08 43 36 \[MII\] cmp\.lt\.or p2,p3=3Dr0,r4 - 416: 20 00 10 06 74 40 cmp\.gt\.or\.andcm p2,p3=3Dr0,r4 - 41c: 08 20 0c e9 cmp\.lt\.or\.andcm p2,p3=3Dr0,r4 - 420: 00 10 02 08 03 36 \[MII\] cmp\.le\.or p2,p3=3Dr0,r4 - 426: 20 00 10 86 6c 40 cmp\.ge\.or p2,p3=3Dr0,r4 - 42c: 08 20 0c c8 cmp\.le\.and p2,p3=3Dr0,r4 - 430: 00 10 00 08 43 32 \[MII\] cmp\.ge\.and p2,p3=3Dr0,r4 - 436: 30 04 10 04 74 60 cmp\.le\.or\.andcm p3,p2=3Dr0,r4 - 43c: 00 20 08 e9 cmp\.ge\.or\.andcm p3,p2=3Dr0,r4 - 440: 00 10 00 08 43 32 \[MII\] cmp\.ge\.and p2,p3=3Dr0,r4 - 446: 20 04 10 06 64 40 cmp\.le\.and p2,p3=3Dr0,r4 - 44c: 00 20 0c d9 cmp\.ge\.or p2,p3=3Dr0,r4 - 450: 00 10 02 08 03 36 \[MII\] cmp\.le\.or p2,p3=3Dr0,r4 - 456: 20 00 10 86 74 40 cmp\.ge\.or\.andcm p2,p3=3Dr0,r4 - 45c: 08 20 0c e8 cmp\.le\.or\.andcm p2,p3=3Dr0,r4 - 460: 00 10 02 08 43 36 \[MII\] cmp\.lt\.or p2,p3=3Dr0,r4 - 466: 20 00 10 06 6c 40 cmp\.gt\.or p2,p3=3Dr0,r4 - 46c: 08 20 0c c9 cmp\.lt\.and p2,p3=3Dr0,r4 - 470: 00 10 00 08 03 32 \[MII\] cmp\.gt\.and p2,p3=3Dr0,r4 - 476: 30 04 10 84 74 60 cmp\.lt\.or\.andcm p3,p2=3Dr0,r4 - 47c: 00 20 08 e8 cmp\.gt\.or\.andcm p3,p2=3Dr0,r4 - 480: 00 10 0c 08 83 38 \[MII\] cmp4\.eq p2,p3=3Dr3,r4 - 486: 20 18 10 06 73 60 cmp4\.eq p2,p3=3D3,r4 - 48c: 30 20 08 e2 cmp4\.eq p3,p2=3Dr3,r4 - 490: 00 18 0c 08 82 39 \[MII\] cmp4\.eq p3,p2=3D3,r4 - 496: 20 18 10 06 61 40 cmp4\.lt p2,p3=3Dr3,r4 - 49c: 30 20 0c c6 cmp4\.lt p2,p3=3D3,r4 - 4a0: 00 18 10 06 82 30 \[MII\] cmp4\.lt p3,p2=3Dr4,r3 - 4a6: 20 10 10 06 63 40 cmp4\.lt p2,p3=3D2,r4 - 4ac: 40 18 0c c2 cmp4\.lt p2,p3=3Dr4,r3 - 4b0: 00 18 08 08 82 31 \[MII\] cmp4\.lt p3,p2=3D2,r4 - 4b6: 30 18 10 04 61 60 cmp4\.lt p3,p2=3Dr3,r4 - 4bc: 30 20 08 c6 cmp4\.lt p3,p2=3D3,r4 - 4c0: 00 10 0c 08 83 34 \[MII\] cmp4\.ltu p2,p3=3Dr3,r4 - 4c6: 20 18 10 06 6b 60 cmp4\.ltu p2,p3=3D3,r4 - 4cc: 40 18 08 d2 cmp4\.ltu p3,p2=3Dr4,r3 - 4d0: 00 10 08 08 83 35 \[MII\] cmp4\.ltu p2,p3=3D2,r4 - 4d6: 20 20 0c 06 69 60 cmp4\.ltu p2,p3=3Dr4,r3 - 4dc: 20 20 08 d6 cmp4\.ltu p3,p2=3D2,r4 - 4e0: 00 18 0c 08 82 34 \[MII\] cmp4\.ltu p3,p2=3Dr3,r4 - 4e6: 30 18 10 04 6b 40 cmp4\.ltu p3,p2=3D3,r4 - 4ec: 38 20 0c e2 cmp4\.eq\.unc p2,p3=3Dr3,r4 - 4f0: 00 10 0e 08 83 39 \[MII\] cmp4\.eq\.unc p2,p3=3D3,r4 - 4f6: 30 1c 10 04 71 60 cmp4\.eq\.unc p3,p2=3Dr3,r4 - 4fc: 38 20 08 e6 cmp4\.eq\.unc p3,p2=3D3,r4 - 500: 00 10 0e 08 83 30 \[MII\] cmp4\.lt\.unc p2,p3=3Dr3,r4 - 506: 20 1c 10 06 63 60 cmp4\.lt\.unc p2,p3=3D3,r4 - 50c: 48 18 08 c2 cmp4\.lt\.unc p3,p2=3Dr4,r3 - 510: 00 10 0a 08 83 31 \[MII\] cmp4\.lt\.unc p2,p3=3D2,r4 - 516: 20 24 0c 06 61 60 cmp4\.lt\.unc p2,p3=3Dr4,r3 - 51c: 28 20 08 c6 cmp4\.lt\.unc p3,p2=3D2,r4 - 520: 00 18 0e 08 82 30 \[MII\] cmp4\.lt\.unc p3,p2=3Dr3,r4 - 526: 30 1c 10 04 63 40 cmp4\.lt\.unc p3,p2=3D3,r4 - 52c: 38 20 0c d2 cmp4\.ltu\.unc p2,p3=3Dr3,r4 - 530: 00 10 0e 08 83 35 \[MII\] cmp4\.ltu\.unc p2,p3=3D3,r4 - 536: 30 24 0c 04 69 40 cmp4\.ltu\.unc p3,p2=3Dr4,r3 - 53c: 28 20 0c d6 cmp4\.ltu\.unc p2,p3=3D2,r4 - 540: 00 10 12 06 83 34 \[MII\] cmp4\.ltu\.unc p2,p3=3Dr4,r3 - 546: 30 14 10 04 6b 60 cmp4\.ltu\.unc p3,p2=3D2,r4 - 54c: 38 20 08 d2 cmp4\.ltu\.unc p3,p2=3Dr3,r4 - 550: 00 18 0e 08 82 35 \[MII\] cmp4\.ltu\.unc p3,p2=3D3,r4 - 556: 20 18 10 86 61 40 cmp4\.eq\.and p2,p3=3Dr3,r4 - 55c: 30 20 0c c7 cmp4\.eq\.and p2,p3=3D3,r4 - 560: 00 10 0c 08 c3 34 \[MII\] cmp4\.eq\.or p2,p3=3Dr3,r4 - 566: 20 18 10 86 6b 40 cmp4\.eq\.or p2,p3=3D3,r4 - 56c: 30 20 0c e3 cmp4\.eq\.or\.andcm p2,p3=3Dr3,r4 - 570: 00 10 0c 08 c3 39 \[MII\] cmp4\.eq\.or\.andcm p2,p3=3D3,r4 - 576: 20 1c 10 86 69 40 cmp4\.ne\.or p2,p3=3Dr3,r4 - 57c: 38 20 0c d7 cmp4\.ne\.or p2,p3=3D3,r4 - 580: 00 10 0e 08 c3 30 \[MII\] cmp4\.ne\.and p2,p3=3Dr3,r4 - 586: 20 1c 10 86 63 60 cmp4\.ne\.and p2,p3=3D3,r4 - 58c: 38 20 08 e3 cmp4\.ne\.or\.andcm p3,p2=3Dr3,r4 - 590: 00 18 0e 08 c2 39 \[MII\] cmp4\.ne\.or\.andcm p3,p2=3D3,r4 - 596: 20 1c 10 86 61 40 cmp4\.ne\.and p2,p3=3Dr3,r4 - 59c: 38 20 0c c7 cmp4\.ne\.and p2,p3=3D3,r4 - 5a0: 00 10 0e 08 c3 34 \[MII\] cmp4\.ne\.or p2,p3=3Dr3,r4 - 5a6: 20 1c 10 86 6b 40 cmp4\.ne\.or p2,p3=3D3,r4 - 5ac: 38 20 0c e3 cmp4\.ne\.or\.andcm p2,p3=3Dr3,r4 - 5b0: 00 10 0e 08 c3 39 \[MII\] cmp4\.ne\.or\.andcm p2,p3=3D3,r4 - 5b6: 20 18 10 86 69 40 cmp4\.eq\.or p2,p3=3Dr3,r4 - 5bc: 30 20 0c d7 cmp4\.eq\.or p2,p3=3D3,r4 - 5c0: 00 10 0c 08 c3 30 \[MII\] cmp4\.eq\.and p2,p3=3Dr3,r4 - 5c6: 20 18 10 86 63 60 cmp4\.eq\.and p2,p3=3D3,r4 - 5cc: 30 20 08 e3 cmp4\.eq\.or\.andcm p3,p2=3Dr3,r4 - 5d0: 00 18 0c 08 c2 39 \[MII\] cmp4\.eq\.or\.andcm p3,p2=3D3,r4 - 5d6: 20 00 10 86 61 40 cmp4\.eq\.and p2,p3=3Dr0,r4 - 5dc: 40 00 0c c3 cmp4\.eq\.and p2,p3=3Dr4,r0 - 5e0: 00 10 00 08 c3 34 \[MII\] cmp4\.eq\.or p2,p3=3Dr0,r4 - 5e6: 20 20 00 86 69 40 cmp4\.eq\.or p2,p3=3Dr4,r0 - 5ec: 00 20 0c e3 cmp4\.eq\.or\.andcm p2,p3=3Dr0,r4 - 5f0: 00 10 10 00 c3 38 \[MII\] cmp4\.eq\.or\.andcm p2,p3=3Dr4,r0 - 5f6: 20 04 10 86 69 40 cmp4\.ne\.or p2,p3=3Dr0,r4 - 5fc: 48 00 0c d3 cmp4\.ne\.or p2,p3=3Dr4,r0 - 600: 00 10 02 08 c3 30 \[MII\] cmp4\.ne\.and p2,p3=3Dr0,r4 - 606: 20 24 00 86 61 60 cmp4\.ne\.and p2,p3=3Dr4,r0 - 60c: 08 20 08 e3 cmp4\.ne\.or\.andcm p3,p2=3Dr0,r4 - 610: 00 18 12 00 c2 38 \[MII\] cmp4\.ne\.or\.andcm p3,p2=3Dr4,r0 - 616: 20 04 10 86 61 40 cmp4\.ne\.and p2,p3=3Dr0,r4 - 61c: 48 00 0c c3 cmp4\.ne\.and p2,p3=3Dr4,r0 - 620: 00 10 02 08 c3 34 \[MII\] cmp4\.ne\.or p2,p3=3Dr0,r4 - 626: 20 24 00 86 69 40 cmp4\.ne\.or p2,p3=3Dr4,r0 - 62c: 08 20 0c e3 cmp4\.ne\.or\.andcm p2,p3=3Dr0,r4 - 630: 00 10 12 00 c3 38 \[MII\] cmp4\.ne\.or\.andcm p2,p3=3Dr4,r0 - 636: 20 00 10 86 69 40 cmp4\.eq\.or p2,p3=3Dr0,r4 - 63c: 40 00 0c d3 cmp4\.eq\.or p2,p3=3Dr4,r0 - 640: 00 10 00 08 c3 30 \[MII\] cmp4\.eq\.and p2,p3=3Dr0,r4 - 646: 20 20 00 86 61 60 cmp4\.eq\.and p2,p3=3Dr4,r0 - 64c: 00 20 08 e3 cmp4\.eq\.or\.andcm p3,p2=3Dr0,r4 - 650: 00 18 10 00 c2 38 \[MII\] cmp4\.eq\.or\.andcm p3,p2=3Dr4,r0 - 656: 20 04 10 86 65 40 cmp4\.lt\.and p2,p3=3Dr0,r4 - 65c: 00 20 0c ca cmp4\.gt\.and p2,p3=3Dr0,r4 - 660: 00 10 02 08 c3 36 \[MII\] cmp4\.lt\.or p2,p3=3Dr0,r4 - 666: 20 00 10 06 6d 40 cmp4\.gt\.or p2,p3=3Dr0,r4 - 66c: 08 20 0c eb cmp4\.lt\.or\.andcm p2,p3=3Dr0,r4 - 670: 00 10 00 08 83 3a \[MII\] cmp4\.gt\.or\.andcm p2,p3=3Dr0,r4 - 676: 20 00 10 86 6d 40 cmp4\.ge\.or p2,p3=3Dr0,r4 - 67c: 08 20 0c da cmp4\.le\.or p2,p3=3Dr0,r4 - 680: 00 10 00 08 c3 32 \[MII\] cmp4\.ge\.and p2,p3=3Dr0,r4 - 686: 20 04 10 06 65 60 cmp4\.le\.and p2,p3=3Dr0,r4 - 68c: 00 20 08 eb cmp4\.ge\.or\.andcm p3,p2=3Dr0,r4 - 690: 00 18 02 08 82 3a \[MII\] cmp4\.le\.or\.andcm p3,p2=3Dr0,r4 - 696: 20 04 10 06 65 40 cmp4\.le\.and p2,p3=3Dr0,r4 - 69c: 00 20 0c cb cmp4\.ge\.and p2,p3=3Dr0,r4 - 6a0: 00 10 02 08 83 36 \[MII\] cmp4\.le\.or p2,p3=3Dr0,r4 - 6a6: 20 00 10 86 6d 40 cmp4\.ge\.or p2,p3=3Dr0,r4 - 6ac: 08 20 0c ea cmp4\.le\.or\.andcm p2,p3=3Dr0,r4 - 6b0: 00 10 00 08 c3 3a \[MII\] cmp4\.ge\.or\.andcm p2,p3=3Dr0,r4 - 6b6: 20 00 10 06 6d 40 cmp4\.gt\.or p2,p3=3Dr0,r4 - 6bc: 08 20 0c db cmp4\.lt\.or p2,p3=3Dr0,r4 - 6c0: 00 10 00 08 83 32 \[MII\] cmp4\.gt\.and p2,p3=3Dr0,r4 - 6c6: 20 04 10 86 65 60 cmp4\.lt\.and p2,p3=3Dr0,r4 - 6cc: 00 20 08 ea cmp4\.gt\.or\.andcm p3,p2=3Dr0,r4 - 6d0: 00 18 02 08 c2 3a \[MII\] cmp4\.lt\.or\.andcm p3,p2=3Dr0,r4 - 6d6: 20 00 10 06 65 40 cmp4\.gt\.and p2,p3=3Dr0,r4 - 6dc: 08 20 0c cb cmp4\.lt\.and p2,p3=3Dr0,r4 - 6e0: 00 10 00 08 83 36 \[MII\] cmp4\.gt\.or p2,p3=3Dr0,r4 - 6e6: 20 04 10 86 6d 40 cmp4\.lt\.or p2,p3=3Dr0,r4 - 6ec: 00 20 0c ea cmp4\.gt\.or\.andcm p2,p3=3Dr0,r4 - 6f0: 00 10 02 08 c3 3a \[MII\] cmp4\.lt\.or\.andcm p2,p3=3Dr0,r4 - 6f6: 20 04 10 06 6d 40 cmp4\.le\.or p2,p3=3Dr0,r4 - 6fc: 00 20 0c db cmp4\.ge\.or p2,p3=3Dr0,r4 - 700: 00 10 02 08 83 32 \[MII\] cmp4\.le\.and p2,p3=3Dr0,r4 - 706: 20 00 10 86 65 60 cmp4\.ge\.and p2,p3=3Dr0,r4 - 70c: 08 20 08 ea cmp4\.le\.or\.andcm p3,p2=3Dr0,r4 - 710: 00 18 00 08 c2 3a \[MII\] cmp4\.ge\.or\.andcm p3,p2=3Dr0,r4 - 716: 20 00 10 86 65 40 cmp4\.ge\.and p2,p3=3Dr0,r4 - 71c: 08 20 0c ca cmp4\.le\.and p2,p3=3Dr0,r4 - 720: 00 10 00 08 c3 36 \[MII\] cmp4\.ge\.or p2,p3=3Dr0,r4 - 726: 20 04 10 06 6d 40 cmp4\.le\.or p2,p3=3Dr0,r4 - 72c: 00 20 0c eb cmp4\.ge\.or\.andcm p2,p3=3Dr0,r4 - 730: 00 10 02 08 83 3a \[MII\] cmp4\.le\.or\.andcm p2,p3=3Dr0,r4 - 736: 20 04 10 86 6d 40 cmp4\.lt\.or p2,p3=3Dr0,r4 - 73c: 00 20 0c da cmp4\.gt\.or p2,p3=3Dr0,r4 - 740: 00 10 02 08 c3 32 \[MII\] cmp4\.lt\.and p2,p3=3Dr0,r4 - 746: 20 00 10 06 65 60 cmp4\.gt\.and p2,p3=3Dr0,r4 - 74c: 08 20 08 eb cmp4\.lt\.or\.andcm p3,p2=3Dr0,r4 - 750: 01 18 00 08 82 3a \[MII\] cmp4\.gt\.or\.andcm p3,p2=3Dr0,r4 - 756: 00 00 00 02 00 00 nop\.i 0x0 - 75c: 00 00 04 00 nop\.i 0x0;; diff --git a/gas/testsuite/gas/ia64/opc-a.pl b/gas/testsuite/gas/ia64/opc-a= .pl deleted file mode 100644 index 8b5e12da453..00000000000 --- a/gas/testsuite/gas/ia64/opc-a.pl +++ /dev/null @@ -1,142 +0,0 @@ -$AT =3D '@'; -print <: - 0: 17 00 00 00 00 88 \[BBB\] nop\.b 0x0 - 6: 00 f8 15 00 20 00 \(p02\) br\.cond\.sptk\.few 0x2bf0 - c: 00 00 00 40 br\.few 0x0;; - 10: 17 00 00 00 00 88 \[BBB\] nop\.b 0x0 - 16: 00 f0 15 00 22 00 \(p02\) br\.cond\.sptk\.few\.clr 0x2bf0 - 1c: f0 ff ff 4c br\.few\.clr 0x0;; - 20: 17 00 00 00 00 88 \[BBB\] nop\.b 0x0 - 26: 00 e8 15 00 20 00 \(p02\) br\.cond\.sptk\.few 0x2bf0 - 2c: e0 ff ff 48 br\.few 0x0;; - 30: 17 00 00 00 00 88 \[BBB\] nop\.b 0x0 - 36: 00 e0 15 00 22 00 \(p02\) br\.cond\.sptk\.few\.clr 0x2bf0 - 3c: d0 ff ff 4c br\.few\.clr 0x0;; - 40: 17 00 00 00 00 88 \[BBB\] nop\.b 0x0 - 46: 00 dc 15 00 20 00 \(p02\) br\.cond\.sptk\.many 0x2bf0 - 4c: c8 ff ff 48 br\.many 0x0;; - 50: 17 00 00 00 00 88 \[BBB\] nop\.b 0x0 - 56: 00 d4 15 00 22 00 \(p02\) br\.cond\.sptk\.many\.clr 0x2bf0 - 5c: b8 ff ff 4c br\.many\.clr 0x0;; - 60: 17 00 00 00 00 88 \[BBB\] nop\.b 0x0 - 66: 00 c8 15 80 20 00 \(p02\) br\.cond\.spnt\.few 0x2bf0 - 6c: a0 ff ff 49 br\.cond\.spnt\.few 0x0;; - 70: 17 00 00 00 00 88 \[BBB\] nop\.b 0x0 - 76: 00 c0 15 80 22 00 \(p02\) br\.cond\.spnt\.few\.clr 0x2bf0 - 7c: 90 ff ff 4d br\.cond\.spnt\.few\.clr 0x0;; - 80: 17 00 00 00 00 88 \[BBB\] nop\.b 0x0 - 86: 00 b8 15 80 20 00 \(p02\) br\.cond\.spnt\.few 0x2bf0 - 8c: 80 ff ff 49 br\.cond\.spnt\.few 0x0;; - 90: 17 00 00 00 00 88 \[BBB\] nop\.b 0x0 - 96: 00 b0 15 80 22 00 \(p02\) br\.cond\.spnt\.few\.clr 0x2bf0 - 9c: 70 ff ff 4d br\.cond\.spnt\.few\.clr 0x0;; - a0: 17 00 00 00 00 88 \[BBB\] nop\.b 0x0 - a6: 00 ac 15 80 20 00 \(p02\) br\.cond\.spnt\.many 0x2bf0 - ac: 68 ff ff 49 br\.cond\.spnt\.many 0x0;; - b0: 17 00 00 00 00 88 \[BBB\] nop\.b 0x0 - b6: 00 a4 15 80 22 00 \(p02\) br\.cond\.spnt\.many\.clr 0x2bf0 - bc: 58 ff ff 4d br\.cond\.spnt\.many\.clr 0x0;; - c0: 17 00 00 00 00 88 \[BBB\] nop\.b 0x0 - c6: 00 98 15 00 21 00 \(p02\) br\.cond\.dptk\.few 0x2bf0 - cc: 40 ff ff 4a br\.cond\.dptk\.few 0x0;; - d0: 17 00 00 00 00 88 \[BBB\] nop\.b 0x0 - d6: 00 90 15 00 23 00 \(p02\) br\.cond\.dptk\.few\.clr 0x2bf0 - dc: 30 ff ff 4e br\.cond\.dptk\.few\.clr 0x0;; - e0: 17 00 00 00 00 88 \[BBB\] nop\.b 0x0 - e6: 00 88 15 00 21 00 \(p02\) br\.cond\.dptk\.few 0x2bf0 - ec: 20 ff ff 4a br\.cond\.dptk\.few 0x0;; - f0: 17 00 00 00 00 88 \[BBB\] nop\.b 0x0 - f6: 00 80 15 00 23 00 \(p02\) br\.cond\.dptk\.few\.clr 0x2bf0 - fc: 10 ff ff 4e br\.cond\.dptk\.few\.clr 0x0;; - 100: 17 00 00 00 00 88 \[BBB\] nop\.b 0x0 - 106: 00 7c 15 00 21 00 \(p02\) br\.cond\.dptk\.many 0x2bf0 - 10c: 08 ff ff 4a br\.cond\.dptk\.many 0x0;; - 110: 17 00 00 00 00 88 \[BBB\] nop\.b 0x0 - 116: 00 74 15 00 23 00 \(p02\) br\.cond\.dptk\.many\.clr 0x2bf0 - 11c: f8 fe ff 4e br\.cond\.dptk\.many\.clr 0x0;; - 120: 17 00 00 00 00 88 \[BBB\] nop\.b 0x0 - 126: 00 68 15 80 21 00 \(p02\) br\.cond\.dpnt\.few 0x2bf0 - 12c: e0 fe ff 4b br\.cond\.dpnt\.few 0x0;; - 130: 17 00 00 00 00 88 \[BBB\] nop\.b 0x0 - 136: 00 60 15 80 23 00 \(p02\) br\.cond\.dpnt\.few\.clr 0x2bf0 - 13c: d0 fe ff 4f br\.cond\.dpnt\.few\.clr 0x0;; - 140: 17 00 00 00 00 88 \[BBB\] nop\.b 0x0 - 146: 00 58 15 80 21 00 \(p02\) br\.cond\.dpnt\.few 0x2bf0 - 14c: c0 fe ff 4b br\.cond\.dpnt\.few 0x0;; - 150: 17 00 00 00 00 88 \[BBB\] nop\.b 0x0 - 156: 00 50 15 80 23 00 \(p02\) br\.cond\.dpnt\.few\.clr 0x2bf0 - 15c: b0 fe ff 4f br\.cond\.dpnt\.few\.clr 0x0;; - 160: 17 00 00 00 00 88 \[BBB\] nop\.b 0x0 - 166: 00 4c 15 80 21 00 \(p02\) br\.cond\.dpnt\.many 0x2bf0 - 16c: a8 fe ff 4b br\.cond\.dpnt\.many 0x0;; - 170: 17 00 00 00 00 88 \[BBB\] nop\.b 0x0 - 176: 00 44 15 80 23 00 \(p02\) br\.cond\.dpnt\.many\.clr 0x2bf0 - 17c: 98 fe ff 4f br\.cond\.dpnt\.many\.clr 0x0;; - 180: 17 00 00 00 00 08 \[BBB\] nop\.b 0x0 - 186: 00 00 00 00 10 41 nop\.b 0x0 - 18c: 70 2a 00 40 \(p02\) br\.wexit\.sptk\.few 0x2bf0;; - 190: 17 00 00 00 00 08 \[BBB\] nop\.b 0x0 - 196: 00 00 00 00 10 40 nop\.b 0x0 - 19c: 60 2a 00 40 br\.wexit\.sptk\.few 0x2bf0;; - 1a0: 17 00 00 00 00 08 \[BBB\] nop\.b 0x0 - 1a6: 00 00 00 00 10 41 nop\.b 0x0 - 1ac: 50 2a 00 44 \(p02\) br\.wexit\.sptk\.few\.clr 0x2bf= 0;; - 1b0: 17 00 00 00 00 08 \[BBB\] nop\.b 0x0 - 1b6: 00 00 00 00 10 40 nop\.b 0x0 - 1bc: 40 2a 00 44 br\.wexit\.sptk\.few\.clr 0x2bf0;; - 1c0: 17 00 00 00 00 08 \[BBB\] nop\.b 0x0 - 1c6: 00 00 00 00 10 41 nop\.b 0x0 - 1cc: 30 2a 00 40 \(p02\) br\.wexit\.sptk\.few 0x2bf0;; - 1d0: 17 00 00 00 00 08 \[BBB\] nop\.b 0x0 - 1d6: 00 00 00 00 10 40 nop\.b 0x0 - 1dc: 20 2a 00 40 br\.wexit\.sptk\.few 0x2bf0;; - 1e0: 17 00 00 00 00 08 \[BBB\] nop\.b 0x0 - 1e6: 00 00 00 00 10 41 nop\.b 0x0 - 1ec: 10 2a 00 44 \(p02\) br\.wexit\.sptk\.few\.clr 0x2bf= 0;; - 1f0: 17 00 00 00 00 08 \[BBB\] nop\.b 0x0 - 1f6: 00 00 00 00 10 40 nop\.b 0x0 - 1fc: 00 2a 00 44 br\.wexit\.sptk\.few\.clr 0x2bf0;; - 200: 17 00 00 00 00 08 \[BBB\] nop\.b 0x0 - 206: 00 00 00 00 10 41 nop\.b 0x0 - 20c: f8 29 00 40 \(p02\) br\.wexit\.sptk\.many 0x2bf0;; - 210: 17 00 00 00 00 08 \[BBB\] nop\.b 0x0 - 216: 00 00 00 00 10 40 nop\.b 0x0 - 21c: e8 29 00 40 br\.wexit\.sptk\.many 0x2bf0;; - 220: 17 00 00 00 00 08 \[BBB\] nop\.b 0x0 - 226: 00 00 00 00 10 41 nop\.b 0x0 - 22c: d8 29 00 44 \(p02\) br\.wexit\.sptk\.many\.clr 0x2b= f0;; - 230: 17 00 00 00 00 08 \[BBB\] nop\.b 0x0 - 236: 00 00 00 00 10 40 nop\.b 0x0 - 23c: c8 29 00 44 br\.wexit\.sptk\.many\.clr 0x2bf0= ;; - 240: 17 00 00 00 00 08 \[BBB\] nop\.b 0x0 - 246: 00 00 00 00 10 41 nop\.b 0x0 - 24c: b0 29 00 41 \(p02\) br\.wexit\.spnt\.few 0x2bf0;; - 250: 17 00 00 00 00 08 \[BBB\] nop\.b 0x0 - 256: 00 00 00 00 10 40 nop\.b 0x0 - 25c: a0 29 00 41 br\.wexit\.spnt\.few 0x2bf0;; - 260: 17 00 00 00 00 08 \[BBB\] nop\.b 0x0 - 266: 00 00 00 00 10 41 nop\.b 0x0 - 26c: 90 29 00 45 \(p02\) br\.wexit\.spnt\.few\.clr 0x2bf= 0;; - 270: 17 00 00 00 00 08 \[BBB\] nop\.b 0x0 - 276: 00 00 00 00 10 40 nop\.b 0x0 - 27c: 80 29 00 45 br\.wexit\.spnt\.few\.clr 0x2bf0;; - 280: 17 00 00 00 00 08 \[BBB\] nop\.b 0x0 - 286: 00 00 00 00 10 41 nop\.b 0x0 - 28c: 70 29 00 41 \(p02\) br\.wexit\.spnt\.few 0x2bf0;; - 290: 17 00 00 00 00 08 \[BBB\] nop\.b 0x0 - 296: 00 00 00 00 10 40 nop\.b 0x0 - 29c: 60 29 00 41 br\.wexit\.spnt\.few 0x2bf0;; - 2a0: 17 00 00 00 00 08 \[BBB\] nop\.b 0x0 - 2a6: 00 00 00 00 10 41 nop\.b 0x0 - 2ac: 50 29 00 45 \(p02\) br\.wexit\.spnt\.few\.clr 0x2bf= 0;; - 2b0: 17 00 00 00 00 08 \[BBB\] nop\.b 0x0 - 2b6: 00 00 00 00 10 40 nop\.b 0x0 - 2bc: 40 29 00 45 br\.wexit\.spnt\.few\.clr 0x2bf0;; - 2c0: 17 00 00 00 00 08 \[BBB\] nop\.b 0x0 - 2c6: 00 00 00 00 10 41 nop\.b 0x0 - 2cc: 38 29 00 41 \(p02\) br\.wexit\.spnt\.many 0x2bf0;; - 2d0: 17 00 00 00 00 08 \[BBB\] nop\.b 0x0 - 2d6: 00 00 00 00 10 40 nop\.b 0x0 - 2dc: 28 29 00 41 br\.wexit\.spnt\.many 0x2bf0;; - 2e0: 17 00 00 00 00 08 \[BBB\] nop\.b 0x0 - 2e6: 00 00 00 00 10 41 nop\.b 0x0 - 2ec: 18 29 00 45 \(p02\) br\.wexit\.spnt\.many\.clr 0x2b= f0;; - 2f0: 17 00 00 00 00 08 \[BBB\] nop\.b 0x0 - 2f6: 00 00 00 00 10 40 nop\.b 0x0 - 2fc: 08 29 00 45 br\.wexit\.spnt\.many\.clr 0x2bf0= ;; - 300: 17 00 00 00 00 08 \[BBB\] nop\.b 0x0 - 306: 00 00 00 00 10 41 nop\.b 0x0 - 30c: f0 28 00 42 \(p02\) br\.wexit\.dptk\.few 0x2bf0;; - 310: 17 00 00 00 00 08 \[BBB\] nop\.b 0x0 - 316: 00 00 00 00 10 40 nop\.b 0x0 - 31c: e0 28 00 42 br\.wexit\.dptk\.few 0x2bf0;; - 320: 17 00 00 00 00 08 \[BBB\] nop\.b 0x0 - 326: 00 00 00 00 10 41 nop\.b 0x0 - 32c: d0 28 00 46 \(p02\) br\.wexit\.dptk\.few\.clr 0x2bf= 0;; - 330: 17 00 00 00 00 08 \[BBB\] nop\.b 0x0 - 336: 00 00 00 00 10 40 nop\.b 0x0 - 33c: c0 28 00 46 br\.wexit\.dptk\.few\.clr 0x2bf0;; - 340: 17 00 00 00 00 08 \[BBB\] nop\.b 0x0 - 346: 00 00 00 00 10 41 nop\.b 0x0 - 34c: b0 28 00 42 \(p02\) br\.wexit\.dptk\.few 0x2bf0;; - 350: 17 00 00 00 00 08 \[BBB\] nop\.b 0x0 - 356: 00 00 00 00 10 40 nop\.b 0x0 - 35c: a0 28 00 42 br\.wexit\.dptk\.few 0x2bf0;; - 360: 17 00 00 00 00 08 \[BBB\] nop\.b 0x0 - 366: 00 00 00 00 10 41 nop\.b 0x0 - 36c: 90 28 00 46 \(p02\) br\.wexit\.dptk\.few\.clr 0x2bf= 0;; - 370: 17 00 00 00 00 08 \[BBB\] nop\.b 0x0 - 376: 00 00 00 00 10 40 nop\.b 0x0 - 37c: 80 28 00 46 br\.wexit\.dptk\.few\.clr 0x2bf0;; - 380: 17 00 00 00 00 08 \[BBB\] nop\.b 0x0 - 386: 00 00 00 00 10 41 nop\.b 0x0 - 38c: 78 28 00 42 \(p02\) br\.wexit\.dptk\.many 0x2bf0;; - 390: 17 00 00 00 00 08 \[BBB\] nop\.b 0x0 - 396: 00 00 00 00 10 40 nop\.b 0x0 - 39c: 68 28 00 42 br\.wexit\.dptk\.many 0x2bf0;; - 3a0: 17 00 00 00 00 08 \[BBB\] nop\.b 0x0 - 3a6: 00 00 00 00 10 41 nop\.b 0x0 - 3ac: 58 28 00 46 \(p02\) br\.wexit\.dptk\.many\.clr 0x2b= f0;; - 3b0: 17 00 00 00 00 08 \[BBB\] nop\.b 0x0 - 3b6: 00 00 00 00 10 40 nop\.b 0x0 - 3bc: 48 28 00 46 br\.wexit\.dptk\.many\.clr 0x2bf0= ;; - 3c0: 17 00 00 00 00 08 \[BBB\] nop\.b 0x0 - 3c6: 00 00 00 00 10 41 nop\.b 0x0 - 3cc: 30 28 00 43 \(p02\) br\.wexit\.dpnt\.few 0x2bf0;; - 3d0: 17 00 00 00 00 08 \[BBB\] nop\.b 0x0 - 3d6: 00 00 00 00 10 40 nop\.b 0x0 - 3dc: 20 28 00 43 br\.wexit\.dpnt\.few 0x2bf0;; - 3e0: 17 00 00 00 00 08 \[BBB\] nop\.b 0x0 - 3e6: 00 00 00 00 10 41 nop\.b 0x0 - 3ec: 10 28 00 47 \(p02\) br\.wexit\.dpnt\.few\.clr 0x2bf= 0;; - 3f0: 17 00 00 00 00 08 \[BBB\] nop\.b 0x0 - 3f6: 00 00 00 00 10 40 nop\.b 0x0 - 3fc: 00 28 00 47 br\.wexit\.dpnt\.few\.clr 0x2bf0;; - 400: 17 00 00 00 00 08 \[BBB\] nop\.b 0x0 - 406: 00 00 00 00 10 41 nop\.b 0x0 - 40c: f0 27 00 43 \(p02\) br\.wexit\.dpnt\.few 0x2bf0;; - 410: 17 00 00 00 00 08 \[BBB\] nop\.b 0x0 - 416: 00 00 00 00 10 40 nop\.b 0x0 - 41c: e0 27 00 43 br\.wexit\.dpnt\.few 0x2bf0;; - 420: 17 00 00 00 00 08 \[BBB\] nop\.b 0x0 - 426: 00 00 00 00 10 41 nop\.b 0x0 - 42c: d0 27 00 47 \(p02\) br\.wexit\.dpnt\.few\.clr 0x2bf= 0;; - 430: 17 00 00 00 00 08 \[BBB\] nop\.b 0x0 - 436: 00 00 00 00 10 40 nop\.b 0x0 - 43c: c0 27 00 47 br\.wexit\.dpnt\.few\.clr 0x2bf0;; - 440: 17 00 00 00 00 08 \[BBB\] nop\.b 0x0 - 446: 00 00 00 00 10 41 nop\.b 0x0 - 44c: b8 27 00 43 \(p02\) br\.wexit\.dpnt\.many 0x2bf0;; - 450: 17 00 00 00 00 08 \[BBB\] nop\.b 0x0 - 456: 00 00 00 00 10 40 nop\.b 0x0 - 45c: a8 27 00 43 br\.wexit\.dpnt\.many 0x2bf0;; - 460: 17 00 00 00 00 08 \[BBB\] nop\.b 0x0 - 466: 00 00 00 00 10 41 nop\.b 0x0 - 46c: 98 27 00 47 \(p02\) br\.wexit\.dpnt\.many\.clr 0x2b= f0;; - 470: 17 00 00 00 00 08 \[BBB\] nop\.b 0x0 - 476: 00 00 00 00 10 40 nop\.b 0x0 - 47c: 88 27 00 47 br\.wexit\.dpnt\.many\.clr 0x2bf0= ;; - 480: 17 00 00 00 00 08 \[BBB\] nop\.b 0x0 - 486: 00 00 00 00 10 61 nop\.b 0x0 - 48c: 70 27 00 40 \(p02\) br\.wtop\.sptk\.few 0x2bf0;; - 490: 17 00 00 00 00 08 \[BBB\] nop\.b 0x0 - 496: 00 00 00 00 10 60 nop\.b 0x0 - 49c: 60 27 00 40 br\.wtop\.sptk\.few 0x2bf0;; - 4a0: 17 00 00 00 00 08 \[BBB\] nop\.b 0x0 - 4a6: 00 00 00 00 10 61 nop\.b 0x0 - 4ac: 50 27 00 44 \(p02\) br\.wtop\.sptk\.few\.clr 0x2bf0= ;; - 4b0: 17 00 00 00 00 08 \[BBB\] nop\.b 0x0 - 4b6: 00 00 00 00 10 60 nop\.b 0x0 - 4bc: 40 27 00 44 br\.wtop\.sptk\.few\.clr 0x2bf0;; - 4c0: 17 00 00 00 00 08 \[BBB\] nop\.b 0x0 - 4c6: 00 00 00 00 10 61 nop\.b 0x0 - 4cc: 30 27 00 40 \(p02\) br\.wtop\.sptk\.few 0x2bf0;; - 4d0: 17 00 00 00 00 08 \[BBB\] nop\.b 0x0 - 4d6: 00 00 00 00 10 60 nop\.b 0x0 - 4dc: 20 27 00 40 br\.wtop\.sptk\.few 0x2bf0;; - 4e0: 17 00 00 00 00 08 \[BBB\] nop\.b 0x0 - 4e6: 00 00 00 00 10 61 nop\.b 0x0 - 4ec: 10 27 00 44 \(p02\) br\.wtop\.sptk\.few\.clr 0x2bf0= ;; - 4f0: 17 00 00 00 00 08 \[BBB\] nop\.b 0x0 - 4f6: 00 00 00 00 10 60 nop\.b 0x0 - 4fc: 00 27 00 44 br\.wtop\.sptk\.few\.clr 0x2bf0;; - 500: 17 00 00 00 00 08 \[BBB\] nop\.b 0x0 - 506: 00 00 00 00 10 61 nop\.b 0x0 - 50c: f8 26 00 40 \(p02\) br\.wtop\.sptk\.many 0x2bf0;; - 510: 17 00 00 00 00 08 \[BBB\] nop\.b 0x0 - 516: 00 00 00 00 10 60 nop\.b 0x0 - 51c: e8 26 00 40 br\.wtop\.sptk\.many 0x2bf0;; - 520: 17 00 00 00 00 08 \[BBB\] nop\.b 0x0 - 526: 00 00 00 00 10 61 nop\.b 0x0 - 52c: d8 26 00 44 \(p02\) br\.wtop\.sptk\.many\.clr 0x2bf= 0;; - 530: 17 00 00 00 00 08 \[BBB\] nop\.b 0x0 - 536: 00 00 00 00 10 60 nop\.b 0x0 - 53c: c8 26 00 44 br\.wtop\.sptk\.many\.clr 0x2bf0;; - 540: 17 00 00 00 00 08 \[BBB\] nop\.b 0x0 - 546: 00 00 00 00 10 61 nop\.b 0x0 - 54c: b0 26 00 41 \(p02\) br\.wtop\.spnt\.few 0x2bf0;; - 550: 17 00 00 00 00 08 \[BBB\] nop\.b 0x0 - 556: 00 00 00 00 10 60 nop\.b 0x0 - 55c: a0 26 00 41 br\.wtop\.spnt\.few 0x2bf0;; - 560: 17 00 00 00 00 08 \[BBB\] nop\.b 0x0 - 566: 00 00 00 00 10 61 nop\.b 0x0 - 56c: 90 26 00 45 \(p02\) br\.wtop\.spnt\.few\.clr 0x2bf0= ;; - 570: 17 00 00 00 00 08 \[BBB\] nop\.b 0x0 - 576: 00 00 00 00 10 60 nop\.b 0x0 - 57c: 80 26 00 45 br\.wtop\.spnt\.few\.clr 0x2bf0;; - 580: 17 00 00 00 00 08 \[BBB\] nop\.b 0x0 - 586: 00 00 00 00 10 61 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b2;; - 1130: 17 00 00 00 00 88 \[BBB\] nop\.b 0x0 - 1136: 40 14 00 c2 02 80 \(p02\) br\.ret\.spnt\.many\.clr b2 - 113c: 28 00 84 05 br\.ret\.spnt\.many\.clr b2;; - 1140: 17 00 00 00 00 88 \[BBB\] nop\.b 0x0 - 1146: 40 10 00 42 01 80 \(p02\) br\.ret\.dptk\.few b2 - 114c: 20 00 84 02 br\.ret\.dptk\.few b2;; - 1150: 17 00 00 00 00 88 \[BBB\] nop\.b 0x0 - 1156: 40 10 00 42 03 80 \(p02\) br\.ret\.dptk\.few\.clr b2 - 115c: 20 00 84 06 br\.ret\.dptk\.few\.clr b2;; - 1160: 17 00 00 00 00 88 \[BBB\] nop\.b 0x0 - 1166: 40 10 00 42 01 80 \(p02\) br\.ret\.dptk\.few b2 - 116c: 20 00 84 02 br\.ret\.dptk\.few b2;; - 1170: 17 00 00 00 00 88 \[BBB\] nop\.b 0x0 - 1176: 40 10 00 42 03 80 \(p02\) br\.ret\.dptk\.few\.clr b2 - 117c: 20 00 84 06 br\.ret\.dptk\.few\.clr b2;; - 1180: 17 00 00 00 00 88 \[BBB\] nop\.b 0x0 - 1186: 40 14 00 42 01 80 \(p02\) br\.ret\.dptk\.many b2 - 118c: 28 00 84 02 br\.ret\.dptk\.many b2;; - 1190: 17 00 00 00 00 88 \[BBB\] nop\.b 0x0 - 1196: 40 14 00 42 03 80 \(p02\) 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00 00 88 \[BBB\] nop\.b 0x0 - 1206: 00 10 00 40 08 00 \(p02\) br\.call\.sptk\.few b0=3Db2 - 120c: 20 00 80 10 br\.call\.sptk\.few b0=3Db2;; - 1210: 17 00 00 00 00 88 \[BBB\] nop\.b 0x0 - 1216: 00 10 00 40 0a 00 \(p02\) br\.call\.sptk\.few\.clr b0=3Db2 - 121c: 20 00 80 14 br\.call\.sptk\.few\.clr b0=3Db2;; - 1220: 17 00 00 00 00 88 \[BBB\] nop\.b 0x0 - 1226: 00 10 00 40 08 00 \(p02\) br\.call\.sptk\.few b0=3Db2 - 122c: 20 00 80 10 br\.call\.sptk\.few b0=3Db2;; - 1230: 17 00 00 00 00 88 \[BBB\] nop\.b 0x0 - 1236: 00 10 00 40 0a 00 \(p02\) br\.call\.sptk\.few\.clr b0=3Db2 - 123c: 20 00 80 14 br\.call\.sptk\.few\.clr b0=3Db2;; - 1240: 17 00 00 00 00 88 \[BBB\] nop\.b 0x0 - 1246: 00 14 00 40 08 00 \(p02\) br\.call\.sptk\.many b0=3Db2 - 124c: 28 00 80 10 br\.call\.sptk\.many b0=3Db2;; - 1250: 17 00 00 00 00 88 \[BBB\] nop\.b 0x0 - 1256: 00 14 00 40 0a 00 \(p02\) br\.call\.sptk\.many\.clr b0=3D= b2 - 125c: 28 00 80 14 br\.call\.sptk\.many\.clr b0=3Db2= ;; - 1260: 17 00 00 00 00 88 \[BBB\] nop\.b 0x0 - 1266: 00 10 00 c0 08 00 \(p02\) br\.call\.spnt\.few b0=3Db2 - 126c: 20 00 80 11 br\.call\.spnt\.few b0=3Db2;; - 1270: 17 00 00 00 00 88 \[BBB\] nop\.b 0x0 - 1276: 00 10 00 c0 0a 00 \(p02\) br\.call\.spnt\.few\.clr b0=3Db2 - 127c: 20 00 80 15 br\.call\.spnt\.few\.clr b0=3Db2;; - 1280: 17 00 00 00 00 88 \[BBB\] nop\.b 0x0 - 1286: 00 10 00 c0 08 00 \(p02\) br\.call\.spnt\.few b0=3Db2 - 128c: 20 00 80 11 br\.call\.spnt\.few b0=3Db2;; - 1290: 17 00 00 00 00 88 \[BBB\] nop\.b 0x0 - 1296: 00 10 00 c0 0a 00 \(p02\) br\.call\.spnt\.few\.clr b0=3Db2 - 129c: 20 00 80 15 br\.call\.spnt\.few\.clr b0=3Db2;; - 12a0: 17 00 00 00 00 88 \[BBB\] nop\.b 0x0 - 12a6: 00 14 00 c0 08 00 \(p02\) br\.call\.spnt\.many b0=3Db2 - 12ac: 28 00 80 11 br\.call\.spnt\.many b0=3Db2;; - 12b0: 17 00 00 00 00 88 \[BBB\] nop\.b 0x0 - 12b6: 00 14 00 c0 0a 00 \(p02\) br\.call\.spnt\.many\.clr b0=3D= b2 - 12bc: 28 00 80 15 br\.call\.spnt\.many\.clr b0=3Db2= ;; - 12c0: 17 00 00 00 00 88 \[BBB\] nop\.b 0x0 - 12c6: 00 10 00 40 09 00 \(p02\) br\.call\.dptk\.few b0=3Db2 - 12cc: 20 00 80 12 br\.call\.dptk\.few b0=3Db2;; - 12d0: 17 00 00 00 00 88 \[BBB\] nop\.b 0x0 - 12d6: 00 10 00 40 0b 00 \(p02\) br\.call\.dptk\.few\.clr b0=3Db2 - 12dc: 20 00 80 16 br\.call\.dptk\.few\.clr b0=3Db2;; - 12e0: 17 00 00 00 00 88 \[BBB\] nop\.b 0x0 - 12e6: 00 10 00 40 09 00 \(p02\) br\.call\.dptk\.few b0=3Db2 - 12ec: 20 00 80 12 br\.call\.dptk\.few b0=3Db2;; - 12f0: 17 00 00 00 00 88 \[BBB\] nop\.b 0x0 - 12f6: 00 10 00 40 0b 00 \(p02\) br\.call\.dptk\.few\.clr b0=3Db2 - 12fc: 20 00 80 16 br\.call\.dptk\.few\.clr b0=3Db2;; - 1300: 17 00 00 00 00 88 \[BBB\] nop\.b 0x0 - 1306: 00 14 00 40 09 00 \(p02\) br\.call\.dptk\.many b0=3Db2 - 130c: 28 00 80 12 br\.call\.dptk\.many b0=3Db2;; - 1310: 17 00 00 00 00 88 \[BBB\] nop\.b 0x0 - 1316: 00 14 00 40 0b 00 \(p02\) br\.call\.dptk\.many\.clr b0=3D= b2 - 131c: 28 00 80 16 br\.call\.dptk\.many\.clr b0=3Db2= ;; - 1320: 17 00 00 00 00 88 \[BBB\] nop\.b 0x0 - 1326: 00 10 00 c0 09 00 \(p02\) br\.call\.dpnt\.few b0=3Db2 - 132c: 20 00 80 13 br\.call\.dpnt\.few b0=3Db2;; - 1330: 17 00 00 00 00 88 \[BBB\] nop\.b 0x0 - 1336: 00 10 00 c0 0b 00 \(p02\) br\.call\.dpnt\.few\.clr b0=3Db2 - 133c: 20 00 80 17 br\.call\.dpnt\.few\.clr b0=3Db2;; - 1340: 17 00 00 00 00 88 \[BBB\] nop\.b 0x0 - 1346: 00 10 00 c0 09 00 \(p02\) br\.call\.dpnt\.few b0=3Db2 - 134c: 20 00 80 13 br\.call\.dpnt\.few b0=3Db2;; - 1350: 17 00 00 00 00 88 \[BBB\] nop\.b 0x0 - 1356: 00 10 00 c0 0b 00 \(p02\) br\.call\.dpnt\.few\.clr b0=3Db2 - 135c: 20 00 80 17 br\.call\.dpnt\.few\.clr b0=3Db2;; - 1360: 17 00 00 00 00 88 \[BBB\] nop\.b 0x0 - 1366: 00 14 00 c0 09 00 \(p02\) br\.call\.dpnt\.many b0=3Db2 - 136c: 28 00 80 13 br\.call\.dpnt\.many b0=3Db2;; - 1370: 17 00 00 00 00 88 \[BBB\] nop\.b 0x0 - 1376: 00 14 00 c0 0b 00 \(p02\) br\.call\.dpnt\.many\.clr b0=3D= b2 - 137c: 28 00 80 17 br\.call\.dpnt\.many\.clr b0=3Db2= ;; - 1380: 17 00 00 00 00 00 \[BBB\] break\.b 0x0 - 1386: 00 00 00 00 10 40 nop\.b 0x0 - 138c: 80 ec ff 78 brp\.sptk 0x0,0x13a0;; - 1390: 17 00 00 00 00 00 \[BBB\] break\.b 0x0 - 1396: 00 00 00 00 10 20 nop\.b 0x0 - 139c: 70 ec ff 7c brp\.sptk\.imp 0x0,0x13a0;; - 13a0: 17 00 00 00 00 00 \[BBB\] break\.b 0x0 - 13a6: 00 00 00 00 10 44 nop\.b 0x0 - 13ac: 60 ec ff 78 brp\.loop 0x0,0x13c0;; - 13b0: 17 00 00 00 00 00 \[BBB\] break\.b 0x0 - 13b6: 00 00 00 00 10 24 nop\.b 0x0 - 13bc: 50 ec ff 7c brp\.loop\.imp 0x0,0x13c0;; - 13c0: 17 00 00 00 00 00 \[BBB\] break\.b 0x0 - 13c6: 00 00 00 00 10 48 nop\.b 0x0 - 13cc: 40 ec ff 78 brp\.dptk 0x0,0x13e0;; - 13d0: 17 00 00 00 00 00 \[BBB\] break\.b 0x0 - 13d6: 00 00 00 00 10 28 nop\.b 0x0 - 13dc: 30 ec ff 7c brp\.dptk\.imp 0x0,0x13e0;; - 13e0: 17 00 00 00 00 00 \[BBB\] break\.b 0x0 - 13e6: 00 00 00 00 10 4c nop\.b 0x0 - 13ec: 20 ec ff 78 brp\.exit 0x0,0x1400;; - 13f0: 17 00 00 00 00 00 \[BBB\] break\.b 0x0 - 13f6: 00 00 00 00 10 2c nop\.b 0x0 - 13fc: 10 ec ff 7c brp\.exit\.imp 0x0,0x1400;; - 1400: 17 00 00 00 00 00 \[BBB\] break\.b 0x0 - 1406: 00 00 00 00 10 40 nop\.b 0x0 - 140c: 30 00 40 20 brp\.sptk b3,0x1420;; - 1410: 17 00 00 00 00 00 \[BBB\] break\.b 0x0 - 1416: 00 00 00 00 10 20 nop\.b 0x0 - 141c: 30 00 40 24 brp\.sptk\.imp b3,0x1420;; - 1420: 17 00 00 00 00 00 \[BBB\] break\.b 0x0 - 1426: 00 00 00 00 10 48 nop\.b 0x0 - 142c: 30 00 40 20 brp\.dptk b3,0x1440;; - 1430: 17 00 00 00 00 00 \[BBB\] break\.b 0x0 - 1436: 00 00 00 00 10 28 nop\.b 0x0 - 143c: 30 00 40 24 brp\.dptk.imp b3,0x1440;; - 1440: 17 00 00 00 00 00 \[BBB\] break\.b 0x0 - 1446: 00 00 00 00 10 40 nop\.b 0x0 - 144c: 30 00 44 20 brp\.ret\.sptk b3,0x1460;; - 1450: 17 00 00 00 00 00 \[BBB\] break\.b 0x0 - 1456: 00 00 00 00 10 20 nop\.b 0x0 - 145c: 30 00 44 24 brp\.ret\.sptk\.imp b3,0x1460;; - 1460: 17 00 00 00 00 00 \[BBB\] break\.b 0x0 - 1466: 00 00 00 00 10 48 nop\.b 0x0 - 146c: 30 00 44 20 brp\.ret\.dptk b3,0x1480;; - 1470: 17 00 00 00 00 00 \[BBB\] break\.b 0x0 - 1476: 00 00 00 00 10 28 nop\.b 0x0 - 147c: 30 00 44 24 brp\.ret\.dptk.imp b3,0x1480;; - \.\.\. - 2b80: 17 00 00 00 00 08 \[BBB\] nop\.b 0x0 - 2b86: 00 00 00 00 10 00 nop\.b 0x0 - 2b8c: 00 00 08 00 cover;; - 2b90: 17 00 00 00 00 08 \[BBB\] nop\.b 0x0 - 2b96: 00 00 00 00 10 00 nop\.b 0x0 - 2b9c: 00 00 10 00 clrrrb;; - 2ba0: 17 00 00 00 00 08 \[BBB\] nop\.b 0x0 - 2ba6: 00 00 00 00 10 00 nop\.b 0x0 - 2bac: 00 00 14 00 clrrrb\.pr;; - 2bb0: 17 00 00 00 00 08 \[BBB\] nop\.b 0x0 - 2bb6: 00 00 00 00 10 00 nop\.b 0x0 - 2bbc: 00 00 20 00 rfi;; - 2bc0: 17 00 00 00 00 08 \[BBB\] nop\.b 0x0 - 2bc6: 00 00 00 00 10 00 nop\.b 0x0 - 2bcc: 00 00 30 00 bsw\.0;; - 2bd0: 17 00 00 00 00 08 \[BBB\] nop\.b 0x0 - 2bd6: 00 00 00 00 10 00 nop\.b 0x0 - 2bdc: 00 00 34 00 bsw\.1;; - 2be0: 17 00 00 00 00 08 \[BBB\] nop\.b 0x0 - 2be6: 00 00 00 00 10 00 nop\.b 0x0 - 2bec: 00 00 40 00 epc;; - 2bf0: 16 f8 ff 0f 00 00 \[BBB\] break\.b 0x1ffff - 2bf6: 00 00 00 02 10 e0 hint\.b 0x0 - 2bfc: ff 3f 04 20 hint\.b 0x1ffff - 2c00: 17 f8 ff 0f 00 08 \[BBB\] nop\.b 0x1ffff - 2c06: 00 00 00 30 00 00 vmsw.0 - 2c0c: 00 00 64 00 vmsw.1;; diff --git a/gas/testsuite/gas/ia64/opc-b.pl b/gas/testsuite/gas/ia64/opc-b= .pl deleted file mode 100644 index bdfdd36e654..00000000000 --- a/gas/testsuite/gas/ia64/opc-b.pl +++ /dev/null @@ -1,95 +0,0 @@ -@ph =3D ( "", ".few", ".many" ); -@bwh =3D ( ".sptk", ".spnt", ".dptk", ".dpnt" ); -@dh =3D ( "", ".clr" ); - -@iprel =3D ( ".cond", ".wexit", ".wtop", ".cloop", ".cexit", ".ctop", ".ca= ll" ); -@indir =3D ( ".cond", ".ia", ".ret", ".call" ); -%noqual =3D ( ".ia", 1, ".cloop", 1, ".ctop", 1, ".cexit", 1 ); -%slottwo =3D ( ".cloop", 1, ".ctop", 1, ".cexit", 1, ".wtop", 1, ".wexit",= 1 ); - -print ".L0:\n\n"; - -foreach $i (@iprel) { - $call =3D ($i eq ".call" ? "b0 =3D " : ""); - foreach $b (@bwh) { - foreach $p (@ph) { - foreach $d (@dh) { - if ($slottwo{$i}) { - if (!$noqual{$i}) { - print ("\t{ .bbb; (p2) br${i}${b}${p}${d} ${call}.L1 ;; }\n"); - } - print ("\t{ .bbb; br${i}${b}${p}${d} ${call}.L1 ;; }\n"); - } else { - print ("\t{ .bbb; nop.b 0\n"); - if (!$noqual{$i}) { - print ("(p2)\tbr${i}${b}${p}${d} ${call}.L1\n"); - } else { - print ("\tnop.b 0\n"); - } - print ("\tbr${i}${b}${p}${d} ${call}.L0\n"); - print ("\t;; }\n"); - } - } - } - } - print "\n"; -} - -foreach $i (@indir) { - $call =3D ($i eq ".call" ? "b0 =3D " : ""); - foreach $b (@bwh) { - foreach $p (@ph) { - foreach $d (@dh) { - print ("\t{ .bbb; nop.b 0;\n"); - if (!$noqual{$i}) { - print ("(p2)\tbr${i}${b}${p}${d} ${call}b2\n"); - } else { - print ("\tnop.b 0\n"); - } - print ("\tbr${i}${b}${p}${d} ${call}b2\n"); - print ("\t;; }\n"); - } - } - } - print "\n"; -} - -@ih =3D ( "", ".imp" ); -@ipwh =3D ( ".sptk", ".loop", ".dptk", ".exit" ); -@indwh =3D ( ".sptk", ".dptk" ); - -$CTR =3D 2; - -foreach $w (@ipwh) { - foreach $i (@ih) { - print ("\t{ .bbb; break.b 0; nop.b 0\n"); - print ("\tbrp${w}${i} .L0, .L${CTR}\n"); - print ("\t;; }\n"); - } - print (".L${CTR}:\n"); - ++$CTR; -} - -print "\n"; - -foreach $b ("", ".ret") { - foreach $w (@indwh) { - foreach $i (@ih) { - print ("\t{ .bbb; break.b 0; nop.b 0\n"); - print ("\tbrp${b}${w}${i} b3, .L${CTR}\n"); - print ("\t;; }\n"); - } - print (".L${CTR}:\n"); - ++$CTR; - } - print "\n"; -} - -print ".space 5888\n"; - -@last =3D ( "cover", "clrrrb", "clrrrb.pr", "rfi", "bsw.0", "bsw.1", "epc"= ); -foreach $i (@last) { - print "\t{ .bbb; nop.b 0; nop.b 0; $i ;; }\n"; -} - -print "\n.L1:\n"; diff --git a/gas/testsuite/gas/ia64/opc-b.s b/gas/testsuite/gas/ia64/opc-b.s deleted file mode 100644 index 565ab5474ab..00000000000 --- a/gas/testsuite/gas/ia64/opc-b.s +++ /dev/null @@ -1,837 +0,0 @@ -.L0: - - { .bbb; nop.b 0 -(p2) br.cond.sptk .L1 - br.cond.sptk .L0 - ;; } - { .bbb; nop.b 0 -(p2) br.cond.sptk.clr .L1 - br.cond.sptk.clr .L0 - ;; } - { .bbb; nop.b 0 -(p2) br.cond.sptk.few .L1 - br.cond.sptk.few .L0 - ;; } - { .bbb; nop.b 0 -(p2) br.cond.sptk.few.clr .L1 - br.cond.sptk.few.clr .L0 - ;; } - { .bbb; nop.b 0 -(p2) br.cond.sptk.many .L1 - br.cond.sptk.many .L0 - ;; } - { .bbb; nop.b 0 -(p2) br.cond.sptk.many.clr .L1 - br.cond.sptk.many.clr .L0 - ;; } - { .bbb; nop.b 0 -(p2) br.cond.spnt .L1 - br.cond.spnt .L0 - ;; } - { .bbb; nop.b 0 -(p2) br.cond.spnt.clr .L1 - br.cond.spnt.clr .L0 - ;; } - { .bbb; nop.b 0 -(p2) br.cond.spnt.few .L1 - br.cond.spnt.few .L0 - ;; } - { .bbb; nop.b 0 -(p2) br.cond.spnt.few.clr .L1 - br.cond.spnt.few.clr .L0 - ;; } - { .bbb; nop.b 0 -(p2) br.cond.spnt.many .L1 - br.cond.spnt.many .L0 - ;; } - { .bbb; nop.b 0 -(p2) br.cond.spnt.many.clr .L1 - br.cond.spnt.many.clr .L0 - ;; } - { .bbb; nop.b 0 -(p2) br.cond.dptk .L1 - br.cond.dptk .L0 - ;; } - { .bbb; nop.b 0 -(p2) br.cond.dptk.clr .L1 - br.cond.dptk.clr .L0 - ;; } - { .bbb; nop.b 0 -(p2) br.cond.dptk.few .L1 - br.cond.dptk.few .L0 - ;; } - { .bbb; nop.b 0 -(p2) br.cond.dptk.few.clr .L1 - br.cond.dptk.few.clr .L0 - ;; } - { .bbb; nop.b 0 -(p2) br.cond.dptk.many .L1 - br.cond.dptk.many .L0 - ;; } - { .bbb; nop.b 0 -(p2) br.cond.dptk.many.clr .L1 - br.cond.dptk.many.clr .L0 - ;; } - { .bbb; nop.b 0 -(p2) br.cond.dpnt .L1 - br.cond.dpnt .L0 - ;; } - { .bbb; nop.b 0 -(p2) br.cond.dpnt.clr .L1 - br.cond.dpnt.clr .L0 - ;; } - { .bbb; nop.b 0 -(p2) br.cond.dpnt.few .L1 - br.cond.dpnt.few .L0 - ;; } - { .bbb; nop.b 0 -(p2) br.cond.dpnt.few.clr .L1 - br.cond.dpnt.few.clr .L0 - ;; } - { .bbb; nop.b 0 -(p2) br.cond.dpnt.many .L1 - br.cond.dpnt.many .L0 - ;; } - { .bbb; nop.b 0 -(p2) br.cond.dpnt.many.clr .L1 - br.cond.dpnt.many.clr .L0 - ;; } - - { .bbb; (p2) br.wexit.sptk .L1 ;; } - { .bbb; br.wexit.sptk .L1 ;; } - { .bbb; (p2) br.wexit.sptk.clr .L1 ;; } - { .bbb; br.wexit.sptk.clr .L1 ;; } - { .bbb; (p2) br.wexit.sptk.few .L1 ;; } - { .bbb; br.wexit.sptk.few .L1 ;; } - { .bbb; (p2) br.wexit.sptk.few.clr .L1 ;; } - { .bbb; br.wexit.sptk.few.clr .L1 ;; } - { .bbb; (p2) br.wexit.sptk.many .L1 ;; } - { .bbb; br.wexit.sptk.many .L1 ;; } - { .bbb; (p2) br.wexit.sptk.many.clr .L1 ;; } - { .bbb; br.wexit.sptk.many.clr .L1 ;; } - { .bbb; (p2) br.wexit.spnt .L1 ;; } - { .bbb; br.wexit.spnt .L1 ;; } - { .bbb; (p2) br.wexit.spnt.clr .L1 ;; } - { .bbb; br.wexit.spnt.clr .L1 ;; } - { .bbb; (p2) br.wexit.spnt.few .L1 ;; } - { .bbb; br.wexit.spnt.few .L1 ;; } - { .bbb; (p2) br.wexit.spnt.few.clr .L1 ;; } - { .bbb; br.wexit.spnt.few.clr .L1 ;; } - { .bbb; (p2) br.wexit.spnt.many .L1 ;; } - { .bbb; br.wexit.spnt.many .L1 ;; } - { .bbb; (p2) br.wexit.spnt.many.clr .L1 ;; } - { .bbb; br.wexit.spnt.many.clr .L1 ;; } - { .bbb; (p2) br.wexit.dptk .L1 ;; } - { .bbb; br.wexit.dptk .L1 ;; } - { .bbb; (p2) br.wexit.dptk.clr .L1 ;; } - { .bbb; br.wexit.dptk.clr .L1 ;; } - { .bbb; (p2) br.wexit.dptk.few .L1 ;; } - { .bbb; br.wexit.dptk.few .L1 ;; } - { .bbb; (p2) br.wexit.dptk.few.clr .L1 ;; } - { .bbb; br.wexit.dptk.few.clr .L1 ;; } - { .bbb; (p2) br.wexit.dptk.many .L1 ;; } - { .bbb; br.wexit.dptk.many .L1 ;; } - { .bbb; (p2) br.wexit.dptk.many.clr .L1 ;; } - { .bbb; br.wexit.dptk.many.clr .L1 ;; } - { .bbb; (p2) br.wexit.dpnt .L1 ;; } - { .bbb; br.wexit.dpnt .L1 ;; } - { .bbb; (p2) br.wexit.dpnt.clr .L1 ;; } - { .bbb; br.wexit.dpnt.clr .L1 ;; } - { .bbb; (p2) br.wexit.dpnt.few .L1 ;; } - { .bbb; br.wexit.dpnt.few .L1 ;; } - { .bbb; (p2) br.wexit.dpnt.few.clr .L1 ;; } - { .bbb; br.wexit.dpnt.few.clr .L1 ;; } - { .bbb; (p2) br.wexit.dpnt.many .L1 ;; } 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br.cond.dptk.clr b2 - ;; } - { .bbb; nop.b 0; -(p2) br.cond.dptk.few b2 - br.cond.dptk.few b2 - ;; } - { .bbb; nop.b 0; -(p2) br.cond.dptk.few.clr b2 - br.cond.dptk.few.clr b2 - ;; } - { .bbb; nop.b 0; -(p2) br.cond.dptk.many b2 - br.cond.dptk.many b2 - ;; } - { .bbb; nop.b 0; -(p2) br.cond.dptk.many.clr b2 - br.cond.dptk.many.clr b2 - ;; } - { .bbb; nop.b 0; -(p2) br.cond.dpnt b2 - br.cond.dpnt b2 - ;; } - { .bbb; nop.b 0; -(p2) br.cond.dpnt.clr b2 - br.cond.dpnt.clr b2 - ;; } - { .bbb; nop.b 0; -(p2) br.cond.dpnt.few b2 - br.cond.dpnt.few b2 - ;; } - { .bbb; nop.b 0; -(p2) br.cond.dpnt.few.clr b2 - br.cond.dpnt.few.clr b2 - ;; } - { .bbb; nop.b 0; -(p2) br.cond.dpnt.many b2 - br.cond.dpnt.many b2 - ;; } - { .bbb; nop.b 0; -(p2) br.cond.dpnt.many.clr b2 - br.cond.dpnt.many.clr b2 - ;; } - - { .bbb; nop.b 0; - nop.b 0 - br.ia.sptk b2 - ;; } - { .bbb; nop.b 0; - nop.b 0 - br.ia.sptk.clr b2 - ;; } - { .bbb; nop.b 0; - nop.b 0 - br.ia.sptk.few b2 - ;; } - { .bbb; nop.b 0; - nop.b 0 - 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.bbb; nop.b 0; - nop.b 0 - br.ia.dpnt.few.clr b2 - ;; } - { .bbb; nop.b 0; - nop.b 0 - br.ia.dpnt.many b2 - ;; } - { .bbb; nop.b 0; - nop.b 0 - br.ia.dpnt.many.clr b2 - ;; } - - { .bbb; nop.b 0; -(p2) br.ret.sptk b2 - br.ret.sptk b2 - ;; } - { .bbb; nop.b 0; -(p2) br.ret.sptk.clr b2 - br.ret.sptk.clr b2 - ;; } - { .bbb; nop.b 0; -(p2) br.ret.sptk.few b2 - br.ret.sptk.few b2 - ;; } - { .bbb; nop.b 0; -(p2) br.ret.sptk.few.clr b2 - br.ret.sptk.few.clr b2 - ;; } - { .bbb; nop.b 0; -(p2) br.ret.sptk.many b2 - br.ret.sptk.many b2 - ;; } - { .bbb; nop.b 0; -(p2) br.ret.sptk.many.clr b2 - br.ret.sptk.many.clr b2 - ;; } - { .bbb; nop.b 0; -(p2) br.ret.spnt b2 - br.ret.spnt b2 - ;; } - { .bbb; nop.b 0; -(p2) br.ret.spnt.clr b2 - br.ret.spnt.clr b2 - ;; } - { .bbb; nop.b 0; -(p2) br.ret.spnt.few b2 - br.ret.spnt.few b2 - ;; } - { .bbb; nop.b 0; -(p2) br.ret.spnt.few.clr b2 - br.ret.spnt.few.clr b2 - ;; } - { .bbb; nop.b 0; -(p2) br.ret.spnt.many b2 - br.ret.spnt.many b2 - ;; } - { .bbb; nop.b 0; -(p2) br.ret.spnt.many.clr b2 - br.ret.spnt.many.clr b2 - ;; } - { .bbb; nop.b 0; -(p2) br.ret.dptk b2 - br.ret.dptk b2 - ;; } - { .bbb; nop.b 0; -(p2) br.ret.dptk.clr b2 - br.ret.dptk.clr b2 - ;; } - { .bbb; nop.b 0; -(p2) br.ret.dptk.few b2 - br.ret.dptk.few b2 - ;; } - { .bbb; nop.b 0; -(p2) br.ret.dptk.few.clr b2 - br.ret.dptk.few.clr b2 - ;; } - { .bbb; nop.b 0; -(p2) br.ret.dptk.many b2 - br.ret.dptk.many b2 - ;; } - { .bbb; nop.b 0; -(p2) br.ret.dptk.many.clr b2 - br.ret.dptk.many.clr b2 - ;; } - { .bbb; nop.b 0; -(p2) br.ret.dpnt b2 - br.ret.dpnt b2 - ;; } - { .bbb; nop.b 0; -(p2) br.ret.dpnt.clr b2 - br.ret.dpnt.clr b2 - ;; } - { .bbb; nop.b 0; -(p2) br.ret.dpnt.few b2 - br.ret.dpnt.few b2 - ;; } - { .bbb; nop.b 0; -(p2) br.ret.dpnt.few.clr b2 - br.ret.dpnt.few.clr b2 - ;; } - { .bbb; nop.b 0; -(p2) br.ret.dpnt.many b2 - br.ret.dpnt.many b2 - ;; } - { .bbb; nop.b 0; -(p2) br.ret.dpnt.many.clr b2 - br.ret.dpnt.many.clr b2 - ;; } - - { .bbb; nop.b 0; -(p2) br.call.sptk b0 =3D b2 - br.call.sptk b0 =3D b2 - ;; } - { .bbb; nop.b 0; -(p2) br.call.sptk.clr b0 =3D b2 - br.call.sptk.clr b0 =3D b2 - ;; } - { .bbb; nop.b 0; -(p2) br.call.sptk.few b0 =3D b2 - br.call.sptk.few b0 =3D b2 - ;; } - { .bbb; nop.b 0; -(p2) br.call.sptk.few.clr b0 =3D b2 - br.call.sptk.few.clr b0 =3D b2 - ;; } - { .bbb; nop.b 0; -(p2) br.call.sptk.many b0 =3D b2 - br.call.sptk.many b0 =3D b2 - ;; } - { .bbb; nop.b 0; -(p2) br.call.sptk.many.clr b0 =3D b2 - br.call.sptk.many.clr b0 =3D b2 - ;; } - { .bbb; nop.b 0; -(p2) br.call.spnt b0 =3D b2 - br.call.spnt b0 =3D b2 - ;; } - { .bbb; nop.b 0; -(p2) br.call.spnt.clr b0 =3D b2 - br.call.spnt.clr b0 =3D b2 - ;; } - { .bbb; nop.b 0; -(p2) br.call.spnt.few b0 =3D b2 - br.call.spnt.few b0 =3D b2 - ;; } - { .bbb; nop.b 0; -(p2) br.call.spnt.few.clr b0 =3D b2 - br.call.spnt.few.clr b0 =3D b2 - ;; } - { .bbb; nop.b 0; -(p2) br.call.spnt.many b0 =3D b2 - br.call.spnt.many b0 =3D b2 - ;; } - { .bbb; nop.b 0; -(p2) br.call.spnt.many.clr b0 =3D b2 - br.call.spnt.many.clr b0 =3D b2 - ;; } - { .bbb; nop.b 0; -(p2) br.call.dptk b0 =3D b2 - br.call.dptk b0 =3D b2 - ;; } - { .bbb; nop.b 0; -(p2) br.call.dptk.clr b0 =3D b2 - br.call.dptk.clr b0 =3D b2 - ;; } - { .bbb; nop.b 0; -(p2) br.call.dptk.few b0 =3D b2 - br.call.dptk.few b0 =3D b2 - ;; } - { .bbb; nop.b 0; -(p2) br.call.dptk.few.clr b0 =3D b2 - br.call.dptk.few.clr b0 =3D b2 - ;; } - { .bbb; nop.b 0; -(p2) br.call.dptk.many b0 =3D b2 - br.call.dptk.many b0 =3D b2 - ;; } - { .bbb; nop.b 0; -(p2) br.call.dptk.many.clr b0 =3D b2 - br.call.dptk.many.clr b0 =3D b2 - ;; } - { .bbb; nop.b 0; -(p2) br.call.dpnt b0 =3D b2 - br.call.dpnt b0 =3D b2 - ;; } - { .bbb; nop.b 0; -(p2) br.call.dpnt.clr b0 =3D b2 - br.call.dpnt.clr b0 =3D b2 - ;; } - { .bbb; nop.b 0; -(p2) br.call.dpnt.few b0 =3D b2 - br.call.dpnt.few b0 =3D b2 - ;; } - { .bbb; nop.b 0; -(p2) br.call.dpnt.few.clr b0 =3D b2 - br.call.dpnt.few.clr b0 =3D b2 - ;; } - { .bbb; nop.b 0; -(p2) br.call.dpnt.many b0 =3D b2 - br.call.dpnt.many b0 =3D b2 - ;; } - { .bbb; nop.b 0; -(p2) br.call.dpnt.many.clr b0 =3D b2 - br.call.dpnt.many.clr b0 =3D b2 - ;; } - - { .bbb; break.b 0; nop.b 0 - brp.sptk .L0, .L2 - ;; } - { .bbb; break.b 0; nop.b 0 - brp.sptk.imp .L0, .L2 - ;; } -.L2: - { .bbb; break.b 0; nop.b 0 - brp.loop .L0, .L3 - ;; } - { .bbb; break.b 0; nop.b 0 - brp.loop.imp .L0, .L3 - ;; } -.L3: - { .bbb; break.b 0; nop.b 0 - brp.dptk .L0, .L4 - ;; } - { .bbb; break.b 0; nop.b 0 - brp.dptk.imp .L0, .L4 - ;; } -.L4: - { .bbb; break.b 0; nop.b 0 - brp.exit .L0, .L5 - ;; } - { .bbb; break.b 0; nop.b 0 - brp.exit.imp .L0, .L5 - ;; } -.L5: - - { .bbb; break.b 0; nop.b 0 - brp.sptk b3, .L6 - ;; } - { .bbb; break.b 0; nop.b 0 - brp.sptk.imp b3, .L6 - ;; } -.L6: - { .bbb; break.b 0; nop.b 0 - brp.dptk b3, .L7 - ;; } - { .bbb; break.b 0; nop.b 0 - brp.dptk.imp b3, .L7 - ;; } -.L7: - - { .bbb; break.b 0; nop.b 0 - brp.ret.sptk b3, .L8 - ;; } - { .bbb; break.b 0; nop.b 0 - brp.ret.sptk.imp b3, .L8 - ;; } -.L8: - { .bbb; break.b 0; nop.b 0 - brp.ret.dptk b3, .L9 - ;; } - { .bbb; break.b 0; nop.b 0 - brp.ret.dptk.imp b3, .L9 - ;; } -.L9: - -.space 5888 - { .bbb; nop.b 0; nop.b 0; cover ;; } - { .bbb; nop.b 0; nop.b 0; clrrrb ;; } - { .bbb; nop.b 0; nop.b 0; clrrrb.pr ;; } - { .bbb; nop.b 0; nop.b 0; rfi ;; } - { .bbb; nop.b 0; nop.b 0; bsw.0 ;; } - { .bbb; nop.b 0; nop.b 0; bsw.1 ;; } - { .bbb; nop.b 0; nop.b 0; epc ;; } - -.L1: - - # instructions added by SDM2.1: - - break.b 0x1ffff - hint.b @pause - hint.b 0x1ffff - nop.b 0x1ffff - - # instructions added by SDM2.2: - vmsw.0 - vmsw.1 diff --git a/gas/testsuite/gas/ia64/opc-f.d b/gas/testsuite/gas/ia64/opc-f.d deleted file mode 100644 index 0dfa8811cd1..00000000000 --- a/gas/testsuite/gas/ia64/opc-f.d +++ /dev/null @@ -1,1572 +0,0 @@ -# as: -xnone -mtune=3Ditanium1 -# objdump: -d --disassemble-zeroes -# name: ia64 opc-f - -.*: +file format .* - -Disassembly of section \.text: - -0+000 <_start>: - 0: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 6: 40 38 14 0c 40 00 fma\.s0 f4=3Df5,f6,f7 - c: 00 00 00 20 nop\.b 0x0 - 10: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 16: 40 38 14 0c 40 00 fma\.s0 f4=3Df5,f6,f7 - 1c: 00 00 00 20 nop\.b 0x0 - 20: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 26: 40 38 14 0c 41 00 fma\.s1 f4=3Df5,f6,f7 - 2c: 00 00 00 20 nop\.b 0x0 - 30: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 36: 40 38 14 0c 42 00 fma\.s2 f4=3Df5,f6,f7 - 3c: 00 00 00 20 nop\.b 0x0 - 40: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 46: 40 38 14 0c 43 00 fma\.s3 f4=3Df5,f6,f7 - 4c: 00 00 00 20 nop\.b 0x0 - 50: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 56: 40 38 14 0c 44 00 fma\.s\.s0 f4=3Df5,f6,f7 - 5c: 00 00 00 20 nop\.b 0x0 - 60: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 66: 40 38 14 0c 44 00 fma\.s\.s0 f4=3Df5,f6,f7 - 6c: 00 00 00 20 nop\.b 0x0 - 70: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 76: 40 38 14 0c 45 00 fma\.s\.s1 f4=3Df5,f6,f7 - 7c: 00 00 00 20 nop\.b 0x0 - 80: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 86: 40 38 14 0c 46 00 fma\.s\.s2 f4=3Df5,f6,f7 - 8c: 00 00 00 20 nop\.b 0x0 - 90: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 96: 40 38 14 0c 47 00 fma\.s\.s3 f4=3Df5,f6,f7 - 9c: 00 00 00 20 nop\.b 0x0 - a0: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - a6: 40 38 14 0c 48 00 fma\.d\.s0 f4=3Df5,f6,f7 - ac: 00 00 00 20 nop\.b 0x0 - b0: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - b6: 40 38 14 0c 48 00 fma\.d\.s0 f4=3Df5,f6,f7 - bc: 00 00 00 20 nop\.b 0x0 - c0: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - c6: 40 38 14 0c 49 00 fma\.d\.s1 f4=3Df5,f6,f7 - cc: 00 00 00 20 nop\.b 0x0 - d0: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - d6: 40 38 14 0c 4a 00 fma\.d\.s2 f4=3Df5,f6,f7 - dc: 00 00 00 20 nop\.b 0x0 - e0: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - e6: 40 38 14 0c 4b 00 fma\.d\.s3 f4=3Df5,f6,f7 - ec: 00 00 00 20 nop\.b 0x0 - f0: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - f6: 40 38 14 0c 4c 00 fpma\.s0 f4=3Df5,f6,f7 - fc: 00 00 00 20 nop\.b 0x0 - 100: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 106: 40 38 14 0c 4c 00 fpma\.s0 f4=3Df5,f6,f7 - 10c: 00 00 00 20 nop\.b 0x0 - 110: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 116: 40 38 14 0c 4d 00 fpma\.s1 f4=3Df5,f6,f7 - 11c: 00 00 00 20 nop\.b 0x0 - 120: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 126: 40 38 14 0c 4e 00 fpma\.s2 f4=3Df5,f6,f7 - 12c: 00 00 00 20 nop\.b 0x0 - 130: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 136: 40 38 14 0c 4f 00 fpma\.s3 f4=3Df5,f6,f7 - 13c: 00 00 00 20 nop\.b 0x0 - 140: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 146: 40 38 14 0c 50 00 fms\.s0 f4=3Df5,f6,f7 - 14c: 00 00 00 20 nop\.b 0x0 - 150: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 156: 40 38 14 0c 50 00 fms\.s0 f4=3Df5,f6,f7 - 15c: 00 00 00 20 nop\.b 0x0 - 160: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 166: 40 38 14 0c 51 00 fms\.s1 f4=3Df5,f6,f7 - 16c: 00 00 00 20 nop\.b 0x0 - 170: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 176: 40 38 14 0c 52 00 fms\.s2 f4=3Df5,f6,f7 - 17c: 00 00 00 20 nop\.b 0x0 - 180: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 186: 40 38 14 0c 53 00 fms\.s3 f4=3Df5,f6,f7 - 18c: 00 00 00 20 nop\.b 0x0 - 190: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 196: 40 38 14 0c 54 00 fms\.s\.s0 f4=3Df5,f6,f7 - 19c: 00 00 00 20 nop\.b 0x0 - 1a0: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 1a6: 40 38 14 0c 54 00 fms\.s\.s0 f4=3Df5,f6,f7 - 1ac: 00 00 00 20 nop\.b 0x0 - 1b0: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 1b6: 40 38 14 0c 55 00 fms\.s\.s1 f4=3Df5,f6,f7 - 1bc: 00 00 00 20 nop\.b 0x0 - 1c0: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 1c6: 40 38 14 0c 56 00 fms\.s\.s2 f4=3Df5,f6,f7 - 1cc: 00 00 00 20 nop\.b 0x0 - 1d0: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 1d6: 40 38 14 0c 57 00 fms\.s\.s3 f4=3Df5,f6,f7 - 1dc: 00 00 00 20 nop\.b 0x0 - 1e0: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 1e6: 40 38 14 0c 58 00 fms\.d\.s0 f4=3Df5,f6,f7 - 1ec: 00 00 00 20 nop\.b 0x0 - 1f0: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 1f6: 40 38 14 0c 58 00 fms\.d\.s0 f4=3Df5,f6,f7 - 1fc: 00 00 00 20 nop\.b 0x0 - 200: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 206: 40 38 14 0c 59 00 fms\.d\.s1 f4=3Df5,f6,f7 - 20c: 00 00 00 20 nop\.b 0x0 - 210: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 216: 40 38 14 0c 5a 00 fms\.d\.s2 f4=3Df5,f6,f7 - 21c: 00 00 00 20 nop\.b 0x0 - 220: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 226: 40 38 14 0c 5b 00 fms\.d\.s3 f4=3Df5,f6,f7 - 22c: 00 00 00 20 nop\.b 0x0 - 230: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 236: 40 38 14 0c 5c 00 fpms\.s0 f4=3Df5,f6,f7 - 23c: 00 00 00 20 nop\.b 0x0 - 240: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 246: 40 38 14 0c 5c 00 fpms\.s0 f4=3Df5,f6,f7 - 24c: 00 00 00 20 nop\.b 0x0 - 250: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 256: 40 38 14 0c 5d 00 fpms\.s1 f4=3Df5,f6,f7 - 25c: 00 00 00 20 nop\.b 0x0 - 260: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 266: 40 38 14 0c 5e 00 fpms\.s2 f4=3Df5,f6,f7 - 26c: 00 00 00 20 nop\.b 0x0 - 270: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 276: 40 38 14 0c 5f 00 fpms\.s3 f4=3Df5,f6,f7 - 27c: 00 00 00 20 nop\.b 0x0 - 280: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 286: 40 38 14 0c 60 00 fnma\.s0 f4=3Df5,f6,f7 - 28c: 00 00 00 20 nop\.b 0x0 - 290: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 296: 40 38 14 0c 60 00 fnma\.s0 f4=3Df5,f6,f7 - 29c: 00 00 00 20 nop\.b 0x0 - 2a0: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 2a6: 40 38 14 0c 61 00 fnma\.s1 f4=3Df5,f6,f7 - 2ac: 00 00 00 20 nop\.b 0x0 - 2b0: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 2b6: 40 38 14 0c 62 00 fnma\.s2 f4=3Df5,f6,f7 - 2bc: 00 00 00 20 nop\.b 0x0 - 2c0: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 2c6: 40 38 14 0c 63 00 fnma\.s3 f4=3Df5,f6,f7 - 2cc: 00 00 00 20 nop\.b 0x0 - 2d0: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 2d6: 40 38 14 0c 64 00 fnma\.s\.s0 f4=3Df5,f6,f7 - 2dc: 00 00 00 20 nop\.b 0x0 - 2e0: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 2e6: 40 38 14 0c 64 00 fnma\.s\.s0 f4=3Df5,f6,f7 - 2ec: 00 00 00 20 nop\.b 0x0 - 2f0: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 2f6: 40 38 14 0c 65 00 fnma\.s\.s1 f4=3Df5,f6,f7 - 2fc: 00 00 00 20 nop\.b 0x0 - 300: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 306: 40 38 14 0c 66 00 fnma\.s\.s2 f4=3Df5,f6,f7 - 30c: 00 00 00 20 nop\.b 0x0 - 310: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 316: 40 38 14 0c 67 00 fnma\.s\.s3 f4=3Df5,f6,f7 - 31c: 00 00 00 20 nop\.b 0x0 - 320: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 326: 40 38 14 0c 68 00 fnma\.d\.s0 f4=3Df5,f6,f7 - 32c: 00 00 00 20 nop\.b 0x0 - 330: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 336: 40 38 14 0c 68 00 fnma\.d\.s0 f4=3Df5,f6,f7 - 33c: 00 00 00 20 nop\.b 0x0 - 340: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 346: 40 38 14 0c 69 00 fnma\.d\.s1 f4=3Df5,f6,f7 - 34c: 00 00 00 20 nop\.b 0x0 - 350: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 356: 40 38 14 0c 6a 00 fnma\.d\.s2 f4=3Df5,f6,f7 - 35c: 00 00 00 20 nop\.b 0x0 - 360: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 366: 40 38 14 0c 6b 00 fnma\.d\.s3 f4=3Df5,f6,f7 - 36c: 00 00 00 20 nop\.b 0x0 - 370: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 376: 40 38 14 0c 6c 00 fpnma\.s0 f4=3Df5,f6,f7 - 37c: 00 00 00 20 nop\.b 0x0 - 380: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 386: 40 38 14 0c 6c 00 fpnma\.s0 f4=3Df5,f6,f7 - 38c: 00 00 00 20 nop\.b 0x0 - 390: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 396: 40 38 14 0c 6d 00 fpnma\.s1 f4=3Df5,f6,f7 - 39c: 00 00 00 20 nop\.b 0x0 - 3a0: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 3a6: 40 38 14 0c 6e 00 fpnma\.s2 f4=3Df5,f6,f7 - 3ac: 00 00 00 20 nop\.b 0x0 - 3b0: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 3b6: 40 38 14 0c 6f 00 fpnma\.s3 f4=3Df5,f6,f7 - 3bc: 00 00 00 20 nop\.b 0x0 - 3c0: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 3c6: 40 00 14 0c 40 00 fmpy\.s0 f4=3Df5,f6 - 3cc: 00 00 00 20 nop\.b 0x0 - 3d0: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 3d6: 40 00 14 0c 40 00 fmpy\.s0 f4=3Df5,f6 - 3dc: 00 00 00 20 nop\.b 0x0 - 3e0: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 3e6: 40 00 14 0c 41 00 fmpy\.s1 f4=3Df5,f6 - 3ec: 00 00 00 20 nop\.b 0x0 - 3f0: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 3f6: 40 00 14 0c 42 00 fmpy\.s2 f4=3Df5,f6 - 3fc: 00 00 00 20 nop\.b 0x0 - 400: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 406: 40 00 14 0c 43 00 fmpy\.s3 f4=3Df5,f6 - 40c: 00 00 00 20 nop\.b 0x0 - 410: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 416: 40 00 14 0c 44 00 fmpy\.s\.s0 f4=3Df5,f6 - 41c: 00 00 00 20 nop\.b 0x0 - 420: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 426: 40 00 14 0c 44 00 fmpy\.s\.s0 f4=3Df5,f6 - 42c: 00 00 00 20 nop\.b 0x0 - 430: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 436: 40 00 14 0c 45 00 fmpy\.s\.s1 f4=3Df5,f6 - 43c: 00 00 00 20 nop\.b 0x0 - 440: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 446: 40 00 14 0c 46 00 fmpy\.s\.s2 f4=3Df5,f6 - 44c: 00 00 00 20 nop\.b 0x0 - 450: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 456: 40 00 14 0c 47 00 fmpy\.s\.s3 f4=3Df5,f6 - 45c: 00 00 00 20 nop\.b 0x0 - 460: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 466: 40 00 14 0c 48 00 fmpy\.d\.s0 f4=3Df5,f6 - 46c: 00 00 00 20 nop\.b 0x0 - 470: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 476: 40 00 14 0c 48 00 fmpy\.d\.s0 f4=3Df5,f6 - 47c: 00 00 00 20 nop\.b 0x0 - 480: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 486: 40 00 14 0c 49 00 fmpy\.d\.s1 f4=3Df5,f6 - 48c: 00 00 00 20 nop\.b 0x0 - 490: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 496: 40 00 14 0c 4a 00 fmpy\.d\.s2 f4=3Df5,f6 - 49c: 00 00 00 20 nop\.b 0x0 - 4a0: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 4a6: 40 00 14 0c 4b 00 fmpy\.d\.s3 f4=3Df5,f6 - 4ac: 00 00 00 20 nop\.b 0x0 - 4b0: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 4b6: 40 00 14 0c 4c 00 fpmpy\.s0 f4=3Df5,f6 - 4bc: 00 00 00 20 nop\.b 0x0 - 4c0: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 4c6: 40 00 14 0c 4c 00 fpmpy\.s0 f4=3Df5,f6 - 4cc: 00 00 00 20 nop\.b 0x0 - 4d0: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 4d6: 40 00 14 0c 4d 00 fpmpy\.s1 f4=3Df5,f6 - 4dc: 00 00 00 20 nop\.b 0x0 - 4e0: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 4e6: 40 00 14 0c 4e 00 fpmpy\.s2 f4=3Df5,f6 - 4ec: 00 00 00 20 nop\.b 0x0 - 4f0: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 4f6: 40 00 14 0c 4f 00 fpmpy\.s3 f4=3Df5,f6 - 4fc: 00 00 00 20 nop\.b 0x0 - 500: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 506: 40 30 14 02 40 00 fadd\.s0 f4=3Df5,f6 - 50c: 00 00 00 20 nop\.b 0x0 - 510: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 516: 40 30 14 02 40 00 fadd\.s0 f4=3Df5,f6 - 51c: 00 00 00 20 nop\.b 0x0 - 520: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 526: 40 30 14 02 41 00 fadd\.s1 f4=3Df5,f6 - 52c: 00 00 00 20 nop\.b 0x0 - 530: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 536: 40 30 14 02 42 00 fadd\.s2 f4=3Df5,f6 - 53c: 00 00 00 20 nop\.b 0x0 - 540: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 546: 40 30 14 02 43 00 fadd\.s3 f4=3Df5,f6 - 54c: 00 00 00 20 nop\.b 0x0 - 550: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 556: 40 30 14 02 44 00 fadd\.s\.s0 f4=3Df5,f6 - 55c: 00 00 00 20 nop\.b 0x0 - 560: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 566: 40 30 14 02 44 00 fadd\.s\.s0 f4=3Df5,f6 - 56c: 00 00 00 20 nop\.b 0x0 - 570: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 576: 40 30 14 02 45 00 fadd\.s\.s1 f4=3Df5,f6 - 57c: 00 00 00 20 nop\.b 0x0 - 580: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 586: 40 30 14 02 46 00 fadd\.s\.s2 f4=3Df5,f6 - 58c: 00 00 00 20 nop\.b 0x0 - 590: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 596: 40 30 14 02 47 00 fadd\.s\.s3 f4=3Df5,f6 - 59c: 00 00 00 20 nop\.b 0x0 - 5a0: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 5a6: 40 30 14 02 48 00 fadd\.d\.s0 f4=3Df5,f6 - 5ac: 00 00 00 20 nop\.b 0x0 - 5b0: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 5b6: 40 30 14 02 48 00 fadd\.d\.s0 f4=3Df5,f6 - 5bc: 00 00 00 20 nop\.b 0x0 - 5c0: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 5c6: 40 30 14 02 49 00 fadd\.d\.s1 f4=3Df5,f6 - 5cc: 00 00 00 20 nop\.b 0x0 - 5d0: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 5d6: 40 30 14 02 4a 00 fadd\.d\.s2 f4=3Df5,f6 - 5dc: 00 00 00 20 nop\.b 0x0 - 5e0: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 5e6: 40 30 14 02 4b 00 fadd\.d\.s3 f4=3Df5,f6 - 5ec: 00 00 00 20 nop\.b 0x0 - 5f0: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 5f6: 40 30 14 02 50 00 fsub\.s0 f4=3Df5,f6 - 5fc: 00 00 00 20 nop\.b 0x0 - 600: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 606: 40 30 14 02 50 00 fsub\.s0 f4=3Df5,f6 - 60c: 00 00 00 20 nop\.b 0x0 - 610: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 616: 40 30 14 02 51 00 fsub\.s1 f4=3Df5,f6 - 61c: 00 00 00 20 nop\.b 0x0 - 620: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 626: 40 30 14 02 52 00 fsub\.s2 f4=3Df5,f6 - 62c: 00 00 00 20 nop\.b 0x0 - 630: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 636: 40 30 14 02 53 00 fsub\.s3 f4=3Df5,f6 - 63c: 00 00 00 20 nop\.b 0x0 - 640: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 646: 40 30 14 02 54 00 fsub\.s\.s0 f4=3Df5,f6 - 64c: 00 00 00 20 nop\.b 0x0 - 650: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 656: 40 30 14 02 54 00 fsub\.s\.s0 f4=3Df5,f6 - 65c: 00 00 00 20 nop\.b 0x0 - 660: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 666: 40 30 14 02 55 00 fsub\.s\.s1 f4=3Df5,f6 - 66c: 00 00 00 20 nop\.b 0x0 - 670: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 676: 40 30 14 02 56 00 fsub\.s\.s2 f4=3Df5,f6 - 67c: 00 00 00 20 nop\.b 0x0 - 680: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 686: 40 30 14 02 57 00 fsub\.s\.s3 f4=3Df5,f6 - 68c: 00 00 00 20 nop\.b 0x0 - 690: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 696: 40 30 14 02 58 00 fsub\.d\.s0 f4=3Df5,f6 - 69c: 00 00 00 20 nop\.b 0x0 - 6a0: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 6a6: 40 30 14 02 58 00 fsub\.d\.s0 f4=3Df5,f6 - 6ac: 00 00 00 20 nop\.b 0x0 - 6b0: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 6b6: 40 30 14 02 59 00 fsub\.d\.s1 f4=3Df5,f6 - 6bc: 00 00 00 20 nop\.b 0x0 - 6c0: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 6c6: 40 30 14 02 5a 00 fsub\.d\.s2 f4=3Df5,f6 - 6cc: 00 00 00 20 nop\.b 0x0 - 6d0: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 6d6: 40 30 14 02 5b 00 fsub\.d\.s3 f4=3Df5,f6 - 6dc: 00 00 00 20 nop\.b 0x0 - 6e0: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 6e6: 40 00 14 0c 60 00 fnmpy\.s0 f4=3Df5,f6 - 6ec: 00 00 00 20 nop\.b 0x0 - 6f0: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 6f6: 40 00 14 0c 60 00 fnmpy\.s0 f4=3Df5,f6 - 6fc: 00 00 00 20 nop\.b 0x0 - 700: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 706: 40 00 14 0c 61 00 fnmpy\.s1 f4=3Df5,f6 - 70c: 00 00 00 20 nop\.b 0x0 - 710: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 716: 40 00 14 0c 62 00 fnmpy\.s2 f4=3Df5,f6 - 71c: 00 00 00 20 nop\.b 0x0 - 720: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 726: 40 00 14 0c 63 00 fnmpy\.s3 f4=3Df5,f6 - 72c: 00 00 00 20 nop\.b 0x0 - 730: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 736: 40 00 14 0c 64 00 fnmpy\.s\.s0 f4=3Df5,f6 - 73c: 00 00 00 20 nop\.b 0x0 - 740: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 746: 40 00 14 0c 64 00 fnmpy\.s\.s0 f4=3Df5,f6 - 74c: 00 00 00 20 nop\.b 0x0 - 750: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 756: 40 00 14 0c 65 00 fnmpy\.s\.s1 f4=3Df5,f6 - 75c: 00 00 00 20 nop\.b 0x0 - 760: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 766: 40 00 14 0c 66 00 fnmpy\.s\.s2 f4=3Df5,f6 - 76c: 00 00 00 20 nop\.b 0x0 - 770: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 776: 40 00 14 0c 67 00 fnmpy\.s\.s3 f4=3Df5,f6 - 77c: 00 00 00 20 nop\.b 0x0 - 780: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 786: 40 00 14 0c 68 00 fnmpy\.d\.s0 f4=3Df5,f6 - 78c: 00 00 00 20 nop\.b 0x0 - 790: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 796: 40 00 14 0c 68 00 fnmpy\.d\.s0 f4=3Df5,f6 - 79c: 00 00 00 20 nop\.b 0x0 - 7a0: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 7a6: 40 00 14 0c 69 00 fnmpy\.d\.s1 f4=3Df5,f6 - 7ac: 00 00 00 20 nop\.b 0x0 - 7b0: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 7b6: 40 00 14 0c 6a 00 fnmpy\.d\.s2 f4=3Df5,f6 - 7bc: 00 00 00 20 nop\.b 0x0 - 7c0: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 7c6: 40 00 14 0c 6b 00 fnmpy\.d\.s3 f4=3Df5,f6 - 7cc: 00 00 00 20 nop\.b 0x0 - 7d0: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 7d6: 40 00 14 0c 6c 00 fpnmpy\.s0 f4=3Df5,f6 - 7dc: 00 00 00 20 nop\.b 0x0 - 7e0: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 7e6: 40 00 14 0c 6c 00 fpnmpy\.s0 f4=3Df5,f6 - 7ec: 00 00 00 20 nop\.b 0x0 - 7f0: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 7f6: 40 00 14 0c 6d 00 fpnmpy\.s1 f4=3Df5,f6 - 7fc: 00 00 00 20 nop\.b 0x0 - 800: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 806: 40 00 14 0c 6e 00 fpnmpy\.s2 f4=3Df5,f6 - 80c: 00 00 00 20 nop\.b 0x0 - 810: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 816: 40 00 14 0c 6f 00 fpnmpy\.s3 f4=3Df5,f6 - 81c: 00 00 00 20 nop\.b 0x0 - 820: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 826: 40 00 14 02 40 00 fnorm\.s0 f4=3Df5 - 82c: 00 00 00 20 nop\.b 0x0 - 830: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 836: 40 00 14 02 40 00 fnorm\.s0 f4=3Df5 - 83c: 00 00 00 20 nop\.b 0x0 - 840: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 846: 40 00 14 02 41 00 fnorm\.s1 f4=3Df5 - 84c: 00 00 00 20 nop\.b 0x0 - 850: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 856: 40 00 14 02 42 00 fnorm\.s2 f4=3Df5 - 85c: 00 00 00 20 nop\.b 0x0 - 860: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 866: 40 00 14 02 43 00 fnorm\.s3 f4=3Df5 - 86c: 00 00 00 20 nop\.b 0x0 - 870: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 876: 40 00 14 02 44 00 fnorm\.s\.s0 f4=3Df5 - 87c: 00 00 00 20 nop\.b 0x0 - 880: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 886: 40 00 14 02 44 00 fnorm\.s\.s0 f4=3Df5 - 88c: 00 00 00 20 nop\.b 0x0 - 890: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 896: 40 00 14 02 45 00 fnorm\.s\.s1 f4=3Df5 - 89c: 00 00 00 20 nop\.b 0x0 - 8a0: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 8a6: 40 00 14 02 46 00 fnorm\.s\.s2 f4=3Df5 - 8ac: 00 00 00 20 nop\.b 0x0 - 8b0: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 8b6: 40 00 14 02 47 00 fnorm\.s\.s3 f4=3Df5 - 8bc: 00 00 00 20 nop\.b 0x0 - 8c0: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 8c6: 40 00 14 02 48 00 fnorm\.d\.s0 f4=3Df5 - 8cc: 00 00 00 20 nop\.b 0x0 - 8d0: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 8d6: 40 00 14 02 48 00 fnorm\.d\.s0 f4=3Df5 - 8dc: 00 00 00 20 nop\.b 0x0 - 8e0: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 8e6: 40 00 14 02 49 00 fnorm\.d\.s1 f4=3Df5 - 8ec: 00 00 00 20 nop\.b 0x0 - 8f0: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 8f6: 40 00 14 02 4a 00 fnorm\.d\.s2 f4=3Df5 - 8fc: 00 00 00 20 nop\.b 0x0 - 900: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 906: 40 00 14 02 4b 00 fnorm\.d\.s3 f4=3Df5 - 90c: 00 00 00 20 nop\.b 0x0 - 910: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 916: 40 38 14 0c 74 00 xma\.l f4=3Df5,f6,f7 - 91c: 00 00 00 20 nop\.b 0x0 - 920: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 926: 40 38 14 0c 74 00 xma\.l f4=3Df5,f6,f7 - 92c: 00 00 00 20 nop\.b 0x0 - 930: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 936: 40 38 14 0c 77 00 xma\.h f4=3Df5,f6,f7 - 93c: 00 00 00 20 nop\.b 0x0 - 940: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 946: 40 38 14 0c 76 00 xma\.hu f4=3Df5,f6,f7 - 94c: 00 00 00 20 nop\.b 0x0 - 950: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 956: 40 00 14 0c 74 00 xmpy\.l f4=3Df5,f6 - 95c: 00 00 00 20 nop\.b 0x0 - 960: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 966: 40 00 14 0c 74 00 xmpy\.l f4=3Df5,f6 - 96c: 00 00 00 20 nop\.b 0x0 - 970: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 976: 40 00 14 0c 77 00 xmpy\.h f4=3Df5,f6 - 97c: 00 00 00 20 nop\.b 0x0 - 980: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 986: 40 00 14 0c 76 00 xmpy\.hu f4=3Df5,f6 - 98c: 00 00 00 20 nop\.b 0x0 - 990: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 996: 40 38 14 0c 70 00 fselect f4=3Df5,f6,f7 - 99c: 00 00 00 20 nop\.b 0x0 - 9a0: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 9a6: 30 20 14 08 20 00 fcmp\.eq\.s0 p3,p4=3Df4,f5 - 9ac: 00 00 00 20 nop\.b 0x0 - 9b0: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 9b6: 30 20 14 08 20 00 fcmp\.eq\.s0 p3,p4=3Df4,f5 - 9bc: 00 00 00 20 nop\.b 0x0 - 9c0: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 9c6: 30 20 14 08 21 00 fcmp\.eq\.s1 p3,p4=3Df4,f5 - 9cc: 00 00 00 20 nop\.b 0x0 - 9d0: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 9d6: 30 20 14 08 22 00 fcmp\.eq\.s2 p3,p4=3Df4,f5 - 9dc: 00 00 00 20 nop\.b 0x0 - 9e0: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 9e6: 30 20 14 08 23 00 fcmp\.eq\.s3 p3,p4=3Df4,f5 - 9ec: 00 00 00 20 nop\.b 0x0 - 9f0: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 9f6: 30 24 14 08 20 00 fcmp\.eq\.unc\.s0 p3,p4=3Df4,f5 - 9fc: 00 00 00 20 nop\.b 0x0 - a00: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - a06: 30 24 14 08 20 00 fcmp\.eq\.unc\.s0 p3,p4=3Df4,f5 - a0c: 00 00 00 20 nop\.b 0x0 - a10: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - a16: 30 24 14 08 21 00 fcmp\.eq\.unc\.s1 p3,p4=3Df4,f5 - a1c: 00 00 00 20 nop\.b 0x0 - a20: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - a26: 30 24 14 08 22 00 fcmp\.eq\.unc\.s2 p3,p4=3Df4,f5 - a2c: 00 00 00 20 nop\.b 0x0 - a30: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - a36: 30 24 14 08 23 00 fcmp\.eq\.unc\.s3 p3,p4=3Df4,f5 - a3c: 00 00 00 20 nop\.b 0x0 - a40: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - a46: 30 20 14 08 24 00 fcmp\.lt\.s0 p3,p4=3Df4,f5 - a4c: 00 00 00 20 nop\.b 0x0 - a50: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - a56: 30 20 14 08 24 00 fcmp\.lt\.s0 p3,p4=3Df4,f5 - a5c: 00 00 00 20 nop\.b 0x0 - a60: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - a66: 30 20 14 08 25 00 fcmp\.lt\.s1 p3,p4=3Df4,f5 - a6c: 00 00 00 20 nop\.b 0x0 - a70: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - a76: 30 20 14 08 26 00 fcmp\.lt\.s2 p3,p4=3Df4,f5 - a7c: 00 00 00 20 nop\.b 0x0 - a80: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - a86: 30 20 14 08 27 00 fcmp\.lt\.s3 p3,p4=3Df4,f5 - a8c: 00 00 00 20 nop\.b 0x0 - a90: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - a96: 30 24 14 08 24 00 fcmp\.lt\.unc\.s0 p3,p4=3Df4,f5 - a9c: 00 00 00 20 nop\.b 0x0 - aa0: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - aa6: 30 24 14 08 24 00 fcmp\.lt\.unc\.s0 p3,p4=3Df4,f5 - aac: 00 00 00 20 nop\.b 0x0 - ab0: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - ab6: 30 24 14 08 25 00 fcmp\.lt\.unc\.s1 p3,p4=3Df4,f5 - abc: 00 00 00 20 nop\.b 0x0 - ac0: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - ac6: 30 24 14 08 26 00 fcmp\.lt\.unc\.s2 p3,p4=3Df4,f5 - acc: 00 00 00 20 nop\.b 0x0 - ad0: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - ad6: 30 24 14 08 27 00 fcmp\.lt\.unc\.s3 p3,p4=3Df4,f5 - adc: 00 00 00 20 nop\.b 0x0 - ae0: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - ae6: 30 20 14 88 20 00 fcmp\.le\.s0 p3,p4=3Df4,f5 - aec: 00 00 00 20 nop\.b 0x0 - af0: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - af6: 30 20 14 88 20 00 fcmp\.le\.s0 p3,p4=3Df4,f5 - afc: 00 00 00 20 nop\.b 0x0 - b00: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - b06: 30 20 14 88 21 00 fcmp\.le\.s1 p3,p4=3Df4,f5 - b0c: 00 00 00 20 nop\.b 0x0 - b10: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - b16: 30 20 14 88 22 00 fcmp\.le\.s2 p3,p4=3Df4,f5 - b1c: 00 00 00 20 nop\.b 0x0 - b20: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - b26: 30 20 14 88 23 00 fcmp\.le\.s3 p3,p4=3Df4,f5 - b2c: 00 00 00 20 nop\.b 0x0 - b30: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - b36: 30 24 14 88 20 00 fcmp\.le\.unc\.s0 p3,p4=3Df4,f5 - b3c: 00 00 00 20 nop\.b 0x0 - b40: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - b46: 30 24 14 88 20 00 fcmp\.le\.unc\.s0 p3,p4=3Df4,f5 - b4c: 00 00 00 20 nop\.b 0x0 - b50: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - b56: 30 24 14 88 21 00 fcmp\.le\.unc\.s1 p3,p4=3Df4,f5 - b5c: 00 00 00 20 nop\.b 0x0 - b60: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - b66: 30 24 14 88 22 00 fcmp\.le\.unc\.s2 p3,p4=3Df4,f5 - b6c: 00 00 00 20 nop\.b 0x0 - b70: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - b76: 30 24 14 88 23 00 fcmp\.le\.unc\.s3 p3,p4=3Df4,f5 - b7c: 00 00 00 20 nop\.b 0x0 - b80: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - b86: 30 20 14 88 24 00 fcmp\.unord\.s0 p3,p4=3Df4,f5 - b8c: 00 00 00 20 nop\.b 0x0 - b90: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - b96: 30 20 14 88 24 00 fcmp\.unord\.s0 p3,p4=3Df4,f5 - b9c: 00 00 00 20 nop\.b 0x0 - ba0: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - ba6: 30 20 14 88 25 00 fcmp\.unord\.s1 p3,p4=3Df4,f5 - bac: 00 00 00 20 nop\.b 0x0 - bb0: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - bb6: 30 20 14 88 26 00 fcmp\.unord\.s2 p3,p4=3Df4,f5 - bbc: 00 00 00 20 nop\.b 0x0 - bc0: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - bc6: 30 20 14 88 27 00 fcmp\.unord\.s3 p3,p4=3Df4,f5 - bcc: 00 00 00 20 nop\.b 0x0 - bd0: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - bd6: 30 24 14 88 24 00 fcmp\.unord\.unc\.s0 p3,p4=3Df4,f5 - bdc: 00 00 00 20 nop\.b 0x0 - be0: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - be6: 30 24 14 88 24 00 fcmp\.unord\.unc\.s0 p3,p4=3Df4,f5 - bec: 00 00 00 20 nop\.b 0x0 - bf0: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - bf6: 30 24 14 88 25 00 fcmp\.unord\.unc\.s1 p3,p4=3Df4,f5 - bfc: 00 00 00 20 nop\.b 0x0 - c00: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - c06: 30 24 14 88 26 00 fcmp\.unord\.unc\.s2 p3,p4=3Df4,f5 - c0c: 00 00 00 20 nop\.b 0x0 - c10: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - c16: 30 24 14 88 27 00 fcmp\.unord\.unc\.s3 p3,p4=3Df4,f5 - c1c: 00 00 00 20 nop\.b 0x0 - c20: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - c26: 30 28 10 08 24 00 fcmp\.lt\.s0 p3,p4=3Df5,f4 - c2c: 00 00 00 20 nop\.b 0x0 - c30: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - c36: 30 28 10 08 24 00 fcmp\.lt\.s0 p3,p4=3Df5,f4 - c3c: 00 00 00 20 nop\.b 0x0 - c40: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - c46: 30 28 10 08 25 00 fcmp\.lt\.s1 p3,p4=3Df5,f4 - c4c: 00 00 00 20 nop\.b 0x0 - c50: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - c56: 30 28 10 08 26 00 fcmp\.lt\.s2 p3,p4=3Df5,f4 - c5c: 00 00 00 20 nop\.b 0x0 - c60: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - c66: 30 28 10 08 27 00 fcmp\.lt\.s3 p3,p4=3Df5,f4 - c6c: 00 00 00 20 nop\.b 0x0 - c70: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - c76: 30 2c 10 08 24 00 fcmp\.lt\.unc\.s0 p3,p4=3Df5,f4 - c7c: 00 00 00 20 nop\.b 0x0 - c80: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - c86: 30 2c 10 08 24 00 fcmp\.lt\.unc\.s0 p3,p4=3Df5,f4 - c8c: 00 00 00 20 nop\.b 0x0 - c90: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - c96: 30 2c 10 08 25 00 fcmp\.lt\.unc\.s1 p3,p4=3Df5,f4 - c9c: 00 00 00 20 nop\.b 0x0 - ca0: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - ca6: 30 2c 10 08 26 00 fcmp\.lt\.unc\.s2 p3,p4=3Df5,f4 - cac: 00 00 00 20 nop\.b 0x0 - cb0: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - cb6: 30 2c 10 08 27 00 fcmp\.lt\.unc\.s3 p3,p4=3Df5,f4 - cbc: 00 00 00 20 nop\.b 0x0 - cc0: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - cc6: 30 28 10 88 20 00 fcmp\.le\.s0 p3,p4=3Df5,f4 - ccc: 00 00 00 20 nop\.b 0x0 - cd0: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - cd6: 30 28 10 88 20 00 fcmp\.le\.s0 p3,p4=3Df5,f4 - cdc: 00 00 00 20 nop\.b 0x0 - ce0: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - ce6: 30 28 10 88 21 00 fcmp\.le\.s1 p3,p4=3Df5,f4 - cec: 00 00 00 20 nop\.b 0x0 - cf0: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - cf6: 30 28 10 88 22 00 fcmp\.le\.s2 p3,p4=3Df5,f4 - cfc: 00 00 00 20 nop\.b 0x0 - d00: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - d06: 30 28 10 88 23 00 fcmp\.le\.s3 p3,p4=3Df5,f4 - d0c: 00 00 00 20 nop\.b 0x0 - d10: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - d16: 30 2c 10 88 20 00 fcmp\.le\.unc\.s0 p3,p4=3Df5,f4 - d1c: 00 00 00 20 nop\.b 0x0 - d20: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - d26: 30 2c 10 88 20 00 fcmp\.le\.unc\.s0 p3,p4=3Df5,f4 - d2c: 00 00 00 20 nop\.b 0x0 - d30: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - d36: 30 2c 10 88 21 00 fcmp\.le\.unc\.s1 p3,p4=3Df5,f4 - d3c: 00 00 00 20 nop\.b 0x0 - d40: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - d46: 30 2c 10 88 22 00 fcmp\.le\.unc\.s2 p3,p4=3Df5,f4 - d4c: 00 00 00 20 nop\.b 0x0 - d50: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - d56: 30 2c 10 88 23 00 fcmp\.le\.unc\.s3 p3,p4=3Df5,f4 - d5c: 00 00 00 20 nop\.b 0x0 - d60: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - d66: 40 20 14 06 20 00 fcmp\.eq\.s0 p4,p3=3Df4,f5 - d6c: 00 00 00 20 nop\.b 0x0 - d70: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - d76: 40 20 14 06 20 00 fcmp\.eq\.s0 p4,p3=3Df4,f5 - d7c: 00 00 00 20 nop\.b 0x0 - d80: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - d86: 40 20 14 06 21 00 fcmp\.eq\.s1 p4,p3=3Df4,f5 - d8c: 00 00 00 20 nop\.b 0x0 - d90: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - d96: 40 20 14 06 22 00 fcmp\.eq\.s2 p4,p3=3Df4,f5 - d9c: 00 00 00 20 nop\.b 0x0 - da0: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - da6: 40 20 14 06 23 00 fcmp\.eq\.s3 p4,p3=3Df4,f5 - dac: 00 00 00 20 nop\.b 0x0 - db0: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - db6: 40 24 14 06 20 00 fcmp\.eq\.unc\.s0 p4,p3=3Df4,f5 - dbc: 00 00 00 20 nop\.b 0x0 - dc0: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - dc6: 40 24 14 06 20 00 fcmp\.eq\.unc\.s0 p4,p3=3Df4,f5 - dcc: 00 00 00 20 nop\.b 0x0 - dd0: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - dd6: 40 24 14 06 21 00 fcmp\.eq\.unc\.s1 p4,p3=3Df4,f5 - ddc: 00 00 00 20 nop\.b 0x0 - de0: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - de6: 40 24 14 06 22 00 fcmp\.eq\.unc\.s2 p4,p3=3Df4,f5 - dec: 00 00 00 20 nop\.b 0x0 - df0: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - df6: 40 24 14 06 23 00 fcmp\.eq\.unc\.s3 p4,p3=3Df4,f5 - dfc: 00 00 00 20 nop\.b 0x0 - e00: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - e06: 40 20 14 06 24 00 fcmp\.lt\.s0 p4,p3=3Df4,f5 - e0c: 00 00 00 20 nop\.b 0x0 - e10: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - e16: 40 20 14 06 24 00 fcmp\.lt\.s0 p4,p3=3Df4,f5 - e1c: 00 00 00 20 nop\.b 0x0 - e20: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - e26: 40 20 14 06 25 00 fcmp\.lt\.s1 p4,p3=3Df4,f5 - e2c: 00 00 00 20 nop\.b 0x0 - e30: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - e36: 40 20 14 06 26 00 fcmp\.lt\.s2 p4,p3=3Df4,f5 - e3c: 00 00 00 20 nop\.b 0x0 - e40: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - e46: 40 20 14 06 27 00 fcmp\.lt\.s3 p4,p3=3Df4,f5 - e4c: 00 00 00 20 nop\.b 0x0 - e50: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - e56: 40 24 14 06 24 00 fcmp\.lt\.unc\.s0 p4,p3=3Df4,f5 - e5c: 00 00 00 20 nop\.b 0x0 - e60: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - e66: 40 24 14 06 24 00 fcmp\.lt\.unc\.s0 p4,p3=3Df4,f5 - e6c: 00 00 00 20 nop\.b 0x0 - e70: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - e76: 40 24 14 06 25 00 fcmp\.lt\.unc\.s1 p4,p3=3Df4,f5 - e7c: 00 00 00 20 nop\.b 0x0 - e80: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - e86: 40 24 14 06 26 00 fcmp\.lt\.unc\.s2 p4,p3=3Df4,f5 - e8c: 00 00 00 20 nop\.b 0x0 - e90: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - e96: 40 24 14 06 27 00 fcmp\.lt\.unc\.s3 p4,p3=3Df4,f5 - e9c: 00 00 00 20 nop\.b 0x0 - ea0: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - ea6: 40 20 14 86 20 00 fcmp\.le\.s0 p4,p3=3Df4,f5 - eac: 00 00 00 20 nop\.b 0x0 - eb0: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - eb6: 40 20 14 86 20 00 fcmp\.le\.s0 p4,p3=3Df4,f5 - ebc: 00 00 00 20 nop\.b 0x0 - ec0: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - ec6: 40 20 14 86 21 00 fcmp\.le\.s1 p4,p3=3Df4,f5 - ecc: 00 00 00 20 nop\.b 0x0 - ed0: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - ed6: 40 20 14 86 22 00 fcmp\.le\.s2 p4,p3=3Df4,f5 - edc: 00 00 00 20 nop\.b 0x0 - ee0: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - ee6: 40 20 14 86 23 00 fcmp\.le\.s3 p4,p3=3Df4,f5 - eec: 00 00 00 20 nop\.b 0x0 - ef0: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - ef6: 40 24 14 86 20 00 fcmp\.le\.unc\.s0 p4,p3=3Df4,f5 - efc: 00 00 00 20 nop\.b 0x0 - f00: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - f06: 40 24 14 86 20 00 fcmp\.le\.unc\.s0 p4,p3=3Df4,f5 - f0c: 00 00 00 20 nop\.b 0x0 - f10: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - f16: 40 24 14 86 21 00 fcmp\.le\.unc\.s1 p4,p3=3Df4,f5 - f1c: 00 00 00 20 nop\.b 0x0 - f20: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - f26: 40 24 14 86 22 00 fcmp\.le\.unc\.s2 p4,p3=3Df4,f5 - f2c: 00 00 00 20 nop\.b 0x0 - f30: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - f36: 40 24 14 86 23 00 fcmp\.le\.unc\.s3 p4,p3=3Df4,f5 - f3c: 00 00 00 20 nop\.b 0x0 - f40: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - f46: 40 28 10 06 24 00 fcmp\.lt\.s0 p4,p3=3Df5,f4 - f4c: 00 00 00 20 nop\.b 0x0 - f50: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - f56: 40 28 10 06 24 00 fcmp\.lt\.s0 p4,p3=3Df5,f4 - f5c: 00 00 00 20 nop\.b 0x0 - f60: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - f66: 40 28 10 06 25 00 fcmp\.lt\.s1 p4,p3=3Df5,f4 - f6c: 00 00 00 20 nop\.b 0x0 - f70: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - f76: 40 28 10 06 26 00 fcmp\.lt\.s2 p4,p3=3Df5,f4 - f7c: 00 00 00 20 nop\.b 0x0 - f80: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - f86: 40 28 10 06 27 00 fcmp\.lt\.s3 p4,p3=3Df5,f4 - f8c: 00 00 00 20 nop\.b 0x0 - f90: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - f96: 40 2c 10 06 24 00 fcmp\.lt\.unc\.s0 p4,p3=3Df5,f4 - f9c: 00 00 00 20 nop\.b 0x0 - fa0: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - fa6: 40 2c 10 06 24 00 fcmp\.lt\.unc\.s0 p4,p3=3Df5,f4 - fac: 00 00 00 20 nop\.b 0x0 - fb0: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - fb6: 40 2c 10 06 25 00 fcmp\.lt\.unc\.s1 p4,p3=3Df5,f4 - fbc: 00 00 00 20 nop\.b 0x0 - fc0: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - fc6: 40 2c 10 06 26 00 fcmp\.lt\.unc\.s2 p4,p3=3Df5,f4 - fcc: 00 00 00 20 nop\.b 0x0 - fd0: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - fd6: 40 2c 10 06 27 00 fcmp\.lt\.unc\.s3 p4,p3=3Df5,f4 - fdc: 00 00 00 20 nop\.b 0x0 - fe0: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - fe6: 40 28 10 86 20 00 fcmp\.le\.s0 p4,p3=3Df5,f4 - fec: 00 00 00 20 nop\.b 0x0 - ff0: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - ff6: 40 28 10 86 20 00 fcmp\.le\.s0 p4,p3=3Df5,f4 - ffc: 00 00 00 20 nop\.b 0x0 - 1000: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 1006: 40 28 10 86 21 00 fcmp\.le\.s1 p4,p3=3Df5,f4 - 100c: 00 00 00 20 nop\.b 0x0 - 1010: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 1016: 40 28 10 86 22 00 fcmp\.le\.s2 p4,p3=3Df5,f4 - 101c: 00 00 00 20 nop\.b 0x0 - 1020: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 1026: 40 28 10 86 23 00 fcmp\.le\.s3 p4,p3=3Df5,f4 - 102c: 00 00 00 20 nop\.b 0x0 - 1030: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 1036: 40 2c 10 86 20 00 fcmp\.le\.unc\.s0 p4,p3=3Df5,f4 - 103c: 00 00 00 20 nop\.b 0x0 - 1040: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 1046: 40 2c 10 86 20 00 fcmp\.le\.unc\.s0 p4,p3=3Df5,f4 - 104c: 00 00 00 20 nop\.b 0x0 - 1050: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 1056: 40 2c 10 86 21 00 fcmp\.le\.unc\.s1 p4,p3=3Df5,f4 - 105c: 00 00 00 20 nop\.b 0x0 - 1060: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 1066: 40 2c 10 86 22 00 fcmp\.le\.unc\.s2 p4,p3=3Df5,f4 - 106c: 00 00 00 20 nop\.b 0x0 - 1070: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 1076: 40 2c 10 86 23 00 fcmp\.le\.unc\.s3 p4,p3=3Df5,f4 - 107c: 00 00 00 20 nop\.b 0x0 - 1080: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 1086: 40 20 14 86 24 00 fcmp\.unord\.s0 p4,p3=3Df4,f5 - 108c: 00 00 00 20 nop\.b 0x0 - 1090: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 1096: 40 20 14 86 24 00 fcmp\.unord\.s0 p4,p3=3Df4,f5 - 109c: 00 00 00 20 nop\.b 0x0 - 10a0: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 10a6: 40 20 14 86 25 00 fcmp\.unord\.s1 p4,p3=3Df4,f5 - 10ac: 00 00 00 20 nop\.b 0x0 - 10b0: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 10b6: 40 20 14 86 26 00 fcmp\.unord\.s2 p4,p3=3Df4,f5 - 10bc: 00 00 00 20 nop\.b 0x0 - 10c0: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 10c6: 40 20 14 86 27 00 fcmp\.unord\.s3 p4,p3=3Df4,f5 - 10cc: 00 00 00 20 nop\.b 0x0 - 10d0: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 10d6: 40 24 14 86 24 00 fcmp\.unord\.unc\.s0 p4,p3=3Df4,f5 - 10dc: 00 00 00 20 nop\.b 0x0 - 10e0: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 10e6: 40 24 14 86 24 00 fcmp\.unord\.unc\.s0 p4,p3=3Df4,f5 - 10ec: 00 00 00 20 nop\.b 0x0 - 10f0: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 10f6: 40 24 14 86 25 00 fcmp\.unord\.unc\.s1 p4,p3=3Df4,f5 - 10fc: 00 00 00 20 nop\.b 0x0 - 1100: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 1106: 40 24 14 86 26 00 fcmp\.unord\.unc\.s2 p4,p3=3Df4,f5 - 110c: 00 00 00 20 nop\.b 0x0 - 1110: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 1116: 40 24 14 86 27 00 fcmp\.unord\.unc\.s3 p4,p3=3Df4,f5 - 111c: 00 00 00 20 nop\.b 0x0 - 1120: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 1126: 30 20 00 09 28 00 fclass\.m p3,p4=3Df4,0x100 - 112c: 00 00 00 20 nop\.b 0x0 - 1130: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 1136: 40 20 00 07 28 00 fclass\.m p4,p3=3Df4,0x100 - 113c: 00 00 00 20 nop\.b 0x0 - 1140: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 1146: 30 20 80 08 28 00 fclass\.m p3,p4=3Df4,0x80 - 114c: 00 00 00 20 nop\.b 0x0 - 1150: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 1156: 40 20 80 06 28 00 fclass\.m p4,p3=3Df4,0x80 - 115c: 00 00 00 20 nop\.b 0x0 - 1160: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 1166: 30 20 40 08 28 00 fclass\.m p3,p4=3Df4,0x40 - 116c: 00 00 00 20 nop\.b 0x0 - 1170: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 1176: 40 20 40 06 28 00 fclass\.m p4,p3=3Df4,0x40 - 117c: 00 00 00 20 nop\.b 0x0 - 1180: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 1186: 30 20 00 88 28 00 fclass\.m p3,p4=3Df4,0x1 - 118c: 00 00 00 20 nop\.b 0x0 - 1190: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 1196: 40 20 00 86 28 00 fclass\.m p4,p3=3Df4,0x1 - 119c: 00 00 00 20 nop\.b 0x0 - 11a0: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 11a6: 30 20 00 08 29 00 fclass\.m p3,p4=3Df4,0x2 - 11ac: 00 00 00 20 nop\.b 0x0 - 11b0: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 11b6: 40 20 00 06 29 00 fclass\.m p4,p3=3Df4,0x2 - 11bc: 00 00 00 20 nop\.b 0x0 - 11c0: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 11c6: 30 20 08 88 29 00 fclass\.m p3,p4=3Df4,0xb - 11cc: 00 00 00 20 nop\.b 0x0 - 11d0: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 11d6: 40 20 08 86 29 00 fclass\.m p4,p3=3Df4,0xb - 11dc: 00 00 00 20 nop\.b 0x0 - 11e0: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 11e6: 30 20 10 88 29 00 fclass\.m p3,p4=3Df4,0x13 - 11ec: 00 00 00 20 nop\.b 0x0 - 11f0: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 11f6: 40 20 10 86 29 00 fclass\.m p4,p3=3Df4,0x13 - 11fc: 00 00 00 20 nop\.b 0x0 - 1200: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 1206: 30 20 20 88 29 00 fclass\.m p3,p4=3Df4,0x23 - 120c: 00 00 00 20 nop\.b 0x0 - 1210: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 1216: 40 20 20 86 29 00 fclass\.m p4,p3=3Df4,0x23 - 121c: 00 00 00 20 nop\.b 0x0 - 1220: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 1226: 30 20 fc 89 29 00 fclass\.m p3,p4=3Df4,0x1ff - 122c: 00 00 00 20 nop\.b 0x0 - 1230: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 1236: 40 20 fc 87 29 00 fclass\.m p4,p3=3Df4,0x1ff - 123c: 00 00 00 20 nop\.b 0x0 - 1240: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 1246: 30 24 00 09 28 00 fclass\.m\.unc p3,p4=3Df4,0x100 - 124c: 00 00 00 20 nop\.b 0x0 - 1250: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 1256: 40 24 00 07 28 00 fclass\.m\.unc p4,p3=3Df4,0x100 - 125c: 00 00 00 20 nop\.b 0x0 - 1260: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 1266: 30 24 80 08 28 00 fclass\.m\.unc p3,p4=3Df4,0x80 - 126c: 00 00 00 20 nop\.b 0x0 - 1270: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 1276: 40 24 80 06 28 00 fclass\.m\.unc p4,p3=3Df4,0x80 - 127c: 00 00 00 20 nop\.b 0x0 - 1280: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 1286: 30 24 40 08 28 00 fclass\.m\.unc p3,p4=3Df4,0x40 - 128c: 00 00 00 20 nop\.b 0x0 - 1290: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 1296: 40 24 40 06 28 00 fclass\.m\.unc p4,p3=3Df4,0x40 - 129c: 00 00 00 20 nop\.b 0x0 - 12a0: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 12a6: 30 24 00 88 28 00 fclass\.m\.unc p3,p4=3Df4,0x1 - 12ac: 00 00 00 20 nop\.b 0x0 - 12b0: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 12b6: 40 24 00 86 28 00 fclass\.m\.unc p4,p3=3Df4,0x1 - 12bc: 00 00 00 20 nop\.b 0x0 - 12c0: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 12c6: 30 24 00 08 29 00 fclass\.m\.unc p3,p4=3Df4,0x2 - 12cc: 00 00 00 20 nop\.b 0x0 - 12d0: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 12d6: 40 24 00 06 29 00 fclass\.m\.unc p4,p3=3Df4,0x2 - 12dc: 00 00 00 20 nop\.b 0x0 - 12e0: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 12e6: 30 24 08 88 29 00 fclass\.m\.unc p3,p4=3Df4,0xb - 12ec: 00 00 00 20 nop\.b 0x0 - 12f0: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 12f6: 40 24 08 86 29 00 fclass\.m\.unc p4,p3=3Df4,0xb - 12fc: 00 00 00 20 nop\.b 0x0 - 1300: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 1306: 30 24 10 88 29 00 fclass\.m\.unc p3,p4=3Df4,0x13 - 130c: 00 00 00 20 nop\.b 0x0 - 1310: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 1316: 40 24 10 86 29 00 fclass\.m\.unc p4,p3=3Df4,0x13 - 131c: 00 00 00 20 nop\.b 0x0 - 1320: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 1326: 30 24 20 88 29 00 fclass\.m\.unc p3,p4=3Df4,0x23 - 132c: 00 00 00 20 nop\.b 0x0 - 1330: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 1336: 40 24 20 86 29 00 fclass\.m\.unc p4,p3=3Df4,0x23 - 133c: 00 00 00 20 nop\.b 0x0 - 1340: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 1346: 30 24 fc 89 29 00 fclass\.m\.unc p3,p4=3Df4,0x1ff - 134c: 00 00 00 20 nop\.b 0x0 - 1350: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 1356: 40 24 fc 87 29 00 fclass\.m\.unc p4,p3=3Df4,0x1ff - 135c: 00 00 00 20 nop\.b 0x0 - 1360: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 1366: 40 30 1c 8a 00 00 frcpa\.s0 f4,p5=3Df6,f7 - 136c: 00 00 00 20 nop\.b 0x0 - 1370: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 1376: 40 30 1c 8a 00 00 frcpa\.s0 f4,p5=3Df6,f7 - 137c: 00 00 00 20 nop\.b 0x0 - 1380: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 1386: 40 30 1c 8a 01 00 frcpa\.s1 f4,p5=3Df6,f7 - 138c: 00 00 00 20 nop\.b 0x0 - 1390: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 1396: 40 30 1c 8a 02 00 frcpa\.s2 f4,p5=3Df6,f7 - 139c: 00 00 00 20 nop\.b 0x0 - 13a0: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 13a6: 40 30 1c 8a 03 00 frcpa\.s3 f4,p5=3Df6,f7 - 13ac: 00 00 00 20 nop\.b 0x0 - 13b0: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 13b6: 40 30 1c 8a 08 00 fprcpa\.s0 f4,p5=3Df6,f7 - 13bc: 00 00 00 20 nop\.b 0x0 - 13c0: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 13c6: 40 30 1c 8a 08 00 fprcpa\.s0 f4,p5=3Df6,f7 - 13cc: 00 00 00 20 nop\.b 0x0 - 13d0: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 13d6: 40 30 1c 8a 09 00 fprcpa\.s1 f4,p5=3Df6,f7 - 13dc: 00 00 00 20 nop\.b 0x0 - 13e0: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 13e6: 40 30 1c 8a 0a 00 fprcpa\.s2 f4,p5=3Df6,f7 - 13ec: 00 00 00 20 nop\.b 0x0 - 13f0: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 13f6: 40 30 1c 8a 0b 00 fprcpa\.s3 f4,p5=3Df6,f7 - 13fc: 00 00 00 20 nop\.b 0x0 - 1400: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 1406: 40 00 18 8a 04 00 frsqrta\.s0 f4,p5=3Df6 - 140c: 00 00 00 20 nop\.b 0x0 - 1410: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 1416: 40 00 18 8a 04 00 frsqrta\.s0 f4,p5=3Df6 - 141c: 00 00 00 20 nop\.b 0x0 - 1420: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 1426: 40 00 18 8a 05 00 frsqrta\.s1 f4,p5=3Df6 - 142c: 00 00 00 20 nop\.b 0x0 - 1430: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 1436: 40 00 18 8a 06 00 frsqrta\.s2 f4,p5=3Df6 - 143c: 00 00 00 20 nop\.b 0x0 - 1440: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 1446: 40 00 18 8a 07 00 frsqrta\.s3 f4,p5=3Df6 - 144c: 00 00 00 20 nop\.b 0x0 - 1450: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 1456: 40 00 18 8a 0c 00 fprsqrta\.s0 f4,p5=3Df6 - 145c: 00 00 00 20 nop\.b 0x0 - 1460: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 1466: 40 00 18 8a 0c 00 fprsqrta\.s0 f4,p5=3Df6 - 146c: 00 00 00 20 nop\.b 0x0 - 1470: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 1476: 40 00 18 8a 0d 00 fprsqrta\.s1 f4,p5=3Df6 - 147c: 00 00 00 20 nop\.b 0x0 - 1480: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 1486: 40 00 18 8a 0e 00 fprsqrta\.s2 f4,p5=3Df6 - 148c: 00 00 00 20 nop\.b 0x0 - 1490: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 1496: 40 00 18 8a 0f 00 fprsqrta\.s3 f4,p5=3Df6 - 149c: 00 00 00 20 nop\.b 0x0 - 14a0: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 14a6: 40 28 18 28 00 00 fmin\.s0 f4=3Df5,f6 - 14ac: 00 00 00 20 nop\.b 0x0 - 14b0: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 14b6: 40 28 18 28 00 00 fmin\.s0 f4=3Df5,f6 - 14bc: 00 00 00 20 nop\.b 0x0 - 14c0: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 14c6: 40 28 18 28 01 00 fmin\.s1 f4=3Df5,f6 - 14cc: 00 00 00 20 nop\.b 0x0 - 14d0: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 14d6: 40 28 18 28 02 00 fmin\.s2 f4=3Df5,f6 - 14dc: 00 00 00 20 nop\.b 0x0 - 14e0: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 14e6: 40 28 18 28 03 00 fmin\.s3 f4=3Df5,f6 - 14ec: 00 00 00 20 nop\.b 0x0 - 14f0: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 14f6: 40 28 18 2a 00 00 fmax\.s0 f4=3Df5,f6 - 14fc: 00 00 00 20 nop\.b 0x0 - 1500: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 1506: 40 28 18 2a 00 00 fmax\.s0 f4=3Df5,f6 - 150c: 00 00 00 20 nop\.b 0x0 - 1510: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 1516: 40 28 18 2a 01 00 fmax\.s1 f4=3Df5,f6 - 151c: 00 00 00 20 nop\.b 0x0 - 1520: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 1526: 40 28 18 2a 02 00 fmax\.s2 f4=3Df5,f6 - 152c: 00 00 00 20 nop\.b 0x0 - 1530: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 1536: 40 28 18 2a 03 00 fmax\.s3 f4=3Df5,f6 - 153c: 00 00 00 20 nop\.b 0x0 - 1540: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 1546: 40 28 18 2c 00 00 famin\.s0 f4=3Df5,f6 - 154c: 00 00 00 20 nop\.b 0x0 - 1550: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 1556: 40 28 18 2c 00 00 famin\.s0 f4=3Df5,f6 - 155c: 00 00 00 20 nop\.b 0x0 - 1560: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 1566: 40 28 18 2c 01 00 famin\.s1 f4=3Df5,f6 - 156c: 00 00 00 20 nop\.b 0x0 - 1570: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 1576: 40 28 18 2c 02 00 famin\.s2 f4=3Df5,f6 - 157c: 00 00 00 20 nop\.b 0x0 - 1580: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 1586: 40 28 18 2c 03 00 famin\.s3 f4=3Df5,f6 - 158c: 00 00 00 20 nop\.b 0x0 - 1590: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 1596: 40 28 18 2e 00 00 famax\.s0 f4=3Df5,f6 - 159c: 00 00 00 20 nop\.b 0x0 - 15a0: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 15a6: 40 28 18 2e 00 00 famax\.s0 f4=3Df5,f6 - 15ac: 00 00 00 20 nop\.b 0x0 - 15b0: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 15b6: 40 28 18 2e 01 00 famax\.s1 f4=3Df5,f6 - 15bc: 00 00 00 20 nop\.b 0x0 - 15c0: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 15c6: 40 28 18 2e 02 00 famax\.s2 f4=3Df5,f6 - 15cc: 00 00 00 20 nop\.b 0x0 - 15d0: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 15d6: 40 28 18 2e 03 00 famax\.s3 f4=3Df5,f6 - 15dc: 00 00 00 20 nop\.b 0x0 - 15e0: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 15e6: 40 28 18 28 08 00 fpmin\.s0 f4=3Df5,f6 - 15ec: 00 00 00 20 nop\.b 0x0 - 15f0: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 15f6: 40 28 18 28 08 00 fpmin\.s0 f4=3Df5,f6 - 15fc: 00 00 00 20 nop\.b 0x0 - 1600: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 1606: 40 28 18 28 09 00 fpmin\.s1 f4=3Df5,f6 - 160c: 00 00 00 20 nop\.b 0x0 - 1610: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 1616: 40 28 18 28 0a 00 fpmin\.s2 f4=3Df5,f6 - 161c: 00 00 00 20 nop\.b 0x0 - 1620: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 1626: 40 28 18 28 0b 00 fpmin\.s3 f4=3Df5,f6 - 162c: 00 00 00 20 nop\.b 0x0 - 1630: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 1636: 40 28 18 2a 08 00 fpmax\.s0 f4=3Df5,f6 - 163c: 00 00 00 20 nop\.b 0x0 - 1640: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 1646: 40 28 18 2a 08 00 fpmax\.s0 f4=3Df5,f6 - 164c: 00 00 00 20 nop\.b 0x0 - 1650: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 1656: 40 28 18 2a 09 00 fpmax\.s1 f4=3Df5,f6 - 165c: 00 00 00 20 nop\.b 0x0 - 1660: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 1666: 40 28 18 2a 0a 00 fpmax\.s2 f4=3Df5,f6 - 166c: 00 00 00 20 nop\.b 0x0 - 1670: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 1676: 40 28 18 2a 0b 00 fpmax\.s3 f4=3Df5,f6 - 167c: 00 00 00 20 nop\.b 0x0 - 1680: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 1686: 40 28 18 2c 08 00 fpamin\.s0 f4=3Df5,f6 - 168c: 00 00 00 20 nop\.b 0x0 - 1690: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 1696: 40 28 18 2c 08 00 fpamin\.s0 f4=3Df5,f6 - 169c: 00 00 00 20 nop\.b 0x0 - 16a0: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 16a6: 40 28 18 2c 09 00 fpamin\.s1 f4=3Df5,f6 - 16ac: 00 00 00 20 nop\.b 0x0 - 16b0: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 16b6: 40 28 18 2c 0a 00 fpamin\.s2 f4=3Df5,f6 - 16bc: 00 00 00 20 nop\.b 0x0 - 16c0: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 16c6: 40 28 18 2c 0b 00 fpamin\.s3 f4=3Df5,f6 - 16cc: 00 00 00 20 nop\.b 0x0 - 16d0: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 16d6: 40 28 18 2e 08 00 fpamax\.s0 f4=3Df5,f6 - 16dc: 00 00 00 20 nop\.b 0x0 - 16e0: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 16e6: 40 28 18 2e 08 00 fpamax\.s0 f4=3Df5,f6 - 16ec: 00 00 00 20 nop\.b 0x0 - 16f0: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 16f6: 40 28 18 2e 09 00 fpamax\.s1 f4=3Df5,f6 - 16fc: 00 00 00 20 nop\.b 0x0 - 1700: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 1706: 40 28 18 2e 0a 00 fpamax\.s2 f4=3Df5,f6 - 170c: 00 00 00 20 nop\.b 0x0 - 1710: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 1716: 40 28 18 2e 0b 00 fpamax\.s3 f4=3Df5,f6 - 171c: 00 00 00 20 nop\.b 0x0 - 1720: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 1726: 30 20 14 60 08 00 fpcmp\.eq\.s0 f3=3Df4,f5 - 172c: 00 00 00 20 nop\.b 0x0 - 1730: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 1736: 30 20 14 60 08 00 fpcmp\.eq\.s0 f3=3Df4,f5 - 173c: 00 00 00 20 nop\.b 0x0 - 1740: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 1746: 30 20 14 60 09 00 fpcmp\.eq\.s1 f3=3Df4,f5 - 174c: 00 00 00 20 nop\.b 0x0 - 1750: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 1756: 30 20 14 60 0a 00 fpcmp\.eq\.s2 f3=3Df4,f5 - 175c: 00 00 00 20 nop\.b 0x0 - 1760: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 1766: 30 20 14 60 0b 00 fpcmp\.eq\.s3 f3=3Df4,f5 - 176c: 00 00 00 20 nop\.b 0x0 - 1770: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 1776: 30 20 14 62 08 00 fpcmp\.lt\.s0 f3=3Df4,f5 - 177c: 00 00 00 20 nop\.b 0x0 - 1780: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 1786: 30 20 14 62 08 00 fpcmp\.lt\.s0 f3=3Df4,f5 - 178c: 00 00 00 20 nop\.b 0x0 - 1790: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 1796: 30 20 14 62 09 00 fpcmp\.lt\.s1 f3=3Df4,f5 - 179c: 00 00 00 20 nop\.b 0x0 - 17a0: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 17a6: 30 20 14 62 0a 00 fpcmp\.lt\.s2 f3=3Df4,f5 - 17ac: 00 00 00 20 nop\.b 0x0 - 17b0: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 17b6: 30 20 14 62 0b 00 fpcmp\.lt\.s3 f3=3Df4,f5 - 17bc: 00 00 00 20 nop\.b 0x0 - 17c0: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 17c6: 30 20 14 64 08 00 fpcmp\.le\.s0 f3=3Df4,f5 - 17cc: 00 00 00 20 nop\.b 0x0 - 17d0: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 17d6: 30 20 14 64 08 00 fpcmp\.le\.s0 f3=3Df4,f5 - 17dc: 00 00 00 20 nop\.b 0x0 - 17e0: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 17e6: 30 20 14 64 09 00 fpcmp\.le\.s1 f3=3Df4,f5 - 17ec: 00 00 00 20 nop\.b 0x0 - 17f0: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 17f6: 30 20 14 64 0a 00 fpcmp\.le\.s2 f3=3Df4,f5 - 17fc: 00 00 00 20 nop\.b 0x0 - 1800: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 1806: 30 20 14 64 0b 00 fpcmp\.le\.s3 f3=3Df4,f5 - 180c: 00 00 00 20 nop\.b 0x0 - 1810: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 1816: 30 20 14 66 08 00 fpcmp\.unord\.s0 f3=3Df4,f5 - 181c: 00 00 00 20 nop\.b 0x0 - 1820: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 1826: 30 20 14 66 08 00 fpcmp\.unord\.s0 f3=3Df4,f5 - 182c: 00 00 00 20 nop\.b 0x0 - 1830: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 1836: 30 20 14 66 09 00 fpcmp\.unord\.s1 f3=3Df4,f5 - 183c: 00 00 00 20 nop\.b 0x0 - 1840: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 1846: 30 20 14 66 0a 00 fpcmp\.unord\.s2 f3=3Df4,f5 - 184c: 00 00 00 20 nop\.b 0x0 - 1850: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 1856: 30 20 14 66 0b 00 fpcmp\.unord\.s3 f3=3Df4,f5 - 185c: 00 00 00 20 nop\.b 0x0 - 1860: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 1866: 30 28 10 62 08 00 fpcmp\.lt\.s0 f3=3Df5,f4 - 186c: 00 00 00 20 nop\.b 0x0 - 1870: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 1876: 30 28 10 62 08 00 fpcmp\.lt\.s0 f3=3Df5,f4 - 187c: 00 00 00 20 nop\.b 0x0 - 1880: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 1886: 30 28 10 62 09 00 fpcmp\.lt\.s1 f3=3Df5,f4 - 188c: 00 00 00 20 nop\.b 0x0 - 1890: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 1896: 30 28 10 62 0a 00 fpcmp\.lt\.s2 f3=3Df5,f4 - 189c: 00 00 00 20 nop\.b 0x0 - 18a0: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 18a6: 30 28 10 62 0b 00 fpcmp\.lt\.s3 f3=3Df5,f4 - 18ac: 00 00 00 20 nop\.b 0x0 - 18b0: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 18b6: 30 28 10 64 08 00 fpcmp\.le\.s0 f3=3Df5,f4 - 18bc: 00 00 00 20 nop\.b 0x0 - 18c0: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 18c6: 30 28 10 64 08 00 fpcmp\.le\.s0 f3=3Df5,f4 - 18cc: 00 00 00 20 nop\.b 0x0 - 18d0: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 18d6: 30 28 10 64 09 00 fpcmp\.le\.s1 f3=3Df5,f4 - 18dc: 00 00 00 20 nop\.b 0x0 - 18e0: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 18e6: 30 28 10 64 0a 00 fpcmp\.le\.s2 f3=3Df5,f4 - 18ec: 00 00 00 20 nop\.b 0x0 - 18f0: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 18f6: 30 28 10 64 0b 00 fpcmp\.le\.s3 f3=3Df5,f4 - 18fc: 00 00 00 20 nop\.b 0x0 - 1900: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 1906: 30 20 14 68 08 00 fpcmp\.neq\.s0 f3=3Df4,f5 - 190c: 00 00 00 20 nop\.b 0x0 - 1910: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 1916: 30 20 14 68 08 00 fpcmp\.neq\.s0 f3=3Df4,f5 - 191c: 00 00 00 20 nop\.b 0x0 - 1920: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 1926: 30 20 14 68 09 00 fpcmp\.neq\.s1 f3=3Df4,f5 - 192c: 00 00 00 20 nop\.b 0x0 - 1930: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 1936: 30 20 14 68 0a 00 fpcmp\.neq\.s2 f3=3Df4,f5 - 193c: 00 00 00 20 nop\.b 0x0 - 1940: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 1946: 30 20 14 68 0b 00 fpcmp\.neq\.s3 f3=3Df4,f5 - 194c: 00 00 00 20 nop\.b 0x0 - 1950: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 1956: 30 20 14 6a 08 00 fpcmp\.nlt\.s0 f3=3Df4,f5 - 195c: 00 00 00 20 nop\.b 0x0 - 1960: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 1966: 30 20 14 6a 08 00 fpcmp\.nlt\.s0 f3=3Df4,f5 - 196c: 00 00 00 20 nop\.b 0x0 - 1970: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 1976: 30 20 14 6a 09 00 fpcmp\.nlt\.s1 f3=3Df4,f5 - 197c: 00 00 00 20 nop\.b 0x0 - 1980: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 1986: 30 20 14 6a 0a 00 fpcmp\.nlt\.s2 f3=3Df4,f5 - 198c: 00 00 00 20 nop\.b 0x0 - 1990: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 1996: 30 20 14 6a 0b 00 fpcmp\.nlt\.s3 f3=3Df4,f5 - 199c: 00 00 00 20 nop\.b 0x0 - 19a0: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 19a6: 30 20 14 6c 08 00 fpcmp\.nle\.s0 f3=3Df4,f5 - 19ac: 00 00 00 20 nop\.b 0x0 - 19b0: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 19b6: 30 20 14 6c 08 00 fpcmp\.nle\.s0 f3=3Df4,f5 - 19bc: 00 00 00 20 nop\.b 0x0 - 19c0: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 19c6: 30 20 14 6c 09 00 fpcmp\.nle\.s1 f3=3Df4,f5 - 19cc: 00 00 00 20 nop\.b 0x0 - 19d0: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 19d6: 30 20 14 6c 0a 00 fpcmp\.nle\.s2 f3=3Df4,f5 - 19dc: 00 00 00 20 nop\.b 0x0 - 19e0: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 19e6: 30 20 14 6c 0b 00 fpcmp\.nle\.s3 f3=3Df4,f5 - 19ec: 00 00 00 20 nop\.b 0x0 - 19f0: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 19f6: 30 28 10 6a 08 00 fpcmp\.nlt\.s0 f3=3Df5,f4 - 19fc: 00 00 00 20 nop\.b 0x0 - 1a00: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 1a06: 30 28 10 6a 08 00 fpcmp\.nlt\.s0 f3=3Df5,f4 - 1a0c: 00 00 00 20 nop\.b 0x0 - 1a10: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 1a16: 30 28 10 6a 09 00 fpcmp\.nlt\.s1 f3=3Df5,f4 - 1a1c: 00 00 00 20 nop\.b 0x0 - 1a20: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 1a26: 30 28 10 6a 0a 00 fpcmp\.nlt\.s2 f3=3Df5,f4 - 1a2c: 00 00 00 20 nop\.b 0x0 - 1a30: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 1a36: 30 28 10 6a 0b 00 fpcmp\.nlt\.s3 f3=3Df5,f4 - 1a3c: 00 00 00 20 nop\.b 0x0 - 1a40: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 1a46: 30 28 10 6c 08 00 fpcmp\.nle\.s0 f3=3Df5,f4 - 1a4c: 00 00 00 20 nop\.b 0x0 - 1a50: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 1a56: 30 28 10 6c 08 00 fpcmp\.nle\.s0 f3=3Df5,f4 - 1a5c: 00 00 00 20 nop\.b 0x0 - 1a60: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 1a66: 30 28 10 6c 09 00 fpcmp\.nle\.s1 f3=3Df5,f4 - 1a6c: 00 00 00 20 nop\.b 0x0 - 1a70: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 1a76: 30 28 10 6c 0a 00 fpcmp\.nle\.s2 f3=3Df5,f4 - 1a7c: 00 00 00 20 nop\.b 0x0 - 1a80: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 1a86: 30 28 10 6c 0b 00 fpcmp\.nle\.s3 f3=3Df5,f4 - 1a8c: 00 00 00 20 nop\.b 0x0 - 1a90: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 1a96: 30 20 14 6e 08 00 fpcmp\.ord\.s0 f3=3Df4,f5 - 1a9c: 00 00 00 20 nop\.b 0x0 - 1aa0: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 1aa6: 30 20 14 6e 08 00 fpcmp\.ord\.s0 f3=3Df4,f5 - 1aac: 00 00 00 20 nop\.b 0x0 - 1ab0: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 1ab6: 30 20 14 6e 09 00 fpcmp\.ord\.s1 f3=3Df4,f5 - 1abc: 00 00 00 20 nop\.b 0x0 - 1ac0: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 1ac6: 30 20 14 6e 0a 00 fpcmp\.ord\.s2 f3=3Df4,f5 - 1acc: 00 00 00 20 nop\.b 0x0 - 1ad0: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 1ad6: 30 20 14 6e 0b 00 fpcmp\.ord\.s3 f3=3Df4,f5 - 1adc: 00 00 00 20 nop\.b 0x0 - 1ae0: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 1ae6: 40 28 18 20 00 00 fmerge\.s f4=3Df5,f6 - 1aec: 00 00 00 20 nop\.b 0x0 - 1af0: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 1af6: 40 28 18 22 00 00 fmerge\.ns f4=3Df5,f6 - 1afc: 00 00 00 20 nop\.b 0x0 - 1b00: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 1b06: 40 28 18 24 00 00 fmerge\.se f4=3Df5,f6 - 1b0c: 00 00 00 20 nop\.b 0x0 - 1b10: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 1b16: 40 28 18 72 00 00 fmix\.lr f4=3Df5,f6 - 1b1c: 00 00 00 20 nop\.b 0x0 - 1b20: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 1b26: 40 28 18 74 00 00 fmix\.r f4=3Df5,f6 - 1b2c: 00 00 00 20 nop\.b 0x0 - 1b30: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 1b36: 40 28 18 76 00 00 fmix\.l f4=3Df5,f6 - 1b3c: 00 00 00 20 nop\.b 0x0 - 1b40: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 1b46: 40 28 18 7a 00 00 fsxt\.l f4=3Df5,f6 - 1b4c: 00 00 00 20 nop\.b 0x0 - 1b50: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 1b56: 40 28 18 50 00 00 fpack f4=3Df5,f6 - 1b5c: 00 00 00 20 nop\.b 0x0 - 1b60: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 1b66: 40 28 18 68 00 00 fswap f4=3Df5,f6 - 1b6c: 00 00 00 20 nop\.b 0x0 - 1b70: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 1b76: 40 28 18 6a 00 00 fswap\.nl f4=3Df5,f6 - 1b7c: 00 00 00 20 nop\.b 0x0 - 1b80: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 1b86: 40 28 18 6c 00 00 fswap\.nr f4=3Df5,f6 - 1b8c: 00 00 00 20 nop\.b 0x0 - 1b90: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 1b96: 40 28 18 58 00 00 fand f4=3Df5,f6 - 1b9c: 00 00 00 20 nop\.b 0x0 - 1ba0: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 1ba6: 40 28 18 5a 00 00 fandcm f4=3Df5,f6 - 1bac: 00 00 00 20 nop\.b 0x0 - 1bb0: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 1bb6: 40 28 18 5c 00 00 for f4=3Df5,f6 - 1bbc: 00 00 00 20 nop\.b 0x0 - 1bc0: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 1bc6: 40 28 18 5e 00 00 fxor f4=3Df5,f6 - 1bcc: 00 00 00 20 nop\.b 0x0 - 1bd0: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 1bd6: 40 28 18 20 08 00 fpmerge\.s f4=3Df5,f6 - 1bdc: 00 00 00 20 nop\.b 0x0 - 1be0: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 1be6: 40 28 18 22 08 00 fpmerge\.ns f4=3Df5,f6 - 1bec: 00 00 00 20 nop\.b 0x0 - 1bf0: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 1bf6: 40 28 18 24 08 00 fpmerge\.se f4=3Df5,f6 - 1bfc: 00 00 00 20 nop\.b 0x0 - 1c00: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 1c06: 40 00 14 20 00 00 fabs f4=3Df5 - 1c0c: 00 00 00 20 nop\.b 0x0 - 1c10: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 1c16: 40 28 14 22 00 00 fneg f4=3Df5 - 1c1c: 00 00 00 20 nop\.b 0x0 - 1c20: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 1c26: 40 00 14 22 00 00 fnegabs f4=3Df5 - 1c2c: 00 00 00 20 nop\.b 0x0 - 1c30: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 1c36: 40 00 14 20 08 00 fpabs f4=3Df5 - 1c3c: 00 00 00 20 nop\.b 0x0 - 1c40: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 1c46: 40 28 14 22 08 00 fpneg f4=3Df5 - 1c4c: 00 00 00 20 nop\.b 0x0 - 1c50: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 1c56: 40 00 14 22 08 00 fpnegabs f4=3Df5 - 1c5c: 00 00 00 20 nop\.b 0x0 - 1c60: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 1c66: 40 28 00 30 00 00 fcvt\.fx\.s0 f4=3Df5 - 1c6c: 00 00 00 20 nop\.b 0x0 - 1c70: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 1c76: 40 28 00 30 00 00 fcvt\.fx\.s0 f4=3Df5 - 1c7c: 00 00 00 20 nop\.b 0x0 - 1c80: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 1c86: 40 28 00 30 01 00 fcvt\.fx\.s1 f4=3Df5 - 1c8c: 00 00 00 20 nop\.b 0x0 - 1c90: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 1c96: 40 28 00 30 02 00 fcvt\.fx\.s2 f4=3Df5 - 1c9c: 00 00 00 20 nop\.b 0x0 - 1ca0: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 1ca6: 40 28 00 30 03 00 fcvt\.fx\.s3 f4=3Df5 - 1cac: 00 00 00 20 nop\.b 0x0 - 1cb0: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 1cb6: 40 28 00 34 00 00 fcvt\.fx\.trunc\.s0 f4=3Df5 - 1cbc: 00 00 00 20 nop\.b 0x0 - 1cc0: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 1cc6: 40 28 00 34 00 00 fcvt\.fx\.trunc\.s0 f4=3Df5 - 1ccc: 00 00 00 20 nop\.b 0x0 - 1cd0: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 1cd6: 40 28 00 34 01 00 fcvt\.fx\.trunc\.s1 f4=3Df5 - 1cdc: 00 00 00 20 nop\.b 0x0 - 1ce0: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 1ce6: 40 28 00 34 02 00 fcvt\.fx\.trunc\.s2 f4=3Df5 - 1cec: 00 00 00 20 nop\.b 0x0 - 1cf0: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 1cf6: 40 28 00 34 03 00 fcvt\.fx\.trunc\.s3 f4=3Df5 - 1cfc: 00 00 00 20 nop\.b 0x0 - 1d00: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 1d06: 40 28 00 32 00 00 fcvt\.fxu\.s0 f4=3Df5 - 1d0c: 00 00 00 20 nop\.b 0x0 - 1d10: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 1d16: 40 28 00 32 00 00 fcvt\.fxu\.s0 f4=3Df5 - 1d1c: 00 00 00 20 nop\.b 0x0 - 1d20: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 1d26: 40 28 00 32 01 00 fcvt\.fxu\.s1 f4=3Df5 - 1d2c: 00 00 00 20 nop\.b 0x0 - 1d30: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 1d36: 40 28 00 32 02 00 fcvt\.fxu\.s2 f4=3Df5 - 1d3c: 00 00 00 20 nop\.b 0x0 - 1d40: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 1d46: 40 28 00 32 03 00 fcvt\.fxu\.s3 f4=3Df5 - 1d4c: 00 00 00 20 nop\.b 0x0 - 1d50: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 1d56: 40 28 00 36 00 00 fcvt\.fxu\.trunc\.s0 f4=3Df5 - 1d5c: 00 00 00 20 nop\.b 0x0 - 1d60: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 1d66: 40 28 00 36 00 00 fcvt\.fxu\.trunc\.s0 f4=3Df5 - 1d6c: 00 00 00 20 nop\.b 0x0 - 1d70: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 1d76: 40 28 00 36 01 00 fcvt\.fxu\.trunc\.s1 f4=3Df5 - 1d7c: 00 00 00 20 nop\.b 0x0 - 1d80: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 1d86: 40 28 00 36 02 00 fcvt\.fxu\.trunc\.s2 f4=3Df5 - 1d8c: 00 00 00 20 nop\.b 0x0 - 1d90: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 1d96: 40 28 00 36 03 00 fcvt\.fxu\.trunc\.s3 f4=3Df5 - 1d9c: 00 00 00 20 nop\.b 0x0 - 1da0: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 1da6: 40 28 00 30 08 00 fpcvt\.fx\.s0 f4=3Df5 - 1dac: 00 00 00 20 nop\.b 0x0 - 1db0: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 1db6: 40 28 00 30 08 00 fpcvt\.fx\.s0 f4=3Df5 - 1dbc: 00 00 00 20 nop\.b 0x0 - 1dc0: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 1dc6: 40 28 00 30 09 00 fpcvt\.fx\.s1 f4=3Df5 - 1dcc: 00 00 00 20 nop\.b 0x0 - 1dd0: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 1dd6: 40 28 00 30 0a 00 fpcvt\.fx\.s2 f4=3Df5 - 1ddc: 00 00 00 20 nop\.b 0x0 - 1de0: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 1de6: 40 28 00 30 0b 00 fpcvt\.fx\.s3 f4=3Df5 - 1dec: 00 00 00 20 nop\.b 0x0 - 1df0: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 1df6: 40 28 00 34 08 00 fpcvt\.fx\.trunc\.s0 f4=3Df5 - 1dfc: 00 00 00 20 nop\.b 0x0 - 1e00: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 1e06: 40 28 00 34 08 00 fpcvt\.fx\.trunc\.s0 f4=3Df5 - 1e0c: 00 00 00 20 nop\.b 0x0 - 1e10: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 1e16: 40 28 00 34 09 00 fpcvt\.fx\.trunc\.s1 f4=3Df5 - 1e1c: 00 00 00 20 nop\.b 0x0 - 1e20: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 1e26: 40 28 00 34 0a 00 fpcvt\.fx\.trunc\.s2 f4=3Df5 - 1e2c: 00 00 00 20 nop\.b 0x0 - 1e30: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 1e36: 40 28 00 34 0b 00 fpcvt\.fx\.trunc\.s3 f4=3Df5 - 1e3c: 00 00 00 20 nop\.b 0x0 - 1e40: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 1e46: 40 28 00 32 08 00 fpcvt\.fxu\.s0 f4=3Df5 - 1e4c: 00 00 00 20 nop\.b 0x0 - 1e50: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 1e56: 40 28 00 32 08 00 fpcvt\.fxu\.s0 f4=3Df5 - 1e5c: 00 00 00 20 nop\.b 0x0 - 1e60: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 1e66: 40 28 00 32 09 00 fpcvt\.fxu\.s1 f4=3Df5 - 1e6c: 00 00 00 20 nop\.b 0x0 - 1e70: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 1e76: 40 28 00 32 0a 00 fpcvt\.fxu\.s2 f4=3Df5 - 1e7c: 00 00 00 20 nop\.b 0x0 - 1e80: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 1e86: 40 28 00 32 0b 00 fpcvt\.fxu\.s3 f4=3Df5 - 1e8c: 00 00 00 20 nop\.b 0x0 - 1e90: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 1e96: 40 28 00 36 08 00 fpcvt\.fxu\.trunc\.s0 f4=3Df5 - 1e9c: 00 00 00 20 nop\.b 0x0 - 1ea0: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 1ea6: 40 28 00 36 08 00 fpcvt\.fxu\.trunc\.s0 f4=3Df5 - 1eac: 00 00 00 20 nop\.b 0x0 - 1eb0: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 1eb6: 40 28 00 36 09 00 fpcvt\.fxu\.trunc\.s1 f4=3Df5 - 1ebc: 00 00 00 20 nop\.b 0x0 - 1ec0: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 1ec6: 40 28 00 36 0a 00 fpcvt\.fxu\.trunc\.s2 f4=3Df5 - 1ecc: 00 00 00 20 nop\.b 0x0 - 1ed0: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 1ed6: 40 28 00 36 0b 00 fpcvt\.fxu\.trunc\.s3 f4=3Df5 - 1edc: 00 00 00 20 nop\.b 0x0 - 1ee0: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 1ee6: 40 28 00 38 00 00 fcvt\.xf f4=3Df5 - 1eec: 00 00 00 20 nop\.b 0x0 - 1ef0: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 1ef6: 40 00 14 02 40 00 fnorm\.s0 f4=3Df5 - 1efc: 00 00 00 20 nop\.b 0x0 - 1f00: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 1f06: 00 00 00 08 00 00 fsetc\.s0 0x0,0x0 - 1f0c: 00 00 00 20 nop\.b 0x0 - 1f10: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 1f16: 00 f8 fd 08 00 00 fsetc\.s0 0x3f,0x3f - 1f1c: 00 00 00 20 nop\.b 0x0 - 1f20: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 1f26: 00 00 00 08 00 00 fsetc\.s0 0x0,0x0 - 1f2c: 00 00 00 20 nop\.b 0x0 - 1f30: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 1f36: 00 f8 fd 08 00 00 fsetc\.s0 0x3f,0x3f - 1f3c: 00 00 00 20 nop\.b 0x0 - 1f40: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 1f46: 00 00 00 08 01 00 fsetc\.s1 0x0,0x0 - 1f4c: 00 00 00 20 nop\.b 0x0 - 1f50: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 1f56: 00 f8 fd 08 01 00 fsetc\.s1 0x3f,0x3f - 1f5c: 00 00 00 20 nop\.b 0x0 - 1f60: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 1f66: 00 00 00 08 02 00 fsetc\.s2 0x0,0x0 - 1f6c: 00 00 00 20 nop\.b 0x0 - 1f70: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 1f76: 00 f8 fd 08 02 00 fsetc\.s2 0x3f,0x3f - 1f7c: 00 00 00 20 nop\.b 0x0 - 1f80: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 1f86: 00 00 00 08 03 00 fsetc\.s3 0x0,0x0 - 1f8c: 00 00 00 20 nop\.b 0x0 - 1f90: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 1f96: 00 f8 fd 08 03 00 fsetc\.s3 0x3f,0x3f - 1f9c: 00 00 00 20 nop\.b 0x0 - 1fa0: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 1fa6: 00 00 00 0a 00 00 fclrf\.s0 - 1fac: 00 00 00 20 nop\.b 0x0 - 1fb0: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 1fb6: 00 00 00 0a 00 00 fclrf\.s0 - 1fbc: 00 00 00 20 nop\.b 0x0 - 1fc0: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 1fc6: 00 00 00 0a 01 00 fclrf\.s1 - 1fcc: 00 00 00 20 nop\.b 0x0 - 1fd0: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 1fd6: 00 00 00 0a 02 00 fclrf\.s2 - 1fdc: 00 00 00 20 nop\.b 0x0 - 1fe0: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 1fe6: 00 00 00 0a 03 00 fclrf\.s3 - 1fec: 00 00 00 20 nop\.b 0x0 - 1ff0: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 1ff6: 10 e0 ff 10 04 00 fchkf\.s0 0 <_start> - 1ffc: 00 00 00 20 nop\.b 0x0 - 2000: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 2006: 00 e0 ff 10 04 00 fchkf\.s0 0 <_start> - 200c: 00 00 00 20 nop\.b 0x0 - 2010: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 2016: f0 df ff 10 05 00 fchkf\.s1 0 <_start> - 201c: 00 00 00 20 nop\.b 0x0 - 2020: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 2026: e0 df ff 10 06 00 fchkf\.s2 0 <_start> - 202c: 00 00 00 20 nop\.b 0x0 - 2030: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 2036: d0 df ff 10 07 00 fchkf\.s3 0 <_start> - 203c: 00 00 00 20 nop\.b 0x0 - 2040: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 2046: 00 00 00 00 00 00 break\.f 0x0 - 204c: 00 00 00 20 nop\.b 0x0 - 2050: 1d 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 2056: 00 00 00 02 00 00 nop\.f 0x0 - 205c: 00 00 00 20 nop\.b 0x0;; - 2060: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 2066: 00 00 00 03 00 00 hint\.f 0x0 - 206c: 00 00 00 20 nop\.b 0x0 - 2070: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 2076: 00 00 00 03 00 00 hint\.f 0x0 - 207c: 00 00 00 20 nop\.b 0x0 - 2080: 1d 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 2086: f0 ff 1f 03 00 00 hint\.f 0x1ffff - 208c: 00 00 00 20 nop\.b 0x0;; diff --git a/gas/testsuite/gas/ia64/opc-f.pl b/gas/testsuite/gas/ia64/opc-f= .pl deleted file mode 100644 index d0f947bcf78..00000000000 --- a/gas/testsuite/gas/ia64/opc-f.pl +++ /dev/null @@ -1,174 +0,0 @@ -print ".text\n\t.type _start,@", "function\n_start:\n\n"; - -@sf =3D ( "", ".s0", ".s1", ".s2", ".s3" ); - -# Arithmetic - -foreach $i ( "fma", "fma.s", "fma.d", "fpma", - "fms", "fms.s", "fms.d", "fpms", - "fnma", "fnma.s", "fnma.d", "fpnma" ) { - foreach $s (@sf) { - print "\t${i}${s} f4 =3D f5, f6, f7\n"; - } - print "\n"; -} - -foreach $i ( "fmpy", "fmpy.s", "fmpy.d", "fpmpy", - "fadd", "fadd.s", "fadd.d", - "fsub", "fsub.s", "fsub.d", - "fnmpy", "fnmpy.s", "fnmpy.d", "fpnmpy" ) { - foreach $s (@sf) { - print "\t${i}${s} f4 =3D f5, f6\n"; - } - print "\n"; -} - -foreach $i ( "fnorm", "fnorm.s", "fnorm.d" ) {=20 - foreach $s (@sf) { - print "\t${i}${s} f4 =3D f5\n"; - } - print "\n"; -} - -# Fixed Point Multiply Add - -foreach $s ( ".l", ".lu", ".h", ".hu" ) { - print "\txma${s} f4 =3D f5, f6, f7\n"; -} -print "\n"; - -foreach $s ( ".l", ".lu", ".h", ".hu" ) { - print "\txmpy${s} f4 =3D f5, f6\n"; -} -print "\n"; - -# Parallel Floating Point Select - -print "\tfselect f4 =3D f5, f6, f7\n\n"; - -# Floating Point Compare - -@cmp =3D ( ".eq", ".lt", ".le", ".unord", ".gt", ".ge", ".neq", ".nlt",=20 - ".nle", ".ngt", ".nge", ".ord" ); - -@fctype =3D ( "", ".unc" ); - -foreach $c (@cmp) { - foreach $u (@fctype) { - foreach $s (@sf) { - print "\tfcmp${c}${u}${s} p3, p4 =3D f4, f5\n"; - } - } - print "\n"; -} - -# Floating Point Class - -foreach $u (@fctype) { - foreach $c ( '@nat', '@qnan', '@snan', '@pos', '@neg', '@unorm', - '@norm', '@inf', '0x1ff' ) { - foreach $m ( ".m", ".nm" ) { - print "\tfclass${m}${u} p3, p4 =3D f4, $c\n"; - } - } - print "\n"; -} - -# Approximation - -foreach $i ( "frcpa", "fprcpa" ) { - foreach $s (@sf) { - print "\t${i}${s} f4, p5 =3D f6, f7\n"; - } - print "\n"; -} - -foreach $i ( "frsqrta", "fprsqrta" ) { - foreach $s (@sf) { - print "\t${i}${s} f4, p5 =3D f6\n"; - } - print "\n"; -} - -# Min/Max - -foreach $i ( "fmin", "fmax", "famin", "famax", - "fpmin", "fpmax", "fpamin", "fpamax" ) { - foreach $s (@sf) { - print "\t${i}${s} f4 =3D f5, f6\n"; - } - print "\n"; -} - -# Parallel Compare - -foreach $c (@cmp) { - foreach $s (@sf) { - print "\tfpcmp${c}${s} f3 =3D f4, f5\n"; - } - print "\n"; -} - -# Merge and Logical - -foreach $i ( "fmerge.s", "fmerge.ns", "fmerge.se", "fmix.lr", "fmix.r", - "fmix.l", "fsxt.l", "fpack", "fswap", "fswap.nl", "fswap.nr", - "fand", "fandcm", "for", "fxor", "fpmerge.s", "fpmerge.ns", - "fpmerge.se" ) { - print "\t$i f4 =3D f5, f6\n"; -} -print "\n"; - -foreach $i ( "fabs", "fneg", "fnegabs", "fpabs", "fpneg", "fpnegabs" ) { - print "\t$i f4 =3D f5\n"; -} -print "\n"; - -# Convert Floating to Fixed - -foreach $b ( "fcvt", "fpcvt" ) { - foreach $f ( ".fx", ".fxu" ) { - foreach $t ( "", ".trunc" ) { - foreach $s (@sf) { - print "\t${b}${f}${t}${s} f4 =3D f5\n"; - } - print "\n"; - } - } -} - -# Convert Fixed to Floating - -foreach $e ( ".xf", ".xuf" ) { - print "\tfcvt$e f4 =3D f5\n"; -} -print "\n"; - -# Set Controls - -foreach $s (@sf) { - print "\tfsetc$s 0, 0\n"; - print "\tfsetc$s 0x3f, 0x3f\n"; -} -print "\n"; - -# Clear flags - -foreach $s (@sf) { - print "\tfclrf$s\n"; -} -print "\n"; - -# Check flags - -foreach $s (@sf) { - print "\tfchkf$s _start\n"; -} -print "\n"; - -# Misc - -print "\tbreak.f 0\n"; -print "\tnop.f 0;;\n"; -print "\n"; - diff --git a/gas/testsuite/gas/ia64/opc-f.s b/gas/testsuite/gas/ia64/opc-f.s deleted file mode 100644 index 4e6f51d5169..00000000000 --- a/gas/testsuite/gas/ia64/opc-f.s +++ /dev/null @@ -1,612 +0,0 @@ -.text - .type _start,@function -_start: - - fma f4 =3D f5, f6, f7 - fma.s0 f4 =3D f5, f6, f7 - fma.s1 f4 =3D f5, f6, f7 - fma.s2 f4 =3D f5, f6, f7 - fma.s3 f4 =3D f5, f6, f7 - - fma.s f4 =3D f5, f6, f7 - fma.s.s0 f4 =3D f5, f6, f7 - fma.s.s1 f4 =3D f5, f6, f7 - fma.s.s2 f4 =3D f5, f6, f7 - fma.s.s3 f4 =3D f5, f6, f7 - - fma.d f4 =3D f5, f6, f7 - fma.d.s0 f4 =3D f5, f6, f7 - fma.d.s1 f4 =3D f5, f6, f7 - fma.d.s2 f4 =3D f5, f6, f7 - fma.d.s3 f4 =3D f5, f6, f7 - - fpma f4 =3D f5, f6, f7 - fpma.s0 f4 =3D f5, f6, f7 - fpma.s1 f4 =3D f5, f6, f7 - fpma.s2 f4 =3D f5, f6, f7 - fpma.s3 f4 =3D f5, f6, f7 - - fms f4 =3D f5, f6, f7 - fms.s0 f4 =3D f5, f6, f7 - fms.s1 f4 =3D f5, f6, f7 - fms.s2 f4 =3D f5, f6, f7 - fms.s3 f4 =3D f5, f6, f7 - - fms.s f4 =3D f5, f6, f7 - fms.s.s0 f4 =3D f5, f6, f7 - fms.s.s1 f4 =3D f5, f6, f7 - fms.s.s2 f4 =3D f5, f6, f7 - fms.s.s3 f4 =3D f5, f6, f7 - - fms.d f4 =3D f5, f6, f7 - fms.d.s0 f4 =3D f5, f6, f7 - fms.d.s1 f4 =3D f5, f6, f7 - fms.d.s2 f4 =3D f5, f6, f7 - fms.d.s3 f4 =3D f5, f6, f7 - - fpms f4 =3D f5, f6, f7 - fpms.s0 f4 =3D f5, f6, f7 - fpms.s1 f4 =3D f5, f6, f7 - fpms.s2 f4 =3D f5, f6, f7 - fpms.s3 f4 =3D f5, f6, f7 - - fnma f4 =3D f5, f6, f7 - fnma.s0 f4 =3D f5, f6, f7 - fnma.s1 f4 =3D f5, f6, f7 - fnma.s2 f4 =3D f5, f6, f7 - fnma.s3 f4 =3D f5, f6, f7 - - fnma.s f4 =3D f5, f6, f7 - fnma.s.s0 f4 =3D f5, f6, f7 - fnma.s.s1 f4 =3D f5, f6, f7 - fnma.s.s2 f4 =3D f5, f6, f7 - fnma.s.s3 f4 =3D f5, f6, f7 - - fnma.d f4 =3D f5, f6, f7 - fnma.d.s0 f4 =3D f5, f6, f7 - fnma.d.s1 f4 =3D f5, f6, f7 - fnma.d.s2 f4 =3D f5, f6, f7 - fnma.d.s3 f4 =3D f5, f6, f7 - - fpnma f4 =3D f5, f6, f7 - fpnma.s0 f4 =3D f5, f6, f7 - fpnma.s1 f4 =3D f5, f6, f7 - fpnma.s2 f4 =3D f5, f6, f7 - fpnma.s3 f4 =3D f5, f6, f7 - - fmpy f4 =3D f5, f6 - fmpy.s0 f4 =3D f5, f6 - fmpy.s1 f4 =3D f5, f6 - fmpy.s2 f4 =3D f5, f6 - fmpy.s3 f4 =3D f5, f6 - - fmpy.s f4 =3D f5, f6 - fmpy.s.s0 f4 =3D f5, f6 - fmpy.s.s1 f4 =3D f5, f6 - fmpy.s.s2 f4 =3D f5, f6 - fmpy.s.s3 f4 =3D f5, f6 - - fmpy.d f4 =3D f5, f6 - fmpy.d.s0 f4 =3D f5, f6 - fmpy.d.s1 f4 =3D f5, f6 - fmpy.d.s2 f4 =3D f5, f6 - fmpy.d.s3 f4 =3D f5, f6 - - fpmpy f4 =3D f5, f6 - fpmpy.s0 f4 =3D f5, f6 - fpmpy.s1 f4 =3D f5, f6 - fpmpy.s2 f4 =3D f5, f6 - fpmpy.s3 f4 =3D f5, f6 - - fadd f4 =3D f5, f6 - fadd.s0 f4 =3D f5, f6 - fadd.s1 f4 =3D f5, f6 - fadd.s2 f4 =3D f5, f6 - fadd.s3 f4 =3D f5, f6 - - fadd.s f4 =3D f5, f6 - fadd.s.s0 f4 =3D f5, f6 - fadd.s.s1 f4 =3D f5, f6 - fadd.s.s2 f4 =3D f5, f6 - fadd.s.s3 f4 =3D f5, f6 - - fadd.d f4 =3D f5, f6 - fadd.d.s0 f4 =3D f5, f6 - fadd.d.s1 f4 =3D f5, f6 - fadd.d.s2 f4 =3D f5, f6 - fadd.d.s3 f4 =3D f5, f6 - - fsub f4 =3D f5, f6 - fsub.s0 f4 =3D f5, f6 - fsub.s1 f4 =3D f5, f6 - fsub.s2 f4 =3D f5, f6 - fsub.s3 f4 =3D f5, f6 - - fsub.s f4 =3D f5, f6 - fsub.s.s0 f4 =3D f5, f6 - fsub.s.s1 f4 =3D f5, f6 - fsub.s.s2 f4 =3D f5, f6 - fsub.s.s3 f4 =3D f5, f6 - - fsub.d f4 =3D f5, f6 - fsub.d.s0 f4 =3D f5, f6 - fsub.d.s1 f4 =3D f5, f6 - fsub.d.s2 f4 =3D f5, f6 - fsub.d.s3 f4 =3D f5, f6 - - fnmpy f4 =3D f5, f6 - fnmpy.s0 f4 =3D f5, f6 - fnmpy.s1 f4 =3D f5, f6 - fnmpy.s2 f4 =3D f5, f6 - fnmpy.s3 f4 =3D f5, f6 - - fnmpy.s f4 =3D f5, f6 - fnmpy.s.s0 f4 =3D f5, f6 - fnmpy.s.s1 f4 =3D f5, f6 - fnmpy.s.s2 f4 =3D f5, f6 - fnmpy.s.s3 f4 =3D f5, f6 - - fnmpy.d f4 =3D f5, f6 - fnmpy.d.s0 f4 =3D f5, f6 - fnmpy.d.s1 f4 =3D f5, f6 - fnmpy.d.s2 f4 =3D f5, f6 - fnmpy.d.s3 f4 =3D f5, f6 - - fpnmpy f4 =3D f5, f6 - fpnmpy.s0 f4 =3D f5, f6 - fpnmpy.s1 f4 =3D f5, f6 - fpnmpy.s2 f4 =3D f5, f6 - fpnmpy.s3 f4 =3D f5, f6 - - fnorm f4 =3D f5 - fnorm.s0 f4 =3D f5 - fnorm.s1 f4 =3D f5 - fnorm.s2 f4 =3D f5 - fnorm.s3 f4 =3D f5 - - fnorm.s f4 =3D f5 - fnorm.s.s0 f4 =3D f5 - fnorm.s.s1 f4 =3D f5 - fnorm.s.s2 f4 =3D f5 - fnorm.s.s3 f4 =3D f5 - - fnorm.d f4 =3D f5 - fnorm.d.s0 f4 =3D f5 - fnorm.d.s1 f4 =3D f5 - fnorm.d.s2 f4 =3D f5 - fnorm.d.s3 f4 =3D f5 - - xma.l f4 =3D f5, f6, f7 - xma.lu f4 =3D f5, f6, f7 - xma.h f4 =3D f5, f6, f7 - xma.hu f4 =3D f5, f6, f7 - - xmpy.l f4 =3D f5, f6 - xmpy.lu f4 =3D f5, f6 - xmpy.h f4 =3D f5, f6 - xmpy.hu f4 =3D f5, f6 - - fselect f4 =3D f5, f6, f7 - - fcmp.eq p3, p4 =3D f4, f5 - fcmp.eq.s0 p3, p4 =3D f4, f5 - fcmp.eq.s1 p3, p4 =3D f4, f5 - fcmp.eq.s2 p3, p4 =3D f4, f5 - fcmp.eq.s3 p3, p4 =3D f4, f5 - fcmp.eq.unc p3, p4 =3D f4, f5 - fcmp.eq.unc.s0 p3, p4 =3D f4, f5 - fcmp.eq.unc.s1 p3, p4 =3D f4, f5 - fcmp.eq.unc.s2 p3, p4 =3D f4, f5 - fcmp.eq.unc.s3 p3, p4 =3D f4, f5 - - fcmp.lt p3, p4 =3D f4, f5 - fcmp.lt.s0 p3, p4 =3D f4, f5 - fcmp.lt.s1 p3, p4 =3D f4, f5 - fcmp.lt.s2 p3, p4 =3D f4, f5 - fcmp.lt.s3 p3, p4 =3D f4, f5 - fcmp.lt.unc p3, p4 =3D f4, f5 - fcmp.lt.unc.s0 p3, p4 =3D f4, f5 - fcmp.lt.unc.s1 p3, p4 =3D f4, f5 - fcmp.lt.unc.s2 p3, p4 =3D f4, f5 - fcmp.lt.unc.s3 p3, p4 =3D f4, f5 - - fcmp.le p3, p4 =3D f4, f5 - fcmp.le.s0 p3, p4 =3D f4, f5 - fcmp.le.s1 p3, p4 =3D f4, f5 - fcmp.le.s2 p3, p4 =3D f4, f5 - fcmp.le.s3 p3, p4 =3D f4, f5 - fcmp.le.unc p3, p4 =3D f4, f5 - fcmp.le.unc.s0 p3, p4 =3D f4, f5 - fcmp.le.unc.s1 p3, p4 =3D f4, f5 - fcmp.le.unc.s2 p3, p4 =3D f4, f5 - fcmp.le.unc.s3 p3, p4 =3D f4, f5 - - fcmp.unord p3, p4 =3D f4, f5 - fcmp.unord.s0 p3, p4 =3D f4, f5 - fcmp.unord.s1 p3, p4 =3D f4, f5 - fcmp.unord.s2 p3, p4 =3D f4, f5 - fcmp.unord.s3 p3, p4 =3D f4, f5 - fcmp.unord.unc p3, p4 =3D f4, f5 - fcmp.unord.unc.s0 p3, p4 =3D f4, f5 - fcmp.unord.unc.s1 p3, p4 =3D f4, f5 - fcmp.unord.unc.s2 p3, p4 =3D f4, f5 - fcmp.unord.unc.s3 p3, p4 =3D f4, f5 - - fcmp.gt p3, p4 =3D f4, f5 - fcmp.gt.s0 p3, p4 =3D f4, f5 - fcmp.gt.s1 p3, p4 =3D f4, f5 - fcmp.gt.s2 p3, p4 =3D f4, f5 - fcmp.gt.s3 p3, p4 =3D f4, f5 - fcmp.gt.unc p3, p4 =3D f4, f5 - fcmp.gt.unc.s0 p3, p4 =3D f4, f5 - fcmp.gt.unc.s1 p3, p4 =3D f4, f5 - fcmp.gt.unc.s2 p3, p4 =3D f4, f5 - fcmp.gt.unc.s3 p3, p4 =3D f4, f5 - - fcmp.ge p3, p4 =3D f4, f5 - fcmp.ge.s0 p3, p4 =3D f4, f5 - fcmp.ge.s1 p3, p4 =3D f4, f5 - fcmp.ge.s2 p3, p4 =3D f4, f5 - fcmp.ge.s3 p3, p4 =3D f4, f5 - fcmp.ge.unc p3, p4 =3D f4, f5 - fcmp.ge.unc.s0 p3, p4 =3D f4, f5 - fcmp.ge.unc.s1 p3, p4 =3D f4, f5 - fcmp.ge.unc.s2 p3, p4 =3D f4, f5 - fcmp.ge.unc.s3 p3, p4 =3D f4, f5 - - fcmp.neq p3, p4 =3D f4, f5 - fcmp.neq.s0 p3, p4 =3D f4, f5 - fcmp.neq.s1 p3, p4 =3D f4, f5 - fcmp.neq.s2 p3, p4 =3D f4, f5 - fcmp.neq.s3 p3, p4 =3D f4, f5 - fcmp.neq.unc p3, p4 =3D f4, f5 - fcmp.neq.unc.s0 p3, p4 =3D f4, f5 - fcmp.neq.unc.s1 p3, p4 =3D f4, f5 - fcmp.neq.unc.s2 p3, p4 =3D f4, f5 - fcmp.neq.unc.s3 p3, p4 =3D f4, f5 - - fcmp.nlt p3, p4 =3D f4, f5 - fcmp.nlt.s0 p3, p4 =3D f4, f5 - fcmp.nlt.s1 p3, p4 =3D f4, f5 - fcmp.nlt.s2 p3, p4 =3D f4, f5 - fcmp.nlt.s3 p3, p4 =3D f4, f5 - fcmp.nlt.unc p3, p4 =3D f4, f5 - fcmp.nlt.unc.s0 p3, p4 =3D f4, f5 - fcmp.nlt.unc.s1 p3, p4 =3D f4, f5 - fcmp.nlt.unc.s2 p3, p4 =3D f4, f5 - fcmp.nlt.unc.s3 p3, p4 =3D f4, f5 - - fcmp.nle p3, p4 =3D f4, f5 - fcmp.nle.s0 p3, p4 =3D f4, f5 - fcmp.nle.s1 p3, p4 =3D f4, f5 - fcmp.nle.s2 p3, p4 =3D f4, f5 - fcmp.nle.s3 p3, p4 =3D f4, f5 - fcmp.nle.unc p3, p4 =3D f4, f5 - fcmp.nle.unc.s0 p3, p4 =3D f4, f5 - fcmp.nle.unc.s1 p3, p4 =3D f4, f5 - fcmp.nle.unc.s2 p3, p4 =3D f4, f5 - fcmp.nle.unc.s3 p3, p4 =3D f4, f5 - - fcmp.ngt p3, p4 =3D f4, f5 - fcmp.ngt.s0 p3, p4 =3D f4, f5 - fcmp.ngt.s1 p3, p4 =3D f4, f5 - fcmp.ngt.s2 p3, p4 =3D f4, f5 - fcmp.ngt.s3 p3, p4 =3D f4, f5 - fcmp.ngt.unc p3, p4 =3D f4, f5 - fcmp.ngt.unc.s0 p3, p4 =3D f4, f5 - fcmp.ngt.unc.s1 p3, p4 =3D f4, f5 - fcmp.ngt.unc.s2 p3, p4 =3D f4, f5 - fcmp.ngt.unc.s3 p3, p4 =3D f4, f5 - - fcmp.nge p3, p4 =3D f4, f5 - fcmp.nge.s0 p3, p4 =3D f4, f5 - fcmp.nge.s1 p3, p4 =3D f4, f5 - fcmp.nge.s2 p3, p4 =3D f4, f5 - fcmp.nge.s3 p3, p4 =3D f4, f5 - fcmp.nge.unc p3, p4 =3D f4, f5 - fcmp.nge.unc.s0 p3, p4 =3D f4, f5 - fcmp.nge.unc.s1 p3, p4 =3D f4, f5 - fcmp.nge.unc.s2 p3, p4 =3D f4, f5 - fcmp.nge.unc.s3 p3, p4 =3D f4, f5 - - fcmp.ord p3, p4 =3D f4, f5 - fcmp.ord.s0 p3, p4 =3D f4, f5 - fcmp.ord.s1 p3, p4 =3D f4, f5 - fcmp.ord.s2 p3, p4 =3D f4, f5 - fcmp.ord.s3 p3, p4 =3D f4, f5 - fcmp.ord.unc p3, p4 =3D f4, f5 - fcmp.ord.unc.s0 p3, p4 =3D f4, f5 - fcmp.ord.unc.s1 p3, p4 =3D f4, f5 - fcmp.ord.unc.s2 p3, p4 =3D f4, f5 - fcmp.ord.unc.s3 p3, p4 =3D f4, f5 - - fclass.m p3, p4 =3D f4, @nat - fclass.nm p3, p4 =3D f4, @nat - fclass.m p3, p4 =3D f4, @qnan - fclass.nm p3, p4 =3D f4, @qnan - fclass.m p3, p4 =3D f4, @snan - fclass.nm p3, p4 =3D f4, @snan - fclass.m p3, p4 =3D f4, @pos - fclass.nm p3, p4 =3D f4, @pos - fclass.m p3, p4 =3D f4, @neg - fclass.nm p3, p4 =3D f4, @neg - fclass.m p3, p4 =3D f4, @unorm - fclass.nm p3, p4 =3D f4, @unorm - fclass.m p3, p4 =3D f4, @norm - fclass.nm p3, p4 =3D f4, @norm - fclass.m p3, p4 =3D f4, @inf - fclass.nm p3, p4 =3D f4, @inf - fclass.m p3, p4 =3D f4, 0x1ff - fclass.nm p3, p4 =3D f4, 0x1ff - - fclass.m.unc p3, p4 =3D f4, @nat - fclass.nm.unc p3, p4 =3D f4, @nat - fclass.m.unc p3, p4 =3D f4, @qnan - fclass.nm.unc p3, p4 =3D f4, @qnan - fclass.m.unc p3, p4 =3D f4, @snan - fclass.nm.unc p3, p4 =3D f4, @snan - fclass.m.unc p3, p4 =3D f4, @pos - fclass.nm.unc p3, p4 =3D f4, @pos - fclass.m.unc p3, p4 =3D f4, @neg - fclass.nm.unc p3, p4 =3D f4, @neg - fclass.m.unc p3, p4 =3D f4, @unorm - fclass.nm.unc p3, p4 =3D f4, @unorm - fclass.m.unc p3, p4 =3D f4, @norm - fclass.nm.unc p3, p4 =3D f4, @norm - fclass.m.unc p3, p4 =3D f4, @inf - fclass.nm.unc p3, p4 =3D f4, @inf - fclass.m.unc p3, p4 =3D f4, 0x1ff - fclass.nm.unc p3, p4 =3D f4, 0x1ff - - frcpa f4, p5 =3D f6, f7 - frcpa.s0 f4, p5 =3D f6, f7 - frcpa.s1 f4, p5 =3D f6, f7 - frcpa.s2 f4, p5 =3D f6, f7 - frcpa.s3 f4, p5 =3D f6, f7 - - fprcpa f4, p5 =3D f6, f7 - fprcpa.s0 f4, p5 =3D f6, f7 - fprcpa.s1 f4, p5 =3D f6, f7 - fprcpa.s2 f4, p5 =3D f6, f7 - fprcpa.s3 f4, p5 =3D f6, f7 - - frsqrta f4, p5 =3D f6 - frsqrta.s0 f4, p5 =3D f6 - frsqrta.s1 f4, p5 =3D f6 - frsqrta.s2 f4, p5 =3D f6 - frsqrta.s3 f4, p5 =3D f6 - - fprsqrta f4, p5 =3D f6 - fprsqrta.s0 f4, p5 =3D f6 - fprsqrta.s1 f4, p5 =3D f6 - fprsqrta.s2 f4, p5 =3D f6 - fprsqrta.s3 f4, p5 =3D f6 - - fmin f4 =3D f5, f6 - fmin.s0 f4 =3D f5, f6 - fmin.s1 f4 =3D f5, f6 - fmin.s2 f4 =3D f5, f6 - fmin.s3 f4 =3D f5, f6 - - fmax f4 =3D f5, f6 - fmax.s0 f4 =3D f5, f6 - fmax.s1 f4 =3D f5, f6 - fmax.s2 f4 =3D f5, f6 - fmax.s3 f4 =3D f5, f6 - - famin f4 =3D f5, f6 - famin.s0 f4 =3D f5, f6 - famin.s1 f4 =3D f5, f6 - famin.s2 f4 =3D f5, f6 - famin.s3 f4 =3D f5, f6 - - famax f4 =3D f5, f6 - famax.s0 f4 =3D f5, f6 - famax.s1 f4 =3D f5, f6 - famax.s2 f4 =3D f5, f6 - famax.s3 f4 =3D f5, f6 - - fpmin f4 =3D f5, f6 - fpmin.s0 f4 =3D f5, f6 - fpmin.s1 f4 =3D f5, f6 - fpmin.s2 f4 =3D f5, f6 - fpmin.s3 f4 =3D f5, f6 - - fpmax f4 =3D f5, f6 - fpmax.s0 f4 =3D f5, f6 - fpmax.s1 f4 =3D f5, f6 - fpmax.s2 f4 =3D f5, f6 - fpmax.s3 f4 =3D f5, f6 - - fpamin f4 =3D f5, f6 - fpamin.s0 f4 =3D f5, f6 - fpamin.s1 f4 =3D f5, f6 - fpamin.s2 f4 =3D f5, f6 - fpamin.s3 f4 =3D f5, f6 - - fpamax f4 =3D f5, f6 - fpamax.s0 f4 =3D f5, f6 - fpamax.s1 f4 =3D f5, f6 - fpamax.s2 f4 =3D f5, f6 - fpamax.s3 f4 =3D f5, f6 - - fpcmp.eq f3 =3D f4, f5 - fpcmp.eq.s0 f3 =3D f4, f5 - fpcmp.eq.s1 f3 =3D f4, f5 - fpcmp.eq.s2 f3 =3D f4, f5 - fpcmp.eq.s3 f3 =3D f4, f5 - - fpcmp.lt f3 =3D f4, f5 - fpcmp.lt.s0 f3 =3D f4, f5 - fpcmp.lt.s1 f3 =3D f4, f5 - fpcmp.lt.s2 f3 =3D f4, f5 - fpcmp.lt.s3 f3 =3D f4, f5 - - fpcmp.le f3 =3D f4, f5 - fpcmp.le.s0 f3 =3D f4, f5 - fpcmp.le.s1 f3 =3D f4, f5 - fpcmp.le.s2 f3 =3D f4, f5 - fpcmp.le.s3 f3 =3D f4, f5 - - fpcmp.unord f3 =3D f4, f5 - fpcmp.unord.s0 f3 =3D f4, f5 - fpcmp.unord.s1 f3 =3D f4, f5 - fpcmp.unord.s2 f3 =3D f4, f5 - fpcmp.unord.s3 f3 =3D f4, f5 - - fpcmp.gt f3 =3D f4, f5 - fpcmp.gt.s0 f3 =3D f4, f5 - fpcmp.gt.s1 f3 =3D f4, f5 - fpcmp.gt.s2 f3 =3D f4, f5 - fpcmp.gt.s3 f3 =3D f4, f5 - - fpcmp.ge f3 =3D f4, f5 - fpcmp.ge.s0 f3 =3D f4, f5 - fpcmp.ge.s1 f3 =3D f4, f5 - fpcmp.ge.s2 f3 =3D f4, f5 - fpcmp.ge.s3 f3 =3D f4, f5 - - fpcmp.neq f3 =3D f4, f5 - fpcmp.neq.s0 f3 =3D f4, f5 - fpcmp.neq.s1 f3 =3D f4, f5 - fpcmp.neq.s2 f3 =3D f4, f5 - fpcmp.neq.s3 f3 =3D f4, f5 - - fpcmp.nlt f3 =3D f4, f5 - fpcmp.nlt.s0 f3 =3D f4, f5 - fpcmp.nlt.s1 f3 =3D f4, f5 - fpcmp.nlt.s2 f3 =3D f4, f5 - fpcmp.nlt.s3 f3 =3D f4, f5 - - fpcmp.nle f3 =3D f4, f5 - fpcmp.nle.s0 f3 =3D f4, f5 - fpcmp.nle.s1 f3 =3D f4, f5 - fpcmp.nle.s2 f3 =3D f4, f5 - fpcmp.nle.s3 f3 =3D f4, f5 - - fpcmp.ngt f3 =3D f4, f5 - fpcmp.ngt.s0 f3 =3D f4, f5 - fpcmp.ngt.s1 f3 =3D f4, f5 - fpcmp.ngt.s2 f3 =3D f4, f5 - fpcmp.ngt.s3 f3 =3D f4, f5 - - fpcmp.nge f3 =3D f4, f5 - fpcmp.nge.s0 f3 =3D f4, f5 - fpcmp.nge.s1 f3 =3D f4, f5 - fpcmp.nge.s2 f3 =3D f4, f5 - fpcmp.nge.s3 f3 =3D f4, f5 - - fpcmp.ord f3 =3D f4, f5 - fpcmp.ord.s0 f3 =3D f4, f5 - fpcmp.ord.s1 f3 =3D f4, f5 - fpcmp.ord.s2 f3 =3D f4, f5 - fpcmp.ord.s3 f3 =3D f4, f5 - - fmerge.s f4 =3D f5, f6 - fmerge.ns f4 =3D f5, f6 - fmerge.se f4 =3D f5, f6 - fmix.lr f4 =3D f5, f6 - fmix.r f4 =3D f5, f6 - fmix.l f4 =3D f5, f6 - fsxt.l f4 =3D f5, f6 - fpack f4 =3D f5, f6 - fswap f4 =3D f5, f6 - fswap.nl f4 =3D f5, f6 - fswap.nr f4 =3D f5, f6 - fand f4 =3D f5, f6 - fandcm f4 =3D f5, f6 - for f4 =3D f5, f6 - fxor f4 =3D f5, f6 - fpmerge.s f4 =3D f5, f6 - fpmerge.ns f4 =3D f5, f6 - fpmerge.se f4 =3D f5, f6 - - fabs f4 =3D f5 - fneg f4 =3D f5 - fnegabs f4 =3D f5 - fpabs f4 =3D f5 - fpneg f4 =3D f5 - fpnegabs f4 =3D f5 - - fcvt.fx f4 =3D f5 - fcvt.fx.s0 f4 =3D f5 - fcvt.fx.s1 f4 =3D f5 - fcvt.fx.s2 f4 =3D f5 - fcvt.fx.s3 f4 =3D f5 - - fcvt.fx.trunc f4 =3D f5 - fcvt.fx.trunc.s0 f4 =3D f5 - fcvt.fx.trunc.s1 f4 =3D f5 - fcvt.fx.trunc.s2 f4 =3D f5 - fcvt.fx.trunc.s3 f4 =3D f5 - - fcvt.fxu f4 =3D f5 - fcvt.fxu.s0 f4 =3D f5 - fcvt.fxu.s1 f4 =3D f5 - fcvt.fxu.s2 f4 =3D f5 - fcvt.fxu.s3 f4 =3D f5 - - fcvt.fxu.trunc f4 =3D f5 - fcvt.fxu.trunc.s0 f4 =3D f5 - fcvt.fxu.trunc.s1 f4 =3D f5 - fcvt.fxu.trunc.s2 f4 =3D f5 - fcvt.fxu.trunc.s3 f4 =3D f5 - - fpcvt.fx f4 =3D f5 - fpcvt.fx.s0 f4 =3D f5 - fpcvt.fx.s1 f4 =3D f5 - fpcvt.fx.s2 f4 =3D f5 - fpcvt.fx.s3 f4 =3D f5 - - fpcvt.fx.trunc f4 =3D f5 - fpcvt.fx.trunc.s0 f4 =3D f5 - fpcvt.fx.trunc.s1 f4 =3D f5 - fpcvt.fx.trunc.s2 f4 =3D f5 - fpcvt.fx.trunc.s3 f4 =3D f5 - - fpcvt.fxu f4 =3D f5 - fpcvt.fxu.s0 f4 =3D f5 - fpcvt.fxu.s1 f4 =3D f5 - fpcvt.fxu.s2 f4 =3D f5 - fpcvt.fxu.s3 f4 =3D f5 - - fpcvt.fxu.trunc f4 =3D f5 - fpcvt.fxu.trunc.s0 f4 =3D f5 - fpcvt.fxu.trunc.s1 f4 =3D f5 - fpcvt.fxu.trunc.s2 f4 =3D f5 - fpcvt.fxu.trunc.s3 f4 =3D f5 - - fcvt.xf f4 =3D f5 - fcvt.xuf f4 =3D f5 - - fsetc 0, 0 - fsetc 0x3f, 0x3f - fsetc.s0 0, 0 - fsetc.s0 0x3f, 0x3f - fsetc.s1 0, 0 - fsetc.s1 0x3f, 0x3f - fsetc.s2 0, 0 - fsetc.s2 0x3f, 0x3f - fsetc.s3 0, 0 - fsetc.s3 0x3f, 0x3f - - fclrf - fclrf.s0 - fclrf.s1 - fclrf.s2 - fclrf.s3 - - fchkf _start - fchkf.s0 _start - fchkf.s1 _start - fchkf.s2 _start - fchkf.s3 _start - - break.f 0 - nop.f 0;; - - # instructions added by SDM2.1: - - hint.f 0 - hint.f @pause - hint.f 0x1ffff diff --git a/gas/testsuite/gas/ia64/opc-i.d b/gas/testsuite/gas/ia64/opc-i.d deleted file mode 100644 index 6efcc9a5f62..00000000000 --- a/gas/testsuite/gas/ia64/opc-i.d +++ /dev/null @@ -1,312 +0,0 @@ -# as: -xnone -mtune=3Ditanium1 -# objdump: -d -# name: ia64 opc-i - -.*: +file format .* - -Disassembly of section \.text: - -0+000 <_start>: - 0: 00 00 00 00 01 00 \[MII\] nop\.m 0x0 - 6: 40 28 18 8c 38 80 pmpyshr2 r4=3Dr5,r6,0 - c: 50 30 68 71 pmpyshr2\.u r4=3Dr5,r6,16 - 10: 00 00 00 00 01 00 \[MII\] nop\.m 0x0 - 16: 40 28 18 b4 3a 80 pmpy2\.r r4=3Dr5,r6 - 1c: 50 30 78 75 pmpy2\.l r4=3Dr5,r6 - 20: 00 00 00 00 01 00 \[MII\] nop\.m 0x0 - 26: 40 28 18 20 3a 80 mix1\.r r4=3Dr5,r6 - 2c: 50 30 40 75 mix2\.r r4=3Dr5,r6 - 30: 00 00 00 00 01 00 \[MII\] nop\.m 0x0 - 36: 40 28 18 20 3e 80 mix4\.r r4=3Dr5,r6 - 3c: 50 30 50 74 mix1\.l r4=3Dr5,r6 - 40: 00 00 00 00 01 00 \[MII\] nop\.m 0x0 - 46: 40 28 18 a8 3a 80 mix2\.l r4=3Dr5,r6 - 4c: 50 30 50 7c mix4\.l r4=3Dr5,r6 - 50: 00 00 00 00 01 00 \[MII\] nop\.m 0x0 - 56: 40 28 18 80 3a 80 pack2\.uss r4=3Dr5,r6 - 5c: 50 30 10 75 pack2\.sss r4=3Dr5,r6 - 60: 00 00 00 00 01 00 \[MII\] nop\.m 0x0 - 66: 40 28 18 08 3e 80 pack4\.sss r4=3Dr5,r6 - 6c: 50 30 20 74 unpack1\.h r4=3Dr5,r6 - 70: 00 00 00 00 01 00 \[MII\] nop\.m 0x0 - 76: 40 28 18 90 3a 80 unpack2\.h r4=3Dr5,r6 - 7c: 50 30 20 7c unpack4\.h r4=3Dr5,r6 - 80: 00 00 00 00 01 00 \[MII\] nop\.m 0x0 - 86: 40 28 18 18 3a 80 unpack1\.l r4=3Dr5,r6 - 8c: 50 30 30 75 unpack2\.l r4=3Dr5,r6 - 90: 00 00 00 00 01 00 \[MII\] nop\.m 0x0 - 96: 40 28 18 18 3e 80 unpack4\.l r4=3Dr5,r6 - 9c: 50 30 08 74 pmin1\.u r4=3Dr5,r6 - a0: 00 00 00 00 01 00 \[MII\] nop\.m 0x0 - a6: 40 28 18 14 3a 80 pmax1\.u r4=3Dr5,r6 - ac: 50 30 18 75 pmin2 r4=3Dr5,r6 - b0: 00 00 00 00 01 00 \[MII\] nop\.m 0x0 - b6: 40 28 18 9c 3a 80 pmax2 r4=3Dr5,r6 - bc: 50 30 58 74 psad1 r4=3Dr5,r6 - c0: 00 00 00 00 01 00 \[MII\] nop\.m 0x0 - c6: 40 28 2c 28 3b 80 mux1 r4=3Dr5,@rev - cc: 50 40 50 76 mux1 r4=3Dr5,@mix - d0: 00 00 00 00 01 00 \[MII\] nop\.m 0x0 - d6: 40 28 24 28 3b 80 mux1 r4=3Dr5,@shuf - dc: 50 50 50 76 mux1 r4=3Dr5,@alt - e0: 00 00 00 00 01 00 \[MII\] nop\.m 0x0 - e6: 40 28 00 28 3b 80 mux1 r4=3Dr5,@brcst - ec: 50 00 50 77 mux2 r4=3Dr5,0x0 - f0: 00 00 00 00 01 00 \[MII\] nop\.m 0x0 - f6: 40 28 fc ab 3b 80 mux2 r4=3Dr5,0xff - fc: 50 50 55 77 mux2 r4=3Dr5,0xaa - 100: 00 00 00 00 01 00 \[MII\] nop\.m 0x0 - 106: 40 30 14 88 38 80 pshr2 r4=3Dr5,r6 - 10c: 00 28 18 73 pshr2 r4=3Dr5,0 - 110: 00 00 00 00 01 00 \[MII\] nop\.m 0x0 - 116: 40 80 14 8c 39 80 pshr2 r4=3Dr5,8 - 11c: e0 2b 18 73 pshr2 r4=3Dr5,31 - 120: 00 00 00 00 01 00 \[MII\] nop\.m 0x0 - 126: 40 30 14 08 3c 80 pshr4 r4=3Dr5,r6 - 12c: 00 28 18 7a pshr4 r4=3Dr5,0 - 130: 00 00 00 00 01 00 \[MII\] nop\.m 0x0 - 136: 40 80 14 0c 3d 80 pshr4 r4=3Dr5,8 - 13c: e0 2b 18 7a pshr4 r4=3Dr5,31 - 140: 00 00 00 00 01 00 \[MII\] nop\.m 0x0 - 146: 40 30 14 80 38 80 pshr2\.u r4=3Dr5,r6 - 14c: 00 28 08 73 pshr2\.u r4=3Dr5,0 - 150: 00 00 00 00 01 00 \[MII\] nop\.m 0x0 - 156: 40 80 14 84 39 80 pshr2\.u r4=3Dr5,8 - 15c: e0 2b 08 73 pshr2\.u r4=3Dr5,31 - 160: 00 00 00 00 01 00 \[MII\] nop\.m 0x0 - 166: 40 30 14 00 3c 80 pshr4\.u r4=3Dr5,r6 - 16c: 00 28 08 7a pshr4\.u r4=3Dr5,0 - 170: 00 00 00 00 01 00 \[MII\] nop\.m 0x0 - 176: 40 80 14 04 3d 80 pshr4\.u r4=3Dr5,8 - 17c: e0 2b 08 7a pshr4\.u r4=3Dr5,31 - 180: 00 00 00 00 01 00 \[MII\] nop\.m 0x0 - 186: 40 30 14 88 3c 80 shr r4=3Dr5,r6 - 18c: 60 28 00 79 shr\.u r4=3Dr5,r6 - 190: 00 00 00 00 01 00 \[MII\] nop\.m 0x0 - 196: 40 28 18 90 38 80 pshl2 r4=3Dr5,r6 - 19c: 50 f8 28 77 pshl2 r4=3Dr5,0 - 1a0: 00 00 00 00 01 00 \[MII\] nop\.m 0x0 - 1a6: 40 28 5c 94 3b 80 pshl2 r4=3Dr5,8 - 1ac: 50 00 28 77 pshl2 r4=3Dr5,31 - 1b0: 00 00 00 00 01 00 \[MII\] nop\.m 0x0 - 1b6: 40 28 18 10 3c 80 pshl4 r4=3Dr5,r6 - 1bc: 50 f8 28 7e pshl4 r4=3Dr5,0 - 1c0: 00 00 00 00 01 00 \[MII\] nop\.m 0x0 - 1c6: 40 28 5c 14 3f 80 pshl4 r4=3Dr5,8 - 1cc: 50 00 28 7e pshl4 r4=3Dr5,31 - 1d0: 00 00 00 00 01 00 \[MII\] nop\.m 0x0 - 1d6: 40 28 18 90 3c 80 shl r4=3Dr5,r6 - 1dc: 00 28 48 73 popcnt r4=3Dr5 - 1e0: 00 00 00 00 01 00 \[MII\] nop\.m 0x0 - 1e6: 40 28 18 00 2b 80 shrp r4=3Dr5,r6,0 - 1ec: 50 30 30 56 shrp r4=3Dr5,r6,12 - 1f0: 00 00 00 00 01 00 \[MII\] nop\.m 0x0 - 1f6: 40 28 18 7e 2b 80 shrp r4=3Dr5,r6,63 - 1fc: 10 28 3c 52 extr r4=3Dr5,0,16 - 200: 00 00 00 00 01 00 \[MII\] nop\.m 0x0 - 206: 40 08 14 7c 29 80 extr r4=3Dr5,0,63 - 20c: 50 29 9c 52 extr r4=3Dr5,10,40 - 210: 00 00 00 00 01 00 \[MII\] nop\.m 0x0 - 216: 40 00 14 1e 29 80 extr\.u r4=3Dr5,0,16 - 21c: 00 28 f8 52 extr\.u r4=3Dr5,0,63 - 220: 00 00 00 00 01 00 \[MII\] nop\.m 0x0 - 226: 40 a0 14 4e 29 80 extr\.u r4=3Dr5,10,40 - 22c: 50 f8 3d 53 dep\.z r4=3Dr5,0,16 - 230: 00 00 00 00 01 00 \[MII\] nop\.m 0x0 - 236: 40 28 fc fc 29 80 dep\.z r4=3Dr5,0,63 - 23c: 50 a8 9d 53 dep\.z r4=3Dr5,10,40 - 240: 00 00 00 00 01 00 \[MII\] nop\.m 0x0 - 246: 40 00 fc 9f 29 80 dep\.z r4=3D0,0,16 - 24c: f0 ff fb 53 dep\.z r4=3D127,0,63 - 250: 00 00 00 00 01 00 \[MII\] nop\.m 0x0 - 256: 40 00 e8 e3 2d 80 dep\.z r4=3D-128,5,50 - 25c: 50 ad 9f 53 dep\.z r4=3D85,10,40 - 260: 00 00 00 00 01 00 \[MII\] nop\.m 0x0 - 266: 40 f0 17 9e 2b 80 dep r4=3D0,r5,0,16 - 26c: e0 2f f8 5f dep r4=3D-1,r5,0,63 - 270: 0c 00 00 00 01 00 \[MFI\] nop\.m 0x0 - 276: 00 00 00 02 00 80 nop\.f 0x0 - 27c: 50 30 58 4d dep r4=3Dr5,r6,10,7 - 280: 04 00 00 00 01 00 \[MLX\] nop\.m 0x0 - 286: 00 00 00 00 00 80 movl r4=3D0x0 - 28c: 00 00 00 60=20 - 290: 04 00 00 00 01 c0 \[MLX\] nop\.m 0x0 - 296: ff ff ff ff 7f 80 movl r4=3D0xffffffffffffffff - 29c: f0 f7 ff 6f=20 - 2a0: 04 00 00 00 01 80 \[MLX\] nop\.m 0x0 - 2a6: 90 78 56 34 12 80 movl r4=3D0x1234567890abcdef - 2ac: f0 76 6d 66=20 - 2b0: 00 00 00 00 01 00 \[MII\] nop\.m 0x0 - 2b6: 00 00 00 00 00 e0 break\.i 0x0 - 2bc: ff ff 01 08 break\.i 0x1fffff - 2c0: 00 00 00 00 01 00 \[MII\] nop\.m 0x0 - 2c6: 00 00 00 02 00 e0 nop\.i 0x0 - 2cc: ff ff 05 08 nop\.i 0x1fffff - 2d0: 00 00 00 00 01 00 \[MII\] nop\.m 0x0 - 2d6: 30 25 fc ff 04 80 chk\.s\.i r4,0 <_start> - 2dc: 00 00 c4 00 mov r4=3Db0 - 2e0: 00 00 00 00 01 00 \[MII\] nop\.m 0x0 - 2e6: 00 20 04 80 03 00 mov b0=3Dr4 - 2ec: 40 00 00 03 mov pr=3Dr4,0x0 - 2f0: 00 00 00 00 01 00 \[MII\] nop\.m 0x0 - 2f6: a0 21 80 84 01 e0 mov pr=3Dr4,0x1234 - 2fc: 4f 80 7f 0b mov pr=3Dr4,0xfffffffffffffffe - 300: 00 00 00 00 01 00 \[MII\] nop\.m 0x0 - 306: 00 00 00 00 01 e0 mov pr\.rot=3D0x0 - 30c: 7f 00 00 02 mov pr\.rot=3D0x3ff0000 - 310: 00 00 00 00 01 00 \[MII\] nop\.m 0x0 - 316: 00 c0 ff 7f 05 80 mov pr\.rot=3D0xfffffffffc000000 - 31c: 00 28 40 00 zxt1 r4=3Dr5 - 320: 00 00 00 00 01 00 \[MII\] nop\.m 0x0 - 326: 40 00 14 22 00 80 zxt2 r4=3Dr5 - 32c: 00 28 48 00 zxt4 r4=3Dr5 - 330: 00 00 00 00 01 00 \[MII\] nop\.m 0x0 - 336: 40 00 14 28 00 80 sxt1 r4=3Dr5 - 33c: 00 28 54 00 sxt2 r4=3Dr5 - 340: 00 00 00 00 01 00 \[MII\] nop\.m 0x0 - 346: 40 00 14 2c 00 80 sxt4 r4=3Dr5 - 34c: 00 28 60 00 czx1\.l r4=3Dr5 - 350: 00 00 00 00 01 00 \[MII\] nop\.m 0x0 - 356: 40 00 14 32 00 80 czx2\.l r4=3Dr5 - 35c: 00 28 70 00 czx1\.r r4=3Dr5 - 360: 00 00 00 00 01 00 \[MII\] nop\.m 0x0 - 366: 40 00 14 3a 00 40 czx2\.r r4=3Dr5 - 36c: 00 20 0c 50 tbit\.z p2,p3=3Dr4,0 - 370: 00 00 00 00 01 00 \[MII\] nop\.m 0x0 - 376: 20 14 10 06 28 40 tbit\.z\.unc p2,p3=3Dr4,1 - 37c: 40 20 0c 58 tbit\.z\.and p2,p3=3Dr4,2 - 380: 00 00 00 00 01 00 \[MII\] nop\.m 0x0 - 386: 20 30 10 86 28 40 tbit\.z\.or p2,p3=3Dr4,3 - 38c: 80 20 0c 59 tbit\.z\.or\.andcm p2,p3=3Dr4,4 - 390: 00 00 00 00 01 00 \[MII\] nop\.m 0x0 - 396: 30 54 10 84 28 60 tbit\.nz\.or p3,p2=3Dr4,5 - 39c: c8 20 08 58 tbit\.nz\.and p3,p2=3Dr4,6 - 3a0: 00 00 00 00 01 00 \[MII\] nop\.m 0x0 - 3a6: 30 74 10 84 2c 60 tbit\.nz\.or\.andcm p3,p2=3Dr4,7 - 3ac: 00 21 08 50 tbit\.z p3,p2=3Dr4,8 - 3b0: 00 00 00 00 01 00 \[MII\] nop\.m 0x0 - 3b6: 30 94 10 04 28 40 tbit\.z\.unc p3,p2=3Dr4,9 - 3bc: 48 21 0c 58 tbit\.nz\.and p2,p3=3Dr4,10 - 3c0: 00 00 00 00 01 00 \[MII\] nop\.m 0x0 - 3c6: 20 b4 10 86 28 40 tbit\.nz\.or p2,p3=3Dr4,11 - 3cc: 88 21 0c 59 tbit\.nz\.or\.andcm p2,p3=3Dr4,12 - 3d0: 00 00 00 00 01 00 \[MII\] nop\.m 0x0 - 3d6: 30 d0 10 84 28 60 tbit\.z\.or p3,p2=3Dr4,13 - 3dc: c0 21 08 58 tbit\.z\.and p3,p2=3Dr4,14 - 3e0: 00 00 00 00 01 00 \[MII\] nop\.m 0x0 - 3e6: 30 f0 10 84 2c 40 tbit\.z\.or\.andcm p3,p2=3Dr4,15 - 3ec: 10 20 0c 50 tnat\.z p2,p3=3Dr4 - 3f0: 00 00 00 00 01 00 \[MII\] nop\.m 0x0 - 3f6: 20 0c 10 06 28 40 tnat\.z\.unc p2,p3=3Dr4 - 3fc: 10 20 0c 58 tnat\.z\.and p2,p3=3Dr4 - 400: 00 00 00 00 01 00 \[MII\] nop\.m 0x0 - 406: 20 08 10 86 28 40 tnat\.z\.or p2,p3=3Dr4 - 40c: 10 20 0c 59 tnat\.z\.or\.andcm p2,p3=3Dr4 - 410: 00 00 00 00 01 00 \[MII\] nop\.m 0x0 - 416: 30 0c 10 84 28 60 tnat\.nz\.or p3,p2=3Dr4 - 41c: 18 20 08 58 tnat\.nz\.and p3,p2=3Dr4 - 420: 00 00 00 00 01 00 \[MII\] nop\.m 0x0 - 426: 30 0c 10 84 2c 60 tnat\.nz\.or\.andcm p3,p2=3Dr4 - 42c: 10 20 08 50 tnat\.z p3,p2=3Dr4 - 430: 00 00 00 00 01 00 \[MII\] nop\.m 0x0 - 436: 30 0c 10 04 28 40 tnat\.z\.unc p3,p2=3Dr4 - 43c: 18 20 0c 58 tnat\.nz\.and p2,p3=3Dr4 - 440: 00 00 00 00 01 00 \[MII\] nop\.m 0x0 - 446: 20 0c 10 86 28 40 tnat\.nz\.or p2,p3=3Dr4 - 44c: 18 20 0c 59 tnat\.nz\.or\.andcm p2,p3=3Dr4 - 450: 00 00 00 00 01 00 \[MII\] nop\.m 0x0 - 456: 30 08 10 84 28 60 tnat\.z\.or p3,p2=3Dr4 - 45c: 10 20 08 58 tnat\.z\.and p3,p2=3Dr4 - 460: 00 00 00 00 01 00 \[MII\] nop\.m 0x0 - 466: 30 08 10 84 2c 60 tnat\.z\.or\.andcm p3,p2=3Dr4 - 46c: 40 88 08 07 mov b3=3Dr4 - 470: 0d 00 00 00 01 00 \[MFI\] nop\.m 0x0 - 476: 00 00 00 02 00 60 nop\.f 0x0 - 47c: 40 48 08 07 mov\.imp b3=3Dr4,570 <_start\+0x570>;; - \.\.\. - 570: 01 00 00 00 01 00 \[MII\] nop\.m 0x0 - 576: 30 20 00 84 03 60 mov\.sptk b3=3Dr4,670 <_start\+0x670> - 57c: 40 40 08 07 mov\.sptk\.imp b3=3Dr4,670 <_start\+0= x670>;; - \.\.\. - 670: 01 00 00 00 01 00 \[MII\] nop\.m 0x0 - 676: 30 20 08 84 03 60 mov\.dptk b3=3Dr4,770 <_start\+0x770> - 67c: 40 50 08 07 mov\.dptk\.imp b3=3Dr4,770 <_start\+0= x770>;; - \.\.\. - 770: 01 00 00 00 01 00 \[MII\] nop\.m 0x0 - 776: 30 20 14 84 03 60 mov\.ret b3=3Dr4,870 <_start\+0x870> - 77c: 40 68 08 07 mov\.ret\.imp b3=3Dr4,870 <_start\+0x= 870>;; - \.\.\. - 870: 01 00 00 00 01 00 \[MII\] nop\.m 0x0 - 876: 30 20 10 84 03 60 mov\.ret\.sptk b3=3Dr4,970 <_start\+0= x970> - 87c: 40 60 08 07 mov\.ret\.sptk\.imp b3=3Dr4,970 <_sta= rt\+0x970>;; - \.\.\. - 970: 01 00 00 00 01 00 \[MII\] nop\.m 0x0 - 976: 30 20 18 84 03 60 mov\.ret\.dptk b3=3Dr4,a70 <_start\+0= xa70> - 97c: 40 70 08 07 mov\.ret\.dptk\.imp b3=3Dr4,a70 <_sta= rt\+0xa70>;; - \.\.\. - a70: 00 00 00 80 01 00 \[MII\] hint\.m 0 - a76: 00 00 00 03 00 00 hint\.i 0x0 - a7c: 00 00 06 00 hint\.i 0x0 - a80: 00 00 00 00 01 00 \[MII\] nop\.m 0x0 - a86: f0 ff ff 03 84 03 hint\.i 0x1fffff - a8c: 00 00 06 00 \(p07\) hint\.i 0x0 - a90: 00 00 00 00 01 c0 \[MII\] nop\.m 0x0 - a96: 01 00 00 03 80 03 \(p07\) hint\.i 0x0 - a9c: 00 00 06 00 \(p07\) hint\.i 0x0 - aa0: 00 00 00 00 01 c0 \[MII\] nop\.m 0x0 - aa6: f1 ff ff 03 84 03 \(p07\) hint\.i 0x1fffff - aac: 00 00 06 00 \(p07\) hint\.i 0x0 - ab0: 00 00 00 00 01 c0 \[MII\] nop\.m 0x0 - ab6: 01 00 00 03 80 03 \(p07\) hint\.i 0x0 - abc: 00 00 06 00 \(p07\) hint\.i 0x0 - ac0: 00 00 00 00 01 c0 \[MII\] nop\.m 0x0 - ac6: f1 ff ff 03 04 40 \(p07\) hint\.i 0x1fffff - acc: f0 04 0c 50 tf\.z p2,p3=3D39 - ad0: 00 00 00 00 01 00 \[MII\] nop\.m 0x0 - ad6: 20 7c 02 06 28 40 tf\.z\.unc p2,p3=3D39 - adc: f0 04 0c 58 tf\.z\.and p2,p3=3D39 - ae0: 00 00 00 00 01 00 \[MII\] nop\.m 0x0 - ae6: 20 78 02 86 28 40 tf\.z\.or p2,p3=3D39 - aec: f0 04 0c 59 tf\.z\.or\.andcm p2,p3=3D39 - af0: 00 00 00 00 01 00 \[MII\] nop\.m 0x0 - af6: 30 7c 02 84 28 60 tf\.nz\.or p3,p2=3D39 - afc: f8 04 08 58 tf\.nz\.and p3,p2=3D39 - b00: 00 00 00 00 01 00 \[MII\] nop\.m 0x0 - b06: 30 7c 02 84 2c 60 tf\.nz\.or\.andcm p3,p2=3D39 - b0c: f0 04 08 50 tf\.z p3,p2=3D39 - b10: 00 00 00 00 01 00 \[MII\] nop\.m 0x0 - b16: 30 7c 02 04 28 40 tf\.z\.unc p3,p2=3D39 - b1c: f8 04 0c 58 tf\.nz\.and p2,p3=3D39 - b20: 00 00 00 00 01 00 \[MII\] nop\.m 0x0 - b26: 20 7c 02 86 28 40 tf\.nz\.or p2,p3=3D39 - b2c: f8 04 0c 59 tf\.nz\.or\.andcm p2,p3=3D39 - b30: 00 00 00 00 01 00 \[MII\] nop\.m 0x0 - b36: 30 78 02 84 28 60 tf\.z\.or p3,p2=3D39 - b3c: f0 04 08 58 tf\.z\.and p3,p2=3D39 - b40: 00 00 00 00 01 00 \[MII\] nop\.m 0x0 - b46: 30 78 02 84 ac 43 tf\.z\.or\.andcm p3,p2=3D39 - b4c: f0 04 0c 50 \(p07\) tf\.z p2,p3=3D39 - b50: 00 00 00 00 01 c0 \[MII\] nop\.m 0x0 - b56: 21 7c 02 06 a8 43 \(p07\) tf\.z\.unc p2,p3=3D39 - b5c: f0 04 0c 58 \(p07\) tf\.z\.and p2,p3=3D39 - b60: 00 00 00 00 01 c0 \[MII\] nop\.m 0x0 - b66: 21 78 02 86 a8 43 \(p07\) tf\.z\.or p2,p3=3D39 - b6c: f0 04 0c 59 \(p07\) tf\.z\.or\.andcm p2,p3=3D39 - b70: 00 00 00 00 01 c0 \[MII\] nop\.m 0x0 - b76: 31 7c 02 84 a8 63 \(p07\) tf\.nz\.or p3,p2=3D39 - b7c: f8 04 08 58 \(p07\) tf\.nz\.and p3,p2=3D39 - b80: 00 00 00 00 01 c0 \[MII\] nop\.m 0x0 - b86: 31 7c 02 84 ac 63 \(p07\) tf\.nz\.or\.andcm p3,p2=3D39 - b8c: f0 04 08 50 \(p07\) tf\.z p3,p2=3D39 - b90: 00 00 00 00 01 c0 \[MII\] nop\.m 0x0 - b96: 31 7c 02 04 a8 43 \(p07\) tf\.z\.unc p3,p2=3D39 - b9c: f8 04 0c 58 \(p07\) tf\.nz\.and p2,p3=3D39 - ba0: 00 00 00 00 01 c0 \[MII\] nop\.m 0x0 - ba6: 21 7c 02 86 a8 43 \(p07\) tf\.nz\.or p2,p3=3D39 - bac: f8 04 0c 59 \(p07\) tf\.nz\.or\.andcm p2,p3=3D39 - bb0: 00 00 00 00 01 c0 \[MII\] nop\.m 0x0 - bb6: 31 78 02 84 a8 63 \(p07\) tf\.z\.or p3,p2=3D39 - bbc: f0 04 08 58 \(p07\) tf\.z\.and p3,p2=3D39 - bc0: 0d 00 00 00 01 00 \[MFI\] nop\.m 0x0 - bc6: 00 00 00 02 80 63 nop\.f 0x0 - bcc: f0 04 08 59 \(p07\) tf\.z\.or\.andcm p3,p2=3D39;; diff --git a/gas/testsuite/gas/ia64/opc-i.pl b/gas/testsuite/gas/ia64/opc-i= .pl deleted file mode 100644 index 9e444fd2654..00000000000 --- a/gas/testsuite/gas/ia64/opc-i.pl +++ /dev/null @@ -1,189 +0,0 @@ -$AT =3D '@'; -print <: - 0: 18 20 00 0a 00 10 \[MMB\] ld1 r4=3D\[r5\] - 6: 40 30 14 00 24 00 ld1 r4=3D\[r5\],r6 - c: 00 00 00 20 nop\.b 0x0 - 10: 18 20 00 0a 00 16 \[MMB\] ld1 r4=3D\[r5\],-256 - 16: 40 00 14 04 20 00 ld1\.nt1 r4=3D\[r5\] - 1c: 00 00 00 20 nop\.b 0x0 - 20: 18 20 18 0a 02 12 \[MMB\] ld1\.nt1 r4=3D\[r5\],r6 - 26: 40 68 14 04 2c 00 ld1\.nt1 r4=3D\[r5\],-243 - 2c: 00 00 00 20 nop\.b 0x0 - 30: 18 20 00 0a 06 10 \[MMB\] ld1\.nta r4=3D\[r5\] - 36: 40 30 14 0c 24 00 ld1\.nta r4=3D\[r5\],r6 - 3c: 00 00 00 20 nop\.b 0x0 - 40: 18 20 68 0a 06 16 \[MMB\] ld1\.nta r4=3D\[r5\],-230 - 46: 40 00 14 40 20 00 ld1\.s r4=3D\[r5\] - 4c: 00 00 00 20 nop\.b 0x0 - 50: 18 20 18 0a 20 12 \[MMB\] ld1\.s r4=3D\[r5\],r6 - 56: 40 38 15 40 2c 00 ld1\.s r4=3D\[r5\],-217 - 5c: 00 00 00 20 nop\.b 0x0 - 60: 18 20 00 0a 22 10 \[MMB\] ld1\.s\.nt1 r4=3D\[r5\] - 66: 40 30 14 44 24 00 ld1\.s\.nt1 r4=3D\[r5\],r6 - 6c: 00 00 00 20 nop\.b 0x0 - 70: 18 20 d0 0a 22 16 \[MMB\] ld1\.s\.nt1 r4=3D\[r5\],-204 - 76: 40 00 14 4c 20 00 ld1\.s\.nta r4=3D\[r5\] - 7c: 00 00 00 20 nop\.b 0x0 - 80: 18 20 18 0a 26 12 \[MMB\] ld1\.s\.nta r4=3D\[r5\],r6 - 86: 40 08 16 4c 2c 00 ld1\.s\.nta r4=3D\[r5\],-191 - 8c: 00 00 00 20 nop\.b 0x0 - 90: 18 20 00 0a 40 10 \[MMB\] ld1\.a r4=3D\[r5\] - 96: 40 30 14 80 24 00 ld1\.a r4=3D\[r5\],r6 - 9c: 00 00 00 20 nop\.b 0x0 - a0: 18 20 38 0b 40 16 \[MMB\] ld1\.a r4=3D\[r5\],-178 - a6: 40 00 14 84 20 00 ld1\.a\.nt1 r4=3D\[r5\] - ac: 00 00 00 20 nop\.b 0x0 - b0: 18 20 18 0a 42 12 \[MMB\] ld1\.a\.nt1 r4=3D\[r5\],r6 - b6: 40 d8 16 84 2c 00 ld1\.a\.nt1 r4=3D\[r5\],-165 - bc: 00 00 00 20 nop\.b 0x0 - c0: 18 20 00 0a 46 10 \[MMB\] ld1\.a\.nta r4=3D\[r5\] - c6: 40 30 14 8c 24 00 ld1\.a\.nta r4=3D\[r5\],r6 - cc: 00 00 00 20 nop\.b 0x0 - d0: 18 20 a0 0b 46 16 \[MMB\] ld1\.a\.nta r4=3D\[r5\],-152 - d6: 40 00 14 c0 20 00 ld1\.sa r4=3D\[r5\] - dc: 00 00 00 20 nop\.b 0x0 - e0: 18 20 18 0a 60 12 \[MMB\] ld1\.sa r4=3D\[r5\],r6 - e6: 40 a8 17 c0 2c 00 ld1\.sa r4=3D\[r5\],-139 - ec: 00 00 00 20 nop\.b 0x0 - f0: 18 20 00 0a 62 10 \[MMB\] ld1\.sa\.nt1 r4=3D\[r5\] - f6: 40 30 14 c4 24 00 ld1\.sa\.nt1 r4=3D\[r5\],r6 - fc: 00 00 00 20 nop\.b 0x0 - 100: 18 20 08 0a 63 16 \[MMB\] ld1\.sa\.nt1 r4=3D\[r5\],-126 - 106: 40 00 14 cc 20 00 ld1\.sa\.nta r4=3D\[r5\] - 10c: 00 00 00 20 nop\.b 0x0 - 110: 18 20 18 0a 66 12 \[MMB\] ld1\.sa\.nta r4=3D\[r5\],r6 - 116: 40 78 14 ce 2c 00 ld1\.sa\.nta r4=3D\[r5\],-113 - 11c: 00 00 00 20 nop\.b 0x0 - 120: 18 20 00 0a 00 11 \[MMB\] ld1\.c\.clr r4=3D\[r5\] - 126: 40 30 14 00 26 00 ld1\.c\.clr r4=3D\[r5\],r6 - 12c: 00 00 00 20 nop\.b 0x0 - 130: 18 20 70 0a 01 17 \[MMB\] ld1\.c\.clr r4=3D\[r5\],-100 - 136: 40 00 14 04 22 00 ld1\.c\.clr\.nt1 r4=3D\[r5\] - 13c: 00 00 00 20 nop\.b 0x0 - 140: 18 20 18 0a 02 13 \[MMB\] ld1\.c\.clr\.nt1 r4=3D\[r5\],r6 - 146: 40 48 15 06 2e 00 ld1\.c\.clr\.nt1 r4=3D\[r5\],-87 - 14c: 00 00 00 20 nop\.b 0x0 - 150: 18 20 00 0a 06 11 \[MMB\] ld1\.c\.clr\.nta r4=3D\[r5\] - 156: 40 30 14 0c 26 00 ld1\.c\.clr\.nta r4=3D\[r5\],r6 - 15c: 00 00 00 20 nop\.b 0x0 - 160: 18 20 d8 0a 07 17 \[MMB\] ld1\.c\.clr\.nta r4=3D\[r5\],-74 - 166: 40 00 14 40 22 00 ld1\.c\.nc r4=3D\[r5\] - 16c: 00 00 00 20 nop\.b 0x0 - 170: 18 20 18 0a 20 13 \[MMB\] ld1\.c\.nc r4=3D\[r5\],r6 - 176: 40 18 16 42 2e 00 ld1\.c\.nc r4=3D\[r5\],-61 - 17c: 00 00 00 20 nop\.b 0x0 - 180: 18 20 00 0a 22 11 \[MMB\] ld1\.c\.nc\.nt1 r4=3D\[r5\] - 186: 40 30 14 44 26 00 ld1\.c\.nc\.nt1 r4=3D\[r5\],r6 - 18c: 00 00 00 20 nop\.b 0x0 - 190: 18 20 40 0b 23 17 \[MMB\] ld1\.c\.nc\.nt1 r4=3D\[r5\],-48 - 196: 40 00 14 4c 22 00 ld1\.c\.nc\.nta r4=3D\[r5\] - 19c: 00 00 00 20 nop\.b 0x0 - 1a0: 18 20 18 0a 26 13 \[MMB\] ld1\.c\.nc\.nta r4=3D\[r5\],r6 - 1a6: 40 e8 16 4e 2e 00 ld1\.c\.nc\.nta r4=3D\[r5\],-35 - 1ac: 00 00 00 20 nop\.b 0x0 - 1b0: 18 20 00 0a 80 10 \[MMB\] ld1\.bias r4=3D\[r5\] - 1b6: 40 30 14 00 25 00 ld1\.bias r4=3D\[r5\],r6 - 1bc: 00 00 00 20 nop\.b 0x0 - 1c0: 18 20 a8 0b 81 16 \[MMB\] ld1\.bias r4=3D\[r5\],-22 - 1c6: 40 00 14 04 21 00 ld1\.bias\.nt1 r4=3D\[r5\] - 1cc: 00 00 00 20 nop\.b 0x0 - 1d0: 18 20 18 0a 82 12 \[MMB\] ld1\.bias\.nt1 r4=3D\[r5\],r6 - 1d6: 40 b8 17 06 2d 00 ld1\.bias\.nt1 r4=3D\[r5\],-9 - 1dc: 00 00 00 20 nop\.b 0x0 - 1e0: 18 20 00 0a 86 10 \[MMB\] ld1\.bias\.nta r4=3D\[r5\] - 1e6: 40 30 14 0c 25 00 ld1\.bias\.nta r4=3D\[r5\],r6 - 1ec: 00 00 00 20 nop\.b 0x0 - 1f0: 18 20 10 0a 86 14 \[MMB\] ld1\.bias\.nta r4=3D\[r5\],4 - 1f6: 40 00 14 40 21 00 ld1\.acq r4=3D\[r5\] - 1fc: 00 00 00 20 nop\.b 0x0 - 200: 18 20 18 0a a0 12 \[MMB\] ld1\.acq r4=3D\[r5\],r6 - 206: 40 88 14 40 29 00 ld1\.acq r4=3D\[r5\],17 - 20c: 00 00 00 20 nop\.b 0x0 - 210: 18 20 00 0a a2 10 \[MMB\] ld1\.acq\.nt1 r4=3D\[r5\] - 216: 40 30 14 44 25 00 ld1\.acq\.nt1 r4=3D\[r5\],r6 - 21c: 00 00 00 20 nop\.b 0x0 - 220: 18 20 78 0a a2 14 \[MMB\] ld1\.acq\.nt1 r4=3D\[r5\],30 - 226: 40 00 14 4c 21 00 ld1\.acq\.nta r4=3D\[r5\] - 22c: 00 00 00 20 nop\.b 0x0 - 230: 18 20 18 0a a6 12 \[MMB\] ld1\.acq\.nta r4=3D\[r5\],r6 - 236: 40 58 15 4c 29 00 ld1\.acq\.nta r4=3D\[r5\],43 - 23c: 00 00 00 20 nop\.b 0x0 - 240: 18 20 00 0a 40 11 \[MMB\] ld1\.c\.clr\.acq r4=3D\[r5\] - 246: 40 30 14 80 26 00 ld1\.c\.clr\.acq r4=3D\[r5\],r6 - 24c: 00 00 00 20 nop\.b 0x0 - 250: 18 20 e0 0a 40 15 \[MMB\] ld1\.c\.clr\.acq r4=3D\[r5\],56 - 256: 40 00 14 84 22 00 ld1\.c\.clr\.acq\.nt1 r4=3D\[r5\] - 25c: 00 00 00 20 nop\.b 0x0 - 260: 18 20 18 0a 42 13 \[MMB\] ld1\.c\.clr\.acq\.nt1 r4=3D\[r5= \],r6 - 266: 40 28 16 84 2a 00 ld1\.c\.clr\.acq\.nt1 r4=3D\[r5\]= ,69 - 26c: 00 00 00 20 nop\.b 0x0 - 270: 18 20 00 0a 46 11 \[MMB\] ld1\.c\.clr\.acq\.nta r4=3D\[r5= \] - 276: 40 30 14 8c 26 00 ld1\.c\.clr\.acq\.nta r4=3D\[r5\]= ,r6 - 27c: 00 00 00 20 nop\.b 0x0 - 280: 18 20 48 0b 46 15 \[MMB\] ld1\.c\.clr\.acq\.nta r4=3D\[r5= \],82 - 286: 40 00 14 10 20 00 ld2 r4=3D\[r5\] - 28c: 00 00 00 20 nop\.b 0x0 - 290: 18 20 18 0a 08 12 \[MMB\] ld2 r4=3D\[r5\],r6 - 296: 40 f8 16 10 28 00 ld2 r4=3D\[r5\],95 - 29c: 00 00 00 20 nop\.b 0x0 - 2a0: 18 20 00 0a 0a 10 \[MMB\] ld2\.nt1 r4=3D\[r5\] - 2a6: 40 30 14 14 24 00 ld2\.nt1 r4=3D\[r5\],r6 - 2ac: 00 00 00 20 nop\.b 0x0 - 2b0: 18 20 b0 0b 0a 14 \[MMB\] ld2\.nt1 r4=3D\[r5\],108 - 2b6: 40 00 14 1c 20 00 ld2\.nta r4=3D\[r5\] - 2bc: 00 00 00 20 nop\.b 0x0 - 2c0: 18 20 18 0a 0e 12 \[MMB\] ld2\.nta r4=3D\[r5\],r6 - 2c6: 40 c8 17 1c 28 00 ld2\.nta r4=3D\[r5\],121 - 2cc: 00 00 00 20 nop\.b 0x0 - 2d0: 18 20 00 0a 28 10 \[MMB\] ld2\.s r4=3D\[r5\] - 2d6: 40 30 14 50 24 00 ld2\.s r4=3D\[r5\],r6 - 2dc: 00 00 00 20 nop\.b 0x0 - 2e0: 18 20 18 0a 29 14 \[MMB\] ld2\.s r4=3D\[r5\],134 - 2e6: 40 00 14 54 20 00 ld2\.s\.nt1 r4=3D\[r5\] - 2ec: 00 00 00 20 nop\.b 0x0 - 2f0: 18 20 18 0a 2a 12 \[MMB\] ld2\.s\.nt1 r4=3D\[r5\],r6 - 2f6: 40 98 14 56 28 00 ld2\.s\.nt1 r4=3D\[r5\],147 - 2fc: 00 00 00 20 nop\.b 0x0 - 300: 18 20 00 0a 2e 10 \[MMB\] ld2\.s\.nta r4=3D\[r5\] - 306: 40 30 14 5c 24 00 ld2\.s\.nta r4=3D\[r5\],r6 - 30c: 00 00 00 20 nop\.b 0x0 - 310: 18 20 80 0a 2f 14 \[MMB\] ld2\.s\.nta r4=3D\[r5\],160 - 316: 40 00 14 90 20 00 ld2\.a r4=3D\[r5\] - 31c: 00 00 00 20 nop\.b 0x0 - 320: 18 20 18 0a 48 12 \[MMB\] ld2\.a r4=3D\[r5\],r6 - 326: 40 68 15 92 28 00 ld2\.a r4=3D\[r5\],173 - 32c: 00 00 00 20 nop\.b 0x0 - 330: 18 20 00 0a 4a 10 \[MMB\] ld2\.a\.nt1 r4=3D\[r5\] - 336: 40 30 14 94 24 00 ld2\.a\.nt1 r4=3D\[r5\],r6 - 33c: 00 00 00 20 nop\.b 0x0 - 340: 18 20 e8 0a 4b 14 \[MMB\] ld2\.a\.nt1 r4=3D\[r5\],186 - 346: 40 00 14 9c 20 00 ld2\.a\.nta r4=3D\[r5\] - 34c: 00 00 00 20 nop\.b 0x0 - 350: 18 20 18 0a 4e 12 \[MMB\] ld2\.a\.nta r4=3D\[r5\],r6 - 356: 40 38 16 9e 28 00 ld2\.a\.nta r4=3D\[r5\],199 - 35c: 00 00 00 20 nop\.b 0x0 - 360: 18 20 00 0a 68 10 \[MMB\] ld2\.sa r4=3D\[r5\] - 366: 40 30 14 d0 24 00 ld2\.sa r4=3D\[r5\],r6 - 36c: 00 00 00 20 nop\.b 0x0 - 370: 18 20 50 0b 69 14 \[MMB\] ld2\.sa r4=3D\[r5\],212 - 376: 40 00 14 d4 20 00 ld2\.sa\.nt1 r4=3D\[r5\] - 37c: 00 00 00 20 nop\.b 0x0 - 380: 18 20 18 0a 6a 12 \[MMB\] ld2\.sa\.nt1 r4=3D\[r5\],r6 - 386: 40 08 17 d6 28 00 ld2\.sa\.nt1 r4=3D\[r5\],225 - 38c: 00 00 00 20 nop\.b 0x0 - 390: 18 20 00 0a 6e 10 \[MMB\] ld2\.sa\.nta r4=3D\[r5\] - 396: 40 30 14 dc 24 00 ld2\.sa\.nta r4=3D\[r5\],r6 - 39c: 00 00 00 20 nop\.b 0x0 - 3a0: 18 20 b8 0b 6f 14 \[MMB\] ld2\.sa\.nta r4=3D\[r5\],238 - 3a6: 40 00 14 10 22 00 ld2\.c\.clr r4=3D\[r5\] - 3ac: 00 00 00 20 nop\.b 0x0 - 3b0: 18 20 18 0a 08 13 \[MMB\] ld2\.c\.clr r4=3D\[r5\],r6 - 3b6: 40 d8 17 12 2a 00 ld2\.c\.clr r4=3D\[r5\],251 - 3bc: 00 00 00 20 nop\.b 0x0 - 3c0: 18 20 00 0a 0a 11 \[MMB\] ld2\.c\.clr\.nt1 r4=3D\[r5\] - 3c6: 40 30 14 14 26 00 ld2\.c\.clr\.nt1 r4=3D\[r5\],r6 - 3cc: 00 00 00 20 nop\.b 0x0 - 3d0: 18 20 20 0a 0a 17 \[MMB\] ld2\.c\.clr\.nt1 r4=3D\[r5\],-2= 48 - 3d6: 40 00 14 1c 22 00 ld2\.c\.clr\.nta r4=3D\[r5\] - 3dc: 00 00 00 20 nop\.b 0x0 - 3e0: 18 20 18 0a 0e 13 \[MMB\] ld2\.c\.clr\.nta r4=3D\[r5\],r6 - 3e6: 40 a8 14 1c 2e 00 ld2\.c\.clr\.nta r4=3D\[r5\],-235 - 3ec: 00 00 00 20 nop\.b 0x0 - 3f0: 18 20 00 0a 28 11 \[MMB\] ld2\.c\.nc r4=3D\[r5\] - 3f6: 40 30 14 50 26 00 ld2\.c\.nc r4=3D\[r5\],r6 - 3fc: 00 00 00 20 nop\.b 0x0 - 400: 18 20 88 0a 28 17 \[MMB\] ld2\.c\.nc r4=3D\[r5\],-222 - 406: 40 00 14 54 22 00 ld2\.c\.nc\.nt1 r4=3D\[r5\] - 40c: 00 00 00 20 nop\.b 0x0 - 410: 18 20 18 0a 2a 13 \[MMB\] ld2\.c\.nc\.nt1 r4=3D\[r5\],r6 - 416: 40 78 15 54 2e 00 ld2\.c\.nc\.nt1 r4=3D\[r5\],-209 - 41c: 00 00 00 20 nop\.b 0x0 - 420: 18 20 00 0a 2e 11 \[MMB\] ld2\.c\.nc\.nta r4=3D\[r5\] - 426: 40 30 14 5c 26 00 ld2\.c\.nc\.nta r4=3D\[r5\],r6 - 42c: 00 00 00 20 nop\.b 0x0 - 430: 18 20 f0 0a 2e 17 \[MMB\] ld2\.c\.nc\.nta r4=3D\[r5\],-196 - 436: 40 00 14 10 21 00 ld2\.bias r4=3D\[r5\] - 43c: 00 00 00 20 nop\.b 0x0 - 440: 18 20 18 0a 88 12 \[MMB\] ld2\.bias r4=3D\[r5\],r6 - 446: 40 48 16 10 2d 00 ld2\.bias r4=3D\[r5\],-183 - 44c: 00 00 00 20 nop\.b 0x0 - 450: 18 20 00 0a 8a 10 \[MMB\] ld2\.bias\.nt1 r4=3D\[r5\] - 456: 40 30 14 14 25 00 ld2\.bias\.nt1 r4=3D\[r5\],r6 - 45c: 00 00 00 20 nop\.b 0x0 - 460: 18 20 58 0b 8a 16 \[MMB\] ld2\.bias\.nt1 r4=3D\[r5\],-170 - 466: 40 00 14 1c 21 00 ld2\.bias\.nta r4=3D\[r5\] - 46c: 00 00 00 20 nop\.b 0x0 - 470: 18 20 18 0a 8e 12 \[MMB\] ld2\.bias\.nta r4=3D\[r5\],r6 - 476: 40 18 17 1c 2d 00 ld2\.bias\.nta r4=3D\[r5\],-157 - 47c: 00 00 00 20 nop\.b 0x0 - 480: 18 20 00 0a a8 10 \[MMB\] ld2\.acq r4=3D\[r5\] - 486: 40 30 14 50 25 00 ld2\.acq r4=3D\[r5\],r6 - 48c: 00 00 00 20 nop\.b 0x0 - 490: 18 20 c0 0b a8 16 \[MMB\] ld2\.acq r4=3D\[r5\],-144 - 496: 40 00 14 54 21 00 ld2\.acq\.nt1 r4=3D\[r5\] - 49c: 00 00 00 20 nop\.b 0x0 - 4a0: 18 20 18 0a aa 12 \[MMB\] ld2\.acq\.nt1 r4=3D\[r5\],r6 - 4a6: 40 e8 17 54 2d 00 ld2\.acq\.nt1 r4=3D\[r5\],-131 - 4ac: 00 00 00 20 nop\.b 0x0 - 4b0: 18 20 00 0a ae 10 \[MMB\] ld2\.acq\.nta r4=3D\[r5\] - 4b6: 40 30 14 5c 25 00 ld2\.acq\.nta r4=3D\[r5\],r6 - 4bc: 00 00 00 20 nop\.b 0x0 - 4c0: 18 20 28 0a af 16 \[MMB\] ld2\.acq\.nta r4=3D\[r5\],-118 - 4c6: 40 00 14 90 22 00 ld2\.c\.clr\.acq r4=3D\[r5\] - 4cc: 00 00 00 20 nop\.b 0x0 - 4d0: 18 20 18 0a 48 13 \[MMB\] ld2\.c\.clr\.acq r4=3D\[r5\],r6 - 4d6: 40 b8 14 92 2e 00 ld2\.c\.clr\.acq r4=3D\[r5\],-105 - 4dc: 00 00 00 20 nop\.b 0x0 - 4e0: 18 20 00 0a 4a 11 \[MMB\] ld2\.c\.clr\.acq\.nt1 r4=3D\[r5= \] - 4e6: 40 30 14 94 26 00 ld2\.c\.clr\.acq\.nt1 r4=3D\[r5\]= ,r6 - 4ec: 00 00 00 20 nop\.b 0x0 - 4f0: 18 20 90 0a 4b 17 \[MMB\] ld2\.c\.clr\.acq\.nt1 r4=3D\[r5= \],-92 - 4f6: 40 00 14 9c 22 00 ld2\.c\.clr\.acq\.nta r4=3D\[r5\] - 4fc: 00 00 00 20 nop\.b 0x0 - 500: 18 20 18 0a 4e 13 \[MMB\] ld2\.c\.clr\.acq\.nta r4=3D\[r5= \],r6 - 506: 40 88 15 9e 2e 00 ld2\.c\.clr\.acq\.nta r4=3D\[r5\]= ,-79 - 50c: 00 00 00 20 nop\.b 0x0 - 510: 18 20 00 0a 10 10 \[MMB\] ld4 r4=3D\[r5\] - 516: 40 30 14 20 24 00 ld4 r4=3D\[r5\],r6 - 51c: 00 00 00 20 nop\.b 0x0 - 520: 18 20 f8 0a 11 16 \[MMB\] ld4 r4=3D\[r5\],-66 - 526: 40 00 14 24 20 00 ld4\.nt1 r4=3D\[r5\] - 52c: 00 00 00 20 nop\.b 0x0 - 530: 18 20 18 0a 12 12 \[MMB\] ld4\.nt1 r4=3D\[r5\],r6 - 536: 40 58 16 26 2c 00 ld4\.nt1 r4=3D\[r5\],-53 - 53c: 00 00 00 20 nop\.b 0x0 - 540: 18 20 00 0a 16 10 \[MMB\] ld4\.nta r4=3D\[r5\] - 546: 40 30 14 2c 24 00 ld4\.nta r4=3D\[r5\],r6 - 54c: 00 00 00 20 nop\.b 0x0 - 550: 18 20 60 0b 17 16 \[MMB\] ld4\.nta r4=3D\[r5\],-40 - 556: 40 00 14 60 20 00 ld4\.s r4=3D\[r5\] - 55c: 00 00 00 20 nop\.b 0x0 - 560: 18 20 18 0a 30 12 \[MMB\] ld4\.s r4=3D\[r5\],r6 - 566: 40 28 17 62 2c 00 ld4\.s r4=3D\[r5\],-27 - 56c: 00 00 00 20 nop\.b 0x0 - 570: 18 20 00 0a 32 10 \[MMB\] ld4\.s\.nt1 r4=3D\[r5\] - 576: 40 30 14 64 24 00 ld4\.s\.nt1 r4=3D\[r5\],r6 - 57c: 00 00 00 20 nop\.b 0x0 - 580: 18 20 c8 0b 33 16 \[MMB\] ld4\.s\.nt1 r4=3D\[r5\],-14 - 586: 40 00 14 6c 20 00 ld4\.s\.nta r4=3D\[r5\] - 58c: 00 00 00 20 nop\.b 0x0 - 590: 18 20 18 0a 36 12 \[MMB\] ld4\.s\.nta r4=3D\[r5\],r6 - 596: 40 f8 17 6e 2c 00 ld4\.s\.nta r4=3D\[r5\],-1 - 59c: 00 00 00 20 nop\.b 0x0 - 5a0: 18 20 00 0a 50 10 \[MMB\] ld4\.a r4=3D\[r5\] - 5a6: 40 30 14 a0 24 00 ld4\.a r4=3D\[r5\],r6 - 5ac: 00 00 00 20 nop\.b 0x0 - 5b0: 18 20 30 0a 50 14 \[MMB\] ld4\.a r4=3D\[r5\],12 - 5b6: 40 00 14 a4 20 00 ld4\.a\.nt1 r4=3D\[r5\] - 5bc: 00 00 00 20 nop\.b 0x0 - 5c0: 18 20 18 0a 52 12 \[MMB\] ld4\.a\.nt1 r4=3D\[r5\],r6 - 5c6: 40 c8 14 a4 28 00 ld4\.a\.nt1 r4=3D\[r5\],25 - 5cc: 00 00 00 20 nop\.b 0x0 - 5d0: 18 20 00 0a 56 10 \[MMB\] ld4\.a\.nta r4=3D\[r5\] - 5d6: 40 30 14 ac 24 00 ld4\.a\.nta r4=3D\[r5\],r6 - 5dc: 00 00 00 20 nop\.b 0x0 - 5e0: 18 20 98 0a 56 14 \[MMB\] ld4\.a\.nta r4=3D\[r5\],38 - 5e6: 40 00 14 e0 20 00 ld4\.sa r4=3D\[r5\] - 5ec: 00 00 00 20 nop\.b 0x0 - 5f0: 18 20 18 0a 70 12 \[MMB\] ld4\.sa r4=3D\[r5\],r6 - 5f6: 40 98 15 e0 28 00 ld4\.sa r4=3D\[r5\],51 - 5fc: 00 00 00 20 nop\.b 0x0 - 600: 18 20 00 0a 72 10 \[MMB\] ld4\.sa\.nt1 r4=3D\[r5\] - 606: 40 30 14 e4 24 00 ld4\.sa\.nt1 r4=3D\[r5\],r6 - 60c: 00 00 00 20 nop\.b 0x0 - 610: 18 20 00 0b 72 14 \[MMB\] ld4\.sa\.nt1 r4=3D\[r5\],64 - 616: 40 00 14 ec 20 00 ld4\.sa\.nta r4=3D\[r5\] - 61c: 00 00 00 20 nop\.b 0x0 - 620: 18 20 18 0a 76 12 \[MMB\] ld4\.sa\.nta r4=3D\[r5\],r6 - 626: 40 68 16 ec 28 00 ld4\.sa\.nta r4=3D\[r5\],77 - 62c: 00 00 00 20 nop\.b 0x0 - 630: 18 20 00 0a 10 11 \[MMB\] ld4\.c\.clr r4=3D\[r5\] - 636: 40 30 14 20 26 00 ld4\.c\.clr r4=3D\[r5\],r6 - 63c: 00 00 00 20 nop\.b 0x0 - 640: 18 20 68 0b 10 15 \[MMB\] ld4\.c\.clr r4=3D\[r5\],90 - 646: 40 00 14 24 22 00 ld4\.c\.clr\.nt1 r4=3D\[r5\] - 64c: 00 00 00 20 nop\.b 0x0 - 650: 18 20 18 0a 12 13 \[MMB\] ld4\.c\.clr\.nt1 r4=3D\[r5\],r6 - 656: 40 38 17 24 2a 00 ld4\.c\.clr\.nt1 r4=3D\[r5\],103 - 65c: 00 00 00 20 nop\.b 0x0 - 660: 18 20 00 0a 16 11 \[MMB\] ld4\.c\.clr\.nta r4=3D\[r5\] - 666: 40 30 14 2c 26 00 ld4\.c\.clr\.nta r4=3D\[r5\],r6 - 66c: 00 00 00 20 nop\.b 0x0 - 670: 18 20 d0 0b 16 15 \[MMB\] ld4\.c\.clr\.nta r4=3D\[r5\],116 - 676: 40 00 14 60 22 00 ld4\.c\.nc r4=3D\[r5\] - 67c: 00 00 00 20 nop\.b 0x0 - 680: 18 20 18 0a 30 13 \[MMB\] ld4\.c\.nc r4=3D\[r5\],r6 - 686: 40 08 14 62 2a 00 ld4\.c\.nc r4=3D\[r5\],129 - 68c: 00 00 00 20 nop\.b 0x0 - 690: 18 20 00 0a 32 11 \[MMB\] ld4\.c\.nc\.nt1 r4=3D\[r5\] - 696: 40 30 14 64 26 00 ld4\.c\.nc\.nt1 r4=3D\[r5\],r6 - 69c: 00 00 00 20 nop\.b 0x0 - 6a0: 18 20 38 0a 33 15 \[MMB\] ld4\.c\.nc\.nt1 r4=3D\[r5\],142 - 6a6: 40 00 14 6c 22 00 ld4\.c\.nc\.nta r4=3D\[r5\] - 6ac: 00 00 00 20 nop\.b 0x0 - 6b0: 18 20 18 0a 36 13 \[MMB\] ld4\.c\.nc\.nta r4=3D\[r5\],r6 - 6b6: 40 d8 14 6e 2a 00 ld4\.c\.nc\.nta r4=3D\[r5\],155 - 6bc: 00 00 00 20 nop\.b 0x0 - 6c0: 18 20 00 0a 90 10 \[MMB\] ld4\.bias r4=3D\[r5\] - 6c6: 40 30 14 20 25 00 ld4\.bias r4=3D\[r5\],r6 - 6cc: 00 00 00 20 nop\.b 0x0 - 6d0: 18 20 a0 0a 91 14 \[MMB\] ld4\.bias r4=3D\[r5\],168 - 6d6: 40 00 14 24 21 00 ld4\.bias\.nt1 r4=3D\[r5\] - 6dc: 00 00 00 20 nop\.b 0x0 - 6e0: 18 20 18 0a 92 12 \[MMB\] ld4\.bias\.nt1 r4=3D\[r5\],r6 - 6e6: 40 a8 15 26 29 00 ld4\.bias\.nt1 r4=3D\[r5\],181 - 6ec: 00 00 00 20 nop\.b 0x0 - 6f0: 18 20 00 0a 96 10 \[MMB\] ld4\.bias\.nta r4=3D\[r5\] - 6f6: 40 30 14 2c 25 00 ld4\.bias\.nta r4=3D\[r5\],r6 - 6fc: 00 00 00 20 nop\.b 0x0 - 700: 18 20 08 0b 97 14 \[MMB\] ld4\.bias\.nta r4=3D\[r5\],194 - 706: 40 00 14 60 21 00 ld4\.acq r4=3D\[r5\] - 70c: 00 00 00 20 nop\.b 0x0 - 710: 18 20 18 0a b0 12 \[MMB\] ld4\.acq r4=3D\[r5\],r6 - 716: 40 78 16 62 29 00 ld4\.acq r4=3D\[r5\],207 - 71c: 00 00 00 20 nop\.b 0x0 - 720: 18 20 00 0a b2 10 \[MMB\] ld4\.acq\.nt1 r4=3D\[r5\] - 726: 40 30 14 64 25 00 ld4\.acq\.nt1 r4=3D\[r5\],r6 - 72c: 00 00 00 20 nop\.b 0x0 - 730: 18 20 70 0b b3 14 \[MMB\] ld4\.acq\.nt1 r4=3D\[r5\],220 - 736: 40 00 14 6c 21 00 ld4\.acq\.nta r4=3D\[r5\] - 73c: 00 00 00 20 nop\.b 0x0 - 740: 18 20 18 0a b6 12 \[MMB\] ld4\.acq\.nta r4=3D\[r5\],r6 - 746: 40 48 17 6e 29 00 ld4\.acq\.nta r4=3D\[r5\],233 - 74c: 00 00 00 20 nop\.b 0x0 - 750: 18 20 00 0a 50 11 \[MMB\] ld4\.c\.clr\.acq r4=3D\[r5\] - 756: 40 30 14 a0 26 00 ld4\.c\.clr\.acq r4=3D\[r5\],r6 - 75c: 00 00 00 20 nop\.b 0x0 - 760: 18 20 d8 0b 51 15 \[MMB\] ld4\.c\.clr\.acq r4=3D\[r5\],246 - 766: 40 00 14 a4 22 00 ld4\.c\.clr\.acq\.nt1 r4=3D\[r5\] - 76c: 00 00 00 20 nop\.b 0x0 - 770: 18 20 18 0a 52 13 \[MMB\] ld4\.c\.clr\.acq\.nt1 r4=3D\[r5= \],r6 - 776: 40 18 14 a4 2e 00 ld4\.c\.clr\.acq\.nt1 r4=3D\[r5\]= ,-253 - 77c: 00 00 00 20 nop\.b 0x0 - 780: 18 20 00 0a 56 11 \[MMB\] ld4\.c\.clr\.acq\.nta r4=3D\[r5= \] - 786: 40 30 14 ac 26 00 ld4\.c\.clr\.acq\.nta r4=3D\[r5\]= ,r6 - 78c: 00 00 00 20 nop\.b 0x0 - 790: 18 20 40 0a 56 17 \[MMB\] ld4\.c\.clr\.acq\.nta r4=3D\[r5= \],-240 - 796: 40 00 14 30 20 00 ld8 r4=3D\[r5\] - 79c: 00 00 00 20 nop\.b 0x0 - 7a0: 18 20 18 0a 18 12 \[MMB\] ld8 r4=3D\[r5\],r6 - 7a6: 40 e8 14 30 2c 00 ld8 r4=3D\[r5\],-227 - 7ac: 00 00 00 20 nop\.b 0x0 - 7b0: 18 20 00 0a 1a 10 \[MMB\] ld8\.nt1 r4=3D\[r5\] - 7b6: 40 30 14 34 24 00 ld8\.nt1 r4=3D\[r5\],r6 - 7bc: 00 00 00 20 nop\.b 0x0 - 7c0: 18 20 a8 0a 1a 16 \[MMB\] ld8\.nt1 r4=3D\[r5\],-214 - 7c6: 40 00 14 3c 20 00 ld8\.nta r4=3D\[r5\] - 7cc: 00 00 00 20 nop\.b 0x0 - 7d0: 18 20 18 0a 1e 12 \[MMB\] ld8\.nta r4=3D\[r5\],r6 - 7d6: 40 b8 15 3c 2c 00 ld8\.nta r4=3D\[r5\],-201 - 7dc: 00 00 00 20 nop\.b 0x0 - 7e0: 18 20 00 0a 38 10 \[MMB\] ld8\.s r4=3D\[r5\] - 7e6: 40 30 14 70 24 00 ld8\.s r4=3D\[r5\],r6 - 7ec: 00 00 00 20 nop\.b 0x0 - 7f0: 18 20 10 0b 38 16 \[MMB\] ld8\.s r4=3D\[r5\],-188 - 7f6: 40 00 14 74 20 00 ld8\.s\.nt1 r4=3D\[r5\] - 7fc: 00 00 00 20 nop\.b 0x0 - 800: 18 20 18 0a 3a 12 \[MMB\] ld8\.s\.nt1 r4=3D\[r5\],r6 - 806: 40 88 16 74 2c 00 ld8\.s\.nt1 r4=3D\[r5\],-175 - 80c: 00 00 00 20 nop\.b 0x0 - 810: 18 20 00 0a 3e 10 \[MMB\] ld8\.s\.nta r4=3D\[r5\] - 816: 40 30 14 7c 24 00 ld8\.s\.nta r4=3D\[r5\],r6 - 81c: 00 00 00 20 nop\.b 0x0 - 820: 18 20 78 0b 3e 16 \[MMB\] ld8\.s\.nta r4=3D\[r5\],-162 - 826: 40 00 14 b0 20 00 ld8\.a r4=3D\[r5\] - 82c: 00 00 00 20 nop\.b 0x0 - 830: 18 20 18 0a 58 12 \[MMB\] ld8\.a r4=3D\[r5\],r6 - 836: 40 58 17 b0 2c 00 ld8\.a r4=3D\[r5\],-149 - 83c: 00 00 00 20 nop\.b 0x0 - 840: 18 20 00 0a 5a 10 \[MMB\] ld8\.a\.nt1 r4=3D\[r5\] - 846: 40 30 14 b4 24 00 ld8\.a\.nt1 r4=3D\[r5\],r6 - 84c: 00 00 00 20 nop\.b 0x0 - 850: 18 20 e0 0b 5a 16 \[MMB\] ld8\.a\.nt1 r4=3D\[r5\],-136 - 856: 40 00 14 bc 20 00 ld8\.a\.nta r4=3D\[r5\] - 85c: 00 00 00 20 nop\.b 0x0 - 860: 18 20 18 0a 5e 12 \[MMB\] ld8\.a\.nta r4=3D\[r5\],r6 - 866: 40 28 14 be 2c 00 ld8\.a\.nta r4=3D\[r5\],-123 - 86c: 00 00 00 20 nop\.b 0x0 - 870: 18 20 00 0a 78 10 \[MMB\] ld8\.sa r4=3D\[r5\] - 876: 40 30 14 f0 24 00 ld8\.sa r4=3D\[r5\],r6 - 87c: 00 00 00 20 nop\.b 0x0 - 880: 18 20 48 0a 79 16 \[MMB\] ld8\.sa r4=3D\[r5\],-110 - 886: 40 00 14 f4 20 00 ld8\.sa\.nt1 r4=3D\[r5\] - 88c: 00 00 00 20 nop\.b 0x0 - 890: 18 20 18 0a 7a 12 \[MMB\] ld8\.sa\.nt1 r4=3D\[r5\],r6 - 896: 40 f8 14 f6 2c 00 ld8\.sa\.nt1 r4=3D\[r5\],-97 - 89c: 00 00 00 20 nop\.b 0x0 - 8a0: 18 20 00 0a 7e 10 \[MMB\] ld8\.sa\.nta r4=3D\[r5\] - 8a6: 40 30 14 fc 24 00 ld8\.sa\.nta r4=3D\[r5\],r6 - 8ac: 00 00 00 20 nop\.b 0x0 - 8b0: 18 20 b0 0a 7f 16 \[MMB\] ld8\.sa\.nta r4=3D\[r5\],-84 - 8b6: 40 00 14 30 22 00 ld8\.c\.clr r4=3D\[r5\] - 8bc: 00 00 00 20 nop\.b 0x0 - 8c0: 18 20 18 0a 18 13 \[MMB\] ld8\.c\.clr r4=3D\[r5\],r6 - 8c6: 40 c8 15 32 2e 00 ld8\.c\.clr r4=3D\[r5\],-71 - 8cc: 00 00 00 20 nop\.b 0x0 - 8d0: 18 20 00 0a 1a 11 \[MMB\] ld8\.c\.clr\.nt1 r4=3D\[r5\] - 8d6: 40 30 14 34 26 00 ld8\.c\.clr\.nt1 r4=3D\[r5\],r6 - 8dc: 00 00 00 20 nop\.b 0x0 - 8e0: 18 20 18 0b 1b 17 \[MMB\] ld8\.c\.clr\.nt1 r4=3D\[r5\],-58 - 8e6: 40 00 14 3c 22 00 ld8\.c\.clr\.nta r4=3D\[r5\] - 8ec: 00 00 00 20 nop\.b 0x0 - 8f0: 18 20 18 0a 1e 13 \[MMB\] ld8\.c\.clr\.nta r4=3D\[r5\],r6 - 8f6: 40 98 16 3e 2e 00 ld8\.c\.clr\.nta r4=3D\[r5\],-45 - 8fc: 00 00 00 20 nop\.b 0x0 - 900: 18 20 00 0a 38 11 \[MMB\] ld8\.c\.nc r4=3D\[r5\] - 906: 40 30 14 70 26 00 ld8\.c\.nc r4=3D\[r5\],r6 - 90c: 00 00 00 20 nop\.b 0x0 - 910: 18 20 80 0b 39 17 \[MMB\] ld8\.c\.nc r4=3D\[r5\],-32 - 916: 40 00 14 74 22 00 ld8\.c\.nc\.nt1 r4=3D\[r5\] - 91c: 00 00 00 20 nop\.b 0x0 - 920: 18 20 18 0a 3a 13 \[MMB\] ld8\.c\.nc\.nt1 r4=3D\[r5\],r6 - 926: 40 68 17 76 2e 00 ld8\.c\.nc\.nt1 r4=3D\[r5\],-19 - 92c: 00 00 00 20 nop\.b 0x0 - 930: 18 20 00 0a 3e 11 \[MMB\] ld8\.c\.nc\.nta r4=3D\[r5\] - 936: 40 30 14 7c 26 00 ld8\.c\.nc\.nta r4=3D\[r5\],r6 - 93c: 00 00 00 20 nop\.b 0x0 - 940: 18 20 e8 0b 3f 17 \[MMB\] ld8\.c\.nc\.nta r4=3D\[r5\],-6 - 946: 40 00 14 30 21 00 ld8\.bias r4=3D\[r5\] - 94c: 00 00 00 20 nop\.b 0x0 - 950: 18 20 18 0a 98 12 \[MMB\] ld8\.bias r4=3D\[r5\],r6 - 956: 40 38 14 30 29 00 ld8\.bias r4=3D\[r5\],7 - 95c: 00 00 00 20 nop\.b 0x0 - 960: 18 20 00 0a 9a 10 \[MMB\] ld8\.bias\.nt1 r4=3D\[r5\] - 966: 40 30 14 34 25 00 ld8\.bias\.nt1 r4=3D\[r5\],r6 - 96c: 00 00 00 20 nop\.b 0x0 - 970: 18 20 50 0a 9a 14 \[MMB\] ld8\.bias\.nt1 r4=3D\[r5\],20 - 976: 40 00 14 3c 21 00 ld8\.bias\.nta r4=3D\[r5\] - 97c: 00 00 00 20 nop\.b 0x0 - 980: 18 20 18 0a 9e 12 \[MMB\] ld8\.bias\.nta r4=3D\[r5\],r6 - 986: 40 08 15 3c 29 00 ld8\.bias\.nta r4=3D\[r5\],33 - 98c: 00 00 00 20 nop\.b 0x0 - 990: 18 20 00 0a b8 10 \[MMB\] ld8\.acq r4=3D\[r5\] - 996: 40 30 14 70 25 00 ld8\.acq r4=3D\[r5\],r6 - 99c: 00 00 00 20 nop\.b 0x0 - 9a0: 18 20 b8 0a b8 14 \[MMB\] ld8\.acq r4=3D\[r5\],46 - 9a6: 40 00 14 74 21 00 ld8\.acq\.nt1 r4=3D\[r5\] - 9ac: 00 00 00 20 nop\.b 0x0 - 9b0: 18 20 18 0a ba 12 \[MMB\] ld8\.acq\.nt1 r4=3D\[r5\],r6 - 9b6: 40 d8 15 74 29 00 ld8\.acq\.nt1 r4=3D\[r5\],59 - 9bc: 00 00 00 20 nop\.b 0x0 - 9c0: 18 20 00 0a be 10 \[MMB\] ld8\.acq\.nta r4=3D\[r5\] - 9c6: 40 30 14 7c 25 00 ld8\.acq\.nta r4=3D\[r5\],r6 - 9cc: 00 00 00 20 nop\.b 0x0 - 9d0: 18 20 20 0b be 14 \[MMB\] ld8\.acq\.nta r4=3D\[r5\],72 - 9d6: 40 00 14 b0 22 00 ld8\.c\.clr\.acq r4=3D\[r5\] - 9dc: 00 00 00 20 nop\.b 0x0 - 9e0: 18 20 18 0a 58 13 \[MMB\] ld8\.c\.clr\.acq r4=3D\[r5\],r6 - 9e6: 40 a8 16 b0 2a 00 ld8\.c\.clr\.acq r4=3D\[r5\],85 - 9ec: 00 00 00 20 nop\.b 0x0 - 9f0: 18 20 00 0a 5a 11 \[MMB\] ld8\.c\.clr\.acq\.nt1 r4=3D\[r5= \] - 9f6: 40 30 14 b4 26 00 ld8\.c\.clr\.acq\.nt1 r4=3D\[r5\]= ,r6 - 9fc: 00 00 00 20 nop\.b 0x0 - a00: 18 20 88 0b 5a 15 \[MMB\] ld8\.c\.clr\.acq\.nt1 r4=3D\[r5= \],98 - a06: 40 00 14 bc 22 00 ld8\.c\.clr\.acq\.nta r4=3D\[r5\] - a0c: 00 00 00 20 nop\.b 0x0 - a10: 18 20 18 0a 5e 13 \[MMB\] ld8\.c\.clr\.acq\.nta r4=3D\[r5= \],r6 - a16: 40 78 17 bc 2a 00 ld8\.c\.clr\.acq\.nta r4=3D\[r5\]= ,111 - a1c: 00 00 00 20 nop\.b 0x0 - a20: 18 20 00 0a d8 10 \[MMB\] ld8\.fill r4=3D\[r5\] - a26: 40 30 14 b0 25 00 ld8\.fill r4=3D\[r5\],r6 - a2c: 00 00 00 20 nop\.b 0x0 - a30: 18 20 f0 0b d8 14 \[MMB\] ld8\.fill r4=3D\[r5\],124 - a36: 40 00 14 b4 21 00 ld8\.fill\.nt1 r4=3D\[r5\] - a3c: 00 00 00 20 nop\.b 0x0 - a40: 18 20 18 0a da 12 \[MMB\] ld8\.fill\.nt1 r4=3D\[r5\],r6 - a46: 40 48 14 b6 29 00 ld8\.fill\.nt1 r4=3D\[r5\],137 - a4c: 00 00 00 20 nop\.b 0x0 - a50: 18 20 00 0a de 10 \[MMB\] ld8\.fill\.nta r4=3D\[r5\] - a56: 40 30 14 bc 25 00 ld8\.fill\.nta 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20 nop\.b 0x0 - ed0: 18 20 00 0a 3e 19 \[MMB\] ldfd\.c\.nc\.nta f4=3D\[r5\] - ed6: 40 30 14 7c 36 00 ldfd\.c\.nc\.nta f4=3D\[r5\],r6 - edc: 00 00 00 20 nop\.b 0x0 - ee0: 18 20 50 0b 3e 1f \[MMB\] ldfd\.c\.nc\.nta f4=3D\[r5\],-1= 72 - ee6: 40 00 14 10 30 00 ldf8 f4=3D\[r5\] - eec: 00 00 00 20 nop\.b 0x0 - ef0: 18 20 18 0a 08 1a \[MMB\] ldf8 f4=3D\[r5\],r6 - ef6: 40 08 17 10 3c 00 ldf8 f4=3D\[r5\],-159 - efc: 00 00 00 20 nop\.b 0x0 - f00: 18 20 00 0a 0a 18 \[MMB\] ldf8\.nt1 f4=3D\[r5\] - f06: 40 30 14 14 34 00 ldf8\.nt1 f4=3D\[r5\],r6 - f0c: 00 00 00 20 nop\.b 0x0 - f10: 18 20 b8 0b 0a 1e \[MMB\] ldf8\.nt1 f4=3D\[r5\],-146 - f16: 40 00 14 1c 30 00 ldf8\.nta f4=3D\[r5\] - f1c: 00 00 00 20 nop\.b 0x0 - f20: 18 20 18 0a 0e 1a \[MMB\] ldf8\.nta f4=3D\[r5\],r6 - f26: 40 d8 17 1c 3c 00 ldf8\.nta f4=3D\[r5\],-133 - f2c: 00 00 00 20 nop\.b 0x0 - f30: 18 20 00 0a 28 18 \[MMB\] ldf8\.s f4=3D\[r5\] - f36: 40 30 14 50 34 00 ldf8\.s f4=3D\[r5\],r6 - f3c: 00 00 00 20 nop\.b 0x0 - f40: 18 20 20 0a 29 1e \[MMB\] ldf8\.s f4=3D\[r5\],-120 - f46: 40 00 14 54 30 00 ldf8\.s\.nt1 f4=3D\[r5\] - f4c: 00 00 00 20 nop\.b 0x0 - f50: 18 20 18 0a 2a 1a \[MMB\] ldf8\.s\.nt1 f4=3D\[r5\],r6 - f56: 40 a8 14 56 3c 00 ldf8\.s\.nt1 f4=3D\[r5\],-107 - f5c: 00 00 00 20 nop\.b 0x0 - f60: 18 20 00 0a 2e 18 \[MMB\] ldf8\.s\.nta f4=3D\[r5\] - f66: 40 30 14 5c 34 00 ldf8\.s\.nta f4=3D\[r5\],r6 - f6c: 00 00 00 20 nop\.b 0x0 - f70: 18 20 88 0a 2f 1e \[MMB\] ldf8\.s\.nta f4=3D\[r5\],-94 - f76: 40 00 14 90 30 00 ldf8\.a f4=3D\[r5\] - f7c: 00 00 00 20 nop\.b 0x0 - f80: 18 20 18 0a 48 1a \[MMB\] ldf8\.a f4=3D\[r5\],r6 - f86: 40 78 15 92 3c 00 ldf8\.a f4=3D\[r5\],-81 - f8c: 00 00 00 20 nop\.b 0x0 - f90: 18 20 00 0a 4a 18 \[MMB\] ldf8\.a\.nt1 f4=3D\[r5\] - f96: 40 30 14 94 34 00 ldf8\.a\.nt1 f4=3D\[r5\],r6 - f9c: 00 00 00 20 nop\.b 0x0 - fa0: 18 20 f0 0a 4b 1e \[MMB\] ldf8\.a\.nt1 f4=3D\[r5\],-68 - fa6: 40 00 14 9c 30 00 ldf8\.a\.nta f4=3D\[r5\] - fac: 00 00 00 20 nop\.b 0x0 - fb0: 18 20 18 0a 4e 1a \[MMB\] ldf8\.a\.nta f4=3D\[r5\],r6 - fb6: 40 48 16 9e 3c 00 ldf8\.a\.nta f4=3D\[r5\],-55 - fbc: 00 00 00 20 nop\.b 0x0 - fc0: 18 20 00 0a 68 18 \[MMB\] ldf8\.sa f4=3D\[r5\] - fc6: 40 30 14 d0 34 00 ldf8\.sa f4=3D\[r5\],r6 - fcc: 00 00 00 20 nop\.b 0x0 - fd0: 18 20 58 0b 69 1e \[MMB\] ldf8\.sa f4=3D\[r5\],-42 - fd6: 40 00 14 d4 30 00 ldf8\.sa\.nt1 f4=3D\[r5\] - fdc: 00 00 00 20 nop\.b 0x0 - fe0: 18 20 18 0a 6a 1a \[MMB\] ldf8\.sa\.nt1 f4=3D\[r5\],r6 - fe6: 40 18 17 d6 3c 00 ldf8\.sa\.nt1 f4=3D\[r5\],-29 - fec: 00 00 00 20 nop\.b 0x0 - ff0: 18 20 00 0a 6e 18 \[MMB\] ldf8\.sa\.nta f4=3D\[r5\] - ff6: 40 30 14 dc 34 00 ldf8\.sa\.nta f4=3D\[r5\],r6 - ffc: 00 00 00 20 nop\.b 0x0 - 1000: 18 20 c0 0b 6f 1e \[MMB\] ldf8\.sa\.nta f4=3D\[r5\],-16 - 1006: 40 00 14 10 32 00 ldf8\.c\.clr f4=3D\[r5\] - 100c: 00 00 00 20 nop\.b 0x0 - 1010: 18 20 18 0a 08 1b \[MMB\] ldf8\.c\.clr f4=3D\[r5\],r6 - 1016: 40 e8 17 12 3e 00 ldf8\.c\.clr f4=3D\[r5\],-3 - 101c: 00 00 00 20 nop\.b 0x0 - 1020: 18 20 00 0a 0a 19 \[MMB\] ldf8\.c\.clr\.nt1 f4=3D\[r5\] - 1026: 40 30 14 14 36 00 ldf8\.c\.clr\.nt1 f4=3D\[r5\],r6 - 102c: 00 00 00 20 nop\.b 0x0 - 1030: 18 20 28 0a 0a 1d \[MMB\] ldf8\.c\.clr\.nt1 f4=3D\[r5\],10 - 1036: 40 00 14 1c 32 00 ldf8\.c\.clr\.nta f4=3D\[r5\] - 103c: 00 00 00 20 nop\.b 0x0 - 1040: 18 20 18 0a 0e 1b \[MMB\] ldf8\.c\.clr\.nta f4=3D\[r5\],r6 - 1046: 40 b8 14 1c 3a 00 ldf8\.c\.clr\.nta f4=3D\[r5\],23 - 104c: 00 00 00 20 nop\.b 0x0 - 1050: 18 20 00 0a 28 19 \[MMB\] ldf8\.c\.nc f4=3D\[r5\] - 1056: 40 30 14 50 36 00 ldf8\.c\.nc f4=3D\[r5\],r6 - 105c: 00 00 00 20 nop\.b 0x0 - 1060: 18 20 90 0a 28 1d \[MMB\] ldf8\.c\.nc f4=3D\[r5\],36 - 1066: 40 00 14 54 32 00 ldf8\.c\.nc\.nt1 f4=3D\[r5\] - 106c: 00 00 00 20 nop\.b 0x0 - 1070: 18 20 18 0a 2a 1b \[MMB\] ldf8\.c\.nc\.nt1 f4=3D\[r5\],r6 - 1076: 40 88 15 54 3a 00 ldf8\.c\.nc\.nt1 f4=3D\[r5\],49 - 107c: 00 00 00 20 nop\.b 0x0 - 1080: 18 20 00 0a 2e 19 \[MMB\] ldf8\.c\.nc\.nta f4=3D\[r5\] - 1086: 40 30 14 5c 36 00 ldf8\.c\.nc\.nta f4=3D\[r5\],r6 - 108c: 00 00 00 20 nop\.b 0x0 - 1090: 18 20 f8 0a 2e 1d \[MMB\] ldf8\.c\.nc\.nta f4=3D\[r5\],62 - 1096: 40 00 14 00 30 00 ldfe f4=3D\[r5\] - 109c: 00 00 00 20 nop\.b 0x0 - 10a0: 18 20 18 0a 00 1a \[MMB\] ldfe f4=3D\[r5\],r6 - 10a6: 40 58 16 00 38 00 ldfe f4=3D\[r5\],75 - 10ac: 00 00 00 20 nop\.b 0x0 - 10b0: 18 20 00 0a 02 18 \[MMB\] ldfe\.nt1 f4=3D\[r5\] - 10b6: 40 30 14 04 34 00 ldfe\.nt1 f4=3D\[r5\],r6 - 10bc: 00 00 00 20 nop\.b 0x0 - 10c0: 18 20 60 0b 02 1c \[MMB\] ldfe\.nt1 f4=3D\[r5\],88 - 10c6: 40 00 14 0c 30 00 ldfe\.nta f4=3D\[r5\] - 10cc: 00 00 00 20 nop\.b 0x0 - 10d0: 18 20 18 0a 06 1a \[MMB\] ldfe\.nta f4=3D\[r5\],r6 - 10d6: 40 28 17 0c 38 00 ldfe\.nta f4=3D\[r5\],101 - 10dc: 00 00 00 20 nop\.b 0x0 - 10e0: 18 20 00 0a 20 18 \[MMB\] ldfe\.s f4=3D\[r5\] - 10e6: 40 30 14 40 34 00 ldfe\.s f4=3D\[r5\],r6 - 10ec: 00 00 00 20 nop\.b 0x0 - 10f0: 18 20 c8 0b 20 1c \[MMB\] ldfe\.s f4=3D\[r5\],114 - 10f6: 40 00 14 44 30 00 ldfe\.s\.nt1 f4=3D\[r5\] - 10fc: 00 00 00 20 nop\.b 0x0 - 1100: 18 20 18 0a 22 1a \[MMB\] ldfe\.s\.nt1 f4=3D\[r5\],r6 - 1106: 40 f8 17 44 38 00 ldfe\.s\.nt1 f4=3D\[r5\],127 - 110c: 00 00 00 20 nop\.b 0x0 - 1110: 18 20 00 0a 26 18 \[MMB\] ldfe\.s\.nta f4=3D\[r5\] - 1116: 40 30 14 4c 34 00 ldfe\.s\.nta f4=3D\[r5\],r6 - 111c: 00 00 00 20 nop\.b 0x0 - 1120: 18 20 30 0a 27 1c \[MMB\] ldfe\.s\.nta f4=3D\[r5\],140 - 1126: 40 00 14 80 30 00 ldfe\.a f4=3D\[r5\] - 112c: 00 00 00 20 nop\.b 0x0 - 1130: 18 20 18 0a 40 1a \[MMB\] ldfe\.a f4=3D\[r5\],r6 - 1136: 40 c8 14 82 38 00 ldfe\.a f4=3D\[r5\],153 - 113c: 00 00 00 20 nop\.b 0x0 - 1140: 18 20 00 0a 42 18 \[MMB\] ldfe\.a\.nt1 f4=3D\[r5\] - 1146: 40 30 14 84 34 00 ldfe\.a\.nt1 f4=3D\[r5\],r6 - 114c: 00 00 00 20 nop\.b 0x0 - 1150: 18 20 98 0a 43 1c \[MMB\] ldfe\.a\.nt1 f4=3D\[r5\],166 - 1156: 40 00 14 8c 30 00 ldfe\.a\.nta f4=3D\[r5\] - 115c: 00 00 00 20 nop\.b 0x0 - 1160: 18 20 18 0a 46 1a \[MMB\] ldfe\.a\.nta f4=3D\[r5\],r6 - 1166: 40 98 15 8e 38 00 ldfe\.a\.nta f4=3D\[r5\],179 - 116c: 00 00 00 20 nop\.b 0x0 - 1170: 18 20 00 0a 60 18 \[MMB\] ldfe\.sa f4=3D\[r5\] - 1176: 40 30 14 c0 34 00 ldfe\.sa f4=3D\[r5\],r6 - 117c: 00 00 00 20 nop\.b 0x0 - 1180: 18 20 00 0b 61 1c \[MMB\] ldfe\.sa f4=3D\[r5\],192 - 1186: 40 00 14 c4 30 00 ldfe\.sa\.nt1 f4=3D\[r5\] - 118c: 00 00 00 20 nop\.b 0x0 - 1190: 18 20 18 0a 62 1a \[MMB\] ldfe\.sa\.nt1 f4=3D\[r5\],r6 - 1196: 40 68 16 c6 38 00 ldfe\.sa\.nt1 f4=3D\[r5\],205 - 119c: 00 00 00 20 nop\.b 0x0 - 11a0: 18 20 00 0a 66 18 \[MMB\] ldfe\.sa\.nta f4=3D\[r5\] - 11a6: 40 30 14 cc 34 00 ldfe\.sa\.nta f4=3D\[r5\],r6 - 11ac: 00 00 00 20 nop\.b 0x0 - 11b0: 18 20 68 0b 67 1c \[MMB\] ldfe\.sa\.nta f4=3D\[r5\],218 - 11b6: 40 00 14 00 32 00 ldfe\.c\.clr f4=3D\[r5\] - 11bc: 00 00 00 20 nop\.b 0x0 - 11c0: 18 20 18 0a 00 1b \[MMB\] ldfe\.c\.clr f4=3D\[r5\],r6 - 11c6: 40 38 17 02 3a 00 ldfe\.c\.clr f4=3D\[r5\],231 - 11cc: 00 00 00 20 nop\.b 0x0 - 11d0: 18 20 00 0a 02 19 \[MMB\] ldfe\.c\.clr\.nt1 f4=3D\[r5\] - 11d6: 40 30 14 04 36 00 ldfe\.c\.clr\.nt1 f4=3D\[r5\],r6 - 11dc: 00 00 00 20 nop\.b 0x0 - 11e0: 18 20 d0 0b 03 1d \[MMB\] ldfe\.c\.clr\.nt1 f4=3D\[r5\],2= 44 - 11e6: 40 00 14 0c 32 00 ldfe\.c\.clr\.nta f4=3D\[r5\] - 11ec: 00 00 00 20 nop\.b 0x0 - 11f0: 18 20 18 0a 06 1b \[MMB\] ldfe\.c\.clr\.nta f4=3D\[r5\],r6 - 11f6: 40 08 14 0c 3e 00 ldfe\.c\.clr\.nta f4=3D\[r5\],-255 - 11fc: 00 00 00 20 nop\.b 0x0 - 1200: 18 20 00 0a 20 19 \[MMB\] ldfe\.c\.nc f4=3D\[r5\] - 1206: 40 30 14 40 36 00 ldfe\.c\.nc f4=3D\[r5\],r6 - 120c: 00 00 00 20 nop\.b 0x0 - 1210: 18 20 38 0a 20 1f \[MMB\] ldfe\.c\.nc f4=3D\[r5\],-242 - 1216: 40 00 14 44 32 00 ldfe\.c\.nc\.nt1 f4=3D\[r5\] - 121c: 00 00 00 20 nop\.b 0x0 - 1220: 18 20 18 0a 22 1b \[MMB\] ldfe\.c\.nc\.nt1 f4=3D\[r5\],r6 - 1226: 40 d8 14 44 3e 00 ldfe\.c\.nc\.nt1 f4=3D\[r5\],-229 - 122c: 00 00 00 20 nop\.b 0x0 - 1230: 18 20 00 0a 26 19 \[MMB\] ldfe\.c\.nc\.nta f4=3D\[r5\] - 1236: 40 30 14 4c 36 00 ldfe\.c\.nc\.nta f4=3D\[r5\],r6 - 123c: 00 00 00 20 nop\.b 0x0 - 1240: 18 20 a0 0a 26 1f \[MMB\] ldfe\.c\.nc\.nta f4=3D\[r5\],-2= 16 - 1246: 40 00 14 b0 31 00 ldf\.fill f4=3D\[r5\] - 124c: 00 00 00 20 nop\.b 0x0 - 1250: 18 20 18 0a d8 1a \[MMB\] ldf\.fill f4=3D\[r5\],r6 - 1256: 40 a8 15 b0 3d 00 ldf\.fill f4=3D\[r5\],-203 - 125c: 00 00 00 20 nop\.b 0x0 - 1260: 18 20 00 0a da 18 \[MMB\] ldf\.fill\.nt1 f4=3D\[r5\] - 1266: 40 30 14 b4 35 00 ldf\.fill\.nt1 f4=3D\[r5\],r6 - 126c: 00 00 00 20 nop\.b 0x0 - 1270: 18 20 08 0b da 1e \[MMB\] ldf\.fill\.nt1 f4=3D\[r5\],-190 - 1276: 40 00 14 bc 31 00 ldf\.fill\.nta f4=3D\[r5\] - 127c: 00 00 00 20 nop\.b 0x0 - 1280: 18 20 18 0a de 1a \[MMB\] ldf\.fill\.nta f4=3D\[r5\],r6 - 1286: 40 78 16 bc 3d 00 ldf\.fill\.nta f4=3D\[r5\],-177 - 128c: 00 00 00 20 nop\.b 0x0 - 1290: 18 00 14 08 90 19 \[MMB\] stfs \[r4\]=3Df5 - 1296: c0 2d 10 20 3f 00 stfs \[r4\]=3Df5,-164 - 129c: 00 00 00 20 nop\.b 0x0 - 12a0: 18 00 14 08 96 19 \[MMB\] stfs\.nta \[r4\]=3Df5 - 12a6: 90 2e 10 2c 3f 00 stfs\.nta \[r4\]=3Df5,-151 - 12ac: 00 00 00 20 nop\.b 0x0 - 12b0: 18 00 14 08 98 19 \[MMB\] stfd \[r4\]=3Df5 - 12b6: 60 2f 10 30 3f 00 stfd \[r4\]=3Df5,-138 - 12bc: 00 00 00 20 nop\.b 0x0 - 12c0: 18 00 14 08 9e 19 \[MMB\] stfd\.nta \[r4\]=3Df5 - 12c6: 30 28 10 3e 3f 00 stfd\.nta \[r4\]=3Df5,-125 - 12cc: 00 00 00 20 nop\.b 0x0 - 12d0: 18 00 14 08 88 19 \[MMB\] stf8 \[r4\]=3Df5 - 12d6: 00 29 10 12 3f 00 stf8 \[r4\]=3Df5,-112 - 12dc: 00 00 00 20 nop\.b 0x0 - 12e0: 18 00 14 08 8e 19 \[MMB\] stf8\.nta \[r4\]=3Df5 - 12e6: d0 29 10 1e 3f 00 stf8\.nta \[r4\]=3Df5,-99 - 12ec: 00 00 00 20 nop\.b 0x0 - 12f0: 18 00 14 08 80 19 \[MMB\] stfe \[r4\]=3Df5 - 12f6: a0 2a 10 02 3f 00 stfe \[r4\]=3Df5,-86 - 12fc: 00 00 00 20 nop\.b 0x0 - 1300: 18 00 14 08 86 19 \[MMB\] stfe\.nta \[r4\]=3Df5 - 1306: 70 2b 10 0e 3f 00 stfe\.nta \[r4\]=3Df5,-73 - 130c: 00 00 00 20 nop\.b 0x0 - 1310: 18 00 14 08 d8 19 \[MMB\] stf\.spill \[r4\]=3Df5 - 1316: 40 2c 10 b2 3f 00 stf\.spill \[r4\]=3Df5,-60 - 131c: 00 00 00 20 nop\.b 0x0 - 1320: 18 00 14 08 de 19 \[MMB\] stf\.spill\.nta \[r4\]=3Df5 - 1326: 10 2d 10 be 3f 00 stf\.spill\.nta \[r4\]=3Df5,-47 - 132c: 00 00 00 20 nop\.b 0x0 - 1330: 18 20 14 0a 11 18 \[MMB\] ldfps f4,f5=3D\[r5\] - 1336: 40 28 14 22 34 00 ldfps f4,f5=3D\[r5\],8 - 133c: 00 00 00 20 nop\.b 0x0 - 1340: 18 20 14 0a 13 18 \[MMB\] ldfps\.nt1 f4,f5=3D\[r5\] - 1346: 40 28 14 26 34 00 ldfps\.nt1 f4,f5=3D\[r5\],8 - 134c: 00 00 00 20 nop\.b 0x0 - 1350: 18 20 14 0a 17 18 \[MMB\] ldfps\.nta f4,f5=3D\[r5\] - 1356: 40 28 14 2e 34 00 ldfps\.nta f4,f5=3D\[r5\],8 - 135c: 00 00 00 20 nop\.b 0x0 - 1360: 18 20 14 0a 31 18 \[MMB\] ldfps\.s f4,f5=3D\[r5\] - 1366: 40 28 14 62 34 00 ldfps\.s f4,f5=3D\[r5\],8 - 136c: 00 00 00 20 nop\.b 0x0 - 1370: 18 20 14 0a 33 18 \[MMB\] ldfps\.s\.nt1 f4,f5=3D\[r5\] - 1376: 40 28 14 66 34 00 ldfps\.s\.nt1 f4,f5=3D\[r5\],8 - 137c: 00 00 00 20 nop\.b 0x0 - 1380: 18 20 14 0a 37 18 \[MMB\] ldfps\.s\.nta f4,f5=3D\[r5\] - 1386: 40 28 14 6e 34 00 ldfps\.s\.nta f4,f5=3D\[r5\],8 - 138c: 00 00 00 20 nop\.b 0x0 - 1390: 18 20 14 0a 51 18 \[MMB\] ldfps\.a f4,f5=3D\[r5\] - 1396: 40 28 14 a2 34 00 ldfps\.a f4,f5=3D\[r5\],8 - 139c: 00 00 00 20 nop\.b 0x0 - 13a0: 18 20 14 0a 53 18 \[MMB\] ldfps\.a\.nt1 f4,f5=3D\[r5\] - 13a6: 40 28 14 a6 34 00 ldfps\.a\.nt1 f4,f5=3D\[r5\],8 - 13ac: 00 00 00 20 nop\.b 0x0 - 13b0: 18 20 14 0a 57 18 \[MMB\] ldfps\.a\.nta f4,f5=3D\[r5\] - 13b6: 40 28 14 ae 34 00 ldfps\.a\.nta f4,f5=3D\[r5\],8 - 13bc: 00 00 00 20 nop\.b 0x0 - 13c0: 18 20 14 0a 71 18 \[MMB\] ldfps\.sa f4,f5=3D\[r5\] - 13c6: 40 28 14 e2 34 00 ldfps\.sa f4,f5=3D\[r5\],8 - 13cc: 00 00 00 20 nop\.b 0x0 - 13d0: 18 20 14 0a 73 18 \[MMB\] ldfps\.sa\.nt1 f4,f5=3D\[r5\] - 13d6: 40 28 14 e6 34 00 ldfps\.sa\.nt1 f4,f5=3D\[r5\],8 - 13dc: 00 00 00 20 nop\.b 0x0 - 13e0: 18 20 14 0a 77 18 \[MMB\] ldfps\.sa\.nta f4,f5=3D\[r5\] - 13e6: 40 28 14 ee 34 00 ldfps\.sa\.nta f4,f5=3D\[r5\],8 - 13ec: 00 00 00 20 nop\.b 0x0 - 13f0: 18 20 14 0a 11 19 \[MMB\] ldfps\.c\.clr f4,f5=3D\[r5\] - 13f6: 40 28 14 22 36 00 ldfps\.c\.clr f4,f5=3D\[r5\],8 - 13fc: 00 00 00 20 nop\.b 0x0 - 1400: 18 20 14 0a 13 19 \[MMB\] ldfps\.c\.clr\.nt1 f4,f5=3D\[r5= \] - 1406: 40 28 14 26 36 00 ldfps\.c\.clr\.nt1 f4,f5=3D\[r5\]= ,8 - 140c: 00 00 00 20 nop\.b 0x0 - 1410: 18 20 14 0a 17 19 \[MMB\] ldfps\.c\.clr\.nta f4,f5=3D\[r5= \] - 1416: 40 28 14 2e 36 00 ldfps\.c\.clr\.nta f4,f5=3D\[r5\]= ,8 - 141c: 00 00 00 20 nop\.b 0x0 - 1420: 18 20 14 0a 31 19 \[MMB\] ldfps\.c\.nc f4,f5=3D\[r5\] - 1426: 40 28 14 62 36 00 ldfps\.c\.nc f4,f5=3D\[r5\],8 - 142c: 00 00 00 20 nop\.b 0x0 - 1430: 18 20 14 0a 33 19 \[MMB\] ldfps\.c\.nc\.nt1 f4,f5=3D\[r5\] - 1436: 40 28 14 66 36 00 ldfps\.c\.nc\.nt1 f4,f5=3D\[r5\],8 - 143c: 00 00 00 20 nop\.b 0x0 - 1440: 18 20 14 0a 37 19 \[MMB\] ldfps\.c\.nc\.nta f4,f5=3D\[r5\] - 1446: 40 28 14 6e 36 00 ldfps\.c\.nc\.nta f4,f5=3D\[r5\],8 - 144c: 00 00 00 20 nop\.b 0x0 - 1450: 18 20 14 0a 19 18 \[MMB\] ldfpd f4,f5=3D\[r5\] - 1456: 40 28 14 32 34 00 ldfpd f4,f5=3D\[r5\],16 - 145c: 00 00 00 20 nop\.b 0x0 - 1460: 18 20 14 0a 1b 18 \[MMB\] ldfpd\.nt1 f4,f5=3D\[r5\] - 1466: 40 28 14 36 34 00 ldfpd\.nt1 f4,f5=3D\[r5\],16 - 146c: 00 00 00 20 nop\.b 0x0 - 1470: 18 20 14 0a 1f 18 \[MMB\] ldfpd\.nta f4,f5=3D\[r5\] - 1476: 40 28 14 3e 34 00 ldfpd\.nta f4,f5=3D\[r5\],16 - 147c: 00 00 00 20 nop\.b 0x0 - 1480: 18 20 14 0a 39 18 \[MMB\] ldfpd\.s f4,f5=3D\[r5\] - 1486: 40 28 14 72 34 00 ldfpd\.s f4,f5=3D\[r5\],16 - 148c: 00 00 00 20 nop\.b 0x0 - 1490: 18 20 14 0a 3b 18 \[MMB\] ldfpd\.s\.nt1 f4,f5=3D\[r5\] - 1496: 40 28 14 76 34 00 ldfpd\.s\.nt1 f4,f5=3D\[r5\],16 - 149c: 00 00 00 20 nop\.b 0x0 - 14a0: 18 20 14 0a 3f 18 \[MMB\] ldfpd\.s\.nta f4,f5=3D\[r5\] - 14a6: 40 28 14 7e 34 00 ldfpd\.s\.nta f4,f5=3D\[r5\],16 - 14ac: 00 00 00 20 nop\.b 0x0 - 14b0: 18 20 14 0a 59 18 \[MMB\] ldfpd\.a f4,f5=3D\[r5\] - 14b6: 40 28 14 b2 34 00 ldfpd\.a f4,f5=3D\[r5\],16 - 14bc: 00 00 00 20 nop\.b 0x0 - 14c0: 18 20 14 0a 5b 18 \[MMB\] ldfpd\.a\.nt1 f4,f5=3D\[r5\] - 14c6: 40 28 14 b6 34 00 ldfpd\.a\.nt1 f4,f5=3D\[r5\],16 - 14cc: 00 00 00 20 nop\.b 0x0 - 14d0: 18 20 14 0a 5f 18 \[MMB\] ldfpd\.a\.nta f4,f5=3D\[r5\] - 14d6: 40 28 14 be 34 00 ldfpd\.a\.nta f4,f5=3D\[r5\],16 - 14dc: 00 00 00 20 nop\.b 0x0 - 14e0: 18 20 14 0a 79 18 \[MMB\] ldfpd\.sa f4,f5=3D\[r5\] - 14e6: 40 28 14 f2 34 00 ldfpd\.sa f4,f5=3D\[r5\],16 - 14ec: 00 00 00 20 nop\.b 0x0 - 14f0: 18 20 14 0a 7b 18 \[MMB\] ldfpd\.sa\.nt1 f4,f5=3D\[r5\] - 14f6: 40 28 14 f6 34 00 ldfpd\.sa\.nt1 f4,f5=3D\[r5\],16 - 14fc: 00 00 00 20 nop\.b 0x0 - 1500: 18 20 14 0a 7f 18 \[MMB\] ldfpd\.sa\.nta f4,f5=3D\[r5\] - 1506: 40 28 14 fe 34 00 ldfpd\.sa\.nta f4,f5=3D\[r5\],16 - 150c: 00 00 00 20 nop\.b 0x0 - 1510: 18 20 14 0a 19 19 \[MMB\] ldfpd\.c\.clr f4,f5=3D\[r5\] - 1516: 40 28 14 32 36 00 ldfpd\.c\.clr f4,f5=3D\[r5\],16 - 151c: 00 00 00 20 nop\.b 0x0 - 1520: 18 20 14 0a 1b 19 \[MMB\] ldfpd\.c\.clr\.nt1 f4,f5=3D\[r5= \] - 1526: 40 28 14 36 36 00 ldfpd\.c\.clr\.nt1 f4,f5=3D\[r5\]= ,16 - 152c: 00 00 00 20 nop\.b 0x0 - 1530: 18 20 14 0a 1f 19 \[MMB\] ldfpd\.c\.clr\.nta f4,f5=3D\[r5= \] - 1536: 40 28 14 3e 36 00 ldfpd\.c\.clr\.nta f4,f5=3D\[r5\]= ,16 - 153c: 00 00 00 20 nop\.b 0x0 - 1540: 18 20 14 0a 39 19 \[MMB\] ldfpd\.c\.nc f4,f5=3D\[r5\] - 1546: 40 28 14 72 36 00 ldfpd\.c\.nc f4,f5=3D\[r5\],16 - 154c: 00 00 00 20 nop\.b 0x0 - 1550: 18 20 14 0a 3b 19 \[MMB\] ldfpd\.c\.nc\.nt1 f4,f5=3D\[r5\] - 1556: 40 28 14 76 36 00 ldfpd\.c\.nc\.nt1 f4,f5=3D\[r5\],= 16 - 155c: 00 00 00 20 nop\.b 0x0 - 1560: 18 20 14 0a 3f 19 \[MMB\] ldfpd\.c\.nc\.nta f4,f5=3D\[r5\] - 1566: 40 28 14 7e 36 00 ldfpd\.c\.nc\.nta f4,f5=3D\[r5\],= 16 - 156c: 00 00 00 20 nop\.b 0x0 - 1570: 18 20 14 0a 09 18 \[MMB\] ldfp8 f4,f5=3D\[r5\] - 1576: 40 28 14 12 34 00 ldfp8 f4,f5=3D\[r5\],16 - 157c: 00 00 00 20 nop\.b 0x0 - 1580: 18 20 14 0a 0b 18 \[MMB\] ldfp8\.nt1 f4,f5=3D\[r5\] - 1586: 40 28 14 16 34 00 ldfp8\.nt1 f4,f5=3D\[r5\],16 - 158c: 00 00 00 20 nop\.b 0x0 - 1590: 18 20 14 0a 0f 18 \[MMB\] ldfp8\.nta f4,f5=3D\[r5\] - 1596: 40 28 14 1e 34 00 ldfp8\.nta f4,f5=3D\[r5\],16 - 159c: 00 00 00 20 nop\.b 0x0 - 15a0: 18 20 14 0a 29 18 \[MMB\] ldfp8\.s f4,f5=3D\[r5\] - 15a6: 40 28 14 52 34 00 ldfp8\.s f4,f5=3D\[r5\],16 - 15ac: 00 00 00 20 nop\.b 0x0 - 15b0: 18 20 14 0a 2b 18 \[MMB\] ldfp8\.s\.nt1 f4,f5=3D\[r5\] - 15b6: 40 28 14 56 34 00 ldfp8\.s\.nt1 f4,f5=3D\[r5\],16 - 15bc: 00 00 00 20 nop\.b 0x0 - 15c0: 18 20 14 0a 2f 18 \[MMB\] ldfp8\.s\.nta f4,f5=3D\[r5\] - 15c6: 40 28 14 5e 34 00 ldfp8\.s\.nta f4,f5=3D\[r5\],16 - 15cc: 00 00 00 20 nop\.b 0x0 - 15d0: 18 20 14 0a 49 18 \[MMB\] ldfp8\.a f4,f5=3D\[r5\] - 15d6: 40 28 14 92 34 00 ldfp8\.a f4,f5=3D\[r5\],16 - 15dc: 00 00 00 20 nop\.b 0x0 - 15e0: 18 20 14 0a 4b 18 \[MMB\] ldfp8\.a\.nt1 f4,f5=3D\[r5\] - 15e6: 40 28 14 96 34 00 ldfp8\.a\.nt1 f4,f5=3D\[r5\],16 - 15ec: 00 00 00 20 nop\.b 0x0 - 15f0: 18 20 14 0a 4f 18 \[MMB\] ldfp8\.a\.nta f4,f5=3D\[r5\] - 15f6: 40 28 14 9e 34 00 ldfp8\.a\.nta f4,f5=3D\[r5\],16 - 15fc: 00 00 00 20 nop\.b 0x0 - 1600: 18 20 14 0a 69 18 \[MMB\] ldfp8\.sa f4,f5=3D\[r5\] - 1606: 40 28 14 d2 34 00 ldfp8\.sa f4,f5=3D\[r5\],16 - 160c: 00 00 00 20 nop\.b 0x0 - 1610: 18 20 14 0a 6b 18 \[MMB\] ldfp8\.sa\.nt1 f4,f5=3D\[r5\] - 1616: 40 28 14 d6 34 00 ldfp8\.sa\.nt1 f4,f5=3D\[r5\],16 - 161c: 00 00 00 20 nop\.b 0x0 - 1620: 18 20 14 0a 6f 18 \[MMB\] ldfp8\.sa\.nta f4,f5=3D\[r5\] - 1626: 40 28 14 de 34 00 ldfp8\.sa\.nta f4,f5=3D\[r5\],16 - 162c: 00 00 00 20 nop\.b 0x0 - 1630: 18 20 14 0a 09 19 \[MMB\] ldfp8\.c\.clr f4,f5=3D\[r5\] - 1636: 40 28 14 12 36 00 ldfp8\.c\.clr f4,f5=3D\[r5\],16 - 163c: 00 00 00 20 nop\.b 0x0 - 1640: 18 20 14 0a 0b 19 \[MMB\] ldfp8\.c\.clr\.nt1 f4,f5=3D\[r5= \] - 1646: 40 28 14 16 36 00 ldfp8\.c\.clr\.nt1 f4,f5=3D\[r5\]= ,16 - 164c: 00 00 00 20 nop\.b 0x0 - 1650: 18 20 14 0a 0f 19 \[MMB\] ldfp8\.c\.clr\.nta f4,f5=3D\[r5= \] - 1656: 40 28 14 1e 36 00 ldfp8\.c\.clr\.nta f4,f5=3D\[r5\]= ,16 - 165c: 00 00 00 20 nop\.b 0x0 - 1660: 18 20 14 0a 29 19 \[MMB\] ldfp8\.c\.nc f4,f5=3D\[r5\] - 1666: 40 28 14 52 36 00 ldfp8\.c\.nc f4,f5=3D\[r5\],16 - 166c: 00 00 00 20 nop\.b 0x0 - 1670: 18 20 14 0a 2b 19 \[MMB\] ldfp8\.c\.nc\.nt1 f4,f5=3D\[r5\] - 1676: 40 28 14 56 36 00 ldfp8\.c\.nc\.nt1 f4,f5=3D\[r5\],= 16 - 167c: 00 00 00 20 nop\.b 0x0 - 1680: 18 20 14 0a 2f 19 \[MMB\] ldfp8\.c\.nc\.nta f4,f5=3D\[r5\] - 1686: 40 28 14 5e 36 00 ldfp8\.c\.nc\.nta f4,f5=3D\[r5\],= 16 - 168c: 00 00 00 20 nop\.b 0x0 - 1690: 18 00 00 08 60 19 \[MMB\] lfetch \[r4\] - 1696: 00 28 10 c0 36 00 lfetch \[r4\],r5 - 169c: 00 00 00 20 nop\.b 0x0 - 16a0: 18 00 78 09 61 1f \[MMB\] lfetch \[r4\],-34 - 16a6: 00 00 10 c4 32 00 lfetch\.nt1 \[r4\] - 16ac: 00 00 00 20 nop\.b 0x0 - 16b0: 18 00 14 08 62 1b \[MMB\] lfetch\.nt1 \[r4\],r5 - 16b6: 00 58 13 c6 3e 00 lfetch\.nt1 \[r4\],-21 - 16bc: 00 00 00 20 nop\.b 0x0 - 16c0: 18 00 00 08 64 19 \[MMB\] lfetch\.nt2 \[r4\] - 16c6: 00 28 10 c8 36 00 lfetch\.nt2 \[r4\],r5 - 16cc: 00 00 00 20 nop\.b 0x0 - 16d0: 18 00 e0 09 65 1f \[MMB\] lfetch\.nt2 \[r4\],-8 - 16d6: 00 00 10 cc 32 00 lfetch\.nta \[r4\] - 16dc: 00 00 00 20 nop\.b 0x0 - 16e0: 18 00 14 08 66 1b \[MMB\] lfetch\.nta \[r4\],r5 - 16e6: 00 28 10 cc 3a 00 lfetch\.nta \[r4\],5 - 16ec: 00 00 00 20 nop\.b 0x0 - 16f0: 18 00 00 08 70 19 \[MMB\] lfetch\.fault \[r4\] - 16f6: 00 28 10 e0 36 00 lfetch\.fault \[r4\],r5 - 16fc: 00 00 00 20 nop\.b 0x0 - 1700: 18 00 48 08 70 1d \[MMB\] lfetch\.fault \[r4\],18 - 1706: 00 00 10 e4 32 00 lfetch\.fault\.nt1 \[r4\] - 170c: 00 00 00 20 nop\.b 0x0 - 1710: 18 00 14 08 72 1b \[MMB\] lfetch\.fault\.nt1 \[r4\],r5 - 1716: 00 f8 10 e4 3a 00 lfetch\.fault\.nt1 \[r4\],31 - 171c: 00 00 00 20 nop\.b 0x0 - 1720: 18 00 00 08 74 19 \[MMB\] lfetch\.fault\.nt2 \[r4\] - 1726: 00 28 10 e8 36 00 lfetch\.fault\.nt2 \[r4\],r5 - 172c: 00 00 00 20 nop\.b 0x0 - 1730: 18 00 b0 08 74 1d \[MMB\] lfetch\.fault\.nt2 \[r4\],44 - 1736: 00 00 10 ec 32 00 lfetch\.fault\.nta \[r4\] - 173c: 00 00 00 20 nop\.b 0x0 - 1740: 18 00 14 08 76 1b \[MMB\] lfetch\.fault\.nta \[r4\],r5 - 1746: 00 c8 11 ec 3a 00 lfetch\.fault\.nta \[r4\],57 - 174c: 00 00 00 20 nop\.b 0x0 - 1750: 18 00 00 08 68 19 \[MMB\] lfetch\.excl \[r4\] - 1756: 00 28 10 d0 36 00 lfetch\.excl \[r4\],r5 - 175c: 00 00 00 20 nop\.b 0x0 - 1760: 18 00 18 09 68 1d \[MMB\] lfetch\.excl \[r4\],70 - 1766: 00 00 10 d4 32 00 lfetch\.excl\.nt1 \[r4\] - 176c: 00 00 00 20 nop\.b 0x0 - 1770: 18 00 14 08 6a 1b \[MMB\] lfetch\.excl\.nt1 \[r4\],r5 - 1776: 00 98 12 d4 3a 00 lfetch\.excl\.nt1 \[r4\],83 - 177c: 00 00 00 20 nop\.b 0x0 - 1780: 18 00 00 08 6c 19 \[MMB\] lfetch\.excl\.nt2 \[r4\] - 1786: 00 28 10 d8 36 00 lfetch\.excl\.nt2 \[r4\],r5 - 178c: 00 00 00 20 nop\.b 0x0 - 1790: 18 00 80 09 6c 1d \[MMB\] lfetch\.excl\.nt2 \[r4\],96 - 1796: 00 00 10 dc 32 00 lfetch\.excl\.nta \[r4\] - 179c: 00 00 00 20 nop\.b 0x0 - 17a0: 18 00 14 08 6e 1b \[MMB\] lfetch\.excl\.nta \[r4\],r5 - 17a6: 00 68 13 dc 3a 00 lfetch\.excl\.nta \[r4\],109 - 17ac: 00 00 00 20 nop\.b 0x0 - 17b0: 18 00 00 08 78 19 \[MMB\] lfetch\.fault\.excl \[r4\] - 17b6: 00 28 10 f0 36 00 lfetch\.fault\.excl \[r4\],r5 - 17bc: 00 00 00 20 nop\.b 0x0 - 17c0: 18 00 e8 09 78 1d \[MMB\] lfetch\.fault\.excl \[r4\],122 - 17c6: 00 00 10 f4 32 00 lfetch\.fault\.excl\.nt1 \[r4\] - 17cc: 00 00 00 20 nop\.b 0x0 - 17d0: 18 00 14 08 7a 1b \[MMB\] lfetch\.fault\.excl\.nt1 \[r4\]= ,r5 - 17d6: 00 38 10 f6 3a 00 lfetch\.fault\.excl\.nt1 \[r4\],1= 35 - 17dc: 00 00 00 20 nop\.b 0x0 - 17e0: 18 00 00 08 7c 19 \[MMB\] lfetch\.fault\.excl\.nt2 \[r4\] - 17e6: 00 28 10 f8 36 00 lfetch\.fault\.excl\.nt2 \[r4\],r5 - 17ec: 00 00 00 20 nop\.b 0x0 - 17f0: 18 00 50 08 7d 1d \[MMB\] lfetch\.fault\.excl\.nt2 \[r4\]= ,148 - 17f6: 00 00 10 fc 32 00 lfetch\.fault\.excl\.nta \[r4\] - 17fc: 00 00 00 20 nop\.b 0x0 - 1800: 18 00 14 08 7e 1b \[MMB\] lfetch\.fault\.excl\.nta \[r4\]= ,r5 - 1806: 00 08 11 fe 3a 00 lfetch\.fault\.excl\.nta \[r4\],1= 61 - 180c: 00 00 00 20 nop\.b 0x0 - 1810: 18 20 18 0a 01 10 \[MMB\] cmpxchg1\.acq r4=3D\[r5\],r6,ar= \.ccv - 1816: 40 30 14 06 20 00 cmpxchg1\.acq\.nt1 r4=3D\[r5\],r6= ,ar\.ccv - 181c: 00 00 00 20 nop\.b 0x0 - 1820: 18 20 18 0a 07 10 \[MMB\] cmpxchg1\.acq\.nta r4=3D\[r5\],= r6,ar\.ccv - 1826: 40 30 14 42 20 00 cmpxchg1\.rel r4=3D\[r5\],r6,ar\.= ccv - 182c: 00 00 00 20 nop\.b 0x0 - 1830: 18 20 18 0a 23 10 \[MMB\] cmpxchg1\.rel\.nt1 r4=3D\[r5\],= r6,ar\.ccv - 1836: 40 30 14 4e 20 00 cmpxchg1\.rel\.nta r4=3D\[r5\],r6= ,ar\.ccv - 183c: 00 00 00 20 nop\.b 0x0 - 1840: 18 20 18 0a 09 10 \[MMB\] cmpxchg2\.acq r4=3D\[r5\],r6,ar= \.ccv - 1846: 40 30 14 16 20 00 cmpxchg2\.acq\.nt1 r4=3D\[r5\],r6= ,ar\.ccv - 184c: 00 00 00 20 nop\.b 0x0 - 1850: 18 20 18 0a 0f 10 \[MMB\] cmpxchg2\.acq\.nta r4=3D\[r5\],= r6,ar\.ccv - 1856: 40 30 14 52 20 00 cmpxchg2\.rel r4=3D\[r5\],r6,ar\.= ccv - 185c: 00 00 00 20 nop\.b 0x0 - 1860: 18 20 18 0a 2b 10 \[MMB\] cmpxchg2\.rel\.nt1 r4=3D\[r5\],= r6,ar\.ccv - 1866: 40 30 14 5e 20 00 cmpxchg2\.rel\.nta r4=3D\[r5\],r6= ,ar\.ccv - 186c: 00 00 00 20 nop\.b 0x0 - 1870: 18 20 18 0a 11 10 \[MMB\] cmpxchg4\.acq r4=3D\[r5\],r6,ar= \.ccv - 1876: 40 30 14 26 20 00 cmpxchg4\.acq\.nt1 r4=3D\[r5\],r6= ,ar\.ccv - 187c: 00 00 00 20 nop\.b 0x0 - 1880: 18 20 18 0a 17 10 \[MMB\] cmpxchg4\.acq\.nta r4=3D\[r5\],= r6,ar\.ccv - 1886: 40 30 14 62 20 00 cmpxchg4\.rel r4=3D\[r5\],r6,ar\.= ccv - 188c: 00 00 00 20 nop\.b 0x0 - 1890: 18 20 18 0a 33 10 \[MMB\] cmpxchg4\.rel\.nt1 r4=3D\[r5\],= r6,ar\.ccv - 1896: 40 30 14 6e 20 00 cmpxchg4\.rel\.nta r4=3D\[r5\],r6= ,ar\.ccv - 189c: 00 00 00 20 nop\.b 0x0 - 18a0: 18 20 18 0a 19 10 \[MMB\] cmpxchg8\.acq r4=3D\[r5\],r6,ar= \.ccv - 18a6: 40 30 14 36 20 00 cmpxchg8\.acq\.nt1 r4=3D\[r5\],r6= ,ar\.ccv - 18ac: 00 00 00 20 nop\.b 0x0 - 18b0: 18 20 18 0a 1f 10 \[MMB\] cmpxchg8\.acq\.nta r4=3D\[r5\],= r6,ar\.ccv - 18b6: 40 30 14 72 20 00 cmpxchg8\.rel r4=3D\[r5\],r6,ar\.= ccv - 18bc: 00 00 00 20 nop\.b 0x0 - 18c0: 18 20 18 0a 3b 10 \[MMB\] cmpxchg8\.rel\.nt1 r4=3D\[r5\],= r6,ar\.ccv - 18c6: 40 30 14 7e 20 00 cmpxchg8\.rel\.nta r4=3D\[r5\],r6= ,ar\.ccv - 18cc: 00 00 00 20 nop\.b 0x0 - 18d0: 18 20 18 0a 41 10 \[MMB\] xchg1 r4=3D\[r5\],r6 - 18d6: 40 30 14 86 20 00 xchg1\.nt1 r4=3D\[r5\],r6 - 18dc: 00 00 00 20 nop\.b 0x0 - 18e0: 18 20 18 0a 47 10 \[MMB\] xchg1\.nta r4=3D\[r5\],r6 - 18e6: 40 30 14 92 20 00 xchg2 r4=3D\[r5\],r6 - 18ec: 00 00 00 20 nop\.b 0x0 - 18f0: 18 20 18 0a 4b 10 \[MMB\] xchg2\.nt1 r4=3D\[r5\],r6 - 18f6: 40 30 14 9e 20 00 xchg2\.nta r4=3D\[r5\],r6 - 18fc: 00 00 00 20 nop\.b 0x0 - 1900: 18 20 18 0a 51 10 \[MMB\] xchg4 r4=3D\[r5\],r6 - 1906: 40 30 14 a6 20 00 xchg4\.nt1 r4=3D\[r5\],r6 - 190c: 00 00 00 20 nop\.b 0x0 - 1910: 18 20 18 0a 57 10 \[MMB\] xchg4\.nta r4=3D\[r5\],r6 - 1916: 40 30 14 b2 20 00 xchg8 r4=3D\[r5\],r6 - 191c: 00 00 00 20 nop\.b 0x0 - 1920: 18 20 18 0a 5b 10 \[MMB\] xchg8\.nt1 r4=3D\[r5\],r6 - 1926: 40 30 14 be 20 00 xchg8\.nta r4=3D\[r5\],r6 - 192c: 00 00 00 20 nop\.b 0x0 - 1930: 18 20 10 0a 91 10 \[MMB\] fetchadd4\.acq r4=3D\[r5\],-16 - 1936: 40 28 14 26 21 00 fetchadd4\.acq\.nt1 r4=3D\[r5\],-8 - 193c: 00 00 00 20 nop\.b 0x0 - 1940: 18 20 18 0a 97 10 \[MMB\] fetchadd4\.acq\.nta r4=3D\[r5\]= ,-4 - 1946: 40 38 14 32 21 00 fetchadd8\.acq r4=3D\[r5\],-1 - 194c: 00 00 00 20 nop\.b 0x0 - 1950: 18 20 0c 0a 9b 10 \[MMB\] fetchadd8\.acq\.nt1 r4=3D\[r5\]= ,1 - 1956: 40 10 14 3e 21 00 fetchadd8\.acq\.nta r4=3D\[r5\],4 - 195c: 00 00 00 20 nop\.b 0x0 - 1960: 18 20 04 0a b1 10 \[MMB\] fetchadd4\.rel r4=3D\[r5\],8 - 1966: 40 00 14 66 21 00 fetchadd4\.rel\.nt1 r4=3D\[r5\],16 - 196c: 00 00 00 20 nop\.b 0x0 - 1970: 18 20 10 0a b7 10 \[MMB\] fetchadd4\.rel\.nta r4=3D\[r5\]= ,-16 - 1976: 40 28 14 72 21 00 fetchadd8\.rel r4=3D\[r5\],-8 - 197c: 00 00 00 20 nop\.b 0x0 - 1980: 18 20 18 0a bb 10 \[MMB\] fetchadd8\.rel\.nt1 r4=3D\[r5\]= ,-4 - 1986: 40 38 14 7e 21 00 fetchadd8\.rel\.nta r4=3D\[r5\],-1 - 198c: 00 00 00 20 nop\.b 0x0 - 1990: 18 20 14 00 e1 18 \[MMB\] setf\.sig f4=3Dr5 - 1996: 40 28 00 d2 31 00 setf\.exp f4=3Dr5 - 199c: 00 00 00 20 nop\.b 0x0 - 19a0: 18 20 14 00 f1 18 \[MMB\] setf\.s f4=3Dr5 - 19a6: 40 28 00 f2 31 00 setf\.d f4=3Dr5 - 19ac: 00 00 00 20 nop\.b 0x0 - 19b0: 18 20 14 00 e1 10 \[MMB\] getf\.sig r4=3Df5 - 19b6: 40 28 00 d2 21 00 getf\.exp r4=3Df5 - 19bc: 00 00 00 20 nop\.b 0x0 - 19c0: 18 20 14 00 f1 10 \[MMB\] getf\.s r4=3Df5 - 19c6: 40 28 00 f2 21 00 getf\.d r4=3Df5 - 19cc: 00 00 00 20 nop\.b 0x0 - 19d0: 18 18 13 f8 7f 06 \[MMB\] chk\.s\.m r4,0 <_start> - 19d6: 30 26 f0 ff 0d 00 chk\.s f4,0 <_start> - 19dc: 00 00 00 20 nop\.b 0x0 - 19e0: 18 20 88 f9 3f 03 \[MMB\] chk\.a\.nc r4,0 <_start> - 19e6: 40 10 f3 ff 06 00 chk\.a\.clr r4,0 <_start> - 19ec: 00 00 00 20 nop\.b 0x0 - 19f0: 18 20 84 f9 bf 03 \[MMB\] chk\.a\.nc f4,0 <_start> - 19f6: 40 08 f3 ff 07 00 chk\.a\.clr f4,0 <_start> - 19fc: 00 00 00 20 nop\.b 0x0 - 1a00: 18 00 00 00 10 00 \[MMB\] invala - 1a06: 00 00 00 40 00 00 fwb - 1a0c: 00 00 00 20 nop\.b 0x0 - 1a10: 18 00 00 00 22 00 \[MMB\] mf - 1a16: 00 00 00 46 00 00 mf\.a - 1a1c: 00 00 00 20 nop\.b 0x0 - 1a20: 18 00 00 00 30 00 \[MMB\] srlz\.d - 1a26: 00 00 00 62 00 00 srlz\.i - 1a2c: 00 00 00 20 nop\.b 0x0 - 1a30: 09 00 00 00 33 00 \[MMI\] sync\.i - 1a36: 00 00 00 02 00 00 nop\.m 0x0 - 1a3c: 00 00 04 00 nop\.i 0x0;; - 1a40: 01 20 70 18 82 05 \[MII\] alloc r4=3Dar\.pfs,28,12,16 - 1a46: 00 00 00 02 00 00 nop\.i 0x0 - 1a4c: 00 00 04 00 nop\.i 0x0;; - 1a50: 01 00 00 00 0c 00 \[MII\] flushrs - 1a56: 00 00 00 02 00 00 nop\.i 0x0 - 1a5c: 00 00 04 00 nop\.i 0x0;; - 1a60: 00 00 00 00 0a 00 \[MII\] loadrs - 1a66: 00 00 00 02 00 00 nop\.i 0x0 - 1a6c: 00 00 04 00 nop\.i 0x0 - 1a70: 18 20 00 00 12 00 \[MMB\] invala\.e r4 - 1a76: 40 00 00 26 00 00 invala\.e f4 - 1a7c: 00 00 00 20 nop\.b 0x0 - 1a80: 18 00 00 08 30 04 \[MMB\] fc r4 - 1a86: 00 00 10 68 08 00 ptc\.e r4 - 1a8c: 00 00 00 20 nop\.b 0x0 - 1a90: 18 00 00 00 00 00 \[MMB\] break\.m 0x0 - 1a96: f0 ff 1f 00 00 00 break\.m 0x1ffff - 1a9c: 00 00 00 20 nop\.b 0x0 - 1aa0: 18 00 00 00 01 00 \[MMB\] nop\.m 0x0 - 1aa6: f0 ff 1f 02 00 00 nop\.m 0x1ffff - 1aac: 00 00 00 20 nop\.b 0x0 - 1ab0: 18 20 18 0a 38 04 \[MMB\] probe\.r r4=3Dr5,r6 - 1ab6: 40 30 14 72 08 00 probe\.w r4=3Dr5,r6 - 1abc: 00 00 00 20 nop\.b 0x0 - 1ac0: 18 20 00 0a 18 04 \[MMB\] probe\.r r4=3Dr5,0 - 1ac6: 40 08 14 32 08 00 probe\.w r4=3Dr5,1 - 1acc: 00 00 00 20 nop\.b 0x0 - 1ad0: 18 00 08 06 32 04 \[MMB\] probe\.r\.fault r3,2 - 1ad6: 00 18 0c 66 08 00 probe\.w\.fault r3,3 - 1adc: 00 00 00 20 nop\.b 0x0 - 1ae0: 18 00 00 06 31 04 \[MMB\] probe\.rw\.fault r3,0 - 1ae6: 00 00 00 02 00 00 nop\.m 0x0 - 1aec: 00 00 00 20 nop\.b 0x0 - 1af0: 0b 00 20 00 2e 04 \[MMI\] itc\.d r8;; - 1af6: 00 00 00 02 00 00 nop\.m 0x0 - 1afc: 00 00 04 00 nop\.i 0x0;; - 1b00: 0a 00 24 00 2f 04 \[MMI\] itc\.i r9;; - 1b06: 40 23 01 08 00 00 sum 0x1234 - 1b0c: 00 00 04 00 nop\.i 0x0 - 1b10: 18 50 55 d5 25 00 \[MMB\] rum 0x5aaaaa - 1b16: f0 ff ff 6d 04 00 ssm 0xffffff - 1b1c: 00 00 00 20 nop\.b 0x0 - 1b20: 18 00 00 00 27 00 \[MMB\] rsm 0x400000 - 1b26: 00 28 10 12 08 00 ptc\.l r4,r5 - 1b2c: 00 00 00 20 nop\.b 0x0 - 1b30: 0a 00 14 08 0a 04 \[MMI\] ptc\.g r4,r5;; - 1b36: 00 00 00 02 00 00 nop\.m 0x0 - 1b3c: 00 00 04 00 nop\.i 0x0 - 1b40: 0a 00 14 08 0b 04 \[MMI\] ptc\.ga r4,r5;; - 1b46: 00 00 00 02 00 00 nop\.m 0x0 - 1b4c: 00 00 04 00 nop\.i 0x0 - 1b50: 18 00 14 08 0c 04 \[MMB\] ptr\.d r4,r5 - 1b56: 00 28 10 1a 08 00 ptr\.i r4,r5 - 1b5c: 00 00 00 20 nop\.b 0x0 - 1b60: 18 20 00 0a 1a 04 \[MMB\] thash r4=3Dr5 - 1b66: 40 00 14 36 08 00 ttag r4=3Dr5 - 1b6c: 00 00 00 20 nop\.b 0x0 - 1b70: 18 20 00 0a 1e 04 \[MMB\] tpa r4=3Dr5 - 1b76: 40 00 14 3e 08 00 tak r4=3Dr5 - 1b7c: 00 00 00 20 nop\.b 0x0 - 1b80: 18 00 00 80 01 00 \[MMB\] hint\.m 0 - 1b86: 00 00 00 03 00 00 hint\.m 0 - 1b8c: 00 00 00 20 nop\.b 0x0 - 1b90: 18 78 fe bf 01 00 \[MMB\] hint\.m 131071 - 1b96: 40 30 14 02 22 00 cmp8xchg16\.acq r4=3D\[r5\],r6,ar= \.csd,ar\.ccv - 1b9c: 00 00 00 20 nop\.b 0x0 - 1ba0: 18 20 18 0a 03 11 \[MMB\] cmp8xchg16\.acq\.nt1 r4=3D\[r5\= ],r6,ar\.csd,ar\.ccv - 1ba6: 40 30 14 0e 22 00 cmp8xchg16\.acq\.nta r4=3D\[r5\],= r6,ar\.csd,ar\.ccv - 1bac: 00 00 00 20 nop\.b 0x0 - 1bb0: 18 20 18 0a 21 11 \[MMB\] cmp8xchg16\.rel r4=3D\[r5\],r6,= ar\.csd,ar\.ccv - 1bb6: 40 30 14 46 22 00 cmp8xchg16\.rel\.nt1 r4=3D\[r5\],= r6,ar\.csd,ar\.ccv - 1bbc: 00 00 00 20 nop\.b 0x0 - 1bc0: 18 20 18 0a 27 11 \[MMB\] cmp8xchg16\.rel\.nta r4=3D\[r5\= ],r6,ar\.csd,ar\.ccv - 1bc6: 00 00 10 60 0c 00 fc\.i r4 - 1bcc: 00 00 00 20 nop\.b 0x0 - 1bd0: 18 20 00 0a 41 11 \[MMB\] ld16 r4,ar\.csd=3D\[r5\] - 1bd6: 40 00 14 86 22 00 ld16\.nt1 r4,ar\.csd=3D\[r5\] - 1bdc: 00 00 00 20 nop\.b 0x0 - 1be0: 18 20 00 0a 47 11 \[MMB\] ld16\.nta r4,ar\.csd=3D\[r5\] - 1be6: 40 00 14 c2 22 00 ld16\.acq r4,ar\.csd=3D\[r5\] - 1bec: 00 00 00 20 nop\.b 0x0 - 1bf0: 18 20 00 0a 63 11 \[MMB\] ld16\.acq\.nt1 r4,ar\.csd=3D\[r= 5\] - 1bf6: 40 00 14 ce 22 00 ld16\.acq\.nta r4,ar\.csd=3D\[r5\] - 1bfc: 00 00 00 20 nop\.b 0x0 - 1c00: 18 00 14 08 81 11 \[MMB\] st16 \[r4\]=3Dr5,ar\.csd - 1c06: 00 28 10 0e 23 00 st16\.nta \[r4\]=3Dr5,ar\.csd - 1c0c: 00 00 00 20 nop\.b 0x0 - 1c10: 19 00 14 08 a1 11 \[MMB\] st16\.rel \[r4\]=3Dr5,ar\.csd - 1c16: 00 28 10 4e 23 00 st16\.rel\.nta \[r4\]=3Dr5,ar\.csd - 1c1c: 00 00 00 20 nop\.b 0x0;; diff --git a/gas/testsuite/gas/ia64/opc-m.pl b/gas/testsuite/gas/ia64/opc-m= .pl deleted file mode 100644 index 93c7bc97be4..00000000000 --- a/gas/testsuite/gas/ia64/opc-m.pl +++ /dev/null @@ -1,218 +0,0 @@ -print ".text\n\t.type _start,@", "function\n_start:\n\n"; - -@ldhint =3D ( "", ".nt1", ".nta" ); -@ldspec =3D ( "", ".s", ".a", ".sa", ".c.clr", ".c.nc" ); -@sthint =3D ( "", ".nta" ); - -$i =3D 0; - -# Integer Load - -foreach $s ( "1", "2", "4", "8" ) { - foreach $e (@ldspec, ".bias", ".acq", ".c.clr.acq") { - foreach $l (@ldhint) { - print "\tld${s}${e}${l} r4 =3D [r5]\n"; - print "\tld${s}${e}${l} r4 =3D [r5], r6\n"; - print "\tld${s}${e}${l} r4 =3D [r5], ", $i - 256, "\n"; - $i =3D ($i + 13) % 512; - } - print "\n"; - } -} - -# Integer Fill - -for $l (@ldhint) { - print "\tld8.fill${l} r4 =3D [r5]\n"; - print "\tld8.fill${l} r4 =3D [r5], r6\n"; - print "\tld8.fill${l} r4 =3D [r5], ", $i - 256, "\n"; - $i =3D ($i + 13) % 512; -} -print "\n"; - -# Integer Store - -foreach $s ("1", "2", "4", "8", "1.rel", "2.rel", "4.rel", "8.rel", "8.spi= ll") { - for $l (@sthint) { - print "\tst${s}${l} [r4] =3D r5\n"; - print "\tst${s}${l} [r4] =3D r5, ", $i - 256, "\n"; - $i =3D ($i + 13) % 512; - } - print "\n"; -} - -# Floating Point Load - -foreach $s ( "fs", "fd", "f8", "fe" ) { - foreach $e (@ldspec) { - foreach $l (@ldhint) { - print "\tld${s}${e}${l} f4 =3D [r5]\n"; - print "\tld${s}${e}${l} f4 =3D [r5], r6\n"; - print "\tld${s}${e}${l} f4 =3D [r5], ", $i - 256, "\n"; - $i =3D ($i + 13) % 512; - } - print "\n"; - } -} - -# Floating Point Fill - -for $l (@ldhint) { - print "\tldf.fill${l} f4 =3D [r5]\n"; - print "\tldf.fill${l} f4 =3D [r5], r6\n"; - print "\tldf.fill${l} f4 =3D [r5], ", $i - 256, "\n"; - $i =3D ($i + 13) % 512; -} -print "\n"; - -# Floating Point Store - -foreach $s ( "fs", "fd", "f8", "fe", "f.spill" ) { - for $l (@sthint) { - print "\tst${s}${l} [r4] =3D f5\n"; - print "\tst${s}${l} [r4] =3D f5, ", $i - 256, "\n"; - $i =3D ($i + 13) % 512; - } - print "\n"; -} - -# Floating Point Load Pair - -foreach $s ( "fps", "fpd", "fp8" ) { - foreach $e (@ldspec) { - foreach $l (@ldhint) { - print "\tld${s}${e}${l} f4, f5 =3D [r5]\n"; - print "\tld${s}${e}${l} f4, f5 =3D [r5], ", ($s eq "fps" ? 8 : 16), = "\n"; - } - print "\n"; - } -} - -# Line Prefetch - -@lfhint =3D ( "", ".nt1", ".nt2", ".nta" ); - -foreach $e ( "", ".excl" ) { - foreach $f ( "", ".fault" ) { - foreach $h (@lfhint) { - print "\tlfetch${f}${e}${h} [r4]\n"; - print "\tlfetch${f}${e}${h} [r4], r5\n"; - print "\tlfetch${f}${e}${h} [r4], ", $i - 256, "\n"; - $i =3D ($i + 13) % 512; - } - print "\n"; - } -} - -# Compare and Exchange - -foreach $s ( "1", "2", "4", "8" ) { - foreach $e ( ".acq", ".rel" ) { - foreach $h (@ldhint) { - print "\tcmpxchg${s}${e}${h} r4 =3D [r5], r6, ar.ccv\n"; - } - print "\n"; - } -} - -# Exchange - -foreach $s ( "1", "2", "4", "8" ) { - foreach $h (@ldhint) { - print "\txchg${s}${h} r4 =3D [r5], r6\n"; - } - print "\n"; -} - -# Fetch and Add - -$i =3D 0; -@inc3 =3D ( -16, -8, -4, -1, 1, 4, 8, 16 ); -foreach $s ( "4.acq", "8.acq", "4.rel", "8.rel" ) { - foreach $h (@ldhint) { - print "\tfetchadd${s}${h} r4 =3D [r5], ", $inc3[$i], "\n"; - $i =3D ($i + 1) % 8; - } - print "\n"; -} - -# Get/Set FR - -foreach $e ( ".sig", ".exp", ".s", ".d" ) { - print "\tsetf${e} f4 =3D r5\n"; -} -print "\n"; - -foreach $e ( ".sig", ".exp", ".s", ".d" ) { - print "\tgetf${e} r4 =3D f5\n"; -} -print "\n"; - -# Speculation and Advanced Load Checkso - -print <: - 0: 04 00 00 00 01 00 \[MLX\] nop\.m 0x0 - 6: 00 00 00 00 00 00 break\.x 0x0 - c: 00 00 00 00=20 - 10: 04 00 00 00 01 c0 \[MLX\] nop\.m 0x0 - 16: ff ff ff ff 7f e0 break\.x 0x3fffffffffffffff - 1c: ff ff 01 08=20 - 20: 04 00 00 00 01 00 \[MLX\] nop\.m 0x0 - 26: 00 00 00 00 00 00 nop\.x 0x0 - 2c: 00 00 04 00=20 - 30: 04 00 00 00 01 c0 \[MLX\] nop\.m 0x0 - 36: ff ff ff ff 7f e0 nop\.x 0x3fffffffffffffff - 3c: ff ff 05 08=20 - 40: 04 00 00 00 01 00 \[MLX\] nop\.m 0x0 - 46: 00 00 00 00 00 80 movl r4=3D0x0 - 4c: 00 00 00 60=20 - 50: 04 00 00 00 01 c0 \[MLX\] nop\.m 0x0 - 56: ff ff ff ff 7f 80 movl r4=3D0xffffffffffffffff - 5c: f0 f7 ff 6f=20 - 60: 04 00 00 00 01 80 \[MLX\] nop\.m 0x0 - 66: 90 78 56 34 12 80 movl r4=3D0x1234567890abcdef - 6c: f0 76 6d 66=20 - 70: 04 00 00 00 01 00 \[MLX\] nop\.m 0x0 - 76: 00 00 00 00 00 00 hint\.x 0x0 - 7c: 00 00 06 00=20 - 80: 04 00 00 00 01 00 \[MLX\] nop\.m 0x0 - 86: 00 00 00 00 00 00 hint\.x 0x0 - 8c: 00 00 06 00=20 - 90: 05 00 00 00 01 c0 \[MLX\] nop\.m 0x0 - 96: ff ff ff ff 7f e0 hint\.x 0x3fffffffffffffff;; - 9c: ff ff 07 08=20 diff --git a/gas/testsuite/gas/ia64/opc-x.s b/gas/testsuite/gas/ia64/opc-x.s deleted file mode 100644 index 4332d51ed30..00000000000 --- a/gas/testsuite/gas/ia64/opc-x.s +++ /dev/null @@ -1,19 +0,0 @@ -.text - .type _start,@function -_start: - - break.x 0 - break.x 0x3fffffffffffffff - - nop.x 0 - nop.x 0x3fffffffffffffff - - movl r4 =3D 0 - movl r4 =3D 0xffffffffffffffff - movl r4 =3D 0x1234567890abcdef - - # instructions added by SDM2.1: - - hint.x 0 - hint.x @pause - hint.x 0x3fffffffffffffff diff --git a/gas/testsuite/gas/ia64/operand-or.d b/gas/testsuite/gas/ia64/o= perand-or.d deleted file mode 100644 index a40087a853a..00000000000 --- a/gas/testsuite/gas/ia64/operand-or.d +++ /dev/null @@ -1,30 +0,0 @@ -# as: -xnone -mtune=3Ditanium1 -# objdump: -d --disassemble-zeroes -# name: ia64 operand-or - -.*: +file format .* - -Disassembly of section \.text: - -0+000 <_start>: - 0: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 6: 30 20 80 09 28 00 fclass\.m p3,p4=3Df4,0x180 - c: 00 00 00 20 nop\.b 0x0 - 10: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 16: 30 20 c0 09 28 00 fclass\.m p3,p4=3Df4,0x1c0 - 1c: 00 00 00 20 nop\.b 0x0 - 20: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 26: 30 20 c0 89 28 00 fclass\.m p3,p4=3Df4,0x1c1 - 2c: 00 00 00 20 nop\.b 0x0 - 30: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 36: 30 20 c0 89 29 00 fclass\.m p3,p4=3Df4,0x1c3 - 3c: 00 00 00 20 nop\.b 0x0 - 40: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 46: 30 20 c8 89 29 00 fclass\.m p3,p4=3Df4,0x1cb - 4c: 00 00 00 20 nop\.b 0x0 - 50: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 56: 30 20 d8 89 29 00 fclass\.m p3,p4=3Df4,0x1db - 5c: 00 00 00 20 nop\.b 0x0 - 60: 1d 00 00 00 01 00 \[MFB\] nop\.m 0x0 - 66: 30 20 f8 89 29 00 fclass\.m p3,p4=3Df4,0x1fb - 6c: 00 00 00 20 nop\.b 0x0;; diff --git a/gas/testsuite/gas/ia64/operand-or.s b/gas/testsuite/gas/ia64/o= perand-or.s deleted file mode 100644 index a48a9162a4d..00000000000 --- a/gas/testsuite/gas/ia64/operand-or.s +++ /dev/null @@ -1,11 +0,0 @@ -.text - .type _start,@function -_start: - - fclass.m p3, p4 =3D f4, @nat|@qnan - fclass.m p3, p4 =3D f4, @nat|@qnan|@snan - fclass.m p3, p4 =3D f4, @nat|@qnan|@snan|@pos - fclass.m p3, p4 =3D f4, @nat|@qnan|@snan|@pos|@neg - fclass.m p3, p4 =3D f4, @nat|@qnan|@snan|@pos|@neg|@unorm - fclass.m p3, p4 =3D f4, @nat|@qnan|@snan|@pos|@neg|@unorm|@norm - fclass.m p3, p4 =3D f4, @nat|@qnan|@snan|@pos|@neg|@unorm|@norm|@inf diff --git a/gas/testsuite/gas/ia64/operands.l b/gas/testsuite/gas/ia64/ope= rands.l deleted file mode 100644 index 440c78b5260..00000000000 --- a/gas/testsuite/gas/ia64/operands.l +++ /dev/null @@ -1,5 +0,0 @@ -.*: Assembler messages: -.*:3: Error: .* output .* -.*:4: Error: .* input .* -.*:5: Error: .* 1 .* -.*:6: Error: .* 2 .* diff --git a/gas/testsuite/gas/ia64/operands.s b/gas/testsuite/gas/ia64/ope= rands.s deleted file mode 100644 index 08f4ec15b6f..00000000000 --- a/gas/testsuite/gas/ia64/operands.s +++ /dev/null @@ -1,6 +0,0 @@ - .text -_start: - zxt1 r1, r2 =3D r3 - zxt2 r4 =3D r5, r6 - zxt4 p1 =3D r8 - sxt1 r7 =3D 0 diff --git a/gas/testsuite/gas/ia64/order.d b/gas/testsuite/gas/ia64/order.d deleted file mode 100644 index c28bc661a9b..00000000000 --- a/gas/testsuite/gas/ia64/order.d +++ /dev/null @@ -1,36 +0,0 @@ -#objdump: -j .foo -j .bar -rs -#name: ia64 byte order - -.*: +file format .* - -RELOCATION RECORDS FOR \[.foo\]: -OFFSET +TYPE +VALUE -0+00008 DIR64MSB foo -0+00018 DIR64MSB foo -0+00028 DIR64LSB foo -0+00038 DIR64LSB foo - - -RELOCATION RECORDS FOR \[.bar\]: -OFFSET +TYPE +VALUE -0+00010 DIR64LSB foo -0+00040 DIR64LSB foo -0+00058 DIR64MSB foo -0+00080 DIR64MSB foo - - -Contents of section .foo: - 0000 12340000 12345678 00000000 00000000 ................ - 0010 01234567 89abcdef 00000000 00000000 ................ - 0020 34120000 78563412 00000000 00000000 ................ - 0030 efcdab89 67452301 00000000 00000000 ................ -Contents of section .bar: - 0000 cdcccc3d 00000000 9a999999 9999c93f ................ - 0010 00000000 00000000 00000000 00000000 ................ - 0020 cdcccccc cccccccc fd3f0000 00000000 ................ - 0030 cdcccccc cccccccc fe3f0000 00000000 ................ - 0040 00000000 00000000 3dcccccd 00000000 ................ - 0050 3fc99999 9999999a 00000000 00000000 ................ - 0060 3ffdcccc cccccccc cccd0000 00000000 ................ - 0070 3ffecccc cccccccc cccd0000 00000000 ................ - 0080 00000000 00000000 ........=20=20=20=20=20=20=20=20 diff --git a/gas/testsuite/gas/ia64/order.s b/gas/testsuite/gas/ia64/order.s deleted file mode 100644 index 2867ce081ba..00000000000 --- a/gas/testsuite/gas/ia64/order.s +++ /dev/null @@ -1,37 +0,0 @@ - .global foo# - .section .foo,"aw","progbits" - .msb - data2 0x1234 - data4 0x12345678 - data8 foo# - .section .bar,"aw","progbits" - .lsb - real4 0.1 - real8 0.2 - data8 foo# - .section .foo,"aw","progbits" - data8 0x123456789abcdef -// data16 0x123456789abcdef - data8 foo# - .section .bar,"aw","progbits" - real10 0.4 - real16 0.8 - data8 foo# - .section .foo,"aw","progbits" - .lsb - data2 0x1234 - data4 0x12345678 - data8 foo# - .section .bar,"aw","progbits" - .msb - real4 0.1 - real8 0.2 - data8 foo# - .section .foo,"aw","progbits" - data8 0x123456789abcdef -// data16 0x123456789abcdef - data8 foo# - .section .bar,"aw","progbits" - real10 0.4 - real16 0.8 - data8 foo# diff --git a/gas/testsuite/gas/ia64/pcrel.d b/gas/testsuite/gas/ia64/pcrel.d deleted file mode 100644 index 79617b9d1dd..00000000000 --- a/gas/testsuite/gas/ia64/pcrel.d +++ /dev/null @@ -1,63 +0,0 @@ -#as: -mtune=3Ditanium1 -#objdump: -rs -#name: ia64 pcrel - -.*: +file format .* - -RELOCATION RECORDS FOR \[\.mov\]: -OFFSET[[:space:]]+TYPE[[:space:]]+VALUE[[:space:]]* -0+10[[:space:]]+PCREL22[[:space:]]+esym -0+20[[:space:]]+PCREL22[[:space:]]+esym\+0x0+20 -0+30[[:space:]]+PCREL22[[:space:]]+esym -0+40[[:space:]]+PCREL22[[:space:]]+esym-0x0+20 - -RELOCATION RECORDS FOR \[\.movl\]: -OFFSET[[:space:]]+TYPE[[:space:]]+VALUE[[:space:]]* -0+11[[:space:]]+PCREL64I[[:space:]]+esym -0+21[[:space:]]+PCREL64I[[:space:]]+esym\+0x0+20 -0+31[[:space:]]+PCREL64I[[:space:]]+esym -0+41[[:space:]]+PCREL64I[[:space:]]+esym-0x0+20 - -RELOCATION RECORDS FOR \[\.data8\]: -OFFSET[[:space:]]+TYPE[[:space:]]+VALUE[[:space:]]* -0+10[[:space:]]+PCREL64[LM]SB[[:space:]]+esym -0+20[[:space:]]+PCREL64[LM]SB[[:space:]]+esym\+0x0+20 -0+30[[:space:]]+PCREL64[LM]SB[[:space:]]+esym -0+40[[:space:]]+PCREL64[LM]SB[[:space:]]+esym-0x0+20 - -RELOCATION RECORDS FOR \[\.data4\]: -OFFSET[[:space:]]+TYPE[[:space:]]+VALUE[[:space:]]* -0+10[[:space:]]+PCREL32[LM]SB[[:space:]]+esym -0+20[[:space:]]+PCREL32[LM]SB[[:space:]]+esym\+0x0+20 -0+30[[:space:]]+PCREL32[LM]SB[[:space:]]+esym -0+40[[:space:]]+PCREL32[LM]SB[[:space:]]+esym-0x0+20 - - -Contents of section \.mov: - 0+00 1d108001 00240000 00020000 00000020 .* - 0+10 1d100000 00240000 00020000 00000020 .* - 0+20 1d100000 00240000 00020000 00000020 .* - 0+30 1d100000 00240000 00020000 00000020 .* - 0+40 1d100000 00240000 00020000 00000020 .* - 0+50 1d100000 00240000 00020000 00000020 .* -Contents of section \.movl: - 0+00 05000000 01000000 00000040 00060060 .* - 0+10 05000000 01000000 00000040 00000060 .* - 0+20 05000000 01000000 00000040 00000060 .* - 0+30 05000000 01000000 00000040 00000060 .* - 0+40 05000000 01000000 00000040 00000060 .* - 0+50 05000000 01000000 00000040 00000060 .* -Contents of section \.data8: - 0+00 [06]0000000 000000[06]0 00000000 00000000 .* - 0+10 00000000 00000000 00000000 00000000 .* - 0+20 00000000 00000000 00000000 00000000 .* - 0+30 00000000 00000000 00000000 00000000 .* - 0+40 00000000 00000000 00000000 00000000 .* - 0+50 00000000 00000000 00000000 00000000 .* -Contents of section \.data4: - 0+00 [06]00000[06]0 00000000 00000000 00000000 .* - 0+10 00000000 00000000 00000000 00000000 .* - 0+20 00000000 00000000 00000000 00000000 .* - 0+30 00000000 00000000 00000000 00000000 .* - 0+40 00000000 00000000 00000000 00000000 .* - 0+50 00000000 00000000 00000000 00000000 .* diff --git a/gas/testsuite/gas/ia64/pcrel.s b/gas/testsuite/gas/ia64/pcrel.s deleted file mode 100644 index d63130a7d93..00000000000 --- a/gas/testsuite/gas/ia64/pcrel.s +++ /dev/null @@ -1,87 +0,0 @@ -.explicit -.global esym - -.altmacro - -.macro begin n, attr - .section .&n, attr, @progbits - .align 16 -_&n: -.endm -.macro end n - .align 16 -_e&n: -.endm - -.macro m1 op, opnd1 - .align 16 - op opnd1 _e&op - _&op -.endm -.macro m2 op, opnd1 - .align 16 - op opnd1 @pcrel(esym) -.endm -.macro m3 op, opnd1 - .align 16 - op opnd1 esym - _&op -.endm -.macro m4 op, opnd1 - .align 16 - op opnd1 esym - . -.endm -.macro m5 op, opnd1 - .align 16 - op opnd1 esym - _e&op -.endm -.macro m6 op, opnd1 - .align 16 - op opnd1 0 -.endm - -begin mov, "ax" - m1 mov, r2 =3D - ;; - m2 mov, r2 =3D - ;; - m3 mov, r2 =3D - ;; - m4 mov, r2 =3D - ;; - m5 mov, r2 =3D - ;; - m6 mov, r2 =3D - ;; -end mov - -begin movl, "ax" - m1 movl, r2 =3D - ;; - m2 movl, r2 =3D - ;; - m3 movl, r2 =3D - ;; - m4 movl, r2 =3D - ;; - m5 movl, r2 =3D - ;; - m6 movl, r2 =3D - ;; -end movl - -begin data8, "a" - m1 data8 - m2 data8 - m3 data8 - m4 data8 - m5 data8 - m6 data8 -end data8 - -begin data4, "a" - m1 data4 - m2 data4 - m3 data4 - m4 data4 - m5 data4 - m6 data4 -end data4 diff --git a/gas/testsuite/gas/ia64/pound.l b/gas/testsuite/gas/ia64/pound.l deleted file mode 100644 index 71f2a4fa253..00000000000 --- a/gas/testsuite/gas/ia64/pound.l +++ /dev/null @@ -1,58 +0,0 @@ -.*: Assembler messages: -.*:35: Warning: .* WAW .* -#... -.*:41: Error: symbol .esym. .* .efunction. -.*:43: Error: section .\.extra. .* .esection. -GAS LISTING .* -#... -[[:space:]]*[[:digit:]]+[[:space:]]+\.explicit -[[:space:]]*[[:digit:]]+[[:space:]]+ -[[:space:]]*[[:digit:]]+[[:space:]]+\.global esym# -[[:space:]]*[[:digit:]]+[[:space:]]+ -[[:space:]]*[[:digit:]]+[[:space:]]+\.section \.extra#, "a", @progbits -[[:space:]]*[[:digit:]]+[[:space:]]+ -[[:space:]]*[[:digit:]]+[[:space:]]+\.text -[[:space:]]*[[:digit:]]+[[:space:]]+ -[[:space:]]*[[:digit:]]+[[:space:]]+ break 0 -[[:space:]]*[[:digit:]]+[[:space:]]+ -[[:space:]]*[[:digit:]]+[[:space:]]+\?*[[:space:]]+[[:xdigit:]]+[[:space:]= ]+\.proc psym -#... -[[:space:]]*[[:digit:]]+[[:space:]]+psym: -[[:space:]]*[[:digit:]]+[[:space:]]+ mov\.ret\.sptk b7 =3D r0, tag# -[[:space:]]*[[:digit:]]+[[:space:]]+ mov r8 =3D 0 -[[:space:]]*[[:digit:]]+[[:space:]]+\[tag:\] br\.ret\.sptk rp -[[:space:]]*[[:digit:]]+[[:space:]]+\?*[[:space:]]+[[:xdigit:]]+[[:space:]= ]+\.endp psym -#... -[[:space:]]*[[:digit:]]+[[:space:]]+ -[[:space:]]*[[:digit:]]+[[:space:]]+\.proc esym# -[[:space:]]*[[:digit:]]+[[:space:]]+\.entry entry# -[[:space:]]*[[:digit:]]+[[:space:]]+esym: -[[:space:]]*[[:digit:]]+[[:space:]]+\.unwentry -[[:space:]]*[[:digit:]]+[[:space:]]+\.personality psym# -[[:space:]]*[[:digit:]]+[[:space:]]+\.regstk 0, 8, 0, 8 -[[:space:]]*[[:digit:]]+[[:space:]]+\.rotp p#\[2\], p1#\[4\] -[[:space:]]*[[:digit:]]+[[:space:]]+\.rotr r#\[2\], r1#\[4\] -[[:space:]]*[[:digit:]]+[[:space:]]+\.reg\.val r#\[1\], 0 -[[:space:]]*[[:digit:]]+[[:space:]]+\.reg\.val r1#\[3\], 0 -[[:space:]]*[[:digit:]]+[[:space:]]+\(p1#\[1\]\) cmp\.eq p\[0\] =3D r\[1\]= , r1#\[1\] -[[:space:]]*[[:digit:]]+[[:space:]]+\(p1#\[3\]\) cmp\.eq p#\[1\] =3D r#\[1= \], r1#\[3\] -[[:space:]]*[[:digit:]]+[[:space:]]+\.pred\.rel "mutex", p#\[0\], p\[1\] -[[:space:]]*[[:digit:]]+[[:space:]]+ nop 0 -[[:space:]]*[[:digit:]]+[[:space:]]+ ;; -[[:space:]]*[[:digit:]]+[[:space:]]+entry: -[[:space:]]*[[:digit:]]+[[:space:]]+\?*[[:space:]]+61828446[[:space:]]+\(p= \[0\]\) mov r8 =3D 1 -[[:space:]]*[[:digit:]]+[[:space:]]+00781509[[:space:]]* -[[:space:]]*[[:digit:]]+[[:space:]]+95007000[[:space:]]* -[[:space:]]*[[:digit:]]+[[:space:]]+00000400[[:space:]]* -[[:space:]]*[[:digit:]]+[[:space:]]+\(p#\[1\]\) mov r8 =3D 0 -[[:space:]]*[[:digit:]]+[[:space:]]+ br\.ret\.sptk rp -[[:space:]]*[[:digit:]]+[[:space:]]+\.xdata4 \.extra#, -1 -[[:space:]]*[[:digit:]]+[[:space:]]+\?*[[:space:]]+11420400+[[:space:]]+\.= endp esym# -[[:space:]]*[[:digit:]]+[[:space:]]+00648400[[:space:]]* -[[:space:]]*[[:digit:]]+[[:space:]]+00004880[[:space:]]* -[[:space:]]*[[:digit:]]+[[:space:]]+00008400[[:space:]]* -#... -[[:space:]]*[[:digit:]]+[[:space:]]+\.alias esym#, "efunction" -[[:space:]]*[[:digit:]]+[[:space:]]+\.alias esym, "efunc" -[[:space:]]*[[:digit:]]+[[:space:]]+\.secalias \.extra#, "esection" -[[:space:]]*[[:digit:]]+[[:space:]]+\.secalias \.extra, "esec" diff --git a/gas/testsuite/gas/ia64/pound.s b/gas/testsuite/gas/ia64/pound.s deleted file mode 100644 index f54c072f5b6..00000000000 --- a/gas/testsuite/gas/ia64/pound.s +++ /dev/null @@ -1,43 +0,0 @@ -.explicit - -.global esym# - -.section .extra#, "a", @progbits - -.text - - break 0 - -.proc psym -psym: - mov.ret.sptk b7 =3D r0, tag# - mov r8 =3D 0 -[tag:] br.ret.sptk rp -.endp psym - -.proc esym# -.entry entry# -esym: -.unwentry -.personality psym# -.regstk 0, 8, 0, 8 -.rotp p#[2], p1#[4] -.rotr r#[2], r1#[4] -.reg.val r#[1], 0 -.reg.val r1#[3], 0 -(p1#[1]) cmp.eq p[0] =3D r[1], r1#[1] -(p1#[3]) cmp.eq p#[1] =3D r#[1], r1#[3] -.pred.rel "mutex", p#[0], p[1] - nop 0 - ;; -entry: -(p[0]) mov r8 =3D 1 -(p#[1]) mov r8 =3D 0 - br.ret.sptk rp -.xdata4 .extra#, -1 -.endp esym# - -.alias esym#, "efunction" -.alias esym, "efunc" -.secalias .extra#, "esection" -.secalias .extra, "esec" diff --git a/gas/testsuite/gas/ia64/pr13167.d b/gas/testsuite/gas/ia64/pr13= 167.d deleted file mode 100644 index 10c98bcc0be..00000000000 --- a/gas/testsuite/gas/ia64/pr13167.d +++ /dev/null @@ -1,43 +0,0 @@ -#readelf: -wl - -Raw dump of debug contents of section \.debug_line: - - Offset: (0x)?0 - Length: 51 - DWARF Version: 3 - Prologue Length: 26 - Minimum Instruction Length: 1 - Initial value of 'is_stmt': 1 - Line Base: -5 - Line Range: 14 - Opcode Base: 13 - - Opcodes: - Opcode 1 has 0 args - Opcode 2 has 1 arg - Opcode 3 has 1 arg - Opcode 4 has 1 arg - Opcode 5 has 1 arg - Opcode 6 has 0 args - Opcode 7 has 0 args - Opcode 8 has 0 args - Opcode 9 has 1 arg - Opcode 10 has 0 args - Opcode 11 has 0 args - Opcode 12 has 1 arg - - The Directory Table is empty\. - - The File Name Table \(offset 0x.*\): - Entry Dir Time Size Name - 1 0 0 0 x\.c - - Line Number Statements: - \[0x.*\] Extended opcode 2: set Address to 0x1 - \[0x.*\] Special opcode 8: advance Address by 0 to 0x1 and Line by 3 to= 4 - \[0x.*\] Special opcode 216: advance Address by 15 to 0x10 and Line by = 1 to 5 - \[0x.*\] Special opcode 228: advance Address by 16 to 0x20 and Line by = -1 to 4 - \[0x.*\] Advance PC by 16 to 0x30 - \[0x.*\] Extended opcode 1: End of Sequence - - diff --git a/gas/testsuite/gas/ia64/pr13167.s b/gas/testsuite/gas/ia64/pr13= 167.s deleted file mode 100644 index 920f11fbca8..00000000000 --- a/gas/testsuite/gas/ia64/pr13167.s +++ /dev/null @@ -1,9 +0,0 @@ - .file 1 "x.c" - mov r1 =3D r35 - .loc 1 4 0 - nop 0 - mov r36 =3D r8 - br.call.sptk.many b0 =3D _U_Qfcnvff_quad_to_sgl# - .loc 1 5 0 - .loc 1 4 0 - mov r1 =3D r35 diff --git a/gas/testsuite/gas/ia64/pred-rel.s b/gas/testsuite/gas/ia64/pre= d-rel.s deleted file mode 100644 index 1316921a6b8..00000000000 --- a/gas/testsuite/gas/ia64/pred-rel.s +++ /dev/null @@ -1,21 +0,0 @@ -// Make sure all forms of .pred.rel are accepted -_start: - .pred.rel "mutex", p1, p2 - .pred.rel "imply", p2, p3 - .pred.rel "clear", p1, p2, p3 - - .pred.rel "mutex" p1, p2 - .pred.rel "imply" p2, p3 - .pred.rel "clear" p1, p2, p3 - - .pred.rel.mutex p1, p2 - .pred.rel.imply p2, p3 - .pred.rel.clear p1, p2, p3 - - .pred.rel @mutex, p1, p2 - .pred.rel @imply, p2, p3 - .pred.rel @clear, p1, p2, p3 - - .pred.rel @mutex p1, p2 - .pred.rel @imply p2, p3 - .pred.rel @clear p1, p2, p3 diff --git a/gas/testsuite/gas/ia64/proc.l b/gas/testsuite/gas/ia64/proc.l deleted file mode 100644 index 60843c1f00b..00000000000 --- a/gas/testsuite/gas/ia64/proc.l +++ /dev/null @@ -1,6 +0,0 @@ -.*: Assembler messages: -.*:4: Error: .* already defined.* -.*:7: Error: .* not defined.* -.*:7: Warning: .* not specified.* -.*:12: Error: Empty argument of .proc -.*:13: Error: Empty argument of .endp diff --git a/gas/testsuite/gas/ia64/proc.s b/gas/testsuite/gas/ia64/proc.s deleted file mode 100644 index 9225a0a01b5..00000000000 --- a/gas/testsuite/gas/ia64/proc.s +++ /dev/null @@ -1,13 +0,0 @@ -func1:: - br.ret.sptk rp - -.proc func, func1, func2 -func:: - br.ret.sptk rp -.endp func, func1, func2 - -func2:: - br.ret.sptk rp - -.proc -.endp diff --git a/gas/testsuite/gas/ia64/pseudo.d b/gas/testsuite/gas/ia64/pseud= o.d deleted file mode 100644 index 3dd85059474..00000000000 --- a/gas/testsuite/gas/ia64/pseudo.d +++ /dev/null @@ -1,29 +0,0 @@ -# as: -xnone -mtune=3Ditanium1 -# objdump: -d -# name: ia64 pseudo-ops - -.*: +file format .* - -Disassembly of section \.text: - -0+0 <_start>: -[[:space:]]*[[:xdigit:]]*:[[:space:][:xdigit:]]+(\[[[:upper:]]+\])?[[:spac= e:]]+alloc r8=3Dar\.pfs,0,0,0 -[[:space:]]*[[:xdigit:]]*:[[:space:][:xdigit:]]+(\[[[:upper:]]+\])?[[:spac= e:]]+cmp\.eq p6,p0=3Dr0,r0 -[[:space:]]*[[:xdigit:]]*:[[:space:][:xdigit:]]+(\[[[:upper:]]+\])?[[:spac= e:]]+cmp\.eq p7,p0=3D0,r0 -[[:space:]]*[[:xdigit:]]*:[[:space:][:xdigit:]]+(\[[[:upper:]]+\])?[[:spac= e:]]+cmp4\.eq p8,p0=3Dr0,r0 -[[:space:]]*[[:xdigit:]]*:[[:space:][:xdigit:]]+(\[[[:upper:]]+\])?[[:spac= e:]]+nop\.. 0x0 -[[:space:]]*[[:xdigit:]]*:[[:space:][:xdigit:]]+(\[[[:upper:]]+\])?[[:spac= e:]]+cmp4\.eq p9,p0=3D0,r0 -[[:space:]]*[[:xdigit:]]*:[[:space:][:xdigit:]]+(\[[[:upper:]]+\])?[[:spac= e:]]+cmp8xchg16\.acq r9=3D\[r0\],r0,ar\.csd,ar\.ccv -[[:space:]]*[[:xdigit:]]*:[[:space:][:xdigit:]]+(\[[[:upper:]]+\])?[[:spac= e:]]+cmpxchg4\.acq r10=3D\[r0\],r0,ar\.ccv -[[:space:]]*[[:xdigit:]]*:[[:space:][:xdigit:]]+(\[[[:upper:]]+\])?[[:spac= e:]]+fclass\.m p10,p0=3Df0,0x1 -[[:space:]]*[[:xdigit:]]*:[[:space:][:xdigit:]]+(\[[[:upper:]]+\])?[[:spac= e:]]+nop\.. 0x0 -[[:space:]]*[[:xdigit:]]*:[[:space:][:xdigit:]]+(\[[[:upper:]]+\])?[[:spac= e:]]+fcmp\.eq\.s0 p11,p0=3Df0,f0 -[[:space:]]*[[:xdigit:]]*:[[:space:][:xdigit:]]+(\[[[:upper:]]+\])?[[:spac= e:]]+nop\.. 0x0 -[[:space:]]*[[:xdigit:]]*:[[:space:][:xdigit:]]+(\[[[:upper:]]+\])?[[:spac= e:]]+ld16 r11,ar\.csd=3D\[r0\] -[[:space:]]*[[:xdigit:]]*:[[:space:][:xdigit:]]+(\[[[:upper:]]+\])?[[:spac= e:]]+nop\.. 0x0 -[[:space:]]*[[:xdigit:]]*:[[:space:][:xdigit:]]+(\[[[:upper:]]+\])?[[:spac= e:]]+mov pr=3Dr0,0xfffffffffffffffe -[[:space:]]*[[:xdigit:]]*:[[:space:][:xdigit:]]+(\[[[:upper:]]+\])?[[:spac= e:]]+st16 \[r0\]=3Dr0,ar\.csd -[[:space:]]*[[:xdigit:]]*:[[:space:][:xdigit:]]+(\[[[:upper:]]+\])?[[:spac= e:]]+tbit\.z p0,p12=3Dr0,0 -[[:space:]]*[[:xdigit:]]*:[[:space:][:xdigit:]]+(\[[[:upper:]]+\])?[[:spac= e:]]+tnat\.z p0,p13=3Dr0(;;)? -#... -[[:space:]]*[[:xdigit:]]*:[[:space:][:xdigit:]]+(\[[[:upper:]]+\])?[[:spac= e:]]+tf\.z p3,p2=3D33(;;)? diff --git a/gas/testsuite/gas/ia64/pseudo.s b/gas/testsuite/gas/ia64/pseud= o.s deleted file mode 100644 index 06326c172eb..00000000000 --- a/gas/testsuite/gas/ia64/pseudo.s +++ /dev/null @@ -1,19 +0,0 @@ -_start: - alloc r8 =3D 0, 0, 0, 0 - cmp.eq p6 =3D r0, r0 - cmp.eq p7 =3D 0, r0 - cmp4.eq p8 =3D r0, r0 - cmp4.eq p9 =3D 0, r0 - cmp8xchg16.acq r9 =3D [r0], r0 - cmpxchg4.acq r10 =3D [r0], r0 - fclass.m p10 =3D f0, @pos - fcmp.eq p11 =3D f0, f0 - ld16 r11 =3D [r0] - mov pr =3D r0 - st16 [r0] =3D r0 - tbit.nz p12 =3D r0, 0 - tnat.nz p13 =3D r0 - - # instructions added by SDM2.2: - - tf.nz p2, p3 =3D 33 diff --git a/gas/testsuite/gas/ia64/psn.d b/gas/testsuite/gas/ia64/psn.d deleted file mode 100644 index c496cb38379..00000000000 --- a/gas/testsuite/gas/ia64/psn.d +++ /dev/null @@ -1,1467 +0,0 @@ -# as: -xnone -W=20 -# objdump: -d -# name: ia64 psn=20 - -.*: +file format elf..-ia64.* - -Disassembly of section \.text: - -0+000 : - 0: 08 00 04 05 60 19 \[MMI\] lfetch.count \[r2\],1,64 - 6: 40 f8 5a c0 32 00 lfetch.count \[r22\],5,-64 - c: 00 00 04 00 nop.i 0x0 - 10: 08 40 3c 2f 62 19 \[MMI\] lfetch.count.nt1 \[r23\],9,960 - 16: b0 80 ea c5 32 00 lfetch.count.nt1 \[r122\],12,-1024 - 1c: 00 00 04 00 nop.i 0x0 - 20: 08 78 08 0b 64 19 \[MMI\] lfetch.count.nt2 \[r5\],16,128 - 26: 30 e1 3e c8 32 00 lfetch.count.nt2 \[r15\],20,-256 - 2c: 00 00 04 00 nop.i 0x0 - 30: 08 b8 20 fb 66 19 \[MMI\] lfetch.count.nta \[r125\],24,512 - 36: c0 79 22 cc 32 00 lfetch.count.nta \[r8\],29,960 - 3c: 00 00 04 00 nop.i 0x0 - 40: 08 08 43 25 60 19 \[MMI\] lfetch.count.d4 \[r18\],34,-1024 - 46: d0 77 fe c5 32 00 lfetch.count.d5 \[r127\],62,896 - 4c: 00 00 04 00 nop.i 0x0 - 50: 09 f0 43 15 64 19 \[MMI\] lfetch.count.d6 \[r10\],63,-1024 - 56: f0 07 82 cd 32 20 lfetch.count.d7 \[r96\],64,0 - 5c: 10 04 08 50 tf.z p1,p2=3D32;; - 60: 02 00 00 00 01 00 \[MII\] nop.m 0x0 - 66: 20 08 02 0e 28 60 tf.z p2,p7=3D32;; - 6c: 18 04 08 50 tf.z.unc p3,p2=3D32 - 70: 00 00 00 00 01 00 \[MII\] nop.m 0x0 - 76: 40 18 02 06 28 a0 tf.z p4,p3=3D33 - 7c: 50 04 10 58 tf.z.and p5,p4=3D34 - 80: 00 00 00 00 01 00 \[MII\] nop.m 0x0 - 86: 50 3c 02 0c 2c c0 tf.nz.and p5,p6=3D35 - 8c: 70 04 14 58 tf.z.and p6,p5=3D35 - 90: 00 00 00 00 01 00 \[MII\] nop.m 0x0 - 96: 70 f8 03 8c 28 a0 tf.z.or p7,p6=3D63 - 9c: 78 04 18 51 tf.nz.or p5,p6=3D35 - a0: 00 00 00 00 01 00 \[MII\] nop.m 0x0 - a6: 70 18 02 8c 2c e0 tf.z.or.andcm p7,p6=3D33 - ac: 58 04 18 59 tf.nz.or.andcm p7,p6=3D34 - b0: 00 00 00 00 01 00 \[MII\] nop.m 0x0 - b6: 60 0c 02 8e 2c c0 tf.nz.or.andcm p6,p7=3D32 - bc: 30 04 1c 59 tf.z.or.andcm p6,p7=3D33 - c0: 11 00 00 00 01 00 \[MIB\] nop.m 0x0 - c6: 00 1c 02 0c 28 00 tf.z.unc p0,p6=3D33 - cc: 00 00 00 20 nop.b 0x0;; - d0: 08 00 02 24 60 19 \[MMI\] lfetch.d4 \[r18\] - d6: 00 00 00 02 00 00 nop.m 0x0 - dc: 00 00 04 00 nop.i 0x0 - e0: 0a 00 02 26 7e 19 \[MMI\] lfetch.fault.excl.d7 \[r19\];; - e6: 10 10 3a c0 32 00 lfetch.count \[r14\],2,128 - ec: 01 50 58 00 sxt4 r8=3Dr10 - f0: 0a f8 13 17 60 19 \[MMI\] lfetch.count.d4 \[r11\],64,256;; - f6: 00 04 44 d4 32 00 lfetch.excl.d5 \[r17\] - fc: 00 00 04 00 nop.i 0x0 - 100: 0b 00 02 20 74 19 \[MMI\] lfetch.fault.d6 \[r16\];; - 106: 70 01 e0 03 00 60 mov dahr7=3D7 - 10c: 00 48 68 73 clz r3=3Dr9;; - 110: 00 b0 00 e0 01 00 \[MII\] mov dahr6=3D6 - 116: 20 48 20 34 3c 40 mpy4 r2=3Dr9,r8 - 11c: 90 40 78 78 mpyshl4 r2=3Dr9,r8 - 120: 0b a8 00 d0 01 00 \[MMI\] mov dahr5=3D5;; - 126: 40 01 80 03 00 00 mov dahr4=3D4 - 12c: 00 00 04 00 nop.i 0x0;; - 130: 11 98 00 b0 01 00 \[MIB\] mov dahr3=3D3 - 136: 80 10 0c 00 40 00 add r8=3Dr2,r3 - 13c: 00 00 00 20 nop.b 0x0;; - 140: 0b 90 00 a0 01 00 \[MMI\] mov dahr2=3D2;; - 146: 10 01 20 03 00 00 mov dahr1=3D1 - 14c: 00 00 04 00 nop.i 0x0;; - 150: 10 80 00 80 01 00 \[MIB\] mov dahr0=3D0 - 156: 00 00 00 02 00 00 nop.i 0x0 - 15c: 00 00 00 20 nop.b 0x0 - 160: 08 60 00 0a 20 04 \[MMI\] mov r12=3Ddahr\[r5\] - 166: a0 07 dc 40 08 00 mov r122=3Ddahr\[r55\] - 16c: 00 00 04 00 nop.i 0x0 - 170: 08 00 74 83 80 11 \[MMI\] st1 \[r65\]=3Dr93 - 176: 00 e8 06 05 23 00 st1.d1 \[r65\]=3Dr93 - 17c: 00 00 04 00 nop.i 0x0 - 180: 08 00 74 83 82 11 \[MMI\] st1.d1 \[r65\]=3Dr93 - 186: 00 e8 06 09 23 00 st1.d2 \[r65\]=3Dr93 - 18c: 00 00 04 00 nop.i 0x0 - 190: 08 00 74 83 84 11 \[MMI\] st1.d2 \[r65\]=3Dr93 - 196: 00 e8 06 0d 23 00 st1.nta \[r65\]=3Dr93 - 19c: 00 00 04 00 nop.i 0x0 - 1a0: 08 00 74 83 86 11 \[MMI\] st1.nta \[r65\]=3Dr93 - 1a6: 00 ec 06 01 23 00 st1.d4 \[r65\]=3Dr93 - 1ac: 00 00 04 00 nop.i 0x0 - 1b0: 08 00 76 83 82 11 \[MMI\] st1.d5 \[r65\]=3Dr93 - 1b6: 00 ec 06 09 23 00 st1.d6 \[r65\]=3Dr93 - 1bc: 00 00 04 00 nop.i 0x0 - 1c0: 08 00 76 83 86 11 \[MMI\] st1.d7 \[r65\]=3Dr93 - 1c6: 00 e8 06 11 23 00 st2 \[r65\]=3Dr93 - 1cc: 00 00 04 00 nop.i 0x0 - 1d0: 08 00 74 83 8a 11 \[MMI\] st2.d1 \[r65\]=3Dr93 - 1d6: 00 e8 06 15 23 00 st2.d1 \[r65\]=3Dr93 - 1dc: 00 00 04 00 nop.i 0x0 - 1e0: 08 00 74 83 8c 11 \[MMI\] st2.d2 \[r65\]=3Dr93 - 1e6: 00 e8 06 19 23 00 st2.d2 \[r65\]=3Dr93 - 1ec: 00 00 04 00 nop.i 0x0 - 1f0: 08 00 74 83 8e 11 \[MMI\] st2.nta \[r65\]=3Dr93 - 1f6: 00 e8 06 1d 23 00 st2.nta \[r65\]=3Dr93 - 1fc: 00 00 04 00 nop.i 0x0 - 200: 08 00 76 83 88 11 \[MMI\] st2.d4 \[r65\]=3Dr93 - 206: 00 ec 06 15 23 00 st2.d5 \[r65\]=3Dr93 - 20c: 00 00 04 00 nop.i 0x0 - 210: 08 00 76 83 8c 11 \[MMI\] st2.d6 \[r65\]=3Dr93 - 216: 00 ec 06 1d 23 00 st2.d7 \[r65\]=3Dr93 - 21c: 00 00 04 00 nop.i 0x0 - 220: 08 00 74 83 90 11 \[MMI\] st4 \[r65\]=3Dr93 - 226: 00 e8 06 25 23 00 st4.d1 \[r65\]=3Dr93 - 22c: 00 00 04 00 nop.i 0x0 - 230: 08 00 74 83 92 11 \[MMI\] st4.d1 \[r65\]=3Dr93 - 236: 00 e8 06 29 23 00 st4.d2 \[r65\]=3Dr93 - 23c: 00 00 04 00 nop.i 0x0 - 240: 08 00 74 83 94 11 \[MMI\] st4.d2 \[r65\]=3Dr93 - 246: 00 e8 06 2d 23 00 st4.nta \[r65\]=3Dr93 - 24c: 00 00 04 00 nop.i 0x0 - 250: 08 00 74 83 96 11 \[MMI\] st4.nta \[r65\]=3Dr93 - 256: 00 ec 06 21 23 00 st4.d4 \[r65\]=3Dr93 - 25c: 00 00 04 00 nop.i 0x0 - 260: 08 00 76 83 92 11 \[MMI\] st4.d5 \[r65\]=3Dr93 - 266: 00 ec 06 29 23 00 st4.d6 \[r65\]=3Dr93 - 26c: 00 00 04 00 nop.i 0x0 - 270: 08 00 76 83 96 11 \[MMI\] st4.d7 \[r65\]=3Dr93 - 276: 00 e8 06 31 23 00 st8 \[r65\]=3Dr93 - 27c: 00 00 04 00 nop.i 0x0 - 280: 08 00 74 83 9a 11 \[MMI\] st8.d1 \[r65\]=3Dr93 - 286: 00 e8 06 35 23 00 st8.d1 \[r65\]=3Dr93 - 28c: 00 00 04 00 nop.i 0x0 - 290: 08 00 74 83 9c 11 \[MMI\] st8.d2 \[r65\]=3Dr93 - 296: 00 e8 06 39 23 00 st8.d2 \[r65\]=3Dr93 - 29c: 00 00 04 00 nop.i 0x0 - 2a0: 08 00 74 83 9e 11 \[MMI\] st8.nta \[r65\]=3Dr93 - 2a6: 00 e8 06 3d 23 00 st8.nta \[r65\]=3Dr93 - 2ac: 00 00 04 00 nop.i 0x0 - 2b0: 08 00 76 83 98 11 \[MMI\] st8.d4 \[r65\]=3Dr93 - 2b6: 00 ec 06 35 23 00 st8.d5 \[r65\]=3Dr93 - 2bc: 00 00 04 00 nop.i 0x0 - 2c0: 08 00 76 83 9c 11 \[MMI\] st8.d6 \[r65\]=3Dr93 - 2c6: 00 ec 06 3d 23 00 st8.d7 \[r65\]=3Dr93 - 2cc: 00 00 04 00 nop.i 0x0 - 2d0: 08 00 74 83 81 11 \[MMI\] st16 \[r65\]=3Dr93,ar.csd - 2d6: 00 e8 06 03 23 00 st16 \[r65\]=3Dr93,ar.csd - 2dc: 00 00 04 00 nop.i 0x0 - 2e0: 08 00 74 83 83 11 \[MMI\] st16.d1 \[r65\]=3Dr93,ar.csd - 2e6: 00 e8 06 07 23 00 st16.d1 \[r65\]=3Dr93,ar.csd - 2ec: 00 00 04 00 nop.i 0x0 - 2f0: 08 00 74 83 85 11 \[MMI\] st16.d2 \[r65\]=3Dr93,ar.csd - 2f6: 00 e8 06 0b 23 00 st16.d2 \[r65\]=3Dr93,ar.csd - 2fc: 00 00 04 00 nop.i 0x0 - 300: 08 00 74 83 87 11 \[MMI\] st16.nta \[r65\]=3Dr93,ar.csd - 306: 00 e8 06 0f 23 00 st16.nta \[r65\]=3Dr93,ar.csd - 30c: 00 00 04 00 nop.i 0x0 - 310: 08 00 76 83 81 11 \[MMI\] st16.d4 \[r65\]=3Dr93,ar.csd - 316: 00 ec 06 07 23 00 st16.d5 \[r65\]=3Dr93,ar.csd - 31c: 00 00 04 00 nop.i 0x0 - 320: 08 00 76 83 85 11 \[MMI\] st16.d6 \[r65\]=3Dr93,ar.csd - 326: 00 ec 06 0f 23 00 st16.d7 \[r65\]=3Dr93,ar.csd - 32c: 00 00 04 00 nop.i 0x0 - 330: 08 00 74 83 87 11 \[MMI\] st16.nta \[r65\]=3Dr93,ar.csd - 336: 00 e8 06 0f 23 00 st16.nta \[r65\]=3Dr93,ar.csd - 33c: 00 00 04 00 nop.i 0x0 - 340: 08 00 76 83 81 11 \[MMI\] st16.d4 \[r65\]=3Dr93,ar.csd - 346: 00 ec 06 07 23 00 st16.d5 \[r65\]=3Dr93,ar.csd - 34c: 00 00 04 00 nop.i 0x0 - 350: 08 00 76 83 85 11 \[MMI\] st16.d6 \[r65\]=3Dr93,ar.csd - 356: 00 ec 06 0f 23 00 st16.d7 \[r65\]=3Dr93,ar.csd - 35c: 00 00 04 00 nop.i 0x0 - 360: 08 00 74 83 a0 11 \[MMI\] st1.rel \[r65\]=3Dr93 - 366: 00 e8 06 45 23 00 st1.rel.d1 \[r65\]=3Dr93 - 36c: 00 00 04 00 nop.i 0x0 - 370: 08 00 74 83 a2 11 \[MMI\] st1.rel.d1 \[r65\]=3Dr93 - 376: 00 e8 06 49 23 00 st1.rel.d2 \[r65\]=3Dr93 - 37c: 00 00 04 00 nop.i 0x0 - 380: 08 00 74 83 a4 11 \[MMI\] st1.rel.d2 \[r65\]=3Dr93 - 386: 00 e8 06 4d 23 00 st1.rel.nta \[r65\]=3Dr93 - 38c: 00 00 04 00 nop.i 0x0 - 390: 08 00 74 83 a6 11 \[MMI\] st1.rel.nta \[r65\]=3Dr93 - 396: 00 ec 06 41 23 00 st1.rel.d4 \[r65\]=3Dr93 - 39c: 00 00 04 00 nop.i 0x0 - 3a0: 08 00 76 83 a2 11 \[MMI\] st1.rel.d5 \[r65\]=3Dr93 - 3a6: 00 ec 06 49 23 00 st1.rel.d6 \[r65\]=3Dr93 - 3ac: 00 00 04 00 nop.i 0x0 - 3b0: 08 00 76 83 a6 11 \[MMI\] st1.rel.d7 \[r65\]=3Dr93 - 3b6: 00 e8 06 51 23 00 st2.rel \[r65\]=3Dr93 - 3bc: 00 00 04 00 nop.i 0x0 - 3c0: 08 00 74 83 aa 11 \[MMI\] st2.rel.d1 \[r65\]=3Dr93 - 3c6: 00 e8 06 55 23 00 st2.rel.d1 \[r65\]=3Dr93 - 3cc: 00 00 04 00 nop.i 0x0 - 3d0: 08 00 74 83 ac 11 \[MMI\] st2.rel.d2 \[r65\]=3Dr93 - 3d6: 00 e8 06 59 23 00 st2.rel.d2 \[r65\]=3Dr93 - 3dc: 00 00 04 00 nop.i 0x0 - 3e0: 08 00 74 83 ae 11 \[MMI\] st2.rel.nta \[r65\]=3Dr93 - 3e6: 00 e8 06 5d 23 00 st2.rel.nta \[r65\]=3Dr93 - 3ec: 00 00 04 00 nop.i 0x0 - 3f0: 08 00 76 83 a8 11 \[MMI\] st2.rel.d4 \[r65\]=3Dr93 - 3f6: 00 ec 06 55 23 00 st2.rel.d5 \[r65\]=3Dr93 - 3fc: 00 00 04 00 nop.i 0x0 - 400: 08 00 76 83 ac 11 \[MMI\] st2.rel.d6 \[r65\]=3Dr93 - 406: 00 ec 06 5d 23 00 st2.rel.d7 \[r65\]=3Dr93 - 40c: 00 00 04 00 nop.i 0x0 - 410: 08 00 74 83 b0 11 \[MMI\] st4.rel \[r65\]=3Dr93 - 416: 00 e8 06 65 23 00 st4.rel.d1 \[r65\]=3Dr93 - 41c: 00 00 04 00 nop.i 0x0 - 420: 08 00 74 83 b2 11 \[MMI\] st4.rel.d1 \[r65\]=3Dr93 - 426: 00 e8 06 69 23 00 st4.rel.d2 \[r65\]=3Dr93 - 42c: 00 00 04 00 nop.i 0x0 - 430: 08 00 74 83 b4 11 \[MMI\] st4.rel.d2 \[r65\]=3Dr93 - 436: 00 e8 06 6d 23 00 st4.rel.nta \[r65\]=3Dr93 - 43c: 00 00 04 00 nop.i 0x0 - 440: 08 00 74 83 b6 11 \[MMI\] st4.rel.nta \[r65\]=3Dr93 - 446: 00 ec 06 61 23 00 st4.rel.d4 \[r65\]=3Dr93 - 44c: 00 00 04 00 nop.i 0x0 - 450: 08 00 76 83 b2 11 \[MMI\] st4.rel.d5 \[r65\]=3Dr93 - 456: 00 ec 06 69 23 00 st4.rel.d6 \[r65\]=3Dr93 - 45c: 00 00 04 00 nop.i 0x0 - 460: 08 00 76 83 b6 11 \[MMI\] st4.rel.d7 \[r65\]=3Dr93 - 466: 00 e8 06 71 23 00 st8.rel \[r65\]=3Dr93 - 46c: 00 00 04 00 nop.i 0x0 - 470: 08 00 74 83 ba 11 \[MMI\] st8.rel.d1 \[r65\]=3Dr93 - 476: 00 e8 06 75 23 00 st8.rel.d1 \[r65\]=3Dr93 - 47c: 00 00 04 00 nop.i 0x0 - 480: 08 00 74 83 bc 11 \[MMI\] st8.rel.d2 \[r65\]=3Dr93 - 486: 00 e8 06 79 23 00 st8.rel.d2 \[r65\]=3Dr93 - 48c: 00 00 04 00 nop.i 0x0 - 490: 08 00 74 83 be 11 \[MMI\] st8.rel.nta \[r65\]=3Dr93 - 496: 00 e8 06 7d 23 00 st8.rel.nta \[r65\]=3Dr93 - 49c: 00 00 04 00 nop.i 0x0 - 4a0: 08 00 76 83 b8 11 \[MMI\] st8.rel.d4 \[r65\]=3Dr93 - 4a6: 00 ec 06 75 23 00 st8.rel.d5 \[r65\]=3Dr93 - 4ac: 00 00 04 00 nop.i 0x0 - 4b0: 08 00 76 83 bc 11 \[MMI\] st8.rel.d6 \[r65\]=3Dr93 - 4b6: 00 ec 06 7d 23 00 st8.rel.d7 \[r65\]=3Dr93 - 4bc: 00 00 04 00 nop.i 0x0 - 4c0: 08 00 74 83 a1 11 \[MMI\] st16.rel \[r65\]=3Dr93,ar.csd - 4c6: 00 e8 06 43 23 00 st16.rel \[r65\]=3Dr93,ar.csd - 4cc: 00 00 04 00 nop.i 0x0 - 4d0: 08 00 74 83 a3 11 \[MMI\] st16.rel.d1 \[r65\]=3Dr93,ar.csd - 4d6: 00 e8 06 47 23 00 st16.rel.d1 \[r65\]=3Dr93,ar.csd - 4dc: 00 00 04 00 nop.i 0x0 - 4e0: 08 00 74 83 a3 11 \[MMI\] st16.rel.d1 \[r65\]=3Dr93,ar.csd - 4e6: 00 e8 06 47 23 00 st16.rel.d1 \[r65\]=3Dr93,ar.csd - 4ec: 00 00 04 00 nop.i 0x0 - 4f0: 08 00 74 83 a5 11 \[MMI\] st16.rel.d2 \[r65\]=3Dr93,ar.csd - 4f6: 00 e8 06 4b 23 00 st16.rel.d2 \[r65\]=3Dr93,ar.csd - 4fc: 00 00 04 00 nop.i 0x0 - 500: 08 00 74 83 a5 11 \[MMI\] st16.rel.d2 \[r65\]=3Dr93,ar.csd - 506: 00 e8 06 4b 23 00 st16.rel.d2 \[r65\]=3Dr93,ar.csd - 50c: 00 00 04 00 nop.i 0x0 - 510: 08 00 74 83 a7 11 \[MMI\] st16.rel.nta \[r65\]=3Dr93,ar.c= sd - 516: 00 e8 06 4f 23 00 st16.rel.nta \[r65\]=3Dr93,ar.csd - 51c: 00 00 04 00 nop.i 0x0 - 520: 08 00 76 83 a1 11 \[MMI\] st16.rel.d4 \[r65\]=3Dr93,ar.csd - 526: 00 ec 06 47 23 00 st16.rel.d5 \[r65\]=3Dr93,ar.csd - 52c: 00 00 04 00 nop.i 0x0 - 530: 08 00 76 83 a5 11 \[MMI\] st16.rel.d6 \[r65\]=3Dr93,ar.csd - 536: 00 ec 06 4f 23 00 st16.rel.d7 \[r65\]=3Dr93,ar.csd - 53c: 00 00 04 00 nop.i 0x0 - 540: 08 00 74 83 a7 11 \[MMI\] st16.rel.nta \[r65\]=3Dr93,ar.c= sd - 546: 00 e8 06 4f 23 00 st16.rel.nta \[r65\]=3Dr93,ar.csd - 54c: 00 00 04 00 nop.i 0x0 - 550: 08 00 76 83 a1 11 \[MMI\] st16.rel.d4 \[r65\]=3Dr93,ar.csd - 556: 00 ec 06 47 23 00 st16.rel.d5 \[r65\]=3Dr93,ar.csd - 55c: 00 00 04 00 nop.i 0x0 - 560: 08 00 76 83 a5 11 \[MMI\] st16.rel.d6 \[r65\]=3Dr93,ar.csd - 566: 00 ec 06 4f 23 00 st16.rel.d7 \[r65\]=3Dr93,ar.csd - 56c: 00 00 04 00 nop.i 0x0 - 570: 08 00 74 83 d8 11 \[MMI\] st8.spill \[r65\]=3Dr93 - 576: 00 e8 06 b5 23 00 st8.spill.d1 \[r65\]=3Dr93 - 57c: 00 00 04 00 nop.i 0x0 - 580: 08 00 74 83 da 11 \[MMI\] st8.spill.d1 \[r65\]=3Dr93 - 586: 00 e8 06 b9 23 00 st8.spill.d2 \[r65\]=3Dr93 - 58c: 00 00 04 00 nop.i 0x0 - 590: 08 00 74 83 dc 11 \[MMI\] st8.spill.d2 \[r65\]=3Dr93 - 596: 00 e8 06 bd 23 00 st8.spill.nta \[r65\]=3Dr93 - 59c: 00 00 04 00 nop.i 0x0 - 5a0: 08 00 74 83 de 11 \[MMI\] st8.spill.nta \[r65\]=3Dr93 - 5a6: 00 ec 06 b1 23 00 st8.spill.d4 \[r65\]=3Dr93 - 5ac: 00 00 04 00 nop.i 0x0 - 5b0: 08 00 76 83 da 11 \[MMI\] st8.spill.d5 \[r65\]=3Dr93 - 5b6: 00 ec 06 b9 23 00 st8.spill.d6 \[r65\]=3Dr93 - 5bc: 00 00 04 00 nop.i 0x0 - 5c0: 08 00 76 83 de 11 \[MMI\] st8.spill.d7 \[r65\]=3Dr93 - 5c6: 00 00 f0 c0 32 00 lfetch \[r60\] - 5cc: 00 00 04 00 nop.i 0x0 - 5d0: 08 00 00 78 62 19 \[MMI\] lfetch.nt1 \[r60\] - 5d6: 00 00 f0 c4 32 00 lfetch.nt1 \[r60\] - 5dc: 00 00 04 00 nop.i 0x0 - 5e0: 08 00 00 78 64 19 \[MMI\] lfetch.nt2 \[r60\] - 5e6: 00 00 f0 c8 32 00 lfetch.nt2 \[r60\] - 5ec: 00 00 04 00 nop.i 0x0 - 5f0: 08 00 00 78 66 19 \[MMI\] lfetch.nta \[r60\] - 5f6: 00 00 f0 cc 32 00 lfetch.nta \[r60\] - 5fc: 00 00 04 00 nop.i 0x0 - 600: 08 00 02 78 60 19 \[MMI\] lfetch.d4 \[r60\] - 606: 00 04 f0 c4 32 00 lfetch.d5 \[r60\] - 60c: 00 00 04 00 nop.i 0x0 - 610: 08 00 02 78 64 19 \[MMI\] lfetch.d6 \[r60\] - 616: 00 04 f0 cc 32 00 lfetch.d7 \[r60\] - 61c: 00 00 04 00 nop.i 0x0 - 620: 08 00 68 79 90 19 \[MMI\] stfs \[r60\]=3Df90 - 626: 00 d0 f2 24 33 00 stfs.d1 \[r60\]=3Df90 - 62c: 00 00 04 00 nop.i 0x0 - 630: 08 00 68 79 92 19 \[MMI\] stfs.d1 \[r60\]=3Df90 - 636: 00 d0 f2 28 33 00 stfs.d2 \[r60\]=3Df90 - 63c: 00 00 04 00 nop.i 0x0 - 640: 08 00 68 79 94 19 \[MMI\] stfs.d2 \[r60\]=3Df90 - 646: 00 d0 f2 2c 33 00 stfs.nta \[r60\]=3Df90 - 64c: 00 00 04 00 nop.i 0x0 - 650: 08 00 68 79 96 19 \[MMI\] stfs.nta \[r60\]=3Df90 - 656: 00 d4 f2 20 33 00 stfs.d4 \[r60\]=3Df90 - 65c: 00 00 04 00 nop.i 0x0 - 660: 08 00 6a 79 92 19 \[MMI\] stfs.d5 \[r60\]=3Df90 - 666: 00 d4 f2 28 33 00 stfs.d6 \[r60\]=3Df90 - 66c: 00 00 04 00 nop.i 0x0 - 670: 08 00 6a 79 96 19 \[MMI\] stfs.d7 \[r60\]=3Df90 - 676: 00 d0 f2 30 33 00 stfd \[r60\]=3Df90 - 67c: 00 00 04 00 nop.i 0x0 - 680: 08 00 68 79 9a 19 \[MMI\] stfd.d1 \[r60\]=3Df90 - 686: 00 d0 f2 34 33 00 stfd.d1 \[r60\]=3Df90 - 68c: 00 00 04 00 nop.i 0x0 - 690: 08 00 68 79 9c 19 \[MMI\] stfd.d2 \[r60\]=3Df90 - 696: 00 d0 f2 38 33 00 stfd.d2 \[r60\]=3Df90 - 69c: 00 00 04 00 nop.i 0x0 - 6a0: 08 00 68 79 9e 19 \[MMI\] stfd.nta \[r60\]=3Df90 - 6a6: 00 d0 f2 3c 33 00 stfd.nta \[r60\]=3Df90 - 6ac: 00 00 04 00 nop.i 0x0 - 6b0: 08 00 6a 79 98 19 \[MMI\] stfd.d4 \[r60\]=3Df90 - 6b6: 00 d4 f2 34 33 00 stfd.d5 \[r60\]=3Df90 - 6bc: 00 00 04 00 nop.i 0x0 - 6c0: 08 00 6a 79 9c 19 \[MMI\] stfd.d6 \[r60\]=3Df90 - 6c6: 00 d4 f2 3c 33 00 stfd.d7 \[r60\]=3Df90 - 6cc: 00 00 04 00 nop.i 0x0 - 6d0: 08 00 68 79 88 19 \[MMI\] stf8 \[r60\]=3Df90 - 6d6: 00 d0 f2 14 33 00 stf8.d1 \[r60\]=3Df90 - 6dc: 00 00 04 00 nop.i 0x0 - 6e0: 08 00 68 79 8a 19 \[MMI\] stf8.d1 \[r60\]=3Df90 - 6e6: 00 d0 f2 18 33 00 stf8.d2 \[r60\]=3Df90 - 6ec: 00 00 04 00 nop.i 0x0 - 6f0: 08 00 68 79 8c 19 \[MMI\] stf8.d2 \[r60\]=3Df90 - 6f6: 00 d0 f2 1c 33 00 stf8.nta \[r60\]=3Df90 - 6fc: 00 00 04 00 nop.i 0x0 - 700: 08 00 68 79 8e 19 \[MMI\] stf8.nta \[r60\]=3Df90 - 706: 00 d4 f2 10 33 00 stf8.d4 \[r60\]=3Df90 - 70c: 00 00 04 00 nop.i 0x0 - 710: 08 00 6a 79 8a 19 \[MMI\] stf8.d5 \[r60\]=3Df90 - 716: 00 d4 f2 18 33 00 stf8.d6 \[r60\]=3Df90 - 71c: 00 00 04 00 nop.i 0x0 - 720: 08 00 6a 79 8e 19 \[MMI\] stf8.d7 \[r60\]=3Df90 - 726: 00 d0 f2 00 33 00 stfe \[r60\]=3Df90 - 72c: 00 00 04 00 nop.i 0x0 - 730: 08 00 68 79 82 19 \[MMI\] stfe.d1 \[r60\]=3Df90 - 736: 00 d0 f2 04 33 00 stfe.d1 \[r60\]=3Df90 - 73c: 00 00 04 00 nop.i 0x0 - 740: 08 00 68 79 84 19 \[MMI\] stfe.d2 \[r60\]=3Df90 - 746: 00 d0 f2 08 33 00 stfe.d2 \[r60\]=3Df90 - 74c: 00 00 04 00 nop.i 0x0 - 750: 08 00 68 79 86 19 \[MMI\] stfe.nta \[r60\]=3Df90 - 756: 00 d0 f2 0c 33 00 stfe.nta \[r60\]=3Df90 - 75c: 00 00 04 00 nop.i 0x0 - 760: 08 00 6a 79 80 19 \[MMI\] stfe.d4 \[r60\]=3Df90 - 766: 00 d4 f2 04 33 00 stfe.d5 \[r60\]=3Df90 - 76c: 00 00 04 00 nop.i 0x0 - 770: 08 00 6a 79 84 19 \[MMI\] stfe.d6 \[r60\]=3Df90 - 776: 00 d4 f2 0c 33 00 stfe.d7 \[r60\]=3Df90 - 77c: 00 00 04 00 nop.i 0x0 - 780: 08 00 68 79 d8 19 \[MMI\] stf.spill \[r60\]=3Df90 - 786: 00 d0 f2 b4 33 00 stf.spill.d1 \[r60\]=3Df90 - 78c: 00 00 04 00 nop.i 0x0 - 790: 08 00 68 79 da 19 \[MMI\] stf.spill.d1 \[r60\]=3Df90 - 796: 00 d0 f2 b8 33 00 stf.spill.d2 \[r60\]=3Df90 - 79c: 00 00 04 00 nop.i 0x0 - 7a0: 08 00 68 79 dc 19 \[MMI\] stf.spill.d2 \[r60\]=3Df90 - 7a6: 00 d0 f2 bc 33 00 stf.spill.nta \[r60\]=3Df90 - 7ac: 00 00 04 00 nop.i 0x0 - 7b0: 08 00 68 79 de 19 \[MMI\] stf.spill.nta \[r60\]=3Df90 - 7b6: 00 d4 f2 b0 33 00 stf.spill.d4 \[r60\]=3Df90 - 7bc: 00 00 04 00 nop.i 0x0 - 7c0: 08 00 6a 79 da 19 \[MMI\] stf.spill.d5 \[r60\]=3Df90 - 7c6: 00 d4 f2 b8 33 00 stf.spill.d6 \[r60\]=3Df90 - 7cc: 00 00 04 00 nop.i 0x0 - 7d0: 08 00 6a 79 de 19 \[MMI\] stf.spill.d7 \[r60\]=3Df90 - 7d6: 90 07 f4 21 30 00 ldfs f121=3D\[r125\] - 7dc: 00 00 04 00 nop.i 0x0 - 7e0: 08 c8 03 fa 12 18 \[MMI\] ldfs.nt1 f121=3D\[r125\] - 7e6: 90 07 f4 25 30 00 ldfs.nt1 f121=3D\[r125\] - 7ec: 00 00 04 00 nop.i 0x0 - 7f0: 08 c8 03 fa 14 18 \[MMI\] ldfs.d2 f121=3D\[r125\] - 7f6: 90 07 f4 29 30 00 ldfs.d2 f121=3D\[r125\] - 7fc: 00 00 04 00 nop.i 0x0 - 800: 08 c8 03 fa 16 18 \[MMI\] ldfs.nta f121=3D\[r125\] - 806: 90 07 f4 2d 30 00 ldfs.nta f121=3D\[r125\] - 80c: 00 00 04 00 nop.i 0x0 - 810: 08 c8 03 fb 10 18 \[MMI\] ldfs.d4 f121=3D\[r125\] - 816: 90 07 f6 25 30 00 ldfs.d5 f121=3D\[r125\] - 81c: 00 00 04 00 nop.i 0x0 - 820: 08 c8 03 fb 14 18 \[MMI\] ldfs.d6 f121=3D\[r125\] - 826: 90 07 f6 2d 30 00 ldfs.d7 f121=3D\[r125\] - 82c: 00 00 04 00 nop.i 0x0 - 830: 08 c8 03 fa 18 18 \[MMI\] ldfd f121=3D\[r125\] - 836: 90 07 f4 35 30 00 ldfd.nt1 f121=3D\[r125\] - 83c: 00 00 04 00 nop.i 0x0 - 840: 08 c8 03 fa 1a 18 \[MMI\] ldfd.nt1 f121=3D\[r125\] - 846: 90 07 f4 39 30 00 ldfd.d2 f121=3D\[r125\] - 84c: 00 00 04 00 nop.i 0x0 - 850: 08 c8 03 fa 1c 18 \[MMI\] ldfd.d2 f121=3D\[r125\] - 856: 90 07 f4 3d 30 00 ldfd.nta f121=3D\[r125\] - 85c: 00 00 04 00 nop.i 0x0 - 860: 08 c8 03 fa 1e 18 \[MMI\] ldfd.nta f121=3D\[r125\] - 866: 90 07 f6 31 30 00 ldfd.d4 f121=3D\[r125\] - 86c: 00 00 04 00 nop.i 0x0 - 870: 08 c8 03 fb 1a 18 \[MMI\] ldfd.d5 f121=3D\[r125\] - 876: 90 07 f6 39 30 00 ldfd.d6 f121=3D\[r125\] - 87c: 00 00 04 00 nop.i 0x0 - 880: 08 c8 03 fb 1e 18 \[MMI\] ldfd.d7 f121=3D\[r125\] - 886: 90 07 f4 11 30 00 ldf8 f121=3D\[r125\] - 88c: 00 00 04 00 nop.i 0x0 - 890: 08 c8 03 fa 0a 18 \[MMI\] ldf8.nt1 f121=3D\[r125\] - 896: 90 07 f4 15 30 00 ldf8.nt1 f121=3D\[r125\] - 89c: 00 00 04 00 nop.i 0x0 - 8a0: 08 c8 03 fa 0c 18 \[MMI\] ldf8.d2 f121=3D\[r125\] - 8a6: 90 07 f4 19 30 00 ldf8.d2 f121=3D\[r125\] - 8ac: 00 00 04 00 nop.i 0x0 - 8b0: 08 c8 03 fa 0e 18 \[MMI\] ldf8.nta f121=3D\[r125\] - 8b6: 90 07 f4 1d 30 00 ldf8.nta f121=3D\[r125\] - 8bc: 00 00 04 00 nop.i 0x0 - 8c0: 08 c8 03 fb 08 18 \[MMI\] ldf8.d4 f121=3D\[r125\] - 8c6: 90 07 f6 15 30 00 ldf8.d5 f121=3D\[r125\] - 8cc: 00 00 04 00 nop.i 0x0 - 8d0: 08 c8 03 fb 0c 18 \[MMI\] ldf8.d6 f121=3D\[r125\] - 8d6: 90 07 f6 1d 30 00 ldf8.d7 f121=3D\[r125\] - 8dc: 00 00 04 00 nop.i 0x0 - 8e0: 08 c8 03 fa 00 18 \[MMI\] ldfe f121=3D\[r125\] - 8e6: 90 07 f4 05 30 00 ldfe.nt1 f121=3D\[r125\] - 8ec: 00 00 04 00 nop.i 0x0 - 8f0: 08 c8 03 fa 02 18 \[MMI\] ldfe.nt1 f121=3D\[r125\] - 8f6: 90 07 f4 09 30 00 ldfe.d2 f121=3D\[r125\] - 8fc: 00 00 04 00 nop.i 0x0 - 900: 08 c8 03 fa 04 18 \[MMI\] ldfe.d2 f121=3D\[r125\] - 906: 90 07 f4 0d 30 00 ldfe.nta f121=3D\[r125\] - 90c: 00 00 04 00 nop.i 0x0 - 910: 08 c8 03 fa 06 18 \[MMI\] ldfe.nta f121=3D\[r125\] - 916: 90 07 f6 01 30 00 ldfe.d4 f121=3D\[r125\] - 91c: 00 00 04 00 nop.i 0x0 - 920: 08 c8 03 fb 02 18 \[MMI\] ldfe.d5 f121=3D\[r125\] - 926: 90 07 f6 09 30 00 ldfe.d6 f121=3D\[r125\] - 92c: 00 00 04 00 nop.i 0x0 - 930: 08 c8 03 fb 06 18 \[MMI\] ldfe.d7 f121=3D\[r125\] - 936: 90 07 f4 61 30 00 ldfs.s f121=3D\[r125\] - 93c: 00 00 04 00 nop.i 0x0 - 940: 08 c8 03 fa 32 18 \[MMI\] ldfs.s.nt1 f121=3D\[r125\] - 946: 90 07 f4 65 30 00 ldfs.s.nt1 f121=3D\[r125\] - 94c: 00 00 04 00 nop.i 0x0 - 950: 08 c8 03 fa 34 18 \[MMI\] ldfs.s.d2 f121=3D\[r125\] - 956: 90 07 f4 69 30 00 ldfs.s.d2 f121=3D\[r125\] - 95c: 00 00 04 00 nop.i 0x0 - 960: 08 c8 03 fa 36 18 \[MMI\] ldfs.s.nta f121=3D\[r125\] - 966: 90 07 f4 6d 30 00 ldfs.s.nta f121=3D\[r125\] - 96c: 00 00 04 00 nop.i 0x0 - 970: 08 c8 03 fb 30 18 \[MMI\] ldfs.s.d4 f121=3D\[r125\] - 976: 90 07 f6 65 30 00 ldfs.s.d5 f121=3D\[r125\] - 97c: 00 00 04 00 nop.i 0x0 - 980: 08 c8 03 fb 34 18 \[MMI\] ldfs.s.d6 f121=3D\[r125\] - 986: 90 07 f6 6d 30 00 ldfs.s.d7 f121=3D\[r125\] - 98c: 00 00 04 00 nop.i 0x0 - 990: 08 c8 03 fa 38 18 \[MMI\] ldfd.s f121=3D\[r125\] - 996: 90 07 f4 75 30 00 ldfd.s.nt1 f121=3D\[r125\] - 99c: 00 00 04 00 nop.i 0x0 - 9a0: 08 c8 03 fa 3a 18 \[MMI\] ldfd.s.nt1 f121=3D\[r125\] - 9a6: 90 07 f4 79 30 00 ldfd.s.d2 f121=3D\[r125\] - 9ac: 00 00 04 00 nop.i 0x0 - 9b0: 08 c8 03 fa 3c 18 \[MMI\] ldfd.s.d2 f121=3D\[r125\] - 9b6: 90 07 f4 7d 30 00 ldfd.s.nta f121=3D\[r125\] - 9bc: 00 00 04 00 nop.i 0x0 - 9c0: 08 c8 03 fa 3e 18 \[MMI\] ldfd.s.nta f121=3D\[r125\] - 9c6: 90 07 f6 71 30 00 ldfd.s.d4 f121=3D\[r125\] - 9cc: 00 00 04 00 nop.i 0x0 - 9d0: 08 c8 03 fb 3a 18 \[MMI\] ldfd.s.d5 f121=3D\[r125\] - 9d6: 90 07 f6 79 30 00 ldfd.s.d6 f121=3D\[r125\] - 9dc: 00 00 04 00 nop.i 0x0 - 9e0: 08 c8 03 fb 3e 18 \[MMI\] ldfd.s.d7 f121=3D\[r125\] - 9e6: 90 07 f4 51 30 00 ldf8.s f121=3D\[r125\] - 9ec: 00 00 04 00 nop.i 0x0 - 9f0: 08 c8 03 fa 2a 18 \[MMI\] ldf8.s.nt1 f121=3D\[r125\] - 9f6: 90 07 f4 55 30 00 ldf8.s.nt1 f121=3D\[r125\] - 9fc: 00 00 04 00 nop.i 0x0 - a00: 08 c8 03 fa 2c 18 \[MMI\] ldf8.s.d2 f121=3D\[r125\] - a06: 90 07 f4 59 30 00 ldf8.s.d2 f121=3D\[r125\] - a0c: 00 00 04 00 nop.i 0x0 - a10: 08 c8 03 fa 2e 18 \[MMI\] ldf8.s.nta f121=3D\[r125\] - a16: 90 07 f4 5d 30 00 ldf8.s.nta f121=3D\[r125\] - a1c: 00 00 04 00 nop.i 0x0 - a20: 08 c8 03 fb 28 18 \[MMI\] ldf8.s.d4 f121=3D\[r125\] - a26: 90 07 f6 55 30 00 ldf8.s.d5 f121=3D\[r125\] - a2c: 00 00 04 00 nop.i 0x0 - a30: 08 c8 03 fb 2c 18 \[MMI\] ldf8.s.d6 f121=3D\[r125\] - a36: 90 07 f6 5d 30 00 ldf8.s.d7 f121=3D\[r125\] - a3c: 00 00 04 00 nop.i 0x0 - a40: 08 c8 03 fa 20 18 \[MMI\] ldfe.s f121=3D\[r125\] - a46: 90 07 f4 45 30 00 ldfe.s.nt1 f121=3D\[r125\] - a4c: 00 00 04 00 nop.i 0x0 - a50: 08 c8 03 fa 22 18 \[MMI\] ldfe.s.nt1 f121=3D\[r125\] - a56: 90 07 f4 49 30 00 ldfe.s.d2 f121=3D\[r125\] - a5c: 00 00 04 00 nop.i 0x0 - a60: 08 c8 03 fa 24 18 \[MMI\] ldfe.s.d2 f121=3D\[r125\] - a66: 90 07 f4 4d 30 00 ldfe.s.nta f121=3D\[r125\] - a6c: 00 00 04 00 nop.i 0x0 - a70: 08 c8 03 fa 26 18 \[MMI\] ldfe.s.nta f121=3D\[r125\] - a76: 90 07 f6 41 30 00 ldfe.s.d4 f121=3D\[r125\] - a7c: 00 00 04 00 nop.i 0x0 - a80: 08 c8 03 fb 22 18 \[MMI\] ldfe.s.d5 f121=3D\[r125\] - a86: 90 07 f6 49 30 00 ldfe.s.d6 f121=3D\[r125\] - a8c: 00 00 04 00 nop.i 0x0 - a90: 08 c8 03 fb 26 18 \[MMI\] ldfe.s.d7 f121=3D\[r125\] - a96: 90 07 f4 a1 30 00 ldfs.a f121=3D\[r125\] - a9c: 00 00 04 00 nop.i 0x0 - aa0: 08 c8 03 fa 52 18 \[MMI\] ldfs.a.nt1 f121=3D\[r125\] - aa6: 90 07 f4 a5 30 00 ldfs.a.nt1 f121=3D\[r125\] - aac: 00 00 04 00 nop.i 0x0 - ab0: 08 c8 03 fa 54 18 \[MMI\] ldfs.a.d2 f121=3D\[r125\] - ab6: 90 07 f4 a9 30 00 ldfs.a.d2 f121=3D\[r125\] - abc: 00 00 04 00 nop.i 0x0 - ac0: 08 c8 03 fa 56 18 \[MMI\] ldfs.a.nta f121=3D\[r125\] - ac6: 90 07 f4 ad 30 00 ldfs.a.nta f121=3D\[r125\] - acc: 00 00 04 00 nop.i 0x0 - ad0: 08 c8 03 fb 50 18 \[MMI\] ldfs.a.d4 f121=3D\[r125\] - ad6: 90 07 f6 a5 30 00 ldfs.a.d5 f121=3D\[r125\] - adc: 00 00 04 00 nop.i 0x0 - ae0: 08 c8 03 fb 54 18 \[MMI\] ldfs.a.d6 f121=3D\[r125\] - ae6: 90 07 f6 ad 30 00 ldfs.a.d7 f121=3D\[r125\] - aec: 00 00 04 00 nop.i 0x0 - af0: 08 c8 03 fa 58 18 \[MMI\] ldfd.a f121=3D\[r125\] - af6: 90 07 f4 b5 30 00 ldfd.a.nt1 f121=3D\[r125\] - afc: 00 00 04 00 nop.i 0x0 - b00: 08 c8 03 fa 5a 18 \[MMI\] ldfd.a.nt1 f121=3D\[r125\] - b06: 90 07 f4 b9 30 00 ldfd.a.d2 f121=3D\[r125\] - b0c: 00 00 04 00 nop.i 0x0 - b10: 08 c8 03 fa 5c 18 \[MMI\] ldfd.a.d2 f121=3D\[r125\] - b16: 90 07 f4 bd 30 00 ldfd.a.nta f121=3D\[r125\] - b1c: 00 00 04 00 nop.i 0x0 - b20: 08 c8 03 fa 5e 18 \[MMI\] ldfd.a.nta f121=3D\[r125\] - b26: 90 07 f6 b1 30 00 ldfd.a.d4 f121=3D\[r125\] - b2c: 00 00 04 00 nop.i 0x0 - b30: 08 c8 03 fb 5a 18 \[MMI\] ldfd.a.d5 f121=3D\[r125\] - b36: 90 07 f6 b9 30 00 ldfd.a.d6 f121=3D\[r125\] - b3c: 00 00 04 00 nop.i 0x0 - b40: 08 c8 03 fb 5e 18 \[MMI\] ldfd.a.d7 f121=3D\[r125\] - b46: 90 07 f4 91 30 00 ldf8.a f121=3D\[r125\] - b4c: 00 00 04 00 nop.i 0x0 - b50: 08 c8 03 fa 4a 18 \[MMI\] ldf8.a.nt1 f121=3D\[r125\] - b56: 90 07 f4 95 30 00 ldf8.a.nt1 f121=3D\[r125\] - b5c: 00 00 04 00 nop.i 0x0 - b60: 08 c8 03 fa 4c 18 \[MMI\] ldf8.a.d2 f121=3D\[r125\] - b66: 90 07 f4 99 30 00 ldf8.a.d2 f121=3D\[r125\] - b6c: 00 00 04 00 nop.i 0x0 - b70: 08 c8 03 fa 4e 18 \[MMI\] ldf8.a.nta f121=3D\[r125\] - b76: 90 07 f4 9d 30 00 ldf8.a.nta f121=3D\[r125\] - b7c: 00 00 04 00 nop.i 0x0 - b80: 08 c8 03 fb 48 18 \[MMI\] ldf8.a.d4 f121=3D\[r125\] - b86: 90 07 f6 95 30 00 ldf8.a.d5 f121=3D\[r125\] - b8c: 00 00 04 00 nop.i 0x0 - b90: 08 c8 03 fb 4c 18 \[MMI\] ldf8.a.d6 f121=3D\[r125\] - b96: 90 07 f6 9d 30 00 ldf8.a.d7 f121=3D\[r125\] - b9c: 00 00 04 00 nop.i 0x0 - ba0: 08 c8 03 fa 40 18 \[MMI\] ldfe.a f121=3D\[r125\] - ba6: 90 07 f4 85 30 00 ldfe.a.nt1 f121=3D\[r125\] - bac: 00 00 04 00 nop.i 0x0 - bb0: 08 c8 03 fa 42 18 \[MMI\] ldfe.a.nt1 f121=3D\[r125\] - bb6: 90 07 f4 89 30 00 ldfe.a.d2 f121=3D\[r125\] - bbc: 00 00 04 00 nop.i 0x0 - bc0: 08 c8 03 fa 44 18 \[MMI\] ldfe.a.d2 f121=3D\[r125\] - bc6: 90 07 f4 8d 30 00 ldfe.a.nta f121=3D\[r125\] - bcc: 00 00 04 00 nop.i 0x0 - bd0: 08 c8 03 fa 46 18 \[MMI\] ldfe.a.nta f121=3D\[r125\] - bd6: 90 07 f6 81 30 00 ldfe.a.d4 f121=3D\[r125\] - bdc: 00 00 04 00 nop.i 0x0 - be0: 08 c8 03 fb 42 18 \[MMI\] ldfe.a.d5 f121=3D\[r125\] - be6: 90 07 f6 89 30 00 ldfe.a.d6 f121=3D\[r125\] - bec: 00 00 04 00 nop.i 0x0 - bf0: 08 c8 03 fb 46 18 \[MMI\] ldfe.a.d7 f121=3D\[r125\] - bf6: 90 07 f4 e1 30 00 ldfs.sa f121=3D\[r125\] - bfc: 00 00 04 00 nop.i 0x0 - c00: 08 c8 03 fa 72 18 \[MMI\] ldfs.sa.nt1 f121=3D\[r125\] - c06: 90 07 f4 e5 30 00 ldfs.sa.nt1 f121=3D\[r125\] - c0c: 00 00 04 00 nop.i 0x0 - c10: 08 c8 03 fa 74 18 \[MMI\] ldfs.sa.d2 f121=3D\[r125\] - c16: 90 07 f4 e9 30 00 ldfs.sa.d2 f121=3D\[r125\] - c1c: 00 00 04 00 nop.i 0x0 - c20: 08 c8 03 fa 76 18 \[MMI\] ldfs.sa.nta f121=3D\[r125\] - c26: 90 07 f4 ed 30 00 ldfs.sa.nta f121=3D\[r125\] - c2c: 00 00 04 00 nop.i 0x0 - c30: 08 c8 03 fb 70 18 \[MMI\] ldfs.sa.d4 f121=3D\[r125\] - c36: 90 07 f6 e5 30 00 ldfs.sa.d5 f121=3D\[r125\] - c3c: 00 00 04 00 nop.i 0x0 - c40: 08 c8 03 fb 74 18 \[MMI\] ldfs.sa.d6 f121=3D\[r125\] - c46: 90 07 f6 ed 30 00 ldfs.sa.d7 f121=3D\[r125\] - c4c: 00 00 04 00 nop.i 0x0 - c50: 08 c8 03 fa 78 18 \[MMI\] ldfd.sa f121=3D\[r125\] - c56: 90 07 f4 f5 30 00 ldfd.sa.nt1 f121=3D\[r125\] - c5c: 00 00 04 00 nop.i 0x0 - c60: 08 c8 03 fa 7a 18 \[MMI\] ldfd.sa.nt1 f121=3D\[r125\] - c66: 90 07 f4 f9 30 00 ldfd.sa.d2 f121=3D\[r125\] - c6c: 00 00 04 00 nop.i 0x0 - c70: 08 c8 03 fa 7c 18 \[MMI\] ldfd.sa.d2 f121=3D\[r125\] - c76: 90 07 f4 fd 30 00 ldfd.sa.nta f121=3D\[r125\] - c7c: 00 00 04 00 nop.i 0x0 - c80: 08 c8 03 fa 7e 18 \[MMI\] ldfd.sa.nta f121=3D\[r125\] - c86: 90 07 f6 f1 30 00 ldfd.sa.d4 f121=3D\[r125\] - c8c: 00 00 04 00 nop.i 0x0 - c90: 08 c8 03 fb 7a 18 \[MMI\] ldfd.sa.d5 f121=3D\[r125\] - c96: 90 07 f6 f9 30 00 ldfd.sa.d6 f121=3D\[r125\] - c9c: 00 00 04 00 nop.i 0x0 - ca0: 08 c8 03 fb 7e 18 \[MMI\] ldfd.sa.d7 f121=3D\[r125\] - ca6: 90 07 f4 d1 30 00 ldf8.sa f121=3D\[r125\] - cac: 00 00 04 00 nop.i 0x0 - cb0: 08 c8 03 fa 6a 18 \[MMI\] ldf8.sa.nt1 f121=3D\[r125\] - cb6: 90 07 f4 d5 30 00 ldf8.sa.nt1 f121=3D\[r125\] - cbc: 00 00 04 00 nop.i 0x0 - cc0: 08 c8 03 fa 6c 18 \[MMI\] ldf8.sa.d2 f121=3D\[r125\] - cc6: 90 07 f4 d9 30 00 ldf8.sa.d2 f121=3D\[r125\] - ccc: 00 00 04 00 nop.i 0x0 - cd0: 08 c8 03 fa 6e 18 \[MMI\] ldf8.sa.nta f121=3D\[r125\] - cd6: 90 07 f4 dd 30 00 ldf8.sa.nta f121=3D\[r125\] - cdc: 00 00 04 00 nop.i 0x0 - ce0: 08 c8 03 fb 68 18 \[MMI\] ldf8.sa.d4 f121=3D\[r125\] - ce6: 90 07 f6 d5 30 00 ldf8.sa.d5 f121=3D\[r125\] - cec: 00 00 04 00 nop.i 0x0 - cf0: 08 c8 03 fb 6c 18 \[MMI\] ldf8.sa.d6 f121=3D\[r125\] - cf6: 90 07 f6 dd 30 00 ldf8.sa.d7 f121=3D\[r125\] - cfc: 00 00 04 00 nop.i 0x0 - d00: 08 c8 03 fa 60 18 \[MMI\] ldfe.sa f121=3D\[r125\] - d06: 90 07 f4 c5 30 00 ldfe.sa.nt1 f121=3D\[r125\] - d0c: 00 00 04 00 nop.i 0x0 - d10: 08 c8 03 fa 62 18 \[MMI\] ldfe.sa.nt1 f121=3D\[r125\] - d16: 90 07 f4 c9 30 00 ldfe.sa.d2 f121=3D\[r125\] - d1c: 00 00 04 00 nop.i 0x0 - d20: 08 c8 03 fa 64 18 \[MMI\] ldfe.sa.d2 f121=3D\[r125\] - d26: 90 07 f4 cd 30 00 ldfe.sa.nta f121=3D\[r125\] - d2c: 00 00 04 00 nop.i 0x0 - d30: 08 c8 03 fa 66 18 \[MMI\] ldfe.sa.nta f121=3D\[r125\] - d36: 90 07 f6 c1 30 00 ldfe.sa.d4 f121=3D\[r125\] - d3c: 00 00 04 00 nop.i 0x0 - d40: 08 c8 03 fb 62 18 \[MMI\] ldfe.sa.d5 f121=3D\[r125\] - d46: 90 07 f6 c9 30 00 ldfe.sa.d6 f121=3D\[r125\] - d4c: 00 00 04 00 nop.i 0x0 - d50: 08 c8 03 fb 66 18 \[MMI\] ldfe.sa.d7 f121=3D\[r125\] - d56: 90 07 f4 b1 31 00 ldf.fill f121=3D\[r125\] - d5c: 00 00 04 00 nop.i 0x0 - d60: 08 c8 03 fa da 18 \[MMI\] ldf.fill.nt1 f121=3D\[r125\] - d66: 90 07 f4 b5 31 00 ldf.fill.nt1 f121=3D\[r125\] - d6c: 00 00 04 00 nop.i 0x0 - d70: 08 c8 03 fa dc 18 \[MMI\] ldf.fill.d2 f121=3D\[r125\] - d76: 90 07 f4 b9 31 00 ldf.fill.d2 f121=3D\[r125\] - d7c: 00 00 04 00 nop.i 0x0 - d80: 08 c8 03 fa de 18 \[MMI\] ldf.fill.nta f121=3D\[r125\] - d86: 90 07 f4 bd 31 00 ldf.fill.nta f121=3D\[r125\] - d8c: 00 00 04 00 nop.i 0x0 - d90: 08 c8 03 fb d8 18 \[MMI\] ldf.fill.d4 f121=3D\[r125\] - d96: 90 07 f6 b5 31 00 ldf.fill.d5 f121=3D\[r125\] - d9c: 00 00 04 00 nop.i 0x0 - da0: 08 c8 03 fb dc 18 \[MMI\] ldf.fill.d6 f121=3D\[r125\] - da6: 90 07 f6 bd 31 00 ldf.fill.d7 f121=3D\[r125\] - dac: 00 00 04 00 nop.i 0x0 - db0: 08 c8 03 fa 10 19 \[MMI\] ldfs.c.clr f121=3D\[r125\] - db6: 90 07 f4 25 32 00 ldfs.c.clr.nt1 f121=3D\[r125\] - dbc: 00 00 04 00 nop.i 0x0 - dc0: 08 c8 03 fa 12 19 \[MMI\] ldfs.c.clr.nt1 f121=3D\[r125\] - dc6: 90 07 f4 29 32 00 ldfs.c.clr.d2 f121=3D\[r125\] - dcc: 00 00 04 00 nop.i 0x0 - dd0: 08 c8 03 fa 14 19 \[MMI\] ldfs.c.clr.d2 f121=3D\[r125\] - dd6: 90 07 f4 2d 32 00 ldfs.c.clr.nta f121=3D\[r125\] - ddc: 00 00 04 00 nop.i 0x0 - de0: 08 c8 03 fa 16 19 \[MMI\] ldfs.c.clr.nta f121=3D\[r125\] - de6: 90 07 f6 21 32 00 ldfs.c.clr.d4 f121=3D\[r125\] - dec: 00 00 04 00 nop.i 0x0 - df0: 08 c8 03 fb 12 19 \[MMI\] ldfs.c.clr.d5 f121=3D\[r125\] - df6: 90 07 f6 29 32 00 ldfs.c.clr.d6 f121=3D\[r125\] - dfc: 00 00 04 00 nop.i 0x0 - e00: 08 c8 03 fb 16 19 \[MMI\] ldfs.c.clr.d7 f121=3D\[r125\] - e06: 90 07 f4 31 32 00 ldfd.c.clr f121=3D\[r125\] - e0c: 00 00 04 00 nop.i 0x0 - e10: 08 c8 03 fa 1a 19 \[MMI\] ldfd.c.clr.nt1 f121=3D\[r125\] - e16: 90 07 f4 35 32 00 ldfd.c.clr.nt1 f121=3D\[r125\] - e1c: 00 00 04 00 nop.i 0x0 - e20: 08 c8 03 fa 1c 19 \[MMI\] ldfd.c.clr.d2 f121=3D\[r125\] - e26: 90 07 f4 39 32 00 ldfd.c.clr.d2 f121=3D\[r125\] - e2c: 00 00 04 00 nop.i 0x0 - e30: 08 c8 03 fa 1e 19 \[MMI\] ldfd.c.clr.nta f121=3D\[r125\] - e36: 90 07 f4 3d 32 00 ldfd.c.clr.nta f121=3D\[r125\] - e3c: 00 00 04 00 nop.i 0x0 - e40: 08 c8 03 fb 18 19 \[MMI\] ldfd.c.clr.d4 f121=3D\[r125\] - e46: 90 07 f6 35 32 00 ldfd.c.clr.d5 f121=3D\[r125\] - e4c: 00 00 04 00 nop.i 0x0 - e50: 08 c8 03 fb 1c 19 \[MMI\] ldfd.c.clr.d6 f121=3D\[r125\] - e56: 90 07 f6 3d 32 00 ldfd.c.clr.d7 f121=3D\[r125\] - e5c: 00 00 04 00 nop.i 0x0 - e60: 08 c8 03 fa 08 19 \[MMI\] ldf8.c.clr f121=3D\[r125\] - e66: 90 07 f4 15 32 00 ldf8.c.clr.nt1 f121=3D\[r125\] - e6c: 00 00 04 00 nop.i 0x0 - e70: 08 c8 03 fa 0a 19 \[MMI\] ldf8.c.clr.nt1 f121=3D\[r125\] - e76: 90 07 f4 19 32 00 ldf8.c.clr.d2 f121=3D\[r125\] - e7c: 00 00 04 00 nop.i 0x0 - e80: 08 c8 03 fa 0c 19 \[MMI\] ldf8.c.clr.d2 f121=3D\[r125\] - e86: 90 07 f4 1d 32 00 ldf8.c.clr.nta f121=3D\[r125\] - e8c: 00 00 04 00 nop.i 0x0 - e90: 08 c8 03 fa 0e 19 \[MMI\] ldf8.c.clr.nta f121=3D\[r125\] - e96: 90 07 f6 11 32 00 ldf8.c.clr.d4 f121=3D\[r125\] - e9c: 00 00 04 00 nop.i 0x0 - ea0: 08 c8 03 fb 0a 19 \[MMI\] ldf8.c.clr.d5 f121=3D\[r125\] - ea6: 90 07 f6 19 32 00 ldf8.c.clr.d6 f121=3D\[r125\] - eac: 00 00 04 00 nop.i 0x0 - eb0: 08 c8 03 fb 0e 19 \[MMI\] ldf8.c.clr.d7 f121=3D\[r125\] - eb6: 90 07 f4 01 32 00 ldfe.c.clr f121=3D\[r125\] - ebc: 00 00 04 00 nop.i 0x0 - ec0: 08 c8 03 fa 02 19 \[MMI\] ldfe.c.clr.nt1 f121=3D\[r125\] - ec6: 90 07 f4 05 32 00 ldfe.c.clr.nt1 f121=3D\[r125\] - ecc: 00 00 04 00 nop.i 0x0 - ed0: 08 c8 03 fa 04 19 \[MMI\] ldfe.c.clr.d2 f121=3D\[r125\] - ed6: 90 07 f4 09 32 00 ldfe.c.clr.d2 f121=3D\[r125\] - edc: 00 00 04 00 nop.i 0x0 - ee0: 08 c8 03 fa 06 19 \[MMI\] ldfe.c.clr.nta f121=3D\[r125\] - ee6: 90 07 f4 0d 32 00 ldfe.c.clr.nta f121=3D\[r125\] - eec: 00 00 04 00 nop.i 0x0 - ef0: 08 c8 03 fb 00 19 \[MMI\] ldfe.c.clr.d4 f121=3D\[r125\] - ef6: 90 07 f6 05 32 00 ldfe.c.clr.d5 f121=3D\[r125\] - efc: 00 00 04 00 nop.i 0x0 - f00: 08 c8 03 fb 04 19 \[MMI\] ldfe.c.clr.d6 f121=3D\[r125\] - f06: 90 07 f6 0d 32 00 ldfe.c.clr.d7 f121=3D\[r125\] - f0c: 00 00 04 00 nop.i 0x0 - f10: 08 c8 03 fa 30 19 \[MMI\] ldfs.c.nc f121=3D\[r125\] - f16: 90 07 f4 65 32 00 ldfs.c.nc.nt1 f121=3D\[r125\] - f1c: 00 00 04 00 nop.i 0x0 - f20: 08 c8 03 fa 32 19 \[MMI\] ldfs.c.nc.nt1 f121=3D\[r125\] - f26: 90 07 f4 69 32 00 ldfs.c.nc.d2 f121=3D\[r125\] - f2c: 00 00 04 00 nop.i 0x0 - f30: 08 c8 03 fa 34 19 \[MMI\] ldfs.c.nc.d2 f121=3D\[r125\] - f36: 90 07 f4 6d 32 00 ldfs.c.nc.nta f121=3D\[r125\] - f3c: 00 00 04 00 nop.i 0x0 - f40: 08 c8 03 fa 36 19 \[MMI\] ldfs.c.nc.nta f121=3D\[r125\] - f46: 90 07 f6 61 32 00 ldfs.c.nc.d4 f121=3D\[r125\] - f4c: 00 00 04 00 nop.i 0x0 - f50: 08 c8 03 fb 32 19 \[MMI\] ldfs.c.nc.d5 f121=3D\[r125\] - f56: 90 07 f6 69 32 00 ldfs.c.nc.d6 f121=3D\[r125\] - f5c: 00 00 04 00 nop.i 0x0 - f60: 08 c8 03 fb 36 19 \[MMI\] ldfs.c.nc.d7 f121=3D\[r125\] - f66: 90 07 f4 71 32 00 ldfd.c.nc f121=3D\[r125\] - f6c: 00 00 04 00 nop.i 0x0 - f70: 08 c8 03 fa 3a 19 \[MMI\] ldfd.c.nc.nt1 f121=3D\[r125\] - f76: 90 07 f4 75 32 00 ldfd.c.nc.nt1 f121=3D\[r125\] - f7c: 00 00 04 00 nop.i 0x0 - f80: 08 c8 03 fa 3c 19 \[MMI\] ldfd.c.nc.d2 f121=3D\[r125\] - f86: 90 07 f4 79 32 00 ldfd.c.nc.d2 f121=3D\[r125\] - f8c: 00 00 04 00 nop.i 0x0 - f90: 08 c8 03 fa 3e 19 \[MMI\] ldfd.c.nc.nta f121=3D\[r125\] - f96: 90 07 f4 7d 32 00 ldfd.c.nc.nta f121=3D\[r125\] - f9c: 00 00 04 00 nop.i 0x0 - fa0: 08 c8 03 fb 38 19 \[MMI\] ldfd.c.nc.d4 f121=3D\[r125\] - fa6: 90 07 f6 75 32 00 ldfd.c.nc.d5 f121=3D\[r125\] - fac: 00 00 04 00 nop.i 0x0 - fb0: 08 c8 03 fb 3c 19 \[MMI\] ldfd.c.nc.d6 f121=3D\[r125\] - fb6: 90 07 f6 7d 32 00 ldfd.c.nc.d7 f121=3D\[r125\] - fbc: 00 00 04 00 nop.i 0x0 - fc0: 08 c8 03 fa 28 19 \[MMI\] ldf8.c.nc f121=3D\[r125\] - fc6: 90 07 f4 55 32 00 ldf8.c.nc.nt1 f121=3D\[r125\] - fcc: 00 00 04 00 nop.i 0x0 - fd0: 08 c8 03 fa 2a 19 \[MMI\] ldf8.c.nc.nt1 f121=3D\[r125\] - fd6: 90 07 f4 59 32 00 ldf8.c.nc.d2 f121=3D\[r125\] - fdc: 00 00 04 00 nop.i 0x0 - fe0: 08 c8 03 fa 2c 19 \[MMI\] ldf8.c.nc.d2 f121=3D\[r125\] - fe6: 90 07 f4 5d 32 00 ldf8.c.nc.nta f121=3D\[r125\] - fec: 00 00 04 00 nop.i 0x0 - ff0: 08 c8 03 fa 2e 19 \[MMI\] ldf8.c.nc.nta f121=3D\[r125\] - ff6: 90 07 f6 51 32 00 ldf8.c.nc.d4 f121=3D\[r125\] - ffc: 00 00 04 00 nop.i 0x0 - 1000: 08 c8 03 fb 2a 19 \[MMI\] ldf8.c.nc.d5 f121=3D\[r125\] - 1006: 90 07 f6 59 32 00 ldf8.c.nc.d6 f121=3D\[r125\] - 100c: 00 00 04 00 nop.i 0x0 - 1010: 08 c8 03 fb 2e 19 \[MMI\] ldf8.c.nc.d7 f121=3D\[r125\] - 1016: 90 07 f4 41 32 00 ldfe.c.nc f121=3D\[r125\] - 101c: 00 00 04 00 nop.i 0x0 - 1020: 08 c8 03 fa 22 19 \[MMI\] ldfe.c.nc.nt1 f121=3D\[r125\] - 1026: 90 07 f4 45 32 00 ldfe.c.nc.nt1 f121=3D\[r125\] - 102c: 00 00 04 00 nop.i 0x0 - 1030: 08 c8 03 fa 24 19 \[MMI\] ldfe.c.nc.d2 f121=3D\[r125\] - 1036: 90 07 f4 49 32 00 ldfe.c.nc.d2 f121=3D\[r125\] - 103c: 00 00 04 00 nop.i 0x0 - 1040: 08 c8 03 fa 26 19 \[MMI\] ldfe.c.nc.nta f121=3D\[r125\] - 1046: 90 07 f4 4d 32 00 ldfe.c.nc.nta f121=3D\[r125\] - 104c: 00 00 04 00 nop.i 0x0 - 1050: 08 c8 03 fb 20 19 \[MMI\] ldfe.c.nc.d4 f121=3D\[r125\] - 1056: 90 07 f6 45 32 00 ldfe.c.nc.d5 f121=3D\[r125\] - 105c: 00 00 04 00 nop.i 0x0 - 1060: 08 c8 03 fb 24 19 \[MMI\] ldfe.c.nc.d6 f121=3D\[r125\] - 1066: 90 07 f6 4d 32 00 ldfe.c.nc.d7 f121=3D\[r125\] - 106c: 00 00 04 00 nop.i 0x0 - 1070: 08 c0 03 28 00 10 \[MMI\] ld1 r120=3D\[r20\] - 1076: 80 07 50 04 20 00 ld1.nt1 r120=3D\[r20\] - 107c: 00 00 04 00 nop.i 0x0 - 1080: 08 c0 03 28 02 10 \[MMI\] ld1.nt1 r120=3D\[r20\] - 1086: 80 07 50 08 20 00 ld1.d2 r120=3D\[r20\] - 108c: 00 00 04 00 nop.i 0x0 - 1090: 08 c0 03 28 04 10 \[MMI\] ld1.d2 r120=3D\[r20\] - 1096: 80 07 50 0c 20 00 ld1.nta r120=3D\[r20\] - 109c: 00 00 04 00 nop.i 0x0 - 10a0: 08 c0 03 28 06 10 \[MMI\] ld1.nta r120=3D\[r20\] - 10a6: 80 07 52 00 20 00 ld1.d4 r120=3D\[r20\] - 10ac: 00 00 04 00 nop.i 0x0 - 10b0: 08 c0 03 29 02 10 \[MMI\] ld1.d5 r120=3D\[r20\] - 10b6: 80 07 52 08 20 00 ld1.d6 r120=3D\[r20\] - 10bc: 00 00 04 00 nop.i 0x0 - 10c0: 08 c0 03 29 06 10 \[MMI\] ld1.d7 r120=3D\[r20\] - 10c6: 80 07 50 10 20 00 ld2 r120=3D\[r20\] - 10cc: 00 00 04 00 nop.i 0x0 - 10d0: 08 c0 03 28 0a 10 \[MMI\] ld2.nt1 r120=3D\[r20\] - 10d6: 80 07 50 14 20 00 ld2.nt1 r120=3D\[r20\] - 10dc: 00 00 04 00 nop.i 0x0 - 10e0: 08 c0 03 28 0c 10 \[MMI\] ld2.d2 r120=3D\[r20\] - 10e6: 80 07 50 18 20 00 ld2.d2 r120=3D\[r20\] - 10ec: 00 00 04 00 nop.i 0x0 - 10f0: 08 c0 03 28 0e 10 \[MMI\] ld2.nta r120=3D\[r20\] - 10f6: 80 07 50 1c 20 00 ld2.nta r120=3D\[r20\] - 10fc: 00 00 04 00 nop.i 0x0 - 1100: 08 c0 03 29 08 10 \[MMI\] ld2.d4 r120=3D\[r20\] - 1106: 80 07 52 14 20 00 ld2.d5 r120=3D\[r20\] - 110c: 00 00 04 00 nop.i 0x0 - 1110: 08 c0 03 29 0c 10 \[MMI\] ld2.d6 r120=3D\[r20\] - 1116: 80 07 52 1c 20 00 ld2.d7 r120=3D\[r20\] - 111c: 00 00 04 00 nop.i 0x0 - 1120: 08 c0 03 28 10 10 \[MMI\] ld4 r120=3D\[r20\] - 1126: 80 07 50 24 20 00 ld4.nt1 r120=3D\[r20\] - 112c: 00 00 04 00 nop.i 0x0 - 1130: 08 c0 03 28 12 10 \[MMI\] ld4.nt1 r120=3D\[r20\] - 1136: 80 07 50 28 20 00 ld4.d2 r120=3D\[r20\] - 113c: 00 00 04 00 nop.i 0x0 - 1140: 08 c0 03 28 14 10 \[MMI\] ld4.d2 r120=3D\[r20\] - 1146: 80 07 50 2c 20 00 ld4.nta r120=3D\[r20\] - 114c: 00 00 04 00 nop.i 0x0 - 1150: 08 c0 03 28 16 10 \[MMI\] ld4.nta r120=3D\[r20\] - 1156: 80 07 52 20 20 00 ld4.d4 r120=3D\[r20\] - 115c: 00 00 04 00 nop.i 0x0 - 1160: 08 c0 03 29 12 10 \[MMI\] ld4.d5 r120=3D\[r20\] - 1166: 80 07 52 28 20 00 ld4.d6 r120=3D\[r20\] - 116c: 00 00 04 00 nop.i 0x0 - 1170: 08 c0 03 29 16 10 \[MMI\] ld4.d7 r120=3D\[r20\] - 1176: 80 07 50 30 20 00 ld8 r120=3D\[r20\] - 117c: 00 00 04 00 nop.i 0x0 - 1180: 08 c0 03 28 1a 10 \[MMI\] ld8.nt1 r120=3D\[r20\] - 1186: 80 07 50 34 20 00 ld8.nt1 r120=3D\[r20\] - 118c: 00 00 04 00 nop.i 0x0 - 1190: 08 c0 03 28 1c 10 \[MMI\] ld8.d2 r120=3D\[r20\] - 1196: 80 07 50 38 20 00 ld8.d2 r120=3D\[r20\] - 119c: 00 00 04 00 nop.i 0x0 - 11a0: 08 c0 03 28 1e 10 \[MMI\] ld8.nta r120=3D\[r20\] - 11a6: 80 07 50 3c 20 00 ld8.nta r120=3D\[r20\] - 11ac: 00 00 04 00 nop.i 0x0 - 11b0: 08 c0 03 29 18 10 \[MMI\] ld8.d4 r120=3D\[r20\] - 11b6: 80 07 52 34 20 00 ld8.d5 r120=3D\[r20\] - 11bc: 00 00 04 00 nop.i 0x0 - 11c0: 08 c0 03 29 1c 10 \[MMI\] ld8.d6 r120=3D\[r20\] - 11c6: 80 07 52 3c 20 00 ld8.d7 r120=3D\[r20\] - 11cc: 00 00 04 00 nop.i 0x0 - 11d0: 08 c0 03 28 20 10 \[MMI\] ld1.s r120=3D\[r20\] - 11d6: 80 07 50 44 20 00 ld1.s.nt1 r120=3D\[r20\] - 11dc: 00 00 04 00 nop.i 0x0 - 11e0: 08 c0 03 28 22 10 \[MMI\] ld1.s.nt1 r120=3D\[r20\] - 11e6: 80 07 50 48 20 00 ld1.s.d2 r120=3D\[r20\] - 11ec: 00 00 04 00 nop.i 0x0 - 11f0: 08 c0 03 28 24 10 \[MMI\] ld1.s.d2 r120=3D\[r20\] - 11f6: 80 07 50 4c 20 00 ld1.s.nta r120=3D\[r20\] - 11fc: 00 00 04 00 nop.i 0x0 - 1200: 08 c0 03 28 26 10 \[MMI\] ld1.s.nta r120=3D\[r20\] - 1206: 80 07 52 40 20 00 ld1.s.d4 r120=3D\[r20\] - 120c: 00 00 04 00 nop.i 0x0 - 1210: 08 c0 03 29 22 10 \[MMI\] ld1.s.d5 r120=3D\[r20\] - 1216: 80 07 52 48 20 00 ld1.s.d6 r120=3D\[r20\] - 121c: 00 00 04 00 nop.i 0x0 - 1220: 08 c0 03 29 26 10 \[MMI\] ld1.s.d7 r120=3D\[r20\] - 1226: 80 07 50 50 20 00 ld2.s r120=3D\[r20\] - 122c: 00 00 04 00 nop.i 0x0 - 1230: 08 c0 03 28 2a 10 \[MMI\] ld2.s.nt1 r120=3D\[r20\] - 1236: 80 07 50 54 20 00 ld2.s.nt1 r120=3D\[r20\] - 123c: 00 00 04 00 nop.i 0x0 - 1240: 08 c0 03 28 2c 10 \[MMI\] ld2.s.d2 r120=3D\[r20\] - 1246: 80 07 50 58 20 00 ld2.s.d2 r120=3D\[r20\] - 124c: 00 00 04 00 nop.i 0x0 - 1250: 08 c0 03 28 2e 10 \[MMI\] ld2.s.nta r120=3D\[r20\] - 1256: 80 07 50 5c 20 00 ld2.s.nta r120=3D\[r20\] - 125c: 00 00 04 00 nop.i 0x0 - 1260: 08 c0 03 29 28 10 \[MMI\] ld2.s.d4 r120=3D\[r20\] - 1266: 80 07 52 54 20 00 ld2.s.d5 r120=3D\[r20\] - 126c: 00 00 04 00 nop.i 0x0 - 1270: 08 c0 03 29 2c 10 \[MMI\] ld2.s.d6 r120=3D\[r20\] - 1276: 80 07 52 5c 20 00 ld2.s.d7 r120=3D\[r20\] - 127c: 00 00 04 00 nop.i 0x0 - 1280: 08 c0 03 28 30 10 \[MMI\] ld4.s r120=3D\[r20\] - 1286: 80 07 50 64 20 00 ld4.s.nt1 r120=3D\[r20\] - 128c: 00 00 04 00 nop.i 0x0 - 1290: 08 c0 03 28 32 10 \[MMI\] ld4.s.nt1 r120=3D\[r20\] - 1296: 80 07 50 68 20 00 ld4.s.d2 r120=3D\[r20\] - 129c: 00 00 04 00 nop.i 0x0 - 12a0: 08 c0 03 28 34 10 \[MMI\] ld4.s.d2 r120=3D\[r20\] - 12a6: 80 07 50 6c 20 00 ld4.s.nta r120=3D\[r20\] - 12ac: 00 00 04 00 nop.i 0x0 - 12b0: 08 c0 03 28 36 10 \[MMI\] ld4.s.nta r120=3D\[r20\] - 12b6: 80 07 52 60 20 00 ld4.s.d4 r120=3D\[r20\] - 12bc: 00 00 04 00 nop.i 0x0 - 12c0: 08 c0 03 29 32 10 \[MMI\] ld4.s.d5 r120=3D\[r20\] - 12c6: 80 07 52 68 20 00 ld4.s.d6 r120=3D\[r20\] - 12cc: 00 00 04 00 nop.i 0x0 - 12d0: 08 c0 03 29 36 10 \[MMI\] ld4.s.d7 r120=3D\[r20\] - 12d6: 80 07 50 70 20 00 ld8.s r120=3D\[r20\] - 12dc: 00 00 04 00 nop.i 0x0 - 12e0: 08 c0 03 28 3a 10 \[MMI\] ld8.s.nt1 r120=3D\[r20\] - 12e6: 80 07 50 74 20 00 ld8.s.nt1 r120=3D\[r20\] - 12ec: 00 00 04 00 nop.i 0x0 - 12f0: 08 c0 03 28 3c 10 \[MMI\] ld8.s.d2 r120=3D\[r20\] - 12f6: 80 07 50 78 20 00 ld8.s.d2 r120=3D\[r20\] - 12fc: 00 00 04 00 nop.i 0x0 - 1300: 08 c0 03 28 3e 10 \[MMI\] ld8.s.nta r120=3D\[r20\] - 1306: 80 07 50 7c 20 00 ld8.s.nta r120=3D\[r20\] - 130c: 00 00 04 00 nop.i 0x0 - 1310: 08 c0 03 29 38 10 \[MMI\] ld8.s.d4 r120=3D\[r20\] - 1316: 80 07 52 74 20 00 ld8.s.d5 r120=3D\[r20\] - 131c: 00 00 04 00 nop.i 0x0 - 1320: 08 c0 03 29 3c 10 \[MMI\] ld8.s.d6 r120=3D\[r20\] - 1326: 80 07 52 7c 20 00 ld8.s.d7 r120=3D\[r20\] - 132c: 00 00 04 00 nop.i 0x0 - 1330: 08 c0 03 28 40 10 \[MMI\] ld1.a r120=3D\[r20\] - 1336: 80 07 50 84 20 00 ld1.a.nt1 r120=3D\[r20\] - 133c: 00 00 04 00 nop.i 0x0 - 1340: 08 c0 03 28 42 10 \[MMI\] ld1.a.nt1 r120=3D\[r20\] - 1346: 80 07 50 88 20 00 ld1.a.d2 r120=3D\[r20\] - 134c: 00 00 04 00 nop.i 0x0 - 1350: 08 c0 03 28 44 10 \[MMI\] ld1.a.d2 r120=3D\[r20\] - 1356: 80 07 50 8c 20 00 ld1.a.nta r120=3D\[r20\] - 135c: 00 00 04 00 nop.i 0x0 - 1360: 08 c0 03 28 46 10 \[MMI\] ld1.a.nta r120=3D\[r20\] - 1366: 80 07 52 80 20 00 ld1.a.d4 r120=3D\[r20\] - 136c: 00 00 04 00 nop.i 0x0 - 1370: 08 c0 03 29 42 10 \[MMI\] ld1.a.d5 r120=3D\[r20\] - 1376: 80 07 52 88 20 00 ld1.a.d6 r120=3D\[r20\] - 137c: 00 00 04 00 nop.i 0x0 - 1380: 08 c0 03 29 46 10 \[MMI\] ld1.a.d7 r120=3D\[r20\] - 1386: 80 07 50 90 20 00 ld2.a r120=3D\[r20\] - 138c: 00 00 04 00 nop.i 0x0 - 1390: 08 c0 03 28 4a 10 \[MMI\] ld2.a.nt1 r120=3D\[r20\] - 1396: 80 07 50 94 20 00 ld2.a.nt1 r120=3D\[r20\] - 139c: 00 00 04 00 nop.i 0x0 - 13a0: 08 c0 03 28 4c 10 \[MMI\] ld2.a.d2 r120=3D\[r20\] - 13a6: 80 07 50 9c 20 00 ld2.a.nta r120=3D\[r20\] - 13ac: 00 00 04 00 nop.i 0x0 - 13b0: 08 c0 03 28 4e 10 \[MMI\] ld2.a.nta r120=3D\[r20\] - 13b6: 80 07 52 90 20 00 ld2.a.d4 r120=3D\[r20\] - 13bc: 00 00 04 00 nop.i 0x0 - 13c0: 08 c0 03 29 4a 10 \[MMI\] ld2.a.d5 r120=3D\[r20\] - 13c6: 80 07 52 98 20 00 ld2.a.d6 r120=3D\[r20\] - 13cc: 00 00 04 00 nop.i 0x0 - 13d0: 08 c0 03 29 4e 10 \[MMI\] ld2.a.d7 r120=3D\[r20\] - 13d6: 80 07 50 a0 20 00 ld4.a r120=3D\[r20\] - 13dc: 00 00 04 00 nop.i 0x0 - 13e0: 08 c0 03 28 52 10 \[MMI\] ld4.a.nt1 r120=3D\[r20\] - 13e6: 80 07 50 a4 20 00 ld4.a.nt1 r120=3D\[r20\] - 13ec: 00 00 04 00 nop.i 0x0 - 13f0: 08 c0 03 28 54 10 \[MMI\] ld4.a.d2 r120=3D\[r20\] - 13f6: 80 07 50 a8 20 00 ld4.a.d2 r120=3D\[r20\] - 13fc: 00 00 04 00 nop.i 0x0 - 1400: 08 c0 03 28 56 10 \[MMI\] ld4.a.nta r120=3D\[r20\] - 1406: 80 07 50 ac 20 00 ld4.a.nta r120=3D\[r20\] - 140c: 00 00 04 00 nop.i 0x0 - 1410: 08 c0 03 29 50 10 \[MMI\] ld4.a.d4 r120=3D\[r20\] - 1416: 80 07 52 a4 20 00 ld4.a.d5 r120=3D\[r20\] - 141c: 00 00 04 00 nop.i 0x0 - 1420: 08 c0 03 29 54 10 \[MMI\] ld4.a.d6 r120=3D\[r20\] - 1426: 80 07 52 ac 20 00 ld4.a.d7 r120=3D\[r20\] - 142c: 00 00 04 00 nop.i 0x0 - 1430: 08 c0 03 28 58 10 \[MMI\] ld8.a r120=3D\[r20\] - 1436: 80 07 50 b4 20 00 ld8.a.nt1 r120=3D\[r20\] - 143c: 00 00 04 00 nop.i 0x0 - 1440: 08 c0 03 28 5a 10 \[MMI\] ld8.a.nt1 r120=3D\[r20\] - 1446: 80 07 50 b8 20 00 ld8.a.d2 r120=3D\[r20\] - 144c: 00 00 04 00 nop.i 0x0 - 1450: 08 c0 03 28 5c 10 \[MMI\] ld8.a.d2 r120=3D\[r20\] - 1456: 80 07 50 bc 20 00 ld8.a.nta r120=3D\[r20\] - 145c: 00 00 04 00 nop.i 0x0 - 1460: 08 c0 03 28 5e 10 \[MMI\] ld8.a.nta r120=3D\[r20\] - 1466: 80 07 52 b4 20 00 ld8.a.d5 r120=3D\[r20\] - 146c: 00 00 04 00 nop.i 0x0 - 1470: 08 c0 03 29 5c 10 \[MMI\] ld8.a.d6 r120=3D\[r20\] - 1476: 80 07 52 bc 20 00 ld8.a.d7 r120=3D\[r20\] - 147c: 00 00 04 00 nop.i 0x0 - 1480: 08 c0 03 28 60 10 \[MMI\] ld1.sa r120=3D\[r20\] - 1486: 80 07 50 c4 20 00 ld1.sa.nt1 r120=3D\[r20\] - 148c: 00 00 04 00 nop.i 0x0 - 1490: 08 c0 03 28 62 10 \[MMI\] ld1.sa.nt1 r120=3D\[r20\] - 1496: 80 07 50 c8 20 00 ld1.sa.d2 r120=3D\[r20\] - 149c: 00 00 04 00 nop.i 0x0 - 14a0: 08 c0 03 28 64 10 \[MMI\] ld1.sa.d2 r120=3D\[r20\] - 14a6: 80 07 50 cc 20 00 ld1.sa.nta r120=3D\[r20\] - 14ac: 00 00 04 00 nop.i 0x0 - 14b0: 08 c0 03 28 66 10 \[MMI\] ld1.sa.nta r120=3D\[r20\] - 14b6: 80 07 52 c0 20 00 ld1.sa.d4 r120=3D\[r20\] - 14bc: 00 00 04 00 nop.i 0x0 - 14c0: 08 c0 03 29 62 10 \[MMI\] ld1.sa.d5 r120=3D\[r20\] - 14c6: 80 07 52 c8 20 00 ld1.sa.d6 r120=3D\[r20\] - 14cc: 00 00 04 00 nop.i 0x0 - 14d0: 08 c0 03 29 66 10 \[MMI\] ld1.sa.d7 r120=3D\[r20\] - 14d6: 80 07 50 d0 20 00 ld2.sa r120=3D\[r20\] - 14dc: 00 00 04 00 nop.i 0x0 - 14e0: 08 c0 03 28 6a 10 \[MMI\] ld2.sa.nt1 r120=3D\[r20\] - 14e6: 80 07 50 d4 20 00 ld2.sa.nt1 r120=3D\[r20\] - 14ec: 00 00 04 00 nop.i 0x0 - 14f0: 08 c0 03 28 6c 10 \[MMI\] ld2.sa.d2 r120=3D\[r20\] - 14f6: 80 07 50 d8 20 00 ld2.sa.d2 r120=3D\[r20\] - 14fc: 00 00 04 00 nop.i 0x0 - 1500: 08 c0 03 28 6e 10 \[MMI\] ld2.sa.nta r120=3D\[r20\] - 1506: 80 07 50 dc 20 00 ld2.sa.nta r120=3D\[r20\] - 150c: 00 00 04 00 nop.i 0x0 - 1510: 08 c0 03 29 68 10 \[MMI\] ld2.sa.d4 r120=3D\[r20\] - 1516: 80 07 52 d4 20 00 ld2.sa.d5 r120=3D\[r20\] - 151c: 00 00 04 00 nop.i 0x0 - 1520: 08 c0 03 29 6c 10 \[MMI\] ld2.sa.d6 r120=3D\[r20\] - 1526: 80 07 52 dc 20 00 ld2.sa.d7 r120=3D\[r20\] - 152c: 00 00 04 00 nop.i 0x0 - 1530: 08 c0 03 28 72 10 \[MMI\] ld4.sa.nt1 r120=3D\[r20\] - 1536: 80 07 50 e4 20 00 ld4.sa.nt1 r120=3D\[r20\] - 153c: 00 00 04 00 nop.i 0x0 - 1540: 08 c0 03 28 74 10 \[MMI\] ld4.sa.d2 r120=3D\[r20\] - 1546: 80 07 50 e8 20 00 ld4.sa.d2 r120=3D\[r20\] - 154c: 00 00 04 00 nop.i 0x0 - 1550: 08 c0 03 28 76 10 \[MMI\] ld4.sa.nta r120=3D\[r20\] - 1556: 80 07 50 ec 20 00 ld4.sa.nta r120=3D\[r20\] - 155c: 00 00 04 00 nop.i 0x0 - 1560: 08 c0 03 29 70 10 \[MMI\] ld4.sa.d4 r120=3D\[r20\] - 1566: 80 07 52 e4 20 00 ld4.sa.d5 r120=3D\[r20\] - 156c: 00 00 04 00 nop.i 0x0 - 1570: 08 c0 03 29 74 10 \[MMI\] ld4.sa.d6 r120=3D\[r20\] - 1576: 80 07 52 ec 20 00 ld4.sa.d7 r120=3D\[r20\] - 157c: 00 00 04 00 nop.i 0x0 - 1580: 08 c0 03 28 78 10 \[MMI\] ld8.sa r120=3D\[r20\] - 1586: 80 07 50 f4 20 00 ld8.sa.nt1 r120=3D\[r20\] - 158c: 00 00 04 00 nop.i 0x0 - 1590: 08 c0 03 28 7a 10 \[MMI\] ld8.sa.nt1 r120=3D\[r20\] - 1596: 80 07 50 f8 20 00 ld8.sa.d2 r120=3D\[r20\] - 159c: 00 00 04 00 nop.i 0x0 - 15a0: 08 c0 03 28 7c 10 \[MMI\] ld8.sa.d2 r120=3D\[r20\] - 15a6: 80 07 50 fc 20 00 ld8.sa.nta r120=3D\[r20\] - 15ac: 00 00 04 00 nop.i 0x0 - 15b0: 08 c0 03 28 7e 10 \[MMI\] ld8.sa.nta r120=3D\[r20\] - 15b6: 80 07 52 f0 20 00 ld8.sa.d4 r120=3D\[r20\] - 15bc: 00 00 04 00 nop.i 0x0 - 15c0: 08 c0 03 29 7a 10 \[MMI\] ld8.sa.d5 r120=3D\[r20\] - 15c6: 80 07 52 f8 20 00 ld8.sa.d6 r120=3D\[r20\] - 15cc: 00 00 04 00 nop.i 0x0 - 15d0: 08 c0 03 29 7e 10 \[MMI\] ld8.sa.d7 r120=3D\[r20\] - 15d6: 80 07 50 00 21 00 ld1.bias r120=3D\[r20\] - 15dc: 00 00 04 00 nop.i 0x0 - 15e0: 08 c0 03 28 82 10 \[MMI\] ld1.bias.nt1 r120=3D\[r20\] - 15e6: 80 07 50 04 21 00 ld1.bias.nt1 r120=3D\[r20\] - 15ec: 00 00 04 00 nop.i 0x0 - 15f0: 08 c0 03 28 84 10 \[MMI\] ld1.bias.d2 r120=3D\[r20\] - 15f6: 80 07 50 08 21 00 ld1.bias.d2 r120=3D\[r20\] - 15fc: 00 00 04 00 nop.i 0x0 - 1600: 08 c0 03 28 86 10 \[MMI\] ld1.bias.nta r120=3D\[r20\] - 1606: 80 07 50 0c 21 00 ld1.bias.nta r120=3D\[r20\] - 160c: 00 00 04 00 nop.i 0x0 - 1610: 08 c0 03 29 80 10 \[MMI\] ld1.bias.d4 r120=3D\[r20\] - 1616: 80 07 52 04 21 00 ld1.bias.d5 r120=3D\[r20\] - 161c: 00 00 04 00 nop.i 0x0 - 1620: 08 c0 03 29 84 10 \[MMI\] ld1.bias.d6 r120=3D\[r20\] - 1626: 80 07 52 0c 21 00 ld1.bias.d7 r120=3D\[r20\] - 162c: 00 00 04 00 nop.i 0x0 - 1630: 08 c0 03 28 88 10 \[MMI\] ld2.bias r120=3D\[r20\] - 1636: 80 07 50 14 21 00 ld2.bias.nt1 r120=3D\[r20\] - 163c: 00 00 04 00 nop.i 0x0 - 1640: 08 c0 03 28 8a 10 \[MMI\] ld2.bias.nt1 r120=3D\[r20\] - 1646: 80 07 50 18 21 00 ld2.bias.d2 r120=3D\[r20\] - 164c: 00 00 04 00 nop.i 0x0 - 1650: 08 c0 03 28 8c 10 \[MMI\] ld2.bias.d2 r120=3D\[r20\] - 1656: 80 07 50 1c 21 00 ld2.bias.nta r120=3D\[r20\] - 165c: 00 00 04 00 nop.i 0x0 - 1660: 08 c0 03 28 8e 10 \[MMI\] ld2.bias.nta r120=3D\[r20\] - 1666: 80 07 52 10 21 00 ld2.bias.d4 r120=3D\[r20\] - 166c: 00 00 04 00 nop.i 0x0 - 1670: 08 c0 03 29 8a 10 \[MMI\] ld2.bias.d5 r120=3D\[r20\] - 1676: 80 07 52 18 21 00 ld2.bias.d6 r120=3D\[r20\] - 167c: 00 00 04 00 nop.i 0x0 - 1680: 08 c0 03 29 8e 10 \[MMI\] ld2.bias.d7 r120=3D\[r20\] - 1686: 80 07 50 20 21 00 ld4.bias r120=3D\[r20\] - 168c: 00 00 04 00 nop.i 0x0 - 1690: 08 c0 03 28 92 10 \[MMI\] ld4.bias.nt1 r120=3D\[r20\] - 1696: 80 07 50 24 21 00 ld4.bias.nt1 r120=3D\[r20\] - 169c: 00 00 04 00 nop.i 0x0 - 16a0: 08 c0 03 28 94 10 \[MMI\] ld4.bias.d2 r120=3D\[r20\] - 16a6: 80 07 50 28 21 00 ld4.bias.d2 r120=3D\[r20\] - 16ac: 00 00 04 00 nop.i 0x0 - 16b0: 08 c0 03 28 96 10 \[MMI\] ld4.bias.nta r120=3D\[r20\] - 16b6: 80 07 50 2c 21 00 ld4.bias.nta r120=3D\[r20\] - 16bc: 00 00 04 00 nop.i 0x0 - 16c0: 08 c0 03 29 90 10 \[MMI\] ld4.bias.d4 r120=3D\[r20\] - 16c6: 80 07 52 24 21 00 ld4.bias.d5 r120=3D\[r20\] - 16cc: 00 00 04 00 nop.i 0x0 - 16d0: 08 c0 03 29 94 10 \[MMI\] ld4.bias.d6 r120=3D\[r20\] - 16d6: 80 07 52 2c 21 00 ld4.bias.d7 r120=3D\[r20\] - 16dc: 00 00 04 00 nop.i 0x0 - 16e0: 08 c0 03 28 98 10 \[MMI\] ld8.bias r120=3D\[r20\] - 16e6: 80 07 50 34 21 00 ld8.bias.nt1 r120=3D\[r20\] - 16ec: 00 00 04 00 nop.i 0x0 - 16f0: 08 c0 03 28 9a 10 \[MMI\] ld8.bias.nt1 r120=3D\[r20\] - 16f6: 80 07 50 38 21 00 ld8.bias.d2 r120=3D\[r20\] - 16fc: 00 00 04 00 nop.i 0x0 - 1700: 08 c0 03 28 9c 10 \[MMI\] ld8.bias.d2 r120=3D\[r20\] - 1706: 80 07 50 3c 21 00 ld8.bias.nta r120=3D\[r20\] - 170c: 00 00 04 00 nop.i 0x0 - 1710: 08 c0 03 28 9e 10 \[MMI\] ld8.bias.nta r120=3D\[r20\] - 1716: 80 07 52 30 21 00 ld8.bias.d4 r120=3D\[r20\] - 171c: 00 00 04 00 nop.i 0x0 - 1720: 08 c0 03 29 9a 10 \[MMI\] ld8.bias.d5 r120=3D\[r20\] - 1726: 80 07 52 38 21 00 ld8.bias.d6 r120=3D\[r20\] - 172c: 00 00 04 00 nop.i 0x0 - 1730: 08 c0 03 29 9e 10 \[MMI\] ld8.bias.d7 r120=3D\[r20\] - 1736: 80 07 50 40 21 00 ld1.acq r120=3D\[r20\] - 173c: 00 00 04 00 nop.i 0x0 - 1740: 08 c0 03 28 a2 10 \[MMI\] ld1.acq.nt1 r120=3D\[r20\] - 1746: 80 07 50 44 21 00 ld1.acq.nt1 r120=3D\[r20\] - 174c: 00 00 04 00 nop.i 0x0 - 1750: 08 c0 03 28 a4 10 \[MMI\] ld1.acq.d2 r120=3D\[r20\] - 1756: 80 07 50 48 21 00 ld1.acq.d2 r120=3D\[r20\] - 175c: 00 00 04 00 nop.i 0x0 - 1760: 08 c0 03 28 a6 10 \[MMI\] ld1.acq.nta r120=3D\[r20\] - 1766: 80 07 50 4c 21 00 ld1.acq.nta r120=3D\[r20\] - 176c: 00 00 04 00 nop.i 0x0 - 1770: 08 c0 03 29 a0 10 \[MMI\] ld1.acq.d4 r120=3D\[r20\] - 1776: 80 07 52 44 21 00 ld1.acq.d5 r120=3D\[r20\] - 177c: 00 00 04 00 nop.i 0x0 - 1780: 08 c0 03 29 a4 10 \[MMI\] ld1.acq.d6 r120=3D\[r20\] - 1786: 80 07 50 50 21 00 ld2.acq r120=3D\[r20\] - 178c: 00 00 04 00 nop.i 0x0 - 1790: 08 c0 03 28 aa 10 \[MMI\] ld2.acq.nt1 r120=3D\[r20\] - 1796: 80 07 50 54 21 00 ld2.acq.nt1 r120=3D\[r20\] - 179c: 00 00 04 00 nop.i 0x0 - 17a0: 08 c0 03 28 ac 10 \[MMI\] ld2.acq.d2 r120=3D\[r20\] - 17a6: 80 07 50 58 21 00 ld2.acq.d2 r120=3D\[r20\] - 17ac: 00 00 04 00 nop.i 0x0 - 17b0: 08 c0 03 28 ae 10 \[MMI\] ld2.acq.nta r120=3D\[r20\] - 17b6: 80 07 50 5c 21 00 ld2.acq.nta r120=3D\[r20\] - 17bc: 00 00 04 00 nop.i 0x0 - 17c0: 08 c0 03 29 a8 10 \[MMI\] ld2.acq.d4 r120=3D\[r20\] - 17c6: 80 07 52 54 21 00 ld2.acq.d5 r120=3D\[r20\] - 17cc: 00 00 04 00 nop.i 0x0 - 17d0: 08 c0 03 29 ac 10 \[MMI\] ld2.acq.d6 r120=3D\[r20\] - 17d6: 80 07 52 5c 21 00 ld2.acq.d7 r120=3D\[r20\] - 17dc: 00 00 04 00 nop.i 0x0 - 17e0: 08 c0 03 28 b0 10 \[MMI\] ld4.acq r120=3D\[r20\] - 17e6: 80 07 50 64 21 00 ld4.acq.nt1 r120=3D\[r20\] - 17ec: 00 00 04 00 nop.i 0x0 - 17f0: 08 c0 03 28 b2 10 \[MMI\] ld4.acq.nt1 r120=3D\[r20\] - 17f6: 80 07 50 68 21 00 ld4.acq.d2 r120=3D\[r20\] - 17fc: 00 00 04 00 nop.i 0x0 - 1800: 08 c0 03 28 b4 10 \[MMI\] ld4.acq.d2 r120=3D\[r20\] - 1806: 80 07 50 6c 21 00 ld4.acq.nta r120=3D\[r20\] - 180c: 00 00 04 00 nop.i 0x0 - 1810: 08 c0 03 28 b6 10 \[MMI\] ld4.acq.nta r120=3D\[r20\] - 1816: 80 07 52 60 21 00 ld4.acq.d4 r120=3D\[r20\] - 181c: 00 00 04 00 nop.i 0x0 - 1820: 08 c0 03 29 b2 10 \[MMI\] ld4.acq.d5 r120=3D\[r20\] - 1826: 80 07 52 68 21 00 ld4.acq.d6 r120=3D\[r20\] - 182c: 00 00 04 00 nop.i 0x0 - 1830: 08 c0 03 29 b6 10 \[MMI\] ld4.acq.d7 r120=3D\[r20\] - 1836: 80 07 50 70 21 00 ld8.acq r120=3D\[r20\] - 183c: 00 00 04 00 nop.i 0x0 - 1840: 08 c0 03 28 ba 10 \[MMI\] ld8.acq.nt1 r120=3D\[r20\] - 1846: 80 07 50 74 21 00 ld8.acq.nt1 r120=3D\[r20\] - 184c: 00 00 04 00 nop.i 0x0 - 1850: 08 c0 03 28 bc 10 \[MMI\] ld8.acq.d2 r120=3D\[r20\] - 1856: 80 07 50 78 21 00 ld8.acq.d2 r120=3D\[r20\] - 185c: 00 00 04 00 nop.i 0x0 - 1860: 08 c0 03 28 be 10 \[MMI\] ld8.acq.nta r120=3D\[r20\] - 1866: 80 07 50 7c 21 00 ld8.acq.nta r120=3D\[r20\] - 186c: 00 00 04 00 nop.i 0x0 - 1870: 08 c0 03 29 b8 10 \[MMI\] ld8.acq.d4 r120=3D\[r20\] - 1876: 80 07 52 74 21 00 ld8.acq.d5 r120=3D\[r20\] - 187c: 00 00 04 00 nop.i 0x0 - 1880: 08 c0 03 29 bc 10 \[MMI\] ld8.acq.d6 r120=3D\[r20\] - 1886: 80 07 52 7c 21 00 ld8.acq.d7 r120=3D\[r20\] - 188c: 00 00 04 00 nop.i 0x0 - 1890: 08 c0 03 28 d8 10 \[MMI\] ld8.fill r120=3D\[r20\] - 1896: 80 07 50 b4 21 00 ld8.fill.nt1 r120=3D\[r20\] - 189c: 00 00 04 00 nop.i 0x0 - 18a0: 08 c0 03 28 da 10 \[MMI\] ld8.fill.nt1 r120=3D\[r20\] - 18a6: 80 07 50 b8 21 00 ld8.fill.d2 r120=3D\[r20\] - 18ac: 00 00 04 00 nop.i 0x0 - 18b0: 08 c0 03 28 dc 10 \[MMI\] ld8.fill.d2 r120=3D\[r20\] - 18b6: 80 07 50 bc 21 00 ld8.fill.nta r120=3D\[r20\] - 18bc: 00 00 04 00 nop.i 0x0 - 18c0: 08 c0 03 28 de 10 \[MMI\] ld8.fill.nta r120=3D\[r20\] - 18c6: 80 07 52 b0 21 00 ld8.fill.d4 r120=3D\[r20\] - 18cc: 00 00 04 00 nop.i 0x0 - 18d0: 08 c0 03 29 da 10 \[MMI\] ld8.fill.d5 r120=3D\[r20\] - 18d6: 80 07 52 b8 21 00 ld8.fill.d6 r120=3D\[r20\] - 18dc: 00 00 04 00 nop.i 0x0 - 18e0: 08 c0 03 29 de 10 \[MMI\] ld8.fill.d7 r120=3D\[r20\] - 18e6: 80 07 50 00 22 00 ld1.c.clr r120=3D\[r20\] - 18ec: 00 00 04 00 nop.i 0x0 - 18f0: 08 c0 03 28 02 11 \[MMI\] ld1.c.clr.nt1 r120=3D\[r20\] - 18f6: 80 07 50 04 22 00 ld1.c.clr.nt1 r120=3D\[r20\] - 18fc: 00 00 04 00 nop.i 0x0 - 1900: 08 c0 03 28 04 11 \[MMI\] ld1.c.clr.d2 r120=3D\[r20\] - 1906: 80 07 50 08 22 00 ld1.c.clr.d2 r120=3D\[r20\] - 190c: 00 00 04 00 nop.i 0x0 - 1910: 08 c0 03 28 06 11 \[MMI\] ld1.c.clr.nta r120=3D\[r20\] - 1916: 80 07 50 0c 22 00 ld1.c.clr.nta r120=3D\[r20\] - 191c: 00 00 04 00 nop.i 0x0 - 1920: 08 c0 03 29 00 11 \[MMI\] ld1.c.clr.d4 r120=3D\[r20\] - 1926: 80 07 52 04 22 00 ld1.c.clr.d5 r120=3D\[r20\] - 192c: 00 00 04 00 nop.i 0x0 - 1930: 08 c0 03 29 04 11 \[MMI\] ld1.c.clr.d6 r120=3D\[r20\] - 1936: 80 07 52 0c 22 00 ld1.c.clr.d7 r120=3D\[r20\] - 193c: 00 00 04 00 nop.i 0x0 - 1940: 08 c0 03 28 08 11 \[MMI\] ld2.c.clr r120=3D\[r20\] - 1946: 80 07 50 14 22 00 ld2.c.clr.nt1 r120=3D\[r20\] - 194c: 00 00 04 00 nop.i 0x0 - 1950: 08 c0 03 28 0a 11 \[MMI\] ld2.c.clr.nt1 r120=3D\[r20\] - 1956: 80 07 50 18 22 00 ld2.c.clr.d2 r120=3D\[r20\] - 195c: 00 00 04 00 nop.i 0x0 - 1960: 08 c0 03 28 0c 11 \[MMI\] ld2.c.clr.d2 r120=3D\[r20\] - 1966: 80 07 50 1c 22 00 ld2.c.clr.nta r120=3D\[r20\] - 196c: 00 00 04 00 nop.i 0x0 - 1970: 08 c0 03 28 0e 11 \[MMI\] ld2.c.clr.nta r120=3D\[r20\] - 1976: 80 07 52 10 22 00 ld2.c.clr.d4 r120=3D\[r20\] - 197c: 00 00 04 00 nop.i 0x0 - 1980: 08 c0 03 29 0a 11 \[MMI\] ld2.c.clr.d5 r120=3D\[r20\] - 1986: 80 07 52 18 22 00 ld2.c.clr.d6 r120=3D\[r20\] - 198c: 00 00 04 00 nop.i 0x0 - 1990: 08 c0 03 29 0e 11 \[MMI\] ld2.c.clr.d7 r120=3D\[r20\] - 1996: 80 07 50 20 22 00 ld4.c.clr r120=3D\[r20\] - 199c: 00 00 04 00 nop.i 0x0 - 19a0: 08 c0 03 28 12 11 \[MMI\] ld4.c.clr.nt1 r120=3D\[r20\] - 19a6: 80 07 50 24 22 00 ld4.c.clr.nt1 r120=3D\[r20\] - 19ac: 00 00 04 00 nop.i 0x0 - 19b0: 08 c0 03 28 14 11 \[MMI\] ld4.c.clr.d2 r120=3D\[r20\] - 19b6: 80 07 50 28 22 00 ld4.c.clr.d2 r120=3D\[r20\] - 19bc: 00 00 04 00 nop.i 0x0 - 19c0: 08 c0 03 28 16 11 \[MMI\] ld4.c.clr.nta r120=3D\[r20\] - 19c6: 80 07 50 2c 22 00 ld4.c.clr.nta r120=3D\[r20\] - 19cc: 00 00 04 00 nop.i 0x0 - 19d0: 08 c0 03 29 10 11 \[MMI\] ld4.c.clr.d4 r120=3D\[r20\] - 19d6: 80 07 52 24 22 00 ld4.c.clr.d5 r120=3D\[r20\] - 19dc: 00 00 04 00 nop.i 0x0 - 19e0: 08 c0 03 29 14 11 \[MMI\] ld4.c.clr.d6 r120=3D\[r20\] - 19e6: 80 07 52 2c 22 00 ld4.c.clr.d7 r120=3D\[r20\] - 19ec: 00 00 04 00 nop.i 0x0 - 19f0: 08 c0 03 28 18 11 \[MMI\] ld8.c.clr r120=3D\[r20\] - 19f6: 80 07 50 34 22 00 ld8.c.clr.nt1 r120=3D\[r20\] - 19fc: 00 00 04 00 nop.i 0x0 - 1a00: 08 c0 03 28 1a 11 \[MMI\] ld8.c.clr.nt1 r120=3D\[r20\] - 1a06: 80 07 50 38 22 00 ld8.c.clr.d2 r120=3D\[r20\] - 1a0c: 00 00 04 00 nop.i 0x0 - 1a10: 08 c0 03 28 1c 11 \[MMI\] ld8.c.clr.d2 r120=3D\[r20\] - 1a16: 80 07 50 3c 22 00 ld8.c.clr.nta r120=3D\[r20\] - 1a1c: 00 00 04 00 nop.i 0x0 - 1a20: 08 c0 03 28 1e 11 \[MMI\] ld8.c.clr.nta r120=3D\[r20\] - 1a26: 80 07 52 30 22 00 ld8.c.clr.d4 r120=3D\[r20\] - 1a2c: 00 00 04 00 nop.i 0x0 - 1a30: 08 c0 03 29 1a 11 \[MMI\] ld8.c.clr.d5 r120=3D\[r20\] - 1a36: 80 07 52 38 22 00 ld8.c.clr.d6 r120=3D\[r20\] - 1a3c: 00 00 04 00 nop.i 0x0 - 1a40: 08 c0 03 29 1e 11 \[MMI\] ld8.c.clr.d7 r120=3D\[r20\] - 1a46: 80 07 50 40 22 00 ld1.c.nc r120=3D\[r20\] - 1a4c: 00 00 04 00 nop.i 0x0 - 1a50: 08 c0 03 28 22 11 \[MMI\] ld1.c.nc.nt1 r120=3D\[r20\] - 1a56: 80 07 50 44 22 00 ld1.c.nc.nt1 r120=3D\[r20\] - 1a5c: 00 00 04 00 nop.i 0x0 - 1a60: 08 c0 03 28 24 11 \[MMI\] ld1.c.nc.d2 r120=3D\[r20\] - 1a66: 80 07 50 48 22 00 ld1.c.nc.d2 r120=3D\[r20\] - 1a6c: 00 00 04 00 nop.i 0x0 - 1a70: 08 c0 03 28 26 11 \[MMI\] ld1.c.nc.nta r120=3D\[r20\] - 1a76: 80 07 50 4c 22 00 ld1.c.nc.nta r120=3D\[r20\] - 1a7c: 00 00 04 00 nop.i 0x0 - 1a80: 08 c0 03 29 20 11 \[MMI\] ld1.c.nc.d4 r120=3D\[r20\] - 1a86: 80 07 52 44 22 00 ld1.c.nc.d5 r120=3D\[r20\] - 1a8c: 00 00 04 00 nop.i 0x0 - 1a90: 08 c0 03 29 26 11 \[MMI\] ld1.c.nc.d7 r120=3D\[r20\] - 1a96: 80 07 50 50 22 00 ld2.c.nc r120=3D\[r20\] - 1a9c: 00 00 04 00 nop.i 0x0 - 1aa0: 08 c0 03 28 2a 11 \[MMI\] ld2.c.nc.nt1 r120=3D\[r20\] - 1aa6: 80 07 50 54 22 00 ld2.c.nc.nt1 r120=3D\[r20\] - 1aac: 00 00 04 00 nop.i 0x0 - 1ab0: 08 c0 03 28 2c 11 \[MMI\] ld2.c.nc.d2 r120=3D\[r20\] - 1ab6: 80 07 50 58 22 00 ld2.c.nc.d2 r120=3D\[r20\] - 1abc: 00 00 04 00 nop.i 0x0 - 1ac0: 08 c0 03 28 2e 11 \[MMI\] ld2.c.nc.nta r120=3D\[r20\] - 1ac6: 80 07 50 5c 22 00 ld2.c.nc.nta r120=3D\[r20\] - 1acc: 00 00 04 00 nop.i 0x0 - 1ad0: 08 c0 03 29 28 11 \[MMI\] ld2.c.nc.d4 r120=3D\[r20\] - 1ad6: 80 07 52 54 22 00 ld2.c.nc.d5 r120=3D\[r20\] - 1adc: 00 00 04 00 nop.i 0x0 - 1ae0: 08 c0 03 29 2c 11 \[MMI\] ld2.c.nc.d6 r120=3D\[r20\] - 1ae6: 80 07 52 5c 22 00 ld2.c.nc.d7 r120=3D\[r20\] - 1aec: 00 00 04 00 nop.i 0x0 - 1af0: 08 c0 03 28 30 11 \[MMI\] ld4.c.nc r120=3D\[r20\] - 1af6: 80 07 50 64 22 00 ld4.c.nc.nt1 r120=3D\[r20\] - 1afc: 00 00 04 00 nop.i 0x0 - 1b00: 08 c0 03 28 32 11 \[MMI\] ld4.c.nc.nt1 r120=3D\[r20\] - 1b06: 80 07 50 68 22 00 ld4.c.nc.d2 r120=3D\[r20\] - 1b0c: 00 00 04 00 nop.i 0x0 - 1b10: 08 c0 03 28 34 11 \[MMI\] ld4.c.nc.d2 r120=3D\[r20\] - 1b16: 80 07 50 6c 22 00 ld4.c.nc.nta r120=3D\[r20\] - 1b1c: 00 00 04 00 nop.i 0x0 - 1b20: 08 c0 03 28 36 11 \[MMI\] ld4.c.nc.nta r120=3D\[r20\] - 1b26: 80 07 52 60 22 00 ld4.c.nc.d4 r120=3D\[r20\] - 1b2c: 00 00 04 00 nop.i 0x0 - 1b30: 08 c0 03 29 32 11 \[MMI\] ld4.c.nc.d5 r120=3D\[r20\] - 1b36: 80 07 52 68 22 00 ld4.c.nc.d6 r120=3D\[r20\] - 1b3c: 00 00 04 00 nop.i 0x0 - 1b40: 08 c0 03 29 36 11 \[MMI\] ld4.c.nc.d7 r120=3D\[r20\] - 1b46: 80 07 50 70 22 00 ld8.c.nc r120=3D\[r20\] - 1b4c: 00 00 04 00 nop.i 0x0 - 1b50: 08 c0 03 28 3a 11 \[MMI\] ld8.c.nc.nt1 r120=3D\[r20\] - 1b56: 80 07 50 74 22 00 ld8.c.nc.nt1 r120=3D\[r20\] - 1b5c: 00 00 04 00 nop.i 0x0 - 1b60: 08 c0 03 28 3c 11 \[MMI\] ld8.c.nc.d2 r120=3D\[r20\] - 1b66: 80 07 50 78 22 00 ld8.c.nc.d2 r120=3D\[r20\] - 1b6c: 00 00 04 00 nop.i 0x0 - 1b70: 08 c0 03 28 3e 11 \[MMI\] ld8.c.nc.nta r120=3D\[r20\] - 1b76: 80 07 50 7c 22 00 ld8.c.nc.nta r120=3D\[r20\] - 1b7c: 00 00 04 00 nop.i 0x0 - 1b80: 08 c0 03 29 38 11 \[MMI\] ld8.c.nc.d4 r120=3D\[r20\] - 1b86: 80 07 52 74 22 00 ld8.c.nc.d5 r120=3D\[r20\] - 1b8c: 00 00 04 00 nop.i 0x0 - 1b90: 08 c0 03 29 3c 11 \[MMI\] ld8.c.nc.d6 r120=3D\[r20\] - 1b96: 80 07 52 7c 22 00 ld8.c.nc.d7 r120=3D\[r20\] - 1b9c: 00 00 04 00 nop.i 0x0 - 1ba0: 08 c0 03 28 40 11 \[MMI\] ld1.c.clr.acq r120=3D\[r20\] - 1ba6: 80 07 50 84 22 00 ld1.c.clr.acq.nt1 r120=3D\[r20\] - 1bac: 00 00 04 00 nop.i 0x0 - 1bb0: 08 c0 03 28 42 11 \[MMI\] ld1.c.clr.acq.nt1 r120=3D\[r20\] - 1bb6: 80 07 50 88 22 00 ld1.c.clr.acq.d2 r120=3D\[r20\] - 1bbc: 00 00 04 00 nop.i 0x0 - 1bc0: 08 c0 03 28 44 11 \[MMI\] ld1.c.clr.acq.d2 r120=3D\[r20\] - 1bc6: 80 07 50 8c 22 00 ld1.c.clr.acq.nta r120=3D\[r20\] - 1bcc: 00 00 04 00 nop.i 0x0 - 1bd0: 08 c0 03 28 46 11 \[MMI\] ld1.c.clr.acq.nta r120=3D\[r20\] - 1bd6: 80 07 52 80 22 00 ld1.c.clr.acq.d4 r120=3D\[r20\] - 1bdc: 00 00 04 00 nop.i 0x0 - 1be0: 08 c0 03 29 42 11 \[MMI\] ld1.c.clr.acq.d5 r120=3D\[r20\] - 1be6: 80 07 52 88 22 00 ld1.c.clr.acq.d6 r120=3D\[r20\] - 1bec: 00 00 04 00 nop.i 0x0 - 1bf0: 08 c0 03 29 46 11 \[MMI\] ld1.c.clr.acq.d7 r120=3D\[r20\] - 1bf6: 80 07 50 90 22 00 ld2.c.clr.acq r120=3D\[r20\] - 1bfc: 00 00 04 00 nop.i 0x0 - 1c00: 08 c0 03 28 4a 11 \[MMI\] ld2.c.clr.acq.nt1 r120=3D\[r20\] - 1c06: 80 07 50 94 22 00 ld2.c.clr.acq.nt1 r120=3D\[r20\] - 1c0c: 00 00 04 00 nop.i 0x0 - 1c10: 08 c0 03 28 4c 11 \[MMI\] ld2.c.clr.acq.d2 r120=3D\[r20\] - 1c16: 80 07 50 98 22 00 ld2.c.clr.acq.d2 r120=3D\[r20\] - 1c1c: 00 00 04 00 nop.i 0x0 - 1c20: 08 c0 03 28 4e 11 \[MMI\] ld2.c.clr.acq.nta r120=3D\[r20\] - 1c26: 80 07 52 90 22 00 ld2.c.clr.acq.d4 r120=3D\[r20\] - 1c2c: 00 00 04 00 nop.i 0x0 - 1c30: 08 c0 03 29 4a 11 \[MMI\] ld2.c.clr.acq.d5 r120=3D\[r20\] - 1c36: 80 07 52 98 22 00 ld2.c.clr.acq.d6 r120=3D\[r20\] - 1c3c: 00 00 04 00 nop.i 0x0 - 1c40: 08 c0 03 29 4e 11 \[MMI\] ld2.c.clr.acq.d7 r120=3D\[r20\] - 1c46: 80 07 50 a0 22 00 ld4.c.clr.acq r120=3D\[r20\] - 1c4c: 00 00 04 00 nop.i 0x0 - 1c50: 08 c0 03 28 52 11 \[MMI\] ld4.c.clr.acq.nt1 r120=3D\[r20\] - 1c56: 80 07 50 a4 22 00 ld4.c.clr.acq.nt1 r120=3D\[r20\] - 1c5c: 00 00 04 00 nop.i 0x0 - 1c60: 08 c0 03 28 54 11 \[MMI\] ld4.c.clr.acq.d2 r120=3D\[r20\] - 1c66: 80 07 50 a8 22 00 ld4.c.clr.acq.d2 r120=3D\[r20\] - 1c6c: 00 00 04 00 nop.i 0x0 - 1c70: 08 c0 03 28 56 11 \[MMI\] ld4.c.clr.acq.nta r120=3D\[r20\] - 1c76: 80 07 50 ac 22 00 ld4.c.clr.acq.nta r120=3D\[r20\] - 1c7c: 00 00 04 00 nop.i 0x0 - 1c80: 08 c0 03 29 50 11 \[MMI\] ld4.c.clr.acq.d4 r120=3D\[r20\] - 1c86: 80 07 52 a4 22 00 ld4.c.clr.acq.d5 r120=3D\[r20\] - 1c8c: 00 00 04 00 nop.i 0x0 - 1c90: 08 c0 03 29 54 11 \[MMI\] ld4.c.clr.acq.d6 r120=3D\[r20\] - 1c96: 80 07 52 ac 22 00 ld4.c.clr.acq.d7 r120=3D\[r20\] - 1c9c: 00 00 04 00 nop.i 0x0 - 1ca0: 08 c0 03 28 58 11 \[MMI\] ld8.c.clr.acq r120=3D\[r20\] - 1ca6: 80 07 50 b4 22 00 ld8.c.clr.acq.nt1 r120=3D\[r20\] - 1cac: 00 00 04 00 nop.i 0x0 - 1cb0: 08 c0 03 28 5a 11 \[MMI\] ld8.c.clr.acq.nt1 r120=3D\[r20\] - 1cb6: 80 07 50 b8 22 00 ld8.c.clr.acq.d2 r120=3D\[r20\] - 1cbc: 00 00 04 00 nop.i 0x0 - 1cc0: 08 c0 03 28 5c 11 \[MMI\] ld8.c.clr.acq.d2 r120=3D\[r20\] - 1cc6: 80 07 50 bc 22 00 ld8.c.clr.acq.nta r120=3D\[r20\] - 1ccc: 00 00 04 00 nop.i 0x0 - 1cd0: 08 c0 03 28 5e 11 \[MMI\] ld8.c.clr.acq.nta r120=3D\[r20\] - 1cd6: 80 07 52 b0 22 00 ld8.c.clr.acq.d4 r120=3D\[r20\] - 1cdc: 00 00 04 00 nop.i 0x0 - 1ce0: 08 c0 03 29 5a 11 \[MMI\] ld8.c.clr.acq.d5 r120=3D\[r20\] - 1ce6: 80 07 52 b8 22 00 ld8.c.clr.acq.d6 r120=3D\[r20\] - 1cec: 00 00 04 00 nop.i 0x0 - 1cf0: 08 c0 03 29 5e 11 \[MMI\] ld8.c.clr.acq.d7 r120=3D\[r20\] - 1cf6: 80 07 50 82 22 00 ld16 r120,ar.csd=3D\[r20\] - 1cfc: 00 00 04 00 nop.i 0x0 - 1d00: 08 c0 03 28 41 11 \[MMI\] ld16 r120,ar.csd=3D\[r20\] - 1d06: 80 07 50 86 22 00 ld16.nt1 r120,ar.csd=3D\[r20\] - 1d0c: 00 00 04 00 nop.i 0x0 - 1d10: 08 c0 03 28 43 11 \[MMI\] ld16.nt1 r120,ar.csd=3D\[r20\] - 1d16: 80 07 50 8a 22 00 ld16.d2 r120,ar.csd=3D\[r20\] - 1d1c: 00 00 04 00 nop.i 0x0 - 1d20: 08 c0 03 28 45 11 \[MMI\] ld16.d2 r120,ar.csd=3D\[r20\] - 1d26: 80 07 50 86 22 00 ld16.nt1 r120,ar.csd=3D\[r20\] - 1d2c: 00 00 04 00 nop.i 0x0 - 1d30: 08 c0 03 28 43 11 \[MMI\] ld16.nt1 r120,ar.csd=3D\[r20\] - 1d36: 80 07 50 8a 22 00 ld16.d2 r120,ar.csd=3D\[r20\] - 1d3c: 00 00 04 00 nop.i 0x0 - 1d40: 08 c0 03 28 45 11 \[MMI\] ld16.d2 r120,ar.csd=3D\[r20\] - 1d46: 80 07 50 8e 22 00 ld16.nta r120,ar.csd=3D\[r20\] - 1d4c: 00 00 04 00 nop.i 0x0 - 1d50: 08 c0 03 28 47 11 \[MMI\] ld16.nta r120,ar.csd=3D\[r20\] - 1d56: 80 07 52 82 22 00 ld16.d4 r120,ar.csd=3D\[r20\] - 1d5c: 00 00 04 00 nop.i 0x0 - 1d60: 08 c0 03 29 43 11 \[MMI\] ld16.d5 r120,ar.csd=3D\[r20\] - 1d66: 80 07 52 8a 22 00 ld16.d6 r120,ar.csd=3D\[r20\] - 1d6c: 00 00 04 00 nop.i 0x0 - 1d70: 08 c0 03 29 47 11 \[MMI\] ld16.d7 r120,ar.csd=3D\[r20\] - 1d76: 80 07 50 8e 22 00 ld16.nta r120,ar.csd=3D\[r20\] - 1d7c: 00 00 04 00 nop.i 0x0 - 1d80: 08 c0 03 28 47 11 \[MMI\] ld16.nta r120,ar.csd=3D\[r20\] - 1d86: 80 07 52 82 22 00 ld16.d4 r120,ar.csd=3D\[r20\] - 1d8c: 00 00 04 00 nop.i 0x0 - 1d90: 08 c0 03 29 43 11 \[MMI\] ld16.d5 r120,ar.csd=3D\[r20\] - 1d96: 80 07 52 8a 22 00 ld16.d6 r120,ar.csd=3D\[r20\] - 1d9c: 00 00 04 00 nop.i 0x0 - 1da0: 08 c0 03 29 47 11 \[MMI\] ld16.d7 r120,ar.csd=3D\[r20\] - 1da6: 80 07 50 c2 22 00 ld16.acq r120,ar.csd=3D\[r20\] - 1dac: 00 00 04 00 nop.i 0x0 - 1db0: 08 c0 03 28 61 11 \[MMI\] ld16.acq r120,ar.csd=3D\[r20\] - 1db6: 80 07 50 c6 22 00 ld16.acq.nt1 r120,ar.csd=3D\[r20\] - 1dbc: 00 00 04 00 nop.i 0x0 - 1dc0: 08 c0 03 28 63 11 \[MMI\] ld16.acq.nt1 r120,ar.csd=3D\[r2= 0\] - 1dc6: 80 07 50 ca 22 00 ld16.acq.d2 r120,ar.csd=3D\[r20\] - 1dcc: 00 00 04 00 nop.i 0x0 - 1dd0: 08 c0 03 28 65 11 \[MMI\] ld16.acq.d2 r120,ar.csd=3D\[r20= \] - 1dd6: 80 07 50 c6 22 00 ld16.acq.nt1 r120,ar.csd=3D\[r20\] - 1ddc: 00 00 04 00 nop.i 0x0 - 1de0: 08 c0 03 28 63 11 \[MMI\] ld16.acq.nt1 r120,ar.csd=3D\[r2= 0\] - 1de6: 80 07 50 ca 22 00 ld16.acq.d2 r120,ar.csd=3D\[r20\] - 1dec: 00 00 04 00 nop.i 0x0 - 1df0: 08 c0 03 28 65 11 \[MMI\] ld16.acq.d2 r120,ar.csd=3D\[r20= \] - 1df6: 80 07 50 ce 22 00 ld16.acq.nta r120,ar.csd=3D\[r20\] - 1dfc: 00 00 04 00 nop.i 0x0 - 1e00: 08 c0 03 28 67 11 \[MMI\] ld16.acq.nta r120,ar.csd=3D\[r2= 0\] - 1e06: 80 07 52 c2 22 00 ld16.acq.d4 r120,ar.csd=3D\[r20\] - 1e0c: 00 00 04 00 nop.i 0x0 - 1e10: 08 c0 03 29 63 11 \[MMI\] ld16.acq.d5 r120,ar.csd=3D\[r20= \] - 1e16: 80 07 52 ca 22 00 ld16.acq.d6 r120,ar.csd=3D\[r20\] - 1e1c: 00 00 04 00 nop.i 0x0 - 1e20: 08 c0 03 29 67 11 \[MMI\] ld16.acq.d7 r120,ar.csd=3D\[r20= \] - 1e26: 80 07 50 ce 22 00 ld16.acq.nta r120,ar.csd=3D\[r20\] - 1e2c: 00 00 04 00 nop.i 0x0 - 1e30: 08 c0 03 28 67 11 \[MMI\] ld16.acq.nta r120,ar.csd=3D\[r2= 0\] - 1e36: 80 07 52 c2 22 00 ld16.acq.d4 r120,ar.csd=3D\[r20\] - 1e3c: 00 00 04 00 nop.i 0x0 - 1e40: 08 c0 03 29 63 11 \[MMI\] ld16.acq.d5 r120,ar.csd=3D\[r20= \] - 1e46: 80 07 52 ca 22 00 ld16.acq.d6 r120,ar.csd=3D\[r20\] - 1e4c: 00 00 04 00 nop.i 0x0 - 1e50: 09 c0 03 29 67 11 \[MMI\] ld16.acq.d7 r120,ar.csd=3D\[r20= \] - 1e56: 80 07 50 30 20 00 ld8 r120=3D\[r20\] - 1e5c: 00 00 04 00 nop.i 0x0;; diff --git a/gas/testsuite/gas/ia64/psn.s b/gas/testsuite/gas/ia64/psn.s deleted file mode 100644 index bd2a4ef8289..00000000000 --- a/gas/testsuite/gas/ia64/psn.s +++ /dev/null @@ -1,1018 +0,0 @@ - - lfetch.count [r2], 1, 64 - lfetch.count.d0 [r22], 5, -64 - lfetch.count.nt1 [r23], 9, 1024-64 - lfetch.count.d1 [r122], 12, -1024 - lfetch.count.nt2 [r5], 16, 0x80 - lfetch.count.d2 [r15], 20, -0x100 - lfetch.count.nta [r125], 24, 512 - lfetch.count.d3 [r8], 29, 960 - lfetch.count.d4 [r18], 34, -0x400 - lfetch.count.d5 [r127], 62, 0x3bf - lfetch.count.d6 [r10], 63, -0x3ff - lfetch.count.d7 [r96], 64, 0 - - - - tf.z p1,p2 =3D 32;; - tf.nz p7,p2 =3D @clz;; - tf.z.unc p3,p2 =3D @clz - tf.nz p3,p4 =3D @mpy - tf.z.and p5,p4 =3D @datahints - tf.nz.and p5,p6 =3D 35 - tf.nz.andcm p5,p6 =3D 35 - tf.z.or p7,p6 =3D 63 - tf.nz.or p5,p6 =3D 35 - tf.z.or.andcm p7,p6 =3D @mpy - tf.nz.or.andcm p7,p6 =3D @datahints - tf.z.and.orcm p7,p6 =3D @clz - tf.nz.and.orcm p7,p6 =3D @mpy - - - { .mib - tf.nz.unc p6,p0=3D33=09=09=09 - nop.b 0 ;; - } - lfetch.d4 [r18]=20=09=09=09 - { .mmi - lfetch.fault.excl.d7 [r19] ;;=09=09 - lfetch.count [r14], 2, 128=09=09=09 - sxt4 r8=3Dr10=09=09=09=09=09 - } - { .mmi - lfetch.count.d4 [r11], 64, 256;;=09=09=09 - lfetch.excl.d5 [r17]=09=09=09=09 - nop.i 0 - } - { .mmi - lfetch.fault.d6 [r16] ;;=09=09=09 - mov dahr7=3D7=09=09=09=09=09 - clz r3=3Dr9 ;;=09=09=09=09 - } -=20 - mov dahr6=3D6=09=09=09=09=09 - mpy4 r2=3Dr9,r8=09=09=09=09 - mpyshl4 r2=3Dr9,r8 - - { .mmi - mov dahr5=3D5 ;;=09=09=09=09 - mov dahr4=3D4=09=09=09=09=09 - nop.i 0 ;; - } - { .mib - mov dahr3=3D3=09=09=09=09=09 - add r8=3Dr2,r3=09=09=09=09 - nop.b 0 ;; - } - { .mmi - mov dahr2=3D2 ;;=09=09=09=09 - mov dahr1=3D1=09=09=09=09=09 - nop.i 0 ;; - } - { .mib - mov dahr0=3D0=09=09=09=09=09 - nop.i 0 - } - mov r12 =3D dahr[r5] - mov r122 =3D dahr[r55] - - st1 [ r65 ] =3D r93 - st1.d1 [ r65 ] =3D r93 - st1.nt1 [ r65 ] =3D r93 - st1.d2 [ r65 ] =3D r93 - st1.nt2 [ r65 ] =3D r93 - st1.nta [ r65 ] =3D r93 - st1.d3 [ r65 ] =3D r93 - st1.d4 [ r65 ] =3D r93 - st1.d5 [ r65 ] =3D r93 - st1.d6 [ r65 ] =3D r93 - st1.d7 [ r65 ] =3D r93 - st2 [ r65 ] =3D r93 - st2.d1 [ r65 ] =3D r93 - st2.nt1 [ r65 ] =3D r93 - st2.d2 [ r65 ] =3D r93 - st2.nt2 [ r65 ] =3D r93 - st2.nta [ r65 ] =3D r93 - st2.d3 [ r65 ] =3D r93 - st2.d4 [ r65 ] =3D r93 - st2.d5 [ r65 ] =3D r93 - st2.d6 [ r65 ] =3D r93 - st2.d7 [ r65 ] =3D r93 - st4 [ r65 ] =3D r93 - st4.d1 [ r65 ] =3D r93 - st4.nt1 [ r65 ] =3D r93 - st4.d2 [ r65 ] =3D r93 - st4.nt2 [ r65 ] =3D r93 - st4.nta [ r65 ] =3D r93 - st4.d3 [ r65 ] =3D r93 - st4.d4 [ r65 ] =3D r93 - st4.d5 [ r65 ] =3D r93 - st4.d6 [ r65 ] =3D r93 - st4.d7 [ r65 ] =3D r93 - st8 [ r65 ] =3D r93 - st8.d1 [ r65 ] =3D r93 - st8.nt1 [ r65 ] =3D r93 - st8.d2 [ r65 ] =3D r93 - st8.nt2 [ r65 ] =3D r93 - st8.nta [ r65 ] =3D r93 - st8.d3 [ r65 ] =3D r93 - st8.d4 [ r65 ] =3D r93 - st8.d5 [ r65 ] =3D r93 - st8.d6 [ r65 ] =3D r93 - st8.d7 [ r65 ] =3D r93 - st16 [ r65 ] =3D r93 - st16 [ r65 ] =3D r93 - st16.d1 [ r65 ] =3D r93 - st16.nt1 [ r65 ] =3D r93 - st16.d2 [ r65 ] =3D r93 - st16.nt2 [ r65 ] =3D r93 - st16.nta [ r65 ] =3D r93 - st16.d3 [ r65 ] =3D r93 - st16.d4 [ r65 ] =3D r93 - st16.d5 [ r65 ] =3D r93 - st16.d6 [ r65 ] =3D r93 - st16.d7 [ r65 ] =3D r93 - st16.nta [ r65 ] =3D r93 - st16.d3 [ r65 ] =3D r93 - st16.d4 [ r65 ] =3D r93 - st16.d5 [ r65 ] =3D r93 - st16.d6 [ r65 ] =3D r93 - st16.d7 [ r65 ] =3D r93 - st1.rel [ r65 ] =3D r93 - st1.rel.d1 [ r65 ] =3D r93 - st1.rel.nt1 [ r65 ] =3D r93 - st1.rel.d2 [ r65 ] =3D r93 - st1.rel.nt2 [ r65 ] =3D r93 - st1.rel.nta [ r65 ] =3D r93 - st1.rel.d3 [ r65 ] =3D r93 - st1.rel.d4 [ r65 ] =3D r93 - st1.rel.d5 [ r65 ] =3D r93 - st1.rel.d6 [ r65 ] =3D r93 - st1.rel.d7 [ r65 ] =3D r93 - st2.rel [ r65 ] =3D r93 - st2.rel.d1 [ r65 ] =3D r93 - st2.rel.nt1 [ r65 ] =3D r93 - st2.rel.d2 [ r65 ] =3D r93 - st2.rel.nt2 [ r65 ] =3D r93 - st2.rel.nta [ r65 ] =3D r93 - st2.rel.d3 [ r65 ] =3D r93 - st2.rel.d4 [ r65 ] =3D r93 - st2.rel.d5 [ r65 ] =3D r93 - st2.rel.d6 [ r65 ] =3D r93 - st2.rel.d7 [ r65 ] =3D r93 - st4.rel [ r65 ] =3D r93 - st4.rel.d1 [ r65 ] =3D r93 - st4.rel.nt1 [ r65 ] =3D r93 - st4.rel.d2 [ r65 ] =3D r93 - st4.rel.nt2 [ r65 ] =3D r93 - st4.rel.nta [ r65 ] =3D r93 - st4.rel.d3 [ r65 ] =3D r93 - st4.rel.d4 [ r65 ] =3D r93 - st4.rel.d5 [ r65 ] =3D r93 - st4.rel.d6 [ r65 ] =3D r93 - st4.rel.d7 [ r65 ] =3D r93 - st8.rel [ r65 ] =3D r93 - st8.rel.d1 [ r65 ] =3D r93 - st8.rel.nt1 [ r65 ] =3D r93 - st8.rel.d2 [ r65 ] =3D r93 - st8.rel.nt2 [ r65 ] =3D r93 - st8.rel.nta [ r65 ] =3D r93 - st8.rel.d3 [ r65 ] =3D r93 - st8.rel.d4 [ r65 ] =3D r93 - st8.rel.d5 [ r65 ] =3D r93 - st8.rel.d6 [ r65 ] =3D r93 - st8.rel.d7 [ r65 ] =3D r93 - st16.rel [ r65 ] =3D r93 - st16.rel [ r65 ] =3D r93, ar.csd - st16.rel.d1 [ r65 ] =3D r93 - st16.rel.d1 [ r65 ] =3D r93, ar.csd - st16.rel.nt1 [ r65 ] =3D r93 - st16.rel.nt1 [ r65 ] =3D r93, ar.csd - st16.rel.d2 [ r65 ] =3D r93 - st16.rel.d2 [ r65 ] =3D r93, ar.csd - st16.rel.nt2 [ r65 ] =3D r93 - st16.rel.nt2 [ r65 ] =3D r93, ar.csd - st16.rel.nta [ r65 ] =3D r93 - st16.rel.d3 [ r65 ] =3D r93 - st16.rel.d4 [ r65 ] =3D r93 - st16.rel.d5 [ r65 ] =3D r93 - st16.rel.d6 [ r65 ] =3D r93 - st16.rel.d7 [ r65 ] =3D r93 - st16.rel.nta [ r65 ] =3D r93, ar.csd - st16.rel.d3 [ r65 ] =3D r93, ar.csd - st16.rel.d4 [ r65 ] =3D r93, ar.csd - st16.rel.d5 [ r65 ] =3D r93, ar.csd - st16.rel.d6 [ r65 ] =3D r93, ar.csd - st16.rel.d7 [ r65 ] =3D r93, ar.csd - st8.spill [ r65 ] =3D r93 - st8.spill.d1 [ r65 ] =3D r93 - st8.spill.nt1 [ r65 ] =3D r93 - st8.spill.d2 [ r65 ] =3D r93 - st8.spill.nt2 [ r65 ] =3D r93 - st8.spill.nta [ r65 ] =3D r93 - st8.spill.d3 [ r65 ] =3D r93 - st8.spill.d4 [ r65 ] =3D r93 - st8.spill.d5 [ r65 ] =3D r93 - st8.spill.d6 [ r65 ] =3D r93 - st8.spill.d7 [ r65 ] =3D r93 - - lfetch [ r60 ]=20 - lfetch.d1 [ r60 ]=20 - lfetch.nt1 [ r60 ]=20 - lfetch.d2 [ r60 ]=20 - lfetch.nt2 [ r60 ]=20 - lfetch.nta [ r60 ]=20 - lfetch.d3 [ r60 ]=20 - lfetch.d4 [ r60 ]=20 - lfetch.d5 [ r60 ]=20 - lfetch.d6 [ r60 ]=20 - lfetch.d7 [ r60 ]=20 - - - stfs [ r60 ] =3D f90 - stfs.d1 [ r60 ] =3D f90 - stfs.nt1 [ r60 ] =3D f90 - stfs.d2 [ r60 ] =3D f90 - stfs.nt2 [ r60 ] =3D f90 - stfs.nta [ r60 ] =3D f90 - stfs.d3 [ r60 ] =3D f90 - stfs.d4 [ r60 ] =3D f90 - stfs.d5 [ r60 ] =3D f90 - stfs.d6 [ r60 ] =3D f90 - stfs.d7 [ r60 ] =3D f90 - stfd [ r60 ] =3D f90 - stfd.d1 [ r60 ] =3D f90 - stfd.nt1 [ r60 ] =3D f90 - stfd.d2 [ r60 ] =3D f90 - stfd.nt2 [ r60 ] =3D f90 - stfd.nta [ r60 ] =3D f90 - stfd.d3 [ r60 ] =3D f90 - stfd.d4 [ r60 ] =3D f90 - stfd.d5 [ r60 ] =3D f90 - stfd.d6 [ r60 ] =3D f90 - stfd.d7 [ r60 ] =3D f90 - stf8 [ r60 ] =3D f90 - stf8.d1 [ r60 ] =3D f90 - stf8.nt1 [ r60 ] =3D f90 - stf8.d2 [ r60 ] =3D f90 - stf8.nt2 [ r60 ] =3D f90 - stf8.nta [ r60 ] =3D f90 - stf8.d3 [ r60 ] =3D f90 - stf8.d4 [ r60 ] =3D f90 - stf8.d5 [ r60 ] =3D f90 - stf8.d6 [ r60 ] =3D f90 - stf8.d7 [ r60 ] =3D f90 - stfe [ r60 ] =3D f90 - stfe.d1 [ r60 ] =3D f90 - stfe.nt1 [ r60 ] =3D f90 - stfe.d2 [ r60 ] =3D f90 - stfe.nt2 [ r60 ] =3D f90 - stfe.nta [ r60 ] =3D f90 - stfe.d3 [ r60 ] =3D f90 - stfe.d4 [ r60 ] =3D f90 - stfe.d5 [ r60 ] =3D f90 - stfe.d6 [ r60 ] =3D f90 - stfe.d7 [ r60 ] =3D f90 - stf.spill [ r60 ] =3D f90 - stf.spill.d1 [ r60 ] =3D f90 - stf.spill.nt1 [ r60 ] =3D f90 - stf.spill.d2 [ r60 ] =3D f90 - stf.spill.nt2 [ r60 ] =3D f90 - stf.spill.nta [ r60 ] =3D f90 - stf.spill.d3 [ r60 ] =3D f90 - stf.spill.d4 [ r60 ] =3D f90 - stf.spill.d5 [ r60 ] =3D f90 - stf.spill.d6 [ r60 ] =3D f90 - stf.spill.d7 [ r60 ] =3D f90 - - - /* Floating-point load. */ - ldfs f121 =3D [ r125 ] - ldfs.nt1 f121 =3D [ r125 ] - ldfs.d1 f121 =3D [ r125 ] - ldfs.d2 f121 =3D [ r125 ] - ldfs.nt2 f121 =3D [ r125 ] - ldfs.nta f121 =3D [ r125 ] - ldfs.d3 f121 =3D [ r125 ] - ldfs.d4 f121 =3D [ r125 ] - ldfs.d5 f121 =3D [ r125 ] - ldfs.d6 f121 =3D [ r125 ] - ldfs.d7 f121 =3D [ r125 ] - ldfd f121 =3D [ r125 ] - ldfd.nt1 f121 =3D [ r125 ] - ldfd.d1 f121 =3D [ r125 ] - ldfd.d2 f121 =3D [ r125 ] - ldfd.nt2 f121 =3D [ r125 ] - ldfd.nta f121 =3D [ r125 ] - ldfd.d3 f121 =3D [ r125 ] - ldfd.d4 f121 =3D [ r125 ] - ldfd.d5 f121 =3D [ r125 ] - ldfd.d6 f121 =3D [ r125 ] - ldfd.d7 f121 =3D [ r125 ] - ldf8 f121 =3D [ r125 ] - ldf8.nt1 f121 =3D [ r125 ] - ldf8.d1 f121 =3D [ r125 ] - ldf8.d2 f121 =3D [ r125 ] - ldf8.nt2 f121 =3D [ r125 ] - ldf8.nta f121 =3D [ r125 ] - ldf8.d3 f121 =3D [ r125 ] - ldf8.d4 f121 =3D [ r125 ] - ldf8.d5 f121 =3D [ r125 ] - ldf8.d6 f121 =3D [ r125 ] - ldf8.d7 f121 =3D [ r125 ] - ldfe f121 =3D [ r125 ] - ldfe.nt1 f121 =3D [ r125 ] - ldfe.d1 f121 =3D [ r125 ] - ldfe.d2 f121 =3D [ r125 ] - ldfe.nt2 f121 =3D [ r125 ] - ldfe.nta f121 =3D [ r125 ] - ldfe.d3 f121 =3D [ r125 ] - ldfe.d4 f121 =3D [ r125 ] - ldfe.d5 f121 =3D [ r125 ] - ldfe.d6 f121 =3D [ r125 ] - ldfe.d7 f121 =3D [ r125 ] - ldfs.s f121 =3D [ r125 ] - ldfs.s.nt1 f121 =3D [ r125 ] - ldfs.s.d1 f121 =3D [ r125 ] - ldfs.s.d2 f121 =3D [ r125 ] - ldfs.s.nt2 f121 =3D [ r125 ] - ldfs.s.nta f121 =3D [ r125 ] - ldfs.s.d3 f121 =3D [ r125 ] - ldfs.s.d4 f121 =3D [ r125 ] - ldfs.s.d5 f121 =3D [ r125 ] - ldfs.s.d6 f121 =3D [ r125 ] - ldfs.s.d7 f121 =3D [ r125 ] - ldfd.s f121 =3D [ r125 ] - ldfd.s.nt1 f121 =3D [ r125 ] - ldfd.s.d1 f121 =3D [ r125 ] - ldfd.s.d2 f121 =3D [ r125 ] - ldfd.s.nt2 f121 =3D [ r125 ] - ldfd.s.nta f121 =3D [ r125 ] - ldfd.s.d3 f121 =3D [ r125 ] - ldfd.s.d4 f121 =3D [ r125 ] - ldfd.s.d5 f121 =3D [ r125 ] - ldfd.s.d6 f121 =3D [ r125 ] - ldfd.s.d7 f121 =3D [ r125 ] - ldf8.s f121 =3D [ r125 ] - ldf8.s.nt1 f121 =3D [ r125 ] - ldf8.s.d1 f121 =3D [ r125 ] - ldf8.s.d2 f121 =3D [ r125 ] - ldf8.s.nt2 f121 =3D [ r125 ] - ldf8.s.nta f121 =3D [ r125 ] - ldf8.s.d3 f121 =3D [ r125 ] - ldf8.s.d4 f121 =3D [ r125 ] - ldf8.s.d5 f121 =3D [ r125 ] - ldf8.s.d6 f121 =3D [ r125 ] - ldf8.s.d7 f121 =3D [ r125 ] - ldfe.s f121 =3D [ r125 ] - ldfe.s.nt1 f121 =3D [ r125 ] - ldfe.s.d1 f121 =3D [ r125 ] - ldfe.s.d2 f121 =3D [ r125 ] - ldfe.s.nt2 f121 =3D [ r125 ] - ldfe.s.nta f121 =3D [ r125 ] - ldfe.s.d3 f121 =3D [ r125 ] - ldfe.s.d4 f121 =3D [ r125 ] - ldfe.s.d5 f121 =3D [ r125 ] - ldfe.s.d6 f121 =3D [ r125 ] - ldfe.s.d7 f121 =3D [ r125 ] - ldfs.a f121 =3D [ r125 ] - ldfs.a.nt1 f121 =3D [ r125 ] - ldfs.a.d1 f121 =3D [ r125 ] - ldfs.a.d2 f121 =3D [ r125 ] - ldfs.a.nt2 f121 =3D [ r125 ] - ldfs.a.nta f121 =3D [ r125 ] - ldfs.a.d3 f121 =3D [ r125 ] - ldfs.a.d4 f121 =3D [ r125 ] - ldfs.a.d5 f121 =3D [ r125 ] - ldfs.a.d6 f121 =3D [ r125 ] - ldfs.a.d7 f121 =3D [ r125 ] - ldfd.a f121 =3D [ r125 ] - ldfd.a.nt1 f121 =3D [ r125 ] - ldfd.a.d1 f121 =3D [ r125 ] - ldfd.a.d2 f121 =3D [ r125 ] - ldfd.a.nt2 f121 =3D [ r125 ] - ldfd.a.nta f121 =3D [ r125 ] - ldfd.a.d3 f121 =3D [ r125 ] - ldfd.a.d4 f121 =3D [ r125 ] - ldfd.a.d5 f121 =3D [ r125 ] - ldfd.a.d6 f121 =3D [ r125 ] - ldfd.a.d7 f121 =3D [ r125 ] - ldf8.a f121 =3D [ r125 ] - ldf8.a.nt1 f121 =3D [ r125 ] - ldf8.a.d1 f121 =3D [ r125 ] - ldf8.a.d2 f121 =3D [ r125 ] - ldf8.a.nt2 f121 =3D [ r125 ] - ldf8.a.nta f121 =3D [ r125 ] - ldf8.a.d3 f121 =3D [ r125 ] - ldf8.a.d4 f121 =3D [ r125 ] - ldf8.a.d5 f121 =3D [ r125 ] - ldf8.a.d6 f121 =3D [ r125 ] - ldf8.a.d7 f121 =3D [ r125 ] - ldfe.a f121 =3D [ r125 ] - ldfe.a.nt1 f121 =3D [ r125 ] - ldfe.a.d1 f121 =3D [ r125 ] - ldfe.a.d2 f121 =3D [ r125 ] - ldfe.a.nt2 f121 =3D [ r125 ] - ldfe.a.nta f121 =3D [ r125 ] - ldfe.a.d3 f121 =3D [ r125 ] - ldfe.a.d4 f121 =3D [ r125 ] - ldfe.a.d5 f121 =3D [ r125 ] - ldfe.a.d6 f121 =3D [ r125 ] - ldfe.a.d7 f121 =3D [ r125 ] - ldfs.sa f121 =3D [ r125 ] - ldfs.sa.nt1 f121 =3D [ r125 ] - ldfs.sa.d1 f121 =3D [ r125 ] - ldfs.sa.d2 f121 =3D [ r125 ] - ldfs.sa.nt2 f121 =3D [ r125 ] - ldfs.sa.nta f121 =3D [ r125 ] - ldfs.sa.d3 f121 =3D [ r125 ] - ldfs.sa.d4 f121 =3D [ r125 ] - ldfs.sa.d5 f121 =3D [ r125 ] - ldfs.sa.d6 f121 =3D [ r125 ] - ldfs.sa.d7 f121 =3D [ r125 ] - ldfd.sa f121 =3D [ r125 ] - ldfd.sa.nt1 f121 =3D [ r125 ] - ldfd.sa.d1 f121 =3D [ r125 ] - ldfd.sa.d2 f121 =3D [ r125 ] - ldfd.sa.nt2 f121 =3D [ r125 ] - ldfd.sa.nta f121 =3D [ r125 ] - ldfd.sa.d3 f121 =3D [ r125 ] - ldfd.sa.d4 f121 =3D [ r125 ] - ldfd.sa.d5 f121 =3D [ r125 ] - ldfd.sa.d6 f121 =3D [ r125 ] - ldfd.sa.d7 f121 =3D [ r125 ] - ldf8.sa f121 =3D [ r125 ] - ldf8.sa.nt1 f121 =3D [ r125 ] - ldf8.sa.d1 f121 =3D [ r125 ] - ldf8.sa.d2 f121 =3D [ r125 ] - ldf8.sa.nt2 f121 =3D [ r125 ] - ldf8.sa.nta f121 =3D [ r125 ] - ldf8.sa.d3 f121 =3D [ r125 ] - ldf8.sa.d4 f121 =3D [ r125 ] - ldf8.sa.d5 f121 =3D [ r125 ] - ldf8.sa.d6 f121 =3D [ r125 ] - ldf8.sa.d7 f121 =3D [ r125 ] - ldfe.sa f121 =3D [ r125 ] - ldfe.sa.nt1 f121 =3D [ r125 ] - ldfe.sa.d1 f121 =3D [ r125 ] - ldfe.sa.d2 f121 =3D [ r125 ] - ldfe.sa.nt2 f121 =3D [ r125 ] - ldfe.sa.nta f121 =3D [ r125 ] - ldfe.sa.d3 f121 =3D [ r125 ] - ldfe.sa.d4 f121 =3D [ r125 ] - ldfe.sa.d5 f121 =3D [ r125 ] - ldfe.sa.d6 f121 =3D [ r125 ] - ldfe.sa.d7 f121 =3D [ r125 ] - ldf.fill f121 =3D [ r125 ] - ldf.fill.nt1 f121 =3D [ r125 ] - ldf.fill.d1 f121 =3D [ r125 ] - ldf.fill.d2 f121 =3D [ r125 ] - ldf.fill.nt2 f121 =3D [ r125 ] - ldf.fill.nta f121 =3D [ r125 ] - ldf.fill.d3 f121 =3D [ r125 ] - ldf.fill.d4 f121 =3D [ r125 ] - ldf.fill.d5 f121 =3D [ r125 ] - ldf.fill.d6 f121 =3D [ r125 ] - ldf.fill.d7 f121 =3D [ r125 ] - ldfs.c.clr f121 =3D [ r125 ] - ldfs.c.clr.nt1 f121 =3D [ r125 ] - ldfs.c.clr.d1 f121 =3D [ r125 ] - ldfs.c.clr.d2 f121 =3D [ r125 ] - ldfs.c.clr.nt2 f121 =3D [ r125 ] - ldfs.c.clr.nta f121 =3D [ r125 ] - ldfs.c.clr.d3 f121 =3D [ r125 ] - ldfs.c.clr.d4 f121 =3D [ r125 ] - ldfs.c.clr.d5 f121 =3D [ r125 ] - ldfs.c.clr.d6 f121 =3D [ r125 ] - ldfs.c.clr.d7 f121 =3D [ r125 ] - ldfd.c.clr f121 =3D [ r125 ] - ldfd.c.clr.nt1 f121 =3D [ r125 ] - ldfd.c.clr.d1 f121 =3D [ r125 ] - ldfd.c.clr.d2 f121 =3D [ r125 ] - ldfd.c.clr.nt2 f121 =3D [ r125 ] - ldfd.c.clr.nta f121 =3D [ r125 ] - ldfd.c.clr.d3 f121 =3D [ r125 ] - ldfd.c.clr.d4 f121 =3D [ r125 ] - ldfd.c.clr.d5 f121 =3D [ r125 ] - ldfd.c.clr.d6 f121 =3D [ r125 ] - ldfd.c.clr.d7 f121 =3D [ r125 ] - ldf8.c.clr f121 =3D [ r125 ] - ldf8.c.clr.nt1 f121 =3D [ r125 ] - ldf8.c.clr.d1 f121 =3D [ r125 ] - ldf8.c.clr.d2 f121 =3D [ r125 ] - ldf8.c.clr.nt2 f121 =3D [ r125 ] - ldf8.c.clr.nta f121 =3D [ r125 ] - ldf8.c.clr.d3 f121 =3D [ r125 ] - ldf8.c.clr.d4 f121 =3D [ r125 ] - ldf8.c.clr.d5 f121 =3D [ r125 ] - ldf8.c.clr.d6 f121 =3D [ r125 ] - ldf8.c.clr.d7 f121 =3D [ r125 ] - ldfe.c.clr f121 =3D [ r125 ] - ldfe.c.clr.nt1 f121 =3D [ r125 ] - ldfe.c.clr.d1 f121 =3D [ r125 ] - ldfe.c.clr.d2 f121 =3D [ r125 ] - ldfe.c.clr.nt2 f121 =3D [ r125 ] - ldfe.c.clr.nta f121 =3D [ r125 ] - ldfe.c.clr.d3 f121 =3D [ r125 ] - ldfe.c.clr.d4 f121 =3D [ r125 ] - ldfe.c.clr.d5 f121 =3D [ r125 ] - ldfe.c.clr.d6 f121 =3D [ r125 ] - ldfe.c.clr.d7 f121 =3D [ r125 ] - ldfs.c.nc f121 =3D [ r125 ] - ldfs.c.nc.nt1 f121 =3D [ r125 ] - ldfs.c.nc.d1 f121 =3D [ r125 ] - ldfs.c.nc.d2 f121 =3D [ r125 ] - ldfs.c.nc.nt2 f121 =3D [ r125 ] - ldfs.c.nc.nta f121 =3D [ r125 ] - ldfs.c.nc.d3 f121 =3D [ r125 ] - ldfs.c.nc.d4 f121 =3D [ r125 ] - ldfs.c.nc.d5 f121 =3D [ r125 ] - ldfs.c.nc.d6 f121 =3D [ r125 ] - ldfs.c.nc.d7 f121 =3D [ r125 ] - ldfd.c.nc f121 =3D [ r125 ] - ldfd.c.nc.nt1 f121 =3D [ r125 ] - ldfd.c.nc.d1 f121 =3D [ r125 ] - ldfd.c.nc.d2 f121 =3D [ r125 ] - ldfd.c.nc.nt2 f121 =3D [ r125 ] - ldfd.c.nc.nta f121 =3D [ r125 ] - ldfd.c.nc.d3 f121 =3D [ r125 ] - ldfd.c.nc.d4 f121 =3D [ r125 ] - ldfd.c.nc.d5 f121 =3D [ r125 ] - ldfd.c.nc.d6 f121 =3D [ r125 ] - ldfd.c.nc.d7 f121 =3D [ r125 ] - ldf8.c.nc f121 =3D [ r125 ] - ldf8.c.nc.nt1 f121 =3D [ r125 ] - ldf8.c.nc.d1 f121 =3D [ r125 ] - ldf8.c.nc.d2 f121 =3D [ r125 ] - ldf8.c.nc.nt2 f121 =3D [ r125 ] - ldf8.c.nc.nta f121 =3D [ r125 ] - ldf8.c.nc.d3 f121 =3D [ r125 ] - ldf8.c.nc.d4 f121 =3D [ r125 ] - ldf8.c.nc.d5 f121 =3D [ r125 ] - ldf8.c.nc.d6 f121 =3D [ r125 ] - ldf8.c.nc.d7 f121 =3D [ r125 ] - ldfe.c.nc f121 =3D [ r125 ] - ldfe.c.nc.nt1 f121 =3D [ r125 ] - ldfe.c.nc.d1 f121 =3D [ r125 ] - ldfe.c.nc.d2 f121 =3D [ r125 ] - ldfe.c.nc.nt2 f121 =3D [ r125 ] - ldfe.c.nc.nta f121 =3D [ r125 ] - ldfe.c.nc.d3 f121 =3D [ r125 ] - ldfe.c.nc.d4 f121 =3D [ r125 ] - ldfe.c.nc.d5 f121 =3D [ r125 ] - ldfe.c.nc.d6 f121 =3D [ r125 ] - ldfe.c.nc.d7 f121 =3D [ r125 ] - - - - - ld1 r120 =3D [ r20 ] - ld1.nt1 r120 =3D [ r20 ] - ld1.d1 r120 =3D [ r20 ] - ld1.d2 r120 =3D [ r20 ] - ld1.nt2 r120 =3D [ r20 ] - ld1.nta r120 =3D [ r20 ] - ld1.d3 r120 =3D [ r20 ] - ld1.d4 r120 =3D [ r20 ] - ld1.d5 r120 =3D [ r20 ] - ld1.d6 r120 =3D [ r20 ] - ld1.d7 r120 =3D [ r20 ] - ld2 r120 =3D [ r20 ] - ld2.nt1 r120 =3D [ r20 ] - ld2.d1 r120 =3D [ r20 ] - ld2.d2 r120 =3D [ r20 ] - ld2.nt2 r120 =3D [ r20 ] - ld2.nta r120 =3D [ r20 ] - ld2.d3 r120 =3D [ r20 ] - ld2.d4 r120 =3D [ r20 ] - ld2.d5 r120 =3D [ r20 ] - ld2.d6 r120 =3D [ r20 ] - ld2.d7 r120 =3D [ r20 ] - ld4 r120 =3D [ r20 ] - ld4.nt1 r120 =3D [ r20 ] - ld4.d1 r120 =3D [ r20 ] - ld4.d2 r120 =3D [ r20 ] - ld4.nt2 r120 =3D [ r20 ] - ld4.nta r120 =3D [ r20 ] - ld4.d3 r120 =3D [ r20 ] - ld4.d4 r120 =3D [ r20 ] - ld4.d5 r120 =3D [ r20 ] - ld4.d6 r120 =3D [ r20 ] - ld4.d7 r120 =3D [ r20 ] - ld8 r120 =3D [ r20 ] - ld8.nt1 r120 =3D [ r20 ] - ld8.d1 r120 =3D [ r20 ] - ld8.d2 r120 =3D [ r20 ] - ld8.nt2 r120 =3D [ r20 ] - ld8.nta r120 =3D [ r20 ] - ld8.d3 r120 =3D [ r20 ] - ld8.d4 r120 =3D [ r20 ] - ld8.d5 r120 =3D [ r20 ] - ld8.d6 r120 =3D [ r20 ] - ld8.d7 r120 =3D [ r20 ] - ld1.s r120 =3D [ r20 ] - ld1.s.nt1 r120 =3D [ r20 ] - ld1.s.d1 r120 =3D [ r20 ] - ld1.s.d2 r120 =3D [ r20 ] - ld1.s.nt2 r120 =3D [ r20 ] - ld1.s.nta r120 =3D [ r20 ] - ld1.s.d3 r120 =3D [ r20 ] - ld1.s.d4 r120 =3D [ r20 ] - ld1.s.d5 r120 =3D [ r20 ] - ld1.s.d6 r120 =3D [ r20 ] - ld1.s.d7 r120 =3D [ r20 ] - ld2.s r120 =3D [ r20 ] - ld2.s.nt1 r120 =3D [ r20 ] - ld2.s.d1 r120 =3D [ r20 ] - ld2.s.d2 r120 =3D [ r20 ] - ld2.s.nt2 r120 =3D [ r20 ] - ld2.s.nta r120 =3D [ r20 ] - ld2.s.d3 r120 =3D [ r20 ] - ld2.s.d4 r120 =3D [ r20 ] - ld2.s.d5 r120 =3D [ r20 ] - ld2.s.d6 r120 =3D [ r20 ] - ld2.s.d7 r120 =3D [ r20 ] - ld4.s r120 =3D [ r20 ] - ld4.s.nt1 r120 =3D [ r20 ] - ld4.s.d1 r120 =3D [ r20 ] - ld4.s.d2 r120 =3D [ r20 ] - ld4.s.nt2 r120 =3D [ r20 ] - ld4.s.nta r120 =3D [ r20 ] - ld4.s.d3 r120 =3D [ r20 ] - ld4.s.d4 r120 =3D [ r20 ] - ld4.s.d5 r120 =3D [ r20 ] - ld4.s.d6 r120 =3D [ r20 ] - ld4.s.d7 r120 =3D [ r20 ] - ld8.s r120 =3D [ r20 ] - ld8.s.nt1 r120 =3D [ r20 ] - ld8.s.d1 r120 =3D [ r20 ] - ld8.s.d2 r120 =3D [ r20 ] - ld8.s.nt2 r120 =3D [ r20 ] - ld8.s.nta r120 =3D [ r20 ] - ld8.s.d3 r120 =3D [ r20 ] - ld8.s.d4 r120 =3D [ r20 ] - ld8.s.d5 r120 =3D [ r20 ] - ld8.s.d6 r120 =3D [ r20 ] - ld8.s.d7 r120 =3D [ r20 ] - ld1.a r120 =3D [ r20 ] - ld1.a.nt1 r120 =3D [ r20 ] - ld1.a.d1 r120 =3D [ r20 ] - ld1.a.d2 r120 =3D [ r20 ] - ld1.a.nt2 r120 =3D [ r20 ] - ld1.a.nta r120 =3D [ r20 ] - ld1.a.d3 r120 =3D [ r20 ] - ld1.a.d4 r120 =3D [ r20 ] - ld1.a.d5 r120 =3D [ r20 ] - ld1.a.d6 r120 =3D [ r20 ] - ld1.a.d7 r120 =3D [ r20 ] - ld2.a r120 =3D [ r20 ] - ld2.a.nt1 r120 =3D [ r20 ] - ld2.a.d1 r120 =3D [ r20 ] - ld2.a.nt2 r120 =3D [ r20 ] - ld2.a.nta r120 =3D [ r20 ] - ld2.a.d3 r120 =3D [ r20 ] - ld2.a.d4 r120 =3D [ r20 ] - ld2.a.d5 r120 =3D [ r20 ] - ld2.a.d6 r120 =3D [ r20 ] - ld2.a.d7 r120 =3D [ r20 ] - ld4.a r120 =3D [ r20 ] - ld4.a.nt1 r120 =3D [ r20 ] - ld4.a.d1 r120 =3D [ r20 ] - ld4.a.d2 r120 =3D [ r20 ] - ld4.a.nt2 r120 =3D [ r20 ] - ld4.a.nta r120 =3D [ r20 ] - ld4.a.d3 r120 =3D [ r20 ] - ld4.a.d4 r120 =3D [ r20 ] - ld4.a.d5 r120 =3D [ r20 ] - ld4.a.d6 r120 =3D [ r20 ] - ld4.a.d7 r120 =3D [ r20 ] - ld8.a r120 =3D [ r20 ] - ld8.a.nt1 r120 =3D [ r20 ] - ld8.a.d1 r120 =3D [ r20 ] - ld8.a.d2 r120 =3D [ r20 ] - ld8.a.nt2 r120 =3D [ r20 ] - ld8.a.nta r120 =3D [ r20 ] - ld8.a.d3 r120 =3D [ r20 ] - ld8.a.d5 r120 =3D [ r20 ] - ld8.a.d6 r120 =3D [ r20 ] - ld8.a.d7 r120 =3D [ r20 ] - ld1.sa r120 =3D [ r20 ] - ld1.sa.nt1 r120 =3D [ r20 ] - ld1.sa.d1 r120 =3D [ r20 ] - ld1.sa.d2 r120 =3D [ r20 ] - ld1.sa.nt2 r120 =3D [ r20 ] - ld1.sa.nta r120 =3D [ r20 ] - ld1.sa.d3 r120 =3D [ r20 ] - ld1.sa.d4 r120 =3D [ r20 ] - ld1.sa.d5 r120 =3D [ r20 ] - ld1.sa.d6 r120 =3D [ r20 ] - ld1.sa.d7 r120 =3D [ r20 ] - ld2.sa r120 =3D [ r20 ] - ld2.sa.nt1 r120 =3D [ r20 ] - ld2.sa.d1 r120 =3D [ r20 ] - ld2.sa.d2 r120 =3D [ r20 ] - ld2.sa.nt2 r120 =3D [ r20 ] - ld2.sa.nta r120 =3D [ r20 ] - ld2.sa.d3 r120 =3D [ r20 ] - ld2.sa.d4 r120 =3D [ r20 ] - ld2.sa.d5 r120 =3D [ r20 ] - ld2.sa.d6 r120 =3D [ r20 ] - ld2.sa.d7 r120 =3D [ r20 ] - ld4.sa.nt1 r120 =3D [ r20 ] - ld4.sa.d1 r120 =3D [ r20 ] - ld4.sa.d2 r120 =3D [ r20 ] - ld4.sa.nt2 r120 =3D [ r20 ] - ld4.sa.nta r120 =3D [ r20 ] - ld4.sa.d3 r120 =3D [ r20 ] - ld4.sa.d4 r120 =3D [ r20 ] - ld4.sa.d5 r120 =3D [ r20 ] - ld4.sa.d6 r120 =3D [ r20 ] - ld4.sa.d7 r120 =3D [ r20 ] - ld8.sa r120 =3D [ r20 ] - ld8.sa.nt1 r120 =3D [ r20 ] - ld8.sa.d1 r120 =3D [ r20 ] - ld8.sa.d2 r120 =3D [ r20 ] - ld8.sa.nt2 r120 =3D [ r20 ] - ld8.sa.nta r120 =3D [ r20 ] - ld8.sa.d3 r120 =3D [ r20 ] - ld8.sa.d4 r120 =3D [ r20 ] - ld8.sa.d5 r120 =3D [ r20 ] - ld8.sa.d6 r120 =3D [ r20 ] - ld8.sa.d7 r120 =3D [ r20 ] - ld1.bias r120 =3D [ r20 ] - ld1.bias.nt1 r120 =3D [ r20 ] - ld1.bias.d1 r120 =3D [ r20 ] - ld1.bias.d2 r120 =3D [ r20 ] - ld1.bias.nt2 r120 =3D [ r20 ] - ld1.bias.nta r120 =3D [ r20 ] - ld1.bias.d3 r120 =3D [ r20 ] - ld1.bias.d4 r120 =3D [ r20 ] - ld1.bias.d5 r120 =3D [ r20 ] - ld1.bias.d6 r120 =3D [ r20 ] - ld1.bias.d7 r120 =3D [ r20 ] - ld2.bias r120 =3D [ r20 ] - ld2.bias.nt1 r120 =3D [ r20 ] - ld2.bias.d1 r120 =3D [ r20 ] - ld2.bias.d2 r120 =3D [ r20 ] - ld2.bias.nt2 r120 =3D [ r20 ] - ld2.bias.nta r120 =3D [ r20 ] - ld2.bias.d3 r120 =3D [ r20 ] - ld2.bias.d4 r120 =3D [ r20 ] - ld2.bias.d5 r120 =3D [ r20 ] - ld2.bias.d6 r120 =3D [ r20 ] - ld2.bias.d7 r120 =3D [ r20 ] - ld4.bias r120 =3D [ r20 ] - ld4.bias.nt1 r120 =3D [ r20 ] - ld4.bias.d1 r120 =3D [ r20 ] - ld4.bias.d2 r120 =3D [ r20 ] - ld4.bias.nt2 r120 =3D [ r20 ] - ld4.bias.nta r120 =3D [ r20 ] - ld4.bias.d3 r120 =3D [ r20 ] - ld4.bias.d4 r120 =3D [ r20 ] - ld4.bias.d5 r120 =3D [ r20 ] - ld4.bias.d6 r120 =3D [ r20 ] - ld4.bias.d7 r120 =3D [ r20 ] - ld8.bias r120 =3D [ r20 ] - ld8.bias.nt1 r120 =3D [ r20 ] - ld8.bias.d1 r120 =3D [ r20 ] - ld8.bias.d2 r120 =3D [ r20 ] - ld8.bias.nt2 r120 =3D [ r20 ] - ld8.bias.nta r120 =3D [ r20 ] - ld8.bias.d3 r120 =3D [ r20 ] - ld8.bias.d4 r120 =3D [ r20 ] - ld8.bias.d5 r120 =3D [ r20 ] - ld8.bias.d6 r120 =3D [ r20 ] - ld8.bias.d7 r120 =3D [ r20 ] - ld1.acq r120 =3D [ r20 ] - ld1.acq.nt1 r120 =3D [ r20 ] - ld1.acq.d1 r120 =3D [ r20 ] - ld1.acq.d2 r120 =3D [ r20 ] - ld1.acq.nt2 r120 =3D [ r20 ] - ld1.acq.nta r120 =3D [ r20 ] - ld1.acq.d3 r120 =3D [ r20 ] - ld1.acq.d4 r120 =3D [ r20 ] - ld1.acq.d5 r120 =3D [ r20 ] - ld1.acq.d6 r120 =3D [ r20 ] - ld2.acq r120 =3D [ r20 ] - ld2.acq.nt1 r120 =3D [ r20 ] - ld2.acq.d1 r120 =3D [ r20 ] - ld2.acq.d2 r120 =3D [ r20 ] - ld2.acq.nt2 r120 =3D [ r20 ] - ld2.acq.nta r120 =3D [ r20 ] - ld2.acq.d3 r120 =3D [ r20 ] - ld2.acq.d4 r120 =3D [ r20 ] - ld2.acq.d5 r120 =3D [ r20 ] - ld2.acq.d6 r120 =3D [ r20 ] - ld2.acq.d7 r120 =3D [ r20 ] - ld4.acq r120 =3D [ r20 ] - ld4.acq.nt1 r120 =3D [ r20 ] - ld4.acq.d1 r120 =3D [ r20 ] - ld4.acq.d2 r120 =3D [ r20 ] - ld4.acq.nt2 r120 =3D [ r20 ] - ld4.acq.nta r120 =3D [ r20 ] - ld4.acq.d3 r120 =3D [ r20 ] - ld4.acq.d4 r120 =3D [ r20 ] - ld4.acq.d5 r120 =3D [ r20 ] - ld4.acq.d6 r120 =3D [ r20 ] - ld4.acq.d7 r120 =3D [ r20 ] - ld8.acq r120 =3D [ r20 ] - ld8.acq.nt1 r120 =3D [ r20 ] - ld8.acq.d1 r120 =3D [ r20 ] - ld8.acq.d2 r120 =3D [ r20 ] - ld8.acq.nt2 r120 =3D [ r20 ] - ld8.acq.nta r120 =3D [ r20 ] - ld8.acq.d3 r120 =3D [ r20 ] - ld8.acq.d4 r120 =3D [ r20 ] - ld8.acq.d5 r120 =3D [ r20 ] - ld8.acq.d6 r120 =3D [ r20 ] - ld8.acq.d7 r120 =3D [ r20 ] - ld8.fill r120 =3D [ r20 ] - ld8.fill.nt1 r120 =3D [ r20 ] - ld8.fill.d1 r120 =3D [ r20 ] - ld8.fill.d2 r120 =3D [ r20 ] - ld8.fill.nt2 r120 =3D [ r20 ] - ld8.fill.nta r120 =3D [ r20 ] - ld8.fill.d3 r120 =3D [ r20 ] - ld8.fill.d4 r120 =3D [ r20 ] - ld8.fill.d5 r120 =3D [ r20 ] - ld8.fill.d6 r120 =3D [ r20 ] - ld8.fill.d7 r120 =3D [ r20 ] - ld1.c.clr r120 =3D [ r20 ] - ld1.c.clr.nt1 r120 =3D [ r20 ] - ld1.c.clr.d1 r120 =3D [ r20 ] - ld1.c.clr.d2 r120 =3D [ r20 ] - ld1.c.clr.nt2 r120 =3D [ r20 ] - ld1.c.clr.nta r120 =3D [ r20 ] - ld1.c.clr.d3 r120 =3D [ r20 ] - ld1.c.clr.d4 r120 =3D [ r20 ] - ld1.c.clr.d5 r120 =3D [ r20 ] - ld1.c.clr.d6 r120 =3D [ r20 ] - ld1.c.clr.d7 r120 =3D [ r20 ] - ld2.c.clr r120 =3D [ r20 ] - ld2.c.clr.nt1 r120 =3D [ r20 ] - ld2.c.clr.d1 r120 =3D [ r20 ] - ld2.c.clr.d2 r120 =3D [ r20 ] - ld2.c.clr.nt2 r120 =3D [ r20 ] - ld2.c.clr.nta r120 =3D [ r20 ] - ld2.c.clr.d3 r120 =3D [ r20 ] - ld2.c.clr.d4 r120 =3D [ r20 ] - ld2.c.clr.d5 r120 =3D [ r20 ] - ld2.c.clr.d6 r120 =3D [ r20 ] - ld2.c.clr.d7 r120 =3D [ r20 ] - ld4.c.clr r120 =3D [ r20 ] - ld4.c.clr.nt1 r120 =3D [ r20 ] - ld4.c.clr.d1 r120 =3D [ r20 ] - ld4.c.clr.d2 r120 =3D [ r20 ] - ld4.c.clr.nt2 r120 =3D [ r20 ] - ld4.c.clr.nta r120 =3D [ r20 ] - ld4.c.clr.d3 r120 =3D [ r20 ] - ld4.c.clr.d4 r120 =3D [ r20 ] - ld4.c.clr.d5 r120 =3D [ r20 ] - ld4.c.clr.d6 r120 =3D [ r20 ] - ld4.c.clr.d7 r120 =3D [ r20 ] - ld8.c.clr r120 =3D [ r20 ] - ld8.c.clr.nt1 r120 =3D [ r20 ] - ld8.c.clr.d1 r120 =3D [ r20 ] - ld8.c.clr.d2 r120 =3D [ r20 ] - ld8.c.clr.nt2 r120 =3D [ r20 ] - ld8.c.clr.nta r120 =3D [ r20 ] - ld8.c.clr.d3 r120 =3D [ r20 ] - ld8.c.clr.d4 r120 =3D [ r20 ] - ld8.c.clr.d5 r120 =3D [ r20 ] - ld8.c.clr.d6 r120 =3D [ r20 ] - ld8.c.clr.d7 r120 =3D [ r20 ] - ld1.c.nc r120 =3D [ r20 ] - ld1.c.nc.nt1 r120 =3D [ r20 ] - ld1.c.nc.d1 r120 =3D [ r20 ] - ld1.c.nc.d2 r120 =3D [ r20 ] - ld1.c.nc.nt2 r120 =3D [ r20 ] - ld1.c.nc.nta r120 =3D [ r20 ] - ld1.c.nc.d3 r120 =3D [ r20 ] - ld1.c.nc.d4 r120 =3D [ r20 ] - ld1.c.nc.d5 r120 =3D [ r20 ] - ld1.c.nc.d7 r120 =3D [ r20 ] - ld2.c.nc r120 =3D [ r20 ] - ld2.c.nc.nt1 r120 =3D [ r20 ] - ld2.c.nc.d1 r120 =3D [ r20 ] - ld2.c.nc.d2 r120 =3D [ r20 ] - ld2.c.nc.nt2 r120 =3D [ r20 ] - ld2.c.nc.nta r120 =3D [ r20 ] - ld2.c.nc.d3 r120 =3D [ r20 ] - ld2.c.nc.d4 r120 =3D [ r20 ] - ld2.c.nc.d5 r120 =3D [ r20 ] - ld2.c.nc.d6 r120 =3D [ r20 ] - ld2.c.nc.d7 r120 =3D [ r20 ] - ld4.c.nc r120 =3D [ r20 ] - ld4.c.nc.nt1 r120 =3D [ r20 ] - ld4.c.nc.d1 r120 =3D [ r20 ] - ld4.c.nc.d2 r120 =3D [ r20 ] - ld4.c.nc.nt2 r120 =3D [ r20 ] - ld4.c.nc.nta r120 =3D [ r20 ] - ld4.c.nc.d3 r120 =3D [ r20 ] - ld4.c.nc.d4 r120 =3D [ r20 ] - ld4.c.nc.d5 r120 =3D [ r20 ] - ld4.c.nc.d6 r120 =3D [ r20 ] - ld4.c.nc.d7 r120 =3D [ r20 ] - ld8.c.nc r120 =3D [ r20 ] - ld8.c.nc.nt1 r120 =3D [ r20 ] - ld8.c.nc.d1 r120 =3D [ r20 ] - ld8.c.nc.d2 r120 =3D [ r20 ] - ld8.c.nc.nt2 r120 =3D [ r20 ] - ld8.c.nc.nta r120 =3D [ r20 ] - ld8.c.nc.d3 r120 =3D [ r20 ] - ld8.c.nc.d4 r120 =3D [ r20 ] - ld8.c.nc.d5 r120 =3D [ r20 ] - ld8.c.nc.d6 r120 =3D [ r20 ] - ld8.c.nc.d7 r120 =3D [ r20 ] - ld1.c.clr.acq r120 =3D [ r20 ] - ld1.c.clr.acq.nt1 r120 =3D [ r20 ] - ld1.c.clr.acq.d1 r120 =3D [ r20 ] - ld1.c.clr.acq.d2 r120 =3D [ r20 ] - ld1.c.clr.acq.nt2 r120 =3D [ r20 ] - ld1.c.clr.acq.nta r120 =3D [ r20 ] - ld1.c.clr.acq.d3 r120 =3D [ r20 ] - ld1.c.clr.acq.d4 r120 =3D [ r20 ] - ld1.c.clr.acq.d5 r120 =3D [ r20 ] - ld1.c.clr.acq.d6 r120 =3D [ r20 ] - ld1.c.clr.acq.d7 r120 =3D [ r20 ] - ld2.c.clr.acq r120 =3D [ r20 ] - ld2.c.clr.acq.nt1 r120 =3D [ r20 ] - ld2.c.clr.acq.d1 r120 =3D [ r20 ] - ld2.c.clr.acq.d2 r120 =3D [ r20 ] - ld2.c.clr.acq.nt2 r120 =3D [ r20 ] - ld2.c.clr.acq.d3 r120 =3D [ r20 ] - ld2.c.clr.acq.d4 r120 =3D [ r20 ] - ld2.c.clr.acq.d5 r120 =3D [ r20 ] - ld2.c.clr.acq.d6 r120 =3D [ r20 ] - ld2.c.clr.acq.d7 r120 =3D [ r20 ] - ld4.c.clr.acq r120 =3D [ r20 ] - ld4.c.clr.acq.nt1 r120 =3D [ r20 ] - ld4.c.clr.acq.d1 r120 =3D [ r20 ] - ld4.c.clr.acq.d2 r120 =3D [ r20 ] - ld4.c.clr.acq.nt2 r120 =3D [ r20 ] - ld4.c.clr.acq.nta r120 =3D [ r20 ] - ld4.c.clr.acq.d3 r120 =3D [ r20 ] - ld4.c.clr.acq.d4 r120 =3D [ r20 ] - ld4.c.clr.acq.d5 r120 =3D [ r20 ] - ld4.c.clr.acq.d6 r120 =3D [ r20 ] - ld4.c.clr.acq.d7 r120 =3D [ r20 ] - ld8.c.clr.acq r120 =3D [ r20 ] - ld8.c.clr.acq.nt1 r120 =3D [ r20 ] - ld8.c.clr.acq.d1 r120 =3D [ r20 ] - ld8.c.clr.acq.d2 r120 =3D [ r20 ] - ld8.c.clr.acq.nt2 r120 =3D [ r20 ] - ld8.c.clr.acq.nta r120 =3D [ r20 ] - ld8.c.clr.acq.d3 r120 =3D [ r20 ] - ld8.c.clr.acq.d4 r120 =3D [ r20 ] - ld8.c.clr.acq.d5 r120 =3D [ r20 ] - ld8.c.clr.acq.d6 r120 =3D [ r20 ] - ld8.c.clr.acq.d7 r120 =3D [ r20 ] - ld16 r120 =3D [ r20 ] - ld16 r120 =3D [ r20 ] - ld16.nt1 r120 =3D [ r20 ] - ld16.d1 r120 =3D [ r20 ] - ld16.d2 r120 =3D [ r20 ] - ld16.nt2 r120 =3D [ r20 ] - ld16.nt1 r120 =3D [ r20 ] - ld16.d1 r120 =3D [ r20 ] - ld16.d2 r120 =3D [ r20 ] - ld16.nt2 r120 =3D [ r20 ] - ld16.nta r120 =3D [ r20 ] - ld16.d3 r120 =3D [ r20 ] - ld16.d4 r120 =3D [ r20 ] - ld16.d5 r120 =3D [ r20 ] - ld16.d6 r120 =3D [ r20 ] - ld16.d7 r120 =3D [ r20 ] - ld16.nta r120 =3D [ r20 ] - ld16.d3 r120 =3D [ r20 ] - ld16.d4 r120 =3D [ r20 ] - ld16.d5 r120 =3D [ r20 ] - ld16.d6 r120 =3D [ r20 ] - ld16.d7 r120 =3D [ r20 ] - ld16.acq r120 =3D [ r20 ] - ld16.acq r120, ar.csd =3D [ r20 ] - ld16.acq.nt1 r120 =3D [ r20 ] - ld16.acq.d1 r120 =3D [ r20 ] - ld16.acq.d2 r120, ar.csd =3D [ r20 ] - ld16.acq.nt2 r120 =3D [ r20 ] - ld16.acq.nt1 r120 =3D [ r20 ] - ld16.acq.d1 r120 =3D [ r20 ] - ld16.acq.d2 r120 =3D [ r20 ] - ld16.acq.nt2 r120 =3D [ r20 ] - ld16.acq.nta r120 =3D [ r20 ] - ld16.acq.d3 r120 =3D [ r20 ] - ld16.acq.d4 r120 =3D [ r20 ] - ld16.acq.d5 r120 =3D [ r20 ] - ld16.acq.d6 r120 =3D [ r20 ] - ld16.acq.d7 r120 =3D [ r20 ] - ld16.acq.nta r120, ar.csd =3D [ r20 ] - ld16.acq.d3 r120 =3D [ r20 ] - ld16.acq.d4 r120 =3D [ r20 ] - ld16.acq.d5 r120 =3D [ r20 ] - ld16.acq.d6 r120 =3D [ r20 ] - ld16.acq.d7 r120 =3D [ r20 ] - - /* Pseudo-op that generates ldxmov relocation. */ - ld8.mov r120 =3D [ r20 ], AAAAA -AAAAA: - diff --git a/gas/testsuite/gas/ia64/radix.l b/gas/testsuite/gas/ia64/radix.l deleted file mode 100644 index 92d9e7cda14..00000000000 --- a/gas/testsuite/gas/ia64/radix.l +++ /dev/null @@ -1,4 +0,0 @@ -.*: Assembler messages: -.*:1: Error: Radix .a. .*invalid -.*:4: Error: Radix .cc. .*invalid -.*:5: Error: Radix .Z. .*invalid diff --git a/gas/testsuite/gas/ia64/radix.s b/gas/testsuite/gas/ia64/radix.s deleted file mode 100644 index 75dcf7bc868..00000000000 --- a/gas/testsuite/gas/ia64/radix.s +++ /dev/null @@ -1,5 +0,0 @@ - .radix a - .radix c - .radix C# - .radix cc - .radix Z diff --git a/gas/testsuite/gas/ia64/real.d b/gas/testsuite/gas/ia64/real.d deleted file mode 100644 index 36ceecb116d..00000000000 --- a/gas/testsuite/gas/ia64/real.d +++ /dev/null @@ -1,10 +0,0 @@ -#objdump: -s -j .data -#name: ia64 real10 and real16 (LSB) - -.*: +file format .* - -Contents of section .data: - 0000 ffcdcccc cccccccc ccfc3f00 00000000 ................ - 0010 cdcccccc cccccccc fc3fffcd cccccccc ................ - 0020 ccccccfb 3f000000 00000000 00000000 ................ - 0030 cdcccccc cccccccc fb3f0000 00000000 ................ diff --git a/gas/testsuite/gas/ia64/real.s b/gas/testsuite/gas/ia64/real.s deleted file mode 100644 index f5248da6268..00000000000 --- a/gas/testsuite/gas/ia64/real.s +++ /dev/null @@ -1,8 +0,0 @@ - .data - .lsb - data1 -1 - real10.ua 0.2 - real10 0.2 - data1 -1 - real16.ua 0.1 - real16 0.1 diff --git a/gas/testsuite/gas/ia64/reg-err.l b/gas/testsuite/gas/ia64/reg-= err.l deleted file mode 100644 index bd4dbc401d3..00000000000 --- a/gas/testsuite/gas/ia64/reg-err.l +++ /dev/null @@ -1,14 +0,0 @@ -.*: Assembler messages: -.*:3: (Error|Warning): Invalid use of `r0' as output operand -.*:4: (Error|Warning): Invalid use of `r0' as base update address operand -.*:5: (Error|Warning): Invalid duplicate use of `r1' -.*:6: (Error|Warning): Invalid use of `r0' as base update address operand -.*:7: (Error|Warning): Invalid duplicate use of `p1' -.*:8: (Error|Warning): Invalid use of `f0' as output operand -.*:9: (Error|Warning): Invalid use of `f1' as output operand -.*:10: (Error|Warning): Invalid use of `f0' as output operand -.*:11: (Error|Warning): Invalid use of `f1' as output operand -.*:12: (Error|Warning): Invalid use of `f0' as output operand -.*:12: (Error|Warning): Invalid use of `f1' as output operand -.*:13: (Error|Warning): Invalid simultaneous use of `f2' and `f4' -.*:14: (Error|Warning): Dangerous simultaneous use of `f31' and `f32' diff --git a/gas/testsuite/gas/ia64/reg-err.s b/gas/testsuite/gas/ia64/reg-= err.s deleted file mode 100644 index 88124d365e7..00000000000 --- a/gas/testsuite/gas/ia64/reg-err.s +++ /dev/null @@ -1,14 +0,0 @@ - .text -_start: - mov r0 =3D r0 - ld1 r1 =3D [r0], 1 - ld1 r1 =3D [r1], 1 - st1 [r0] =3D r0, 1 - cmp.eq p1, p1 =3D 0, r0 - mov f0 =3D f0 - mov f1 =3D f1 - ldfs f0 =3D [r0] - ldfs f1 =3D [r0] - ldfps f0, f1 =3D [r0] - ldfps f2, f4 =3D [r0] - ldfps f31, f32 =3D [r0] diff --git a/gas/testsuite/gas/ia64/regs.d b/gas/testsuite/gas/ia64/regs.d deleted file mode 100644 index b1e9e517b1d..00000000000 --- a/gas/testsuite/gas/ia64/regs.d +++ /dev/null @@ -1,2349 +0,0 @@ -#as: -xnone -#objdump: -d -#name: ia64 regs - -.*: +file format .* - -Disassembly of section \.text: - -0+ <_start>: -[ ]*[a-f0-9]+: 01 08 00 00 00 21 \[MII\] mov r1=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 10 00 00 00 21 \[MII\] mov r2=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 18 00 00 00 21 \[MII\] mov r3=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 20 00 00 00 21 \[MII\] mov r4=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 28 00 00 00 21 \[MII\] mov r5=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 30 00 00 00 21 \[MII\] mov r6=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 38 00 00 00 21 \[MII\] mov r7=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 40 00 00 00 21 \[MII\] mov r8=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 48 00 00 00 21 \[MII\] mov r9=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 50 00 00 00 21 \[MII\] mov r10=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 58 00 00 00 21 \[MII\] mov r11=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 60 00 00 00 21 \[MII\] mov r12=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 68 00 00 00 21 \[MII\] mov r13=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 70 00 00 00 21 \[MII\] mov r14=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 78 00 00 00 21 \[MII\] mov r15=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 80 00 00 00 21 \[MII\] mov r16=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 88 00 00 00 21 \[MII\] mov r17=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 90 00 00 00 21 \[MII\] mov r18=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 98 00 00 00 21 \[MII\] mov r19=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 a0 00 00 00 21 \[MII\] mov r20=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 a8 00 00 00 21 \[MII\] mov r21=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 b0 00 00 00 21 \[MII\] mov r22=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 b8 00 00 00 21 \[MII\] mov r23=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 c0 00 00 00 21 \[MII\] mov r24=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 c8 00 00 00 21 \[MII\] mov r25=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 d0 00 00 00 21 \[MII\] mov r26=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 d8 00 00 00 21 \[MII\] mov r27=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 e0 00 00 00 21 \[MII\] mov r28=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 e8 00 00 00 21 \[MII\] mov r29=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 f0 00 00 00 21 \[MII\] mov r30=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 f8 00 00 00 21 \[MII\] mov r31=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 00 01 00 00 21 \[MII\] mov r32=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 08 01 00 00 21 \[MII\] mov r33=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 10 01 00 00 21 \[MII\] mov r34=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 18 01 00 00 21 \[MII\] mov r35=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 20 01 00 00 21 \[MII\] mov r36=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 28 01 00 00 21 \[MII\] mov r37=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 30 01 00 00 21 \[MII\] mov r38=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 38 01 00 00 21 \[MII\] mov r39=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 40 01 00 00 21 \[MII\] mov r40=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 48 01 00 00 21 \[MII\] mov r41=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 50 01 00 00 21 \[MII\] mov r42=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 58 01 00 00 21 \[MII\] mov r43=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 60 01 00 00 21 \[MII\] mov r44=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 68 01 00 00 21 \[MII\] mov r45=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 70 01 00 00 21 \[MII\] mov r46=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 78 01 00 00 21 \[MII\] mov r47=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 80 01 00 00 21 \[MII\] mov r48=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 88 01 00 00 21 \[MII\] mov r49=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 90 01 00 00 21 \[MII\] mov r50=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 98 01 00 00 21 \[MII\] mov r51=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 a0 01 00 00 21 \[MII\] mov r52=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 a8 01 00 00 21 \[MII\] mov r53=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 b0 01 00 00 21 \[MII\] mov r54=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 b8 01 00 00 21 \[MII\] mov r55=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 c0 01 00 00 21 \[MII\] mov r56=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 c8 01 00 00 21 \[MII\] mov r57=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 d0 01 00 00 21 \[MII\] mov r58=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 d8 01 00 00 21 \[MII\] mov r59=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 e0 01 00 00 21 \[MII\] mov r60=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 e8 01 00 00 21 \[MII\] mov r61=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 f0 01 00 00 21 \[MII\] mov r62=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 f8 01 00 00 21 \[MII\] mov r63=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 00 02 00 00 21 \[MII\] mov r64=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 08 02 00 00 21 \[MII\] mov r65=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 10 02 00 00 21 \[MII\] mov r66=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 18 02 00 00 21 \[MII\] mov r67=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 20 02 00 00 21 \[MII\] mov r68=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 28 02 00 00 21 \[MII\] mov r69=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 30 02 00 00 21 \[MII\] mov r70=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 38 02 00 00 21 \[MII\] mov r71=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 40 02 00 00 21 \[MII\] mov r72=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 48 02 00 00 21 \[MII\] mov r73=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 50 02 00 00 21 \[MII\] mov r74=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 58 02 00 00 21 \[MII\] mov r75=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 60 02 00 00 21 \[MII\] mov r76=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 68 02 00 00 21 \[MII\] mov r77=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 70 02 00 00 21 \[MII\] mov r78=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 78 02 00 00 21 \[MII\] mov r79=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 80 02 00 00 21 \[MII\] mov r80=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 88 02 00 00 21 \[MII\] mov r81=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 90 02 00 00 21 \[MII\] mov r82=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 98 02 00 00 21 \[MII\] mov r83=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 a0 02 00 00 21 \[MII\] mov r84=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 a8 02 00 00 21 \[MII\] mov r85=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 b0 02 00 00 21 \[MII\] mov r86=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 b8 02 00 00 21 \[MII\] mov r87=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 c0 02 00 00 21 \[MII\] mov r88=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 c8 02 00 00 21 \[MII\] mov r89=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 d0 02 00 00 21 \[MII\] mov r90=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 d8 02 00 00 21 \[MII\] mov r91=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 e0 02 00 00 21 \[MII\] mov r92=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 e8 02 00 00 21 \[MII\] mov r93=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 f0 02 00 00 21 \[MII\] mov r94=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 f8 02 00 00 21 \[MII\] mov r95=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 00 03 00 00 21 \[MII\] mov r96=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 08 03 00 00 21 \[MII\] mov r97=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 10 03 00 00 21 \[MII\] mov r98=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 18 03 00 00 21 \[MII\] mov r99=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 20 03 00 00 21 \[MII\] mov r100=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 28 03 00 00 21 \[MII\] mov r101=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 30 03 00 00 21 \[MII\] mov r102=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 38 03 00 00 21 \[MII\] mov r103=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 40 03 00 00 21 \[MII\] mov r104=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 48 03 00 00 21 \[MII\] mov r105=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 50 03 00 00 21 \[MII\] mov r106=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 58 03 00 00 21 \[MII\] mov r107=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 60 03 00 00 21 \[MII\] mov r108=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 68 03 00 00 21 \[MII\] mov r109=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 70 03 00 00 21 \[MII\] mov r110=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 78 03 00 00 21 \[MII\] mov r111=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 80 03 00 00 21 \[MII\] mov r112=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 88 03 00 00 21 \[MII\] mov r113=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 90 03 00 00 21 \[MII\] mov r114=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 98 03 00 00 21 \[MII\] mov r115=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 a0 03 00 00 21 \[MII\] mov r116=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 a8 03 00 00 21 \[MII\] mov r117=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 b0 03 00 00 21 \[MII\] mov r118=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 b8 03 00 00 21 \[MII\] mov r119=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 c0 03 00 00 21 \[MII\] mov r120=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 c8 03 00 00 21 \[MII\] mov r121=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 d0 03 00 00 21 \[MII\] mov r122=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 d8 03 00 00 21 \[MII\] mov r123=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 e0 03 00 00 21 \[MII\] mov r124=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 e8 03 00 00 21 \[MII\] mov r125=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 f0 03 00 00 21 \[MII\] mov r126=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 f8 03 00 00 21 \[MII\] mov r127=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 00 01 00 00 21 \[MII\] mov r32=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 08 01 00 00 21 \[MII\] mov r33=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 10 01 00 00 21 \[MII\] mov r34=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 18 01 00 00 21 \[MII\] mov r35=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 20 01 00 00 21 \[MII\] mov r36=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 28 01 00 00 21 \[MII\] mov r37=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 30 01 00 00 21 \[MII\] mov r38=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 38 01 00 00 21 \[MII\] mov r39=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 40 01 00 00 21 \[MII\] mov r40=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 48 01 00 00 21 \[MII\] mov r41=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 50 01 00 00 21 \[MII\] mov r42=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 58 01 00 00 21 \[MII\] mov r43=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 60 01 00 00 21 \[MII\] mov r44=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 68 01 00 00 21 \[MII\] mov r45=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 70 01 00 00 21 \[MII\] mov r46=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 78 01 00 00 21 \[MII\] mov r47=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 80 01 00 00 21 \[MII\] mov r48=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 88 01 00 00 21 \[MII\] mov r49=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 90 01 00 00 21 \[MII\] mov r50=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 98 01 00 00 21 \[MII\] mov r51=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 a0 01 00 00 21 \[MII\] mov r52=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 a8 01 00 00 21 \[MII\] mov r53=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 b0 01 00 00 21 \[MII\] mov r54=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 b8 01 00 00 21 \[MII\] mov r55=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 c0 01 00 00 21 \[MII\] mov r56=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 c8 01 00 00 21 \[MII\] mov r57=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 d0 01 00 00 21 \[MII\] mov r58=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 d8 01 00 00 21 \[MII\] mov r59=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 e0 01 00 00 21 \[MII\] mov r60=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 e8 01 00 00 21 \[MII\] mov r61=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 f0 01 00 00 21 \[MII\] mov r62=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 f8 01 00 00 21 \[MII\] mov r63=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 00 02 00 00 21 \[MII\] mov r64=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 08 02 00 00 21 \[MII\] mov r65=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 10 02 00 00 21 \[MII\] mov r66=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 18 02 00 00 21 \[MII\] mov r67=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 20 02 00 00 21 \[MII\] mov r68=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 28 02 00 00 21 \[MII\] mov r69=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 30 02 00 00 21 \[MII\] mov r70=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 38 02 00 00 21 \[MII\] mov r71=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 40 02 00 00 21 \[MII\] mov r72=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 48 02 00 00 21 \[MII\] mov r73=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 50 02 00 00 21 \[MII\] mov r74=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 58 02 00 00 21 \[MII\] mov r75=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 60 02 00 00 21 \[MII\] mov r76=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 68 02 00 00 21 \[MII\] mov r77=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 70 02 00 00 21 \[MII\] mov r78=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 78 02 00 00 21 \[MII\] mov r79=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 80 02 00 00 21 \[MII\] mov r80=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 88 02 00 00 21 \[MII\] mov r81=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 90 02 00 00 21 \[MII\] mov r82=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 98 02 00 00 21 \[MII\] mov r83=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 a0 02 00 00 21 \[MII\] mov r84=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 a8 02 00 00 21 \[MII\] mov r85=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 b0 02 00 00 21 \[MII\] mov r86=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 b8 02 00 00 21 \[MII\] mov r87=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 c0 02 00 00 21 \[MII\] mov r88=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 c8 02 00 00 21 \[MII\] mov r89=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 d0 02 00 00 21 \[MII\] mov r90=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 d8 02 00 00 21 \[MII\] mov r91=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 e0 02 00 00 21 \[MII\] mov r92=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 e8 02 00 00 21 \[MII\] mov r93=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 f0 02 00 00 21 \[MII\] mov r94=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 f8 02 00 00 21 \[MII\] mov r95=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 00 03 00 00 21 \[MII\] mov r96=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 08 03 00 00 21 \[MII\] mov r97=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 10 03 00 00 21 \[MII\] mov r98=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 18 03 00 00 21 \[MII\] mov r99=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 20 03 00 00 21 \[MII\] mov r100=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 28 03 00 00 21 \[MII\] mov r101=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 30 03 00 00 21 \[MII\] mov r102=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 38 03 00 00 21 \[MII\] mov r103=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 40 03 00 00 21 \[MII\] mov r104=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 48 03 00 00 21 \[MII\] mov r105=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 50 03 00 00 21 \[MII\] mov r106=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 58 03 00 00 21 \[MII\] mov r107=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 60 03 00 00 21 \[MII\] mov r108=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 68 03 00 00 21 \[MII\] mov r109=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 70 03 00 00 21 \[MII\] mov r110=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 78 03 00 00 21 \[MII\] mov r111=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 80 03 00 00 21 \[MII\] mov r112=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 88 03 00 00 21 \[MII\] mov r113=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 90 03 00 00 21 \[MII\] mov r114=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 98 03 00 00 21 \[MII\] mov r115=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 a0 03 00 00 21 \[MII\] mov r116=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 a8 03 00 00 21 \[MII\] mov r117=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 b0 03 00 00 21 \[MII\] mov r118=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 b8 03 00 00 21 \[MII\] mov r119=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 c0 03 00 00 21 \[MII\] mov r120=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 c8 03 00 00 21 \[MII\] mov r121=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 d0 03 00 00 21 \[MII\] mov r122=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 d8 03 00 00 21 \[MII\] mov r123=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 e0 03 00 00 21 \[MII\] mov r124=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 e8 03 00 00 21 \[MII\] mov r125=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 f0 03 00 00 21 \[MII\] mov r126=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 f8 03 00 00 21 \[MII\] mov r127=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 00 01 00 00 21 \[MII\] mov r32=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 08 01 00 00 21 \[MII\] mov r33=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 10 01 00 00 21 \[MII\] mov r34=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 18 01 00 00 21 \[MII\] mov r35=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 20 01 00 00 21 \[MII\] mov r36=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 28 01 00 00 21 \[MII\] mov r37=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 30 01 00 00 21 \[MII\] mov r38=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 38 01 00 00 21 \[MII\] mov r39=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 40 01 00 00 21 \[MII\] mov r40=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 48 01 00 00 21 \[MII\] mov r41=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 50 01 00 00 21 \[MII\] mov r42=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 58 01 00 00 21 \[MII\] mov r43=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 60 01 00 00 21 \[MII\] mov r44=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 68 01 00 00 21 \[MII\] mov r45=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 70 01 00 00 21 \[MII\] mov r46=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 78 01 00 00 21 \[MII\] mov r47=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 80 01 00 00 21 \[MII\] mov r48=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 88 01 00 00 21 \[MII\] mov r49=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 90 01 00 00 21 \[MII\] mov r50=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 98 01 00 00 21 \[MII\] mov r51=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 a0 01 00 00 21 \[MII\] mov r52=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 a8 01 00 00 21 \[MII\] mov r53=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 b0 01 00 00 21 \[MII\] mov r54=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 b8 01 00 00 21 \[MII\] mov r55=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 c0 01 00 00 21 \[MII\] mov r56=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 c8 01 00 00 21 \[MII\] mov r57=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 d0 01 00 00 21 \[MII\] mov r58=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 d8 01 00 00 21 \[MII\] mov r59=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 e0 01 00 00 21 \[MII\] mov r60=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 e8 01 00 00 21 \[MII\] mov r61=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 f0 01 00 00 21 \[MII\] mov r62=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 f8 01 00 00 21 \[MII\] mov r63=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 00 02 00 00 21 \[MII\] mov r64=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 08 02 00 00 21 \[MII\] mov r65=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 10 02 00 00 21 \[MII\] mov r66=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 18 02 00 00 21 \[MII\] mov r67=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 20 02 00 00 21 \[MII\] mov r68=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 28 02 00 00 21 \[MII\] mov r69=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 30 02 00 00 21 \[MII\] mov r70=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 38 02 00 00 21 \[MII\] mov r71=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 40 02 00 00 21 \[MII\] mov r72=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 48 02 00 00 21 \[MII\] mov r73=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 50 02 00 00 21 \[MII\] mov r74=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 58 02 00 00 21 \[MII\] mov r75=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 60 02 00 00 21 \[MII\] mov r76=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 68 02 00 00 21 \[MII\] mov r77=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 70 02 00 00 21 \[MII\] mov r78=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 78 02 00 00 21 \[MII\] mov r79=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 80 02 00 00 21 \[MII\] mov r80=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 88 02 00 00 21 \[MII\] mov r81=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 90 02 00 00 21 \[MII\] mov r82=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 98 02 00 00 21 \[MII\] mov r83=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 a0 02 00 00 21 \[MII\] mov r84=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 a8 02 00 00 21 \[MII\] mov r85=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 b0 02 00 00 21 \[MII\] mov r86=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 b8 02 00 00 21 \[MII\] mov r87=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 c0 02 00 00 21 \[MII\] mov r88=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 c8 02 00 00 21 \[MII\] mov r89=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 d0 02 00 00 21 \[MII\] mov r90=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 d8 02 00 00 21 \[MII\] mov r91=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 e0 02 00 00 21 \[MII\] mov r92=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 e8 02 00 00 21 \[MII\] mov r93=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 f0 02 00 00 21 \[MII\] mov r94=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 f8 02 00 00 21 \[MII\] mov r95=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 00 03 00 00 21 \[MII\] mov r96=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 08 03 00 00 21 \[MII\] mov r97=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 10 03 00 00 21 \[MII\] mov r98=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 18 03 00 00 21 \[MII\] mov r99=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 20 03 00 00 21 \[MII\] mov r100=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 28 03 00 00 21 \[MII\] mov r101=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 30 03 00 00 21 \[MII\] mov r102=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 38 03 00 00 21 \[MII\] mov r103=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 40 03 00 00 21 \[MII\] mov r104=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 48 03 00 00 21 \[MII\] mov r105=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 50 03 00 00 21 \[MII\] mov r106=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 58 03 00 00 21 \[MII\] mov r107=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 60 03 00 00 21 \[MII\] mov r108=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 68 03 00 00 21 \[MII\] mov r109=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 70 03 00 00 21 \[MII\] mov r110=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 78 03 00 00 21 \[MII\] mov r111=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 80 03 00 00 21 \[MII\] mov r112=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 88 03 00 00 21 \[MII\] mov r113=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 90 03 00 00 21 \[MII\] mov r114=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 98 03 00 00 21 \[MII\] mov r115=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 a0 03 00 00 21 \[MII\] mov r116=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 a8 03 00 00 21 \[MII\] mov r117=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 b0 03 00 00 21 \[MII\] mov r118=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 b8 03 00 00 21 \[MII\] mov r119=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 c0 03 00 00 21 \[MII\] mov r120=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 c8 03 00 00 21 \[MII\] mov r121=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 d0 03 00 00 21 \[MII\] mov r122=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 d8 03 00 00 21 \[MII\] mov r123=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 e0 03 00 00 21 \[MII\] mov r124=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 e8 03 00 00 21 \[MII\] mov r125=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 f0 03 00 00 21 \[MII\] mov r126=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 f8 03 00 00 21 \[MII\] mov r127=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 00 01 00 00 21 \[MII\] mov r32=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 08 01 00 00 21 \[MII\] mov r33=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 10 01 00 00 21 \[MII\] mov r34=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 18 01 00 00 21 \[MII\] mov r35=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 20 01 00 00 21 \[MII\] mov r36=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 28 01 00 00 21 \[MII\] mov r37=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 30 01 00 00 21 \[MII\] mov r38=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 38 01 00 00 21 \[MII\] mov r39=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 40 01 00 00 21 \[MII\] mov r40=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 48 01 00 00 21 \[MII\] mov r41=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 50 01 00 00 21 \[MII\] mov r42=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 58 01 00 00 21 \[MII\] mov r43=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 60 01 00 00 21 \[MII\] mov r44=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 68 01 00 00 21 \[MII\] mov r45=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 70 01 00 00 21 \[MII\] mov r46=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 78 01 00 00 21 \[MII\] mov r47=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 80 01 00 00 21 \[MII\] mov r48=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 88 01 00 00 21 \[MII\] mov r49=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 90 01 00 00 21 \[MII\] mov r50=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 98 01 00 00 21 \[MII\] mov r51=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 a0 01 00 00 21 \[MII\] mov r52=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 a8 01 00 00 21 \[MII\] mov r53=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 b0 01 00 00 21 \[MII\] mov r54=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 b8 01 00 00 21 \[MII\] mov r55=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 c0 01 00 00 21 \[MII\] mov r56=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 c8 01 00 00 21 \[MII\] mov r57=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 d0 01 00 00 21 \[MII\] mov r58=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 d8 01 00 00 21 \[MII\] mov r59=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 e0 01 00 00 21 \[MII\] mov r60=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 e8 01 00 00 21 \[MII\] mov r61=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 f0 01 00 00 21 \[MII\] mov r62=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 f8 01 00 00 21 \[MII\] mov r63=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 00 02 00 00 21 \[MII\] mov r64=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 08 02 00 00 21 \[MII\] mov r65=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 10 02 00 00 21 \[MII\] mov r66=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 18 02 00 00 21 \[MII\] mov r67=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 20 02 00 00 21 \[MII\] mov r68=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 28 02 00 00 21 \[MII\] mov r69=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 30 02 00 00 21 \[MII\] mov r70=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 38 02 00 00 21 \[MII\] mov r71=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 40 02 00 00 21 \[MII\] mov r72=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 48 02 00 00 21 \[MII\] mov r73=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 50 02 00 00 21 \[MII\] mov r74=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 58 02 00 00 21 \[MII\] mov r75=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 60 02 00 00 21 \[MII\] mov r76=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 68 02 00 00 21 \[MII\] mov r77=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 70 02 00 00 21 \[MII\] mov r78=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 78 02 00 00 21 \[MII\] mov r79=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 80 02 00 00 21 \[MII\] mov r80=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 88 02 00 00 21 \[MII\] mov r81=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 90 02 00 00 21 \[MII\] mov r82=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 98 02 00 00 21 \[MII\] mov r83=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 a0 02 00 00 21 \[MII\] mov r84=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 a8 02 00 00 21 \[MII\] mov r85=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 b0 02 00 00 21 \[MII\] mov r86=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 b8 02 00 00 21 \[MII\] mov r87=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 c0 02 00 00 21 \[MII\] mov r88=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 c8 02 00 00 21 \[MII\] mov r89=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 d0 02 00 00 21 \[MII\] mov r90=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 d8 02 00 00 21 \[MII\] mov r91=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 e0 02 00 00 21 \[MII\] mov r92=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 e8 02 00 00 21 \[MII\] mov r93=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 f0 02 00 00 21 \[MII\] mov r94=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 f8 02 00 00 21 \[MII\] mov r95=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 00 03 00 00 21 \[MII\] mov r96=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 08 03 00 00 21 \[MII\] mov r97=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 10 03 00 00 21 \[MII\] mov r98=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 18 03 00 00 21 \[MII\] mov r99=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 20 03 00 00 21 \[MII\] mov r100=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 28 03 00 00 21 \[MII\] mov r101=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 30 03 00 00 21 \[MII\] mov r102=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 38 03 00 00 21 \[MII\] mov r103=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 40 03 00 00 21 \[MII\] mov r104=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 48 03 00 00 21 \[MII\] mov r105=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 50 03 00 00 21 \[MII\] mov r106=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 58 03 00 00 21 \[MII\] mov r107=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 60 03 00 00 21 \[MII\] mov r108=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 68 03 00 00 21 \[MII\] mov r109=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 70 03 00 00 21 \[MII\] mov r110=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 78 03 00 00 21 \[MII\] mov r111=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 80 03 00 00 21 \[MII\] mov r112=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 88 03 00 00 21 \[MII\] mov r113=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 90 03 00 00 21 \[MII\] mov r114=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 98 03 00 00 21 \[MII\] mov r115=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 a0 03 00 00 21 \[MII\] mov r116=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 a8 03 00 00 21 \[MII\] mov r117=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 b0 03 00 00 21 \[MII\] mov r118=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 b8 03 00 00 21 \[MII\] mov r119=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 c0 03 00 00 21 \[MII\] mov r120=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 c8 03 00 00 21 \[MII\] mov r121=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 d0 03 00 00 21 \[MII\] mov r122=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 d8 03 00 00 21 \[MII\] mov r123=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 e0 03 00 00 21 \[MII\] mov r124=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 e8 03 00 00 21 \[MII\] mov r125=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 f0 03 00 00 21 \[MII\] mov r126=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 f8 03 00 00 21 \[MII\] mov r127=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 40 00 00 00 21 \[MII\] mov r8=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 48 00 00 00 21 \[MII\] mov r9=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 50 00 00 00 21 \[MII\] mov r10=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 58 00 00 00 21 \[MII\] mov r11=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 08 00 00 00 21 \[MII\] mov r1=3Dr0 -[ ]*[a-f0-9]+: c0 00 00 00 42 a0 mov r12=3Dr0 -[ ]*[a-f0-9]+: 01 00 00 84 mov r13=3Dr0;; -[ ]*[a-f0-9]+: 0d 00 00 00 01 00 \[MFI\] nop.m 0x0 -[ ]*[a-f0-9]+: 20 00 00 20 00 00 mov f2=3Df0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 0d 00 00 00 01 00 \[MFI\] nop.m 0x0 -[ ]*[a-f0-9]+: 30 00 00 20 00 00 mov f3=3Df0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 0d 00 00 00 01 00 \[MFI\] nop.m 0x0 -[ ]*[a-f0-9]+: 40 00 00 20 00 00 mov f4=3Df0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 0d 00 00 00 01 00 \[MFI\] nop.m 0x0 -[ ]*[a-f0-9]+: 50 00 00 20 00 00 mov f5=3Df0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 0d 00 00 00 01 00 \[MFI\] nop.m 0x0 -[ ]*[a-f0-9]+: 60 00 00 20 00 00 mov f6=3Df0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 0d 00 00 00 01 00 \[MFI\] nop.m 0x0 -[ ]*[a-f0-9]+: 70 00 00 20 00 00 mov f7=3Df0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 0d 00 00 00 01 00 \[MFI\] nop.m 0x0 -[ ]*[a-f0-9]+: 80 00 00 20 00 00 mov f8=3Df0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 0d 00 00 00 01 00 \[MFI\] nop.m 0x0 -[ ]*[a-f0-9]+: 90 00 00 20 00 00 mov f9=3Df0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 0d 00 00 00 01 00 \[MFI\] nop.m 0x0 -[ ]*[a-f0-9]+: a0 00 00 20 00 00 mov f10=3Df0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 0d 00 00 00 01 00 \[MFI\] nop.m 0x0 -[ ]*[a-f0-9]+: b0 00 00 20 00 00 mov f11=3Df0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 0d 00 00 00 01 00 \[MFI\] nop.m 0x0 -[ ]*[a-f0-9]+: c0 00 00 20 00 00 mov f12=3Df0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 0d 00 00 00 01 00 \[MFI\] nop.m 0x0 -[ ]*[a-f0-9]+: d0 00 00 20 00 00 mov f13=3Df0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 0d 00 00 00 01 00 \[MFI\] nop.m 0x0 -[ ]*[a-f0-9]+: e0 00 00 20 00 00 mov f14=3Df0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 0d 00 00 00 01 00 \[MFI\] nop.m 0x0 -[ ]*[a-f0-9]+: f0 00 00 20 00 00 mov f15=3Df0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 0d 00 00 00 01 00 \[MFI\] nop.m 0x0 -[ ]*[a-f0-9]+: 00 01 00 20 00 00 mov f16=3Df0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 0d 00 00 00 01 00 \[MFI\] nop.m 0x0 -[ ]*[a-f0-9]+: 10 01 00 20 00 00 mov f17=3Df0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 0d 00 00 00 01 00 \[MFI\] nop.m 0x0 -[ ]*[a-f0-9]+: 20 01 00 20 00 00 mov f18=3Df0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 0d 00 00 00 01 00 \[MFI\] nop.m 0x0 -[ ]*[a-f0-9]+: 30 01 00 20 00 00 mov f19=3Df0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 0d 00 00 00 01 00 \[MFI\] nop.m 0x0 -[ ]*[a-f0-9]+: 40 01 00 20 00 00 mov f20=3Df0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 0d 00 00 00 01 00 \[MFI\] nop.m 0x0 -[ ]*[a-f0-9]+: 50 01 00 20 00 00 mov f21=3Df0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 0d 00 00 00 01 00 \[MFI\] nop.m 0x0 -[ ]*[a-f0-9]+: 60 01 00 20 00 00 mov f22=3Df0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 0d 00 00 00 01 00 \[MFI\] nop.m 0x0 -[ ]*[a-f0-9]+: 70 01 00 20 00 00 mov f23=3Df0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 0d 00 00 00 01 00 \[MFI\] nop.m 0x0 -[ ]*[a-f0-9]+: 80 01 00 20 00 00 mov f24=3Df0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 0d 00 00 00 01 00 \[MFI\] nop.m 0x0 -[ ]*[a-f0-9]+: 90 01 00 20 00 00 mov f25=3Df0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 0d 00 00 00 01 00 \[MFI\] nop.m 0x0 -[ ]*[a-f0-9]+: a0 01 00 20 00 00 mov f26=3Df0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 0d 00 00 00 01 00 \[MFI\] nop.m 0x0 -[ ]*[a-f0-9]+: b0 01 00 20 00 00 mov f27=3Df0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 0d 00 00 00 01 00 \[MFI\] nop.m 0x0 -[ ]*[a-f0-9]+: c0 01 00 20 00 00 mov f28=3Df0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 0d 00 00 00 01 00 \[MFI\] nop.m 0x0 -[ ]*[a-f0-9]+: d0 01 00 20 00 00 mov f29=3Df0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 0d 00 00 00 01 00 \[MFI\] nop.m 0x0 -[ ]*[a-f0-9]+: e0 01 00 20 00 00 mov f30=3Df0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 0d 00 00 00 01 00 \[MFI\] nop.m 0x0 -[ ]*[a-f0-9]+: f0 01 00 20 00 00 mov f31=3Df0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 0d 00 00 00 01 00 \[MFI\] nop.m 0x0 -[ ]*[a-f0-9]+: 00 02 00 20 00 00 mov f32=3Df0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 0d 00 00 00 01 00 \[MFI\] nop.m 0x0 -[ ]*[a-f0-9]+: 10 02 00 20 00 00 mov f33=3Df0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 0d 00 00 00 01 00 \[MFI\] nop.m 0x0 -[ ]*[a-f0-9]+: 20 02 00 20 00 00 mov f34=3Df0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 0d 00 00 00 01 00 \[MFI\] nop.m 0x0 -[ ]*[a-f0-9]+: 30 02 00 20 00 00 mov f35=3Df0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 0d 00 00 00 01 00 \[MFI\] nop.m 0x0 -[ ]*[a-f0-9]+: 40 02 00 20 00 00 mov f36=3Df0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 0d 00 00 00 01 00 \[MFI\] nop.m 0x0 -[ ]*[a-f0-9]+: 50 02 00 20 00 00 mov f37=3Df0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 0d 00 00 00 01 00 \[MFI\] nop.m 0x0 -[ ]*[a-f0-9]+: 60 02 00 20 00 00 mov f38=3Df0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 0d 00 00 00 01 00 \[MFI\] nop.m 0x0 -[ ]*[a-f0-9]+: 70 02 00 20 00 00 mov f39=3Df0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 0d 00 00 00 01 00 \[MFI\] nop.m 0x0 -[ ]*[a-f0-9]+: 80 02 00 20 00 00 mov f40=3Df0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 0d 00 00 00 01 00 \[MFI\] nop.m 0x0 -[ ]*[a-f0-9]+: 90 02 00 20 00 00 mov f41=3Df0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 0d 00 00 00 01 00 \[MFI\] nop.m 0x0 -[ ]*[a-f0-9]+: a0 02 00 20 00 00 mov f42=3Df0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 0d 00 00 00 01 00 \[MFI\] nop.m 0x0 -[ ]*[a-f0-9]+: b0 02 00 20 00 00 mov f43=3Df0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 0d 00 00 00 01 00 \[MFI\] nop.m 0x0 -[ ]*[a-f0-9]+: c0 02 00 20 00 00 mov f44=3Df0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 0d 00 00 00 01 00 \[MFI\] nop.m 0x0 -[ ]*[a-f0-9]+: d0 02 00 20 00 00 mov f45=3Df0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 0d 00 00 00 01 00 \[MFI\] nop.m 0x0 -[ ]*[a-f0-9]+: e0 02 00 20 00 00 mov f46=3Df0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 0d 00 00 00 01 00 \[MFI\] nop.m 0x0 -[ ]*[a-f0-9]+: f0 02 00 20 00 00 mov f47=3Df0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 0d 00 00 00 01 00 \[MFI\] nop.m 0x0 -[ ]*[a-f0-9]+: 00 03 00 20 00 00 mov f48=3Df0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 0d 00 00 00 01 00 \[MFI\] nop.m 0x0 -[ ]*[a-f0-9]+: 10 03 00 20 00 00 mov f49=3Df0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 0d 00 00 00 01 00 \[MFI\] nop.m 0x0 -[ ]*[a-f0-9]+: 20 03 00 20 00 00 mov f50=3Df0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 0d 00 00 00 01 00 \[MFI\] nop.m 0x0 -[ ]*[a-f0-9]+: 30 03 00 20 00 00 mov f51=3Df0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 0d 00 00 00 01 00 \[MFI\] nop.m 0x0 -[ ]*[a-f0-9]+: 40 03 00 20 00 00 mov f52=3Df0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 0d 00 00 00 01 00 \[MFI\] nop.m 0x0 -[ ]*[a-f0-9]+: 50 03 00 20 00 00 mov f53=3Df0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 0d 00 00 00 01 00 \[MFI\] nop.m 0x0 -[ ]*[a-f0-9]+: 60 03 00 20 00 00 mov f54=3Df0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 0d 00 00 00 01 00 \[MFI\] nop.m 0x0 -[ ]*[a-f0-9]+: 70 03 00 20 00 00 mov f55=3Df0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 0d 00 00 00 01 00 \[MFI\] nop.m 0x0 -[ ]*[a-f0-9]+: 80 03 00 20 00 00 mov f56=3Df0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 0d 00 00 00 01 00 \[MFI\] nop.m 0x0 -[ ]*[a-f0-9]+: 90 03 00 20 00 00 mov f57=3Df0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 0d 00 00 00 01 00 \[MFI\] nop.m 0x0 -[ ]*[a-f0-9]+: a0 03 00 20 00 00 mov f58=3Df0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 0d 00 00 00 01 00 \[MFI\] nop.m 0x0 -[ ]*[a-f0-9]+: b0 03 00 20 00 00 mov f59=3Df0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 0d 00 00 00 01 00 \[MFI\] nop.m 0x0 -[ ]*[a-f0-9]+: c0 03 00 20 00 00 mov f60=3Df0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 0d 00 00 00 01 00 \[MFI\] nop.m 0x0 -[ ]*[a-f0-9]+: d0 03 00 20 00 00 mov f61=3Df0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 0d 00 00 00 01 00 \[MFI\] nop.m 0x0 -[ ]*[a-f0-9]+: e0 03 00 20 00 00 mov f62=3Df0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 0d 00 00 00 01 00 \[MFI\] nop.m 0x0 -[ ]*[a-f0-9]+: f0 03 00 20 00 00 mov f63=3Df0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 0d 00 00 00 01 00 \[MFI\] nop.m 0x0 -[ ]*[a-f0-9]+: 00 04 00 20 00 00 mov f64=3Df0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 0d 00 00 00 01 00 \[MFI\] nop.m 0x0 -[ ]*[a-f0-9]+: 10 04 00 20 00 00 mov f65=3Df0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 0d 00 00 00 01 00 \[MFI\] nop.m 0x0 -[ ]*[a-f0-9]+: 20 04 00 20 00 00 mov f66=3Df0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 0d 00 00 00 01 00 \[MFI\] nop.m 0x0 -[ ]*[a-f0-9]+: 30 04 00 20 00 00 mov f67=3Df0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 0d 00 00 00 01 00 \[MFI\] nop.m 0x0 -[ ]*[a-f0-9]+: 40 04 00 20 00 00 mov f68=3Df0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 0d 00 00 00 01 00 \[MFI\] nop.m 0x0 -[ ]*[a-f0-9]+: 50 04 00 20 00 00 mov f69=3Df0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 0d 00 00 00 01 00 \[MFI\] nop.m 0x0 -[ ]*[a-f0-9]+: 60 04 00 20 00 00 mov f70=3Df0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 0d 00 00 00 01 00 \[MFI\] nop.m 0x0 -[ ]*[a-f0-9]+: 70 04 00 20 00 00 mov f71=3Df0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 0d 00 00 00 01 00 \[MFI\] nop.m 0x0 -[ ]*[a-f0-9]+: 80 04 00 20 00 00 mov f72=3Df0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 0d 00 00 00 01 00 \[MFI\] nop.m 0x0 -[ ]*[a-f0-9]+: 90 04 00 20 00 00 mov f73=3Df0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 0d 00 00 00 01 00 \[MFI\] nop.m 0x0 -[ ]*[a-f0-9]+: a0 04 00 20 00 00 mov f74=3Df0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 0d 00 00 00 01 00 \[MFI\] nop.m 0x0 -[ ]*[a-f0-9]+: b0 04 00 20 00 00 mov f75=3Df0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 0d 00 00 00 01 00 \[MFI\] nop.m 0x0 -[ ]*[a-f0-9]+: c0 04 00 20 00 00 mov f76=3Df0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 0d 00 00 00 01 00 \[MFI\] nop.m 0x0 -[ ]*[a-f0-9]+: d0 04 00 20 00 00 mov f77=3Df0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 0d 00 00 00 01 00 \[MFI\] nop.m 0x0 -[ ]*[a-f0-9]+: e0 04 00 20 00 00 mov f78=3Df0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 0d 00 00 00 01 00 \[MFI\] nop.m 0x0 -[ ]*[a-f0-9]+: f0 04 00 20 00 00 mov f79=3Df0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 0d 00 00 00 01 00 \[MFI\] nop.m 0x0 -[ ]*[a-f0-9]+: 00 05 00 20 00 00 mov f80=3Df0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 0d 00 00 00 01 00 \[MFI\] nop.m 0x0 -[ ]*[a-f0-9]+: 10 05 00 20 00 00 mov f81=3Df0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 0d 00 00 00 01 00 \[MFI\] nop.m 0x0 -[ ]*[a-f0-9]+: 20 05 00 20 00 00 mov f82=3Df0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 0d 00 00 00 01 00 \[MFI\] nop.m 0x0 -[ ]*[a-f0-9]+: 30 05 00 20 00 00 mov f83=3Df0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 0d 00 00 00 01 00 \[MFI\] nop.m 0x0 -[ ]*[a-f0-9]+: 40 05 00 20 00 00 mov f84=3Df0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 0d 00 00 00 01 00 \[MFI\] nop.m 0x0 -[ ]*[a-f0-9]+: 50 05 00 20 00 00 mov f85=3Df0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 0d 00 00 00 01 00 \[MFI\] nop.m 0x0 -[ ]*[a-f0-9]+: 60 05 00 20 00 00 mov f86=3Df0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 0d 00 00 00 01 00 \[MFI\] nop.m 0x0 -[ ]*[a-f0-9]+: 70 05 00 20 00 00 mov f87=3Df0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 0d 00 00 00 01 00 \[MFI\] nop.m 0x0 -[ ]*[a-f0-9]+: 80 05 00 20 00 00 mov f88=3Df0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 0d 00 00 00 01 00 \[MFI\] nop.m 0x0 -[ ]*[a-f0-9]+: 90 05 00 20 00 00 mov f89=3Df0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 0d 00 00 00 01 00 \[MFI\] nop.m 0x0 -[ ]*[a-f0-9]+: a0 05 00 20 00 00 mov f90=3Df0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 0d 00 00 00 01 00 \[MFI\] nop.m 0x0 -[ ]*[a-f0-9]+: b0 05 00 20 00 00 mov f91=3Df0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 0d 00 00 00 01 00 \[MFI\] nop.m 0x0 -[ ]*[a-f0-9]+: c0 05 00 20 00 00 mov f92=3Df0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 0d 00 00 00 01 00 \[MFI\] nop.m 0x0 -[ ]*[a-f0-9]+: d0 05 00 20 00 00 mov f93=3Df0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 0d 00 00 00 01 00 \[MFI\] nop.m 0x0 -[ ]*[a-f0-9]+: e0 05 00 20 00 00 mov f94=3Df0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 0d 00 00 00 01 00 \[MFI\] nop.m 0x0 -[ ]*[a-f0-9]+: f0 05 00 20 00 00 mov f95=3Df0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 0d 00 00 00 01 00 \[MFI\] nop.m 0x0 -[ ]*[a-f0-9]+: 00 06 00 20 00 00 mov f96=3Df0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 0d 00 00 00 01 00 \[MFI\] nop.m 0x0 -[ ]*[a-f0-9]+: 10 06 00 20 00 00 mov f97=3Df0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 0d 00 00 00 01 00 \[MFI\] nop.m 0x0 -[ ]*[a-f0-9]+: 20 06 00 20 00 00 mov f98=3Df0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 0d 00 00 00 01 00 \[MFI\] nop.m 0x0 -[ ]*[a-f0-9]+: 30 06 00 20 00 00 mov f99=3Df0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 0d 00 00 00 01 00 \[MFI\] nop.m 0x0 -[ ]*[a-f0-9]+: 40 06 00 20 00 00 mov f100=3Df0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 0d 00 00 00 01 00 \[MFI\] nop.m 0x0 -[ ]*[a-f0-9]+: 50 06 00 20 00 00 mov f101=3Df0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 0d 00 00 00 01 00 \[MFI\] nop.m 0x0 -[ ]*[a-f0-9]+: 60 06 00 20 00 00 mov f102=3Df0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 0d 00 00 00 01 00 \[MFI\] nop.m 0x0 -[ ]*[a-f0-9]+: 70 06 00 20 00 00 mov f103=3Df0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 0d 00 00 00 01 00 \[MFI\] nop.m 0x0 -[ ]*[a-f0-9]+: 80 06 00 20 00 00 mov f104=3Df0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 0d 00 00 00 01 00 \[MFI\] nop.m 0x0 -[ ]*[a-f0-9]+: 90 06 00 20 00 00 mov f105=3Df0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 0d 00 00 00 01 00 \[MFI\] nop.m 0x0 -[ ]*[a-f0-9]+: a0 06 00 20 00 00 mov f106=3Df0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 0d 00 00 00 01 00 \[MFI\] nop.m 0x0 -[ ]*[a-f0-9]+: b0 06 00 20 00 00 mov f107=3Df0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 0d 00 00 00 01 00 \[MFI\] nop.m 0x0 -[ ]*[a-f0-9]+: c0 06 00 20 00 00 mov f108=3Df0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 0d 00 00 00 01 00 \[MFI\] nop.m 0x0 -[ ]*[a-f0-9]+: d0 06 00 20 00 00 mov f109=3Df0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 0d 00 00 00 01 00 \[MFI\] nop.m 0x0 -[ ]*[a-f0-9]+: e0 06 00 20 00 00 mov f110=3Df0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 0d 00 00 00 01 00 \[MFI\] nop.m 0x0 -[ ]*[a-f0-9]+: f0 06 00 20 00 00 mov f111=3Df0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 0d 00 00 00 01 00 \[MFI\] nop.m 0x0 -[ ]*[a-f0-9]+: 00 07 00 20 00 00 mov f112=3Df0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 0d 00 00 00 01 00 \[MFI\] nop.m 0x0 -[ ]*[a-f0-9]+: 10 07 00 20 00 00 mov f113=3Df0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 0d 00 00 00 01 00 \[MFI\] nop.m 0x0 -[ ]*[a-f0-9]+: 20 07 00 20 00 00 mov f114=3Df0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 0d 00 00 00 01 00 \[MFI\] nop.m 0x0 -[ ]*[a-f0-9]+: 30 07 00 20 00 00 mov f115=3Df0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 0d 00 00 00 01 00 \[MFI\] nop.m 0x0 -[ ]*[a-f0-9]+: 40 07 00 20 00 00 mov f116=3Df0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 0d 00 00 00 01 00 \[MFI\] nop.m 0x0 -[ ]*[a-f0-9]+: 50 07 00 20 00 00 mov f117=3Df0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 0d 00 00 00 01 00 \[MFI\] nop.m 0x0 -[ ]*[a-f0-9]+: 60 07 00 20 00 00 mov f118=3Df0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 0d 00 00 00 01 00 \[MFI\] nop.m 0x0 -[ ]*[a-f0-9]+: 70 07 00 20 00 00 mov f119=3Df0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 0d 00 00 00 01 00 \[MFI\] nop.m 0x0 -[ ]*[a-f0-9]+: 80 07 00 20 00 00 mov f120=3Df0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 0d 00 00 00 01 00 \[MFI\] nop.m 0x0 -[ ]*[a-f0-9]+: 90 07 00 20 00 00 mov f121=3Df0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 0d 00 00 00 01 00 \[MFI\] nop.m 0x0 -[ ]*[a-f0-9]+: a0 07 00 20 00 00 mov f122=3Df0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 0d 00 00 00 01 00 \[MFI\] nop.m 0x0 -[ ]*[a-f0-9]+: b0 07 00 20 00 00 mov f123=3Df0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 0d 00 00 00 01 00 \[MFI\] nop.m 0x0 -[ ]*[a-f0-9]+: c0 07 00 20 00 00 mov f124=3Df0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 0d 00 00 00 01 00 \[MFI\] nop.m 0x0 -[ ]*[a-f0-9]+: d0 07 00 20 00 00 mov f125=3Df0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 0d 00 00 00 01 00 \[MFI\] nop.m 0x0 -[ ]*[a-f0-9]+: e0 07 00 20 00 00 mov f126=3Df0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 0d 00 00 00 01 00 \[MFI\] nop.m 0x0 -[ ]*[a-f0-9]+: f0 07 00 20 00 00 mov f127=3Df0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 0d 00 00 00 01 00 \[MFI\] nop.m 0x0 -[ ]*[a-f0-9]+: 80 08 04 20 00 00 mov f8=3Df1 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 0d 00 00 00 01 00 \[MFI\] nop.m 0x0 -[ ]*[a-f0-9]+: 90 08 04 20 00 00 mov f9=3Df1 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 0d 00 00 00 01 00 \[MFI\] nop.m 0x0 -[ ]*[a-f0-9]+: a0 08 04 20 00 00 mov f10=3Df1 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 0d 00 00 00 01 00 \[MFI\] nop.m 0x0 -[ ]*[a-f0-9]+: b0 08 04 20 00 00 mov f11=3Df1 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 0d 00 00 00 01 00 \[MFI\] nop.m 0x0 -[ ]*[a-f0-9]+: c0 08 04 20 00 00 mov f12=3Df1 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 0d 00 00 00 01 00 \[MFI\] nop.m 0x0 -[ ]*[a-f0-9]+: d0 08 04 20 00 00 mov f13=3Df1 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 0d 00 00 00 01 00 \[MFI\] nop.m 0x0 -[ ]*[a-f0-9]+: e0 08 04 20 00 00 mov f14=3Df1 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 0d 00 00 00 01 00 \[MFI\] nop.m 0x0 -[ ]*[a-f0-9]+: f0 08 04 20 00 00 mov f15=3Df1 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 0d 00 00 00 01 00 \[MFI\] nop.m 0x0 -[ ]*[a-f0-9]+: 80 08 04 20 00 00 mov f8=3Df1 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 0d 00 00 00 01 00 \[MFI\] nop.m 0x0 -[ ]*[a-f0-9]+: 90 08 04 20 00 00 mov f9=3Df1 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 0d 00 00 00 01 00 \[MFI\] nop.m 0x0 -[ ]*[a-f0-9]+: a0 08 04 20 00 00 mov f10=3Df1 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 0d 00 00 00 01 00 \[MFI\] nop.m 0x0 -[ ]*[a-f0-9]+: b0 08 04 20 00 00 mov f11=3Df1 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 0d 00 00 00 01 00 \[MFI\] nop.m 0x0 -[ ]*[a-f0-9]+: c0 08 04 20 00 00 mov f12=3Df1 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 0d 00 00 00 01 00 \[MFI\] nop.m 0x0 -[ ]*[a-f0-9]+: d0 08 04 20 00 00 mov f13=3Df1 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 0d 00 00 00 01 00 \[MFI\] nop.m 0x0 -[ ]*[a-f0-9]+: e0 08 04 20 00 00 mov f14=3Df1 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 0d 00 00 00 01 00 \[MFI\] nop.m 0x0 -[ ]*[a-f0-9]+: f0 08 04 20 00 00 mov f15=3Df1 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 08 00 00 00 21 \[MII\] mov r1=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 21 10 00 00 00 21 \[MII\] \(p01\) mov r2=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 41 18 00 00 00 21 \[MII\] \(p02\) mov r3=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 61 20 00 00 00 21 \[MII\] \(p03\) mov r4=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 81 28 00 00 00 21 \[MII\] \(p04\) mov r5=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: a1 30 00 00 00 21 \[MII\] \(p05\) mov r6=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: c1 38 00 00 00 21 \[MII\] \(p06\) mov r7=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: e1 40 00 00 00 21 \[MII\] \(p07\) mov r8=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 49 00 00 00 21 \[MII\] \(p08\) mov r9=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 21 51 00 00 00 21 \[MII\] \(p09\) mov r10=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 41 59 00 00 00 21 \[MII\] \(p10\) mov r11=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 61 61 00 00 00 21 \[MII\] \(p11\) mov r12=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 81 69 00 00 00 21 \[MII\] \(p12\) mov r13=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: a1 71 00 00 00 21 \[MII\] \(p13\) mov r14=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: c1 79 00 00 00 21 \[MII\] \(p14\) mov r15=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: e1 81 00 00 00 21 \[MII\] \(p15\) mov r16=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 8a 00 00 00 21 \[MII\] \(p16\) mov r17=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 21 92 00 00 00 21 \[MII\] \(p17\) mov r18=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 41 9a 00 00 00 21 \[MII\] \(p18\) mov r19=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 61 a2 00 00 00 21 \[MII\] \(p19\) mov r20=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 81 aa 00 00 00 21 \[MII\] \(p20\) mov r21=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: a1 b2 00 00 00 21 \[MII\] \(p21\) mov r22=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: c1 ba 00 00 00 21 \[MII\] \(p22\) mov r23=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: e1 c2 00 00 00 21 \[MII\] \(p23\) mov r24=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 cb 00 00 00 21 \[MII\] \(p24\) mov r25=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 21 d3 00 00 00 21 \[MII\] \(p25\) mov r26=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 41 db 00 00 00 21 \[MII\] \(p26\) mov r27=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 61 e3 00 00 00 21 \[MII\] \(p27\) mov r28=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 81 eb 00 00 00 21 \[MII\] \(p28\) mov r29=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: a1 f3 00 00 00 21 \[MII\] \(p29\) mov r30=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: c1 fb 00 00 00 21 \[MII\] \(p30\) mov r31=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: e1 03 01 00 00 21 \[MII\] \(p31\) mov r32=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 0c 01 00 00 21 \[MII\] \(p32\) mov r33=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 21 14 01 00 00 21 \[MII\] \(p33\) mov r34=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 41 1c 01 00 00 21 \[MII\] \(p34\) mov r35=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 61 24 01 00 00 21 \[MII\] \(p35\) mov r36=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 81 2c 01 00 00 21 \[MII\] \(p36\) mov r37=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: a1 34 01 00 00 21 \[MII\] \(p37\) mov r38=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: c1 3c 01 00 00 21 \[MII\] \(p38\) mov r39=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: e1 44 01 00 00 21 \[MII\] \(p39\) mov r40=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 4d 01 00 00 21 \[MII\] \(p40\) mov r41=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 21 55 01 00 00 21 \[MII\] \(p41\) mov r42=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 41 5d 01 00 00 21 \[MII\] \(p42\) mov r43=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 61 65 01 00 00 21 \[MII\] \(p43\) mov r44=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 81 6d 01 00 00 21 \[MII\] \(p44\) mov r45=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: a1 75 01 00 00 21 \[MII\] \(p45\) mov r46=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: c1 7d 01 00 00 21 \[MII\] \(p46\) mov r47=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: e1 85 01 00 00 21 \[MII\] \(p47\) mov r48=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 8e 01 00 00 21 \[MII\] \(p48\) mov r49=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 21 96 01 00 00 21 \[MII\] \(p49\) mov r50=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 41 9e 01 00 00 21 \[MII\] \(p50\) mov r51=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 61 a6 01 00 00 21 \[MII\] \(p51\) mov r52=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 81 ae 01 00 00 21 \[MII\] \(p52\) mov r53=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: a1 b6 01 00 00 21 \[MII\] \(p53\) mov r54=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: c1 be 01 00 00 21 \[MII\] \(p54\) mov r55=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: e1 c6 01 00 00 21 \[MII\] \(p55\) mov r56=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 cf 01 00 00 21 \[MII\] \(p56\) mov r57=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 21 d7 01 00 00 21 \[MII\] \(p57\) mov r58=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 41 df 01 00 00 21 \[MII\] \(p58\) mov r59=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 61 e7 01 00 00 21 \[MII\] \(p59\) mov r60=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 81 ef 01 00 00 21 \[MII\] \(p60\) mov r61=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: a1 f7 01 00 00 21 \[MII\] \(p61\) mov r62=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: c1 ff 01 00 00 21 \[MII\] \(p62\) mov r63=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: e1 07 02 00 00 21 \[MII\] \(p63\) mov r64=3Dr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 09 00 00 00 01 00 \[MMI\] nop.m 0x0 -[ ]*[a-f0-9]+: 00 00 00 02 00 20 nop.m 0x0 -[ ]*[a-f0-9]+: 00 00 cc 00 mov r1=3Dpr;; -[ ]*[a-f0-9]+: 09 00 00 00 01 00 \[MMI\] nop.m 0x0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.m 0x0 -[ ]*[a-f0-9]+: 00 08 00 07 mov b0=3Dr0;; -[ ]*[a-f0-9]+: 09 00 00 00 01 00 \[MMI\] nop.m 0x0 -[ ]*[a-f0-9]+: 00 00 00 02 00 20 nop.m 0x0 -[ ]*[a-f0-9]+: 00 08 00 07 mov b1=3Dr0;; -[ ]*[a-f0-9]+: 09 00 00 00 01 00 \[MMI\] nop.m 0x0 -[ ]*[a-f0-9]+: 00 00 00 02 00 40 nop.m 0x0 -[ ]*[a-f0-9]+: 00 08 00 07 mov b2=3Dr0;; -[ ]*[a-f0-9]+: 09 00 00 00 01 00 \[MMI\] nop.m 0x0 -[ ]*[a-f0-9]+: 00 00 00 02 00 60 nop.m 0x0 -[ ]*[a-f0-9]+: 00 08 00 07 mov b3=3Dr0;; -[ ]*[a-f0-9]+: 09 00 00 00 01 00 \[MMI\] nop.m 0x0 -[ ]*[a-f0-9]+: 00 00 00 02 00 80 nop.m 0x0 -[ ]*[a-f0-9]+: 00 08 00 07 mov b4=3Dr0;; -[ ]*[a-f0-9]+: 09 00 00 00 01 00 \[MMI\] nop.m 0x0 -[ ]*[a-f0-9]+: 00 00 00 02 00 a0 nop.m 0x0 -[ ]*[a-f0-9]+: 00 08 00 07 mov b5=3Dr0;; -[ ]*[a-f0-9]+: 09 00 00 00 01 00 \[MMI\] nop.m 0x0 -[ ]*[a-f0-9]+: 00 00 00 02 00 c0 nop.m 0x0 -[ ]*[a-f0-9]+: 00 08 00 07 mov b6=3Dr0;; -[ ]*[a-f0-9]+: 09 00 00 00 01 00 \[MMI\] nop.m 0x0 -[ ]*[a-f0-9]+: 00 00 00 02 00 e0 nop.m 0x0 -[ ]*[a-f0-9]+: 00 08 00 07 mov b7=3Dr0;; -[ ]*[a-f0-9]+: 09 00 00 00 01 00 \[MMI\] nop.m 0x0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.m 0x0 -[ ]*[a-f0-9]+: 00 08 00 07 mov b0=3Dr0;; -[ ]*[a-f0-9]+: 09 00 00 00 01 00 \[MMI\] nop.m 0x0 -[ ]*[a-f0-9]+: 10 00 00 44 08 00 mov.m r1=3Dar.k0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 09 00 00 00 01 00 \[MMI\] nop.m 0x0 -[ ]*[a-f0-9]+: 10 00 04 44 08 00 mov.m r1=3Dar.k1 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 09 00 00 00 01 00 \[MMI\] nop.m 0x0 -[ ]*[a-f0-9]+: 10 00 08 44 08 00 mov.m r1=3Dar.k2 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 09 00 00 00 01 00 \[MMI\] nop.m 0x0 -[ ]*[a-f0-9]+: 10 00 0c 44 08 00 mov.m r1=3Dar.k3 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 09 00 00 00 01 00 \[MMI\] nop.m 0x0 -[ ]*[a-f0-9]+: 10 00 10 44 08 00 mov.m r1=3Dar.k4 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 09 00 00 00 01 00 \[MMI\] nop.m 0x0 -[ ]*[a-f0-9]+: 10 00 14 44 08 00 mov.m r1=3Dar.k5 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 09 00 00 00 01 00 \[MMI\] nop.m 0x0 -[ ]*[a-f0-9]+: 10 00 18 44 08 00 mov.m r1=3Dar.k6 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 09 00 00 00 01 00 \[MMI\] nop.m 0x0 -[ ]*[a-f0-9]+: 10 00 1c 44 08 00 mov.m r1=3Dar.k7 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 09 00 00 00 01 00 \[MMI\] nop.m 0x0 -[ ]*[a-f0-9]+: 10 00 40 44 08 00 mov.m r1=3Dar.rsc -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 09 00 00 00 01 00 \[MMI\] nop.m 0x0 -[ ]*[a-f0-9]+: 10 00 44 44 08 00 mov.m r1=3Dar.bsp -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 09 00 00 00 01 00 \[MMI\] nop.m 0x0 -[ ]*[a-f0-9]+: 10 00 48 44 08 00 mov.m r1=3Dar.bspstore -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 09 00 00 00 01 00 \[MMI\] nop.m 0x0 -[ ]*[a-f0-9]+: 10 00 4c 44 08 00 mov.m r1=3Dar.rnat -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 09 00 00 00 01 00 \[MMI\] nop.m 0x0 -[ ]*[a-f0-9]+: 10 00 54 44 08 00 mov.m r1=3Dar.fcr -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 09 00 00 00 01 00 \[MMI\] nop.m 0x0 -[ ]*[a-f0-9]+: 10 00 60 44 08 00 mov.m r1=3Dar.eflag -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 09 00 00 00 01 00 \[MMI\] nop.m 0x0 -[ ]*[a-f0-9]+: 10 00 64 44 08 00 mov.m r1=3Dar.csd -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 09 00 00 00 01 00 \[MMI\] nop.m 0x0 -[ ]*[a-f0-9]+: 10 00 68 44 08 00 mov.m r1=3Dar.ssd -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 09 00 00 00 01 00 \[MMI\] nop.m 0x0 -[ ]*[a-f0-9]+: 10 00 6c 44 08 00 mov.m r1=3Dar.cflg -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 09 00 00 00 01 00 \[MMI\] nop.m 0x0 -[ ]*[a-f0-9]+: 10 00 70 44 08 00 mov.m r1=3Dar.fsr -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 09 00 00 00 01 00 \[MMI\] nop.m 0x0 -[ ]*[a-f0-9]+: 10 00 74 44 08 00 mov.m r1=3Dar.fir -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 09 00 00 00 01 00 \[MMI\] nop.m 0x0 -[ ]*[a-f0-9]+: 10 00 78 44 08 00 mov.m r1=3Dar.fdr -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 09 00 00 00 01 00 \[MMI\] nop.m 0x0 -[ ]*[a-f0-9]+: 10 00 80 44 08 00 mov.m r1=3Dar.ccv -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 09 00 00 00 01 00 \[MMI\] nop.m 0x0 -[ ]*[a-f0-9]+: 10 00 90 44 08 00 mov.m r1=3Dar.unat -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 09 00 00 00 01 00 \[MMI\] nop.m 0x0 -[ ]*[a-f0-9]+: 10 00 a0 44 08 00 mov.m r1=3Dar.fpsr -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 09 00 00 00 01 00 \[MMI\] nop.m 0x0 -[ ]*[a-f0-9]+: 10 00 b0 44 08 00 mov.m r1=3Dar.itc -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 09 00 00 00 01 00 \[MMI\] nop.m 0x0 -[ ]*[a-f0-9]+: 10 00 b4 44 08 00 mov.m r1=3Dar.ruc -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 09 00 00 00 01 00 \[MMI\] nop.m 0x0 -[ ]*[a-f0-9]+: 10 00 c0 44 08 00 mov.m r1=3Dar48 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 09 00 00 00 01 00 \[MMI\] nop.m 0x0 -[ ]*[a-f0-9]+: 10 00 c4 44 08 00 mov.m r1=3Dar49 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 09 00 00 00 01 00 \[MMI\] nop.m 0x0 -[ ]*[a-f0-9]+: 10 00 c8 44 08 00 mov.m r1=3Dar50 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 09 00 00 00 01 00 \[MMI\] nop.m 0x0 -[ ]*[a-f0-9]+: 10 00 cc 44 08 00 mov.m r1=3Dar51 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 09 00 00 00 01 00 \[MMI\] nop.m 0x0 -[ ]*[a-f0-9]+: 10 00 d0 44 08 00 mov.m r1=3Dar52 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 09 00 00 00 01 00 \[MMI\] nop.m 0x0 -[ ]*[a-f0-9]+: 10 00 d4 44 08 00 mov.m r1=3Dar53 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 09 00 00 00 01 00 \[MMI\] nop.m 0x0 -[ ]*[a-f0-9]+: 10 00 d8 44 08 00 mov.m r1=3Dar54 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 09 00 00 00 01 00 \[MMI\] nop.m 0x0 -[ ]*[a-f0-9]+: 10 00 dc 44 08 00 mov.m r1=3Dar55 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 09 00 00 00 01 00 \[MMI\] nop.m 0x0 -[ ]*[a-f0-9]+: 10 00 e0 44 08 00 mov.m r1=3Dar56 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 09 00 00 00 01 00 \[MMI\] nop.m 0x0 -[ ]*[a-f0-9]+: 10 00 e4 44 08 00 mov.m r1=3Dar57 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 09 00 00 00 01 00 \[MMI\] nop.m 0x0 -[ ]*[a-f0-9]+: 10 00 e8 44 08 00 mov.m r1=3Dar58 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 09 00 00 00 01 00 \[MMI\] nop.m 0x0 -[ ]*[a-f0-9]+: 10 00 ec 44 08 00 mov.m r1=3Dar59 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 09 00 00 00 01 00 \[MMI\] nop.m 0x0 -[ ]*[a-f0-9]+: 10 00 f0 44 08 00 mov.m r1=3Dar60 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 09 00 00 00 01 00 \[MMI\] nop.m 0x0 -[ ]*[a-f0-9]+: 10 00 f4 44 08 00 mov.m r1=3Dar61 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 09 00 00 00 01 00 \[MMI\] nop.m 0x0 -[ ]*[a-f0-9]+: 10 00 f8 44 08 00 mov.m r1=3Dar62 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 09 00 00 00 01 00 \[MMI\] nop.m 0x0 -[ ]*[a-f0-9]+: 10 00 fc 44 08 00 mov.m r1=3Dar63 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 09 00 00 00 01 00 \[MMI\] nop.m 0x0 -[ ]*[a-f0-9]+: 00 00 00 02 00 20 nop.m 0x0 -[ ]*[a-f0-9]+: 00 00 ca 00 mov.i r1=3Dar.pfs;; -[ ]*[a-f0-9]+: 09 00 00 00 01 00 \[MMI\] nop.m 0x0 -[ ]*[a-f0-9]+: 00 00 00 02 00 20 nop.m 0x0 -[ ]*[a-f0-9]+: 00 08 ca 00 mov.i r1=3Dar.lc;; -[ ]*[a-f0-9]+: 09 00 00 00 01 00 \[MMI\] nop.m 0x0 -[ ]*[a-f0-9]+: 00 00 00 02 00 20 nop.m 0x0 -[ ]*[a-f0-9]+: 00 10 ca 00 mov.i r1=3Dar.ec;; -[ ]*[a-f0-9]+: 09 00 00 00 01 00 \[MMI\] nop.m 0x0 -[ ]*[a-f0-9]+: 10 00 c0 45 08 00 mov.m r1=3Dar112 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 09 00 00 00 01 00 \[MMI\] nop.m 0x0 -[ ]*[a-f0-9]+: 10 00 c4 45 08 00 mov.m r1=3Dar113 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 09 00 00 00 01 00 \[MMI\] nop.m 0x0 -[ ]*[a-f0-9]+: 10 00 c8 45 08 00 mov.m r1=3Dar114 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 09 00 00 00 01 00 \[MMI\] nop.m 0x0 -[ ]*[a-f0-9]+: 10 00 cc 45 08 00 mov.m r1=3Dar115 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 09 00 00 00 01 00 \[MMI\] nop.m 0x0 -[ ]*[a-f0-9]+: 10 00 d0 45 08 00 mov.m r1=3Dar116 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 09 00 00 00 01 00 \[MMI\] nop.m 0x0 -[ ]*[a-f0-9]+: 10 00 d4 45 08 00 mov.m r1=3Dar117 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 09 00 00 00 01 00 \[MMI\] nop.m 0x0 -[ ]*[a-f0-9]+: 10 00 d8 45 08 00 mov.m r1=3Dar118 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 09 00 00 00 01 00 \[MMI\] nop.m 0x0 -[ ]*[a-f0-9]+: 10 00 dc 45 08 00 mov.m r1=3Dar119 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 09 00 00 00 01 00 \[MMI\] nop.m 0x0 -[ ]*[a-f0-9]+: 10 00 e0 45 08 00 mov.m r1=3Dar120 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 09 00 00 00 01 00 \[MMI\] nop.m 0x0 -[ ]*[a-f0-9]+: 10 00 e4 45 08 00 mov.m r1=3Dar121 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 09 00 00 00 01 00 \[MMI\] nop.m 0x0 -[ ]*[a-f0-9]+: 10 00 e8 45 08 00 mov.m r1=3Dar122 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 09 00 00 00 01 00 \[MMI\] nop.m 0x0 -[ ]*[a-f0-9]+: 10 00 ec 45 08 00 mov.m r1=3Dar123 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 09 00 00 00 01 00 \[MMI\] nop.m 0x0 -[ ]*[a-f0-9]+: 10 00 f0 45 08 00 mov.m r1=3Dar124 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 09 00 00 00 01 00 \[MMI\] nop.m 0x0 -[ ]*[a-f0-9]+: 10 00 f4 45 08 00 mov.m r1=3Dar125 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 09 00 00 00 01 00 \[MMI\] nop.m 0x0 -[ ]*[a-f0-9]+: 10 00 f8 45 08 00 mov.m r1=3Dar126 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 09 00 00 00 01 00 \[MMI\] nop.m 0x0 -[ ]*[a-f0-9]+: 10 00 fc 45 08 00 mov.m r1=3Dar127 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 09 00 00 00 01 00 \[MMI\] nop.m 0x0 -[ ]*[a-f0-9]+: 10 00 00 44 08 00 mov.m r1=3Dar.k0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 09 00 00 00 01 00 \[MMI\] nop.m 0x0 -[ ]*[a-f0-9]+: 10 00 04 44 08 00 mov.m r1=3Dar.k1 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 09 00 00 00 01 00 \[MMI\] nop.m 0x0 -[ ]*[a-f0-9]+: 10 00 08 44 08 00 mov.m r1=3Dar.k2 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 09 00 00 00 01 00 \[MMI\] nop.m 0x0 -[ ]*[a-f0-9]+: 10 00 0c 44 08 00 mov.m r1=3Dar.k3 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 09 00 00 00 01 00 \[MMI\] nop.m 0x0 -[ ]*[a-f0-9]+: 10 00 10 44 08 00 mov.m r1=3Dar.k4 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 09 00 00 00 01 00 \[MMI\] nop.m 0x0 -[ ]*[a-f0-9]+: 10 00 14 44 08 00 mov.m r1=3Dar.k5 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 09 00 00 00 01 00 \[MMI\] nop.m 0x0 -[ ]*[a-f0-9]+: 10 00 18 44 08 00 mov.m r1=3Dar.k6 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 09 00 00 00 01 00 \[MMI\] nop.m 0x0 -[ ]*[a-f0-9]+: 10 00 1c 44 08 00 mov.m r1=3Dar.k7 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 09 00 00 00 01 00 \[MMI\] nop.m 0x0 -[ ]*[a-f0-9]+: 10 00 40 44 08 00 mov.m r1=3Dar.rsc -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 09 00 00 00 01 00 \[MMI\] nop.m 0x0 -[ ]*[a-f0-9]+: 10 00 44 44 08 00 mov.m r1=3Dar.bsp -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 09 00 00 00 01 00 \[MMI\] nop.m 0x0 -[ ]*[a-f0-9]+: 10 00 48 44 08 00 mov.m r1=3Dar.bspstore -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 09 00 00 00 01 00 \[MMI\] nop.m 0x0 -[ ]*[a-f0-9]+: 10 00 4c 44 08 00 mov.m r1=3Dar.rnat -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 09 00 00 00 01 00 \[MMI\] nop.m 0x0 -[ ]*[a-f0-9]+: 10 00 80 44 08 00 mov.m r1=3Dar.ccv -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 09 00 00 00 01 00 \[MMI\] nop.m 0x0 -[ ]*[a-f0-9]+: 10 00 90 44 08 00 mov.m r1=3Dar.unat -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 09 00 00 00 01 00 \[MMI\] nop.m 0x0 -[ ]*[a-f0-9]+: 10 00 a0 44 08 00 mov.m r1=3Dar.fpsr -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 09 00 00 00 01 00 \[MMI\] nop.m 0x0 -[ ]*[a-f0-9]+: 10 00 b0 44 08 00 mov.m r1=3Dar.itc -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 09 00 00 00 01 00 \[MMI\] nop.m 0x0 -[ ]*[a-f0-9]+: 10 00 b4 44 08 00 mov.m r1=3Dar.ruc -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 09 00 00 00 01 00 \[MMI\] nop.m 0x0 -[ ]*[a-f0-9]+: 00 00 00 02 00 20 nop.m 0x0 -[ ]*[a-f0-9]+: 00 00 ca 00 mov.i r1=3Dar.pfs;; -[ ]*[a-f0-9]+: 09 00 00 00 01 00 \[MMI\] nop.m 0x0 -[ ]*[a-f0-9]+: 00 00 00 02 00 20 nop.m 0x0 -[ ]*[a-f0-9]+: 00 08 ca 00 mov.i r1=3Dar.lc;; -[ ]*[a-f0-9]+: 09 00 00 00 01 00 \[MMI\] nop.m 0x0 -[ ]*[a-f0-9]+: 00 00 00 02 00 20 nop.m 0x0 -[ ]*[a-f0-9]+: 00 10 ca 00 mov.i r1=3Dar.ec;; -[ ]*[a-f0-9]+: 1d 08 00 00 24 04 \[MFB\] mov r1=3Dcr.dcr -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.f 0x0 -[ ]*[a-f0-9]+: 00 00 00 20 nop.b 0x0;; -[ ]*[a-f0-9]+: 1d 08 00 02 24 04 \[MFB\] mov r1=3Dcr.itm -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.f 0x0 -[ ]*[a-f0-9]+: 00 00 00 20 nop.b 0x0;; -[ ]*[a-f0-9]+: 1d 08 00 04 24 04 \[MFB\] mov r1=3Dcr.iva -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.f 0x0 -[ ]*[a-f0-9]+: 00 00 00 20 nop.b 0x0;; -[ ]*[a-f0-9]+: 1d 08 00 10 24 04 \[MFB\] mov r1=3Dcr.pta -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.f 0x0 -[ ]*[a-f0-9]+: 00 00 00 20 nop.b 0x0;; -[ ]*[a-f0-9]+: 1d 08 00 12 24 04 \[MFB\] mov r1=3Dcr9 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.f 0x0 -[ ]*[a-f0-9]+: 00 00 00 20 nop.b 0x0;; -[ ]*[a-f0-9]+: 1d 08 00 20 24 04 \[MFB\] mov r1=3Dcr.ipsr -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.f 0x0 -[ ]*[a-f0-9]+: 00 00 00 20 nop.b 0x0;; -[ ]*[a-f0-9]+: 1d 08 00 22 24 04 \[MFB\] mov r1=3Dcr.isr -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.f 0x0 -[ ]*[a-f0-9]+: 00 00 00 20 nop.b 0x0;; -[ ]*[a-f0-9]+: 1d 08 00 26 24 04 \[MFB\] mov r1=3Dcr.iip -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.f 0x0 -[ ]*[a-f0-9]+: 00 00 00 20 nop.b 0x0;; -[ ]*[a-f0-9]+: 1d 08 00 28 24 04 \[MFB\] mov r1=3Dcr.ifa -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.f 0x0 -[ ]*[a-f0-9]+: 00 00 00 20 nop.b 0x0;; -[ ]*[a-f0-9]+: 1d 08 00 2a 24 04 \[MFB\] mov r1=3Dcr.itir -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.f 0x0 -[ ]*[a-f0-9]+: 00 00 00 20 nop.b 0x0;; -[ ]*[a-f0-9]+: 1d 08 00 2c 24 04 \[MFB\] mov r1=3Dcr.iipa -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.f 0x0 -[ ]*[a-f0-9]+: 00 00 00 20 nop.b 0x0;; -[ ]*[a-f0-9]+: 1d 08 00 2e 24 04 \[MFB\] mov r1=3Dcr.ifs -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.f 0x0 -[ ]*[a-f0-9]+: 00 00 00 20 nop.b 0x0;; -[ ]*[a-f0-9]+: 1d 08 00 30 24 04 \[MFB\] mov r1=3Dcr.iim -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.f 0x0 -[ ]*[a-f0-9]+: 00 00 00 20 nop.b 0x0;; -[ ]*[a-f0-9]+: 1d 08 00 32 24 04 \[MFB\] mov r1=3Dcr.iha -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.f 0x0 -[ ]*[a-f0-9]+: 00 00 00 20 nop.b 0x0;; -[ ]*[a-f0-9]+: 1d 08 00 80 24 04 \[MFB\] mov r1=3Dcr.lid -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.f 0x0 -[ ]*[a-f0-9]+: 00 00 00 20 nop.b 0x0;; -[ ]*[a-f0-9]+: 1d 08 00 82 24 04 \[MFB\] mov r1=3Dcr.ivr -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.f 0x0 -[ ]*[a-f0-9]+: 00 00 00 20 nop.b 0x0;; -[ ]*[a-f0-9]+: 1d 08 00 84 24 04 \[MFB\] mov r1=3Dcr.tpr -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.f 0x0 -[ ]*[a-f0-9]+: 00 00 00 20 nop.b 0x0;; -[ ]*[a-f0-9]+: 1d 08 00 86 24 04 \[MFB\] mov r1=3Dcr.eoi -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.f 0x0 -[ ]*[a-f0-9]+: 00 00 00 20 nop.b 0x0;; -[ ]*[a-f0-9]+: 1d 08 00 88 24 04 \[MFB\] mov r1=3Dcr.irr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.f 0x0 -[ ]*[a-f0-9]+: 00 00 00 20 nop.b 0x0;; -[ ]*[a-f0-9]+: 1d 08 00 8a 24 04 \[MFB\] mov r1=3Dcr.irr1 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.f 0x0 -[ ]*[a-f0-9]+: 00 00 00 20 nop.b 0x0;; -[ ]*[a-f0-9]+: 1d 08 00 8c 24 04 \[MFB\] mov r1=3Dcr.irr2 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.f 0x0 -[ ]*[a-f0-9]+: 00 00 00 20 nop.b 0x0;; -[ ]*[a-f0-9]+: 1d 08 00 8e 24 04 \[MFB\] mov r1=3Dcr.irr3 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.f 0x0 -[ ]*[a-f0-9]+: 00 00 00 20 nop.b 0x0;; -[ ]*[a-f0-9]+: 1d 08 00 90 24 04 \[MFB\] mov r1=3Dcr.itv -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.f 0x0 -[ ]*[a-f0-9]+: 00 00 00 20 nop.b 0x0;; -[ ]*[a-f0-9]+: 1d 08 00 92 24 04 \[MFB\] mov r1=3Dcr.pmv -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.f 0x0 -[ ]*[a-f0-9]+: 00 00 00 20 nop.b 0x0;; -[ ]*[a-f0-9]+: 1d 08 00 94 24 04 \[MFB\] mov r1=3Dcr.cmcv -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.f 0x0 -[ ]*[a-f0-9]+: 00 00 00 20 nop.b 0x0;; -[ ]*[a-f0-9]+: 1d 08 00 a0 24 04 \[MFB\] mov r1=3Dcr.lrr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.f 0x0 -[ ]*[a-f0-9]+: 00 00 00 20 nop.b 0x0;; -[ ]*[a-f0-9]+: 1d 08 00 a2 24 04 \[MFB\] mov r1=3Dcr.lrr1 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.f 0x0 -[ ]*[a-f0-9]+: 00 00 00 20 nop.b 0x0;; -[ ]*[a-f0-9]+: 1d 08 00 00 24 04 \[MFB\] mov r1=3Dcr.dcr -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.f 0x0 -[ ]*[a-f0-9]+: 00 00 00 20 nop.b 0x0;; -[ ]*[a-f0-9]+: 1d 08 00 02 24 04 \[MFB\] mov r1=3Dcr.itm -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.f 0x0 -[ ]*[a-f0-9]+: 00 00 00 20 nop.b 0x0;; -[ ]*[a-f0-9]+: 1d 08 00 04 24 04 \[MFB\] mov r1=3Dcr.iva -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.f 0x0 -[ ]*[a-f0-9]+: 00 00 00 20 nop.b 0x0;; -[ ]*[a-f0-9]+: 1d 08 00 10 24 04 \[MFB\] mov r1=3Dcr.pta -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.f 0x0 -[ ]*[a-f0-9]+: 00 00 00 20 nop.b 0x0;; -[ ]*[a-f0-9]+: 1d 08 00 20 24 04 \[MFB\] mov r1=3Dcr.ipsr -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.f 0x0 -[ ]*[a-f0-9]+: 00 00 00 20 nop.b 0x0;; -[ ]*[a-f0-9]+: 1d 08 00 22 24 04 \[MFB\] mov r1=3Dcr.isr -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.f 0x0 -[ ]*[a-f0-9]+: 00 00 00 20 nop.b 0x0;; -[ ]*[a-f0-9]+: 1d 08 00 26 24 04 \[MFB\] mov r1=3Dcr.iip -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.f 0x0 -[ ]*[a-f0-9]+: 00 00 00 20 nop.b 0x0;; -[ ]*[a-f0-9]+: 1d 08 00 2c 24 04 \[MFB\] mov r1=3Dcr.iipa -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.f 0x0 -[ ]*[a-f0-9]+: 00 00 00 20 nop.b 0x0;; -[ ]*[a-f0-9]+: 1d 08 00 2e 24 04 \[MFB\] mov r1=3Dcr.ifs -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.f 0x0 -[ ]*[a-f0-9]+: 00 00 00 20 nop.b 0x0;; -[ ]*[a-f0-9]+: 1d 08 00 30 24 04 \[MFB\] mov r1=3Dcr.iim -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.f 0x0 -[ ]*[a-f0-9]+: 00 00 00 20 nop.b 0x0;; -[ ]*[a-f0-9]+: 1d 08 00 32 24 04 \[MFB\] mov r1=3Dcr.iha -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.f 0x0 -[ ]*[a-f0-9]+: 00 00 00 20 nop.b 0x0;; -[ ]*[a-f0-9]+: 1d 08 00 34 24 04 \[MFB\] mov r1=3Dcr.iib0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.f 0x0 -[ ]*[a-f0-9]+: 00 00 00 20 nop.b 0x0;; -[ ]*[a-f0-9]+: 1d 08 00 36 24 04 \[MFB\] mov r1=3Dcr.iib1 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.f 0x0 -[ ]*[a-f0-9]+: 00 00 00 20 nop.b 0x0;; -[ ]*[a-f0-9]+: 1d 08 00 80 24 04 \[MFB\] mov r1=3Dcr.lid -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.f 0x0 -[ ]*[a-f0-9]+: 00 00 00 20 nop.b 0x0;; -[ ]*[a-f0-9]+: 1d 08 00 82 24 04 \[MFB\] mov r1=3Dcr.ivr -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.f 0x0 -[ ]*[a-f0-9]+: 00 00 00 20 nop.b 0x0;; -[ ]*[a-f0-9]+: 1d 08 00 84 24 04 \[MFB\] mov r1=3Dcr.tpr -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.f 0x0 -[ ]*[a-f0-9]+: 00 00 00 20 nop.b 0x0;; -[ ]*[a-f0-9]+: 1d 08 00 86 24 04 \[MFB\] mov r1=3Dcr.eoi -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.f 0x0 -[ ]*[a-f0-9]+: 00 00 00 20 nop.b 0x0;; -[ ]*[a-f0-9]+: 1d 08 00 88 24 04 \[MFB\] mov r1=3Dcr.irr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.f 0x0 -[ ]*[a-f0-9]+: 00 00 00 20 nop.b 0x0;; -[ ]*[a-f0-9]+: 1d 08 00 8a 24 04 \[MFB\] mov r1=3Dcr.irr1 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.f 0x0 -[ ]*[a-f0-9]+: 00 00 00 20 nop.b 0x0;; -[ ]*[a-f0-9]+: 1d 08 00 8c 24 04 \[MFB\] mov r1=3Dcr.irr2 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.f 0x0 -[ ]*[a-f0-9]+: 00 00 00 20 nop.b 0x0;; -[ ]*[a-f0-9]+: 1d 08 00 8e 24 04 \[MFB\] mov r1=3Dcr.irr3 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.f 0x0 -[ ]*[a-f0-9]+: 00 00 00 20 nop.b 0x0;; -[ ]*[a-f0-9]+: 1d 08 00 90 24 04 \[MFB\] mov r1=3Dcr.itv -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.f 0x0 -[ ]*[a-f0-9]+: 00 00 00 20 nop.b 0x0;; -[ ]*[a-f0-9]+: 1d 08 00 92 24 04 \[MFB\] mov r1=3Dcr.pmv -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.f 0x0 -[ ]*[a-f0-9]+: 00 00 00 20 nop.b 0x0;; -[ ]*[a-f0-9]+: 1d 08 00 a0 24 04 \[MFB\] mov r1=3Dcr.lrr0 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.f 0x0 -[ ]*[a-f0-9]+: 00 00 00 20 nop.b 0x0;; -[ ]*[a-f0-9]+: 1d 08 00 a2 24 04 \[MFB\] mov r1=3Dcr.lrr1 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.f 0x0 -[ ]*[a-f0-9]+: 00 00 00 20 nop.b 0x0;; -[ ]*[a-f0-9]+: 1d 08 00 94 24 04 \[MFB\] mov r1=3Dcr.cmcv -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.f 0x0 -[ ]*[a-f0-9]+: 00 00 00 20 nop.b 0x0;; -[ ]*[a-f0-9]+: 1d 08 00 00 25 04 \[MFB\] mov r1=3Dpsr -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.f 0x0 -[ ]*[a-f0-9]+: 00 00 00 20 nop.b 0x0;; -[ ]*[a-f0-9]+: 1d 08 00 00 21 04 \[MFB\] mov r1=3Dpsr.um -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.f 0x0 -[ ]*[a-f0-9]+: 00 00 00 20 nop.b 0x0;; -[ ]*[a-f0-9]+: 09 00 00 00 01 00 \[MMI\] nop.m 0x0 -[ ]*[a-f0-9]+: 00 00 00 02 00 20 nop.m 0x0 -[ ]*[a-f0-9]+: 00 00 c0 00 mov r1=3Dip;; -[ ]*[a-f0-9]+: 09 08 00 06 14 04 \[MMI\] mov r1=3Dpmc\[r3\] -[ ]*[a-f0-9]+: 20 00 10 28 08 00 mov r2=3Dpmc\[r4\] -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 09 08 00 06 15 04 \[MMI\] mov r1=3Dpmd\[r3\] -[ ]*[a-f0-9]+: 20 00 10 2a 08 00 mov r2=3Dpmd\[r4\] -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 09 08 00 06 13 04 \[MMI\] mov r1=3Dpkr\[r3\] -[ ]*[a-f0-9]+: 20 00 10 26 08 00 mov r2=3Dpkr\[r4\] -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 09 08 00 06 10 04 \[MMI\] mov r1=3Drr\[r3\] -[ ]*[a-f0-9]+: 20 00 10 20 08 00 mov r2=3Drr\[r4\] -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 09 08 00 06 12 04 \[MMI\] mov r1=3Dibr\[r3\] -[ ]*[a-f0-9]+: 20 00 10 24 08 00 mov r2=3Dibr\[r4\] -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 09 08 00 06 11 04 \[MMI\] mov r1=3Ddbr\[r3\] -[ ]*[a-f0-9]+: 20 00 10 22 08 00 mov r2=3Ddbr\[r4\] -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 09 08 00 06 17 04 \[MMI\] mov r1=3Dcpuid\[r3\] -[ ]*[a-f0-9]+: 20 00 10 2e 08 00 mov r2=3Dcpuid\[r4\] -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 09 08 00 06 17 04 \[MMI\] mov r1=3Dcpuid\[r3\] -[ ]*[a-f0-9]+: 20 00 10 2e 08 00 mov r2=3Dcpuid\[r4\] -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; diff --git a/gas/testsuite/gas/ia64/regs.pl b/gas/testsuite/gas/ia64/regs.pl deleted file mode 100644 index 1c7df5c390f..00000000000 --- a/gas/testsuite/gas/ia64/regs.pl +++ /dev/null @@ -1,150 +0,0 @@ -print ".text\n"; -print "\t.type _start,@","function\n"; -print "_start:\n\n"; - -print "// Fixed and stacked integer registers.\n"; -for ($i =3D 1; $i < 128; ++$i) { - print "\t{ .mii; mov r$i =3D r0; nop.i 0; nop.i 0;; }\n"; -} -print "\n"; - -print "// Alternate names for input registers\n"; -print "\t.regstk 96, 0, 0, 0\n"; -for ($i =3D 0; $i < 96; ++$i) { - print "\t{ .mii; mov in$i =3D r0; nop.i 0; nop.i 0;; }\n"; -} -print "\n"; - -print "// Alternate names for output registers\n"; -print "\t.regstk 0, 0, 96, 0\n"; -for ($i =3D 0; $i < 96; ++$i) { - print "\t{ .mii; mov out$i =3D r0; nop.i 0; nop.i 0;; }\n"; -} -print "\n"; - -print "// Alternate names for local registers\n"; -print "\t.regstk 0, 96, 0, 0\n"; -for ($i =3D 0; $i < 96; ++$i) { - print "\t{ .mii; mov loc$i =3D r0; nop.i 0; nop.i 0;; }\n"; -} -print "\n"; - -print "// Return value registers\n"; -for ($i =3D 0; $i < 4; ++$i) { - print "\t{ .mii; mov ret$i =3D r0; nop.i 0; nop.i 0;; }\n"; -} -print "\n"; - -print "\t{ .mii;\n"; -print "\tmov gp =3D r0\n"; -print "\tmov sp =3D r0\n"; -print "\tmov tp =3D r0;; }\n\n"; - -print "// Floating point registers\n"; -for ($i =3D 2; $i < 128; ++$i) { - print "\t{ .mfi; mov f$i =3D f0 ;; }\n"; -} -print "\n"; - -print "// Floating point argument registers\n"; -for ($i =3D 0; $i < 8; ++$i) { - print "\t{ .mfi; mov farg$i =3D f1 ;; }\n"; -} -print "\n"; - -print "// Floating point return value registers\n"; -for ($i =3D 0; $i < 8; ++$i) { - print "\t{ .mfi; mov fret$i =3D f1 ;; }\n"; -} -print "\n"; - -print "// Predicate registers\n"; -for ($i =3D 0; $i < 64; ++$i) { - print "\t{ .mii; (p$i)\tmov r", $i+1, " =3D r0; nop.i 0; nop.i 0;; }\n"; -} -print "\n"; - -print "// Predicates as a unit\n"; -print "\t{ .mmi; nop.m 0; mov r1 =3D pr ;; }\n"; -print "//\tmov r2 =3D pr.rot\n"; -print "\n"; - -print "// Branch registers.\n"; -for ($i =3D 0; $i < 8; ++$i) { - print "\t{ .mmi; mov b$i =3D r0;; }\n"; -} -print "\n"; - -print "\t{ .mmi; mov rp =3D r0;; }\n"; -print "\n"; - -print "// Application registers\n"; -@reserved =3D ( 8..15, 20, 22..23, 31, 33..35, 37..39, 41..47, 67..111 ); -%reserved =3D (); -foreach $i (@reserved) { - $reserved{$i} =3D 1; -} -for ($i =3D 0; $i < 128; ++$i) { - print "//" if $reserved{$i}; - print "\t{ .mmi; nop.m 0; mov r1 =3D ar$i ;; }"; - print "\t\t// reserved" if $reserved{$i}; - print "\n"; -} -print "\n"; - -print "// Application registers by name\n"; -for ($i =3D 0; $i < 8; ++$i) { - print "\t{ .mmi; nop.m 0; mov r1 =3D ar.k$i ;;}\n"; -} - -@regs =3D ( "rsc", "bsp", "bspstore", "rnat", "ccv", "unat", "fpsr", "itc", - "pfs", "lc", "ec" ); -foreach $i (@regs) { - print "\t{ .mmi; nop.m 0; mov r1 =3D ar.$i ;; }\n"; -} -print "\n"; - -print "// Control registers\n"; -@reserved =3D ( 3..7, 10..15, 18, 26..63, 75..79, 82..127 ); -%reserved =3D (); -foreach $i (@reserved) { - $reserved{$i} =3D 1; -} -for ($i =3D 0; $i < 128; ++$i) { - print "//" if $reserved{$i}; - print "\t{ .mfb; mov r1 =3D cr$i ;; }"; - print "\t\t// reserved" if $reserved{$i}; - print "\n"; -} -print "\n"; - -print "// Control registers by name\n"; -@regs =3D ( "dcr", "itm", "iva", "pta", "ipsr", "isr", "iip", - "iipa", "ifs", "iim", "iha", "lid", "ivr", - "tpr", "eoi", "irr0", "irr1", "irr2", "irr3", "itv", "pmv", - "lrr0", "lrr1", "cmcv" ); -# ias doesn't accept these, despite documentation to the contrary. -# push @regs, "ida", "idtr", "iitr" -foreach $i (@regs) { - print "\t{ .mfb; mov r1 =3D cr.$i ;; }\n"; -} -print "\n"; - - -print "// Other registers\n"; -print "\t{ .mfb; mov r1 =3D psr ;; }\n"; -print "//\t{ .mfb; mov r1 =3D psr.l ;; }\n"; -print "\t{ .mfb; mov r1 =3D psr.um ;; }\n"; -print "\t{ .mmi; mov r1 =3D ip ;; }\n"; -print "\n"; - -print "// Indirect register files\n"; -@regs =3D ("pmc", "pmd", "pkr", "rr", "ibr", "dbr", "CPUID", "cpuid"); -# ias doesn't accept these, despite documentation to the contrary. -# push @regs, "itr", "dtr"; -foreach $i (@regs) { - print "\t{ .mmi\n"; - print "\tmov r1 =3D ${i}[r3]\n"; - print "\tmov r2 =3D ${i}[r4]\n"; - print "\tnop.i 0;; }\n"; -} diff --git a/gas/testsuite/gas/ia64/regs.s b/gas/testsuite/gas/ia64/regs.s deleted file mode 100644 index 1c4200e6077..00000000000 --- a/gas/testsuite/gas/ia64/regs.s +++ /dev/null @@ -1,1020 +0,0 @@ -.text - .type _start,@function -_start: - -// Fixed and stacked integer registers. - { .mii; mov r1 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov r2 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov r3 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov r4 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov r5 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov r6 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov r7 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov r8 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov r9 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov r10 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov r11 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov r12 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov r13 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov r14 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov r15 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov r16 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov r17 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov r18 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov r19 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov r20 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov r21 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov r22 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov r23 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov r24 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov r25 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov r26 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov r27 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov r28 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov r29 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov r30 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov r31 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov r32 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov r33 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov r34 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov r35 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov r36 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov r37 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov r38 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov r39 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov r40 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov r41 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov r42 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov r43 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov r44 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov r45 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov r46 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov r47 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov r48 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov r49 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov r50 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov r51 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov r52 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov r53 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov r54 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov r55 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov r56 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov r57 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov r58 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov r59 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov r60 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov r61 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov r62 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov r63 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov r64 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov r65 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov r66 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov r67 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov r68 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov r69 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov r70 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov r71 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov r72 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov r73 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov r74 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov r75 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov r76 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov r77 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov r78 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov r79 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov r80 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov r81 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov r82 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov r83 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov r84 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov r85 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov r86 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov r87 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov r88 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov r89 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov r90 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov r91 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov r92 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov r93 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov r94 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov r95 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov r96 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov r97 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov r98 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov r99 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov r100 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov r101 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov r102 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov r103 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov r104 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov r105 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov r106 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov r107 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov r108 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov r109 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov r110 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov r111 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov r112 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov r113 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov r114 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov r115 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov r116 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov r117 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov r118 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov r119 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov r120 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov r121 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov r122 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov r123 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov r124 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov r125 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov r126 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov r127 =3D r0; nop.i 0; nop.i 0;; } - -// Alternate names for input registers - .regstk 96, 0, 0, 0 - { .mii; mov in0 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov in1 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov in2 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov in3 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov in4 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov in5 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov in6 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov in7 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov in8 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov in9 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov in10 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov in11 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov in12 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov in13 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov in14 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov in15 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov in16 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov in17 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov in18 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov in19 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov in20 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov in21 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov in22 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov in23 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov in24 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov in25 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov in26 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov in27 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov in28 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov in29 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov in30 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov in31 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov in32 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov in33 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov in34 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov in35 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov in36 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov in37 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov in38 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov in39 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov in40 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov in41 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov in42 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov in43 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov in44 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov in45 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov in46 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov in47 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov in48 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov in49 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov in50 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov in51 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov in52 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov in53 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov in54 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov in55 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov in56 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov in57 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov in58 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov in59 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov in60 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov in61 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov in62 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov in63 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov in64 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov in65 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov in66 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov in67 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov in68 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov in69 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov in70 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov in71 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov in72 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov in73 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov in74 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov in75 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov in76 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov in77 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov in78 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov in79 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov in80 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov in81 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov in82 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov in83 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov in84 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov in85 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov in86 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov in87 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov in88 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov in89 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov in90 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov in91 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov in92 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov in93 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov in94 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov in95 =3D r0; nop.i 0; nop.i 0;; } - -// Alternate names for output registers - .regstk 0, 0, 96, 0 - { .mii; mov out0 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov out1 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov out2 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov out3 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov out4 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov out5 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov out6 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov out7 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov out8 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov out9 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov out10 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov out11 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov out12 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov out13 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov out14 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov out15 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov out16 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov out17 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov out18 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov out19 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov out20 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov out21 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov out22 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov out23 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov out24 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov out25 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov out26 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov out27 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov out28 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov out29 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov out30 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov out31 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov out32 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov out33 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov out34 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov out35 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov out36 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov out37 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov out38 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov out39 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov out40 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov out41 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov out42 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov out43 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov out44 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov out45 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov out46 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov out47 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov out48 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov out49 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov out50 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov out51 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov out52 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov out53 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov out54 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov out55 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov out56 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov out57 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov out58 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov out59 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov out60 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov out61 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov out62 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov out63 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov out64 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov out65 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov out66 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov out67 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov out68 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov out69 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov out70 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov out71 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov out72 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov out73 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov out74 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov out75 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov out76 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov out77 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov out78 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov out79 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov out80 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov out81 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov out82 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov out83 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov out84 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov out85 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov out86 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov out87 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov out88 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov out89 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov out90 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov out91 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov out92 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov out93 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov out94 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov out95 =3D r0; nop.i 0; nop.i 0;; } - -// Alternate names for local registers - .regstk 0, 96, 0, 0 - { .mii; mov loc0 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov loc1 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov loc2 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov loc3 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov loc4 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov loc5 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov loc6 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov loc7 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov loc8 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov loc9 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov loc10 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov loc11 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov loc12 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov loc13 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov loc14 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov loc15 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov loc16 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov loc17 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov loc18 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov loc19 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov loc20 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov loc21 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov loc22 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov loc23 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov loc24 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov loc25 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov loc26 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov loc27 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov loc28 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov loc29 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov loc30 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov loc31 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov loc32 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov loc33 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov loc34 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov loc35 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov loc36 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov loc37 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov loc38 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov loc39 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov loc40 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov loc41 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov loc42 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov loc43 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov loc44 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov loc45 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov loc46 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov loc47 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov loc48 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov loc49 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov loc50 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov loc51 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov loc52 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov loc53 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov loc54 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov loc55 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov loc56 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov loc57 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov loc58 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov loc59 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov loc60 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov loc61 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov loc62 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov loc63 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov loc64 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov loc65 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov loc66 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov loc67 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov loc68 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov loc69 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov loc70 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov loc71 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov loc72 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov loc73 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov loc74 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov loc75 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov loc76 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov loc77 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov loc78 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov loc79 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov loc80 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov loc81 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov loc82 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov loc83 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov loc84 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov loc85 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov loc86 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov loc87 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov loc88 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov loc89 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov loc90 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov loc91 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov loc92 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov loc93 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov loc94 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov loc95 =3D r0; nop.i 0; nop.i 0;; } - -// Return value registers - { .mii; mov ret0 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov ret1 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov ret2 =3D r0; nop.i 0; nop.i 0;; } - { .mii; mov ret3 =3D r0; nop.i 0; nop.i 0;; } - - { .mii; - mov gp =3D r0 - mov sp =3D r0 - mov tp =3D r0;; } - -// Floating point registers - { .mfi; mov f2 =3D f0 ;; } - { .mfi; mov f3 =3D f0 ;; } - { .mfi; mov f4 =3D f0 ;; } - { .mfi; mov f5 =3D f0 ;; } - { .mfi; mov f6 =3D f0 ;; } - { .mfi; mov f7 =3D f0 ;; } - { .mfi; mov f8 =3D f0 ;; } - { .mfi; mov f9 =3D f0 ;; } - { .mfi; mov f10 =3D f0 ;; } - { .mfi; mov f11 =3D f0 ;; } - { .mfi; mov f12 =3D f0 ;; } - { .mfi; mov f13 =3D f0 ;; } - { .mfi; mov f14 =3D f0 ;; } - { .mfi; mov f15 =3D f0 ;; } - { .mfi; mov f16 =3D f0 ;; } - { .mfi; mov f17 =3D f0 ;; } - { .mfi; mov f18 =3D f0 ;; } - { .mfi; mov f19 =3D f0 ;; } - { .mfi; mov f20 =3D f0 ;; } - { .mfi; mov f21 =3D f0 ;; } - { .mfi; mov f22 =3D f0 ;; } - { .mfi; mov f23 =3D f0 ;; } - { .mfi; mov f24 =3D f0 ;; } - { .mfi; mov f25 =3D f0 ;; } - { .mfi; mov f26 =3D f0 ;; } - { .mfi; mov f27 =3D f0 ;; } - { .mfi; mov f28 =3D f0 ;; } - { .mfi; mov f29 =3D f0 ;; } - { .mfi; mov f30 =3D f0 ;; } - { .mfi; mov f31 =3D f0 ;; } - { .mfi; mov f32 =3D f0 ;; } - { .mfi; mov f33 =3D f0 ;; } - { .mfi; mov f34 =3D f0 ;; } - { .mfi; mov f35 =3D f0 ;; } - { .mfi; mov f36 =3D f0 ;; } - { .mfi; mov f37 =3D f0 ;; } - { .mfi; mov f38 =3D f0 ;; } - { .mfi; mov f39 =3D f0 ;; } - { .mfi; mov f40 =3D f0 ;; } - { .mfi; mov f41 =3D f0 ;; } - { .mfi; mov f42 =3D f0 ;; } - { .mfi; mov f43 =3D f0 ;; } - { .mfi; mov f44 =3D f0 ;; } - { .mfi; mov f45 =3D f0 ;; } - { .mfi; mov f46 =3D f0 ;; } - { .mfi; mov f47 =3D f0 ;; } - { .mfi; mov f48 =3D f0 ;; } - { .mfi; mov f49 =3D f0 ;; } - { .mfi; mov f50 =3D f0 ;; } - { .mfi; mov f51 =3D f0 ;; } - { .mfi; mov f52 =3D f0 ;; } - { .mfi; mov f53 =3D f0 ;; } - { .mfi; mov f54 =3D f0 ;; } - { .mfi; mov f55 =3D f0 ;; } - { .mfi; mov f56 =3D f0 ;; } - { .mfi; mov f57 =3D f0 ;; } - { .mfi; mov f58 =3D f0 ;; } - { .mfi; mov f59 =3D f0 ;; } - { .mfi; mov f60 =3D f0 ;; } - { .mfi; mov f61 =3D f0 ;; } - { .mfi; mov f62 =3D f0 ;; } - { .mfi; mov f63 =3D f0 ;; } - { .mfi; mov f64 =3D f0 ;; } - { .mfi; mov f65 =3D f0 ;; } - { .mfi; mov f66 =3D f0 ;; } - { .mfi; mov f67 =3D f0 ;; } - { .mfi; mov f68 =3D f0 ;; } - { .mfi; mov f69 =3D f0 ;; } - { .mfi; mov f70 =3D f0 ;; } - { .mfi; mov f71 =3D f0 ;; } - { .mfi; mov f72 =3D f0 ;; } - { .mfi; mov f73 =3D f0 ;; } - { .mfi; mov f74 =3D f0 ;; } - { .mfi; mov f75 =3D f0 ;; } - { .mfi; mov f76 =3D f0 ;; } - { .mfi; mov f77 =3D f0 ;; } - { .mfi; mov f78 =3D f0 ;; } - { .mfi; mov f79 =3D f0 ;; } - { .mfi; mov f80 =3D f0 ;; } - { .mfi; mov f81 =3D f0 ;; } - { .mfi; mov f82 =3D f0 ;; } - { .mfi; mov f83 =3D f0 ;; } - { .mfi; mov f84 =3D f0 ;; } - { .mfi; mov f85 =3D f0 ;; } - { .mfi; mov f86 =3D f0 ;; } - { .mfi; mov f87 =3D f0 ;; } - { .mfi; mov f88 =3D f0 ;; } - { .mfi; mov f89 =3D f0 ;; } - { .mfi; mov f90 =3D f0 ;; } - { .mfi; mov f91 =3D f0 ;; } - { .mfi; mov f92 =3D f0 ;; } - { .mfi; mov f93 =3D f0 ;; } - { .mfi; mov f94 =3D f0 ;; } - { .mfi; mov f95 =3D f0 ;; } - { .mfi; mov f96 =3D f0 ;; } - { .mfi; mov f97 =3D f0 ;; } - { .mfi; mov f98 =3D f0 ;; } - { .mfi; mov f99 =3D f0 ;; } - { .mfi; mov f100 =3D f0 ;; } - { .mfi; mov f101 =3D f0 ;; } - { .mfi; mov f102 =3D f0 ;; } - { .mfi; mov f103 =3D f0 ;; } - { .mfi; mov f104 =3D f0 ;; } - { .mfi; mov f105 =3D f0 ;; } - { .mfi; mov f106 =3D f0 ;; } - { .mfi; mov f107 =3D f0 ;; } - { .mfi; mov f108 =3D f0 ;; } - { .mfi; mov f109 =3D f0 ;; } - { .mfi; mov f110 =3D f0 ;; } - { .mfi; mov f111 =3D f0 ;; } - { .mfi; mov f112 =3D f0 ;; } - { .mfi; mov f113 =3D f0 ;; } - { .mfi; mov f114 =3D f0 ;; } - { .mfi; mov f115 =3D f0 ;; } - { .mfi; mov f116 =3D f0 ;; } - { .mfi; mov f117 =3D f0 ;; } - { .mfi; mov f118 =3D f0 ;; } - { .mfi; mov f119 =3D f0 ;; } - { .mfi; mov f120 =3D f0 ;; } - { .mfi; mov f121 =3D f0 ;; } - { .mfi; mov f122 =3D f0 ;; } - { .mfi; mov f123 =3D f0 ;; } - { .mfi; mov f124 =3D f0 ;; } - { .mfi; mov f125 =3D f0 ;; } - { .mfi; mov f126 =3D f0 ;; } - { .mfi; mov f127 =3D f0 ;; } - -// Floating point argument registers - { .mfi; mov farg0 =3D f1 ;; } - { .mfi; mov farg1 =3D f1 ;; } - { .mfi; mov farg2 =3D f1 ;; } - { .mfi; mov farg3 =3D f1 ;; } - { .mfi; mov farg4 =3D f1 ;; } - { .mfi; mov farg5 =3D f1 ;; } - { .mfi; mov farg6 =3D f1 ;; } - { .mfi; mov farg7 =3D f1 ;; } - -// Floating point return value registers - { .mfi; mov fret0 =3D f1 ;; } - { .mfi; mov fret1 =3D f1 ;; } - { .mfi; mov fret2 =3D f1 ;; } - { .mfi; mov fret3 =3D f1 ;; } - { .mfi; mov fret4 =3D f1 ;; } - { .mfi; mov fret5 =3D f1 ;; } - { .mfi; mov fret6 =3D f1 ;; } - { .mfi; mov fret7 =3D f1 ;; } - -// Predicate registers - { .mii; (p0) mov r1 =3D r0; nop.i 0; nop.i 0;; } - { .mii; (p1) mov r2 =3D r0; nop.i 0; nop.i 0;; } - { .mii; (p2) mov r3 =3D r0; nop.i 0; nop.i 0;; } - { .mii; (p3) mov r4 =3D r0; nop.i 0; nop.i 0;; } - { .mii; (p4) mov r5 =3D r0; nop.i 0; nop.i 0;; } - { .mii; (p5) mov r6 =3D r0; nop.i 0; nop.i 0;; } - { .mii; (p6) mov r7 =3D r0; nop.i 0; nop.i 0;; } - { .mii; (p7) mov r8 =3D r0; nop.i 0; nop.i 0;; } - { .mii; (p8) mov r9 =3D r0; nop.i 0; nop.i 0;; } - { .mii; (p9) mov r10 =3D r0; nop.i 0; nop.i 0;; } - { .mii; (p10) mov r11 =3D r0; nop.i 0; nop.i 0;; } - { .mii; (p11) mov r12 =3D r0; nop.i 0; nop.i 0;; } - { .mii; (p12) mov r13 =3D r0; nop.i 0; nop.i 0;; } - { .mii; (p13) mov r14 =3D r0; nop.i 0; nop.i 0;; } - { .mii; (p14) mov r15 =3D r0; nop.i 0; nop.i 0;; } - { .mii; (p15) mov r16 =3D r0; nop.i 0; nop.i 0;; } - { .mii; (p16) mov r17 =3D r0; nop.i 0; nop.i 0;; } - { .mii; (p17) mov r18 =3D r0; nop.i 0; nop.i 0;; } - { .mii; (p18) mov r19 =3D r0; nop.i 0; nop.i 0;; } - { .mii; (p19) mov r20 =3D r0; nop.i 0; nop.i 0;; } - { .mii; (p20) mov r21 =3D r0; nop.i 0; nop.i 0;; } - { .mii; (p21) mov r22 =3D r0; nop.i 0; nop.i 0;; } - { .mii; (p22) mov r23 =3D r0; nop.i 0; nop.i 0;; } - { .mii; (p23) mov r24 =3D r0; nop.i 0; nop.i 0;; } - { .mii; (p24) mov r25 =3D r0; nop.i 0; nop.i 0;; } - { .mii; (p25) mov r26 =3D r0; nop.i 0; nop.i 0;; } - { .mii; (p26) mov r27 =3D r0; nop.i 0; nop.i 0;; } - { .mii; (p27) mov r28 =3D r0; nop.i 0; nop.i 0;; } - { .mii; (p28) mov r29 =3D r0; nop.i 0; nop.i 0;; } - { .mii; (p29) mov r30 =3D r0; nop.i 0; nop.i 0;; } - { .mii; (p30) mov r31 =3D r0; nop.i 0; nop.i 0;; } - { .mii; (p31) mov r32 =3D r0; nop.i 0; nop.i 0;; } - { .mii; (p32) mov r33 =3D r0; nop.i 0; nop.i 0;; } - { .mii; (p33) mov r34 =3D r0; nop.i 0; nop.i 0;; } - { .mii; (p34) mov r35 =3D r0; nop.i 0; nop.i 0;; } - { .mii; (p35) mov r36 =3D r0; nop.i 0; nop.i 0;; } - { .mii; (p36) mov r37 =3D r0; nop.i 0; nop.i 0;; } - { .mii; (p37) mov r38 =3D r0; nop.i 0; nop.i 0;; } - { .mii; (p38) mov r39 =3D r0; nop.i 0; nop.i 0;; } - { .mii; (p39) mov r40 =3D r0; nop.i 0; nop.i 0;; } - { .mii; (p40) mov r41 =3D r0; nop.i 0; nop.i 0;; } - { .mii; (p41) mov r42 =3D r0; nop.i 0; nop.i 0;; } - { .mii; (p42) mov r43 =3D r0; nop.i 0; nop.i 0;; } - { .mii; (p43) mov r44 =3D r0; nop.i 0; nop.i 0;; } - { .mii; (p44) mov r45 =3D r0; nop.i 0; nop.i 0;; } - { .mii; (p45) mov r46 =3D r0; nop.i 0; nop.i 0;; } - { .mii; (p46) mov r47 =3D r0; nop.i 0; nop.i 0;; } - { .mii; (p47) mov r48 =3D r0; nop.i 0; nop.i 0;; } - { .mii; (p48) mov r49 =3D r0; nop.i 0; nop.i 0;; } - { .mii; (p49) mov r50 =3D r0; nop.i 0; nop.i 0;; } - { .mii; (p50) mov r51 =3D r0; nop.i 0; nop.i 0;; } - { .mii; (p51) mov r52 =3D r0; nop.i 0; nop.i 0;; } - { .mii; (p52) mov r53 =3D r0; nop.i 0; nop.i 0;; } - { .mii; (p53) mov r54 =3D r0; nop.i 0; nop.i 0;; } - { .mii; (p54) mov r55 =3D r0; nop.i 0; nop.i 0;; } - { .mii; (p55) mov r56 =3D r0; nop.i 0; nop.i 0;; } - { .mii; (p56) mov r57 =3D r0; nop.i 0; nop.i 0;; } - { .mii; (p57) mov r58 =3D r0; nop.i 0; nop.i 0;; } - { .mii; (p58) mov r59 =3D r0; nop.i 0; nop.i 0;; } - { .mii; (p59) mov r60 =3D r0; nop.i 0; nop.i 0;; } - { .mii; (p60) mov r61 =3D r0; nop.i 0; nop.i 0;; } - { .mii; (p61) mov r62 =3D r0; nop.i 0; nop.i 0;; } - { .mii; (p62) mov r63 =3D r0; nop.i 0; nop.i 0;; } - { .mii; (p63) mov r64 =3D r0; nop.i 0; nop.i 0;; } - -// Predicates as a unit - { .mmi; nop.m 0; mov r1 =3D pr ;; } -// mov r2 =3D pr.rot - -// Branch registers. - { .mmi; mov b0 =3D r0;; } - { .mmi; mov b1 =3D r0;; } - { .mmi; mov b2 =3D r0;; } - { .mmi; mov b3 =3D r0;; } - { .mmi; mov b4 =3D r0;; } - { .mmi; mov b5 =3D r0;; } - { .mmi; mov b6 =3D r0;; } - { .mmi; mov b7 =3D r0;; } - - { .mmi; mov rp =3D r0;; } - -// Application registers - { .mmi; nop.m 0; mov r1 =3D ar0 ;; } - { .mmi; nop.m 0; mov r1 =3D ar1 ;; } - { .mmi; nop.m 0; mov r1 =3D ar2 ;; } - { .mmi; nop.m 0; mov r1 =3D ar3 ;; } - { .mmi; nop.m 0; mov r1 =3D ar4 ;; } - { .mmi; nop.m 0; mov r1 =3D ar5 ;; } - { .mmi; nop.m 0; mov r1 =3D ar6 ;; } - { .mmi; nop.m 0; mov r1 =3D ar7 ;; } -// { .mmi; nop.m 0; mov r1 =3D ar8 ;; } // reserved -// { .mmi; nop.m 0; mov r1 =3D ar9 ;; } // reserved -// { .mmi; nop.m 0; mov r1 =3D ar10 ;; } // reserved -// { .mmi; nop.m 0; mov r1 =3D ar11 ;; } // reserved -// { .mmi; nop.m 0; mov r1 =3D ar12 ;; } // reserved -// { .mmi; nop.m 0; mov r1 =3D ar13 ;; } // reserved -// { .mmi; nop.m 0; mov r1 =3D ar14 ;; } // reserved -// { .mmi; nop.m 0; mov r1 =3D ar15 ;; } // reserved - { .mmi; nop.m 0; mov r1 =3D ar16 ;; } - { .mmi; nop.m 0; mov r1 =3D ar17 ;; } - { .mmi; nop.m 0; mov r1 =3D ar18 ;; } - { .mmi; nop.m 0; mov r1 =3D ar19 ;; } -// { .mmi; nop.m 0; mov r1 =3D ar20 ;; } // reserved - { .mmi; nop.m 0; mov r1 =3D ar21 ;; } -// { .mmi; nop.m 0; mov r1 =3D ar22 ;; } // reserved -// { .mmi; nop.m 0; mov r1 =3D ar23 ;; } // reserved - { .mmi; nop.m 0; mov r1 =3D ar24 ;; } - { .mmi; nop.m 0; mov r1 =3D ar25 ;; } - { .mmi; nop.m 0; mov r1 =3D ar26 ;; } - { .mmi; nop.m 0; mov r1 =3D ar27 ;; } - { .mmi; nop.m 0; mov r1 =3D ar28 ;; } - { .mmi; nop.m 0; mov r1 =3D ar29 ;; } - { .mmi; nop.m 0; mov r1 =3D ar30 ;; } -// { .mmi; nop.m 0; mov r1 =3D ar31 ;; } // reserved - { .mmi; nop.m 0; mov r1 =3D ar32 ;; } -// { .mmi; nop.m 0; mov r1 =3D ar33 ;; } // reserved -// { .mmi; nop.m 0; mov r1 =3D ar34 ;; } // reserved -// { .mmi; nop.m 0; mov r1 =3D ar35 ;; } // reserved - { .mmi; nop.m 0; mov r1 =3D ar36 ;; } -// { .mmi; nop.m 0; mov r1 =3D ar37 ;; } // reserved -// { .mmi; nop.m 0; mov r1 =3D ar38 ;; } // reserved -// { .mmi; nop.m 0; mov r1 =3D ar39 ;; } // reserved - { .mmi; nop.m 0; mov r1 =3D ar40 ;; } -// { .mmi; nop.m 0; mov r1 =3D ar41 ;; } // reserved -// { .mmi; nop.m 0; mov r1 =3D ar42 ;; } // reserved -// { .mmi; nop.m 0; mov r1 =3D ar43 ;; } // reserved - { .mmi; nop.m 0; mov r1 =3D ar44 ;; } - { .mmi; nop.m 0; mov r1 =3D ar45 ;; } -// { .mmi; nop.m 0; mov r1 =3D ar46 ;; } // reserved -// { .mmi; nop.m 0; mov r1 =3D ar47 ;; } // reserved - { .mmi; nop.m 0; mov r1 =3D ar48 ;; } - { .mmi; nop.m 0; mov r1 =3D ar49 ;; } - { .mmi; nop.m 0; mov r1 =3D ar50 ;; } - { .mmi; nop.m 0; mov r1 =3D ar51 ;; } - { .mmi; nop.m 0; mov r1 =3D ar52 ;; } - { .mmi; nop.m 0; mov r1 =3D ar53 ;; } - { .mmi; nop.m 0; mov r1 =3D ar54 ;; } - { .mmi; nop.m 0; mov r1 =3D ar55 ;; } - { .mmi; nop.m 0; mov r1 =3D ar56 ;; } - { .mmi; nop.m 0; mov r1 =3D ar57 ;; } - { .mmi; nop.m 0; mov r1 =3D ar58 ;; } - { .mmi; nop.m 0; mov r1 =3D ar59 ;; } - { .mmi; nop.m 0; mov r1 =3D ar60 ;; } - { .mmi; nop.m 0; mov r1 =3D ar61 ;; } - { .mmi; nop.m 0; mov r1 =3D ar62 ;; } - { .mmi; nop.m 0; mov r1 =3D ar63 ;; } - { .mmi; nop.m 0; mov r1 =3D ar64 ;; } - { .mmi; nop.m 0; mov r1 =3D ar65 ;; } - { .mmi; nop.m 0; mov r1 =3D ar66 ;; } -// { .mmi; nop.m 0; mov r1 =3D ar67 ;; } // reserved -// { .mmi; nop.m 0; mov r1 =3D ar68 ;; } // reserved -// { .mmi; nop.m 0; mov r1 =3D ar69 ;; } // reserved -// { .mmi; nop.m 0; mov r1 =3D ar70 ;; } // reserved -// { .mmi; nop.m 0; mov r1 =3D ar71 ;; } // reserved -// { .mmi; nop.m 0; mov r1 =3D ar72 ;; } // reserved -// { .mmi; nop.m 0; mov r1 =3D ar73 ;; } // reserved -// { .mmi; nop.m 0; mov r1 =3D ar74 ;; } // reserved -// { .mmi; nop.m 0; mov r1 =3D ar75 ;; } // reserved -// { .mmi; nop.m 0; mov r1 =3D ar76 ;; } // reserved -// { .mmi; nop.m 0; mov r1 =3D ar77 ;; } // reserved -// { .mmi; nop.m 0; mov r1 =3D ar78 ;; } // reserved -// { .mmi; nop.m 0; mov r1 =3D ar79 ;; } // reserved -// { .mmi; nop.m 0; mov r1 =3D ar80 ;; } // reserved -// { .mmi; nop.m 0; mov r1 =3D ar81 ;; } // reserved -// { .mmi; nop.m 0; mov r1 =3D ar82 ;; } // reserved -// { .mmi; nop.m 0; mov r1 =3D ar83 ;; } // reserved -// { .mmi; nop.m 0; mov r1 =3D ar84 ;; } // reserved -// { .mmi; nop.m 0; mov r1 =3D ar85 ;; } // reserved -// { .mmi; nop.m 0; mov r1 =3D ar86 ;; } // reserved -// { .mmi; nop.m 0; mov r1 =3D ar87 ;; } // reserved -// { .mmi; nop.m 0; mov r1 =3D ar88 ;; } // reserved -// { .mmi; nop.m 0; mov r1 =3D ar89 ;; } // reserved -// { .mmi; nop.m 0; mov r1 =3D ar90 ;; } // reserved -// { .mmi; nop.m 0; mov r1 =3D ar91 ;; } // reserved -// { .mmi; nop.m 0; mov r1 =3D ar92 ;; } // reserved -// { .mmi; nop.m 0; mov r1 =3D ar93 ;; } // reserved -// { .mmi; nop.m 0; mov r1 =3D ar94 ;; } // reserved -// { .mmi; nop.m 0; mov r1 =3D ar95 ;; } // reserved -// { .mmi; nop.m 0; mov r1 =3D ar96 ;; } // reserved -// { .mmi; nop.m 0; mov r1 =3D ar97 ;; } // reserved -// { .mmi; nop.m 0; mov r1 =3D ar98 ;; } // reserved -// { .mmi; nop.m 0; mov r1 =3D ar99 ;; } // reserved -// { .mmi; nop.m 0; mov r1 =3D ar100 ;; } // reserved -// { .mmi; nop.m 0; mov r1 =3D ar101 ;; } // reserved -// { .mmi; nop.m 0; mov r1 =3D ar102 ;; } // reserved -// { .mmi; nop.m 0; mov r1 =3D ar103 ;; } // reserved -// { .mmi; nop.m 0; mov r1 =3D ar104 ;; } // reserved -// { .mmi; nop.m 0; mov r1 =3D ar105 ;; } // reserved -// { .mmi; nop.m 0; mov r1 =3D ar106 ;; } // reserved -// { .mmi; nop.m 0; mov r1 =3D ar107 ;; } // reserved -// { .mmi; nop.m 0; mov r1 =3D ar108 ;; } // reserved -// { .mmi; nop.m 0; mov r1 =3D ar109 ;; } // reserved -// { .mmi; nop.m 0; mov r1 =3D ar110 ;; } // reserved -// { .mmi; nop.m 0; mov r1 =3D ar111 ;; } // reserved - { .mmi; nop.m 0; mov r1 =3D ar112 ;; } - { .mmi; nop.m 0; mov r1 =3D ar113 ;; } - { .mmi; nop.m 0; mov r1 =3D ar114 ;; } - { .mmi; nop.m 0; mov r1 =3D ar115 ;; } - { .mmi; nop.m 0; mov r1 =3D ar116 ;; } - { .mmi; nop.m 0; mov r1 =3D ar117 ;; } - { .mmi; nop.m 0; mov r1 =3D ar118 ;; } - { .mmi; nop.m 0; mov r1 =3D ar119 ;; } - { .mmi; nop.m 0; mov r1 =3D ar120 ;; } - { .mmi; nop.m 0; mov r1 =3D ar121 ;; } - { .mmi; nop.m 0; mov r1 =3D ar122 ;; } - { .mmi; nop.m 0; mov r1 =3D ar123 ;; } - { .mmi; nop.m 0; mov r1 =3D ar124 ;; } - { .mmi; nop.m 0; mov r1 =3D ar125 ;; } - { .mmi; nop.m 0; mov r1 =3D ar126 ;; } - { .mmi; nop.m 0; mov r1 =3D ar127 ;; } - -// Application registers by name - { .mmi; nop.m 0; mov r1 =3D ar.k0 ;;} - { .mmi; nop.m 0; mov r1 =3D ar.k1 ;;} - { .mmi; nop.m 0; mov r1 =3D ar.k2 ;;} - { .mmi; nop.m 0; mov r1 =3D ar.k3 ;;} - { .mmi; nop.m 0; mov r1 =3D ar.k4 ;;} - { .mmi; nop.m 0; mov r1 =3D ar.k5 ;;} - { .mmi; nop.m 0; mov r1 =3D ar.k6 ;;} - { .mmi; nop.m 0; mov r1 =3D ar.k7 ;;} - { .mmi; nop.m 0; mov r1 =3D ar.rsc ;; } - { .mmi; nop.m 0; mov r1 =3D ar.bsp ;; } - { .mmi; nop.m 0; mov r1 =3D ar.bspstore ;; } - { .mmi; nop.m 0; mov r1 =3D ar.rnat ;; } - { .mmi; nop.m 0; mov r1 =3D ar.ccv ;; } - { .mmi; nop.m 0; mov r1 =3D ar.unat ;; } - { .mmi; nop.m 0; mov r1 =3D ar.fpsr ;; } - { .mmi; nop.m 0; mov r1 =3D ar.itc ;; } - { .mmi; nop.m 0; mov r1 =3D ar.ruc ;; } - { .mmi; nop.m 0; mov r1 =3D ar.pfs ;; } - { .mmi; nop.m 0; mov r1 =3D ar.lc ;; } - { .mmi; nop.m 0; mov r1 =3D ar.ec ;; } - -// Control registers - { .mfb; mov r1 =3D cr0 ;; } - { .mfb; mov r1 =3D cr1 ;; } - { .mfb; mov r1 =3D cr2 ;; } -// { .mfb; mov r1 =3D cr3 ;; } // reserved -// { .mfb; mov r1 =3D cr4 ;; } // reserved -// { .mfb; mov r1 =3D cr5 ;; } // reserved -// { .mfb; mov r1 =3D cr6 ;; } // reserved -// { .mfb; mov r1 =3D cr7 ;; } // reserved - { .mfb; mov r1 =3D cr8 ;; } - { .mfb; mov r1 =3D cr9 ;; } -// { .mfb; mov r1 =3D cr10 ;; } // reserved -// { .mfb; mov r1 =3D cr11 ;; } // reserved -// { .mfb; mov r1 =3D cr12 ;; } // reserved -// { .mfb; mov r1 =3D cr13 ;; } // reserved -// { .mfb; mov r1 =3D cr14 ;; } // reserved -// { .mfb; mov r1 =3D cr15 ;; } // reserved - { .mfb; mov r1 =3D cr16 ;; } - { .mfb; mov r1 =3D cr17 ;; } -// { .mfb; mov r1 =3D cr18 ;; } // reserved - { .mfb; mov r1 =3D cr19 ;; } - { .mfb; mov r1 =3D cr20 ;; } - { .mfb; mov r1 =3D cr21 ;; } - { .mfb; mov r1 =3D cr22 ;; } - { .mfb; mov r1 =3D cr23 ;; } - { .mfb; mov r1 =3D cr24 ;; } - { .mfb; mov r1 =3D cr25 ;; } -// { .mfb; mov r1 =3D cr26 ;; } // reserved -// { .mfb; mov r1 =3D cr27 ;; } // reserved -// { .mfb; mov r1 =3D cr28 ;; } // reserved -// { .mfb; mov r1 =3D cr29 ;; } // reserved -// { .mfb; mov r1 =3D cr30 ;; } // reserved -// { .mfb; mov r1 =3D cr31 ;; } // reserved -// { .mfb; mov r1 =3D cr32 ;; } // reserved -// { .mfb; mov r1 =3D cr33 ;; } // reserved -// { .mfb; mov r1 =3D cr34 ;; } // reserved -// { .mfb; mov r1 =3D cr35 ;; } // reserved -// { .mfb; mov r1 =3D cr36 ;; } // reserved -// { .mfb; mov r1 =3D cr37 ;; } // reserved -// { .mfb; mov r1 =3D cr38 ;; } // reserved -// { .mfb; mov r1 =3D cr39 ;; } // reserved -// { .mfb; mov r1 =3D cr40 ;; } // reserved -// { .mfb; mov r1 =3D cr41 ;; } // reserved -// { .mfb; mov r1 =3D cr42 ;; } // reserved -// { .mfb; mov r1 =3D cr43 ;; } // reserved -// { .mfb; mov r1 =3D cr44 ;; } // reserved -// { .mfb; mov r1 =3D cr45 ;; } // reserved -// { .mfb; mov r1 =3D cr46 ;; } // reserved -// { .mfb; mov r1 =3D cr47 ;; } // reserved -// { .mfb; mov r1 =3D cr48 ;; } // reserved -// { .mfb; mov r1 =3D cr49 ;; } // reserved -// { .mfb; mov r1 =3D cr50 ;; } // reserved -// { .mfb; mov r1 =3D cr51 ;; } // reserved -// { .mfb; mov r1 =3D cr52 ;; } // reserved -// { .mfb; mov r1 =3D cr53 ;; } // reserved -// { .mfb; mov r1 =3D cr54 ;; } // reserved -// { .mfb; mov r1 =3D cr55 ;; } // reserved -// { .mfb; mov r1 =3D cr56 ;; } // reserved -// { .mfb; mov r1 =3D cr57 ;; } // reserved -// { .mfb; mov r1 =3D cr58 ;; } // reserved -// { .mfb; mov r1 =3D cr59 ;; } // reserved -// { .mfb; mov r1 =3D cr60 ;; } // reserved -// { .mfb; mov r1 =3D cr61 ;; } // reserved -// { .mfb; mov r1 =3D cr62 ;; } // reserved -// { .mfb; mov r1 =3D cr63 ;; } // reserved - { .mfb; mov r1 =3D cr64 ;; } - { .mfb; mov r1 =3D cr65 ;; } - { .mfb; mov r1 =3D cr66 ;; } - { .mfb; mov r1 =3D cr67 ;; } - { .mfb; mov r1 =3D cr68 ;; } - { .mfb; mov r1 =3D cr69 ;; } - { .mfb; mov r1 =3D cr70 ;; } - { .mfb; mov r1 =3D cr71 ;; } - { .mfb; mov r1 =3D cr72 ;; } - { .mfb; mov r1 =3D cr73 ;; } - { .mfb; mov r1 =3D cr74 ;; } -// { .mfb; mov r1 =3D cr75 ;; } // reserved -// { .mfb; mov r1 =3D cr76 ;; } // reserved -// { .mfb; mov r1 =3D cr77 ;; } // reserved -// { .mfb; mov r1 =3D cr78 ;; } // reserved -// { .mfb; mov r1 =3D cr79 ;; } // reserved - { .mfb; mov r1 =3D cr80 ;; } - { .mfb; mov r1 =3D cr81 ;; } -// { .mfb; mov r1 =3D cr82 ;; } // reserved -// { .mfb; mov r1 =3D cr83 ;; } // reserved -// { .mfb; mov r1 =3D cr84 ;; } // reserved -// { .mfb; mov r1 =3D cr85 ;; } // reserved -// { .mfb; mov r1 =3D cr86 ;; } // reserved -// { .mfb; mov r1 =3D cr87 ;; } // reserved -// { .mfb; mov r1 =3D cr88 ;; } // reserved -// { .mfb; mov r1 =3D cr89 ;; } // reserved -// { .mfb; mov r1 =3D cr90 ;; } // reserved -// { .mfb; mov r1 =3D cr91 ;; } // reserved -// { .mfb; mov r1 =3D cr92 ;; } // reserved -// { .mfb; mov r1 =3D cr93 ;; } // reserved -// { .mfb; mov r1 =3D cr94 ;; } // reserved -// { .mfb; mov r1 =3D cr95 ;; } // reserved -// { .mfb; mov r1 =3D cr96 ;; } // reserved -// { .mfb; mov r1 =3D cr97 ;; } // reserved -// { .mfb; mov r1 =3D cr98 ;; } // reserved -// { .mfb; mov r1 =3D cr99 ;; } // reserved -// { .mfb; mov r1 =3D cr100 ;; } // reserved -// { .mfb; mov r1 =3D cr101 ;; } // reserved -// { .mfb; mov r1 =3D cr102 ;; } // reserved -// { .mfb; mov r1 =3D cr103 ;; } // reserved -// { .mfb; mov r1 =3D cr104 ;; } // reserved -// { .mfb; mov r1 =3D cr105 ;; } // reserved -// { .mfb; mov r1 =3D cr106 ;; } // reserved -// { .mfb; mov r1 =3D cr107 ;; } // reserved -// { .mfb; mov r1 =3D cr108 ;; } // reserved -// { .mfb; mov r1 =3D cr109 ;; } // reserved -// { .mfb; mov r1 =3D cr110 ;; } // reserved -// { .mfb; mov r1 =3D cr111 ;; } // reserved -// { .mfb; mov r1 =3D cr112 ;; } // reserved -// { .mfb; mov r1 =3D cr113 ;; } // reserved -// { .mfb; mov r1 =3D cr114 ;; } // reserved -// { .mfb; mov r1 =3D cr115 ;; } // reserved -// { .mfb; mov r1 =3D cr116 ;; } // reserved -// { .mfb; mov r1 =3D cr117 ;; } // reserved -// { .mfb; mov r1 =3D cr118 ;; } // reserved -// { .mfb; mov r1 =3D cr119 ;; } // reserved -// { .mfb; mov r1 =3D cr120 ;; } // reserved -// { .mfb; mov r1 =3D cr121 ;; } // reserved -// { .mfb; mov r1 =3D cr122 ;; } // reserved -// { .mfb; mov r1 =3D cr123 ;; } // reserved -// { .mfb; mov r1 =3D cr124 ;; } // reserved -// { .mfb; mov r1 =3D cr125 ;; } // reserved -// { .mfb; mov r1 =3D cr126 ;; } // reserved -// { .mfb; mov r1 =3D cr127 ;; } // reserved - -// Control registers by name - { .mfb; mov r1 =3D cr.dcr ;; } - { .mfb; mov r1 =3D cr.itm ;; } - { .mfb; mov r1 =3D cr.iva ;; } - { .mfb; mov r1 =3D cr.pta ;; } - { .mfb; mov r1 =3D cr.ipsr ;; } - { .mfb; mov r1 =3D cr.isr ;; } - { .mfb; mov r1 =3D cr.iip ;; } - { .mfb; mov r1 =3D cr.iipa ;; } - { .mfb; mov r1 =3D cr.ifs ;; } - { .mfb; mov r1 =3D cr.iim ;; } - { .mfb; mov r1 =3D cr.iha ;; } - { .mfb; mov r1 =3D cr.iib0 ;; } - { .mfb; mov r1 =3D cr.iib1 ;; } - { .mfb; mov r1 =3D cr.lid ;; } - { .mfb; mov r1 =3D cr.ivr ;; } - { .mfb; mov r1 =3D cr.tpr ;; } - { .mfb; mov r1 =3D cr.eoi ;; } - { .mfb; mov r1 =3D cr.irr0 ;; } - { .mfb; mov r1 =3D cr.irr1 ;; } - { .mfb; mov r1 =3D cr.irr2 ;; } - { .mfb; mov r1 =3D cr.irr3 ;; } - { .mfb; mov r1 =3D cr.itv ;; } - { .mfb; mov r1 =3D cr.pmv ;; } - { .mfb; mov r1 =3D cr.lrr0 ;; } - { .mfb; mov r1 =3D cr.lrr1 ;; } - { .mfb; mov r1 =3D cr.cmcv ;; } - -// Other registers - { .mfb; mov r1 =3D psr ;; } -// { .mfb; mov r1 =3D psr.l ;; } - { .mfb; mov r1 =3D psr.um ;; } - { .mmi; mov r1 =3D ip ;; } - -// Indirect register files - { .mmi - mov r1 =3D pmc[r3] - mov r2 =3D pmc[r4] - nop.i 0;; } - { .mmi - mov r1 =3D pmd[r3] - mov r2 =3D pmd[r4] - nop.i 0;; } - { .mmi - mov r1 =3D pkr[r3] - mov r2 =3D pkr[r4] - nop.i 0;; } - { .mmi - mov r1 =3D rr[r3] - mov r2 =3D rr[r4] - nop.i 0;; } - { .mmi - mov r1 =3D ibr[r3] - mov r2 =3D ibr[r4] - nop.i 0;; } - { .mmi - mov r1 =3D dbr[r3] - mov r2 =3D dbr[r4] - nop.i 0;; } - { .mmi - mov r1 =3D CPUID[r3] - mov r2 =3D CPUID[r4] - nop.i 0;; } - { .mmi - mov r1 =3D cpuid[r3] - mov r2 =3D cpuid[r4] - nop.i 0;; } diff --git a/gas/testsuite/gas/ia64/regval.l b/gas/testsuite/gas/ia64/regva= l.l deleted file mode 100644 index b12a266227f..00000000000 --- a/gas/testsuite/gas/ia64/regval.l +++ /dev/null @@ -1,17 +0,0 @@ -.*: Assembler messages: -.*:11: Warning: Use of 'mov' .* WAW dependency 'RR#' \(impliedf\), specifi= c resource number is 0 -.*:11: Warning: Only the first path encountering the conflict is reported -.*:10: Warning: This is the location of the conflicting usage -#... -.*:25: Warning: Use of 'mov' .* WAW dependency 'RR#' \(impliedf\), specifi= c resource number is 0 -.*:25: Warning: Only the first path encountering the conflict is reported -.*:24: Warning: This is the location of the conflicting usage -#... -.*:32: Warning: Use of 'mov' .* WAW dependency 'RR#' \(impliedf\) -.*:32: Warning: Only the first path encountering the conflict is reported -.*:31: Warning: This is the location of the conflicting usage -#... -.*:46: Warning: Use of 'mov' .* WAW dependency 'RR#' \(impliedf\), specifi= c resource number is 0 -.*:46: Warning: Only the first path encountering the conflict is reported -.*:45: Warning: This is the location of the conflicting usage -#pass diff --git a/gas/testsuite/gas/ia64/regval.s b/gas/testsuite/gas/ia64/regva= l.s deleted file mode 100644 index 3fb033017de..00000000000 --- a/gas/testsuite/gas/ia64/regval.s +++ /dev/null @@ -1,48 +0,0 @@ -.explicit -rr1: - .reg.val r1, 0xE000000000000000 - mov rr[r0] =3D r0 - mov rr[r1] =3D r0 - br.ret.sptk rp - ;; -rr2: - .reg.val r1, 0 - mov rr[r0] =3D r0 - mov rr[r1] =3D r0 - br.ret.sptk rp - ;; -rr3: - movl r1 =3D 0xE000000000000000 - ;; - mov rr[r0] =3D r0 - mov rr[r1] =3D r0 - br.ret.sptk rp - ;; -rr4: - mov r1 =3D 0 - ;; - mov rr[r0] =3D r0 - mov rr[r1] =3D r0 - br.ret.sptk rp - ;; -rr5: - movl r1 =3D xyz+0xE000000000000000 - ;; - mov rr[r0] =3D r0 - mov rr[r1] =3D r0 - br.ret.sptk rp - ;; -rr6: - dep.z r1 =3D 1, 61, 3 - ;; - mov rr[r0] =3D r0 - mov rr[r1] =3D r0 - br.ret.sptk rp - ;; -rr7: - dep.z r1 =3D -1, 0, 61 - ;; - mov rr[r0] =3D r0 - mov rr[r1] =3D r0 - br.ret.sptk rp - ;; diff --git a/gas/testsuite/gas/ia64/reloc-bad.l b/gas/testsuite/gas/ia64/re= loc-bad.l deleted file mode 100644 index 5a2df9a73bb..00000000000 --- a/gas/testsuite/gas/ia64/reloc-bad.l +++ /dev/null @@ -1,43 +0,0 @@ -.*: Assembler messages: -.*:[[:digit:]]+: (Error|Warning): .* GPREL14 .* -.*:[[:digit:]]+: (Error|Warning): .* LTOFF14 .* -.*:[[:digit:]]+: (Error|Warning): .* LTOFF32[LM]SB .* -.*:[[:digit:]]+: (Error|Warning): .* LTOFF64[LM]SB .* -.*:[[:digit:]]+: (Error|Warning): .* PLTOFF14 .* -.*:[[:digit:]]+: (Error|Warning): .* PLTOFF32[LM]SB .* -.*:[[:digit:]]+: (Error|Warning): .* FPTR14 .* -.*:[[:digit:]]+: (Error|Warning): .* FPTR22 .* -.*:[[:digit:]]+: (Error|Warning): .* PCREL14 .* -.*:[[:digit:]]+: (Error|Warning): .* LTOFF_FPTR14 .* -.*:[[:digit:]]+: (Error|Warning): .* SEGREL14 .* -.*:[[:digit:]]+: (Error|Warning): .* SEGREL22 .* -.*:[[:digit:]]+: (Error|Warning): .* SEGREL64I .* -.*:[[:digit:]]+: (Error|Warning): .* SECREL14 .* -.*:[[:digit:]]+: (Error|Warning): .* SECREL22 .* -.*:[[:digit:]]+: (Error|Warning): .* SECREL64I .* -.*:[[:digit:]]+: (Error|Warning): .* LTV14 .* -.*:[[:digit:]]+: (Error|Warning): .* LTV22 .* -.*:[[:digit:]]+: (Error|Warning): .* LTV64I .* -.*:[[:digit:]]+: (Error|Warning): .* IPLT14 .* -.*:[[:digit:]]+: (Error|Warning): .* IPLT22 .* -.*:[[:digit:]]+: (Error|Warning): .* IPLT64I .* -.*:[[:digit:]]+: (Error|Warning): .* IPLT32[LM]SB .* -.*:[[:digit:]]+: (Error|Warning): .* IPLT64[LM]SB .* -.*:[[:digit:]]+: (Error|Warning): .* LTOFF14X .* -.*:[[:digit:]]+: (Error|Warning): .* TPREL32[LM]SB .* -.*:[[:digit:]]+: (Error|Warning): .* LTOFF_TPREL14 .* -.*:[[:digit:]]+: (Error|Warning): .* LTOFF_TPREL64I .* -.*:[[:digit:]]+: (Error|Warning): .* LTOFF_TPREL32[LM]SB .* -.*:[[:digit:]]+: (Error|Warning): .* LTOFF_TPREL64[LM]SB .* -.*:[[:digit:]]+: (Error|Warning): .* DTPMOD14 .* -.*:[[:digit:]]+: (Error|Warning): .* DTPMOD22 .* -.*:[[:digit:]]+: (Error|Warning): .* DTPMOD64I .* -.*:[[:digit:]]+: (Error|Warning): .* DTPMOD32[LM]SB .* -.*:[[:digit:]]+: (Error|Warning): .* LTOFF_DTPMOD14 .* -.*:[[:digit:]]+: (Error|Warning): .* LTOFF_DTPMOD64I .* -.*:[[:digit:]]+: (Error|Warning): .* LTOFF_TPREL32[LM]SB .* -.*:[[:digit:]]+: (Error|Warning): .* LTOFF_TPREL64[LM]SB .* -.*:[[:digit:]]+: (Error|Warning): .* LTOFF_DTPREL14 .* -.*:[[:digit:]]+: (Error|Warning): .* LTOFF_DTPREL64I .* -.*:[[:digit:]]+: (Error|Warning): .* LTOFF_DTPREL32[LM]SB .* -.*:[[:digit:]]+: (Error|Warning): .* LTOFF_DTPREL64[LM]SB .* diff --git a/gas/testsuite/gas/ia64/reloc-bad.s b/gas/testsuite/gas/ia64/re= loc-bad.s deleted file mode 100644 index 488a0d98637..00000000000 --- a/gas/testsuite/gas/ia64/reloc-bad.s +++ /dev/null @@ -1,62 +0,0 @@ - .psr abi64 - .global esym - .section .rodata, "a", @progbits - .text -_start: - adds r1 =3D @gprel(esym), r0 - - adds r1 =3D @ltoff(esym), r0 - .xdata4 .rodata, @ltoff(esym) - .xdata8 .rodata, @ltoff(esym) - - adds r1 =3D @pltoff(esym), r0 - .xdata4 .rodata, @pltoff(esym) - - adds r1 =3D @fptr(esym), r0 - mov r2 =3D @fptr(esym) - - adds r1 =3D @pcrel(esym), r0 - - adds r1 =3D @ltoff(@fptr(esym)), r0 - - adds r1 =3D @segrel(esym), r0 - mov r2 =3D @segrel(esym) - movl r3 =3D @segrel(esym) - - adds r1 =3D @secrel(esym), r0 - mov r2 =3D @secrel(esym) - movl r3 =3D @secrel(esym) - - adds r1 =3D @ltv(esym), r0 - mov r2 =3D @ltv(esym) - movl r3 =3D @ltv(esym) - - adds r1 =3D @iplt(esym), r0 - mov r2 =3D @iplt(esym) - movl r3 =3D @iplt(esym) - .xdata4 .rodata, @iplt(esym) - .xdata8 .rodata, @iplt(esym) - - adds r1 =3D @ltoffx(esym), r0 - - .xdata4 .rodata, @tprel(esym) - - adds r1 =3D @ltoff(@tprel(esym)), r0 - movl r3 =3D @ltoff(@tprel(esym)) - .xdata4 .rodata, @ltoff(@tprel(esym)) - .xdata8 .rodata, @ltoff(@tprel(esym)) - - adds r1 =3D @dtpmod(esym), r0 - mov r2 =3D @dtpmod(esym) - movl r3 =3D @dtpmod(esym) - .xdata4 .rodata, @dtpmod(esym) - - adds r1 =3D @ltoff(@dtpmod(esym)), r0 - movl r3 =3D @ltoff(@dtpmod(esym)) - .xdata4 .rodata, @ltoff(@tprel(esym)) - .xdata8 .rodata, @ltoff(@tprel(esym)) - - adds r1 =3D @ltoff(@dtprel(esym)), r0 - movl r3 =3D @ltoff(@dtprel(esym)) - .xdata4 .rodata, @ltoff(@dtprel(esym)) - .xdata8 .rodata, @ltoff(@dtprel(esym)) diff --git a/gas/testsuite/gas/ia64/reloc-mlx.d b/gas/testsuite/gas/ia64/re= loc-mlx.d deleted file mode 100644 index 1583872481d..00000000000 --- a/gas/testsuite/gas/ia64/reloc-mlx.d +++ /dev/null @@ -1,8 +0,0 @@ -#objdump: -r -#name: ia64 mlx reloc - -.*: +file format .* - -RELOCATION RECORDS FOR \[\.text\]: -OFFSET[[:space:]]+TYPE[[:space:]]+VALUE[[:space:]]* -0+[12][[:space:]]+PCREL60B[[:space:]]+bar diff --git a/gas/testsuite/gas/ia64/reloc-mlx.s b/gas/testsuite/gas/ia64/re= loc-mlx.s deleted file mode 100644 index 1cab555bee8..00000000000 --- a/gas/testsuite/gas/ia64/reloc-mlx.s +++ /dev/null @@ -1,7 +0,0 @@ - .text - .proc foo# -foo: - .mlx - mov r25 =3D r0 - brl.call.sptk.many b0 =3D bar# - .endp foo# diff --git a/gas/testsuite/gas/ia64/reloc-uw-ilp32.d b/gas/testsuite/gas/ia= 64/reloc-uw-ilp32.d deleted file mode 100644 index b59eb40fd7b..00000000000 --- a/gas/testsuite/gas/ia64/reloc-uw-ilp32.d +++ /dev/null @@ -1,15 +0,0 @@ -#objdump: -r -#name: ia64 unwind relocations (ilp32) -#as: -milp32 -#source: reloc-uw.s - -.*: +file format .* - -RELOCATION RECORDS FOR \[\.IA_64\.unwind\]: -OFFSET[[:space:]]+TYPE[[:space:]]+VALUE[[:space:]]* -0*00 SEGREL32[ML]SB[[:space:]]+\.text(\+0x[[:xdigit:]]*0)? -0*04 SEGREL32[ML]SB[[:space:]]+\.text(\+0x[[:xdigit:]]*0)? -0*08 SEGREL32[ML]SB[[:space:]]+\.IA_64\.unwind_info(\+0x[[:xdigit:]]*[048c= ])? -0*0c SEGREL32[ML]SB[[:space:]]+\.text(\+0x[[:xdigit:]]*0)? -0*10 SEGREL32[ML]SB[[:space:]]+\.text(\+0x[[:xdigit:]]*0)? -0*14 SEGREL32[ML]SB[[:space:]]+\.IA_64\.unwind_info(\+0x[[:xdigit:]]*[048c= ])? diff --git a/gas/testsuite/gas/ia64/reloc-uw.d b/gas/testsuite/gas/ia64/rel= oc-uw.d deleted file mode 100644 index e7af6f1b88b..00000000000 --- a/gas/testsuite/gas/ia64/reloc-uw.d +++ /dev/null @@ -1,13 +0,0 @@ -# objdump: -r -# name: ia64 unwind relocations - -.*: +file format .* - -RELOCATION RECORDS FOR \[\.IA_64\.unwind\]: -OFFSET[[:space:]]+TYPE[[:space:]]+VALUE[[:space:]]* -0*00 SEGREL64[ML]SB[[:space:]]+\.text(\+0x[[:xdigit:]]*0)? -0*08 SEGREL64[ML]SB[[:space:]]+\.text(\+0x[[:xdigit:]]*0)? -0*10 SEGREL64[ML]SB[[:space:]]+\.IA_64\.unwind_info(\+0x[[:xdigit:]]*[08])? -0*18 SEGREL64[ML]SB[[:space:]]+\.text(\+0x[[:xdigit:]]*0)? -0*20 SEGREL64[ML]SB[[:space:]]+\.text(\+0x[[:xdigit:]]*0)? -0*28 SEGREL64[ML]SB[[:space:]]+\.IA_64\.unwind_info(\+0x[[:xdigit:]]*[08])? diff --git a/gas/testsuite/gas/ia64/reloc-uw.s b/gas/testsuite/gas/ia64/rel= oc-uw.s deleted file mode 100644 index 1cda453f522..00000000000 --- a/gas/testsuite/gas/ia64/reloc-uw.s +++ /dev/null @@ -1,13 +0,0 @@ - .text - - .macro uw, type - .proc uw\type - .\type uw\type -uw\type: - .unwentry - br.ret.sptk rp - .endp uw\type - .endm - - uw global - uw weak diff --git a/gas/testsuite/gas/ia64/reloc.d b/gas/testsuite/gas/ia64/reloc.d deleted file mode 100644 index 467282dfe92..00000000000 --- a/gas/testsuite/gas/ia64/reloc.d +++ /dev/null @@ -1,64 +0,0 @@ -#objdump: -r -#name: ia64 relocations - -.*: +file format .* - -RELOCATION RECORDS FOR \[\.text\]: -OFFSET[[:space:]]+TYPE[[:space:]]+VALUE[[:space:]]* -[[:xdigit:]]+[012][[:space:]]+IMM14[[:space:]]+esym -[[:xdigit:]]+[012][[:space:]]+IMM22[[:space:]]+esym -[[:xdigit:]]+[012][[:space:]]+IMM64[[:space:]]+esym -[[:xdigit:]]+[012][[:space:]]+GPREL22[[:space:]]+esym -[[:xdigit:]]+[012][[:space:]]+GPREL64I[[:space:]]+esym -[[:xdigit:]]+[012][[:space:]]+LTOFF22[[:space:]]+esym -[[:xdigit:]]+[012][[:space:]]+LTOFF64I[[:space:]]+esym -[[:xdigit:]]+[012][[:space:]]+PLTOFF22[[:space:]]+esym -[[:xdigit:]]+[012][[:space:]]+PLTOFF64I[[:space:]]+esym -[[:xdigit:]]+[012][[:space:]]+FPTR64I[[:space:]]+esym -[[:xdigit:]]+[012][[:space:]]+PCREL60B[[:space:]]+esym -[[:xdigit:]]+[012][[:space:]]+PCREL21B[[:space:]]+esym -[[:xdigit:]]+[012][[:space:]]+PCREL21M[[:space:]]+esym -[[:xdigit:]]+[012][[:space:]]+PCREL21F[[:space:]]+esym -[[:xdigit:]]+[012][[:space:]]+LTOFF_FPTR22[[:space:]]+esym -[[:xdigit:]]+[012][[:space:]]+LTOFF_FPTR64I[[:space:]]+esym -[[:xdigit:]]+[012][[:space:]]+PCREL22[[:space:]]+esym -[[:xdigit:]]+[012][[:space:]]+PCREL64I[[:space:]]+esym -[[:xdigit:]]+[012][[:space:]]+LTOFF22X[[:space:]]+esym -[[:xdigit:]]+[012][[:space:]]+LDXMOV[[:space:]]+esym -[[:xdigit:]]+[012][[:space:]]+TPREL14[[:space:]]+esym -[[:xdigit:]]+[012][[:space:]]+TPREL22[[:space:]]+esym -[[:xdigit:]]+[012][[:space:]]+TPREL64I[[:space:]]+esym -[[:xdigit:]]+[012][[:space:]]+LTOFF_TPREL22[[:space:]]+esym -[[:xdigit:]]+[012][[:space:]]+LTOFF_DTPMOD22[[:space:]]+esym -[[:xdigit:]]+[012][[:space:]]+DTPREL14[[:space:]]+esym -[[:xdigit:]]+[012][[:space:]]+DTPREL22[[:space:]]+esym -[[:xdigit:]]+[012][[:space:]]+DTPREL64I[[:space:]]+esym -[[:xdigit:]]+[012][[:space:]]+LTOFF_DTPREL22[[:space:]]+esym - -RELOCATION RECORDS FOR \[\.rodata\.4\]: -OFFSET[[:space:]]+TYPE[[:space:]]+VALUE[[:space:]]* -[[:xdigit:]]+[048cC][[:space:]]+DIR32[LM]SB[[:space:]]+esym -[[:xdigit:]]+[048cC][[:space:]]+GPREL32[LM]SB[[:space:]]+esym -[[:xdigit:]]+[048cC][[:space:]]+FPTR32[LM]SB[[:space:]]+esym -[[:xdigit:]]+[048cC][[:space:]]+PCREL32[LM]SB[[:space:]]+esym -[[:xdigit:]]+[048cC][[:space:]]+LTOFF_FPTR32[LM]SB[[:space:]]+esym -[[:xdigit:]]+[048cC][[:space:]]+SEGREL32[LM]SB[[:space:]]+esym -[[:xdigit:]]+[048cC][[:space:]]+SECREL32[LM]SB[[:space:]]+esym -[[:xdigit:]]+[048cC][[:space:]]+LTV32[LM]SB[[:space:]]+esym -[[:xdigit:]]+[048cC][[:space:]]+DTPREL32[LM]SB[[:space:]]+esym - -RELOCATION RECORDS FOR \[\.rodata\.8\]: -OFFSET[[:space:]]+TYPE[[:space:]]+VALUE[[:space:]]* -[[:xdigit:]]+[08][[:space:]]+DIR64[LM]SB[[:space:]]+esym -[[:xdigit:]]+[08][[:space:]]+GPREL64[LM]SB[[:space:]]+esym -[[:xdigit:]]+[08][[:space:]]+PLTOFF64[LM]SB[[:space:]]+esym -[[:xdigit:]]+[08][[:space:]]+FPTR64[LM]SB[[:space:]]+esym -[[:xdigit:]]+[08][[:space:]]+PCREL64[LM]SB[[:space:]]+esym -[[:xdigit:]]+[08][[:space:]]+LTOFF_FPTR64[LM]SB[[:space:]]+esym -[[:xdigit:]]+[08][[:space:]]+SEGREL64[LM]SB[[:space:]]+esym -[[:xdigit:]]+[08][[:space:]]+SECREL64[LM]SB[[:space:]]+esym -[[:xdigit:]]+[08][[:space:]]+LTV64[LM]SB[[:space:]]+esym -[[:xdigit:]]+[08][[:space:]]+IPLT[LM]SB[[:space:]]+esym -[[:xdigit:]]+[08][[:space:]]+TPREL64[LM]SB[[:space:]]+esym -[[:xdigit:]]+[08][[:space:]]+DTPMOD64[LM]SB[[:space:]]+esym -[[:xdigit:]]+[08][[:space:]]+DTPREL64[LM]SB[[:space:]]+esym diff --git a/gas/testsuite/gas/ia64/reloc.s b/gas/testsuite/gas/ia64/reloc.s deleted file mode 100644 index e5caa7c6d2f..00000000000 --- a/gas/testsuite/gas/ia64/reloc.s +++ /dev/null @@ -1,82 +0,0 @@ - .global esym - .section .rodata.4, "a", @progbits - .section .rodata.8, "a", @progbits - .text -_start: - adds r1 =3D esym, r0 - mov r2 =3D esym - movl r3 =3D esym - .xdata4 .rodata.4, esym - .xdata8 .rodata.8, esym - - mov r2 =3D @gprel(esym) - movl r3 =3D @gprel(esym) - .xdata4 .rodata.4, @gprel(esym) - .xdata8 .rodata.8, @gprel(esym) - - mov r2 =3D @ltoff(esym) - movl r3 =3D @ltoff(esym) - - mov r2 =3D @pltoff(esym) - movl r3 =3D @pltoff(esym) - .xdata8 .rodata.8, @pltoff(esym) - - movl r3 =3D @fptr(esym) - .xdata4 .rodata.4, @fptr(esym) - .xdata8 .rodata.8, @fptr(esym) - - brl.call.sptk b1 =3D esym - br.call.sptk b2 =3D esym - chk.s r0, esym - fchkf esym - .xdata4 .rodata.4, @pcrel(esym) - .xdata8 .rodata.8, @pcrel(esym) - - mov r2 =3D @ltoff(@fptr(esym)) - movl r3 =3D @ltoff(@fptr(esym)) - .xdata4 .rodata.4, @ltoff(@fptr(esym)) - .xdata8 .rodata.8, @ltoff(@fptr(esym)) - - .xdata4 .rodata.4, @segrel(esym) - .xdata8 .rodata.8, @segrel(esym) - - .xdata4 .rodata.4, @secrel(esym) - .xdata8 .rodata.8, @secrel(esym) - - // REL32 only in executables - // REL64 only in executables - - .xdata4 .rodata.4, @ltv(esym) - .xdata8 .rodata.8, @ltv(esym) - -//todo PCREL21BI - mov r2 =3D @pcrel(esym) - movl r3 =3D @pcrel(esym) - - .xdata16 .rodata.8, @iplt(esym) - - // COPY only in executables - -//todo movl r3 =3D -esym - - mov r2 =3D @ltoffx(esym) - ld8.mov r3 =3D [r2], esym - - adds r1 =3D @tprel(esym), r0 - mov r2 =3D @tprel(esym) - movl r3 =3D @tprel(esym) - .xdata8 .rodata.8, @tprel(esym) - - mov r2 =3D @ltoff(@tprel(esym)) - - .xdata8 .rodata.8, @dtpmod(esym) - - mov r2 =3D @ltoff(@dtpmod(esym)) - - adds r1 =3D @dtprel(esym), r0 - mov r2 =3D @dtprel(esym) - movl r3 =3D @dtprel(esym) - .xdata4 .rodata.4, @dtprel(esym) - .xdata8 .rodata.8, @dtprel(esym) - - mov r2 =3D @ltoff(@dtprel(esym)) diff --git a/gas/testsuite/gas/ia64/rotX.l b/gas/testsuite/gas/ia64/rotX.l deleted file mode 100644 index 1159774575c..00000000000 --- a/gas/testsuite/gas/ia64/rotX.l +++ /dev/null @@ -1,5 +0,0 @@ -.*: Assembler messages: -.*.s:[[:digit:]]+: Error: [Nn]umber of elements must be positive -.*.s:[[:digit:]]+: Error: [Nn]umber of elements must be positive -.*.s:[[:digit:]]+: Error: [Bb]ad or irreducible absolute expression -#pass diff --git a/gas/testsuite/gas/ia64/rotX.s b/gas/testsuite/gas/ia64/rotX.s deleted file mode 100644 index 48320f6d070..00000000000 --- a/gas/testsuite/gas/ia64/rotX.s +++ /dev/null @@ -1,4 +0,0 @@ -.regstk 0, 8, 0, 8 -.rotr a[8], b[-8] -.rotp c[8], d[0] -.rotf e[8], f[x] diff --git a/gas/testsuite/gas/ia64/secname-ilp32.d b/gas/testsuite/gas/ia6= 4/secname-ilp32.d deleted file mode 100644 index 0b8a77193d0..00000000000 --- a/gas/testsuite/gas/ia64/secname-ilp32.d +++ /dev/null @@ -1,19 +0,0 @@ -#readelf: -S -#name: ia64 section name (ilp32) -#as: -milp32 -#source: secname.s - -There are 8 section headers, starting at offset .*: - -Section Headers: - \[Nr\] Name Type Addr Off Size ES Flg L= k Inf Al - \[ 0\] NULL 00000000 000000 000000 00 = 0 0 0 - \[ 1\] .text PROGBITS 00000000 000040 000000 00 AX = 0 0 16 - \[ 2\] .data PROGBITS 00000000 000040 000000 00 WA = 0 0 1 - \[ 3\] .bss NOBITS 00000000 000040 000000 00 WA = 0 0 1 - \[ 4\] .foo PROGBITS 00000000 000040 000008 00 WA = 0 0 8 - \[ 5\] .symtab SYMTAB 00000000 [0-9a-f]+ 000050 10 = 6 5 4 - \[ 6\] .strtab STRTAB 00000000 [0-9a-f]+ 000001 00 = 0 0 1 - \[ 7\] .shstrtab STRTAB 00000000 [0-9a-f]+ 000031 00 = 0 0 1 -Key to Flags: -#... diff --git a/gas/testsuite/gas/ia64/secname.d b/gas/testsuite/gas/ia64/secn= ame.d deleted file mode 100644 index 9d02e1a5f49..00000000000 --- a/gas/testsuite/gas/ia64/secname.d +++ /dev/null @@ -1,26 +0,0 @@ -#readelf: -S -#name: ia64 section name - -There are 8 section headers, starting at offset .*: - -Section Headers: - \[Nr\] Name Type Address Offset - Size EntSize Flags Link Info Align - \[ 0\] NULL 0000000000000000 00000000 - 0000000000000000 0000000000000000 0 0 0 - \[ 1\] \.text PROGBITS 0000000000000000 00000040 - 0000000000000000 0000000000000000 AX 0 0 16 - \[ 2\] \.data PROGBITS 0000000000000000 00000040 - 0000000000000000 0000000000000000 WA 0 0 1 - \[ 3\] \.bss NOBITS 0000000000000000 00000040 - 0000000000000000 0000000000000000 WA 0 0 1 - \[ 4\] \.foo PROGBITS 0000000000000000 00000040 - 0000000000000008 0000000000000000 WA 0 0 8 - \[ 5\] \.symtab SYMTAB 0000000000000000 .* - 0000000000000078 0000000000000018 6 5 8 - \[ 6\] \.strtab STRTAB 0000000000000000 .* - 0000000000000001 0000000000000000 0 0 1 - \[ 7\] \.shstrtab STRTAB 0000000000000000 [0-9a-f]+ - 0000000000000031 0000000000000000 0 0 1 -Key to Flags: -#... diff --git a/gas/testsuite/gas/ia64/secname.s b/gas/testsuite/gas/ia64/secn= ame.s deleted file mode 100644 index 42e21b6205a..00000000000 --- a/gas/testsuite/gas/ia64/secname.s +++ /dev/null @@ -1,2 +0,0 @@ - .section .foo#,"aw","progbits" - data8 1234 diff --git a/gas/testsuite/gas/ia64/slot2.l b/gas/testsuite/gas/ia64/slot2.l deleted file mode 100644 index f52299a1363..00000000000 --- a/gas/testsuite/gas/ia64/slot2.l +++ /dev/null @@ -1,3 +0,0 @@ -.*: Assembler messages: -.*:11: Error: .* must be last in bundle -.*:16: Error: .* must be last in bundle diff --git a/gas/testsuite/gas/ia64/slot2.s b/gas/testsuite/gas/ia64/slot2.s deleted file mode 100644 index 030db8e0695..00000000000 --- a/gas/testsuite/gas/ia64/slot2.s +++ /dev/null @@ -1,18 +0,0 @@ -.explicit -_start: -{.mib - br.cloop.sptk start -} ;; -{.mib - nop 0 - br.cloop.sptk start -} ;; -{.mbb - br.cloop.sptk start - nop 0 -} ;; -{.mbb - nop 0 - br.cloop.sptk start - nop 0 -} ;; diff --git a/gas/testsuite/gas/ia64/slotcount.d b/gas/testsuite/gas/ia64/sl= otcount.d deleted file mode 100644 index 3548266380d..00000000000 --- a/gas/testsuite/gas/ia64/slotcount.d +++ /dev/null @@ -1,10 +0,0 @@ -#objdump: -s -j .slot_test -#name: ia64 slotcount - -.*: +file format .* - -Contents of section .slot_test: - 0000 04000000 01000000 02000000 03000000 ................ - 0010 04000000 05000000 06000000 07000000 ................ - 0020 08000000 02000000 06000000 03000000 ................ - 0030 02000000 ....=20=20=20=20=20=20=20=20=20= =20=20=20 diff --git a/gas/testsuite/gas/ia64/slotcount.s b/gas/testsuite/gas/ia64/sl= otcount.s deleted file mode 100644 index bdbc318e140..00000000000 --- a/gas/testsuite/gas/ia64/slotcount.s +++ /dev/null @@ -1,51 +0,0 @@ - .section .slot_test0,"",@progbits - data4.ua @slotcount(.L1-.L0) - - .text - .align 16 -foo: -[.L0:] - mov r2 =3D r12 -[.L1:] - mov r8 =3D r14 -[.L2:] - ;; - mov r12 =3D r2 -[.L3:] - { - .mii - nop 0 -[.L4:] - nop 0 -[.L5:] - nop 0 - } - { -[.L6:] - nop 0 -[.L7:] - nop 0 -[.L8:] - br.ret.sptk.many b0 - ;; - } - - .section .slot_test,"",@progbits -// data4.ua @slotcount(.Lundef) - - data4.ua @slotcount(17) - - data4.ua @slotcount(.L1-.L0) // 1 - data4.ua @slotcount(.L2-.L0) // 2 - data4.ua @slotcount(.L3-.L0) // 3 - data4.ua @slotcount(.L4-.L0) // 4 - data4.ua @slotcount(.L5-.L0) // 5 - data4.ua @slotcount(.L6-.L0) // 6 - data4.ua @slotcount(.L7-.L0) // 7 - data4.ua @slotcount(.L8-.L0) // 8 - - data4.ua @slotcount(.L3-.L1) // 2 - data4.ua @slotcount(.L8-.L2) // 6 - data4.ua @slotcount(.L4-.L1) // 3 - data4.ua @slotcount(.L4-.L2) // 2 -// data4.ua @slotcount(.L2-.Lundef) diff --git a/gas/testsuite/gas/ia64/strange.d b/gas/testsuite/gas/ia64/stra= nge.d deleted file mode 100644 index 287d073762d..00000000000 --- a/gas/testsuite/gas/ia64/strange.d +++ /dev/null @@ -1,19 +0,0 @@ -#objdump: -s -#name: ia64 strange - -.*: +file format .* - -Contents of section .text: - 0000 0c000000 01001000 00020000 00000400 .* - 0010 04000000 01000000 00000020 00000400 .* - 0020 0c000000 01002000 00020000 00000400 .* - 0030 04000000 01000000 00000040 00000400 .* - 0040 1c000000 01003000 00020000 00000020 .* - 0050 04000000 01000000 00000080 00000400 .* - 0060 04000000 01000000 000000a0 00000400 .* - 0070 04000000 01000000 000000c0 00000400 .* - 0080 04000000 01000000 000000e0 00000400 .* - 0090 0e000000 01000000 00020000 01000400 .* - 00a0 1d000000 01009000 00020080 00008400 .* -Contents of section .data: - 0000 ffffff .* diff --git a/gas/testsuite/gas/ia64/strange.s b/gas/testsuite/gas/ia64/stra= nge.s deleted file mode 100644 index 9a19b046128..00000000000 --- a/gas/testsuite/gas/ia64/strange.s +++ /dev/null @@ -1,18 +0,0 @@ -.explicit -.text -_start: -{.mfi - nop.f 1 } nop.x 1 -{.mfi - nop.f 2 -} nop.x 2 -{.mfb - nop.f 3 -.xdata1 .data, -1 } .xdata1 .data, -1 - nop.x 4 { nop.x 5 -} { nop.x 6 } - nop.x 7 {.mmf - nop.f 8 -} .xdata1 .data, -1 { .mfb - nop.f 9 - br.ret.sptk rp } diff --git a/gas/testsuite/gas/ia64/tls.d b/gas/testsuite/gas/ia64/tls.d deleted file mode 100644 index 3f03b25291b..00000000000 --- a/gas/testsuite/gas/ia64/tls.d +++ /dev/null @@ -1,54 +0,0 @@ -#as: -xnone -mtune=3Ditanium1 -#objdump: -dr -#name: ia64 tls - -.*: +file format .* - -Disassembly of section \.text: - -0+000 : - 0: 0d 20 21 0a 80 05 \[MFI\] alloc r36=3Dar\.pfs,8,5,0 - 2: LTOFF_TPREL22 x - 6: 00 00 00 02 00 00 nop\.f 0x0 - c: 04 08 00 90 addl r32=3D0,r1;; - 10: 0b 00 01 40 18 10 \[MMI\] ld8 r32=3D\[r32\];; - 16: 10 02 35 00 40 00 add r33=3Dr32,r13 - 1c: 00 00 04 00 nop\.i 0x0;; - 20: 0b 10 00 1a 00 21 \[MMI\] mov r2=3Dr13;; - 21: TPREL22 y - 26: 10 02 08 00 48 00 addl r33=3D0,r2 - 2c: 00 00 04 00 nop\.i 0x0;; - 30: 01 00 01 02 00 21 \[MII\] mov r32=3Dr1 - 31: LTOFF_DTPMOD22 z - 32: LTOFF_DTPREL22 z - 36: 50 02 04 00 48 c0 addl r37=3D0,r1 - 3c: 04 08 00 90 addl r38=3D0,r1;; - 40: 19 28 01 4a 18 10 \[MMB\] ld8 r37=3D\[r37\] - 42: PCREL21B __tls_get_addr - 46: 60 02 98 30 20 00 ld8 r38=3D\[r38\] - 4c: 08 00 00 50 br\.call\.sptk\.many b0=3D40 ;; - 50: 0b 08 00 40 00 21 \[MMI\] mov r1=3Dr32;; - 51: LTOFF_DTPMOD22 a - 52: DTPREL22 a - 56: 50 02 04 00 48 c0 addl r37=3D0,r1 - 5c: 04 00 00 90 mov r38=3D0;; - 60: 1d 28 01 4a 18 10 \[MFB\] ld8 r37=3D\[r37\] - 62: PCREL21B __tls_get_addr - 66: 00 00 00 02 00 00 nop\.f 0x0 - 6c: 08 00 00 50 br\.call\.sptk\.many b0=3D60 ;; - 70: 0b 08 00 40 00 21 \[MMI\] mov r1=3Dr32;; - 71: LTOFF_DTPMOD22 b - 76: 50 02 04 00 48 c0 addl r37=3D0,r1 - 7c: 04 00 00 84 mov r38=3Dr0;; - 80: 1d 28 01 4a 18 10 \[MFB\] ld8 r37=3D\[r37\] - 82: PCREL21B __tls_get_addr - 86: 00 00 00 02 00 00 nop\.f 0x0 - 8c: 08 00 00 50 br\.call\.sptk\.many b0=3D80 ;; - 90: 02 08 00 40 00 21 \[MII\] mov r1=3Dr32 - 92: DTPREL22 b - 96: 20 00 20 00 42 20 mov r2=3Dr8;; - 9c: 04 10 00 90 addl r33=3D0,r2 - a0: 1d 10 01 04 00 24 \[MFB\] addl r34=3D0,r2 - a0: DTPREL22 c - a6: 00 00 00 02 00 80 nop\.f 0x0 - ac: 08 00 84 00 br\.ret\.sptk\.many b0;; diff --git a/gas/testsuite/gas/ia64/tls.s b/gas/testsuite/gas/ia64/tls.s deleted file mode 100644 index 6a32386e66c..00000000000 --- a/gas/testsuite/gas/ia64/tls.s +++ /dev/null @@ -1,64 +0,0 @@ - .section ".tdata", "awT", @progbits - .align 16 - .global x#, y#, z#, a#, b#, c# - .protected a#, b#, c# - .type x#,@object - .size x#,4 -x: data4 1 - .type y#,@object - .size y#,4 -y: data4 2 - .type z#,@object - .size z#,4 -z: data4 3 - .align 8 - .type a#,@object - .size a#,8 -a: data8 4 - .type b#,@object - .size b#,8 -b: data8 5 - .type c#,@object - .size c#,1 -c: data1 6 - - .text - .align 16 - .global foo# - .proc foo# -foo: - .prologue - alloc r36 =3D ar.pfs, 0, 5, 3, 0 - .body - addl loc0 =3D @ltoff(@tprel(x)), gp;; - ld8 loc0 =3D [loc0];; - add loc1 =3D loc0, r13;; - - mov r2 =3D r13;; - addl loc1 =3D @tprel(y), r2;; - - mov loc0 =3D gp - addl out0 =3D @ltoff(@dtpmod(z)), gp - addl out1 =3D @ltoff(@dtprel(z)), gp;; - ld8 out0 =3D [out0] - ld8 out1 =3D [out1] - br.call.sptk.many b0 =3D __tls_get_addr;; - mov gp =3D loc0;; - - addl out0 =3D @ltoff(@dtpmod(a)), gp - addl out1 =3D @dtprel(a), r0;; - ld8 out0 =3D [out0] - br.call.sptk.many b0 =3D __tls_get_addr;; - mov gp =3D loc0;; - - addl out0 =3D @ltoff(@dtpmod(b)), gp - mov out1 =3D r0;; - ld8 out0 =3D [out0] - br.call.sptk.many b0 =3D __tls_get_addr;; - mov gp =3D loc0 - mov r2 =3D ret0;; - addl loc1 =3D @dtprel(b), r2 - addl loc2 =3D @dtprel(c), r2 - - br.ret.sptk.many b0 - .endp foo# diff --git a/gas/testsuite/gas/ia64/unwind-bad.l b/gas/testsuite/gas/ia64/u= nwind-bad.l deleted file mode 100644 index 7009fab54af..00000000000 --- a/gas/testsuite/gas/ia64/unwind-bad.l +++ /dev/null @@ -1,51 +0,0 @@ -.*: Assembler messages: -.*:8: Error: First operand to \.save\.g must be a positive 4-bit constant -.*:10: Error: First operand to \.save\.g must be a positive 4-bit constant -.*:12: Error: First operand to \.save\.g must be a positive 4-bit constant -.*:16: Warning: Previous .save incomplete -#FIXME .*:18: Error: Register r4 was already saved -.*:20: Error: Operand to \.save\.f must be a positive 20-bit constant -.*:22: Error: Operand to \.save\.f must be a positive 20-bit constant -.*:24: Error: Operand to \.save\.f must be a positive 20-bit constant -.*:28: Warning: Previous .save incomplete -#FIXME .*:30: Error: Register f2 was already saved -.*:32: Error: First operand to \.save\.b must be a positive 5-bit constant -.*:34: Error: First operand to \.save\.b must be a positive 5-bit constant -.*:36: Error: First operand to \.save\.b must be a positive 5-bit constant -.*:40: Warning: Previous .save incomplete -#FIXME .*:42: Error: Register b1 was already saved -.*:44: Error: Operand 2 to \.spillreg must be a writable register -.*:46: Error: Operand 1 to \.spillreg must be a preserved register -.*:48: Error: Operand 1 to \.spillreg must be a preserved register -.*:50: Error: Operand 1 to \.spillreg must be a preserved register -.*:52: Error: Operand 2 to \.spillreg must be a writable register -.*:54: Error: Operand 2 to \.spillreg must be a writable register -.*:56: Error: Operand 1 to \.spillreg must be a preserved register -#FIXME .*:58: Error: Floating point register cannot be spilled to general = register -#FIXME .*:60: Error: Floating point register cannot be spilled to branch r= egister -.*:62: Warning: Pointless use of p0 as first operand to \.spillreg\.p -.*:64: Error: Operand 3 to \.spillreg.p must be a writable register -.*:66: Error: Operand 3 to \.spillreg.p must be a writable register -.*:68: Warning: Pointless use of p0 as first operand to \.restorereg\.p -.*:78: Error: Operands to \.save\.gf may not be both zero -.*:80: Error: First operand to \.save\.gf must be a non-negative 4-bit con= stant -.*:82: Error: Second operand to \.save\.gf must be a non-negative 20-bit c= onstant -.*:84: Error: First operand to \.save\.gf must be a non-negative 4-bit con= stant -.*:86: Error: Second operand to \.save\.gf must be a non-negative 20-bit c= onstant -.*:90: Warning: Previous .save incomplete -#FIXME .*:92: Error: Register r4 was already saved -#FIXME .*:94: Error: Register f2 was already saved -.*:98: Error: Epilogue count of 2 exceeds number of nested prologues \(1\) -.*:100: Error: Missing \.label_state 2 -.*:108: Error: First operand to \.save\.g must be a positive 4-bit constant -#FIXME .*:110: Error: Second operand to \.save\.g must be a writable gener= al registers -.*:112: Error: Second operand to \.save\.g must be the first of 2 general = registers -.*:115: Error: First operand to \.save\.b must be a positive 5-bit constant -#FIXME .*:117: Error: Second operand to \.save\.b must be a writable gener= al registers -.*:119: Error: Second operand to \.save\.b must be the first of 2 general = registers -.*:128: Error: First operand to \.prologue must be a positive 4-bit consta= nt -.*:134: Warning: Pointless use of zero first operand to \.prologue -.*:140: Error: First operand to \.prologue must be a positive 4-bit consta= nt -#FIXME .*:141: Error: Operand to \.vframe must be a writable general regis= ters -#FIXME .*:147: Error: Second operand to \.prologue must be a writable gene= ral registers -.*:153: Error: Second operand to \.prologue must be the first of 2 general= registers diff --git a/gas/testsuite/gas/ia64/unwind-bad.s b/gas/testsuite/gas/ia64/u= nwind-bad.s deleted file mode 100644 index 9a4b7beab50..00000000000 --- a/gas/testsuite/gas/ia64/unwind-bad.s +++ /dev/null @@ -1,155 +0,0 @@ -.text - -.proc full1 -full1: - -.prologue -.spill 0 -.save.g 0 - nop 0 -.save.g 0x10 - nop 0 -.save.g -1 - nop 0 -.save.g 0x3 - nop 0 -.save.g 0x4 - nop 0 -.save.g 0x1 - nop 0 -.save.f 0 - nop 0 -.save.f 0x100000 - nop 0 -.save.f -1 - nop 0 -.save.f 0x3 - nop 0 -.save.f 0x4 - nop 0 -.save.f 0x1 - nop 0 -.save.b 0 - nop 0 -.save.b 0x20 - nop 0 -.save.b -1 - nop 0 -.save.b 0x3 - nop 0 -.save.b 0x4 - nop 0 -.save.b 0x1 - nop 0 -.spillreg r4, r0 - nop 0 -.spillreg r3, r2 - nop 0 -.spillreg r8, r9 - nop 0 -.spillreg b6, r10 - nop 0 -.spillreg f2, f0 - nop 0 -.spillreg f3, f1 - nop 0 -.spillreg f6, f7 - nop 0 -.spillreg f4, r11 - nop 0 -.spillreg f5, b0 - nop 0 -.spillreg.p p0, r4, r3 - nop 0 -.spillreg.p p1, r4, r0 - nop 0 -.spillreg.p p1, f16, f0 - nop 0 -.restorereg.p p0, r4 - nop 0 -.body - br.ret.sptk rp -.endp full1 - -.proc full2 -full2: -.prologue -.spill 0 -.save.gf 0, 0 - nop 0 -.save.gf 0x10, 0 - nop 0 -.save.gf 0, 0x100000 - nop 0 -.save.gf ~0, 0 - nop 0 -.save.gf 0, ~0 - nop 0 -.save.gf 1, 1 - nop 0 -.save.gf 2, 0 - nop 0 -.save.gf 1, 0 - nop 0 -.save.gf 0, 1 - nop 0 -.body -.label_state 1 -.restore sp, 1 - nop.x 0 -.copy_state 2 - br.ret.sptk rp -.endp full2 - -.proc full3 -full3: -.prologue -.spill 0 -.save.g 0x10, r16 - nop 0 -.save.g 0x01, r0 - nop 0 -.save.g 0x06, r127 - nop 0 - nop 0 -.save.b 0x20, r16 - nop 0 -.save.b 0x01, r0 - nop 0 -.save.b 0x18, r127 - nop 0 - nop 0 -.body - br.ret.sptk rp -.endp full3 - -.proc simple1 -simple1: -.prologue 0x10, r2 - br.ret.sptk rp -.endp simple1 - -.proc simple2 -simple2: -.prologue 0, r2 - br.ret.sptk rp -.endp simple2 - -.proc simple3 -simple3: -.prologue -1, r2 -.vframe r0 - br.ret.sptk rp -.endp simple3 - -.proc simple4 -simple4: -.prologue 0x1, r0 - br.ret.sptk rp -.endp simple4 - -.proc simple5 -simple5: -.prologue 0xc, r127 - br.ret.sptk rp -.endp simple5 diff --git a/gas/testsuite/gas/ia64/unwind-err.l b/gas/testsuite/gas/ia64/u= nwind-err.l deleted file mode 100644 index 71cca18d592..00000000000 --- a/gas/testsuite/gas/ia64/unwind-err.l +++ /dev/null @@ -1,35 +0,0 @@ -.*: Assembler messages: -.*:1: Error: .endp outside of procedure -.*:2: Error: .personality outside of procedure -.*:3: Error: .unwentry outside of procedure -.*:4: Error: .unwabi outside of procedure -.*:5: Error: .handlerdata outside of procedure -.*:6: Error: .prologue outside of procedure -.*:7: Error: .body outside of procedure -.*:8: Error: .spillreg outside of procedure -.*:9: Error: .spillreg.p outside of procedure -.*:10: Error: .spillsp outside of procedure -.*:11: Error: .spillsp.p outside of procedure -.*:12: Error: .spillpsp outside of procedure -.*:13: Error: .spillpsp.p outside of procedure -.*:14: Error: .restorereg outside of procedure -.*:15: Error: .restorereg.p outside of procedure -.*:24: Error: .label_state outside of body region -.*:25: Error: .copy_state outside of body region -.*:26: Error: .fframe outside of prologue -.*:27: Error: .vframe outside of prologue -.*:28: Error: .vframesp outside of prologue -.*:29: Error: .spill outside of prologue -.*:30: Error: .restore outside of body region -.*:31: Error: .save outside of prologue -.*:32: Error: .savesp outside of prologue -.*:33: Error: .savepsp outside of prologue -.*:34: Error: .save.g outside of prologue -.*:35: Error: .save.gf outside of prologue -.*:36: Error: .save.f outside of prologue -.*:37: Error: .save.b outside of prologue -.*:38: Error: .altrp outside of prologue -.*:43: Error: .prologue within prologue -.*:51: Error: .body outside of procedure -.*:58: Warning: Initial .prologue.* -.*:65: Warning: Initial .body.* diff --git a/gas/testsuite/gas/ia64/unwind-err.s b/gas/testsuite/gas/ia64/u= nwind-err.s deleted file mode 100644 index 81b25974644..00000000000 --- a/gas/testsuite/gas/ia64/unwind-err.s +++ /dev/null @@ -1,67 +0,0 @@ -.endp xyz -.personality personality -.unwentry -.unwabi @svr4, 0 -.handlerdata -.prologue -.body -.spillreg r4, r8 -.spillreg.p p1, r4, r8 -.spillsp r5, 0 -.spillsp.p p2, r5, 0 -.spillpsp r6, 0 -.spillpsp.p p2, r6, 0 -.restorereg r4 -.restorereg.p p1, r4 - -.proc personality -personality: -.endp personality - -.proc start -start: - -.label_state 1 -.copy_state 1 -.fframe 0 -.vframe r0 -.vframesp 0 -.spill 0 -.restore sp -.save rp, r0 -.savesp pr, 0 -.savepsp ar.fpsr, 0 -.save.g 2 -.save.gf 2,2 -.save.f 2 -.save.b 2 -.altrp b7 -.body - - - .prologue - .prologue - .save ar.lc, r31 - mov r31 =3D ar.lc - .body - .body - br.ret.sptk rp -.personality personality -.handlerdata -.body - -.endp start - -.proc late_prologue -late_prologue: - nop 0 - .prologue - nop 0 -.endp late_prologue - -.proc late_body -late_body: - nop 0 - .body - nop 0 -.endp late_body diff --git a/gas/testsuite/gas/ia64/unwind-ilp32.d b/gas/testsuite/gas/ia64= /unwind-ilp32.d deleted file mode 100644 index 9c12aad5a54..00000000000 --- a/gas/testsuite/gas/ia64/unwind-ilp32.d +++ /dev/null @@ -1,20 +0,0 @@ -#readelf: -ST -#name: ia64 unwind section (ilp32) -#as: -milp32 -#source: unwind.s - -There are 9 section headers, starting at offset .*: - -Section Headers: - \[Nr\] Name Type Addr Off Size ES Flg L= k Inf Al - \[ 0\] NULL 00000000 000000 000000 00 = 0 0 0 - \[ 1\] .text PROGBITS 00000000 000040 000000 00 AX = 0 0 16 - \[ 2\] .data PROGBITS 00000000 000040 000000 00 WA = 0 0 1 - \[ 3\] .bss NOBITS 00000000 000040 000000 00 WA = 0 0 1 - \[ 4\] .IA_64.unwind_inf PROGBITS 00000000 000040 000008 00 A = 0 0 8 - \[ 5\] .IA_64.unwind IA_64_UNWIND 00000000 000048 000008 00 AL = 1 1 8 - \[ 6\] .symtab SYMTAB 00000000 [0-9a-f]+ 000060 10 = 7 6 4 - \[ 7\] .strtab STRTAB 00000000 [0-9a-f]+ 000001 00 = 0 0 1 - \[ 8\] .shstrtab STRTAB 00000000 [0-9a-f]+ 00004d 00 = 0 0 1 -Key to Flags: -#... diff --git a/gas/testsuite/gas/ia64/unwind-ok.d b/gas/testsuite/gas/ia64/un= wind-ok.d deleted file mode 100644 index e60c7cc94b8..00000000000 --- a/gas/testsuite/gas/ia64/unwind-ok.d +++ /dev/null @@ -1,224 +0,0 @@ -#readelf: -u -#name: ia64 unwind descriptors - -Unwind section '\.IA_64\.unwind' at offset 0x[[:xdigit:]]+ contains 8 entr= ies: - -: \[0x[[:xdigit:]]*0-0x[[:xdigit:]]*0\], info at \+0x[[:xdigit:]]*[= 08] -[[:space:]]*v[[:digit:]]+, flags=3D0x3 \( ?ehandler uhandler\), len=3D[[:d= igit:]]+ bytes -[[:space:]]*R1:prologue\(rlen=3D8\) -[[:space:]]*P6:fr_mem\(frmask=3D\[f2,f5\]\) -[[:space:]]*P6:gr_mem\(grmask=3D\[r4,r7\]\) -[[:space:]]*P1:br_mem\(brmask=3D\[b1,b5\]\) -[[:space:]]*P4:spill_mask\(imask=3D\[rfb,rfb,--\]\) -[[:space:]]*P7:spill_base\(pspoff=3D0x10-0x10\) -[[:space:]]*P3:rp_br\(reg=3Db7\) -[[:space:]]*P10:unwabi\(abi=3D@svr4,context=3D0x00\) -[[:space:]]*R1:body\(rlen=3D25\) -[[:space:]]*X2:spill_reg\(t=3D0,reg=3Dr4,treg=3Dr2\) -[[:space:]]*X4:spill_reg_p\(qp=3Dp1,t=3D1,reg=3Dr7,treg=3Dr31\) -[[:space:]]*X1:spill_sprel\(reg=3Db1,t=3D2,spoff=3D0x8\) -[[:space:]]*X3:spill_sprel_p\(qp=3Dp2,t=3D3,reg=3Db5,spoff=3D0x10\) -[[:space:]]*X1:spill_psprel\(reg=3Df2,t=3D4,pspoff=3D0x10-0x28\) -[[:space:]]*X3:spill_psprel_p\(qp=3Dp4,t=3D5,reg=3Df5,pspoff=3D0x10-0x30\) -[[:space:]]*X2:restore\(t=3D6,reg=3Df16\) -[[:space:]]*X4:restore_p\(qp=3Dp8,t=3D7,reg=3Df31\) -[[:space:]]*X2:spill_reg\(t=3D8,reg=3Dar\.bsp,treg=3Dr16\) -[[:space:]]*X2:spill_reg\(t=3D9,reg=3Dar\.bspstore,treg=3Dr17\) -[[:space:]]*X2:spill_reg\(t=3D10,reg=3Dar\.fpsr,treg=3Dr18\) -[[:space:]]*X2:spill_reg\(t=3D11,reg=3Dar\.lc,treg=3Dr19\) -[[:space:]]*X2:spill_reg\(t=3D12,reg=3Dar\.pfs,treg=3Dr20\) -[[:space:]]*X2:spill_reg\(t=3D13,reg=3Dar\.rnat,treg=3Dr21\) -[[:space:]]*X2:spill_reg\(t=3D14,reg=3Dar\.unat,treg=3Dr22\) -[[:space:]]*X2:spill_reg\(t=3D15,reg=3Dpsp,treg=3Dr23\) -[[:space:]]*X2:spill_reg\(t=3D16,reg=3Dpr,treg=3Dr24\) -[[:space:]]*X2:spill_reg\(t=3D17,reg=3Drp,treg=3Dr25\) -[[:space:]]*X2:spill_reg\(t=3D18,reg=3D@priunat,treg=3Dr26\) -[[:space:]]*B1:label_state\(label=3D1\) -[[:space:]]*B2:epilogue\(t=3D4,ecount=3D0\) -[[:space:]]*B1:copy_state\(label=3D1\) -#... -: \[0x[[:xdigit:]]*0-0x[[:xdigit:]]*0\], info at \+0x[[:xdigit:]]*[= 08] -[[:space:]]*v[[:digit:]]+, flags=3D0x0( \(\))?, len=3D[[:digit:]]+ bytes -[[:space:]]*R2:prologue_gr\(mask=3D\[rp,psp,pr\],grsave=3Dr8,rlen=3D14\) -[[:space:]]*P5:frgr_mem\(grmask=3D\[r4,r7\],frmask=3D\[f2,f31\]\) -[[:space:]]*P4:spill_mask\(imask=3D\[frb,bfr,---,---,--\]\) -[[:space:]]*P7:spill_base\(pspoff=3D0x10-0x10\) -[[:space:]]*P2:br_gr\(brmask=3D\[b1,b5\],gr=3Dr32\) -[[:space:]]*X2:spill_reg\(t=3D6,reg=3Df31,treg=3Df31\) -[[:space:]]*X4:spill_reg_p\(qp=3Dp63,t=3D7,reg=3Df16,treg=3Df0\) -[[:space:]]*X1:spill_sprel\(reg=3Df5,t=3D8,spoff=3D0x20\) -[[:space:]]*X3:spill_sprel_p\(qp=3Dp31,t=3D9,reg=3Df2,spoff=3D0x18\) -[[:space:]]*X1:spill_psprel\(reg=3Db5,t=3D10,pspoff=3D0x10-0x20\) -[[:space:]]*X3:spill_psprel_p\(qp=3Dp15,t=3D11,reg=3Db1,pspoff=3D0x10-0x18= \) -[[:space:]]*X2:restore\(t=3D12,reg=3Dr7\) -[[:space:]]*X4:restore_p\(qp=3Dp7,t=3D13,reg=3Dr4\) -[[:space:]]*R1:body\(rlen=3D0\) -[[:space:]]*R1:prologue\(rlen=3D0\) -[[:space:]]*R1:body\(rlen=3D0\) -[[:space:]]*R1:prologue\(rlen=3D0\) -[[:space:]]*R1:body\(rlen=3D0\) -[[:space:]]*R1:prologue\(rlen=3D0\) -[[:space:]]*R1:body\(rlen=3D0\) -[[:space:]]*R1:prologue\(rlen=3D0\) -[[:space:]]*R1:body\(rlen=3D0\) -[[:space:]]*R1:prologue\(rlen=3D0\) -[[:space:]]*R1:body\(rlen=3D0\) -[[:space:]]*R1:prologue\(rlen=3D0\) -[[:space:]]*R1:body\(rlen=3D0\) -[[:space:]]*R1:prologue\(rlen=3D0\) -[[:space:]]*R1:body\(rlen=3D0\) -[[:space:]]*R1:prologue\(rlen=3D0\) -[[:space:]]*R1:body\(rlen=3D0\) -[[:space:]]*R1:prologue\(rlen=3D0\) -[[:space:]]*R1:body\(rlen=3D0\) -[[:space:]]*R1:prologue\(rlen=3D0\) -[[:space:]]*R1:body\(rlen=3D0\) -[[:space:]]*R1:prologue\(rlen=3D0\) -[[:space:]]*R1:body\(rlen=3D0\) -[[:space:]]*R1:prologue\(rlen=3D0\) -[[:space:]]*R1:body\(rlen=3D0\) -[[:space:]]*R1:prologue\(rlen=3D0\) -[[:space:]]*R1:body\(rlen=3D0\) -[[:space:]]*R1:prologue\(rlen=3D0\) -[[:space:]]*R1:body\(rlen=3D0\) -[[:space:]]*R1:prologue\(rlen=3D0\) -[[:space:]]*R1:body\(rlen=3D0\) -[[:space:]]*R1:prologue\(rlen=3D0\) -[[:space:]]*R1:body\(rlen=3D0\) -[[:space:]]*R1:prologue\(rlen=3D0\) -[[:space:]]*R1:body\(rlen=3D0\) -[[:space:]]*R1:prologue\(rlen=3D0\) -[[:space:]]*R1:body\(rlen=3D0\) -[[:space:]]*R1:prologue\(rlen=3D0\) -[[:space:]]*R1:body\(rlen=3D0\) -[[:space:]]*R1:prologue\(rlen=3D0\) -[[:space:]]*R1:body\(rlen=3D0\) -[[:space:]]*R1:prologue\(rlen=3D0\) -[[:space:]]*R1:body\(rlen=3D0\) -[[:space:]]*R1:prologue\(rlen=3D0\) -[[:space:]]*R1:body\(rlen=3D0\) -[[:space:]]*R1:prologue\(rlen=3D0\) -[[:space:]]*R1:body\(rlen=3D0\) -[[:space:]]*R1:prologue\(rlen=3D0\) -[[:space:]]*R1:body\(rlen=3D0\) -[[:space:]]*R1:prologue\(rlen=3D0\) -[[:space:]]*R1:body\(rlen=3D0\) -[[:space:]]*R1:prologue\(rlen=3D0\) -[[:space:]]*R1:body\(rlen=3D0\) -[[:space:]]*R1:prologue\(rlen=3D0\) -[[:space:]]*R1:body\(rlen=3D0\) -[[:space:]]*R1:prologue\(rlen=3D0\) -[[:space:]]*R1:body\(rlen=3D0\) -[[:space:]]*R1:prologue\(rlen=3D0\) -[[:space:]]*R1:body\(rlen=3D0\) -[[:space:]]*R1:prologue\(rlen=3D0\) -[[:space:]]*R1:body\(rlen=3D0\) -[[:space:]]*R1:prologue\(rlen=3D0\) -[[:space:]]*R1:body\(rlen=3D0\) -[[:space:]]*R1:prologue\(rlen=3D0\) -[[:space:]]*R1:body\(rlen=3D7\) -[[:space:]]*B4:label_state\(label=3D32\) -[[:space:]]*B3:epilogue\(t=3D4,ecount=3D32\) -[[:space:]]*B4:copy_state\(label=3D32\) -#... -: \[0x[[:xdigit:]]*0-0x[[:xdigit:]]*0\], info at \+0x[[:xdigit:]]*[= 08] -[[:space:]]*v[[:digit:]]+, flags=3D0x0( \(\))?, len=3D[[:digit:]]+ bytes -[[:space:]]*R3:prologue\(rlen=3D33\) -[[:space:]]*P4:spill_mask\(imask=3D\[rrb,brr,bb-,---,---,---,---,---,---,-= --,---\]\) -[[:space:]]*P7:spill_base\(pspoff=3D0x10-0x10\) -[[:space:]]*P9:gr_gr\(grmask=3D\[r4,r5\],r32\) -[[:space:]]*P2:br_gr\(brmask=3D\[b1,b2\],gr=3Dr34\) -[[:space:]]*P9:gr_gr\(grmask=3D\[r6,r7\],r124\) -[[:space:]]*P2:br_gr\(brmask=3D\[b4,b5\],gr=3Dr126\) -[[:space:]]*R3:body\(rlen=3D33\) -#... -: \[0x[[:xdigit:]]*0-0x[[:xdigit:]]*0\], info at \+0x[[:xdigit:]]*= [08] -[[:space:]]*v[[:digit:]]+, flags=3D0x0( \(\))?, len=3D[[:digit:]]+ bytes -[[:space:]]*R1:prologue\(rlen=3D1\) -[[:space:]]*P7:mem_stack_f\(t=3D0,size=3D0\) -[[:space:]]*R1:body\(rlen=3D2\) -#... -: \[0x[[:xdigit:]]*0-0x[[:xdigit:]]*0\], info at \+0x[[:xdigit:]]*= [08] -[[:space:]]*v[[:digit:]]+, flags=3D0x0( \(\))?, len=3D[[:digit:]]+ bytes -[[:space:]]*R1:prologue\(rlen=3D11\) -[[:space:]]*P7:mem_stack_v\(t=3D0\) -[[:space:]]*P3:psp_gr\(reg=3Dr16\) -[[:space:]]*P8:bsp_when\(t=3D1\) -[[:space:]]*P3:bsp_gr\(reg=3Dr17\) -[[:space:]]*P8:bspstore_when\(t=3D2\) -[[:space:]]*P3:bspstore_gr\(reg=3Dr18\) -[[:space:]]*P7:fpsr_when\(t=3D3\) -[[:space:]]*P3:fpsr_gr\(reg=3Dr19\) -[[:space:]]*P7:lc_when\(t=3D4\) -[[:space:]]*P3:lc_gr\(reg=3Dr20\) -[[:space:]]*P7:pfs_when\(t=3D5\) -[[:space:]]*P3:pfs_gr\(reg=3Dr21\) -[[:space:]]*P8:rnat_when\(t=3D6\) -[[:space:]]*P3:rnat_gr\(reg=3Dr22\) -[[:space:]]*P7:unat_when\(t=3D7\) -[[:space:]]*P3:unat_gr\(reg=3Dr23\) -[[:space:]]*P7:pr_when\(t=3D8\) -[[:space:]]*P3:pr_gr\(reg=3Dr24\) -[[:space:]]*P8:priunat_when_gr\(t=3D9\) -[[:space:]]*P3:priunat_gr\(reg=3Dr25\) -[[:space:]]*P7:rp_when\(t=3D10\) -[[:space:]]*P3:rp_gr\(reg=3Dr26\) -[[:space:]]*R1:body\(rlen=3D1\) -#... -: \[0x[[:xdigit:]]*0-0x[[:xdigit:]]*0\], info at \+0x[[:xdigit:]= ]*[08] -[[:space:]]*v[[:digit:]]+, flags=3D0x0( \(\))?, len=3D[[:digit:]]+ bytes -[[:space:]]*R1:prologue\(rlen=3D11\) -[[:space:]]*P7:mem_stack_v\(t=3D0\) -[[:space:]]*P7:psp_sprel\(spoff=3D0x0\) -[[:space:]]*P8:bsp_when\(t=3D1\) -[[:space:]]*P8:bsp_sprel\(spoff=3D0x8\) -[[:space:]]*P8:bspstore_when\(t=3D2\) -[[:space:]]*P8:bspstore_sprel\(spoff=3D0x10\) -[[:space:]]*P7:fpsr_when\(t=3D3\) -[[:space:]]*P8:fpsr_sprel\(spoff=3D0x18\) -[[:space:]]*P7:lc_when\(t=3D4\) -[[:space:]]*P8:lc_sprel\(spoff=3D0x20\) -[[:space:]]*P7:pfs_when\(t=3D5\) -[[:space:]]*P8:pfs_sprel\(spoff=3D0x28\) -[[:space:]]*P8:rnat_when\(t=3D6\) -[[:space:]]*P8:rnat_sprel\(spoff=3D0x30\) -[[:space:]]*P7:unat_when\(t=3D7\) -[[:space:]]*P8:unat_sprel\(spoff=3D0x38\) -[[:space:]]*P7:pr_when\(t=3D8\) -[[:space:]]*P8:pr_sprel\(spoff=3D0x40\) -[[:space:]]*P8:priunat_when_mem\(t=3D9\) -[[:space:]]*P8:priunat_sprel\(spoff=3D0x48\) -[[:space:]]*P7:rp_when\(t=3D10\) -[[:space:]]*P8:rp_sprel\(spoff=3D0x50\) -[[:space:]]*R1:body\(rlen=3D1\) -#... -: \[0x[[:xdigit:]]*0-0x[[:xdigit:]]*0\], info at \+0x[[:xdigit:]]*[08] -[[:space:]]*v[[:digit:]]+, flags=3D0x0( \(\))?, len=3D[[:digit:]]+ bytes -[[:space:]]*R1:prologue\(rlen=3D11\) -[[:space:]]*P7:mem_stack_v\(t=3D0\) -[[:space:]]*P7:psp_sprel\(spoff=3D0x0\) -[[:space:]]*P8:bsp_when\(t=3D1\) -[[:space:]]*P8:bsp_psprel\(pspoff=3D0x10-0x18\) -[[:space:]]*P8:bspstore_when\(t=3D2\) -[[:space:]]*P8:bspstore_psprel\(pspoff=3D0x10-0x20\) -[[:space:]]*P7:fpsr_when\(t=3D3\) -[[:space:]]*P7:fpsr_psprel\(pspoff=3D0x10-0x28\) -[[:space:]]*P7:lc_when\(t=3D4\) -[[:space:]]*P7:lc_psprel\(pspoff=3D0x10-0x30\) -[[:space:]]*P7:pfs_when\(t=3D5\) -[[:space:]]*P7:pfs_psprel\(pspoff=3D0x10-0x38\) -[[:space:]]*P8:rnat_when\(t=3D6\) -[[:space:]]*P8:rnat_psprel\(pspoff=3D0x10-0x40\) -[[:space:]]*P7:unat_when\(t=3D7\) -[[:space:]]*P7:unat_psprel\(pspoff=3D0x10-0x48\) -[[:space:]]*P7:pr_when\(t=3D8\) -[[:space:]]*P7:pr_psprel\(pspoff=3D0x10-0x50\) -[[:space:]]*P8:priunat_when_mem\(t=3D9\) -[[:space:]]*P8:priunat_psprel\(pspoff=3D0x10-0x58\) -[[:space:]]*P7:rp_when\(t=3D10\) -[[:space:]]*P7:rp_psprel\(pspoff=3D0x10-0x60\) -[[:space:]]*R1:body\(rlen=3D1\) -#... -: \[0x[[:xdigit:]]*0-0x[[:xdigit:]]*0\], info at \+0x[[:xdigit:]]*= [08] -[[:space:]]*v[[:digit:]]+, flags=3D0x0( \(\))?, len=3D[[:digit:]]+ bytes -#pass diff --git a/gas/testsuite/gas/ia64/unwind-ok.s b/gas/testsuite/gas/ia64/un= wind-ok.s deleted file mode 100644 index f2cc0cfffda..00000000000 --- a/gas/testsuite/gas/ia64/unwind-ok.s +++ /dev/null @@ -1,272 +0,0 @@ -.text -.proc personality -personality: - br.ret.sptk rp -.endp personality - -.proc full1 -full1: - -.prologue -.spill 0 -.save.g 0x1 - nop 0 -.save.f 0x1 - nop 0 -.save.b 0x01 - nop 0 -.save.g 0x8 - nop 0 -.save.f 0x8 - nop 0 -.save.b 0x10 - nop 0 -.altrp b7 - nop 0 -.unwabi @svr4, 0 - nop 0 - -.body -.spillreg r4, r2 - nop 0 -.spillreg.p p1, r7, r127 - nop 0 -.spillsp b1, 0x08 - nop 0 -.spillsp.p p2, b5, 0x10 - nop 0 -.spillpsp f2, 0x18 - nop 0 -.spillpsp.p p4, f5, 0x20 - nop 0 -.restorereg f16 - nop 0 -.restorereg.p p8, f31 - nop 0 - -.spillreg ar.bsp, r16 - nop 0 -.spillreg ar.bspstore, r17 - nop 0 -.spillreg ar.fpsr, r18 - nop 0 -.spillreg ar.lc, r19 - nop 0 -.spillreg ar.pfs, r20 - nop 0 -.spillreg ar.rnat, r21 - nop 0 -.spillreg ar.unat, r22 - nop 0 -.spillreg psp, r23 - nop 0 -.spillreg pr, r24 - nop 0 -.spillreg rp, r25 - nop 0 -.spillreg @priunat, r26 - nop 0 - -.label_state 1 - nop 0 -.restore sp - nop.x 0 -.copy_state 1 - br.ret.sptk rp - -.personality personality -.handlerdata - data4 -1 - data4 0 - -.endp full1 - -.proc full2 -full2: - -.prologue 0xb, r8 -.spill 0 -.save.gf 0x1, 0x00001 - nop 0 - nop 0 -.save.b 0x11, r32 - nop 0 - nop 0 -.save.gf 0x8, 0x80000 - nop 0 - nop 0 -.spillreg f31, f127 - nop 0 -.spillreg.p p63, f16, f32 - nop 0 -.spillsp f5, 0x20 - nop 0 -.spillsp.p p31, f2, 0x18 - nop 0 -.spillpsp b5, 0x10 - nop 0 -.spillpsp.p p15, b1, 0x08 - nop 0 -.restorereg r7 - nop 0 -.restorereg.p p7, r4 - nop 0 - -.body; .prologue; .body; .prologue; .body; .prologue; .body; .prologue -.body; .prologue; .body; .prologue; .body; .prologue; .body; .prologue -.body; .prologue; .body; .prologue; .body; .prologue; .body; .prologue -.body; .prologue; .body; .prologue; .body; .prologue; .body; .prologue -.body; .prologue; .body; .prologue; .body; .prologue; .body; .prologue -.body; .prologue; .body; .prologue; .body; .prologue; .body; .prologue -.body; .prologue; .body; .prologue; .body; .prologue; .body; .prologue -.body; .prologue; .body; .prologue; .body; .prologue; .body; .prologue - -.body -.label_state 32 - nop 0 -.restore sp, 32 - nop.x 0 -.copy_state 32 - br.ret.sptk rp -.endp full2 - -.proc full3 -full3: - -.prologue -.spill 0 -.save.g 0x3, r32 - nop 0 - nop 0 -.save.b 0x03, r34 - nop 0 - nop 0 -.save.g 0xc, r124 - nop 0 - nop 0 -.save.b 0x18, r126 - nop 0 - nop 0 - nop.x 0 - nop.x 0 - nop.x 0 - nop.x 0 - nop.x 0 - nop.x 0 - nop.x 0 - nop.x 0 -.body - nop.x 0 - nop.x 0 - nop.x 0 - nop.x 0 - nop.x 0 - nop.x 0 - nop.x 0 - nop.x 0 - nop.x 0 - nop.x 0 - br.ret.sptk rp -.endp full3 - -.proc fframe -fframe: -.prologue -.fframe 0 - nop 0 -.body - br.ret.sptk rp -.endp fframe - -.proc vframe -vframe: -.prologue -.vframe r16 - nop 0 -.save ar.bsp, r17 - nop 0 -.save ar.bspstore, r18 - nop 0 -.save ar.fpsr, r19 - nop 0 -.save ar.lc, r20 - nop 0 -.save ar.pfs, r21 - nop 0 -.save ar.rnat, r22 - nop 0 -.save ar.unat, r23 - nop 0 -.save pr, r24 - nop 0 -.save @priunat, r25 - nop 0 -.save rp, r26 - nop 0 -.body - br.ret.sptk rp -.endp vframe - -.proc vframesp -vframesp: -.prologue -.vframesp 0 - nop 0 -.savesp ar.bsp, 0x08 - nop 0 -.savesp ar.bspstore, 0x10 - nop 0 -.savesp ar.fpsr, 0x18 - nop 0 -.savesp ar.lc, 0x20 - nop 0 -.savesp ar.pfs, 0x28 - nop 0 -.savesp ar.rnat, 0x30 - nop 0 -.savesp ar.unat, 0x38 - nop 0 -.savesp pr, 0x40 - nop 0 -.savesp @priunat, 0x48 - nop 0 -.savesp rp, 0x50 - nop 0 -.body - br.ret.sptk rp -.endp vframesp - -.proc psp -psp: -.prologue -.vframesp 0 - nop 0 -.savepsp ar.bsp, 0x08 - nop 0 -.savepsp ar.bspstore, 0x10 - nop 0 -.savepsp ar.fpsr, 0x18 - nop 0 -.savepsp ar.lc, 0x20 - nop 0 -.savepsp ar.pfs, 0x28 - nop 0 -.savepsp ar.rnat, 0x30 - nop 0 -.savepsp ar.unat, 0x38 - nop 0 -.savepsp pr, 0x40 - nop 0 -.savepsp @priunat, 0x48 - nop 0 -.savepsp rp, 0x50 - nop 0 -.body - br.ret.sptk rp -.endp psp - -.proc simple -simple: -.unwentry - br.ret.sptk rp -.endp simple diff --git a/gas/testsuite/gas/ia64/unwind.d b/gas/testsuite/gas/ia64/unwin= d.d deleted file mode 100644 index 3f0d2d3f61e..00000000000 --- a/gas/testsuite/gas/ia64/unwind.d +++ /dev/null @@ -1,28 +0,0 @@ -#readelf: -S -T -#name: ia64 unwind section - -There are 9 section headers, starting at offset .*: - -Section Headers: - \[Nr\] Name Type Address Offset - Size EntSize Flags Link Info Align - \[ 0\] NULL 0000000000000000 00000000 - 0000000000000000 0000000000000000 0 0 0 - \[ 1\] \.text PROGBITS 0000000000000000 00000040 - 0000000000000000 0000000000000000 AX 0 0 16 - \[ 2\] \.data PROGBITS 0000000000000000 00000040 - 0000000000000000 0000000000000000 WA 0 0 1 - \[ 3\] \.bss NOBITS 0000000000000000 00000040 - 0000000000000000 0000000000000000 WA 0 0 1 - \[ 4\] \.IA_64\.unwind_inf PROGBITS 0000000000000000 00000040 - 0000000000000008 0000000000000000 A 0 0 8 - \[ 5\] \.IA_64\.unwind IA_64_UNWIND 0000000000000000 00000048 - 0000000000000008 0000000000000000 AL 1 1 8 - \[ 6\] \.symtab SYMTAB 0000000000000000 .* - 0000000000000090 0000000000000018 7 6 8 - \[ 7\] \.strtab STRTAB 0000000000000000 .* - 0000000000000001 0000000000000000 0 0 1 - \[ 8\] \.shstrtab STRTAB 0000000000000000 [0-9a-f]+ - 000000000000004d 0000000000000000 0 0 1 -Key to Flags: -#... diff --git a/gas/testsuite/gas/ia64/unwind.s b/gas/testsuite/gas/ia64/unwin= d.s deleted file mode 100644 index a8c2be0242b..00000000000 --- a/gas/testsuite/gas/ia64/unwind.s +++ /dev/null @@ -1,4 +0,0 @@ - .section .IA_64.unwind_info, "a", "progbits" - data8 1234 - .section .IA_64.unwind, "ao", "unwind" - data8 1234 diff --git a/gas/testsuite/gas/ia64/xdata-ilp32.d b/gas/testsuite/gas/ia64/= xdata-ilp32.d deleted file mode 100644 index e5dd507c5bf..00000000000 --- a/gas/testsuite/gas/ia64/xdata-ilp32.d +++ /dev/null @@ -1,29 +0,0 @@ -#readelf: -S -#name: ia64 xdata (ilp32) -#as: -milp32 -#source: xdata.s - -There are 19 section headers, starting at offset 0x[[:xdigit:]]+: - -Section Headers: - \[Nr\] Name Type Addr Off Size ES Flg L= k Inf Al - \[ 0\] NULL 00000000 000000 000000 00 = 0 0 0 - \[ 1\] .text PROGBITS 00000000 [[:xdigit:]]+ 000000 0= 0 AX 0 0 16 - \[ 2\] .data PROGBITS 00000000 [[:xdigit:]]+ 000000 0= 0 WA 0 0 1 - \[ 3\] .bss NOBITS 00000000 [[:xdigit:]]+ 000000 0= 0 WA 0 0 1 - \[ 4\] \.xdata1 PROGBITS 00000000 [[:xdigit:]]+ 000001 = 00 A 0 0 1 - \[ 5\] \.xdata2 PROGBITS 00000000 [[:xdigit:]]+ 000004 = 00 A 0 0 2 - \[ 6\] ,xdata3 PROGBITS 00000000 [[:xdigit:]]+ 000008 0= 0 A 0 0 4 - \[ 7\] \.xdata,4 PROGBITS 00000000 [[:xdigit:]]+ 000010 = 00 A 0 0 8 - \[ 8\] "\.xdata5" PROGBITS 00000000 [[:xdigit:]]+ 000020 = 00 A 0 0 16 - \[ 9\] \.rela"\.xdata5" RELA 00000000 [[:xdigit:]]+ 000018= 0c I 17 8 4 - \[10\] \.xreal\\1 PROGBITS 00000000 [[:xdigit:]]+ 000008= 00 A 0 0 4 - \[11\] \.xreal\+2 PROGBITS 00000000 [[:xdigit:]]+ 000010= 00 A 0 0 8 - \[12\] \.xreal\(3\) PROGBITS 00000000 [[:xdigit:]]+ 00001= 4 00 A 0 0 16 - \[13\] \.xreal\[4\] PROGBITS 00000000 [[:xdigit:]]+ 00002= 0 00 A 0 0 16 - \[14\] \.xstr<1> PROGBITS 00000000 [[:xdigit:]]+ 000003 = 00 A 0 0 1 - \[15\] \.xstr\{2\} PROGBITS 00000000 [[:xdigit:]]+ 00000= 4 00 A 0 0 1 - \[16\] .symtab SYMTAB 00000000 [[:xdigit:]]+ [[:xdigi= t:]]+ 10 17 15 4 - \[17\] .strtab STRTAB 00000000 [[:xdigit:]]+ [[:xdigi= t:]]+ 00 0 0 1 - \[18\] .shstrtab STRTAB 00000000 [[:xdigit:]]+ [[:xdigi= t:]]+ 00 0 0 1 -#pass diff --git a/gas/testsuite/gas/ia64/xdata.d b/gas/testsuite/gas/ia64/xdata.d deleted file mode 100644 index 67276898c58..00000000000 --- a/gas/testsuite/gas/ia64/xdata.d +++ /dev/null @@ -1,47 +0,0 @@ -#readelf: -S -#name: ia64 xdata - -There are 19 section headers, starting at offset 0x[[:xdigit:]]+: - -Section Headers: - \[Nr\] Name Type Address Offset - Size EntSize Flags Link Info Align - \[ 0\] NULL 0000000000000000 [[:xdigit:]]+ - 0000000000000000 0000000000000000 0 0 0 - \[ 1\] \.text PROGBITS 0000000000000000 [[:xdigit:]= ]+ - 0000000000000000 0000000000000000 AX 0 0 16 - \[ 2\] \.data PROGBITS 0000000000000000 [[:xdigit:]= ]+ - 0000000000000000 0000000000000000 WA 0 0 1 - \[ 3\] \.bss NOBITS 0000000000000000 [[:xdigit:]= ]+ - 0000000000000000 0000000000000000 WA 0 0 1 - \[ 4\] \.xdata1 PROGBITS 0000000000000000 [[:xdigit:]= ]+ - 0000000000000001 0000000000000000 A 0 0 1 - \[ 5\] \.xdata2 PROGBITS 0000000000000000 [[:xdigit:]= ]+ - 0000000000000004 0000000000000000 A 0 0 2 - \[ 6\] ,xdata3 PROGBITS 0000000000000000 [[:xdigit:]]+ - 0000000000000008 0000000000000000 A 0 0 4 - \[ 7\] \.xdata,4 PROGBITS 0000000000000000 [[:xdigit:]= ]+ - 0000000000000010 0000000000000000 A 0 0 8 - \[ 8\] "\.xdata5" PROGBITS 0000000000000000 [[:xdigit:]= ]+ - 0000000000000020 0000000000000000 A 0 0 16 - \[ 9\] \.rela"\.xdata5" RELA 0000000000000000 [[:xdigit:= ]]+ - 0000000000000030 0000000000000018 I 16 8 8 - \[10\] \.xreal\\1 PROGBITS 0000000000000000 [[:xdigit:= ]]+ - 0000000000000008 0000000000000000 A 0 0 4 - \[11\] \.xreal\+2 PROGBITS 0000000000000000 [[:xdigit:= ]]+ - 0000000000000010 0000000000000000 A 0 0 8 - \[12\] \.xreal\(3\) PROGBITS 0000000000000000 [[:xdigit= :]]+ - 0000000000000014 0000000000000000 A 0 0 16 - \[13\] \.xreal\[4\] PROGBITS 0000000000000000 [[:xdigit= :]]+ - 0000000000000020 0000000000000000 A 0 0 16 - \[14\] \.xstr<1> PROGBITS 0000000000000000 [[:xdigit:]= ]+ - 0000000000000003 0000000000000000 A 0 0 1 - \[15\] \.xstr\{2\} PROGBITS 0000000000000000 [[:xdigit= :]]+ - 0000000000000004 0000000000000000 A 0 0 1 - \[16\] \.symtab SYMTAB 0000000000000000 [[:xdigit:]= ]+ - [[:xdigit:]]+ 0000000000000018 17 15 8 - \[17\] \.strtab STRTAB 0000000000000000 [[:xdigit:]= ]+ - [[:xdigit:]]+ 0000000000000000 0 0 1 - \[18\] \.shstrtab STRTAB 0000000000000000 [[:xdigit:]= ]+ - [[:xdigit:]]+ 0000000000000000 0 0 1 -#pass diff --git a/gas/testsuite/gas/ia64/xdata.s b/gas/testsuite/gas/ia64/xdata.s deleted file mode 100644 index 6929405f4fc..00000000000 --- a/gas/testsuite/gas/ia64/xdata.s +++ /dev/null @@ -1,45 +0,0 @@ -// Note that most of the section names used here aren't legal as operands -// to either .section or .xdata/.xreal/.xstring (quoted strings aren't in -// general), but since generic code accepts them for .section we also test -// this here for our target specific directives. This could be viewed as a -// shortcut of a pair of .section/.secalias for each of them. - -.section .xdata1, "a", @progbits -.section ".xdata2", "a", @progbits -.section ",xdata3", "a", @progbits -.section ".xdata,4", "a", @progbits -.section "\".xdata5\"", "a", @progbits - -.section ".xreal\\1", "a", @progbits -.section ".xreal+2", "a", @progbits -.section ".xreal(3)", "a", @progbits -.section ".xreal[4]", "a", @progbits - -.section ".xstr<1>", "a", @progbits -.section ".xstr{2}", "a", @progbits - -.text - -.xdata1 .xdata1, 1 -.xdata2 ".xdata2", 2 -.xdata4 ",xdata3", 3 -.xdata8 ".xdata,4", 4 -.xdata16 "\".xdata5\"", @iplt(_start) - -.xdata2.ua ".xdata2", 2 -.xdata4.ua ",xdata3", 3 -.xdata8.ua ".xdata,4", 4 -.xdata16.ua "\".xdata5\"", @iplt(_start) - -.xreal4 ".xreal\\1", 1 -.xreal8 ".xreal+2", 2 -.xreal10 ".xreal(3)", 3 -.xreal16 ".xreal[4]", 4 - -.xreal4.ua ".xreal\\1", 1 -.xreal8.ua ".xreal+2", 2 -.xreal10.ua ".xreal(3)", 3 -.xreal16.ua ".xreal[4]", 4 - -.xstring ".xstr<1>", "abc" -.xstringz ".xstr{2}", "xyz" diff --git a/gas/testsuite/gas/lns/lns-common-1-ia64.s b/gas/testsuite/gas/= lns/lns-common-1-ia64.s deleted file mode 100644 index 7543be484fa..00000000000 --- a/gas/testsuite/gas/lns/lns-common-1-ia64.s +++ /dev/null @@ -1,18 +0,0 @@ - .file 1 "foo.c" - .loc 1 1 - .explicit - { .mii; nop 0; nop 0; nop 0 ;; } - .loc 1 2 3 - { .mii; nop 0; nop 0; nop 0 ;; } - .loc 1 3 prologue_end - { .mii; nop 0; nop 0; nop 0 ;; } - .loc 1 4 0 epilogue_begin - { .mii; nop 0; nop 0; nop 0 ;; } - .loc 1 5 isa 1 basic_block - { .mii; nop 0; nop 0; nop 0 ;; } - .loc 1 6 is_stmt 0 - { .mii; nop 0; nop 0; nop 0 ;; } - .loc 1 7 is_stmt 1 - { .mii; nop 0; nop 0; nop 0 ;; } - .loc 1 7 discriminator 1 - { .mii; nop 0; nop 0; nop 0 ;; } diff --git a/gas/testsuite/gas/lns/lns.exp b/gas/testsuite/gas/lns/lns.exp index deffca5af83..b497937446e 100644 --- a/gas/testsuite/gas/lns/lns.exp +++ b/gas/testsuite/gas/lns/lns.exp @@ -41,8 +41,6 @@ if { ![istarget s390*-*-*] } { || [istarget xtensa*-*-*] } { run_dump_test "lns-common-1-alt" run_dump_test "lns-big-delta" - } elseif { [istarget ia64*-*-*] } { - run_dump_test "lns-common-1" { { source "lns-common-1-ia64.s" } } } elseif { [istarget or1k*-*-*] } { run_dump_test "lns-common-1" { { source "lns-common-1-or1k.s" } } } elseif { [istarget kvx*-*-*] } { diff --git a/gas/testsuite/gas/symver/symver.exp b/gas/testsuite/gas/symver= /symver.exp index 9cc2cfbf503..2bd00fb8ddc 100644 --- a/gas/testsuite/gas/symver/symver.exp +++ b/gas/testsuite/gas/symver/symver.exp @@ -32,11 +32,6 @@ proc run_error_test { name opts } { =20 # symver is only supported by ELF targets. if { [is_elf_format] } then { - - if {[istarget "ia64-*"]} then { - return - } -=20=20 if {[istarget "hppa*64*-*-*"]} then { return } diff --git a/gas/write.c b/gas/write.c index 18cf18fc830..e3f112ccbc9 100644 --- a/gas/write.c +++ b/gas/write.c @@ -2058,9 +2058,7 @@ maybe_generate_build_notes (void) BFD_RELOC_64, even though it really should. The HPPA backend has a similar issue, although it does not support BFD_RELOCs at all! So we have special case code to handle these targets. */ - if (strstr (bfd_get_target (stdoutput), "-ia64") !=3D NULL) - desc_reloc =3D target_big_endian ? BFD_RELOC_IA64_DIR32MSB : BFD_RELOC_IA= 64_DIR32LSB; - else if (strstr (bfd_get_target (stdoutput), "-hppa") !=3D NULL) + if (strstr (bfd_get_target (stdoutput), "-hppa") !=3D NULL) desc_reloc =3D 80; /* R_PARISC_DIR64. */ else desc_reloc =3D BFD_RELOC_64; diff --git a/gnulib/configure b/gnulib/configure index cc7e8287d5a..1143c08f679 100755 --- a/gnulib/configure +++ b/gnulib/configure @@ -27699,7 +27699,7 @@ int main () result |=3D 1; } =20 -#if ((defined __ia64 && LDBL_MANT_DIG =3D=3D 64) || (defined __x86_64__ ||= defined __amd64__) || (defined __i386 || defined __i386__ || defined _I386= || defined _M_IX86 || defined _X86_)) && !HAVE_SAME_LONG_DOUBLE_AS_DOUBLE +#if ((defined __x86_64__ || defined __amd64__) || (defined __i386 || defin= ed __i386__ || defined _I386 || defined _M_IX86 || defined _X86_)) && !HAVE= _SAME_LONG_DOUBLE_AS_DOUBLE /* Representation of an 80-bit 'long double' as an initializer for a seque= nce of 'unsigned int' words. */ # ifdef WORDS_BIGENDIAN @@ -33386,7 +33386,6 @@ else || (defined __APPLE__ && defined __MACH__ \ ? 4 < __GNUC__ + (1 <=3D __GNUC_MINOR__) \ : __GNUC__) \ - || (__ia64 && (61200 <=3D __HP_cc || 61200 <=3D __HP_aCC)= ) \ || __ICC || 0x590 <=3D __SUNPRO_C || 0x0600 <=3D __xlC__ \ || 1300 <=3D _MSC_VER) struct alignas_test { char c; char alignas (8) alignas_8; }; diff --git a/gnulib/import/isnan.c b/gnulib/import/isnan.c index bd119f691c1..7a912372b38 100644 --- a/gnulib/import/isnan.c +++ b/gnulib/import/isnan.c @@ -94,7 +94,7 @@ int FUNC (DOUBLE x) { #if defined KNOWN_EXPBIT0_LOCATION && IEEE_FLOATING_POINT -# if defined USE_LONG_DOUBLE && ((defined __ia64 && LDBL_MANT_DIG =3D=3D 6= 4) || (defined __x86_64__ || defined __amd64__) || (defined __i386 || defin= ed __i386__ || defined _I386 || defined _M_IX86 || defined _X86_)) && !HAVE= _SAME_LONG_DOUBLE_AS_DOUBLE +# if defined USE_LONG_DOUBLE && ((defined __x86_64__ || defined __amd64__)= || (defined __i386 || defined __i386__ || defined _I386 || defined _M_IX86= || defined _X86_)) && !HAVE_SAME_LONG_DOUBLE_AS_DOUBLE /* Special CPU dependent code is needed to treat bit patterns outside the IEEE 754 specification (such as Pseudo-NaNs, Pseudo-Infinities, Pseudo-Zeroes, Unnormalized Numbers, and Pseudo-Denormals) as NaNs. @@ -169,7 +169,7 @@ FUNC (DOUBLE x) handle only the quiet NaNs. */ if (x =3D=3D x) { -# if defined USE_LONG_DOUBLE && ((defined __ia64 && LDBL_MANT_DIG =3D=3D 6= 4) || (defined __x86_64__ || defined __amd64__) || (defined __i386 || defin= ed __i386__ || defined _I386 || defined _M_IX86 || defined _X86_)) && !HAVE= _SAME_LONG_DOUBLE_AS_DOUBLE +# if defined USE_LONG_DOUBLE && ((defined __x86_64__ || defined __amd64__)= || (defined __i386 || defined __i386__ || defined _I386 || defined _M_IX86= || defined _X86_)) && !HAVE_SAME_LONG_DOUBLE_AS_DOUBLE /* Detect any special bit patterns that pass =3D=3D; see comment abo= ve. */ memory_double m1; memory_double m2; diff --git a/gnulib/import/m4/isnanl.m4 b/gnulib/import/m4/isnanl.m4 index fa49a644fec..bef1412acfc 100644 --- a/gnulib/import/m4/isnanl.m4 +++ b/gnulib/import/m4/isnanl.m4 @@ -168,7 +168,7 @@ int main () result |=3D 1; } =20 -#if ((defined __ia64 && LDBL_MANT_DIG =3D=3D 64) || (defined __x86_64__ ||= defined __amd64__) || (defined __i386 || defined __i386__ || defined _I386= || defined _M_IX86 || defined _X86_)) && !HAVE_SAME_LONG_DOUBLE_AS_DOUBLE +#if ((defined __x86_64__ || defined __amd64__) || (defined __i386 || defin= ed __i386__ || defined _I386 || defined _M_IX86 || defined _X86_)) && !HAVE= _SAME_LONG_DOUBLE_AS_DOUBLE /* Representation of an 80-bit 'long double' as an initializer for a seque= nce of 'unsigned int' words. */ # ifdef WORDS_BIGENDIAN diff --git a/gnulib/import/m4/stdalign.m4 b/gnulib/import/m4/stdalign.m4 index 78577cb2acc..9cd67262076 100644 --- a/gnulib/import/m4/stdalign.m4 +++ b/gnulib/import/m4/stdalign.m4 @@ -37,7 +37,6 @@ AC_DEFUN([gl_STDALIGN_H], || (defined __APPLE__ && defined __MACH__ \ ? 4 < __GNUC__ + (1 <=3D __GNUC_MINOR__) \ : __GNUC__) \ - || (__ia64 && (61200 <=3D __HP_cc || 61200 <=3D __HP_aCC)= ) \ || __ICC || 0x590 <=3D __SUNPRO_C || 0x0600 <=3D __xlC__ \ || 1300 <=3D _MSC_VER) struct alignas_test { char c; char alignas (8) alignas_8; }; diff --git a/gnulib/import/stdalign.in.h b/gnulib/import/stdalign.in.h index 3b117df11fe..255a08f9e9b 100644 --- a/gnulib/import/stdalign.in.h +++ b/gnulib/import/stdalign.in.h @@ -109,7 +109,6 @@ ? 4 < __GNUC__ + (1 <=3D __GNUC_MINOR__) \ : __GNUC__ && !defined __ibmxl__) \ || (4 <=3D __clang_major__) \ - || (__ia64 && (61200 <=3D __HP_cc || 61200 <=3D __HP_aCC)) \ || __ICC || 0x590 <=3D __SUNPRO_C || 0x0600 <=3D __xlC__)) # define _Alignas(a) __attribute__ ((__aligned__ (a))) # elif 1300 <=3D _MSC_VER diff --git a/gprof/configure b/gprof/configure index 6c9d8701c48..f0f258918a7 100755 --- a/gprof/configure +++ b/gprof/configure @@ -5540,10 +5540,6 @@ haiku*) hpux10.20* | hpux11*) lt_cv_file_magic_cmd=3D/usr/bin/file case $host_cpu in - ia64*) - lt_cv_deplibs_check_method=3D'file_magic (s[0-9][0-9][0-9]|ELF-[0-9][0= -9]) shared object file - IA64' - lt_cv_file_magic_test_file=3D/usr/lib/hpux32/libc.so - ;; hppa*64*) lt_cv_deplibs_check_method=3D'file_magic (s[0-9][0-9][0-9]|ELF[ -][0-9= ][0-9])(-bit)?( [LM]SB)? shared object( file)?[, -]* PA-RISC [0-9]\.[0-9]' lt_cv_file_magic_test_file=3D/usr/lib/pa20_64/libc.sl @@ -6102,11 +6098,6 @@ aix*) cygwin* | mingw* | pw32* | cegcc*) symcode=3D'[ABCDGISTW]' ;; -hpux*) - if test "$host_cpu" =3D ia64; then - symcode=3D'[ABCDEGRST]' - fi - ;; irix* | nonstopux*) symcode=3D'[BCDEGRST]' ;; @@ -6137,7 +6128,7 @@ case `$NM -V 2>&1` in esac =20 # Transform an extracted symbol line into a proper C declaration. -# Some systems (esp. on ia64) link data and code symbols differently, +# Some systems link data and code symbols differently, # so use this general approach. lt_cv_sys_global_symbol_to_cdecl=3D"sed -n -e 's/^T .* \(.*\)$/extern int = \1();/p' -e 's/^$symcode* .* \(.*\)$/extern char \1;/p'" =20 @@ -6337,25 +6328,6 @@ test "x$enable_libtool_lock" !=3D xno && enable_libt= ool_lock=3Dyes # Some flags need to be propagated to the compiler or linker for good # libtool support. case $host in -ia64-*-hpux*) - # Find out which ABI we are using. - echo 'int i;' > conftest.$ac_ext - if { { eval echo "\"\$as_me\":${as_lineno-$LINENO}: \"$ac_compile\""; } = >&5 - (eval $ac_compile) 2>&5 - ac_status=3D$? - $as_echo "$as_me:${as_lineno-$LINENO}: \$? =3D $ac_status" >&5 - test $ac_status =3D 0; }; then - case `/usr/bin/file conftest.$ac_objext` in - *ELF-32*) - HPUX_IA64_MODE=3D"32" - ;; - *ELF-64*) - HPUX_IA64_MODE=3D"64" - ;; - esac - fi - rm -rf conftest* - ;; *-*-irix6*) # Find out which ABI we are using. echo '#line '$LINENO' "configure"' > conftest.$ac_ext @@ -7690,10 +7662,6 @@ $as_echo_n "checking for $compiler option to produce= PIC... " >&6; } case $host_os in aix*) # All AIX code is PIC. - if test "$host_cpu" =3D ia64; then - # AIX 5 now supports IA64 processor - lt_prog_compiler_static=3D'-Bstatic' - fi lt_prog_compiler_pic=3D'-fPIC' ;; =20 @@ -7790,12 +7758,7 @@ $as_echo_n "checking for $compiler option to produce= PIC... " >&6; } case $host_os in aix*) lt_prog_compiler_wl=3D'-Wl,' - if test "$host_cpu" =3D ia64; then - # AIX 5 now supports IA64 processor - lt_prog_compiler_static=3D'-Bstatic' - else - lt_prog_compiler_static=3D'-bnso -bI:/lib/syscalls.exp' - fi + lt_prog_compiler_static=3D'-bnso -bI:/lib/syscalls.exp' ;; =20 mingw* | cygwin* | pw32* | os2* | cegcc*) @@ -7809,7 +7772,7 @@ $as_echo_n "checking for $compiler option to produce = PIC... " >&6; } # PIC is the default for IA64 HP-UX and 64-bit HP-UX, but # not for PA HP-UX. case $host_cpu in - hppa*64*|ia64*) + hppa*64*) # +Z the default ;; *) @@ -8334,7 +8297,6 @@ $as_echo_n "checking whether the $compiler linker ($L= D) supports shared librarie case $host_os in aix[3-9]*) # On AIX/PPC, the GNU linker is very broken - if test "$host_cpu" !=3D ia64; then ld_shlibs=3Dno cat <<_LT_EOF 1>&2 =20 @@ -8346,7 +8308,6 @@ $as_echo_n "checking whether the $compiler linker ($L= D) supports shared librarie *** You will then need to restart the configuration process. =20 _LT_EOF - fi ;; =20 amigaos*) @@ -8442,10 +8403,6 @@ _LT_EOF # Portland Group f77 and f90 compilers whole_archive_flag_spec=3D'${wl}--whole-archive`for conv in $convenienc= e\"\"; do test -n \"$conv\" && new_convenience=3D\"$new_convenience,$conv\= "; done; func_echo_all \"$new_convenience\"` ${wl}--no-whole-archive' tmp_addflag=3D' $pic_flag -Mnomain' ;; - ecc*,ia64* | icc*,ia64*) # Intel C compiler on ia64 - tmp_addflag=3D' -i_dynamic' ;; - efc*,ia64* | ifort*,ia64*) # Intel Fortran compiler on ia64 - tmp_addflag=3D' -i_dynamic -nofor_main' ;; ifc* | ifort*) # Intel Fortran compiler tmp_addflag=3D' -nofor_main' ;; lf95*) # Lahey Fortran 8.1 @@ -8599,13 +8556,6 @@ _LT_EOF ;; =20 aix[4-9]*) - if test "$host_cpu" =3D ia64; then - # On IA64, the linker does run time linking by default, so we don't - # have to do anything special. - aix_use_runtimelinking=3Dno - exp_sym_flag=3D'-Bexport' - no_entry_flag=3D"" - else # If we're using GNU nm, then we don't want the "-C" option. # -C means demangle to AIX nm, but means don't demangle with GNU nm # Also, AIX nm treats weak defined symbols like other global @@ -8632,7 +8582,6 @@ _LT_EOF =20 exp_sym_flag=3D'-bexport' no_entry_flag=3D'-bnoentry' - fi =20 # When large executables or shared objects are built, AIX ld can # have problems creating the table of contents. If linking a library @@ -8675,17 +8624,11 @@ _LT_EOF fi else # not using gcc - if test "$host_cpu" =3D ia64; then - # VisualAge C++, Version 5.5 for AIX 5L for IA-64, Beta 3 Release - # chokes on -Wl,-G. The following line is correct: - shared_flag=3D'-G' - else if test "$aix_use_runtimelinking" =3D yes; then shared_flag=3D'${wl}-G' else shared_flag=3D'${wl}-bM:SRE' fi - fi fi =20 export_dynamic_flag_spec=3D'${wl}-bexpall' @@ -8731,11 +8674,6 @@ if test -z "$aix_libpath"; then aix_libpath=3D"/usr/= lib:/lib"; fi hardcode_libdir_flag_spec=3D'${wl}-blibpath:$libdir:'"$aix_libpath" archive_expsym_cmds=3D'$CC -o $output_objdir/$soname $libobjs $dep= libs '"\${wl}$no_entry_flag"' $compiler_flags `if test "x${allow_undefined_= flag}" !=3D "x"; then func_echo_all "${wl}${allow_undefined_flag}"; else :;= fi` '"\${wl}$exp_sym_flag:\$export_symbols $shared_flag" else - if test "$host_cpu" =3D ia64; then - hardcode_libdir_flag_spec=3D'${wl}-R $libdir:/usr/lib:/lib' - allow_undefined_flag=3D"-z nodefs" - archive_expsym_cmds=3D"\$CC $shared_flag"' -o $output_objdir/$soname $l= ibobjs $deplibs '"\${wl}$no_entry_flag"' $compiler_flags ${wl}${allow_undef= ined_flag} '"\${wl}$exp_sym_flag:\$export_symbols" - else # Determine the default libpath from the value encoded in an # empty executable. cat confdefs.h - <<_ACEOF >conftest.$ac_ext @@ -8783,7 +8721,6 @@ if test -z "$aix_libpath"; then aix_libpath=3D"/usr/l= ib:/lib"; fi archive_cmds_need_lc=3Dyes # This is similar to how AIX traditionally builds its shared libraries. archive_expsym_cmds=3D"\$CC $shared_flag"' -o $output_objdir/$soname $l= ibobjs $deplibs ${wl}-bnoentry $compiler_flags ${wl}-bE:$export_symbols${al= low_undefined_flag}~$AR $AR_FLAGS $output_objdir/$libname$release.a $output= _objdir/$soname' - fi fi ;; =20 @@ -8932,9 +8869,6 @@ if test -z "$aix_libpath"; then aix_libpath=3D"/usr/l= ib:/lib"; fi hppa*64*) archive_cmds=3D'$CC -shared ${wl}+h ${wl}$soname ${wl}+nodefaultrpath -= o $lib $libobjs $deplibs $compiler_flags' ;; - ia64*) - archive_cmds=3D'$CC -shared -fPIC ${wl}+h ${wl}$soname ${wl}+nodefaultr= path -o $lib $libobjs $deplibs $compiler_flags' - ;; *) archive_cmds=3D'$CC -shared -fPIC ${wl}+h ${wl}$soname ${wl}+b ${wl}$in= stall_libdir -o $lib $libobjs $deplibs $compiler_flags' ;; @@ -8944,9 +8878,6 @@ if test -z "$aix_libpath"; then aix_libpath=3D"/usr/l= ib:/lib"; fi hppa*64*) archive_cmds=3D'$CC -b ${wl}+h ${wl}$soname ${wl}+nodefaultrpath -o $li= b $libobjs $deplibs $compiler_flags' ;; - ia64*) - archive_cmds=3D'$CC -b ${wl}+h ${wl}$soname ${wl}+nodefaultrpath -o $li= b $libobjs $deplibs $compiler_flags' - ;; *) =20 # Older versions of the 11.00 compiler do not understand -b yet @@ -8996,7 +8927,7 @@ fi hardcode_libdir_separator=3D: =20 case $host_cpu in - hppa*64*|ia64*) + hppa*64*) hardcode_direct=3Dno hardcode_shlibpath_var=3Dno ;; @@ -9633,11 +9564,6 @@ aix[4-9]*) need_lib_prefix=3Dno need_version=3Dno hardcode_into_libs=3Dyes - if test "$host_cpu" =3D ia64; then - # AIX 5 supports IA64 - library_names_spec=3D'${libname}${release}${shared_ext}$major ${libnam= e}${release}${shared_ext}$versuffix $libname${shared_ext}' - shlibpath_var=3DLD_LIBRARY_PATH - else # With GCC up to 2.95.x, collect2 would create an import file # for dependence libraries. The import file would start with # the line `#! .'. This would cause the generated library to @@ -9669,7 +9595,6 @@ aix[4-9]*) soname_spec=3D'${libname}${release}${shared_ext}$major' fi shlibpath_var=3DLIBPATH - fi ;; =20 amigaos*) @@ -9846,21 +9771,6 @@ hpux9* | hpux10* | hpux11*) need_lib_prefix=3Dno need_version=3Dno case $host_cpu in - ia64*) - shrext_cmds=3D'.so' - hardcode_into_libs=3Dyes - dynamic_linker=3D"$host_os dld.so" - shlibpath_var=3DLD_LIBRARY_PATH - shlibpath_overrides_runpath=3Dyes # Unless +noenvvar is specified. - library_names_spec=3D'${libname}${release}${shared_ext}$versuffix ${li= bname}${release}${shared_ext}$major $libname${shared_ext}' - soname_spec=3D'${libname}${release}${shared_ext}$major' - if test "X$HPUX_IA64_MODE" =3D X32; then - sys_lib_search_path_spec=3D"/usr/lib/hpux32 /usr/local/lib/hpux32 /u= sr/local/lib" - else - sys_lib_search_path_spec=3D"/usr/lib/hpux64 /usr/local/lib/hpux64" - fi - sys_lib_dlsearch_path_spec=3D$sys_lib_search_path_spec - ;; hppa*64*) shrext_cmds=3D'.sl' hardcode_into_libs=3Dyes @@ -10951,7 +10861,7 @@ $as_echo_n "checking whether to build shared librar= ies... " >&6; } ;; =20 aix[4-9]*) - if test "$host_cpu" !=3D ia64 && test "$aix_use_runtimelinking" =3D no= ; then + if test "$aix_use_runtimelinking" =3D no ; then test "$enable_shared" =3D yes && enable_static=3Dno fi ;; diff --git a/gprofng/configure b/gprofng/configure index 17d1c500830..8db1d5ac53a 100755 --- a/gprofng/configure +++ b/gprofng/configure @@ -7162,10 +7162,6 @@ haiku*) hpux10.20* | hpux11*) lt_cv_file_magic_cmd=3D/usr/bin/file case $host_cpu in - ia64*) - lt_cv_deplibs_check_method=3D'file_magic (s[0-9][0-9][0-9]|ELF-[0-9][0= -9]) shared object file - IA64' - lt_cv_file_magic_test_file=3D/usr/lib/hpux32/libc.so - ;; hppa*64*) lt_cv_deplibs_check_method=3D'file_magic (s[0-9][0-9][0-9]|ELF[ -][0-9= ][0-9])(-bit)?( [LM]SB)? shared object( file)?[, -]* PA-RISC [0-9]\.[0-9]' lt_cv_file_magic_test_file=3D/usr/lib/pa20_64/libc.sl @@ -7724,11 +7720,6 @@ aix*) cygwin* | mingw* | pw32* | cegcc*) symcode=3D'[ABCDGISTW]' ;; -hpux*) - if test "$host_cpu" =3D ia64; then - symcode=3D'[ABCDEGRST]' - fi - ;; irix* | nonstopux*) symcode=3D'[BCDEGRST]' ;; @@ -7759,7 +7750,7 @@ case `$NM -V 2>&1` in esac =20 # Transform an extracted symbol line into a proper C declaration. -# Some systems (esp. on ia64) link data and code symbols differently, +# Some systems link data and code symbols differently, # so use this general approach. lt_cv_sys_global_symbol_to_cdecl=3D"sed -n -e 's/^T .* \(.*\)$/extern int = \1();/p' -e 's/^$symcode* .* \(.*\)$/extern char \1;/p'" =20 @@ -7959,25 +7950,6 @@ test "x$enable_libtool_lock" !=3D xno && enable_libt= ool_lock=3Dyes # Some flags need to be propagated to the compiler or linker for good # libtool support. case $host in -ia64-*-hpux*) - # Find out which ABI we are using. - echo 'int i;' > conftest.$ac_ext - if { { eval echo "\"\$as_me\":${as_lineno-$LINENO}: \"$ac_compile\""; } = >&5 - (eval $ac_compile) 2>&5 - ac_status=3D$? - $as_echo "$as_me:${as_lineno-$LINENO}: \$? =3D $ac_status" >&5 - test $ac_status =3D 0; }; then - case `/usr/bin/file conftest.$ac_objext` in - *ELF-32*) - HPUX_IA64_MODE=3D"32" - ;; - *ELF-64*) - HPUX_IA64_MODE=3D"64" - ;; - esac - fi - rm -rf conftest* - ;; *-*-irix6*) # Find out which ABI we are using. echo '#line '$LINENO' "configure"' > conftest.$ac_ext @@ -9283,10 +9255,6 @@ $as_echo_n "checking for $compiler option to produce= PIC... " >&6; } case $host_os in aix*) # All AIX code is PIC. - if test "$host_cpu" =3D ia64; then - # AIX 5 now supports IA64 processor - lt_prog_compiler_static=3D'-Bstatic' - fi lt_prog_compiler_pic=3D'-fPIC' ;; =20 @@ -9383,12 +9351,7 @@ $as_echo_n "checking for $compiler option to produce= PIC... " >&6; } case $host_os in aix*) lt_prog_compiler_wl=3D'-Wl,' - if test "$host_cpu" =3D ia64; then - # AIX 5 now supports IA64 processor - lt_prog_compiler_static=3D'-Bstatic' - else - lt_prog_compiler_static=3D'-bnso -bI:/lib/syscalls.exp' - fi + lt_prog_compiler_static=3D'-bnso -bI:/lib/syscalls.exp' ;; =20 mingw* | cygwin* | pw32* | os2* | cegcc*) @@ -9402,7 +9365,7 @@ $as_echo_n "checking for $compiler option to produce = PIC... " >&6; } # PIC is the default for IA64 HP-UX and 64-bit HP-UX, but # not for PA HP-UX. case $host_cpu in - hppa*64*|ia64*) + hppa*64*) # +Z the default ;; *) @@ -9927,7 +9890,6 @@ $as_echo_n "checking whether the $compiler linker ($L= D) supports shared librarie case $host_os in aix[3-9]*) # On AIX/PPC, the GNU linker is very broken - if test "$host_cpu" !=3D ia64; then ld_shlibs=3Dno cat <<_LT_EOF 1>&2 =20 @@ -9939,7 +9901,6 @@ $as_echo_n "checking whether the $compiler linker ($L= D) supports shared librarie *** You will then need to restart the configuration process. =20 _LT_EOF - fi ;; =20 amigaos*) @@ -10035,10 +9996,6 @@ _LT_EOF # Portland Group f77 and f90 compilers whole_archive_flag_spec=3D'${wl}--whole-archive`for conv in $convenienc= e\"\"; do test -n \"$conv\" && new_convenience=3D\"$new_convenience,$conv\= "; done; func_echo_all \"$new_convenience\"` ${wl}--no-whole-archive' tmp_addflag=3D' $pic_flag -Mnomain' ;; - ecc*,ia64* | icc*,ia64*) # Intel C compiler on ia64 - tmp_addflag=3D' -i_dynamic' ;; - efc*,ia64* | ifort*,ia64*) # Intel Fortran compiler on ia64 - tmp_addflag=3D' -i_dynamic -nofor_main' ;; ifc* | ifort*) # Intel Fortran compiler tmp_addflag=3D' -nofor_main' ;; lf95*) # Lahey Fortran 8.1 @@ -10192,13 +10149,6 @@ _LT_EOF ;; =20 aix[4-9]*) - if test "$host_cpu" =3D ia64; then - # On IA64, the linker does run time linking by default, so we don't - # have to do anything special. - aix_use_runtimelinking=3Dno - exp_sym_flag=3D'-Bexport' - no_entry_flag=3D"" - else # If we're using GNU nm, then we don't want the "-C" option. # -C means demangle to AIX nm, but means don't demangle with GNU nm # Also, AIX nm treats weak defined symbols like other global @@ -10225,7 +10175,6 @@ _LT_EOF =20 exp_sym_flag=3D'-bexport' no_entry_flag=3D'-bnoentry' - fi =20 # When large executables or shared objects are built, AIX ld can # have problems creating the table of contents. If linking a library @@ -10268,17 +10217,11 @@ _LT_EOF fi else # not using gcc - if test "$host_cpu" =3D ia64; then - # VisualAge C++, Version 5.5 for AIX 5L for IA-64, Beta 3 Release - # chokes on -Wl,-G. The following line is correct: - shared_flag=3D'-G' - else if test "$aix_use_runtimelinking" =3D yes; then shared_flag=3D'${wl}-G' else shared_flag=3D'${wl}-bM:SRE' fi - fi fi =20 export_dynamic_flag_spec=3D'${wl}-bexpall' @@ -10324,11 +10267,6 @@ if test -z "$aix_libpath"; then aix_libpath=3D"/us= r/lib:/lib"; fi hardcode_libdir_flag_spec=3D'${wl}-blibpath:$libdir:'"$aix_libpath" archive_expsym_cmds=3D'$CC -o $output_objdir/$soname $libobjs $dep= libs '"\${wl}$no_entry_flag"' $compiler_flags `if test "x${allow_undefined_= flag}" !=3D "x"; then func_echo_all "${wl}${allow_undefined_flag}"; else :;= fi` '"\${wl}$exp_sym_flag:\$export_symbols $shared_flag" else - if test "$host_cpu" =3D ia64; then - hardcode_libdir_flag_spec=3D'${wl}-R $libdir:/usr/lib:/lib' - allow_undefined_flag=3D"-z nodefs" - archive_expsym_cmds=3D"\$CC $shared_flag"' -o $output_objdir/$soname $l= ibobjs $deplibs '"\${wl}$no_entry_flag"' $compiler_flags ${wl}${allow_undef= ined_flag} '"\${wl}$exp_sym_flag:\$export_symbols" - else # Determine the default libpath from the value encoded in an # empty executable. cat confdefs.h - <<_ACEOF >conftest.$ac_ext @@ -10376,7 +10314,6 @@ if test -z "$aix_libpath"; then aix_libpath=3D"/usr= /lib:/lib"; fi archive_cmds_need_lc=3Dyes # This is similar to how AIX traditionally builds its shared libraries. archive_expsym_cmds=3D"\$CC $shared_flag"' -o $output_objdir/$soname $l= ibobjs $deplibs ${wl}-bnoentry $compiler_flags ${wl}-bE:$export_symbols${al= low_undefined_flag}~$AR $AR_FLAGS $output_objdir/$libname$release.a $output= _objdir/$soname' - fi fi ;; =20 @@ -10525,9 +10462,6 @@ if test -z "$aix_libpath"; then aix_libpath=3D"/usr= /lib:/lib"; fi hppa*64*) archive_cmds=3D'$CC -shared ${wl}+h ${wl}$soname ${wl}+nodefaultrpath -= o $lib $libobjs $deplibs $compiler_flags' ;; - ia64*) - archive_cmds=3D'$CC -shared -fPIC ${wl}+h ${wl}$soname ${wl}+nodefaultr= path -o $lib $libobjs $deplibs $compiler_flags' - ;; *) archive_cmds=3D'$CC -shared -fPIC ${wl}+h ${wl}$soname ${wl}+b ${wl}$in= stall_libdir -o $lib $libobjs $deplibs $compiler_flags' ;; @@ -10537,9 +10471,6 @@ if test -z "$aix_libpath"; then aix_libpath=3D"/usr= /lib:/lib"; fi hppa*64*) archive_cmds=3D'$CC -b ${wl}+h ${wl}$soname ${wl}+nodefaultrpath -o $li= b $libobjs $deplibs $compiler_flags' ;; - ia64*) - archive_cmds=3D'$CC -b ${wl}+h ${wl}$soname ${wl}+nodefaultrpath -o $li= b $libobjs $deplibs $compiler_flags' - ;; *) =20 # Older versions of the 11.00 compiler do not understand -b yet @@ -10589,7 +10520,7 @@ fi hardcode_libdir_separator=3D: =20 case $host_cpu in - hppa*64*|ia64*) + hppa*64*) hardcode_direct=3Dno hardcode_shlibpath_var=3Dno ;; @@ -11226,11 +11157,6 @@ aix[4-9]*) need_lib_prefix=3Dno need_version=3Dno hardcode_into_libs=3Dyes - if test "$host_cpu" =3D ia64; then - # AIX 5 supports IA64 - library_names_spec=3D'${libname}${release}${shared_ext}$major ${libnam= e}${release}${shared_ext}$versuffix $libname${shared_ext}' - shlibpath_var=3DLD_LIBRARY_PATH - else # With GCC up to 2.95.x, collect2 would create an import file # for dependence libraries. The import file would start with # the line `#! .'. This would cause the generated library to @@ -11262,7 +11188,6 @@ aix[4-9]*) soname_spec=3D'${libname}${release}${shared_ext}$major' fi shlibpath_var=3DLIBPATH - fi ;; =20 amigaos*) @@ -11439,21 +11364,6 @@ hpux9* | hpux10* | hpux11*) need_lib_prefix=3Dno need_version=3Dno case $host_cpu in - ia64*) - shrext_cmds=3D'.so' - hardcode_into_libs=3Dyes - dynamic_linker=3D"$host_os dld.so" - shlibpath_var=3DLD_LIBRARY_PATH - shlibpath_overrides_runpath=3Dyes # Unless +noenvvar is specified. - library_names_spec=3D'${libname}${release}${shared_ext}$versuffix ${li= bname}${release}${shared_ext}$major $libname${shared_ext}' - soname_spec=3D'${libname}${release}${shared_ext}$major' - if test "X$HPUX_IA64_MODE" =3D X32; then - sys_lib_search_path_spec=3D"/usr/lib/hpux32 /usr/local/lib/hpux32 /u= sr/local/lib" - else - sys_lib_search_path_spec=3D"/usr/lib/hpux64 /usr/local/lib/hpux64" - fi - sys_lib_dlsearch_path_spec=3D$sys_lib_search_path_spec - ;; hppa*64*) shrext_cmds=3D'.sl' hardcode_into_libs=3Dyes @@ -12544,7 +12454,7 @@ $as_echo_n "checking whether to build shared librar= ies... " >&6; } ;; =20 aix[4-9]*) - if test "$host_cpu" !=3D ia64 && test "$aix_use_runtimelinking" =3D no= ; then + if test "$aix_use_runtimelinking" =3D no ; then test "$enable_shared" =3D yes && enable_static=3Dno fi ;; @@ -13000,13 +12910,6 @@ $as_echo_n "checking whether the $compiler linker = ($LD) supports shared librarie ld_shlibs_CXX=3Dno ;; aix[4-9]*) - if test "$host_cpu" =3D ia64; then - # On IA64, the linker does run time linking by default, so we do= n't - # have to do anything special. - aix_use_runtimelinking=3Dno - exp_sym_flag=3D'-Bexport' - no_entry_flag=3D"" - else aix_use_runtimelinking=3Dno =20 # Test if we are trying to use run time linking or normal @@ -13026,7 +12929,6 @@ $as_echo_n "checking whether the $compiler linker (= $LD) supports shared librarie =20 exp_sym_flag=3D'-bexport' no_entry_flag=3D'-bnoentry' - fi =20 # When large executables or shared objects are built, AIX ld can # have problems creating the table of contents. If linking a libr= ary @@ -13068,17 +12970,11 @@ $as_echo_n "checking whether the $compiler linker= ($LD) supports shared librarie fi else # not using gcc - if test "$host_cpu" =3D ia64; then - # VisualAge C++, Version 5.5 for AIX 5L for IA-64, Beta 3 Release - # chokes on -Wl,-G. The following line is correct: - shared_flag=3D'-G' - else if test "$aix_use_runtimelinking" =3D yes; then shared_flag=3D'${wl}-G' else shared_flag=3D'${wl}-bM:SRE' fi - fi fi =20 export_dynamic_flag_spec_CXX=3D'${wl}-bexpall' @@ -13126,11 +13022,6 @@ if test -z "$aix_libpath"; then aix_libpath=3D"/us= r/lib:/lib"; fi =20 archive_expsym_cmds_CXX=3D'$CC -o $output_objdir/$soname $libobj= s $deplibs '"\${wl}$no_entry_flag"' $compiler_flags `if test "x${allow_unde= fined_flag}" !=3D "x"; then func_echo_all "${wl}${allow_undefined_flag}"; e= lse :; fi` '"\${wl}$exp_sym_flag:\$export_symbols $shared_flag" else - if test "$host_cpu" =3D ia64; then - hardcode_libdir_flag_spec_CXX=3D'${wl}-R $libdir:/usr/lib:/lib' - allow_undefined_flag_CXX=3D"-z nodefs" - archive_expsym_cmds_CXX=3D"\$CC $shared_flag"' -o $output_objdir/$son= ame $libobjs $deplibs '"\${wl}$no_entry_flag"' $compiler_flags ${wl}${allow= _undefined_flag} '"\${wl}$exp_sym_flag:\$export_symbols" - else # Determine the default libpath from the value encoded in an # empty executable. cat confdefs.h - <<_ACEOF >conftest.$ac_ext @@ -13179,7 +13070,6 @@ if test -z "$aix_libpath"; then aix_libpath=3D"/usr= /lib:/lib"; fi # This is similar to how AIX traditionally builds its shared # libraries. archive_expsym_cmds_CXX=3D"\$CC $shared_flag"' -o $output_objdir/$son= ame $libobjs $deplibs ${wl}-bnoentry $compiler_flags ${wl}-bE:$export_symbo= ls${allow_undefined_flag}~$AR $AR_FLAGS $output_objdir/$libname$release.a $= output_objdir/$soname' - fi fi ;; =20 @@ -13347,7 +13237,7 @@ if test -z "$aix_libpath"; then aix_libpath=3D"/usr= /lib:/lib"; fi hardcode_libdir_separator_CXX=3D: =20 case $host_cpu in - hppa*64*|ia64*) + hppa*64*) ;; *) export_dynamic_flag_spec_CXX=3D'${wl}-E' @@ -13355,7 +13245,7 @@ if test -z "$aix_libpath"; then aix_libpath=3D"/usr= /lib:/lib"; fi esac fi case $host_cpu in - hppa*64*|ia64*) + hppa*64*) hardcode_direct_CXX=3Dno hardcode_shlibpath_var_CXX=3Dno ;; @@ -13378,9 +13268,6 @@ if test -z "$aix_libpath"; then aix_libpath=3D"/usr= /lib:/lib"; fi hppa*64*) archive_cmds_CXX=3D'$CC -b ${wl}+h ${wl}$soname ${wl}+nodefaultrp= ath -o $lib $predep_objects $libobjs $deplibs $postdep_objects $compiler_fl= ags' ;; - ia64*) - archive_cmds_CXX=3D'$CC -b ${wl}+h ${wl}$soname ${wl}+nodefaultrp= ath -o $lib $predep_objects $libobjs $deplibs $postdep_objects $compiler_fl= ags' - ;; *) archive_cmds_CXX=3D'$CC -b ${wl}+h ${wl}$soname ${wl}+b ${wl}$ins= tall_libdir -o $lib $predep_objects $libobjs $deplibs $postdep_objects $com= piler_flags' ;; @@ -13402,9 +13289,6 @@ if test -z "$aix_libpath"; then aix_libpath=3D"/usr= /lib:/lib"; fi hppa*64*) archive_cmds_CXX=3D'$CC -shared -nostdlib -fPIC ${wl}+h ${wl}= $soname ${wl}+nodefaultrpath -o $lib $predep_objects $libobjs $deplibs $pos= tdep_objects $compiler_flags' ;; - ia64*) - archive_cmds_CXX=3D'$CC -shared -nostdlib -fPIC ${wl}+h ${wl}= $soname ${wl}+nodefaultrpath -o $lib $predep_objects $libobjs $deplibs $pos= tdep_objects $compiler_flags' - ;; *) archive_cmds_CXX=3D'$CC -shared -nostdlib -fPIC ${wl}+h ${wl}= $soname ${wl}+b ${wl}$install_libdir -o $lib $predep_objects $libobjs $depl= ibs $postdep_objects $compiler_flags' ;; @@ -13500,9 +13384,6 @@ if test -z "$aix_libpath"; then aix_libpath=3D"/usr= /lib:/lib"; fi ;; *) # Version 8.0 or newer tmp_idyn=3D - case $host_cpu in - ia64*) tmp_idyn=3D' -i_dynamic';; - esac archive_cmds_CXX=3D'$CC -shared'"$tmp_idyn"' $libobjs $deplibs $c= ompiler_flags ${wl}-soname $wl$soname -o $lib' archive_expsym_cmds_CXX=3D'$CC -shared'"$tmp_idyn"' $libobjs $deplibs $c= ompiler_flags ${wl}-soname $wl$soname ${wl}-retain-symbols-file $wl$export_= symbols -o $lib' ;; @@ -14148,10 +14029,6 @@ $as_echo_n "checking for $compiler option to produ= ce PIC... " >&6; } case $host_os in aix*) # All AIX code is PIC. - if test "$host_cpu" =3D ia64; then - # AIX 5 now supports IA64 processor - lt_prog_compiler_static_CXX=3D'-Bstatic' - fi lt_prog_compiler_pic_CXX=3D'-fPIC' ;; =20 @@ -14228,12 +14105,7 @@ $as_echo_n "checking for $compiler option to produ= ce PIC... " >&6; } case $host_os in aix[4-9]*) # All AIX code is PIC. - if test "$host_cpu" =3D ia64; then - # AIX 5 now supports IA64 processor - lt_prog_compiler_static_CXX=3D'-Bstatic' - else - lt_prog_compiler_static_CXX=3D'-bnso -bI:/lib/syscalls.exp' - fi + lt_prog_compiler_static_CXX=3D'-bnso -bI:/lib/syscalls.exp' ;; chorus*) case $cc_basename in @@ -14264,15 +14136,13 @@ $as_echo_n "checking for $compiler option to prod= uce PIC... " >&6; } CC*) lt_prog_compiler_wl_CXX=3D'-Wl,' lt_prog_compiler_static_CXX=3D'${wl}-a ${wl}archive' - if test "$host_cpu" !=3D ia64; then - lt_prog_compiler_pic_CXX=3D'+Z' - fi + lt_prog_compiler_pic_CXX=3D'+Z' ;; aCC*) lt_prog_compiler_wl_CXX=3D'-Wl,' lt_prog_compiler_static_CXX=3D'${wl}-a ${wl}archive' case $host_cpu in - hppa*64*|ia64*) + hppa*64*) # +Z the default ;; *) @@ -14903,11 +14773,6 @@ aix[4-9]*) need_lib_prefix=3Dno need_version=3Dno hardcode_into_libs=3Dyes - if test "$host_cpu" =3D ia64; then - # AIX 5 supports IA64 - library_names_spec=3D'${libname}${release}${shared_ext}$major ${libnam= e}${release}${shared_ext}$versuffix $libname${shared_ext}' - shlibpath_var=3DLD_LIBRARY_PATH - else # With GCC up to 2.95.x, collect2 would create an import file # for dependence libraries. The import file would start with # the line `#! .'. This would cause the generated library to @@ -14939,7 +14804,6 @@ aix[4-9]*) soname_spec=3D'${libname}${release}${shared_ext}$major' fi shlibpath_var=3DLIBPATH - fi ;; =20 amigaos*) @@ -15114,21 +14978,6 @@ hpux9* | hpux10* | hpux11*) need_lib_prefix=3Dno need_version=3Dno case $host_cpu in - ia64*) - shrext_cmds=3D'.so' - hardcode_into_libs=3Dyes - dynamic_linker=3D"$host_os dld.so" - shlibpath_var=3DLD_LIBRARY_PATH - shlibpath_overrides_runpath=3Dyes # Unless +noenvvar is specified. - library_names_spec=3D'${libname}${release}${shared_ext}$versuffix ${li= bname}${release}${shared_ext}$major $libname${shared_ext}' - soname_spec=3D'${libname}${release}${shared_ext}$major' - if test "X$HPUX_IA64_MODE" =3D X32; then - sys_lib_search_path_spec=3D"/usr/lib/hpux32 /usr/local/lib/hpux32 /u= sr/local/lib" - else - sys_lib_search_path_spec=3D"/usr/lib/hpux64 /usr/local/lib/hpux64" - fi - sys_lib_dlsearch_path_spec=3D$sys_lib_search_path_spec - ;; hppa*64*) shrext_cmds=3D'.sl' hardcode_into_libs=3Dyes diff --git a/gprofng/libcollector/configure b/gprofng/libcollector/configure index 9e47af8802b..e5be3e0876c 100755 --- a/gprofng/libcollector/configure +++ b/gprofng/libcollector/configure @@ -6978,10 +6978,6 @@ haiku*) hpux10.20* | hpux11*) lt_cv_file_magic_cmd=3D/usr/bin/file case $host_cpu in - ia64*) - lt_cv_deplibs_check_method=3D'file_magic (s[0-9][0-9][0-9]|ELF-[0-9][0= -9]) shared object file - IA64' - lt_cv_file_magic_test_file=3D/usr/lib/hpux32/libc.so - ;; hppa*64*) lt_cv_deplibs_check_method=3D'file_magic (s[0-9][0-9][0-9]|ELF[ -][0-9= ][0-9])(-bit)?( [LM]SB)? shared object( file)?[, -]* PA-RISC [0-9]\.[0-9]' lt_cv_file_magic_test_file=3D/usr/lib/pa20_64/libc.sl @@ -7540,11 +7536,6 @@ aix*) cygwin* | mingw* | pw32* | cegcc*) symcode=3D'[ABCDGISTW]' ;; -hpux*) - if test "$host_cpu" =3D ia64; then - symcode=3D'[ABCDEGRST]' - fi - ;; irix* | nonstopux*) symcode=3D'[BCDEGRST]' ;; @@ -7575,7 +7566,7 @@ case `$NM -V 2>&1` in esac =20 # Transform an extracted symbol line into a proper C declaration. -# Some systems (esp. on ia64) link data and code symbols differently, +# Some systems link data and code symbols differently, # so use this general approach. lt_cv_sys_global_symbol_to_cdecl=3D"sed -n -e 's/^T .* \(.*\)$/extern int = \1();/p' -e 's/^$symcode* .* \(.*\)$/extern char \1;/p'" =20 @@ -7775,25 +7766,6 @@ test "x$enable_libtool_lock" !=3D xno && enable_libt= ool_lock=3Dyes # Some flags need to be propagated to the compiler or linker for good # libtool support. case $host in -ia64-*-hpux*) - # Find out which ABI we are using. - echo 'int i;' > conftest.$ac_ext - if { { eval echo "\"\$as_me\":${as_lineno-$LINENO}: \"$ac_compile\""; } = >&5 - (eval $ac_compile) 2>&5 - ac_status=3D$? - $as_echo "$as_me:${as_lineno-$LINENO}: \$? =3D $ac_status" >&5 - test $ac_status =3D 0; }; then - case `/usr/bin/file conftest.$ac_objext` in - *ELF-32*) - HPUX_IA64_MODE=3D"32" - ;; - *ELF-64*) - HPUX_IA64_MODE=3D"64" - ;; - esac - fi - rm -rf conftest* - ;; *-*-irix6*) # Find out which ABI we are using. echo '#line '$LINENO' "configure"' > conftest.$ac_ext @@ -9129,10 +9101,6 @@ $as_echo_n "checking for $compiler option to produce= PIC... " >&6; } case $host_os in aix*) # All AIX code is PIC. - if test "$host_cpu" =3D ia64; then - # AIX 5 now supports IA64 processor - lt_prog_compiler_static=3D'-Bstatic' - fi lt_prog_compiler_pic=3D'-fPIC' ;; =20 @@ -9229,12 +9197,7 @@ $as_echo_n "checking for $compiler option to produce= PIC... " >&6; } case $host_os in aix*) lt_prog_compiler_wl=3D'-Wl,' - if test "$host_cpu" =3D ia64; then - # AIX 5 now supports IA64 processor - lt_prog_compiler_static=3D'-Bstatic' - else - lt_prog_compiler_static=3D'-bnso -bI:/lib/syscalls.exp' - fi + lt_prog_compiler_static=3D'-bnso -bI:/lib/syscalls.exp' ;; =20 mingw* | cygwin* | pw32* | os2* | cegcc*) @@ -9248,7 +9211,7 @@ $as_echo_n "checking for $compiler option to produce = PIC... " >&6; } # PIC is the default for IA64 HP-UX and 64-bit HP-UX, but # not for PA HP-UX. case $host_cpu in - hppa*64*|ia64*) + hppa*64*) # +Z the default ;; *) @@ -9773,9 +9736,8 @@ $as_echo_n "checking whether the $compiler linker ($L= D) supports shared librarie case $host_os in aix[3-9]*) # On AIX/PPC, the GNU linker is very broken - if test "$host_cpu" !=3D ia64; then - ld_shlibs=3Dno - cat <<_LT_EOF 1>&2 + ld_shlibs=3Dno + cat <<_LT_EOF 1>&2 =20 *** Warning: the GNU linker, at least up to release 2.19, is reported *** to be unable to reliably create shared libraries on AIX. @@ -9785,7 +9747,6 @@ $as_echo_n "checking whether the $compiler linker ($L= D) supports shared librarie *** You will then need to restart the configuration process. =20 _LT_EOF - fi ;; =20 amigaos*) @@ -9881,10 +9842,6 @@ _LT_EOF # Portland Group f77 and f90 compilers whole_archive_flag_spec=3D'${wl}--whole-archive`for conv in $convenienc= e\"\"; do test -n \"$conv\" && new_convenience=3D\"$new_convenience,$conv\= "; done; func_echo_all \"$new_convenience\"` ${wl}--no-whole-archive' tmp_addflag=3D' $pic_flag -Mnomain' ;; - ecc*,ia64* | icc*,ia64*) # Intel C compiler on ia64 - tmp_addflag=3D' -i_dynamic' ;; - efc*,ia64* | ifort*,ia64*) # Intel Fortran compiler on ia64 - tmp_addflag=3D' -i_dynamic -nofor_main' ;; ifc* | ifort*) # Intel Fortran compiler tmp_addflag=3D' -nofor_main' ;; lf95*) # Lahey Fortran 8.1 @@ -10038,13 +9995,6 @@ _LT_EOF ;; =20 aix[4-9]*) - if test "$host_cpu" =3D ia64; then - # On IA64, the linker does run time linking by default, so we don't - # have to do anything special. - aix_use_runtimelinking=3Dno - exp_sym_flag=3D'-Bexport' - no_entry_flag=3D"" - else # If we're using GNU nm, then we don't want the "-C" option. # -C means demangle to AIX nm, but means don't demangle with GNU nm # Also, AIX nm treats weak defined symbols like other global @@ -10071,7 +10021,6 @@ _LT_EOF =20 exp_sym_flag=3D'-bexport' no_entry_flag=3D'-bnoentry' - fi =20 # When large executables or shared objects are built, AIX ld can # have problems creating the table of contents. If linking a library @@ -10114,17 +10063,11 @@ _LT_EOF fi else # not using gcc - if test "$host_cpu" =3D ia64; then - # VisualAge C++, Version 5.5 for AIX 5L for IA-64, Beta 3 Release - # chokes on -Wl,-G. The following line is correct: - shared_flag=3D'-G' - else if test "$aix_use_runtimelinking" =3D yes; then shared_flag=3D'${wl}-G' else shared_flag=3D'${wl}-bM:SRE' fi - fi fi =20 export_dynamic_flag_spec=3D'${wl}-bexpall' @@ -10170,11 +10113,6 @@ if test -z "$aix_libpath"; then aix_libpath=3D"/us= r/lib:/lib"; fi hardcode_libdir_flag_spec=3D'${wl}-blibpath:$libdir:'"$aix_libpath" archive_expsym_cmds=3D'$CC -o $output_objdir/$soname $libobjs $dep= libs '"\${wl}$no_entry_flag"' $compiler_flags `if test "x${allow_undefined_= flag}" !=3D "x"; then func_echo_all "${wl}${allow_undefined_flag}"; else :;= fi` '"\${wl}$exp_sym_flag:\$export_symbols $shared_flag" else - if test "$host_cpu" =3D ia64; then - hardcode_libdir_flag_spec=3D'${wl}-R $libdir:/usr/lib:/lib' - allow_undefined_flag=3D"-z nodefs" - archive_expsym_cmds=3D"\$CC $shared_flag"' -o $output_objdir/$soname $l= ibobjs $deplibs '"\${wl}$no_entry_flag"' $compiler_flags ${wl}${allow_undef= ined_flag} '"\${wl}$exp_sym_flag:\$export_symbols" - else # Determine the default libpath from the value encoded in an # empty executable. cat confdefs.h - <<_ACEOF >conftest.$ac_ext @@ -10222,7 +10160,6 @@ if test -z "$aix_libpath"; then aix_libpath=3D"/usr= /lib:/lib"; fi archive_cmds_need_lc=3Dyes # This is similar to how AIX traditionally builds its shared libraries. archive_expsym_cmds=3D"\$CC $shared_flag"' -o $output_objdir/$soname $l= ibobjs $deplibs ${wl}-bnoentry $compiler_flags ${wl}-bE:$export_symbols${al= low_undefined_flag}~$AR $AR_FLAGS $output_objdir/$libname$release.a $output= _objdir/$soname' - fi fi ;; =20 @@ -10371,9 +10308,6 @@ if test -z "$aix_libpath"; then aix_libpath=3D"/usr= /lib:/lib"; fi hppa*64*) archive_cmds=3D'$CC -shared ${wl}+h ${wl}$soname ${wl}+nodefaultrpath -= o $lib $libobjs $deplibs $compiler_flags' ;; - ia64*) - archive_cmds=3D'$CC -shared -fPIC ${wl}+h ${wl}$soname ${wl}+nodefaultr= path -o $lib $libobjs $deplibs $compiler_flags' - ;; *) archive_cmds=3D'$CC -shared -fPIC ${wl}+h ${wl}$soname ${wl}+b ${wl}$in= stall_libdir -o $lib $libobjs $deplibs $compiler_flags' ;; @@ -10383,9 +10317,6 @@ if test -z "$aix_libpath"; then aix_libpath=3D"/usr= /lib:/lib"; fi hppa*64*) archive_cmds=3D'$CC -b ${wl}+h ${wl}$soname ${wl}+nodefaultrpath -o $li= b $libobjs $deplibs $compiler_flags' ;; - ia64*) - archive_cmds=3D'$CC -b ${wl}+h ${wl}$soname ${wl}+nodefaultrpath -o $li= b $libobjs $deplibs $compiler_flags' - ;; *) =20 # Older versions of the 11.00 compiler do not understand -b yet @@ -10435,7 +10366,7 @@ fi hardcode_libdir_separator=3D: =20 case $host_cpu in - hppa*64*|ia64*) + hppa*64*) hardcode_direct=3Dno hardcode_shlibpath_var=3Dno ;; @@ -11072,11 +11003,6 @@ aix[4-9]*) need_lib_prefix=3Dno need_version=3Dno hardcode_into_libs=3Dyes - if test "$host_cpu" =3D ia64; then - # AIX 5 supports IA64 - library_names_spec=3D'${libname}${release}${shared_ext}$major ${libnam= e}${release}${shared_ext}$versuffix $libname${shared_ext}' - shlibpath_var=3DLD_LIBRARY_PATH - else # With GCC up to 2.95.x, collect2 would create an import file # for dependence libraries. The import file would start with # the line `#! .'. This would cause the generated library to @@ -11108,7 +11034,6 @@ aix[4-9]*) soname_spec=3D'${libname}${release}${shared_ext}$major' fi shlibpath_var=3DLIBPATH - fi ;; =20 amigaos*) @@ -11285,21 +11210,6 @@ hpux9* | hpux10* | hpux11*) need_lib_prefix=3Dno need_version=3Dno case $host_cpu in - ia64*) - shrext_cmds=3D'.so' - hardcode_into_libs=3Dyes - dynamic_linker=3D"$host_os dld.so" - shlibpath_var=3DLD_LIBRARY_PATH - shlibpath_overrides_runpath=3Dyes # Unless +noenvvar is specified. - library_names_spec=3D'${libname}${release}${shared_ext}$versuffix ${li= bname}${release}${shared_ext}$major $libname${shared_ext}' - soname_spec=3D'${libname}${release}${shared_ext}$major' - if test "X$HPUX_IA64_MODE" =3D X32; then - sys_lib_search_path_spec=3D"/usr/lib/hpux32 /usr/local/lib/hpux32 /u= sr/local/lib" - else - sys_lib_search_path_spec=3D"/usr/lib/hpux64 /usr/local/lib/hpux64" - fi - sys_lib_dlsearch_path_spec=3D$sys_lib_search_path_spec - ;; hppa*64*) shrext_cmds=3D'.sl' hardcode_into_libs=3Dyes @@ -12390,7 +12300,7 @@ $as_echo_n "checking whether to build shared librar= ies... " >&6; } ;; =20 aix[4-9]*) - if test "$host_cpu" !=3D ia64 && test "$aix_use_runtimelinking" =3D no= ; then + if test "$aix_use_runtimelinking" =3D no ; then test "$enable_shared" =3D yes && enable_static=3Dno fi ;; @@ -12846,13 +12756,6 @@ $as_echo_n "checking whether the $compiler linker = ($LD) supports shared librarie ld_shlibs_CXX=3Dno ;; aix[4-9]*) - if test "$host_cpu" =3D ia64; then - # On IA64, the linker does run time linking by default, so we do= n't - # have to do anything special. - aix_use_runtimelinking=3Dno - exp_sym_flag=3D'-Bexport' - no_entry_flag=3D"" - else aix_use_runtimelinking=3Dno =20 # Test if we are trying to use run time linking or normal @@ -12872,7 +12775,6 @@ $as_echo_n "checking whether the $compiler linker (= $LD) supports shared librarie =20 exp_sym_flag=3D'-bexport' no_entry_flag=3D'-bnoentry' - fi =20 # When large executables or shared objects are built, AIX ld can # have problems creating the table of contents. If linking a libr= ary @@ -12914,17 +12816,11 @@ $as_echo_n "checking whether the $compiler linker= ($LD) supports shared librarie fi else # not using gcc - if test "$host_cpu" =3D ia64; then - # VisualAge C++, Version 5.5 for AIX 5L for IA-64, Beta 3 Release - # chokes on -Wl,-G. The following line is correct: - shared_flag=3D'-G' - else if test "$aix_use_runtimelinking" =3D yes; then shared_flag=3D'${wl}-G' else shared_flag=3D'${wl}-bM:SRE' fi - fi fi =20 export_dynamic_flag_spec_CXX=3D'${wl}-bexpall' @@ -12972,11 +12868,6 @@ if test -z "$aix_libpath"; then aix_libpath=3D"/us= r/lib:/lib"; fi =20 archive_expsym_cmds_CXX=3D'$CC -o $output_objdir/$soname $libobj= s $deplibs '"\${wl}$no_entry_flag"' $compiler_flags `if test "x${allow_unde= fined_flag}" !=3D "x"; then func_echo_all "${wl}${allow_undefined_flag}"; e= lse :; fi` '"\${wl}$exp_sym_flag:\$export_symbols $shared_flag" else - if test "$host_cpu" =3D ia64; then - hardcode_libdir_flag_spec_CXX=3D'${wl}-R $libdir:/usr/lib:/lib' - allow_undefined_flag_CXX=3D"-z nodefs" - archive_expsym_cmds_CXX=3D"\$CC $shared_flag"' -o $output_objdir/$son= ame $libobjs $deplibs '"\${wl}$no_entry_flag"' $compiler_flags ${wl}${allow= _undefined_flag} '"\${wl}$exp_sym_flag:\$export_symbols" - else # Determine the default libpath from the value encoded in an # empty executable. cat confdefs.h - <<_ACEOF >conftest.$ac_ext @@ -13025,7 +12916,6 @@ if test -z "$aix_libpath"; then aix_libpath=3D"/usr= /lib:/lib"; fi # This is similar to how AIX traditionally builds its shared # libraries. archive_expsym_cmds_CXX=3D"\$CC $shared_flag"' -o $output_objdir/$son= ame $libobjs $deplibs ${wl}-bnoentry $compiler_flags ${wl}-bE:$export_symbo= ls${allow_undefined_flag}~$AR $AR_FLAGS $output_objdir/$libname$release.a $= output_objdir/$soname' - fi fi ;; =20 @@ -13193,7 +13083,7 @@ if test -z "$aix_libpath"; then aix_libpath=3D"/usr= /lib:/lib"; fi hardcode_libdir_separator_CXX=3D: =20 case $host_cpu in - hppa*64*|ia64*) + hppa*64*) ;; *) export_dynamic_flag_spec_CXX=3D'${wl}-E' @@ -13201,7 +13091,7 @@ if test -z "$aix_libpath"; then aix_libpath=3D"/usr= /lib:/lib"; fi esac fi case $host_cpu in - hppa*64*|ia64*) + hppa*64*) hardcode_direct_CXX=3Dno hardcode_shlibpath_var_CXX=3Dno ;; @@ -13224,9 +13114,6 @@ if test -z "$aix_libpath"; then aix_libpath=3D"/usr= /lib:/lib"; fi hppa*64*) archive_cmds_CXX=3D'$CC -b ${wl}+h ${wl}$soname ${wl}+nodefaultrp= ath -o $lib $predep_objects $libobjs $deplibs $postdep_objects $compiler_fl= ags' ;; - ia64*) - archive_cmds_CXX=3D'$CC -b ${wl}+h ${wl}$soname ${wl}+nodefaultrp= ath -o $lib $predep_objects $libobjs $deplibs $postdep_objects $compiler_fl= ags' - ;; *) archive_cmds_CXX=3D'$CC -b ${wl}+h ${wl}$soname ${wl}+b ${wl}$ins= tall_libdir -o $lib $predep_objects $libobjs $deplibs $postdep_objects $com= piler_flags' ;; @@ -13248,9 +13135,6 @@ if test -z "$aix_libpath"; then aix_libpath=3D"/usr= /lib:/lib"; fi hppa*64*) archive_cmds_CXX=3D'$CC -shared -nostdlib -fPIC ${wl}+h ${wl}= $soname ${wl}+nodefaultrpath -o $lib $predep_objects $libobjs $deplibs $pos= tdep_objects $compiler_flags' ;; - ia64*) - archive_cmds_CXX=3D'$CC -shared -nostdlib -fPIC ${wl}+h ${wl}= $soname ${wl}+nodefaultrpath -o $lib $predep_objects $libobjs $deplibs $pos= tdep_objects $compiler_flags' - ;; *) archive_cmds_CXX=3D'$CC -shared -nostdlib -fPIC ${wl}+h ${wl}= $soname ${wl}+b ${wl}$install_libdir -o $lib $predep_objects $libobjs $depl= ibs $postdep_objects $compiler_flags' ;; @@ -13346,9 +13230,6 @@ if test -z "$aix_libpath"; then aix_libpath=3D"/usr= /lib:/lib"; fi ;; *) # Version 8.0 or newer tmp_idyn=3D - case $host_cpu in - ia64*) tmp_idyn=3D' -i_dynamic';; - esac archive_cmds_CXX=3D'$CC -shared'"$tmp_idyn"' $libobjs $deplibs $c= ompiler_flags ${wl}-soname $wl$soname -o $lib' archive_expsym_cmds_CXX=3D'$CC -shared'"$tmp_idyn"' $libobjs $deplibs $c= ompiler_flags ${wl}-soname $wl$soname ${wl}-retain-symbols-file $wl$export_= symbols -o $lib' ;; @@ -13994,10 +13875,6 @@ $as_echo_n "checking for $compiler option to produ= ce PIC... " >&6; } case $host_os in aix*) # All AIX code is PIC. - if test "$host_cpu" =3D ia64; then - # AIX 5 now supports IA64 processor - lt_prog_compiler_static_CXX=3D'-Bstatic' - fi lt_prog_compiler_pic_CXX=3D'-fPIC' ;; =20 @@ -14074,12 +13951,7 @@ $as_echo_n "checking for $compiler option to produ= ce PIC... " >&6; } case $host_os in aix[4-9]*) # All AIX code is PIC. - if test "$host_cpu" =3D ia64; then - # AIX 5 now supports IA64 processor - lt_prog_compiler_static_CXX=3D'-Bstatic' - else - lt_prog_compiler_static_CXX=3D'-bnso -bI:/lib/syscalls.exp' - fi + lt_prog_compiler_static_CXX=3D'-bnso -bI:/lib/syscalls.exp' ;; chorus*) case $cc_basename in @@ -14110,15 +13982,13 @@ $as_echo_n "checking for $compiler option to prod= uce PIC... " >&6; } CC*) lt_prog_compiler_wl_CXX=3D'-Wl,' lt_prog_compiler_static_CXX=3D'${wl}-a ${wl}archive' - if test "$host_cpu" !=3D ia64; then - lt_prog_compiler_pic_CXX=3D'+Z' - fi + lt_prog_compiler_pic_CXX=3D'+Z' ;; aCC*) lt_prog_compiler_wl_CXX=3D'-Wl,' lt_prog_compiler_static_CXX=3D'${wl}-a ${wl}archive' case $host_cpu in - hppa*64*|ia64*) + hppa*64*) # +Z the default ;; *) @@ -14749,11 +14619,6 @@ aix[4-9]*) need_lib_prefix=3Dno need_version=3Dno hardcode_into_libs=3Dyes - if test "$host_cpu" =3D ia64; then - # AIX 5 supports IA64 - library_names_spec=3D'${libname}${release}${shared_ext}$major ${libnam= e}${release}${shared_ext}$versuffix $libname${shared_ext}' - shlibpath_var=3DLD_LIBRARY_PATH - else # With GCC up to 2.95.x, collect2 would create an import file # for dependence libraries. The import file would start with # the line `#! .'. This would cause the generated library to @@ -14785,7 +14650,6 @@ aix[4-9]*) soname_spec=3D'${libname}${release}${shared_ext}$major' fi shlibpath_var=3DLIBPATH - fi ;; =20 amigaos*) @@ -14960,21 +14824,6 @@ hpux9* | hpux10* | hpux11*) need_lib_prefix=3Dno need_version=3Dno case $host_cpu in - ia64*) - shrext_cmds=3D'.so' - hardcode_into_libs=3Dyes - dynamic_linker=3D"$host_os dld.so" - shlibpath_var=3DLD_LIBRARY_PATH - shlibpath_overrides_runpath=3Dyes # Unless +noenvvar is specified. - library_names_spec=3D'${libname}${release}${shared_ext}$versuffix ${li= bname}${release}${shared_ext}$major $libname${shared_ext}' - soname_spec=3D'${libname}${release}${shared_ext}$major' - if test "X$HPUX_IA64_MODE" =3D X32; then - sys_lib_search_path_spec=3D"/usr/lib/hpux32 /usr/local/lib/hpux32 /u= sr/local/lib" - else - sys_lib_search_path_spec=3D"/usr/lib/hpux64 /usr/local/lib/hpux64" - fi - sys_lib_dlsearch_path_spec=3D$sys_lib_search_path_spec - ;; hppa*64*) shrext_cmds=3D'.sl' hardcode_into_libs=3Dyes diff --git a/include/coff/ia64.h b/include/coff/ia64.h deleted file mode 100644 index 20bbdf6b8fb..00000000000 --- a/include/coff/ia64.h +++ /dev/null @@ -1,89 +0,0 @@ -/* coff information for HP/Intel IA-64. -=20=20=20 - Copyright (C) 2000-2024 Free Software Foundation, Inc. - - This program is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. -=20=20=20 - This program is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. -=20=20=20 - You should have received a copy of the GNU General Public License - along with this program; if not, write to the Free Software - Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, - MA 02110-1301, USA. */ - -#define DO_NOT_DEFINE_AOUTHDR -#define L_LNNO_SIZE 2 -#define INCLUDE_COMDAT_FIELDS_IN_AUXENT -#include "coff/external.h" - -#define IA64MAGIC 0x200 - -#define IA64BADMAG(x) (((x).f_magic !=3D IA64MAGIC)) - -/* Bits for f_flags: - * F_RELFLG relocation info stripped from file - * F_EXEC file is executable (no unresolved external references) - * F_LNNO line numbers stripped from file - * F_LSYMS local symbols stripped from file - * F_AR32WR file has byte ordering of an AR32WR machine (e.g. vax) - */ - -#define F_RELFLG (0x0001) -#define F_EXEC (0x0002) -#define F_LNNO (0x0004) -#define F_LSYMS (0x0008) - -/********************** AOUT "OPTIONAL HEADER" **********************/ -typedef struct=20 -{ - char magic[2]; /* type of file */ - char vstamp[2]; /* version stamp */ - char tsize[4]; /* text size in bytes, padded to FW bdry*/ - char dsize[4]; /* initialized data " " */ - char bsize[4]; /* uninitialized data " " */ - char entry[4]; /* entry pt. */ - char text_start[4]; /* base of text used for this file */ -#ifndef BFD64 - char data_start[4]; /* base of data used for this file */ -#endif -} -AOUTHDR; - -#define PE32MAGIC 0x10b /* 32-bit image */ -#define PE32PMAGIC 0x20b /* 32-bit image inside 64-bit address space */ - -#define PE32PBADMAG(x) (((x).f_magic !=3D PE32PMAGIC)) - -#define AOUTSZ 108 -#define AOUTHDRSZ 108 - -#define OMAGIC 0404 /* object files, eg as output */ -#define ZMAGIC 0413 /* demand load format, eg normal ld output= */ -#define STMAGIC 0401 /* target shlib */ -#define SHMAGIC 0443 /* host shlib */ - -/* define some NT default values */ -/* #define NT_IMAGE_BASE 0x400000 moved to internal.h */ -#define NT_SECTION_ALIGNMENT 0x1000 -#define NT_FILE_ALIGNMENT 0x200 -#define NT_DEF_RESERVE 0x100000 -#define NT_DEF_COMMIT 0x1000 - -/********************** RELOCATION DIRECTIVES **********************/ - -struct external_reloc -{ - char r_vaddr[4]; - char r_symndx[4]; - char r_type[2]; -}; - -#define RELOC struct external_reloc -#define RELSZ 10 - diff --git a/include/elf/ia64.h b/include/elf/ia64.h deleted file mode 100644 index c4a93727cf2..00000000000 --- a/include/elf/ia64.h +++ /dev/null @@ -1,415 +0,0 @@ -/* IA-64 ELF support for BFD. - Copyright (C) 1998-2024 Free Software Foundation, Inc. - Contributed by David Mosberger-Tang - - This file is part of BFD, the Binary File Descriptor library. - - This program is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - This program is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program; if not, write to the Free Software - Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, - MA 02110-1301, USA. */ - -#ifndef _ELF_IA64_H -#define _ELF_IA64_H - -/* Bits in the e_flags field of the Elf64_Ehdr: */ - -#define EF_IA_64_MASKOS 0x0000000f /* OS-specific flags. */ -#define EF_IA_64_ARCH 0xff000000 /* Arch. version mask. */ -#define EF_IA_64_ARCHVER_1 (1 << 24) /* Arch. version level 1 compat. = */ - -/* ??? These four definitions are not part of the SVR4 ABI. - They were present in David's initial code drop, so it is probable - that they are used by HP/UX. */ -#define EF_IA_64_TRAPNIL (1 << 0) /* Trap NIL pointer dereferences. */ -#define EF_IA_64_EXT (1 << 2) /* Program uses arch. extensions. */ -#define EF_IA_64_BE (1 << 3) /* PSR BE bit set (big-endian). */ -#define EFA_IA_64_EAS2_3 0x23000000 /* IA64 EAS 2.3. */ - -#define EF_IA_64_ABI64 (1 << 4) /* 64-bit ABI. */ -/* Not used yet. */ -#define EF_IA_64_REDUCEDFP (1 << 5) /* Only FP6-FP11 used. */ -#define EF_IA_64_CONS_GP (1 << 6) /* gp as program wide constant. */ -#define EF_IA_64_NOFUNCDESC_CONS_GP (1 << 7) /* And no function descriptor= s. */ -/* Not used yet. */ -#define EF_IA_64_ABSOLUTE (1 << 8) /* Load at absolute addresses. */ - -/* OpenVMS speficic. */ -#define EF_IA_64_VMS_COMCOD 0x03 /* Completion code. */ -#define EF_IA_64_VMS_COMCOD_SUCCESS 0 -#define EF_IA_64_VMS_COMCOD_WARNING 1 -#define EF_IA_64_VMS_COMCOD_ERROR 2 -#define EF_IA_64_VMS_COMCOD_ABORT 3 -#define EF_IA_64_VMS_LINKAGES 0x04 /* Contains VMS linkages info. */ - -#define ELF_STRING_ia64_archext ".IA_64.archext" -#define ELF_STRING_ia64_pltoff ".IA_64.pltoff" -#define ELF_STRING_ia64_unwind ".IA_64.unwind" -#define ELF_STRING_ia64_unwind_info ".IA_64.unwind_info" -#define ELF_STRING_ia64_unwind_once ".gnu.linkonce.ia64unw." -#define ELF_STRING_ia64_unwind_info_once ".gnu.linkonce.ia64unwi." -/* .IA_64.unwind_hdr is only used by HP-UX. */ -#define ELF_STRING_ia64_unwind_hdr ".IA_64.unwind_hdr" - -/* Bits in the sh_flags field of Elf64_Shdr: */ - -#define SHF_IA_64_SHORT 0x10000000 /* Section near gp. */ -#define SHF_IA_64_NORECOV 0x20000000 /* Spec insns w/o recovery. */ - -#define SHF_IA_64_HP_TLS 0x01000000 /* HP specific TLS flag. */ - -#define SHF_IA_64_VMS_GLOBAL 0x0100000000ULL /* Global for clustering= . */ -#define SHF_IA_64_VMS_OVERLAID 0x0200000000ULL /* To be overlaid. */ -#define SHF_IA_64_VMS_SHARED 0x0400000000ULL /* Shared btw processes.= */ -#define SHF_IA_64_VMS_VECTOR 0x0800000000ULL /* Priv change mode vect= . */ -#define SHF_IA_64_VMS_ALLOC_64BIT 0x1000000000ULL /* Allocate beyond 2GB. = */ -#define SHF_IA_64_VMS_PROTECTED 0x2000000000ULL /* Export from sharable.= */ - -/* Possible values for sh_type in Elf64_Shdr: */ - -#define SHT_IA_64_EXT (SHT_LOPROC + 0) /* Extension bits. */ -#define SHT_IA_64_UNWIND (SHT_LOPROC + 1) /* Unwind bits. */ -#define SHT_IA_64_LOPSREG (SHT_LOPROC + 0x8000000) -/* ABI says (SHT_LOPROC + 0xfffffff) but I think it's a typo -- this makes= sense. */ -#define SHT_IA_64_HIPSREG (SHT_LOPROC + 0x8ffffff) -#define SHT_IA_64_PRIORITY_INIT (SHT_LOPROC + 0x9000000) - -/* SHT_IA_64_HP_OPT_ANOT is only generated by HPUX compilers for its - optimization annotation section. GCC does not generate it but we - want readelf to know what they are. Do not use two capital Ns in - annotate or sed will turn it into 32 or 64 during the build. */ -#define SHT_IA_64_HP_OPT_ANOT 0x60000004 - -/* OpenVMS section types. */ -/* The section contains PC-to-source correlation information for use by the - VMS RTL's traceback facility. */ -#define SHT_IA_64_VMS_TRACE 0x60000000 -/* The section contains routine signature information for use by the - translated image executive. */ -#define SHT_IA_64_VMS_TIE_SIGNATURES 0x60000001 -/* The section contains dwarf-3 information. */ -#define SHT_IA_64_VMS_DEBUG 0x60000002 -/* The section contains the dwarf-3 string table. */ -#define SHT_IA_64_VMS_DEBUG_STR 0x60000003 -/* The section contains linkage information to perform consistency checking - accross object modules. */ -#define SHT_IA_64_VMS_LINKAGES 0x60000004 -/* The section allows the symbol vector in an image to be location through - the section table. */ -#define SHT_IA_64_VMS_SYMBOL_VECTOR 0x60000005 -/* The section contains inter-image fixups. */ -#define SHT_IA_64_VMS_FIXUP 0x60000006 -/* The section contains unmangled name info. */ -#define SHT_IA_64_VMS_DISPLAY_NAME_INFO 0x60000007 - -/* Bits in the p_flags field of Elf64_Phdr: */ - -#define PF_IA_64_NORECOV 0x80000000 - -/* Possible values for p_type in Elf64_Phdr: */ - -#define PT_IA_64_ARCHEXT (PT_LOPROC + 0) /* Arch extension bits, */ -#define PT_IA_64_UNWIND (PT_LOPROC + 1) /* IA64 unwind bits. */ - -/* HP-UX specific values for p_type in Elf64_Phdr. - These values are currently just used to make - readelf more usable on HP-UX. */ - -#define PT_IA_64_HP_OPT_ANOT (PT_LOOS + 0x12) -#define PT_IA_64_HP_HSL_ANOT (PT_LOOS + 0x13) -#define PT_IA_64_HP_STACK (PT_LOOS + 0x14) - -/* Possible values for d_tag in Elf64_Dyn: */ - -#define DT_IA_64_PLT_RESERVE (DT_LOPROC + 0) - -/* VMS specific values for d_tag in Elf64_Dyn: */ - -#define DT_IA_64_VMS_SUBTYPE (DT_LOOS + 0) -#define DT_IA_64_VMS_IMGIOCNT (DT_LOOS + 2) -#define DT_IA_64_VMS_LNKFLAGS (DT_LOOS + 8) -#define DT_IA_64_VMS_VIR_MEM_BLK_SIZ (DT_LOOS + 10) -#define DT_IA_64_VMS_IDENT (DT_LOOS + 12) -#define DT_IA_64_VMS_NEEDED_IDENT (DT_LOOS + 16) -#define DT_IA_64_VMS_IMG_RELA_CNT (DT_LOOS + 18) -#define DT_IA_64_VMS_SEG_RELA_CNT (DT_LOOS + 20) -#define DT_IA_64_VMS_FIXUP_RELA_CNT (DT_LOOS + 22) -#define DT_IA_64_VMS_FIXUP_NEEDED (DT_LOOS + 24) -#define DT_IA_64_VMS_SYMVEC_CNT (DT_LOOS + 26) -#define DT_IA_64_VMS_XLATED (DT_LOOS + 30) -#define DT_IA_64_VMS_STACKSIZE (DT_LOOS + 32) -#define DT_IA_64_VMS_UNWINDSZ (DT_LOOS + 34) -#define DT_IA_64_VMS_UNWIND_CODSEG (DT_LOOS + 36) -#define DT_IA_64_VMS_UNWIND_INFOSEG (DT_LOOS + 38) -#define DT_IA_64_VMS_LINKTIME (DT_LOOS + 40) -#define DT_IA_64_VMS_SEG_NO (DT_LOOS + 42) -#define DT_IA_64_VMS_SYMVEC_OFFSET (DT_LOOS + 44) -#define DT_IA_64_VMS_SYMVEC_SEG (DT_LOOS + 46) -#define DT_IA_64_VMS_UNWIND_OFFSET (DT_LOOS + 48) -#define DT_IA_64_VMS_UNWIND_SEG (DT_LOOS + 50) -#define DT_IA_64_VMS_STRTAB_OFFSET (DT_LOOS + 52) -#define DT_IA_64_VMS_SYSVER_OFFSET (DT_LOOS + 54) -#define DT_IA_64_VMS_IMG_RELA_OFF (DT_LOOS + 56) -#define DT_IA_64_VMS_SEG_RELA_OFF (DT_LOOS + 58) -#define DT_IA_64_VMS_FIXUP_RELA_OFF (DT_LOOS + 60) -#define DT_IA_64_VMS_PLTGOT_OFFSET (DT_LOOS + 62) -#define DT_IA_64_VMS_PLTGOT_SEG (DT_LOOS + 64) -#define DT_IA_64_VMS_FPMODE (DT_LOOS + 66) - -/* Values for DT_IA_64_LNKFLAGS. */ -#define VMS_LF_CALL_DEBUG 0x0001 /* Activate and call the debugger. */ -#define VMS_LF_NOP0BUFS 0x0002 /* RMS use of P0 for i/o disabled. */ -#define VMS_LF_P0IMAGE 0x0004 /* Image in P0 space only. */ -#define VMS_LF_MKTHREADS 0x0008 /* Multiple kernel threads enabled. */ -#define VMS_LF_UPCALLS 0x0010 /* Upcalls enabled. */ -#define VMS_LF_IMGSTA 0x0020 /* Use SYS$IMGSTA. */ -#define VMS_LF_INITIALIZE 0x0040 /* Image uses tfradr2. */ -#define VMS_LF_MAIN 0x0080 /* Image uses tfradr3. */ -#define VMS_LF_EXE_INIT 0x0200 /* Image uses tfradr4. */ -#define VMS_LF_TBK_IN_IMG 0x0400 /* Traceback records in image. */ -#define VMS_LF_DBG_IN_IMG 0x0800 /* Debug records in image. */ -#define VMS_LF_TBK_IN_DSF 0x1000 /* Traceback records in DSF. */ -#define VMS_LF_DBG_IN_DSF 0x2000 /* Debug records in DSF. */ -#define VMS_LF_SIGNATURES 0x4000 /* Signatures present. */ -#define VMS_LF_REL_SEG_OFF 0x8000 /* Maintain relative pos of seg. */ - -/* This section only used by HP-UX, The HP linker gives weak symbols - precedence over regular common symbols. We want common to override - weak. Using this common instead of SHN_COMMON does that. */ -#define SHN_IA_64_ANSI_COMMON SHN_LORESERVE - -/* This section is only used by OpenVMS. Symbol is defined in the symbol - vector (only possible for image files). */ -#define SHN_IA_64_VMS_SYMVEC SHN_LOOS - -/* OpenVMS IA64-specific symbol attributes. */ -#define VMS_STO_VISIBILITY 3 /* Alias of the standard field. */ -#define VMS_ST_VISIBILITY(o) ((o) & VMS_STO_VISIBILITY) -#define VMS_STO_FUNC_TYPE 0x30 /* Function type. */ -#define VMS_ST_FUNC_TYPE(o) (((o) & VMS_STO_FUNC_TYPE) >> 4) -# define VMS_SFT_CODE_ADDR 0 /* Symbol value is a code address. */ -# define VMS_SFT_SYMV_IDX 1 /* Symbol value is a symbol vector index. = */ -# define VMS_SFT_FD 2 /* Symbol value is a function descriptor. */ -# define VMS_SFT_RESERVE 3 /* Reserved. */ -#define VMS_STO_LINKAGE 0xc0 -#define VMS_ST_LINKAGE(o) (((o) & VMS_STO_LINKAGE) >> 6) -# define VMS_STL_IGNORE 0 /* No associated linkage. */ -# define VMS_STL_RESERVE 1 -# define VMS_STL_STD 2 /* Standard linkage with return value. */ -# define VMS_STL_LNK 3 /* Explicit represented in .vms_linkages. */ - -/* OpenVMS specific symbol binding values. */ -#define STB_VMS_WEAK 11 /* VMS weak symbol. */ -#define STB_VMS_SYSTEM 12 /* System symbol. */ - -/* OpenVMS specific fixup and relocation structures. */ - -typedef struct -{ - unsigned char fixup_offset[8]; - unsigned char type[4]; - unsigned char fixup_seg[4]; - unsigned char addend[8]; - unsigned char symvec_index[4]; - unsigned char data_type[4]; -} Elf64_External_VMS_IMAGE_FIXUP; - -typedef struct -{ - unsigned char rela_offset[8]; - unsigned char type[4]; - unsigned char rela_seg[4]; - unsigned char addend[8]; - unsigned char sym_offset[8]; - unsigned char sym_seg[4]; - unsigned char fill_1[4]; -} Elf64_External_VMS_IMAGE_RELA; - -/* Note segments. VMS is special as it uses 64-bit entries. */ - -typedef struct { - unsigned char namesz[8]; /* Size of entry's owner string */ - unsigned char descsz[8]; /* Size of the note descriptor */ - unsigned char type[8]; /* Interpretation of the descriptor */ - char name[1]; /* Start of the name+desc data */ -} Elf64_External_VMS_Note; - -#define NT_VMS_MHD 1 /* Object module name, version, and date/time= . */ -#define NT_VMS_LNM 2 /* Language processor name. */ -#define NT_VMS_SRC 3 /* Source files. */ -#define NT_VMS_TITLE 4 /* Title text. */ -#define NT_VMS_EIDC 5 /* Entity ident consistency check. */ -#define NT_VMS_FPMODE 6 /* Whole program floating-point mode. */ -#define NT_VMS_LINKTIME 101 /* Date/time image was linked. */ -#define NT_VMS_IMGNAM 102 /* Image name string. */ -#define NT_VMS_IMGID 103 /* Image ident string. */ -#define NT_VMS_LINKID 104 /* Linker ident string. */ -#define NT_VMS_IMGBID 105 /* Image build ident string. */ -#define NT_VMS_GSTNAM 106 /* Global Symbol Table Name. */ -#define NT_VMS_ORIG_DYN 107 /* Original setting of dynamic data. */ -#define NT_VMS_PATCHTIME 108 /* Date/time of last patch. */ - -/* Corresponding data for NT_VMS_ORIG_DYM. */ - -typedef struct { - unsigned char major_id[4]; /* Should be 1. */ - unsigned char minor_id[4]; /* Should be 3. */ - unsigned char manipulation_date[8]; /* Original NT_VMS_LNKTIME. */ - unsigned char link_flags[8]; /* Original NT_VMS_LNKFLAGS. */ - unsigned char elf_flags[4]; /* Original ehdr flags. */ - unsigned char _pad[4]; - unsigned char imgid[1]; /* Original NT_VMS_IMGID. */ -} Elf64_External_VMS_ORIG_DYN_Note; - -/* IA64-specific relocation types: */ - -/* Relocs apply to specific instructions within a bundle. The least - significant 2 bits of the address indicate which instruction in the - bundle the reloc refers to (0=3Dfirst slot, 1=3Dsecond slow, 2=3Dthird - slot, 3=3Dundefined) and the remaining bits give the address of the - bundle (16 byte aligned). - - The top 5 bits of the reloc code specifies the expression type, the - low 3 bits the format of the data word being relocated. */ - -#include "elf/reloc-macros.h" - -START_RELOC_NUMBERS (elf_ia64_reloc_type) - RELOC_NUMBER (R_IA64_NONE, 0x00) /* none */ - - RELOC_NUMBER (R_IA64_IMM14, 0x21) /* symbol + addend, add imm14 */ - RELOC_NUMBER (R_IA64_IMM22, 0x22) /* symbol + addend, add imm22 */ - RELOC_NUMBER (R_IA64_IMM64, 0x23) /* symbol + addend, mov imm64 */ - RELOC_NUMBER (R_IA64_DIR32MSB, 0x24) /* symbol + addend, data4 MSB */ - RELOC_NUMBER (R_IA64_DIR32LSB, 0x25) /* symbol + addend, data4 LSB */ - RELOC_NUMBER (R_IA64_DIR64MSB, 0x26) /* symbol + addend, data8 MSB */ - RELOC_NUMBER (R_IA64_DIR64LSB, 0x27) /* symbol + addend, data8 LSB */ - - RELOC_NUMBER (R_IA64_GPREL22, 0x2a) /* @gprel(sym+add), add imm22 */ - RELOC_NUMBER (R_IA64_GPREL64I, 0x2b) /* @gprel(sym+add), mov imm64 */ - RELOC_NUMBER (R_IA64_GPREL32MSB, 0x2c) /* @gprel(sym+add), data4 MSB */ - RELOC_NUMBER (R_IA64_GPREL32LSB, 0x2d) /* @gprel(sym+add), data4 LSB */ - RELOC_NUMBER (R_IA64_GPREL64MSB, 0x2e) /* @gprel(sym+add), data8 MSB */ - RELOC_NUMBER (R_IA64_GPREL64LSB, 0x2f) /* @gprel(sym+add), data8 LSB */ - - RELOC_NUMBER (R_IA64_LTOFF22, 0x32) /* @ltoff(sym+add), add imm22 */ - RELOC_NUMBER (R_IA64_LTOFF64I, 0x33) /* @ltoff(sym+add), mov imm64 */ - - RELOC_NUMBER (R_IA64_PLTOFF22, 0x3a) /* @pltoff(sym+add), add imm22 */ - RELOC_NUMBER (R_IA64_PLTOFF64I, 0x3b) /* @pltoff(sym+add), mov imm64 */ - RELOC_NUMBER (R_IA64_PLTOFF64MSB, 0x3e) /* @pltoff(sym+add), data8 MSB */ - RELOC_NUMBER (R_IA64_PLTOFF64LSB, 0x3f) /* @pltoff(sym+add), data8 LSB */ - - RELOC_NUMBER (R_IA64_FPTR64I, 0x43) /* @fptr(sym+add), mov imm64 */ - RELOC_NUMBER (R_IA64_FPTR32MSB, 0x44) /* @fptr(sym+add), data4 MSB */ - RELOC_NUMBER (R_IA64_FPTR32LSB, 0x45) /* @fptr(sym+add), data4 LSB */ - RELOC_NUMBER (R_IA64_FPTR64MSB, 0x46) /* @fptr(sym+add), data8 MSB */ - RELOC_NUMBER (R_IA64_FPTR64LSB, 0x47) /* @fptr(sym+add), data8 LSB */ - - RELOC_NUMBER (R_IA64_PCREL60B, 0x48) /* @pcrel(sym+add), brl */ - RELOC_NUMBER (R_IA64_PCREL21B, 0x49) /* @pcrel(sym+add), ptb, call */ - RELOC_NUMBER (R_IA64_PCREL21M, 0x4a) /* @pcrel(sym+add), chk.s */ - RELOC_NUMBER (R_IA64_PCREL21F, 0x4b) /* @pcrel(sym+add), fchkf */ - RELOC_NUMBER (R_IA64_PCREL32MSB, 0x4c) /* @pcrel(sym+add), data4 MSB */ - RELOC_NUMBER (R_IA64_PCREL32LSB, 0x4d) /* @pcrel(sym+add), data4 LSB */ - RELOC_NUMBER (R_IA64_PCREL64MSB, 0x4e) /* @pcrel(sym+add), data8 MSB */ - RELOC_NUMBER (R_IA64_PCREL64LSB, 0x4f) /* @pcrel(sym+add), data8 LSB */ - - RELOC_NUMBER (R_IA64_LTOFF_FPTR22, 0x52) /* @ltoff(@fptr(s+a)), imm22 */ - RELOC_NUMBER (R_IA64_LTOFF_FPTR64I, 0x53) /* @ltoff(@fptr(s+a)), imm64 */ - RELOC_NUMBER (R_IA64_LTOFF_FPTR32MSB, 0x54) /* @ltoff(@fptr(s+a)), 4 MSB= */ - RELOC_NUMBER (R_IA64_LTOFF_FPTR32LSB, 0x55) /* @ltoff(@fptr(s+a)), 4 LSB= */ - RELOC_NUMBER (R_IA64_LTOFF_FPTR64MSB, 0x56) /* @ltoff(@fptr(s+a)), 8 MSB= */ - RELOC_NUMBER (R_IA64_LTOFF_FPTR64LSB, 0x57) /* @ltoff(@fptr(s+a)), 8 LSB= */ - - RELOC_NUMBER (R_IA64_SEGREL32MSB, 0x5c) /* @segrel(sym+add), data4 MSB */ - RELOC_NUMBER (R_IA64_SEGREL32LSB, 0x5d) /* @segrel(sym+add), data4 LSB */ - RELOC_NUMBER (R_IA64_SEGREL64MSB, 0x5e) /* @segrel(sym+add), data8 MSB */ - RELOC_NUMBER (R_IA64_SEGREL64LSB, 0x5f) /* @segrel(sym+add), data8 LSB */ - - RELOC_NUMBER (R_IA64_SECREL32MSB, 0x64) /* @secrel(sym+add), data4 MSB */ - RELOC_NUMBER (R_IA64_SECREL32LSB, 0x65) /* @secrel(sym+add), data4 LSB */ - RELOC_NUMBER (R_IA64_SECREL64MSB, 0x66) /* @secrel(sym+add), data8 MSB */ - RELOC_NUMBER (R_IA64_SECREL64LSB, 0x67) /* @secrel(sym+add), data8 LSB */ - - RELOC_NUMBER (R_IA64_REL32MSB, 0x6c) /* data 4 + REL */ - RELOC_NUMBER (R_IA64_REL32LSB, 0x6d) /* data 4 + REL */ - RELOC_NUMBER (R_IA64_REL64MSB, 0x6e) /* data 8 + REL */ - RELOC_NUMBER (R_IA64_REL64LSB, 0x6f) /* data 8 + REL */ - - RELOC_NUMBER (R_IA64_LTV32MSB, 0x74) /* symbol + addend, data4 MSB */ - RELOC_NUMBER (R_IA64_LTV32LSB, 0x75) /* symbol + addend, data4 LSB */ - RELOC_NUMBER (R_IA64_LTV64MSB, 0x76) /* symbol + addend, data8 MSB */ - RELOC_NUMBER (R_IA64_LTV64LSB, 0x77) /* symbol + addend, data8 LSB */ - - RELOC_NUMBER (R_IA64_PCREL21BI, 0x79) /* @pcrel(sym+add), ptb, call */ - RELOC_NUMBER (R_IA64_PCREL22, 0x7a) /* @pcrel(sym+add), imm22 */ - RELOC_NUMBER (R_IA64_PCREL64I, 0x7b) /* @pcrel(sym+add), imm64 */ - - RELOC_NUMBER (R_IA64_IPLTMSB, 0x80) /* dynamic reloc, imported PLT, MSB = */ - RELOC_NUMBER (R_IA64_IPLTLSB, 0x81) /* dynamic reloc, imported PLT, LSB = */ - RELOC_NUMBER (R_IA64_COPY, 0x84) /* dynamic reloc, data copy */ - RELOC_NUMBER (R_IA64_LTOFF22X, 0x86) /* LTOFF22, relaxable. */ - RELOC_NUMBER (R_IA64_LDXMOV, 0x87) /* Use of LTOFF22X. */ - - RELOC_NUMBER (R_IA64_TPREL14, 0x91) /* @tprel(sym+add), add imm14 */ - RELOC_NUMBER (R_IA64_TPREL22, 0x92) /* @tprel(sym+add), add imm22 */ - RELOC_NUMBER (R_IA64_TPREL64I, 0x93) /* @tprel(sym+add), add imm64 */ - RELOC_NUMBER (R_IA64_TPREL64MSB, 0x96) /* @tprel(sym+add), data8 MSB */ - RELOC_NUMBER (R_IA64_TPREL64LSB, 0x97) /* @tprel(sym+add), data8 LSB */ - - RELOC_NUMBER (R_IA64_LTOFF_TPREL22, 0x9a) /* @ltoff(@tprel(s+a)), add im= m22 */ - - RELOC_NUMBER (R_IA64_DTPMOD64MSB, 0xa6) /* @dtpmod(sym+add), data8 MSB */ - RELOC_NUMBER (R_IA64_DTPMOD64LSB, 0xa7) /* @dtpmod(sym+add), data8 LSB */ - RELOC_NUMBER (R_IA64_LTOFF_DTPMOD22, 0xaa) /* @ltoff(@dtpmod(s+a)), imm2= 2 */ - - RELOC_NUMBER (R_IA64_DTPREL14, 0xb1) /* @dtprel(sym+add), imm14 */ - RELOC_NUMBER (R_IA64_DTPREL22, 0xb2) /* @dtprel(sym+add), imm22 */ - RELOC_NUMBER (R_IA64_DTPREL64I, 0xb3) /* @dtprel(sym+add), imm64 */ - RELOC_NUMBER (R_IA64_DTPREL32MSB, 0xb4) /* @dtprel(sym+add), data4 MSB */ - RELOC_NUMBER (R_IA64_DTPREL32LSB, 0xb5) /* @dtprel(sym+add), data4 LSB */ - RELOC_NUMBER (R_IA64_DTPREL64MSB, 0xb6) /* @dtprel(sym+add), data8 MSB */ - RELOC_NUMBER (R_IA64_DTPREL64LSB, 0xb7) /* @dtprel(sym+add), data8 LSB */ - - RELOC_NUMBER (R_IA64_LTOFF_DTPREL22, 0xba) /* @ltoff(@dtprel(s+a)), imm2= 2 */ - - FAKE_RELOC (R_IA64_MAX_RELOC_CODE, 0xba) - - /* OpenVMS specific relocs. */ - RELOC_NUMBER (R_IA64_VMS_DIR8, 0x70000000) /* S + A */ - RELOC_NUMBER (R_IA64_VMS_DIR16LSB, 0x70000001) /* S + A */ - RELOC_NUMBER (R_IA64_VMS_CALL_SIGNATURE, 0x70000002) - RELOC_NUMBER (R_IA64_VMS_EXECLET_FUNC, 0x70000003) - RELOC_NUMBER (R_IA64_VMS_EXECLET_DATA, 0x70000004) - RELOC_NUMBER (R_IA64_VMS_FIX8, 0x70000005) /* S + A */ - RELOC_NUMBER (R_IA64_VMS_FIX16, 0x70000006) /* S + A */ - RELOC_NUMBER (R_IA64_VMS_FIX32, 0x70000007) /* S + A */ - RELOC_NUMBER (R_IA64_VMS_FIX64, 0x70000008) /* S + A */ - RELOC_NUMBER (R_IA64_VMS_FIXFD, 0x70000009) - RELOC_NUMBER (R_IA64_VMS_ACC_LOAD, 0x7000000a) /* ACC =3D S + A */ - RELOC_NUMBER (R_IA64_VMS_ACC_ADD, 0x7000000b) /* ACC +=3D S + A */ - RELOC_NUMBER (R_IA64_VMS_ACC_SUB, 0x7000000c) /* ACC -=3D S + A */ - RELOC_NUMBER (R_IA64_VMS_ACC_MUL, 0x7000000d) /* ACC *=3D S + A */ - RELOC_NUMBER (R_IA64_VMS_ACC_DIV, 0x7000000e) /* ACC /=3D S + A */ - RELOC_NUMBER (R_IA64_VMS_ACC_AND, 0x7000000f) /* ACC &=3D S + A */ - RELOC_NUMBER (R_IA64_VMS_ACC_IOR, 0x70000010) /* ACC |=3D S + A */ - RELOC_NUMBER (R_IA64_VMS_ACC_EOR, 0x70000011) /* ACC ^=3D S + A */ - RELOC_NUMBER (R_IA64_VMS_ACC_ASH, 0x70000012) /* ACC >>=3D S + A */ - RELOC_NUMBER (R_IA64_VMS_ACC_STO8, 0x70000014) /* ACC */ - RELOC_NUMBER (R_IA64_VMS_ACC_STO16LSH, 0x70000015) /* ACC */ - RELOC_NUMBER (R_IA64_VMS_ACC_STO32LSH, 0x70000016) /* ACC */ - RELOC_NUMBER (R_IA64_VMS_ACC_STO64LSH, 0x70000017) /* ACC */ -END_RELOC_NUMBERS (R_IA64_max) - -#endif /* _ELF_IA64_H */ diff --git a/include/floatformat.h b/include/floatformat.h index ffe96a213a2..ff93671d5c0 100644 --- a/include/floatformat.h +++ b/include/floatformat.h @@ -127,9 +127,6 @@ extern const struct floatformat floatformat_m88110_ext; extern const struct floatformat floatformat_m88110_harris_ext; extern const struct floatformat floatformat_arm_ext_big; extern const struct floatformat floatformat_arm_ext_littlebyte_bigword; -/* IA-64 Floating Point register spilt into memory. */ -extern const struct floatformat floatformat_ia64_spill_big; -extern const struct floatformat floatformat_ia64_spill_little; /* IBM long double (double+double). */ extern const struct floatformat floatformat_ibm_long_double_big; extern const struct floatformat floatformat_ibm_long_double_little; diff --git a/include/longlong.h b/include/longlong.h index e4fe1d24144..38a9859b677 100644 --- a/include/longlong.h +++ b/include/longlong.h @@ -544,55 +544,6 @@ extern UDItype __umulsidi3 (USItype, USItype); __w; }) #endif /* __i960__ */ =20 -#if defined (__ia64) && W_TYPE_SIZE =3D=3D 64 -/* This form encourages gcc (pre-release 3.4 at least) to emit predicated - "sub r=3Dr,r" and "sub r=3Dr,r,1", giving a 2 cycle latency. The gener= ic - code using "al>=3D _c; \ - if (_x >=3D 1 << 4) \ - _x >>=3D 4, _c +=3D 4; \ - if (_x >=3D 1 << 2) \ - _x >>=3D 2, _c +=3D 2; \ - _c +=3D _x >> 1; \ - (count) =3D W_TYPE_SIZE - 1 - _c; \ - } while (0) -/* similar to what gcc does for __builtin_ffs, but 0 based rather than 1 - based, and we don't need a special case for x=3D=3D0 here */ -#define count_trailing_zeros(count, x) \ - do { \ - UWtype __ctz_x =3D (x); \ - __asm__ ("popcnt %0 =3D %1" \ - : "=3Dr" (count) \ - : "r" ((__ctz_x-1) & ~__ctz_x)); \ - } while (0) -#define UMUL_TIME 14 -#endif - #ifdef __loongarch__ # if W_TYPE_SIZE =3D=3D 32 # define count_leading_zeros(count, x) ((count) =3D __builtin_clz (x)) diff --git a/include/opcode/ia64.h b/include/opcode/ia64.h deleted file mode 100644 index 66fdda27b6d..00000000000 --- a/include/opcode/ia64.h +++ /dev/null @@ -1,428 +0,0 @@ -/* ia64.h -- Header file for ia64 opcode table - Copyright (C) 1998-2024 Free Software Foundation, Inc. - Contributed by David Mosberger-Tang - - This file is part of BFD, the Binary File Descriptor library. - - This program is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - This program is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program; if not, write to the Free Software Foundation, - Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ - -#ifndef opcode_ia64_h -#define opcode_ia64_h - -#include - -#include "bfd.h" - -#ifdef __cplusplus -extern "C" { -#endif - -typedef uint64_t ia64_insn; - -enum ia64_insn_type - { - IA64_TYPE_NIL =3D 0, /* illegal type */ - IA64_TYPE_A, /* integer alu (I- or M-unit) */ - IA64_TYPE_I, /* non-alu integer (I-unit) */ - IA64_TYPE_M, /* memory (M-unit) */ - IA64_TYPE_B, /* branch (B-unit) */ - IA64_TYPE_F, /* floating-point (F-unit) */ - IA64_TYPE_X, /* long encoding (X-unit) */ - IA64_TYPE_DYN, /* Dynamic opcode */ - IA64_NUM_TYPES - }; - -enum ia64_unit - { - IA64_UNIT_NIL =3D 0, /* illegal unit */ - IA64_UNIT_I, /* integer unit */ - IA64_UNIT_M, /* memory unit */ - IA64_UNIT_B, /* branching unit */ - IA64_UNIT_F, /* floating-point unit */ - IA64_UNIT_L, /* long "unit" */ - IA64_UNIT_X, /* may be integer or branch unit */ - IA64_NUM_UNITS - }; - -/* Changes to this enumeration must be propagated to the operand table in - bfd/cpu-ia64-opc.c - */ -enum ia64_opnd - { - IA64_OPND_NIL, /* no operand---MUST BE FIRST!*/ - - /* constants */ - IA64_OPND_AR_CSD, /* application register csd (ar.csd) */ - IA64_OPND_AR_CCV, /* application register ccv (ar.ccv) */ - IA64_OPND_AR_PFS, /* application register pfs (ar.pfs) */ - IA64_OPND_C1, /* the constant 1 */ - IA64_OPND_C8, /* the constant 8 */ - IA64_OPND_C16, /* the constant 16 */ - IA64_OPND_GR0, /* gr0 */ - IA64_OPND_IP, /* instruction pointer (ip) */ - IA64_OPND_PR, /* predicate register (pr) */ - IA64_OPND_PR_ROT, /* rotating predicate register (pr.rot) */ - IA64_OPND_PSR, /* processor status register (psr) */ - IA64_OPND_PSR_L, /* processor status register L (psr.l) */ - IA64_OPND_PSR_UM, /* processor status register UM (psr.um) */ - - /* register operands: */ - IA64_OPND_AR3, /* third application register # (bits 20-26) */ - IA64_OPND_B1, /* branch register # (bits 6-8) */ - IA64_OPND_B2, /* branch register # (bits 13-15) */ - IA64_OPND_CR3, /* third control register # (bits 20-26) */ - IA64_OPND_F1, /* first floating-point register # */ - IA64_OPND_F2, /* second floating-point register # */ - IA64_OPND_F3, /* third floating-point register # */ - IA64_OPND_F4, /* fourth floating-point register # */ - IA64_OPND_P1, /* first predicate # */ - IA64_OPND_P2, /* second predicate # */ - IA64_OPND_R1, /* first register # */ - IA64_OPND_R2, /* second register # */ - IA64_OPND_R3, /* third register # */ - IA64_OPND_R3_2, /* third register # (limited to gr0-gr3) */ - IA64_OPND_DAHR3, /* dahr reg # ( bits 23-25) */ - - /* memory operands: */ - IA64_OPND_MR3, /* memory at addr of third register # */ - - /* indirect operands: */ - IA64_OPND_CPUID_R3, /* cpuid[reg] */ - IA64_OPND_DBR_R3, /* dbr[reg] */ - IA64_OPND_DTR_R3, /* dtr[reg] */ - IA64_OPND_ITR_R3, /* itr[reg] */ - IA64_OPND_IBR_R3, /* ibr[reg] */ - IA64_OPND_MSR_R3, /* msr[reg] */ - IA64_OPND_PKR_R3, /* pkr[reg] */ - IA64_OPND_PMC_R3, /* pmc[reg] */ - IA64_OPND_PMD_R3, /* pmd[reg] */ - IA64_OPND_DAHR_R3, /* dahr[reg] */ - IA64_OPND_RR_R3, /* rr[reg] */ - - /* immediate operands: */ - IA64_OPND_CCNT5, /* 5-bit count (31 - bits 20-24) */ - IA64_OPND_CNT2a, /* 2-bit count (1 + bits 27-28) */ - IA64_OPND_CNT2b, /* 2-bit count (bits 27-28): 1, 2, 3 */ - IA64_OPND_CNT2c, /* 2-bit count (bits 30-31): 0, 7, 15, or 16 */ - IA64_OPND_CNT5, /* 5-bit count (bits 14-18) */ - IA64_OPND_CNT6, /* 6-bit count (bits 27-32) */ - IA64_OPND_CPOS6a, /* 6-bit count (63 - bits 20-25) */ - IA64_OPND_CPOS6b, /* 6-bit count (63 - bits 14-19) */ - IA64_OPND_CPOS6c, /* 6-bit count (63 - bits 31-36) */ - IA64_OPND_IMM1, /* signed 1-bit immediate (bit 36) */ - IA64_OPND_IMMU2, /* unsigned 2-bit immediate (bits 13-14) */ - IA64_OPND_IMMU5b, /* unsigned 5-bit immediate (32 + bits 14-18) */ - IA64_OPND_IMMU7a, /* unsigned 7-bit immediate (bits 13-19) */ - IA64_OPND_IMMU7b, /* unsigned 7-bit immediate (bits 20-26) */ - IA64_OPND_SOF, /* 8-bit stack frame size */ - IA64_OPND_SOL, /* 8-bit size of locals */ - IA64_OPND_SOR, /* 6-bit number of rotating registers (scaled by 8) */ - IA64_OPND_IMM8, /* signed 8-bit immediate (bits 13-19 & 36) */ - IA64_OPND_IMM8U4, /* cmp4*u signed 8-bit immediate (bits 13-19 & 36) */ - IA64_OPND_IMM8M1, /* signed 8-bit immediate -1 (bits 13-19 & 36) */ - IA64_OPND_IMM8M1U4, /* cmp4*u signed 8-bit immediate -1 (bits 13-19 & = 36)*/ - IA64_OPND_IMM8M1U8, /* cmp*u signed 8-bit immediate -1 (bits 13-19 & 3= 6) */ - IA64_OPND_IMMU9, /* unsigned 9-bit immediate (bits 33-34, 20-26) */ - IA64_OPND_IMM9a, /* signed 9-bit immediate (bits 6-12, 27, 36) */ - IA64_OPND_IMM9b, /* signed 9-bit immediate (bits 13-19, 27, 36) */ - IA64_OPND_IMM14, /* signed 14-bit immediate (bits 13-19, 27-32, 36) */ - IA64_OPND_IMMU16, /* unsigned 16-bit immediate (bits 6-9, 12-22, 36) */ - IA64_OPND_IMM17, /* signed 17-bit immediate (2*bits 6-12, 24-31, 36) */ - IA64_OPND_IMMU19, /* unsigned 19-bit immediate (bits 6-9, 12-25, 36) */ - IA64_OPND_IMMU21, /* unsigned 21-bit immediate (bits 6-25, 36) */ - IA64_OPND_IMM22, /* signed 22-bit immediate (bits 13-19, 22-36) */ - IA64_OPND_IMMU24, /* unsigned 24-bit immediate (bits 6-26, 31-32, 36) = */ - IA64_OPND_IMM44, /* signed 44-bit immediate (2^16*bits 6-32, 36) */ - IA64_OPND_IMMU62, /* unsigned 62-bit immediate */ - IA64_OPND_IMMU64, /* unsigned 64-bit immediate (lotsa bits...) */ - IA64_OPND_INC3, /* signed 3-bit (bits 13-15): +/-1, 4, 8, 16 */ - IA64_OPND_LEN4, /* 4-bit count (bits 27-30 + 1) */ - IA64_OPND_LEN6, /* 6-bit count (bits 27-32 + 1) */ - IA64_OPND_MBTYPE4, /* 4-bit mux type (bits 20-23) */ - IA64_OPND_MHTYPE8, /* 8-bit mux type (bits 20-27) */ - IA64_OPND_POS6, /* 6-bit count (bits 14-19) */ - IA64_OPND_TAG13, /* signed 13-bit tag (ip + 16*bits 6-12, 33-34) */ - IA64_OPND_TAG13b, /* signed 13-bit tag (ip + 16*bits 24-32) */ - IA64_OPND_TGT25, /* signed 25-bit (ip + 16*bits 6-25, 36) */ - IA64_OPND_TGT25b, /* signed 25-bit (ip + 16*bits 6-12, 20-32, 36) */ - IA64_OPND_TGT25c, /* signed 25-bit (ip + 16*bits 13-32, 36) */ - IA64_OPND_TGT64, /* 64-bit (ip + 16*bits 13-32, 36, 2-40(L)) */ - IA64_OPND_LDXMOV, /* any symbol, generates R_IA64_LDXMOV. */ - - IA64_OPND_CNT6a, /* 6-bit count (bits 6-11) */ - IA64_OPND_STRD5b, /* 5-bit stride (bits 13-17) */ - - IA64_OPND_COUNT /* # of operand types (MUST BE LAST!) */ - }; - -enum ia64_dependency_mode -{ - IA64_DV_RAW, - IA64_DV_WAW, - IA64_DV_WAR, -}; - -enum ia64_dependency_semantics -{ - IA64_DVS_NONE, - IA64_DVS_IMPLIED, - IA64_DVS_IMPLIEDF, - IA64_DVS_DATA, - IA64_DVS_INSTR, - IA64_DVS_SPECIFIC, - IA64_DVS_STOP, - IA64_DVS_OTHER, -}; - -enum ia64_resource_specifier -{ - IA64_RS_ANY, - IA64_RS_AR_K, - IA64_RS_AR_UNAT, - IA64_RS_AR, /* 8-15, 20, 22-23, 31, 33-35, 37-39, 41-43, 45-47, 67-111 */ - IA64_RS_ARb, /* 48-63, 112-127 */ - IA64_RS_BR, - IA64_RS_CFM, - IA64_RS_CPUID, - IA64_RS_CR_IIB, - IA64_RS_CR_IRR, - IA64_RS_CR_LRR, - IA64_RS_CR, /* 3-7,10-15,18,28-63,75-79,82-127 */ - IA64_RS_DAHR, - IA64_RS_DBR, - IA64_RS_FR, - IA64_RS_FRb, - IA64_RS_GR0, - IA64_RS_GR, - IA64_RS_IBR, - IA64_RS_INSERVICE, /* CR[EOI] or CR[IVR] */ - IA64_RS_MSR, - IA64_RS_PKR, - IA64_RS_PMC, - IA64_RS_PMD, - IA64_RS_PR, /* non-rotating, 1-15 */ - IA64_RS_PRr, /* rotating, 16-62 */ - IA64_RS_PR63, - IA64_RS_RR, - - IA64_RS_ARX, /* ARs not in RS_AR or RS_ARb */ - IA64_RS_CRX, /* CRs not in RS_CR */ - IA64_RS_PSR, /* PSR bits */ - IA64_RS_RSE, /* implementation-specific RSE resources */ - IA64_RS_AR_FPSR, - -}; - -enum ia64_rse_resource -{ - IA64_RSE_N_STACKED_PHYS, - IA64_RSE_BOF, - IA64_RSE_STORE_REG, - IA64_RSE_LOAD_REG, - IA64_RSE_BSPLOAD, - IA64_RSE_RNATBITINDEX, - IA64_RSE_CFLE, - IA64_RSE_NDIRTY, -}; - -/* Information about a given resource dependency */ -struct ia64_dependency -{ - /* Name of the resource */ - const char *name; - /* Does this dependency need further specification? */ - enum ia64_resource_specifier specifier; - /* Mode of dependency */ - enum ia64_dependency_mode mode; - /* Dependency semantics */ - enum ia64_dependency_semantics semantics; - /* Register index, if applicable (distinguishes AR, CR, and PSR deps) */ -#define REG_NONE (-1) - int regindex; - /* Special info on semantics */ - const char *info; -}; - -/* Two arrays of indexes into the ia64_dependency table. - chks are dependencies to check for conflicts when an opcode is - encountered; regs are dependencies to register (mark as used) when an - opcode is used. chks correspond to readers (RAW) or writers (WAW or - WAR) of a resource, while regs correspond to writers (RAW or WAW) and - readers (WAR) of a resource. */ -struct ia64_opcode_dependency -{ - int nchks; - const unsigned short *chks; - int nregs; - const unsigned short *regs; -}; - -/* encode/extract the note/index for a dependency */ -#define RDEP(N,X) (((N)<<11)|(X)) -#define NOTE(X) (((X)>>11)&0x1F) -#define DEP(X) ((X)&0x7FF) - -/* A template descriptor describes the execution units that are active - for each of the three slots. It also specifies the location of - instruction group boundaries that may be present between two slots. */ -struct ia64_templ_desc - { - int group_boundary; /* 0=3Dno boundary, 1=3Dbetween slot 0 & 1, etc. */ - enum ia64_unit exec_unit[3]; - const char *name; - }; - -/* The opcode table is an array of struct ia64_opcode. */ - -struct ia64_opcode - { - /* The opcode name. */ - const char *name; - - /* The type of the instruction: */ - enum ia64_insn_type type; - - /* Number of output operands: */ - int num_outputs; - - /* The opcode itself. Those bits which will be filled in with - operands are zeroes. */ - ia64_insn opcode; - - /* The opcode mask. This is used by the disassembler. This is a - mask containing ones indicating those bits which must match the - opcode field, and zeroes indicating those bits which need not - match (and are presumably filled in by operands). */ - ia64_insn mask; - - /* An array of operand codes. Each code is an index into the - operand table. They appear in the order which the operands must - appear in assembly code, and are terminated by a zero. */ - enum ia64_opnd operands[5]; - - /* One bit flags for the opcode. These are primarily used to - indicate specific processors and environments support the - instructions. The defined values are listed below. */ - unsigned int flags; - - /* Used by ia64_find_next_opcode (). */ - short ent_index; - - /* Opcode dependencies. */ - const struct ia64_opcode_dependency *dependencies; - }; - -/* Values defined for the flags field of a struct ia64_opcode. */ - -#define IA64_OPCODE_FIRST (1<<0) /* must be first in an insn group */ -#define IA64_OPCODE_X_IN_MLX (1<<1) /* insn is allowed in X slot of MLX */ -#define IA64_OPCODE_LAST (1<<2) /* must be last in an insn group */ -#define IA64_OPCODE_PRIV (1<<3) /* privileged instruct */ -#define IA64_OPCODE_SLOT2 (1<<4) /* insn allowed in slot 2 only */ -#define IA64_OPCODE_NO_PRED (1<<5) /* insn cannot be predicated */ -#define IA64_OPCODE_PSEUDO (1<<6) /* insn is a pseudo-op */ -#define IA64_OPCODE_F2_EQ_F3 (1<<7) /* constraint: F2 =3D=3D F3 */ -#define IA64_OPCODE_LEN_EQ_64MCNT (1<<8) /* constraint: LEN =3D=3D 64-CNT = */ -#define IA64_OPCODE_MOD_RRBS (1<<9) /* modifies all rrbs in CFM */ -#define IA64_OPCODE_POSTINC (1<<10) /* postincrement MR3 operand */ - -/* A macro to extract the major opcode from an instruction. */ -#define IA64_OP(i) (((i) >> 37) & 0xf) - -enum ia64_operand_class - { - IA64_OPND_CLASS_CST, /* constant */ - IA64_OPND_CLASS_REG, /* register */ - IA64_OPND_CLASS_IND, /* indirect register */ - IA64_OPND_CLASS_ABS, /* absolute value */ - IA64_OPND_CLASS_REL, /* IP-relative value */ - }; - -/* The operands table is an array of struct ia64_operand. */ - -struct ia64_operand -{ - enum ia64_operand_class op_class; - - /* Set VALUE as the operand bits for the operand of type SELF in the - instruction pointed to by CODE. If an error occurs, *CODE is not - modified and the returned string describes the cause of the - error. If no error occurs, NULL is returned. */ - const char *(*insert) (const struct ia64_operand *self, ia64_insn value, - ia64_insn *code); - - /* Extract the operand bits for an operand of type SELF from - instruction CODE store them in *VALUE. If an error occurs, the - cause of the error is described by the string returned. If no - error occurs, NULL is returned. */ - const char *(*extract) (const struct ia64_operand *self, ia64_insn code, - ia64_insn *value); - - /* A string whose meaning depends on the operand class. */ - - const char *str; - - struct bit_field - { - /* The number of bits in the operand. */ - int bits; - - /* How far the operand is left shifted in the instruction. */ - int shift; - } - field[4]; /* no operand has more than this many bit-fields */ - - unsigned int flags; - - const char *desc; /* brief description */ -}; - -/* Values defined for the flags field of a struct ia64_operand. */ - -/* Disassemble as signed decimal (instead of hex): */ -#define IA64_OPND_FLAG_DECIMAL_SIGNED (1<<0) -/* Disassemble as unsigned decimal (instead of hex): */ -#define IA64_OPND_FLAG_DECIMAL_UNSIGNED (1<<1) - -extern const struct ia64_templ_desc ia64_templ_desc[16]; - -/* The tables are sorted by major opcode number and are otherwise in - the order in which the disassembler should consider instructions. */ -extern struct ia64_opcode ia64_opcodes_a[]; -extern struct ia64_opcode ia64_opcodes_i[]; -extern struct ia64_opcode ia64_opcodes_m[]; -extern struct ia64_opcode ia64_opcodes_b[]; -extern struct ia64_opcode ia64_opcodes_f[]; -extern struct ia64_opcode ia64_opcodes_d[]; - - -extern struct ia64_opcode *ia64_find_opcode (const char *); -extern struct ia64_opcode *ia64_find_next_opcode (struct ia64_opcode *); - -extern struct ia64_opcode *ia64_dis_opcode (ia64_insn, - enum ia64_insn_type); - -extern void ia64_free_opcode (struct ia64_opcode *); -extern const struct ia64_dependency *ia64_find_dependency (int); - -/* To avoid circular library dependencies, this array is implemented - in bfd/cpu-ia64-opc.c: */ -extern const struct ia64_operand elf64_ia64_operands[IA64_OPND_COUNT]; - -#ifdef __cplusplus -} -#endif - -#endif /* opcode_ia64_h */ diff --git a/ld/Makefile.am b/ld/Makefile.am index f9ee05b1400..9781ed02a78 100644 --- a/ld/Makefile.am +++ b/ld/Makefile.am @@ -425,9 +425,6 @@ ALL_64_EMULATION_SOURCES =3D \ eelf32ltsmipn32_fbsd.c \ eelf32mipswindiss.c \ eelf64_aix.c \ - eelf64_ia64.c \ - eelf64_ia64_fbsd.c \ - eelf64_ia64_vms.c \ eelf64_s390.c \ eelf64_sparc.c \ eelf64_sparc_fbsd.c \ diff --git a/ld/Makefile.in b/ld/Makefile.in index 8350f00a521..c4aa787d6b5 100644 --- a/ld/Makefile.in +++ b/ld/Makefile.in @@ -935,9 +935,6 @@ ALL_64_EMULATION_SOURCES =3D \ eelf32ltsmipn32_fbsd.c \ eelf32mipswindiss.c \ eelf64_aix.c \ - eelf64_ia64.c \ - eelf64_ia64_fbsd.c \ - eelf64_ia64_vms.c \ eelf64_s390.c \ eelf64_sparc.c \ eelf64_sparc_fbsd.c \ @@ -1443,9 +1440,6 @@ distclean-compile: @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf32xtensa.Po@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf32z80.Po@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf64_aix.Po@am__quote@ -@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf64_ia64.Po@am__quote@ -@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf64_ia64_fbsd.Po@am__q= uote@ -@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf64_ia64_vms.Po@am__qu= ote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf64_s390.Po@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf64_sparc.Po@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf64_sparc_fbsd.Po@am__= quote@ diff --git a/ld/configure b/ld/configure index ba0024699d4..d7bbb400893 100755 --- a/ld/configure +++ b/ld/configure @@ -6567,10 +6567,6 @@ haiku*) hpux10.20* | hpux11*) lt_cv_file_magic_cmd=3D/usr/bin/file case $host_cpu in - ia64*) - lt_cv_deplibs_check_method=3D'file_magic (s[0-9][0-9][0-9]|ELF-[0-9][0= -9]) shared object file - IA64' - lt_cv_file_magic_test_file=3D/usr/lib/hpux32/libc.so - ;; hppa*64*) lt_cv_deplibs_check_method=3D'file_magic (s[0-9][0-9][0-9]|ELF[ -][0-9= ][0-9])(-bit)?( [LM]SB)? shared object( file)?[, -]* PA-RISC [0-9]\.[0-9]' lt_cv_file_magic_test_file=3D/usr/lib/pa20_64/libc.sl @@ -7129,11 +7125,6 @@ aix*) cygwin* | mingw* | pw32* | cegcc*) symcode=3D'[ABCDGISTW]' ;; -hpux*) - if test "$host_cpu" =3D ia64; then - symcode=3D'[ABCDEGRST]' - fi - ;; irix* | nonstopux*) symcode=3D'[BCDEGRST]' ;; @@ -7164,7 +7155,7 @@ case `$NM -V 2>&1` in esac =20 # Transform an extracted symbol line into a proper C declaration. -# Some systems (esp. on ia64) link data and code symbols differently, +# Some systems link data and code symbols differently, # so use this general approach. lt_cv_sys_global_symbol_to_cdecl=3D"sed -n -e 's/^T .* \(.*\)$/extern int = \1();/p' -e 's/^$symcode* .* \(.*\)$/extern char \1;/p'" =20 @@ -7364,25 +7355,6 @@ test "x$enable_libtool_lock" !=3D xno && enable_libt= ool_lock=3Dyes # Some flags need to be propagated to the compiler or linker for good # libtool support. case $host in -ia64-*-hpux*) - # Find out which ABI we are using. - echo 'int i;' > conftest.$ac_ext - if { { eval echo "\"\$as_me\":${as_lineno-$LINENO}: \"$ac_compile\""; } = >&5 - (eval $ac_compile) 2>&5 - ac_status=3D$? - $as_echo "$as_me:${as_lineno-$LINENO}: \$? =3D $ac_status" >&5 - test $ac_status =3D 0; }; then - case `/usr/bin/file conftest.$ac_objext` in - *ELF-32*) - HPUX_IA64_MODE=3D"32" - ;; - *ELF-64*) - HPUX_IA64_MODE=3D"64" - ;; - esac - fi - rm -rf conftest* - ;; *-*-irix6*) # Find out which ABI we are using. echo '#line '$LINENO' "configure"' > conftest.$ac_ext @@ -8718,10 +8690,6 @@ $as_echo_n "checking for $compiler option to produce= PIC... " >&6; } case $host_os in aix*) # All AIX code is PIC. - if test "$host_cpu" =3D ia64; then - # AIX 5 now supports IA64 processor - lt_prog_compiler_static=3D'-Bstatic' - fi lt_prog_compiler_pic=3D'-fPIC' ;; =20 @@ -8818,12 +8786,7 @@ $as_echo_n "checking for $compiler option to produce= PIC... " >&6; } case $host_os in aix*) lt_prog_compiler_wl=3D'-Wl,' - if test "$host_cpu" =3D ia64; then - # AIX 5 now supports IA64 processor - lt_prog_compiler_static=3D'-Bstatic' - else - lt_prog_compiler_static=3D'-bnso -bI:/lib/syscalls.exp' - fi + lt_prog_compiler_static=3D'-bnso -bI:/lib/syscalls.exp' ;; =20 mingw* | cygwin* | pw32* | os2* | cegcc*) @@ -8837,7 +8800,7 @@ $as_echo_n "checking for $compiler option to produce = PIC... " >&6; } # PIC is the default for IA64 HP-UX and 64-bit HP-UX, but # not for PA HP-UX. case $host_cpu in - hppa*64*|ia64*) + hppa*64*) # +Z the default ;; *) @@ -9362,7 +9325,6 @@ $as_echo_n "checking whether the $compiler linker ($L= D) supports shared librarie case $host_os in aix[3-9]*) # On AIX/PPC, the GNU linker is very broken - if test "$host_cpu" !=3D ia64; then ld_shlibs=3Dno cat <<_LT_EOF 1>&2 =20 @@ -9374,7 +9336,6 @@ $as_echo_n "checking whether the $compiler linker ($L= D) supports shared librarie *** You will then need to restart the configuration process. =20 _LT_EOF - fi ;; =20 amigaos*) @@ -9470,10 +9431,6 @@ _LT_EOF # Portland Group f77 and f90 compilers whole_archive_flag_spec=3D'${wl}--whole-archive`for conv in $convenienc= e\"\"; do test -n \"$conv\" && new_convenience=3D\"$new_convenience,$conv\= "; done; func_echo_all \"$new_convenience\"` ${wl}--no-whole-archive' tmp_addflag=3D' $pic_flag -Mnomain' ;; - ecc*,ia64* | icc*,ia64*) # Intel C compiler on ia64 - tmp_addflag=3D' -i_dynamic' ;; - efc*,ia64* | ifort*,ia64*) # Intel Fortran compiler on ia64 - tmp_addflag=3D' -i_dynamic -nofor_main' ;; ifc* | ifort*) # Intel Fortran compiler tmp_addflag=3D' -nofor_main' ;; lf95*) # Lahey Fortran 8.1 @@ -9627,13 +9584,6 @@ _LT_EOF ;; =20 aix[4-9]*) - if test "$host_cpu" =3D ia64; then - # On IA64, the linker does run time linking by default, so we don't - # have to do anything special. - aix_use_runtimelinking=3Dno - exp_sym_flag=3D'-Bexport' - no_entry_flag=3D"" - else # If we're using GNU nm, then we don't want the "-C" option. # -C means demangle to AIX nm, but means don't demangle with GNU nm # Also, AIX nm treats weak defined symbols like other global @@ -9660,7 +9610,6 @@ _LT_EOF =20 exp_sym_flag=3D'-bexport' no_entry_flag=3D'-bnoentry' - fi =20 # When large executables or shared objects are built, AIX ld can # have problems creating the table of contents. If linking a library @@ -9703,17 +9652,11 @@ _LT_EOF fi else # not using gcc - if test "$host_cpu" =3D ia64; then - # VisualAge C++, Version 5.5 for AIX 5L for IA-64, Beta 3 Release - # chokes on -Wl,-G. The following line is correct: - shared_flag=3D'-G' - else if test "$aix_use_runtimelinking" =3D yes; then shared_flag=3D'${wl}-G' else shared_flag=3D'${wl}-bM:SRE' fi - fi fi =20 export_dynamic_flag_spec=3D'${wl}-bexpall' @@ -9759,11 +9702,6 @@ if test -z "$aix_libpath"; then aix_libpath=3D"/usr/= lib:/lib"; fi hardcode_libdir_flag_spec=3D'${wl}-blibpath:$libdir:'"$aix_libpath" archive_expsym_cmds=3D'$CC -o $output_objdir/$soname $libobjs $dep= libs '"\${wl}$no_entry_flag"' $compiler_flags `if test "x${allow_undefined_= flag}" !=3D "x"; then func_echo_all "${wl}${allow_undefined_flag}"; else :;= fi` '"\${wl}$exp_sym_flag:\$export_symbols $shared_flag" else - if test "$host_cpu" =3D ia64; then - hardcode_libdir_flag_spec=3D'${wl}-R $libdir:/usr/lib:/lib' - allow_undefined_flag=3D"-z nodefs" - archive_expsym_cmds=3D"\$CC $shared_flag"' -o $output_objdir/$soname $l= ibobjs $deplibs '"\${wl}$no_entry_flag"' $compiler_flags ${wl}${allow_undef= ined_flag} '"\${wl}$exp_sym_flag:\$export_symbols" - else # Determine the default libpath from the value encoded in an # empty executable. cat confdefs.h - <<_ACEOF >conftest.$ac_ext @@ -9811,7 +9749,6 @@ if test -z "$aix_libpath"; then aix_libpath=3D"/usr/l= ib:/lib"; fi archive_cmds_need_lc=3Dyes # This is similar to how AIX traditionally builds its shared libraries. archive_expsym_cmds=3D"\$CC $shared_flag"' -o $output_objdir/$soname $l= ibobjs $deplibs ${wl}-bnoentry $compiler_flags ${wl}-bE:$export_symbols${al= low_undefined_flag}~$AR $AR_FLAGS $output_objdir/$libname$release.a $output= _objdir/$soname' - fi fi ;; =20 @@ -9960,9 +9897,6 @@ if test -z "$aix_libpath"; then aix_libpath=3D"/usr/l= ib:/lib"; fi hppa*64*) archive_cmds=3D'$CC -shared ${wl}+h ${wl}$soname ${wl}+nodefaultrpath -= o $lib $libobjs $deplibs $compiler_flags' ;; - ia64*) - archive_cmds=3D'$CC -shared -fPIC ${wl}+h ${wl}$soname ${wl}+nodefaultr= path -o $lib $libobjs $deplibs $compiler_flags' - ;; *) archive_cmds=3D'$CC -shared -fPIC ${wl}+h ${wl}$soname ${wl}+b ${wl}$in= stall_libdir -o $lib $libobjs $deplibs $compiler_flags' ;; @@ -9972,9 +9906,6 @@ if test -z "$aix_libpath"; then aix_libpath=3D"/usr/l= ib:/lib"; fi hppa*64*) archive_cmds=3D'$CC -b ${wl}+h ${wl}$soname ${wl}+nodefaultrpath -o $li= b $libobjs $deplibs $compiler_flags' ;; - ia64*) - archive_cmds=3D'$CC -b ${wl}+h ${wl}$soname ${wl}+nodefaultrpath -o $li= b $libobjs $deplibs $compiler_flags' - ;; *) =20 # Older versions of the 11.00 compiler do not understand -b yet @@ -10024,7 +9955,7 @@ fi hardcode_libdir_separator=3D: =20 case $host_cpu in - hppa*64*|ia64*) + hppa*64*) hardcode_direct=3Dno hardcode_shlibpath_var=3Dno ;; @@ -10661,11 +10592,6 @@ aix[4-9]*) need_lib_prefix=3Dno need_version=3Dno hardcode_into_libs=3Dyes - if test "$host_cpu" =3D ia64; then - # AIX 5 supports IA64 - library_names_spec=3D'${libname}${release}${shared_ext}$major ${libnam= e}${release}${shared_ext}$versuffix $libname${shared_ext}' - shlibpath_var=3DLD_LIBRARY_PATH - else # With GCC up to 2.95.x, collect2 would create an import file # for dependence libraries. The import file would start with # the line `#! .'. This would cause the generated library to @@ -10697,7 +10623,6 @@ aix[4-9]*) soname_spec=3D'${libname}${release}${shared_ext}$major' fi shlibpath_var=3DLIBPATH - fi ;; =20 amigaos*) @@ -10874,21 +10799,6 @@ hpux9* | hpux10* | hpux11*) need_lib_prefix=3Dno need_version=3Dno case $host_cpu in - ia64*) - shrext_cmds=3D'.so' - hardcode_into_libs=3Dyes - dynamic_linker=3D"$host_os dld.so" - shlibpath_var=3DLD_LIBRARY_PATH - shlibpath_overrides_runpath=3Dyes # Unless +noenvvar is specified. - library_names_spec=3D'${libname}${release}${shared_ext}$versuffix ${li= bname}${release}${shared_ext}$major $libname${shared_ext}' - soname_spec=3D'${libname}${release}${shared_ext}$major' - if test "X$HPUX_IA64_MODE" =3D X32; then - sys_lib_search_path_spec=3D"/usr/lib/hpux32 /usr/local/lib/hpux32 /u= sr/local/lib" - else - sys_lib_search_path_spec=3D"/usr/lib/hpux64 /usr/local/lib/hpux64" - fi - sys_lib_dlsearch_path_spec=3D$sys_lib_search_path_spec - ;; hppa*64*) shrext_cmds=3D'.sl' hardcode_into_libs=3Dyes @@ -11979,7 +11889,7 @@ $as_echo_n "checking whether to build shared librar= ies... " >&6; } ;; =20 aix[4-9]*) - if test "$host_cpu" !=3D ia64 && test "$aix_use_runtimelinking" =3D no= ; then + if test "$aix_use_runtimelinking" =3D no ; then test "$enable_shared" =3D yes && enable_static=3Dno fi ;; @@ -12435,13 +12345,6 @@ $as_echo_n "checking whether the $compiler linker = ($LD) supports shared librarie ld_shlibs_CXX=3Dno ;; aix[4-9]*) - if test "$host_cpu" =3D ia64; then - # On IA64, the linker does run time linking by default, so we do= n't - # have to do anything special. - aix_use_runtimelinking=3Dno - exp_sym_flag=3D'-Bexport' - no_entry_flag=3D"" - else aix_use_runtimelinking=3Dno =20 # Test if we are trying to use run time linking or normal @@ -12461,7 +12364,6 @@ $as_echo_n "checking whether the $compiler linker (= $LD) supports shared librarie =20 exp_sym_flag=3D'-bexport' no_entry_flag=3D'-bnoentry' - fi =20 # When large executables or shared objects are built, AIX ld can # have problems creating the table of contents. If linking a libr= ary @@ -12503,17 +12405,11 @@ $as_echo_n "checking whether the $compiler linker= ($LD) supports shared librarie fi else # not using gcc - if test "$host_cpu" =3D ia64; then - # VisualAge C++, Version 5.5 for AIX 5L for IA-64, Beta 3 Release - # chokes on -Wl,-G. The following line is correct: - shared_flag=3D'-G' - else if test "$aix_use_runtimelinking" =3D yes; then shared_flag=3D'${wl}-G' else shared_flag=3D'${wl}-bM:SRE' fi - fi fi =20 export_dynamic_flag_spec_CXX=3D'${wl}-bexpall' @@ -12561,11 +12457,6 @@ if test -z "$aix_libpath"; then aix_libpath=3D"/us= r/lib:/lib"; fi =20 archive_expsym_cmds_CXX=3D'$CC -o $output_objdir/$soname $libobj= s $deplibs '"\${wl}$no_entry_flag"' $compiler_flags `if test "x${allow_unde= fined_flag}" !=3D "x"; then func_echo_all "${wl}${allow_undefined_flag}"; e= lse :; fi` '"\${wl}$exp_sym_flag:\$export_symbols $shared_flag" else - if test "$host_cpu" =3D ia64; then - hardcode_libdir_flag_spec_CXX=3D'${wl}-R $libdir:/usr/lib:/lib' - allow_undefined_flag_CXX=3D"-z nodefs" - archive_expsym_cmds_CXX=3D"\$CC $shared_flag"' -o $output_objdir/$son= ame $libobjs $deplibs '"\${wl}$no_entry_flag"' $compiler_flags ${wl}${allow= _undefined_flag} '"\${wl}$exp_sym_flag:\$export_symbols" - else # Determine the default libpath from the value encoded in an # empty executable. cat confdefs.h - <<_ACEOF >conftest.$ac_ext @@ -12614,7 +12505,6 @@ if test -z "$aix_libpath"; then aix_libpath=3D"/usr= /lib:/lib"; fi # This is similar to how AIX traditionally builds its shared # libraries. archive_expsym_cmds_CXX=3D"\$CC $shared_flag"' -o $output_objdir/$son= ame $libobjs $deplibs ${wl}-bnoentry $compiler_flags ${wl}-bE:$export_symbo= ls${allow_undefined_flag}~$AR $AR_FLAGS $output_objdir/$libname$release.a $= output_objdir/$soname' - fi fi ;; =20 @@ -12782,7 +12672,7 @@ if test -z "$aix_libpath"; then aix_libpath=3D"/usr= /lib:/lib"; fi hardcode_libdir_separator_CXX=3D: =20 case $host_cpu in - hppa*64*|ia64*) + hppa*64*) ;; *) export_dynamic_flag_spec_CXX=3D'${wl}-E' @@ -12790,7 +12680,7 @@ if test -z "$aix_libpath"; then aix_libpath=3D"/usr= /lib:/lib"; fi esac fi case $host_cpu in - hppa*64*|ia64*) + hppa*64*) hardcode_direct_CXX=3Dno hardcode_shlibpath_var_CXX=3Dno ;; @@ -12813,9 +12703,6 @@ if test -z "$aix_libpath"; then aix_libpath=3D"/usr= /lib:/lib"; fi hppa*64*) archive_cmds_CXX=3D'$CC -b ${wl}+h ${wl}$soname ${wl}+nodefaultrp= ath -o $lib $predep_objects $libobjs $deplibs $postdep_objects $compiler_fl= ags' ;; - ia64*) - archive_cmds_CXX=3D'$CC -b ${wl}+h ${wl}$soname ${wl}+nodefaultrp= ath -o $lib $predep_objects $libobjs $deplibs $postdep_objects $compiler_fl= ags' - ;; *) archive_cmds_CXX=3D'$CC -b ${wl}+h ${wl}$soname ${wl}+b ${wl}$ins= tall_libdir -o $lib $predep_objects $libobjs $deplibs $postdep_objects $com= piler_flags' ;; @@ -12837,9 +12724,6 @@ if test -z "$aix_libpath"; then aix_libpath=3D"/usr= /lib:/lib"; fi hppa*64*) archive_cmds_CXX=3D'$CC -shared -nostdlib -fPIC ${wl}+h ${wl}= $soname ${wl}+nodefaultrpath -o $lib $predep_objects $libobjs $deplibs $pos= tdep_objects $compiler_flags' ;; - ia64*) - archive_cmds_CXX=3D'$CC -shared -nostdlib -fPIC ${wl}+h ${wl}= $soname ${wl}+nodefaultrpath -o $lib $predep_objects $libobjs $deplibs $pos= tdep_objects $compiler_flags' - ;; *) archive_cmds_CXX=3D'$CC -shared -nostdlib -fPIC ${wl}+h ${wl}= $soname ${wl}+b ${wl}$install_libdir -o $lib $predep_objects $libobjs $depl= ibs $postdep_objects $compiler_flags' ;; @@ -12935,9 +12819,6 @@ if test -z "$aix_libpath"; then aix_libpath=3D"/usr= /lib:/lib"; fi ;; *) # Version 8.0 or newer tmp_idyn=3D - case $host_cpu in - ia64*) tmp_idyn=3D' -i_dynamic';; - esac archive_cmds_CXX=3D'$CC -shared'"$tmp_idyn"' $libobjs $deplibs $c= ompiler_flags ${wl}-soname $wl$soname -o $lib' archive_expsym_cmds_CXX=3D'$CC -shared'"$tmp_idyn"' $libobjs $deplibs $c= ompiler_flags ${wl}-soname $wl$soname ${wl}-retain-symbols-file $wl$export_= symbols -o $lib' ;; @@ -13583,10 +13464,6 @@ $as_echo_n "checking for $compiler option to produ= ce PIC... " >&6; } case $host_os in aix*) # All AIX code is PIC. - if test "$host_cpu" =3D ia64; then - # AIX 5 now supports IA64 processor - lt_prog_compiler_static_CXX=3D'-Bstatic' - fi lt_prog_compiler_pic_CXX=3D'-fPIC' ;; =20 @@ -13663,12 +13540,7 @@ $as_echo_n "checking for $compiler option to produ= ce PIC... " >&6; } case $host_os in aix[4-9]*) # All AIX code is PIC. - if test "$host_cpu" =3D ia64; then - # AIX 5 now supports IA64 processor - lt_prog_compiler_static_CXX=3D'-Bstatic' - else - lt_prog_compiler_static_CXX=3D'-bnso -bI:/lib/syscalls.exp' - fi + lt_prog_compiler_static_CXX=3D'-bnso -bI:/lib/syscalls.exp' ;; chorus*) case $cc_basename in @@ -13699,15 +13571,13 @@ $as_echo_n "checking for $compiler option to prod= uce PIC... " >&6; } CC*) lt_prog_compiler_wl_CXX=3D'-Wl,' lt_prog_compiler_static_CXX=3D'${wl}-a ${wl}archive' - if test "$host_cpu" !=3D ia64; then - lt_prog_compiler_pic_CXX=3D'+Z' - fi + lt_prog_compiler_pic_CXX=3D'+Z' ;; aCC*) lt_prog_compiler_wl_CXX=3D'-Wl,' lt_prog_compiler_static_CXX=3D'${wl}-a ${wl}archive' case $host_cpu in - hppa*64*|ia64*) + hppa*64*) # +Z the default ;; *) @@ -14338,11 +14208,6 @@ aix[4-9]*) need_lib_prefix=3Dno need_version=3Dno hardcode_into_libs=3Dyes - if test "$host_cpu" =3D ia64; then - # AIX 5 supports IA64 - library_names_spec=3D'${libname}${release}${shared_ext}$major ${libnam= e}${release}${shared_ext}$versuffix $libname${shared_ext}' - shlibpath_var=3DLD_LIBRARY_PATH - else # With GCC up to 2.95.x, collect2 would create an import file # for dependence libraries. The import file would start with # the line `#! .'. This would cause the generated library to @@ -14374,7 +14239,6 @@ aix[4-9]*) soname_spec=3D'${libname}${release}${shared_ext}$major' fi shlibpath_var=3DLIBPATH - fi ;; =20 amigaos*) @@ -14549,21 +14413,6 @@ hpux9* | hpux10* | hpux11*) need_lib_prefix=3Dno need_version=3Dno case $host_cpu in - ia64*) - shrext_cmds=3D'.so' - hardcode_into_libs=3Dyes - dynamic_linker=3D"$host_os dld.so" - shlibpath_var=3DLD_LIBRARY_PATH - shlibpath_overrides_runpath=3Dyes # Unless +noenvvar is specified. - library_names_spec=3D'${libname}${release}${shared_ext}$versuffix ${li= bname}${release}${shared_ext}$major $libname${shared_ext}' - soname_spec=3D'${libname}${release}${shared_ext}$major' - if test "X$HPUX_IA64_MODE" =3D X32; then - sys_lib_search_path_spec=3D"/usr/lib/hpux32 /usr/local/lib/hpux32 /u= sr/local/lib" - else - sys_lib_search_path_spec=3D"/usr/lib/hpux64 /usr/local/lib/hpux64" - fi - sys_lib_dlsearch_path_spec=3D$sys_lib_search_path_spec - ;; hppa*64*) shrext_cmds=3D'.sl' hardcode_into_libs=3Dyes diff --git a/ld/configure.tgt b/ld/configure.tgt index f937f78b876..56c9eca2822 100644 --- a/ld/configure.tgt +++ b/ld/configure.tgt @@ -453,21 +453,6 @@ i[3-7]86-*-chaos) targ_emul=3Delf_i386_chaos ia16-*-elf*) targ_emul=3Delf_i386 targ_extra_emuls=3Di386msdos ;; -ia64-*-elf*) targ_emul=3Delf64_ia64 - ;; -ia64-*-freebsd* | ia64-*-kfreebsd*-gnu) - targ_emul=3Delf64_ia64_fbsd - targ_extra_emuls=3D"elf64_ia64" - ;; -ia64-*-netbsd*) targ_emul=3Delf64_ia64 - ;; -ia64-*-linux*) targ_emul=3Delf64_ia64 - ;; -ia64-*-*vms*) targ_emul=3Delf64_ia64_vms - targ_extra_ofiles=3Dldelfgen.o - ;; -ia64-*-aix*) targ_emul=3Delf64_aix - ;; ip2k-*-elf) targ_emul=3Delf32ip2k ;; iq2000-*-elf) targ_emul=3Delf32iq2000 @@ -1132,10 +1117,6 @@ i[3-7]86-pc-interix*) NATIVE_LIB_DIRS=3D'/usr/local/lib $$INTERIX_ROOT/usr/lib /lib /usr/lib' ;; =20 -ia64-*-aix*) - NATIVE_LIB_DIRS=3D'/usr/local/lib /usr/lib/ia64l64 /lib /usr/lib' - ;; - sparc*-*-solaris2*) NATIVE_LIB_DIRS=3D'/usr/local/lib /usr/ccs/lib /lib /usr/lib' ;; @@ -1162,7 +1143,7 @@ alpha*-*-*) esac =20 case "${target}" in -frv-*-* | hppa*-*-* | ia64-*-* | mips*-*-*) +frv-*-* | hppa*-*-* | mips*-*-*) # Don't enable -z relro by default since many relro tests fail on these # targets: # FAIL: strip -z relro (relro1) diff --git a/ld/emulparams/elf64_aix.sh b/ld/emulparams/elf64_aix.sh deleted file mode 100644 index 9b05bf9a903..00000000000 --- a/ld/emulparams/elf64_aix.sh +++ /dev/null @@ -1,21 +0,0 @@ -# See genscripts.sh and ../scripttempl/elf.sc for the meaning of these. -SCRIPT_NAME=3Delf -ELFSIZE=3D64 -TEMPLATE_NAME=3Delf -OUTPUT_FORMAT=3D"elf64-ia64-aix-little" -ARCH=3Dia64 -MACHINE=3D -MAXPAGESIZE=3D"CONSTANT (MAXPAGESIZE)" -TEXT_START_ADDR=3D"0x10000000" -DATA_ADDR=3D"ALIGN (0x10000000) + (. & (${MAXPAGESIZE} - 1))" -GENERATE_SHLIB_SCRIPT=3Dyes -NOP=3D0x00300000010070000002000001000400 # a bundle full of nops -OTHER_GOT_SECTIONS=3D" - .IA_64.pltoff ${RELOCATING-0} : { *(.IA_64.pltoff) }" -OTHER_PLT_RELOC_SECTIONS=3D" - .rela.IA_64.pltoff ${RELOCATING-0} : { *(.rela.IA_64.pltoff) }" -OTHER_READONLY_SECTIONS=3D" - .opd ${RELOCATING-0} : { *(.opd) } - .IA_64.unwind_info ${RELOCATING-0} : { *(.IA_64.unwind_info*${RELOCATING= + .gnu.linkonce.ia64unwi.*}) } - .IA_64.unwind ${RELOCATING-0} : { *(.IA_64.unwind*${RELOCATING+ .gnu.lin= konce.ia64unw.*}) }" -LIB_PATH=3D"=3D/usr/lib/ia64l64:=3D/usr/lib:=3D/usr/local/lib" diff --git a/ld/emulparams/elf64_ia64.sh b/ld/emulparams/elf64_ia64.sh deleted file mode 100644 index 5f05ccbbba4..00000000000 --- a/ld/emulparams/elf64_ia64.sh +++ /dev/null @@ -1,39 +0,0 @@ -# See genscripts.sh and ../scripttempl/elf.sc for the meaning of these. -SCRIPT_NAME=3Delf -ELFSIZE=3D64 -TEMPLATE_NAME=3Delf -EXTRA_EM_FILE=3Dia64elf -OUTPUT_FORMAT=3D"elf64-ia64-little" -ARCH=3Dia64 -MACHINE=3D -MAXPAGESIZE=3D"CONSTANT (MAXPAGESIZE)" -# FIXME: It interferes with linker relaxation. Disable it until it is -# fixed. -if test "0" =3D "1" -a -n "$CREATE_SHLIB"; then - # Optimize shared libraries for 16K page size - COMMONPAGESIZE=3D"CONSTANT (COMMONPAGESIZE)" -fi -TEXT_START_ADDR=3D"0x4000000000000000" -DATA_ADDR=3D"0x6000000000000000 + (. & (${MAXPAGESIZE} - 1))" -GENERATE_SHLIB_SCRIPT=3Dyes -GENERATE_PIE_SCRIPT=3Dyes -NOP=3D0x00300000010070000002000001000400 # a bundle full of nops -OTHER_GOT_SECTIONS=3D" - .IA_64.pltoff ${RELOCATING-0} : { *(.IA_64.pltoff) }" -OTHER_PLT_RELOC_SECTIONS=3D" - .rela.IA_64.pltoff ${RELOCATING-0} : { *(.rela.IA_64.pltoff) }" -OTHER_READONLY_SECTIONS=3D -OTHER_READWRITE_SECTIONS=3D -test -z "$CREATE_PIE" && OTHER_READONLY_SECTIONS=3D" - .opd ${RELOCATING-0} : { *(.opd) }" -test -n "$CREATE_PIE" && OTHER_READWRITE_SECTIONS=3D" - .opd ${RELOCATING-0} : { *(.opd) }" -test -n "$CREATE_PIE" && OTHER_GOT_RELOC_SECTIONS=3D" - .rela.opd ${RELOCATING-0} : { *(.rela.opd) }" -OTHER_READONLY_SECTIONS=3D"${OTHER_READONLY_SECTIONS} - .IA_64.unwind_info ${RELOCATING-0} : { KEEP(*(.IA_64.unwind_info${RELOCA= TING+* .gnu.linkonce.ia64unwi.*})) } - .IA_64.unwind ${RELOCATING-0} : { KEEP(*(.IA_64.unwind${RELOCATING+* .gn= u.linkonce.ia64unw.*})) }" -# Intel C++ compiler, prior to 9.0, puts small data in .ctors and -# .dtors. They have to be next to .sbss/.sbss2/.sdata/.sdata2. -SMALL_DATA_CTOR=3D" " -SMALL_DATA_DTOR=3D" " diff --git a/ld/emulparams/elf64_ia64_fbsd.sh b/ld/emulparams/elf64_ia64_fb= sd.sh deleted file mode 100644 index 4a0e0a66827..00000000000 --- a/ld/emulparams/elf64_ia64_fbsd.sh +++ /dev/null @@ -1,6 +0,0 @@ -source_sh ${srcdir}/emulparams/elf64_ia64.sh -TEXT_START_ADDR=3D"0x2000000000000000" -unset DATA_ADDR -unset SMALL_DATA_CTOR -unset SMALL_DATA_DTOR -source_sh ${srcdir}/emulparams/elf_fbsd.sh diff --git a/ld/emulparams/elf64_ia64_vms.sh b/ld/emulparams/elf64_ia64_vms= .sh deleted file mode 100644 index 53a6a14d2d4..00000000000 --- a/ld/emulparams/elf64_ia64_vms.sh +++ /dev/null @@ -1,6 +0,0 @@ -SCRIPT_NAME=3Dia64vms - -OUTPUT_FORMAT=3D"elf64-ia64-vms" -ARCH=3Dia64 - -EXTRA_EM_FILE=3Dvms diff --git a/ld/emultempl/ia64elf.em b/ld/emultempl/ia64elf.em deleted file mode 100644 index a74849d1dbb..00000000000 --- a/ld/emultempl/ia64elf.em +++ /dev/null @@ -1,63 +0,0 @@ -# This shell script emits a C file. -*- C -*- -# Copyright (C) 2003-2024 Free Software Foundation, Inc. -# -# This file is part of the GNU Binutils. -# -# This program is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; either version 3 of the License, or -# (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, -# MA 02110-1301, USA. -# - -# This file is sourced from elf.em, and defines extra ia64-elf -# specific routines. -# -# Define some shell vars to insert bits of code into the standard elf -# parse_args and list_options functions. -# -fragment <. -# -# Copyright (C) 2014-2024 Free Software Foundation, Inc. -# -# Copying and distribution of this file, with or without modification, -# are permitted in any medium without royalty provided the copyright -# notice and this notice are preserved. - -# Using an empty script for ld -r is better than mashing together -# sections. This hack likely leaves ld -Ur broken. -test -n "${RELOCATING}" || exit 0 - -PAGESIZE=3D0x10000 -BLOCKSIZE=3D0x200 - -cat <: -[ ]*[a-f0-9]+: 0b 60 80 02 00 24 \[MMI\] addl r12=3D32,r1;; -[ ]*[a-f0-9]+: c0 c0 04 00 48 00 addl r12=3D24,r1 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; diff --git a/ld/testsuite/ld-ia64/merge1.s b/ld/testsuite/ld-ia64/merge1.s deleted file mode 100644 index 8998db43c7d..00000000000 --- a/ld/testsuite/ld-ia64/merge1.s +++ /dev/null @@ -1,12 +0,0 @@ - .section .rodata.str1.8,"aMS", 1 -.LC1: .string "foo" -.LC2: .string "foo" - .section .data.rel.local,"aw" - .quad .LC2 - .section .rodata,"a" -.LC3: .string "bar" - .balign 8 - .space 0x400000 - .text - addl r12=3D@ltoffx(.LC1),r1 ;; - addl r12=3D@ltoffx(.LC3),r1 ;; diff --git a/ld/testsuite/ld-ia64/merge2.d b/ld/testsuite/ld-ia64/merge2.d deleted file mode 100644 index 639d7bd636e..00000000000 --- a/ld/testsuite/ld-ia64/merge2.d +++ /dev/null @@ -1,10 +0,0 @@ -#source: merge2.s -#as: -x -#ld: -shared --hash-style=3Dsysv -#objdump: -d - -#... -0+160 <.text>: -[ ]*[a-f0-9]+: 0b 60 80 02 00 24 \[MMI\] addl r12=3D32,r1;; -[ ]*[a-f0-9]+: c0 c0 04 00 48 00 addl r12=3D24,r1 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; diff --git a/ld/testsuite/ld-ia64/merge2.s b/ld/testsuite/ld-ia64/merge2.s deleted file mode 100644 index 6c85ac2ee3e..00000000000 --- a/ld/testsuite/ld-ia64/merge2.s +++ /dev/null @@ -1,12 +0,0 @@ - .section .rodata.str1.8,"aMS", 1 -.LC2: .string "foo" -.LC1: .string "foo" - .section .data.rel.local,"aw" - .quad .LC2 - .section .rodata,"a" -.LC3: .string "bar" - .balign 8 - .space 0x400000 - .text - addl r12=3D@ltoffx(.LC1),r1 ;; - addl r12=3D@ltoffx(.LC3),r1 ;; diff --git a/ld/testsuite/ld-ia64/merge3.d b/ld/testsuite/ld-ia64/merge3.d deleted file mode 100644 index 6e4c4f71e17..00000000000 --- a/ld/testsuite/ld-ia64/merge3.d +++ /dev/null @@ -1,13 +0,0 @@ -#source: merge3.s -#as: -x -#ld: -shared --hash-style=3Dsysv -#objdump: -d - -#... -0+190 <.text>: -[ ]*[a-f0-9]+: 0b 60 80 02 00 24 \[MMI\] addl r12=3D32,r1;; -[ ]*[a-f0-9]+: c0 40 05 00 48 00 addl r12=3D40,r1 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 60 60 02 00 24 \[MII\] addl r12=3D24,r1 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; diff --git a/ld/testsuite/ld-ia64/merge3.s b/ld/testsuite/ld-ia64/merge3.s deleted file mode 100644 index 2442701fc8b..00000000000 --- a/ld/testsuite/ld-ia64/merge3.s +++ /dev/null @@ -1,16 +0,0 @@ - .section .rodata.str1.8,"aMS", 1 -.LC1: .string "foo" -.LC2: .string "foo" -.LC3: .string "bar" -.LC4: .string "bar" - .section .data.rel.local,"aw" - .quad .LC2 - .quad .LC3 - .section .rodata,"a" -.LC5: .string "mumble" - .balign 8 - .space 0x400000 - .text - addl r12=3D@ltoffx(.LC1),r1 ;; - addl r12=3D@ltoffx(.LC4),r1 ;; - addl r12=3D@ltoffx(.LC5),r1 ;; diff --git a/ld/testsuite/ld-ia64/merge4.d b/ld/testsuite/ld-ia64/merge4.d deleted file mode 100644 index 608c123d2ad..00000000000 --- a/ld/testsuite/ld-ia64/merge4.d +++ /dev/null @@ -1,13 +0,0 @@ -#source: merge4.s -#as: -x -#ld: -shared --hash-style=3Dsysv -#objdump: -d - -#... -0+1c0 <.text>: -[ ]*[a-f0-9]+: 0b 60 80 02 00 24 \[MMI\] addl r12=3D32,r1;; -[ ]*[a-f0-9]+: c0 40 05 00 48 00 addl r12=3D40,r1 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 0b 60 c0 02 00 24 \[MMI\] addl r12=3D48,r1;; -[ ]*[a-f0-9]+: c0 c0 04 00 48 00 addl r12=3D24,r1 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; diff --git a/ld/testsuite/ld-ia64/merge4.s b/ld/testsuite/ld-ia64/merge4.s deleted file mode 100644 index c23b4d0ea16..00000000000 --- a/ld/testsuite/ld-ia64/merge4.s +++ /dev/null @@ -1,21 +0,0 @@ - .section .rodata.str1.8,"aMS", 1 -.LC1: .string "foo" -.LC2: .string "foo" -.LC3: .string "bar" -.LC4: .string "bar" -.LC5: .string "baz" -.LC6: .string "baz" - .section .data.rel.local,"aw" - .quad .LC2 - .quad .LC4 - .quad .LC5 - .section .rodata,"a" -.LC7: .string "mumble" - .balign 8 - .space 0x400000 - .text - addl r12=3D@ltoffx(.LC1),r1 ;; - addl r12=3D@ltoffx(.LC3),r1 ;; - addl r12=3D@ltoffx(.LC6),r1 ;; - addl r12=3D@ltoffx(.LC7),r1 ;; - diff --git a/ld/testsuite/ld-ia64/merge5.d b/ld/testsuite/ld-ia64/merge5.d deleted file mode 100644 index 594b188b929..00000000000 --- a/ld/testsuite/ld-ia64/merge5.d +++ /dev/null @@ -1,16 +0,0 @@ -#source: merge5.s -#as: -x -#ld: -shared --hash-style=3Dsysv -#objdump: -d - -#... -0+1f0 <.text>: -[ ]*[a-f0-9]+: 0b 60 80 02 00 24 \[MMI\] addl r12=3D32,r1;; -[ ]*[a-f0-9]+: c0 40 05 00 48 00 addl r12=3D40,r1 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 0b 60 a0 02 00 24 \[MMI\] addl r12=3D40,r1;; -[ ]*[a-f0-9]+: c0 c0 05 00 48 00 addl r12=3D56,r1 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; -[ ]*[a-f0-9]+: 01 60 60 02 00 24 \[MII\] addl r12=3D24,r1 -[ ]*[a-f0-9]+: 00 00 00 02 00 00 nop.i 0x0 -[ ]*[a-f0-9]+: 00 00 04 00 nop.i 0x0;; diff --git a/ld/testsuite/ld-ia64/merge5.s b/ld/testsuite/ld-ia64/merge5.s deleted file mode 100644 index 81428c41cc5..00000000000 --- a/ld/testsuite/ld-ia64/merge5.s +++ /dev/null @@ -1,24 +0,0 @@ - .section .rodata.str1.8,"aMS", 1 -.LC1: .string "foo" -.LC2: .string "foo" -.LC3: .string "bar" -.LC4: .string "bar" -.LC5: .string "bar" -.LC6: .string "bar" -.LC7: .string "baz" -.LC8: .string "baz" - .section .data.rel.local,"aw" - .quad .LC2 - .quad .LC4 - .quad .LC6 - .quad .LC7 - .section .rodata,"a" -.LC9: .string "mumble" - .balign 8 - .space 0x400000 - .text - addl r12=3D@ltoffx(.LC1),r1 ;; - addl r12=3D@ltoffx(.LC3),r1 ;; - addl r12=3D@ltoffx(.LC5),r1 ;; - addl r12=3D@ltoffx(.LC8),r1 ;; - addl r12=3D@ltoffx(.LC9),r1 ;; diff --git a/ld/testsuite/ld-ia64/tlsbin.dd b/ld/testsuite/ld-ia64/tlsbin.dd deleted file mode 100644 index 1c5bc2fe33f..00000000000 --- a/ld/testsuite/ld-ia64/tlsbin.dd +++ /dev/null @@ -1,74 +0,0 @@ -#source: tlsbinpic.s -#source: tlsbin.s -#as: -#ld: -shared -#objdump: -drj.text -#target: ia64-*-* - -.*: +file format elf..-ia64-.* - -Disassembly of section .text: - -40+1000 : -40+1000: 10 10 15 06 80 05[ ]+\[MIB\][ ]+alloc r34=3Dar.pfs,5,3,0 -40+1006: 10 02 00 62 00 00[ ]+mov r33=3Db0 -40+100c: 00 00 00 20[ ]+nop.b 0x0 -40+1010: 0d 70 .0 0. 00 24[ ]+\[MFI\][ ]+addl r14=3D(24|32|40|48|56|64),= r1 -40+1016: 00 00 00 02 00 e0[ ]+nop.f 0x0 -40+101c: .1 0. 00 90[ ]+addl r15=3D(24|32|40|48|56|64),r1;; -40+1020: 19 18 01 1c 18 10[ ]+\[MMB\][ ]+ld8 r35=3D\[r14\] -40+1026: 40 02 3c 30 20 00[ ]+ld8 r36=3D\[r15\] -40+102c: [0-9a-f ]+br.call.sptk.many b0=3D[0-9a-f]+ <.*>;; -40+1030: 0d 70 .0 0. 00 24[ ]+\[MFI\][ ]+addl r14=3D(24|32|40|48|56|64),= r1 -40+1036: 00 00 00 02 00 e0[ ]+nop.f 0x0 -40+103c: .1 0. 00 90[ ]+addl r15=3D(24|32|40|48|56|64),r1;; -40+1040: 19 18 01 1c 18 10[ ]+\[MMB\][ ]+ld8 r35=3D\[r14\] -40+1046: 40 02 3c 30 20 00[ ]+ld8 r36=3D\[r15\] -40+104c: [0-9a-f ]+br.call.sptk.many b0=3D[0-9a-f]+ <.*>;; -40+1050: 0d 70 .0 0. 00 24[ ]+\[MFI\][ ]+addl r14=3D(24|32|40|48|56|64),= r1 -40+1056: 00 00 00 02 00 80[ ]+nop.f 0x0 -40+105c: 14 02 00 90[ ]+mov r36=3D33;; -40+1060: 1d 18 01 1c 18 10[ ]+\[MFB\][ ]+ld8 r35=3D\[r14\] -40+1066: 00 00 00 02 00 00[ ]+nop.f 0x0 -40+106c: [0-9a-f ]+br.call.sptk.many b0=3D[0-9a-f]+ <.*>;; -40+1070: 0d 70 .0 0. 00 24[ ]+\[MFI\][ ]+addl r14=3D(24|32|40|48|56|64),= r1 -40+1076: 00 00 00 02 00 80[ ]+nop.f 0x0 -40+107c: 04 00 00 84[ ]+mov r36=3Dr0;; -40+1080: 1d 18 01 1c 18 10[ ]+\[MFB\][ ]+ld8 r35=3D\[r14\] -40+1086: 00 00 00 02 00 00[ ]+nop.f 0x0 -40+108c: [0-9a-f ]+br.call.sptk.many b0=3D[0-9a-f]+ <.*>;; -40+1090: 0b 10 00 10 00 21[ ]+\[MMI\][ ]+mov r2=3Dr8;; -40+1096: e0 00 0a 00 48 e0[ ]+addl r14=3D64,r2 -40+109c: 61 14 00 90[ ]+addl r15=3D70,r2;; -40+10a0: 05 70 2c 11 00 21[ ]+\[MLX\][ ]+adds r14=3D75,r8 -40+10a6: 00 00 00 00 00 e0[ ]+movl r15=3D0x4d;; -40+10ac: d1 04 00 60=20 -40+10b0: 0a 78 3c 10 00 20[ ]+\[MMI\][ ]+add r15=3Dr15,r8;; -40+10b6: 00 00 00 02 00 00[ ]+nop.m 0x0 -40+10bc: 20 02 aa 00[ ]+mov.i ar.pfs=3Dr34 -40+10c0: 11 00 00 00 01 00[ ]+\[MIB\][ ]+nop.m 0x0 -40+10c6: 00 08 05 80 03 80[ ]+mov b0=3Dr33 -40+10cc: 08 00 84 00[ ]+br.ret.sptk.many b0;; - -40+10d0 <_start>: -40+10d0: 0b 70 .0 0. 00 24[ ]+\[MMI\][ ]+addl r14=3D(24|32|40|48|56|64),= r1;; -40+10d6: e0 00 38 30 20 00[ ]+ld8 r14=3D\[r14\] -40+10dc: 00 00 04 00[ ]+nop.i 0x0;; -40+10e0: 0b 70 38 1a 00 20[ ]+\[MMI\][ ]+add r14=3Dr14,r13;; -40+10e6: e0 .0 0. 00 48 00[ ]+addl r14=3D(24|32|40|48|56|64),r1 -40+10ec: 00 00 04 00[ ]+nop.i 0x0;; -40+10f0: 0b 70 00 1c 18 10[ ]+\[MMI\][ ]+ld8 r14=3D\[r14\];; -40+10f6: e0 70 34 00 40 00[ ]+add r14=3Dr14,r13 -40+10fc: 00 00 04 00[ ]+nop.i 0x0;; -40+1100: 0b 10 00 1a 00 21[ ]+\[MMI\][ ]+mov r2=3Dr13;; -40+1106: e0 80 08 00 48 e0[ ]+addl r14=3D16,r2 -40+110c: 61 11 04 90[ ]+addl r15=3D150,r2;; -40+1110: 05 70 5c 1b 00 21[ ]+\[MLX\][ ]+adds r14=3D87,r13 -40+1116: 00 00 00 00 00 e0[ ]+movl r15=3D0x95;; -40+111c: 51 01 04 60=20 -40+1120: 0a 78 3c 1a 00 20[ ]+\[MMI\][ ]+add r15=3Dr15,r13;; -40+1126: 00 00 00 02 00 00[ ]+nop.m 0x0 -40+112c: 00 00 04 00[ ]+nop.i 0x0 -40+1130: 1d 00 00 00 01 00[ ]+\[MFB\][ ]+nop.m 0x0 -40+1136: 00 00 00 02 00 80[ ]+nop.f 0x0 -40+113c: 08 00 84 00[ ]+br.ret.sptk.many b0;; diff --git a/ld/testsuite/ld-ia64/tlsbin.rd b/ld/testsuite/ld-ia64/tlsbin.rd deleted file mode 100644 index ccbdbdbc523..00000000000 --- a/ld/testsuite/ld-ia64/tlsbin.rd +++ /dev/null @@ -1,136 +0,0 @@ -#source: tlsbinpic.s -#source: tlsbin.s -#as: -#ld: -shared -#readelf: -WSsrl -#target: ia64-*-* - -There are [0-9]+ section headers, starting at offset 0x[0-9a-f]+: - -Section Headers: - +\[Nr\] Name +Type +Address +Off +Size +ES Flg Lk Inf Al - +\[[ 0-9]+\] +NULL +0+ 0+ 0+ 00 +0 +0 +0 - +\[[ 0-9]+\] .interp +.* - +\[[ 0-9]+\] .hash +.* - +\[[ 0-9]+\] .dynsym +.* - +\[[ 0-9]+\] .dynstr +.* - +\[[ 0-9]+\] .rela.dyn +.* - +\[[ 0-9]+\] .rela.IA_64.pltoff +.* - +\[[ 0-9]+\] .plt +.* - +\[[ 0-9]+\] .text +PROGBITS +40+1000 0+1000 0+140 00 +AX +0 +0 4096 - +\[[ 0-9]+\] .IA_64.unwind_info +.* - +\[[ 0-9]+\] .IA_64.unwind +.* - +\[[ 0-9]+\] .tdata +PROGBITS +60+1[0-9a-f]+ 0+1[0-9a-f]+ 0+60 00 WAT +0 = +0 +4 - +\[[ 0-9]+\] .tbss +NOBITS +60+1[0-9a-f]+ 0+1[0-9a-f]+ 0+40 00 WAT +0 +0 = +1 - +\[[ 0-9]+\] .dynamic +DYNAMIC +60+1[0-9a-f]+ 0+1[0-9a-f]+ 0+150 10 +WA += 4 +0 +8 - +\[[ 0-9]+\] .got +PROGBITS +60+1318 0+1318 0+48 00 WAp +0 +0 +8 - +\[[ 0-9]+\] .IA_64.pltoff +.* - +\[[ 0-9]+\] .symtab +.* - +\[[ 0-9]+\] .strtab +.* - +\[[ 0-9]+\] .shstrtab +.* -#... - -Elf file type is EXEC \(Executable file\) -Entry point 0x40+10d0 -There are [0-9]+ program headers, starting at offset [0-9]+ - -Program Headers: - +Type +Offset +VirtAddr +PhysAddr +FileSiz +MemSiz +Flg Align - +PHDR +0x0+40 0x40+40 0x40+40 0x0+188 0x0+188 R +0x8 - +INTERP +0x0+1c8 0x40+1c8 0x40+1c8 0x[0-9a-f]+ 0x[0-9a-f]+ R +0x1 -.*Requesting program interpreter.* - +LOAD +0x0+ 0x40+ 0x40+ 0x0+1[0-9a-f]+ 0x0+1[0-9a-f]+ R E 0x10000 - +LOAD +0x0+1[0-9a-f]+ 0x60+1[0-9a-f]+ 0x60+1[0-9a-f]+ 0x0+0[0-9a-f]+ 0x0+= 0[0-9a-f]+ RW +0x10000 - +DYNAMIC +0x0+1[0-9a-f]+ 0x60+1[0-9a-f]+ 0x60+1[0-9a-f]+ 0x0+150 0x0+150 = RW +0x8 - +TLS +0x0+1[0-9a-f]+ 0x60+1[0-9a-f]+ 0x60+1[0-9a-f]+ 0x0+60 0x0+a0 R +0x4 - +IA_64_UNWIND .* R +0x8 -#... - -Relocation section '.rela.dyn' at offset 0x[0-9a-f]+ contains 3 entries: - +Offset +Info +Type +Symbol's Value +Symbol's Name \+ Addend -[0-9a-f ]+R_IA64_TPREL64LSB +0+ sG2 \+ 0 -[0-9a-f ]+R_IA64_DTPMOD64LSB +0+ sG1 \+ 0 -[0-9a-f ]+R_IA64_DTPREL64LSB +0+ sG1 \+ 0 - -Relocation section '.rela.IA_64.pltoff' at offset 0x[0-9a-f]+ contains 1 e= ntry: - +Offset +Info +Type +Symbol's Value +Symbol's Name \+ Addend -[0-9a-f ]+R_IA64_IPLTLSB +0+ __tls_get_addr \+ 0 - -Symbol table '\.dynsym' contains [0-9]+ entries: - +Num: +Value +Size +Type +Bind +Vis +Ndx +Name -.* NOTYPE +LOCAL +DEFAULT +UND * -.* TLS +GLOBAL +DEFAULT +UND sG2 -.* FUNC +GLOBAL +DEFAULT +UND __tls_get_addr -.* TLS +GLOBAL +DEFAULT +UND sG1 - -Symbol table '\.symtab' contains [0-9]+ entries: - +Num: +Value +Size +Type +Bind +Vis +Ndx +Name -.* NOTYPE +LOCAL +DEFAULT +UND * -.* SECTION +LOCAL +DEFAULT +1.* -.* SECTION +LOCAL +DEFAULT +2.* -.* SECTION +LOCAL +DEFAULT +3.* -.* SECTION +LOCAL +DEFAULT +4.* -.* SECTION +LOCAL +DEFAULT +5.* -.* SECTION +LOCAL +DEFAULT +6.* -.* SECTION +LOCAL +DEFAULT +7.* -.* SECTION +LOCAL +DEFAULT +8.* -.* SECTION +LOCAL +DEFAULT +9.* -.* SECTION +LOCAL +DEFAULT +10.* -.* SECTION +LOCAL +DEFAULT +11.* -.* SECTION +LOCAL +DEFAULT +12.* -.* SECTION +LOCAL +DEFAULT +13.* -.* SECTION +LOCAL +DEFAULT +14.* -.* SECTION +LOCAL +DEFAULT +15.* -.* FILE +LOCAL +DEFAULT +ABS .* -.* TLS +LOCAL +DEFAULT +11 sl1 -.* TLS +LOCAL +DEFAULT +11 sl2 -.* TLS +LOCAL +DEFAULT +11 sl3 -.* TLS +LOCAL +DEFAULT +11 sl4 -.* TLS +LOCAL +DEFAULT +11 sl5 -.* TLS +LOCAL +DEFAULT +11 sl6 -.* TLS +LOCAL +DEFAULT +11 sl7 -.* TLS +LOCAL +DEFAULT +11 sl8 -.* FILE +LOCAL +DEFAULT +ABS .* -.* TLS +LOCAL +DEFAULT +12 bl1 -.* TLS +LOCAL +DEFAULT +12 bl2 -.* TLS +LOCAL +DEFAULT +12 bl3 -.* TLS +LOCAL +DEFAULT +12 bl4 -.* TLS +LOCAL +DEFAULT +12 bl5 -.* TLS +LOCAL +DEFAULT +12 bl6 -.* TLS +LOCAL +DEFAULT +12 bl7 -.* TLS +LOCAL +DEFAULT +12 bl8 -.* FILE +LOCAL +DEFAULT +ABS .* -.* OBJECT +LOCAL +DEFAULT +13 _DYNAMIC -.* OBJECT +LOCAL +DEFAULT +14 _GLOBAL_OFFSET_TABLE_ -.* TLS +GLOBAL +DEFAULT +11 sg8 -.* TLS +GLOBAL +DEFAULT +12 bg8 -.* TLS +GLOBAL +DEFAULT +12 bg6 -.* TLS +GLOBAL +DEFAULT +12 bg3 -.* TLS +GLOBAL +DEFAULT +11 sg3 -.* TLS +GLOBAL +HIDDEN +11 sh3 -.* TLS +GLOBAL +DEFAULT +UND sG2 -.* TLS +GLOBAL +DEFAULT +11 sg4 -.* TLS +GLOBAL +DEFAULT +11 sg5 -.* TLS +GLOBAL +DEFAULT +12 bg5 -.* FUNC +GLOBAL +DEFAULT +UND __tls_get_addr -.* TLS +GLOBAL +HIDDEN +11 sh7 -.* TLS +GLOBAL +HIDDEN +11 sh8 -.* TLS +GLOBAL +DEFAULT +11 sg1 -.* FUNC +GLOBAL +DEFAULT +8 _start -.* TLS +GLOBAL +HIDDEN +11 sh4 -.* TLS +GLOBAL +DEFAULT +12 bg7 -.* TLS +GLOBAL +HIDDEN +11 sh5 -.* NOTYPE +GLOBAL +DEFAULT +15 __bss_start -.* FUNC +GLOBAL +DEFAULT +8 fn2 -.* TLS +GLOBAL +DEFAULT +11 sg2 -.* TLS +GLOBAL +DEFAULT +UND sG1 -.* TLS +GLOBAL +HIDDEN +11 sh1 -.* TLS +GLOBAL +DEFAULT +11 sg6 -.* TLS +GLOBAL +DEFAULT +11 sg7 -.* NOTYPE +GLOBAL +DEFAULT +15 _edata -.* NOTYPE +GLOBAL +DEFAULT +15 _end -.* TLS +GLOBAL +HIDDEN +11 sh2 -.* TLS +GLOBAL +HIDDEN +11 sh6 -.* TLS +GLOBAL +DEFAULT +12 bg2 -.* TLS +GLOBAL +DEFAULT +12 bg1 -.* TLS +GLOBAL +DEFAULT +12 bg4 diff --git a/ld/testsuite/ld-ia64/tlsbin.s b/ld/testsuite/ld-ia64/tlsbin.s deleted file mode 100644 index 7b5f34aca27..00000000000 --- a/ld/testsuite/ld-ia64/tlsbin.s +++ /dev/null @@ -1,54 +0,0 @@ - .section ".tbss", "awT", @nobits - .globl bg1, bg2, bg3, bg4, bg5, bg6, bg7, bg8 -bg1: .space 4 -bg2: .space 4 -bg3: .space 4 -bg4: .space 4 -bg5: .space 4 -bg6: .space 4 -bg7: .space 4 -bg8: .space 4 -bl1: .space 4 -bl2: .space 4 -bl3: .space 4 -bl4: .space 4 -bl5: .space 4 -bl6: .space 4 -bl7: .space 4 -bl8: .space 4 - .explicit - .pred.safe_across_calls p1-p5,p16-p63 - .text - .globl _start# - .proc _start# -_start: - /* IE */ - addl r14 =3D @ltoff(@tprel(sG2#)), gp - ;; - ld8 r14 =3D [r14] - ;; - add r14 =3D r14, r13 - ;; - - /* IE against global symbol in exec */ - addl r14 =3D @ltoff(@tprel(bl1#)), gp - ;; - ld8 r14 =3D [r14] - ;; - add r14 =3D r14, r13 - ;; - - /* LE */ - mov r2 =3D r13 - ;; - addl r14 =3D @tprel(sg1#), r2 - addl r15 =3D @tprel(bl2#) + 2, r2 - ;; - adds r14 =3D @tprel(sh2#) + 3, r13 - movl r15 =3D @tprel(bl2#) + 1 - ;; - add r15 =3D r15, r13 - ;; - - br.ret.sptk.many b0 - .endp _start# diff --git a/ld/testsuite/ld-ia64/tlsbin.sd b/ld/testsuite/ld-ia64/tlsbin.sd deleted file mode 100644 index 411eedb6a37..00000000000 --- a/ld/testsuite/ld-ia64/tlsbin.sd +++ /dev/null @@ -1,15 +0,0 @@ -#source: tlsbinpic.s -#source: tlsbin.s -#as: -#ld: -shared -#objdump: -sj.got -#target: ia64-*-* - -.*: +file format elf..-ia64-.* - -Contents of section .got: - (60+)?1318 0+ 0+ 0+ 0+ .* - (60+)?1328 0+ 0+ 0+ 0+ .* - (60+)?1338 0+ 0+ 0+ 0+ .* - (60+)?1348 (00|01|24|90)000000 0+ (00|01|24|90)000000 0+ .* - (60+)?1358 (00|01|24|90)000000 0+ .* diff --git a/ld/testsuite/ld-ia64/tlsbin.td b/ld/testsuite/ld-ia64/tlsbin.td deleted file mode 100644 index 1e724e7c7f8..00000000000 --- a/ld/testsuite/ld-ia64/tlsbin.td +++ /dev/null @@ -1,16 +0,0 @@ -#source: tlsbinpic.s -#source: tlsbin.s -#as: -#ld: -shared -#objdump: -sj.tdata -#target: ia64-*-* - -.*: +file format elf..-ia64-.* - -Contents of section .tdata: - (60+)?1[0-9a-f]+ 11000000 12000000 13000000 14000000 .* - (60+)?1[0-9a-f]+ 15000000 16000000 17000000 18000000 .* - (60+)?1[0-9a-f]+ 41000000 42000000 43000000 44000000 .* - (60+)?1[0-9a-f]+ 45000000 46000000 47000000 48000000 .* - (60+)?1[0-9a-f]+ 01010000 02010000 03010000 04010000 .* - (60+)?1[0-9a-f]+ 05010000 06010000 07010000 08010000 .* diff --git a/ld/testsuite/ld-ia64/tlsbinpic.s b/ld/testsuite/ld-ia64/tlsbin= pic.s deleted file mode 100644 index f0613434cb2..00000000000 --- a/ld/testsuite/ld-ia64/tlsbinpic.s +++ /dev/null @@ -1,97 +0,0 @@ - /* Force .data aligned to 4K, so that .got very likely gets at - 0x60000000000031b0 (0x60 bytes .tdata and 0x150 bytes - .dynamic). */ - .data - .balign 4096 - .section ".tdata", "awT", @progbits - .globl sg1, sg2, sg3, sg4, sg5, sg6, sg7, sg8 - .globl sh1, sh2, sh3, sh4, sh5, sh6, sh7, sh8 - .hidden sh1, sh2, sh3, sh4, sh5, sh6, sh7, sh8 -sg1: .long 17 -sg2: .long 18 -sg3: .long 19 -sg4: .long 20 -sg5: .long 21 -sg6: .long 22 -sg7: .long 23 -sg8: .long 24 -sl1: .long 65 -sl2: .long 66 -sl3: .long 67 -sl4: .long 68 -sl5: .long 69 -sl6: .long 70 -sl7: .long 71 -sl8: .long 72 -sh1: .long 257 -sh2: .long 258 -sh3: .long 259 -sh4: .long 260 -sh5: .long 261 -sh6: .long 262 -sh7: .long 263 -sh8: .long 264 - .explicit - .pred.safe_across_calls p1-p5,p16-p63 - /* Force .text aligned to 4K, so it very likely gets at - 0x4000000000001000. */ - .text - .balign 4096 - .globl fn2# - .proc fn2# -fn2: - .prologue 12, 33 - .mib - .save ar.pfs, r34 - alloc r34 =3D ar.pfs, 0, 3, 2, 0 - .save rp, r33 - mov r33 =3D b0 - - /* GD */ - addl r14 =3D @ltoff(@dtpmod(sG1#)), gp - addl r15 =3D @ltoff(@dtprel(sG1#)), gp - ;; - ld8 out0 =3D [r14] - ld8 out1 =3D [r15] - br.call.sptk.many b0 =3D __tls_get_addr# - ;; - - /* GD against local symbol */ - addl r14 =3D @ltoff(@dtpmod(sl2#)), gp - addl r15 =3D @ltoff(@dtprel(sl2#)), gp - ;; - ld8 out0 =3D [r14] - ld8 out1 =3D [r15] - br.call.sptk.many b0 =3D __tls_get_addr# - ;; - - /* LD */ - addl r14 =3D @ltoff(@dtpmod(sl1#)), gp - addl out1 =3D @dtprel(sl1#) + 1, r0 - ;; - ld8 out0 =3D [r14] - br.call.sptk.many b0 =3D __tls_get_addr# - ;; - - /* LD with 4 variables variables */ - addl r14 =3D @ltoff(@dtpmod(sh1#)), gp - mov out1 =3D r0 - ;; - ld8 out0 =3D [r14] - br.call.sptk.many b0 =3D __tls_get_addr# - ;; - mov r2 =3D r8 - ;; - addl r14 =3D @dtprel(sh1#), r2 - addl r15 =3D @dtprel(sh2#) + 2, r2 - ;; - adds r14 =3D @dtprel(sh3#) + 3, r8 - movl r15 =3D @dtprel(sh4#) + 1 - ;; - add r15 =3D r15, r8 - ;; - - mov ar.pfs =3D r34 - mov b0 =3D r33 - br.ret.sptk.many b0 - .endp fn2# diff --git a/ld/testsuite/ld-ia64/tlsg.s b/ld/testsuite/ld-ia64/tlsg.s deleted file mode 100644 index fa3fce0c649..00000000000 --- a/ld/testsuite/ld-ia64/tlsg.s +++ /dev/null @@ -1,14 +0,0 @@ - .section .tbss,"awT",@nobits - .align 4 - .skip 24 - .type a#,@object - .size a#,4 -a: - data4 0 - .text - .globl _start# - .proc _start# -_start: - .endp _start# - .section .debug_foobar - data8 @dtprel(a#) diff --git a/ld/testsuite/ld-ia64/tlsg.sd b/ld/testsuite/ld-ia64/tlsg.sd deleted file mode 100644 index 67bc9cdd4ed..00000000000 --- a/ld/testsuite/ld-ia64/tlsg.sd +++ /dev/null @@ -1,10 +0,0 @@ -#source: tlsg.s -#as: -#ld: -#objdump: -sj.debug_foobar -#target: ia64-*-* - -.*: +file format elf..-ia64-.* - -Contents of section .debug_foobar: - 0+ 18000000 0+ +.* diff --git a/ld/testsuite/ld-ia64/tlslib.s b/ld/testsuite/ld-ia64/tlslib.s deleted file mode 100644 index d0e63feb51a..00000000000 --- a/ld/testsuite/ld-ia64/tlslib.s +++ /dev/null @@ -1,18 +0,0 @@ - .section ".tdata", "awT", @progbits - .globl sG1, sG2, sG3, sG4, sG5, sG6, sG7, sG8 -sG1: .long 513 -sG2: .long 514 -sG3: .long 515 -sG4: .long 516 -sG5: .long 517 -sG6: .long 518 -sG7: .long 519 -sG8: .long 520 - - .text - /* Dummy. */ - .globl __tls_get_addr# - .proc __tls_get_addr# -__tls_get_addr: - br.ret.sptk.many b0 - .endp __tls_get_addr# diff --git a/ld/testsuite/ld-ia64/tlspic.dd b/ld/testsuite/ld-ia64/tlspic.dd deleted file mode 100644 index 32850f0df47..00000000000 --- a/ld/testsuite/ld-ia64/tlspic.dd +++ /dev/null @@ -1,64 +0,0 @@ -#source: tlspic1.s -#source: tlspic2.s -#as: -#ld: -#objdump: -drj.text -#target: ia64-*-* - -.*: +file format elf..-ia64-.* - -Disassembly of section .text: - -0+1000 : - +1000: 10 10 15 06 80 05[ ]+\[MIB\] +alloc r34=3Dar.pfs,5,3,0 - +1006: 10 02 00 62 00 00[ ]+mov r33=3Db0 - +100c: 00 00 00 20[ ]+nop.b 0x0 - +1010: 0d 70 60 02 00 24[ ]+\[MFI\] +addl r14=3D24,r1 - +1016: 00 00 00 02 00 e0[ ]+nop.f 0x0 - +101c: 01 0a 00 90[ ]+addl r15=3D32,r1;; - +1020: 19 18 01 1c 18 10[ ]+\[MMB\] +ld8 r35=3D\[r14\] - +1026: 40 02 3c 30 20 00[ ]+ld8 r36=3D\[r15\] - +102c: [0-9a-f ]+br.call.sptk.many b0=3D[0-9a-f]+ <.*>;; - +1030: 0d 70 c0 02 00 24[ ]+\[MFI\] +addl r14=3D48,r1 - +1036: 00 00 00 02 00 e0[ ]+nop.f 0x0 - +103c: 01 0c 00 90[ ]+addl r15=3D64,r1;; - +1040: 19 18 01 1c 18 10[ ]+\[MMB\] +ld8 r35=3D\[r14\] - +1046: 40 02 3c 30 20 00[ ]+ld8 r36=3D\[r15\] - +104c: [0-9a-f ]+br.call.sptk.many b0=3D[0-9a-f]+ <.*>;; - +1050: 0d 70 c0 02 00 24[ ]+\[MFI\] +addl r14=3D48,r1 - +1056: 00 00 00 02 00 80[ ]+nop.f 0x0 - +105c: 14 02 00 90[ ]+mov r36=3D33;; - +1060: 1d 18 01 1c 18 10[ ]+\[MFB\] +ld8 r35=3D\[r14\] - +1066: 00 00 00 02 00 00[ ]+nop.f 0x0 - +106c: [0-9a-f ]+br.call.sptk.many b0=3D[0-9a-f]+ <.*>;; - +1070: 0d 70 c0 02 00 24[ ]+\[MFI\] +addl r14=3D48,r1 - +1076: 00 00 00 02 00 80[ ]+nop.f 0x0 - +107c: 04 00 00 84[ ]+mov r36=3Dr0;; - +1080: 1d 18 01 1c 18 10[ ]+\[MFB\] +ld8 r35=3D\[r14\] - +1086: 00 00 00 02 00 00[ ]+nop.f 0x0 - +108c: [0-9a-f ]+br.call.sptk.many b0=3D[0-9a-f]+ <.*>;; - +1090: 0b 10 00 10 00 21[ ]+\[MMI\] +mov r2=3Dr8;; - +1096: e0 00 0a 00 48 e0[ ]+addl r14=3D64,r2 - +109c: 21 16 00 90[ ]+addl r15=3D98,r2;; - +10a0: 05 70 4c 11 00 21[ ]+\[MLX\] +adds r14=3D83,r8 - +10a6: 00 00 00 00 00 e0[ ]+movl r15=3D0x71;; - +10ac: 11 07 00 60=20 - +10b0: 0b 78 3c 10 00 20[ ]+\[MMI\] +add r15=3Dr15,r8;; - +10b6: e0 40 05 00 48 00[ ]+addl r14=3D40,r1 - +10bc: 00 00 04 00[ ]+nop.i 0x0;; - +10c0: 0b 78 00 1c 18 10[ ]+\[MMI\] +ld8 r15=3D\[r14\];; - +10c6: e0 78 34 00 40 00[ ]+add r14=3Dr15,r13 - +10cc: 00 00 04 00[ ]+nop.i 0x0;; - +10d0: 0d 70 20 03 00 24[ ]+\[MFI\] +addl r14=3D72,r1 - +10d6: 00 00 00 02 00 e0[ ]+nop.f 0x0 - +10dc: 81 0b 00 90[ ]+addl r15=3D56,r1;; - +10e0: 09 70 00 1c 18 10[ ]+\[MMI\] +ld8 r14=3D\[r14\] - +10e6: f0 00 3c 30 20 00[ ]+ld8 r15=3D\[r15\] - +10ec: 00 00 04 00[ ]+nop.i 0x0;; - +10f0: 02 70 38 1a 00 20[ ]+\[MII\] +add r14=3Dr14,r13 - +10f6: f0 78 34 00 40 00[ ]+add r15=3Dr15,r13;; - +10fc: 20 02 aa 00[ ]+mov.i ar.pfs=3Dr34 - +1100: 11 00 00 00 01 00[ ]+\[MIB\] +nop.m 0x0 - +1106: 00 08 05 80 03 80[ ]+mov b0=3Dr33 - +110c: 08 00 84 00[ ]+br.ret.sptk.many b0;; -#pass diff --git a/ld/testsuite/ld-ia64/tlspic.rd b/ld/testsuite/ld-ia64/tlspic.rd deleted file mode 100644 index 4b6e76e5943..00000000000 --- a/ld/testsuite/ld-ia64/tlspic.rd +++ /dev/null @@ -1,127 +0,0 @@ -#source: tlspic1.s -#source: tlspic2.s -#as: -#ld: -shared -#readelf: -WSsrl -#target: ia64-*-* - -There are [0-9]+ section headers, starting at offset 0x[0-9a-f]+: - -Section Headers: - +\[Nr\] Name +Type +Address +Off +Size +ES Flg Lk Inf Al - +\[[ 0-9]+\] +NULL +0+ 0+ 0+ 00 +0 +0 +0 - +\[[ 0-9]+\] .hash +.* - +\[[ 0-9]+\] .dynsym +.* - +\[[ 0-9]+\] .dynstr +.* - +\[[ 0-9]+\] .rela.dyn +.* - +\[[ 0-9]+\] .rela.IA_64.pltoff +.* - +\[[ 0-9]+\] .plt +.* - +\[[ 0-9]+\] .text +PROGBITS +0+1000 0+1000 0+110 00 +AX +0 +0 4096 - +\[[ 0-9]+\] .IA_64.unwind_info +.* - +\[[ 0-9]+\] .IA_64.unwind +.* - +\[[ 0-9]+\] .tdata +PROGBITS +0+11[0-9a-f]+ 0+1[0-9a-f]+ 0+60 00 WAT +0 = +0 +4 - +\[[ 0-9]+\] .tbss +NOBITS +0+11[0-9a-f]+ 0+1[0-9a-f]+ 0+20 00 WAT +0 +0 = +1 - +\[[ 0-9]+\] .dynamic +DYNAMIC +0+11[0-9a-f]+ 0+1[0-9a-f]+ 0+140 10 +WA += 3 +0 +8 - +\[[ 0-9]+\] .got +PROGBITS +0+112d8 0+12d8 0+50 00 WAp +0 +0 +8 - +\[[ 0-9]+\] .IA_64.pltoff +.* - +\[[ 0-9]+\] .symtab +.* - +\[[ 0-9]+\] .strtab +.* - +\[[ 0-9]+\] .shstrtab +.* -Key to Flags: -#... - -Elf file type is DYN \(Shared object file\) -Entry point 0x[0-9a-f]+ -There are [0-9]+ program headers, starting at offset [0-9]+ - -Program Headers: - +Type +Offset +VirtAddr +PhysAddr +FileSiz +MemSiz +Flg Align - +LOAD +0x0+ 0x0+ 0x0+ 0x0+1[0-9a-f]+ 0x0+1[0-9a-f]+ R E 0x10000 - +LOAD +0x0+1[0-9a-f]+ 0x0+11[0-9a-f]+ 0x0+11[0-9a-f]+ 0x0+0[0-9a-f]+ 0x0+= 0[0-9a-f]+ RW +0x10000 - +DYNAMIC +0x0+1[0-9a-f]+ 0x0+11[0-9a-f]+ 0x0+11[0-9a-f]+ 0x0+140 0x0+140 = RW +0x8 - +TLS +0x0+1[0-9a-f]+ 0x0+11[0-9a-f]+ 0x0+11[0-9a-f]+ 0x0+60 0x0+80 R +0x4 - +IA_64_UNWIND +0x0+1[0-9a-f]+ 0x0+1[0-9a-f]+ 0x0+1[0-9a-f]+ 0x0+18 0x0+18= R +0x8 -#... - -Relocation section '.rela.dyn' at offset 0x[0-9a-f]+ contains 6 entries: - +Offset +Info +Type +Symbol's Value +Symbol's Name \+ Addend -[0-9a-f ]+R_IA64_DTPMOD64LSB +0+ sg1 \+ 0 -[0-9a-f ]+R_IA64_DTPREL64LSB +0+ sg1 \+ 0 -[0-9a-f ]+R_IA64_TPREL64LSB +0+4 sg2 \+ 0 -[0-9a-f ]+R_IA64_DTPMOD64LSB +0 -[0-9a-f ]+R_IA64_TPREL64LSB +44 -[0-9a-f ]+R_IA64_TPREL64LSB +24 - -Relocation section '.rela.IA_64.pltoff' at offset 0x[0-9a-f]+ contains 1 e= ntry: - +Offset +Info +Type +Symbol's Value +Symbol's Name \+ Addend -[0-9a-f ]+R_IA64_IPLTLSB +0+ __tls_get_addr \+ 0 - -Symbol table '\.dynsym' contains [0-9]+ entries: - +Num: +Value +Size +Type +Bind +Vis +Ndx +Name -.* NOTYPE +LOCAL +DEFAULT +UND * -.* TLS +GLOBAL +DEFAULT +10 sg8 -.* TLS +GLOBAL +DEFAULT +10 sg3 -.* TLS +GLOBAL +DEFAULT +10 sg4 -.* TLS +GLOBAL +DEFAULT +10 sg5 -.* NOTYPE +GLOBAL +DEFAULT +UND __tls_get_addr -.* TLS +GLOBAL +DEFAULT +10 sg1 -.* FUNC +GLOBAL +DEFAULT +7 fn1 -.* TLS +GLOBAL +DEFAULT +10 sg2 -.* TLS +GLOBAL +DEFAULT +10 sg6 -.* TLS +GLOBAL +DEFAULT +10 sg7 - -Symbol table '\.symtab' contains [0-9]+ entries: - +Num: +Value +Size Type +Bind +Vis +Ndx Name -.* NOTYPE +LOCAL +DEFAULT +UND * -.* SECTION +LOCAL +DEFAULT +1.* -.* SECTION +LOCAL +DEFAULT +2.* -.* SECTION +LOCAL +DEFAULT +3.* -.* SECTION +LOCAL +DEFAULT +4.* -.* SECTION +LOCAL +DEFAULT +5.* -.* SECTION +LOCAL +DEFAULT +6.* -.* SECTION +LOCAL +DEFAULT +7.* -.* SECTION +LOCAL +DEFAULT +8.* -.* SECTION +LOCAL +DEFAULT +9.* -.* SECTION +LOCAL +DEFAULT +10.* -.* SECTION +LOCAL +DEFAULT +11.* -.* SECTION +LOCAL +DEFAULT +12.* -.* SECTION +LOCAL +DEFAULT +13.* -.* SECTION +LOCAL +DEFAULT +14.* -.* FILE +LOCAL +DEFAULT +ABS .* -.* TLS +LOCAL +DEFAULT +10 sl1 -.* TLS +LOCAL +DEFAULT +10 sl2 -.* TLS +LOCAL +DEFAULT +10 sl3 -.* TLS +LOCAL +DEFAULT +10 sl4 -.* TLS +LOCAL +DEFAULT +10 sl5 -.* TLS +LOCAL +DEFAULT +10 sl6 -.* TLS +LOCAL +DEFAULT +10 sl7 -.* TLS +LOCAL +DEFAULT +10 sl8 -.* FILE +LOCAL +DEFAULT +ABS=20 -.* TLS +LOCAL +DEFAULT +11 sH1 -.* OBJECT +LOCAL +DEFAULT +ABS _DYNAMIC -.* TLS +LOCAL +DEFAULT +10 sh3 -.* TLS +LOCAL +DEFAULT +11 sH2 -.* TLS +LOCAL +DEFAULT +11 sH7 -.* TLS +LOCAL +DEFAULT +10 sh7 -.* TLS +LOCAL +DEFAULT +10 sh8 -.* TLS +LOCAL +DEFAULT +11 sH4 -.* TLS +LOCAL +DEFAULT +10 sh4 -.* TLS +LOCAL +DEFAULT +11 sH3 -.* TLS +LOCAL +DEFAULT +10 sh5 -.* TLS +LOCAL +DEFAULT +11 sH5 -.* TLS +LOCAL +DEFAULT +11 sH6 -.* TLS +LOCAL +DEFAULT +11 sH8 -.* TLS +LOCAL +DEFAULT +10 sh1 -.* OBJECT +LOCAL +DEFAULT +ABS _GLOBAL_OFFSET_TABLE_ -.* TLS +LOCAL +DEFAULT +10 sh2 -.* TLS +LOCAL +DEFAULT +10 sh6 -.* TLS +GLOBAL +DEFAULT +10 sg8 -.* TLS +GLOBAL +DEFAULT +10 sg3 -.* TLS +GLOBAL +DEFAULT +10 sg4 -.* TLS +GLOBAL +DEFAULT +10 sg5 -.* NOTYPE +GLOBAL +DEFAULT +UND __tls_get_addr -.* TLS +GLOBAL +DEFAULT +10 sg1 -.* FUNC +GLOBAL +DEFAULT +7 fn1 -.* TLS +GLOBAL +DEFAULT +10 sg2 -.* TLS +GLOBAL +DEFAULT +10 sg6 -.* TLS +GLOBAL +DEFAULT +10 sg7 diff --git a/ld/testsuite/ld-ia64/tlspic.sd b/ld/testsuite/ld-ia64/tlspic.sd deleted file mode 100644 index 7b03a084321..00000000000 --- a/ld/testsuite/ld-ia64/tlspic.sd +++ /dev/null @@ -1,15 +0,0 @@ -#source: tlspic1.s -#source: tlspic2.s -#as: -#ld: -shared -#objdump: -sj.got -#target: ia64-*-* - -.*: +file format elf..-ia64-.* - -Contents of section .got: - 112d8 0+ 0+ 0+ 0+ .* - 112e8 0+ 0+ [0-9a-f]+ [0-9a-f]+ .* - 112f8 [0-9a-f]+ [0-9a-f]+ [0-9a-f]+ [0-9a-f]+ .* - 11308 [0-9a-f]+ [0-9a-f]+ [0-9a-f]+ [0-9a-f]+ .* - 11318 440+ 0+ [0-9a-f]+ [0-9a-f]+ .* diff --git a/ld/testsuite/ld-ia64/tlspic.td b/ld/testsuite/ld-ia64/tlspic.td deleted file mode 100644 index 47b5b6cc482..00000000000 --- a/ld/testsuite/ld-ia64/tlspic.td +++ /dev/null @@ -1,16 +0,0 @@ -#source: tlspic1.s -#source: tlspic2.s -#as: -#ld: -shared -#objdump: -sj.tdata -#target: ia64-*-* - -.*: +file format elf..-ia64-.* - -Contents of section .tdata: - 11[0-9a-f]+ 11000000 12000000 13000000 14000000 .* - 11[0-9a-f]+ 15000000 16000000 17000000 18000000 .* - 11[0-9a-f]+ 41000000 42000000 43000000 44000000 .* - 11[0-9a-f]+ 45000000 46000000 47000000 48000000 .* - 11[0-9a-f]+ 01010000 02010000 03010000 04010000 .* - 11[0-9a-f]+ 05010000 06010000 07010000 08010000 .* diff --git a/ld/testsuite/ld-ia64/tlspic1.s b/ld/testsuite/ld-ia64/tlspic1.s deleted file mode 100644 index 5242d28b466..00000000000 --- a/ld/testsuite/ld-ia64/tlspic1.s +++ /dev/null @@ -1,114 +0,0 @@ - /* Force .data aligned to 4K, so .got very likely gets at 0x13190 - (0x60 bytes .tdata and 0x130 bytes .dynamic) */ - .data - .balign 4096 - .section ".tdata", "awT", @progbits - .globl sg1, sg2, sg3, sg4, sg5, sg6, sg7, sg8 - .globl sh1, sh2, sh3, sh4, sh5, sh6, sh7, sh8 - .hidden sh1, sh2, sh3, sh4, sh5, sh6, sh7, sh8 -sg1: .long 17 -sg2: .long 18 -sg3: .long 19 -sg4: .long 20 -sg5: .long 21 -sg6: .long 22 -sg7: .long 23 -sg8: .long 24 -sl1: .long 65 -sl2: .long 66 -sl3: .long 67 -sl4: .long 68 -sl5: .long 69 -sl6: .long 70 -sl7: .long 71 -sl8: .long 72 -sh1: .long 257 -sh2: .long 258 -sh3: .long 259 -sh4: .long 260 -sh5: .long 261 -sh6: .long 262 -sh7: .long 263 -sh8: .long 264 - .explicit - .pred.safe_across_calls p1-p5,p16-p63 - /* Force .text aligned to 4K, so it very likely gets at 0x1000. */ - .text - .balign 4096 - .globl fn1# - .proc fn1# -fn1: - .prologue 12, 33 - .mib - .save ar.pfs, r34 - alloc r34 =3D ar.pfs, 0, 3, 2, 0 - .save rp, r33 - mov r33 =3D b0 - - /* GD */ - addl r14 =3D @ltoff(@dtpmod(sg1#)), gp - addl r15 =3D @ltoff(@dtprel(sg1#)), gp - ;; - ld8 out0 =3D [r14] - ld8 out1 =3D [r15] - br.call.sptk.many b0 =3D __tls_get_addr# - ;; - - /* GD against hidden symbol */ - addl r14 =3D @ltoff(@dtpmod(sh2#)), gp - addl r15 =3D @ltoff(@dtprel(sh2#)), gp - ;; - ld8 out0 =3D [r14] - ld8 out1 =3D [r15] - br.call.sptk.many b0 =3D __tls_get_addr# - ;; - - /* LD */ - addl r14 =3D @ltoff(@dtpmod(sl1#)), gp - addl out1 =3D @dtprel(sl1#) + 1, r0 - ;; - ld8 out0 =3D [r14] - br.call.sptk.many b0 =3D __tls_get_addr# - ;; - - /* LD with 4 variables variables */ - addl r14 =3D @ltoff(@dtpmod(sh1#)), gp - mov out1 =3D r0 - ;; - ld8 out0 =3D [r14] - br.call.sptk.many b0 =3D __tls_get_addr# - ;; - mov r2 =3D r8 - ;; - addl r14 =3D @dtprel(sh1#), r2 - addl r15 =3D @dtprel(sH1#) + 2, r2 - ;; - adds r14 =3D @dtprel(sh5#) + 3, r8 - movl r15 =3D @dtprel(sH5#) + 1 - ;; - add r15 =3D r15, r8 - ;; - - /* IE against global */ - addl r14 =3D @ltoff(@tprel(sg2#)), gp - ;; - ld8 r15 =3D [r14] - ;; - add r14 =3D r15, r13 - ;; - - /* IE against local and hidden */ - addl r14 =3D @ltoff(@tprel(sl2#)), gp - addl r15 =3D @ltoff(@tprel(sh2#)), gp - ;; - ld8 r14 =3D [r14] - ld8 r15 =3D [r15] - ;; - add r14 =3D r14, r13 - add r15 =3D r15, r13 - ;; - - mov ar.pfs =3D r34 - mov b0 =3D r33 - br.ret.sptk.many b0 - .endp fn1# diff --git a/ld/testsuite/ld-ia64/tlspic2.s b/ld/testsuite/ld-ia64/tlspic2.s deleted file mode 100644 index 5513f9b5851..00000000000 --- a/ld/testsuite/ld-ia64/tlspic2.s +++ /dev/null @@ -1,11 +0,0 @@ - .section ".tbss", "awT", @nobits - .globl sH1, sH2, sH3, sH4, sH5, sH6, sH7, sH8 - .hidden sH1, sH2, sH3, sH4, sH5, sH6, sH7, sH8 -sH1: .space 4 -sH2: .space 4 -sH3: .space 4 -sH4: .space 4 -sH5: .space 4 -sH6: .space 4 -sH7: .space 4 -sH8: .space 4 diff --git a/ld/testsuite/ld-ia64/undefined.s b/ld/testsuite/ld-ia64/undefi= ned.s deleted file mode 100644 index d563c62131b..00000000000 --- a/ld/testsuite/ld-ia64/undefined.s +++ /dev/null @@ -1,152 +0,0 @@ - .file "undefined.c" - .pred.safe_across_calls p1-p5,p16-p63 - .section .debug_abbrev,"",@progbits -.Ldebug_abbrev0: - .section .debug_info,"",@progbits -.Ldebug_info0: - .section .debug_line,"",@progbits -.Ldebug_line0: - .text -.Ltext0: - .align 16 - .global function# - .proc function# -function: -[.LFB2:] - .file 1 "undefined.c" - .loc 1 8 0 - .prologue 12, 32 - .mii - .save ar.pfs, r33 - alloc r33 =3D ar.pfs, 0, 3, 0, 0 - .save rp, r32 - mov r32 =3D b0 - mov r34 =3D r1 - .body - .loc 1 9 0 - ;; - .mib - nop 0 - nop 0 - br.call.sptk.many b0 =3D this_function_is_not_defined# - .loc 1 10 0 - ;; - .loc 1 9 0 - .mmi - nop 0 - mov r1 =3D r34 - .loc 1 10 0 - mov b0 =3D r32 - .mib - nop 0 - mov ar.pfs =3D r33 - br.ret.sptk.many b0 -.LFE2: - .endp function# -.Letext0: - .section .debug_info - data4.ua 0x4c - data2.ua 0x2 - data4.ua @secrel(.Ldebug_abbrev0) - data1 0x8 - .uleb128 0x1 - data4.ua @secrel(.Ldebug_line0) - data8.ua .Letext0 - data8.ua .Ltext0 - data4.ua @secrel(.LASF0) - data1 0x1 - data4.ua @secrel(.LASF1) - .uleb128 0x2 - data1 0x1 - data4.ua @secrel(.LASF2) - data1 0x1 - data1 0x8 - data4.ua 0x48 - data8.ua .LFB2 - data8.ua .LFE2 - data1 0x2 - data1 0x7c - .sleb128 16 - .uleb128 0x3 - stringz "int" - data1 0x4 - data1 0x5 - data1 0x0 - .section .debug_abbrev - .uleb128 0x1 - .uleb128 0x11 - data1 0x1 - .uleb128 0x10 - .uleb128 0x6 - .uleb128 0x12 - .uleb128 0x1 - .uleb128 0x11 - .uleb128 0x1 - .uleb128 0x25 - .uleb128 0xe - .uleb128 0x13 - .uleb128 0xb - .uleb128 0x3 - .uleb128 0xe - data1 0x0 - data1 0x0 - .uleb128 0x2 - .uleb128 0x2e - data1 0x0 - .uleb128 0x3f - .uleb128 0xc - .uleb128 0x3 - .uleb128 0xe - .uleb128 0x3a - .uleb128 0xb - .uleb128 0x3b - .uleb128 0xb - .uleb128 0x49 - .uleb128 0x13 - .uleb128 0x11 - .uleb128 0x1 - .uleb128 0x12 - .uleb128 0x1 - .uleb128 0x40 - .uleb128 0xa - data1 0x0 - data1 0x0 - .uleb128 0x3 - .uleb128 0x24 - data1 0x0 - .uleb128 0x3 - .uleb128 0x8 - .uleb128 0xb - .uleb128 0xb - .uleb128 0x3e - .uleb128 0xb - data1 0x0 - data1 0x0 - data1 0x0 - .section .debug_pubnames,"",@progbits - data4.ua 0x1b - data2.ua 0x2 - data4.ua @secrel(.Ldebug_info0) - data4.ua 0x50 - data4.ua 0x29 - stringz "function" - data4.ua 0x0 - .section .debug_aranges,"",@progbits - data4.ua 0x2c - data2.ua 0x2 - data4.ua @secrel(.Ldebug_info0) - data1 0x8 - data1 0x0 - data2.ua 0x0 - data2.ua 0x0 - data8.ua .Ltext0 - data8.ua .Letext0-.Ltext0 - data8.ua 0x0 - data8.ua 0x0 - .section .debug_str,"MS",@progbits,1 -.LASF0: - stringz "GNU C 4.1.2" -.LASF1: - stringz "undefined.c" -.LASF2: - stringz "function" diff --git a/ld/testsuite/ld-scripts/fill.d b/ld/testsuite/ld-scripts/fill.d index 73cc212e1f2..ce974469dee 100644 --- a/ld/testsuite/ld-scripts/fill.d +++ b/ld/testsuite/ld-scripts/fill.d @@ -4,7 +4,7 @@ #ld: -T fill.t #objdump: -s -j .text #notarget: [is_aout_format] -#skip: ia64-*-* mips*-*-freebsd* mips*-*-gnu* mips*-*-irix* mips*-*-kfreeb= sd* +#skip: mips*-*-freebsd* mips*-*-gnu* mips*-*-irix* mips*-*-kfreebsd* #skip: mips*-*-linux* mips*-*-netbsd* mips*-*-openbsd* mips*-*-sysv4* sh-*= -pe #skip: tilegx*-*-* tilepro-*-* x86_64-*-cygwin x86_64-*-mingw* x86_64-*-pe* #skip: kvx*-*-* @@ -17,7 +17,6 @@ # configurations are listed above. # # alpha-linuxecoff pads out code to 16 bytes. -# ia64 aligns code to minimum 16 bytes. # mips aligns to minimum 16 bytes (except for bare-metal ELF and VxWorks). # sh-pe pads out code sections to 16 bytes # tic30-coff aligns to 2 bytes diff --git a/ld/testsuite/ld-shared/shared.exp b/ld/testsuite/ld-shared/sha= red.exp index 1a0a4a020df..0646a77502d 100644 --- a/ld/testsuite/ld-shared/shared.exp +++ b/ld/testsuite/ld-shared/shared.exp @@ -43,8 +43,6 @@ if { ![istarget hppa*64*-*-hpux*] \ && ![istarget i?86-*-linux*] \ && ![istarget i?86-*-gnu*] \ && ![istarget *-*-nacl*] \ - && ![istarget ia64-*-elf*] \ - && ![istarget ia64-*-linux*] \ && ![istarget m68k-*-linux*] \ && ![istarget mips*-*-irix5*] \ && ![istarget mips*-*-linux*] \ @@ -224,7 +222,6 @@ if ![ld_compile "$CC_FOR_TARGET $SHCFLAG" $srcdir/$subd= ir/main.c $tmpdir/mainnp. } else { # Solaris defaults to -z text. setup_xfail "*-*-solaris2*" - setup_xfail "ia64-*-linux*" setup_xfail "alpha*-*-linux*" setup_xfail "powerpc-*-linux-musl" setup_xfail "powerpc64*-*-*" @@ -251,7 +248,6 @@ if ![ld_compile "$CC_FOR_TARGET $SHCFLAG" $srcdir/$subd= ir/main.c $tmpdir/mainnp. # the load address is not zero (which is the default). setup_xfail "*-*-linux*libc1" setup_xfail "powerpc*-*-linux*" - setup_xfail "ia64-*-linux*" setup_xfail "alpha*-*-linux*" setup_xfail "mips*-*-linux*" if { ![istarget hppa*64*-*-linux*] } { @@ -306,7 +302,6 @@ if ![ld_compile "$CC_FOR_TARGET $SHCFLAG $picflag" $src= dir/$subdir/main.c $tmpdi } else { # Solaris defaults to -z text. setup_xfail "*-*-solaris2*" - setup_xfail "ia64-*-linux*" setup_xfail "alpha*-*-linux*" setup_xfail "powerpc-*-linux-musl" setup_xfail "powerpc64*-*-*" diff --git a/ld/testsuite/ld-srec/srec.exp b/ld/testsuite/ld-srec/srec.exp index bf440a2fa39..93b3b9b938c 100644 --- a/ld/testsuite/ld-srec/srec.exp +++ b/ld/testsuite/ld-srec/srec.exp @@ -417,9 +417,6 @@ setup_xfail "alpha*-*-netbsd*" # Or MeP complex relocs. setup_xfail "hppa*-*-*" "mep-*-*" =20 -# The S-record linker doesn't handle IA64 Elf relaxation. -setup_xfail "ia64-*-*" - # The S-record linker doesn't support the special PE headers - the PE # emulation tries to write pe-specific information to the PE headers # in the output bfd, but it's not a PE bfd (it's an srec bfd) @@ -474,7 +471,6 @@ setup_xfail "v850*-*-elf" setup_xfail "alpha*-*-elf*" "alpha*-*-linux-*" "alpha*-*-gnu*" setup_xfail "alpha*-*-netbsd*" setup_xfail "hppa*-*-*" "mep-*-*" -setup_xfail "ia64-*-*" setup_xfail "*-*-cygwin*" "*-*-mingw*" "*-*-pe*" "*-*-winnt*" setup_xfail "score-*-*" setup_xfail "bfin-*-linux-uclibc" diff --git a/ld/testsuite/ld-unique/pr21529.d b/ld/testsuite/ld-unique/pr21= 529.d index 896f8722782..d08202edcfd 100644 --- a/ld/testsuite/ld-unique/pr21529.d +++ b/ld/testsuite/ld-unique/pr21529.d @@ -1,6 +1,6 @@ #ld: --oformat binary -T pr21529.ld -e main #objdump: -s -b binary -#xfail: aarch64*-*-* arm*-*-* avr-*-* ia64-*-* m68hc1*-*-* nds32*-*-* risc= v*-*-* score-*-* v850-*-* loongarch*-*-* +#xfail: aarch64*-*-* arm*-*-* avr-*-* m68hc1*-*-* nds32*-*-* riscv*-*-* sc= ore-*-* v850-*-* loongarch*-*-* # Skip targets which can't change output format to binary. =20 #pass diff --git a/ld/testsuite/ld-vsb/vsb.exp b/ld/testsuite/ld-vsb/vsb.exp index 43a34d936de..a09cd4ea561 100644 --- a/ld/testsuite/ld-vsb/vsb.exp +++ b/ld/testsuite/ld-vsb/vsb.exp @@ -37,7 +37,6 @@ if { ![istarget hppa*64*-*-hpux*] \ && ![istarget i?86-*-linux*] \ && ![istarget i?86-*-gnu*] \ && ![istarget *-*-nacl*] \ - && ![istarget ia64-*-linux*] \ && ![istarget m68k-*-linux*] \ && ![istarget mips*-*-linux*] \ && ![istarget powerpc*-*-linux*] \ @@ -312,7 +311,6 @@ proc visibility_run {visibility} { # used with overridable symbols. if { ![ string match $visibility "hidden_undef" ] && ![ string match $visibility "protected_undef" ] } { - setup_xfail "ia64-*-linux*" setup_xfail "alpha*-*-linux*" } if { ![ string match $visibility "hidden" ] @@ -369,7 +367,6 @@ proc visibility_run {visibility} { } if { ![ string match $visibility "hidden_undef" ] && ![ string match $visibility "protected_undef" ] } { - setup_xfail "ia64-*-linux*" setup_xfail "alpha*-*-linux*" setup_xfail "mips*-*-linux*" } @@ -435,7 +432,6 @@ proc visibility_run {visibility} { } if { ![ string match $visibility "hidden_undef" ] && ![ string match $visibility "protected_undef" ] } { - setup_xfail "ia64-*-linux*" setup_xfail "alpha*-*-linux*" } if { ![ string match $visibility "hidden" ] diff --git a/ld/testsuite/lib/ld-lib.exp b/ld/testsuite/lib/ld-lib.exp index e6e643ca3ca..516539c2fd6 100644 --- a/ld/testsuite/lib/ld-lib.exp +++ b/ld/testsuite/lib/ld-lib.exp @@ -1099,7 +1099,6 @@ proc check_gc_sections_available { } { || [istarget d30v-*-*] || [istarget dlx-*-*] || [istarget hppa*64-*-*] - || [istarget ia64-*-*] || [istarget mep-*-*] || [istarget mn10200-*-*] || [istarget pj*-*-*] diff --git a/libbacktrace/configure b/libbacktrace/configure index 9d22b74ba32..e82ebc8c899 100755 --- a/libbacktrace/configure +++ b/libbacktrace/configure @@ -6464,10 +6464,6 @@ haiku*) hpux10.20* | hpux11*) lt_cv_file_magic_cmd=3D/usr/bin/file case $host_cpu in - ia64*) - lt_cv_deplibs_check_method=3D'file_magic (s[0-9][0-9][0-9]|ELF-[0-9][0= -9]) shared object file - IA64' - lt_cv_file_magic_test_file=3D/usr/lib/hpux32/libc.so - ;; hppa*64*) lt_cv_deplibs_check_method=3D'file_magic (s[0-9][0-9][0-9]|ELF[ -][0-9= ][0-9])(-bit)?( [LM]SB)? shared object( file)?[, -]* PA-RISC [0-9]\.[0-9]' lt_cv_file_magic_test_file=3D/usr/lib/pa20_64/libc.sl @@ -7026,11 +7022,6 @@ aix*) cygwin* | mingw* | pw32* | cegcc*) symcode=3D'[ABCDGISTW]' ;; -hpux*) - if test "$host_cpu" =3D ia64; then - symcode=3D'[ABCDEGRST]' - fi - ;; irix* | nonstopux*) symcode=3D'[BCDEGRST]' ;; @@ -7061,7 +7052,7 @@ case `$NM -V 2>&1` in esac =20 # Transform an extracted symbol line into a proper C declaration. -# Some systems (esp. on ia64) link data and code symbols differently, +# Some systems link data and code symbols differently, # so use this general approach. lt_cv_sys_global_symbol_to_cdecl=3D"sed -n -e 's/^T .* \(.*\)$/extern int = \1();/p' -e 's/^$symcode* .* \(.*\)$/extern char \1;/p'" =20 @@ -7261,25 +7252,6 @@ test "x$enable_libtool_lock" !=3D xno && enable_libt= ool_lock=3Dyes # Some flags need to be propagated to the compiler or linker for good # libtool support. case $host in -ia64-*-hpux*) - # Find out which ABI we are using. - echo 'int i;' > conftest.$ac_ext - if { { eval echo "\"\$as_me\":${as_lineno-$LINENO}: \"$ac_compile\""; } = >&5 - (eval $ac_compile) 2>&5 - ac_status=3D$? - $as_echo "$as_me:${as_lineno-$LINENO}: \$? =3D $ac_status" >&5 - test $ac_status =3D 0; }; then - case `/usr/bin/file conftest.$ac_objext` in - *ELF-32*) - HPUX_IA64_MODE=3D"32" - ;; - *ELF-64*) - HPUX_IA64_MODE=3D"64" - ;; - esac - fi - rm -rf conftest* - ;; *-*-irix6*) # Find out which ABI we are using. echo '#line '$LINENO' "configure"' > conftest.$ac_ext @@ -8614,10 +8586,6 @@ $as_echo_n "checking for $compiler option to produce= PIC... " >&6; } case $host_os in aix*) # All AIX code is PIC. - if test "$host_cpu" =3D ia64; then - # AIX 5 now supports IA64 processor - lt_prog_compiler_static=3D'-Bstatic' - fi lt_prog_compiler_pic=3D'-fPIC' ;; =20 @@ -8714,12 +8682,7 @@ $as_echo_n "checking for $compiler option to produce= PIC... " >&6; } case $host_os in aix*) lt_prog_compiler_wl=3D'-Wl,' - if test "$host_cpu" =3D ia64; then - # AIX 5 now supports IA64 processor - lt_prog_compiler_static=3D'-Bstatic' - else - lt_prog_compiler_static=3D'-bnso -bI:/lib/syscalls.exp' - fi + lt_prog_compiler_static=3D'-bnso -bI:/lib/syscalls.exp' ;; =20 mingw* | cygwin* | pw32* | os2* | cegcc*) @@ -8733,7 +8696,7 @@ $as_echo_n "checking for $compiler option to produce = PIC... " >&6; } # PIC is the default for IA64 HP-UX and 64-bit HP-UX, but # not for PA HP-UX. case $host_cpu in - hppa*64*|ia64*) + hppa*64*) # +Z the default ;; *) @@ -9258,9 +9221,8 @@ $as_echo_n "checking whether the $compiler linker ($L= D) supports shared librarie case $host_os in aix[3-9]*) # On AIX/PPC, the GNU linker is very broken - if test "$host_cpu" !=3D ia64; then - ld_shlibs=3Dno - cat <<_LT_EOF 1>&2 + ld_shlibs=3Dno + cat <<_LT_EOF 1>&2 =20 *** Warning: the GNU linker, at least up to release 2.19, is reported *** to be unable to reliably create shared libraries on AIX. @@ -9270,7 +9232,6 @@ $as_echo_n "checking whether the $compiler linker ($L= D) supports shared librarie *** You will then need to restart the configuration process. =20 _LT_EOF - fi ;; =20 amigaos*) @@ -9366,10 +9327,6 @@ _LT_EOF # Portland Group f77 and f90 compilers whole_archive_flag_spec=3D'${wl}--whole-archive`for conv in $convenienc= e\"\"; do test -n \"$conv\" && new_convenience=3D\"$new_convenience,$conv\= "; done; func_echo_all \"$new_convenience\"` ${wl}--no-whole-archive' tmp_addflag=3D' $pic_flag -Mnomain' ;; - ecc*,ia64* | icc*,ia64*) # Intel C compiler on ia64 - tmp_addflag=3D' -i_dynamic' ;; - efc*,ia64* | ifort*,ia64*) # Intel Fortran compiler on ia64 - tmp_addflag=3D' -i_dynamic -nofor_main' ;; ifc* | ifort*) # Intel Fortran compiler tmp_addflag=3D' -nofor_main' ;; lf95*) # Lahey Fortran 8.1 @@ -9523,13 +9480,6 @@ _LT_EOF ;; =20 aix[4-9]*) - if test "$host_cpu" =3D ia64; then - # On IA64, the linker does run time linking by default, so we don't - # have to do anything special. - aix_use_runtimelinking=3Dno - exp_sym_flag=3D'-Bexport' - no_entry_flag=3D"" - else # If we're using GNU nm, then we don't want the "-C" option. # -C means demangle to AIX nm, but means don't demangle with GNU nm # Also, AIX nm treats weak defined symbols like other global @@ -9556,7 +9506,6 @@ _LT_EOF =20 exp_sym_flag=3D'-bexport' no_entry_flag=3D'-bnoentry' - fi =20 # When large executables or shared objects are built, AIX ld can # have problems creating the table of contents. If linking a library @@ -9599,17 +9548,11 @@ _LT_EOF fi else # not using gcc - if test "$host_cpu" =3D ia64; then - # VisualAge C++, Version 5.5 for AIX 5L for IA-64, Beta 3 Release - # chokes on -Wl,-G. The following line is correct: - shared_flag=3D'-G' - else if test "$aix_use_runtimelinking" =3D yes; then shared_flag=3D'${wl}-G' else shared_flag=3D'${wl}-bM:SRE' fi - fi fi =20 export_dynamic_flag_spec=3D'${wl}-bexpall' @@ -9655,11 +9598,6 @@ if test -z "$aix_libpath"; then aix_libpath=3D"/usr/= lib:/lib"; fi hardcode_libdir_flag_spec=3D'${wl}-blibpath:$libdir:'"$aix_libpath" archive_expsym_cmds=3D'$CC -o $output_objdir/$soname $libobjs $dep= libs '"\${wl}$no_entry_flag"' $compiler_flags `if test "x${allow_undefined_= flag}" !=3D "x"; then func_echo_all "${wl}${allow_undefined_flag}"; else :;= fi` '"\${wl}$exp_sym_flag:\$export_symbols $shared_flag" else - if test "$host_cpu" =3D ia64; then - hardcode_libdir_flag_spec=3D'${wl}-R $libdir:/usr/lib:/lib' - allow_undefined_flag=3D"-z nodefs" - archive_expsym_cmds=3D"\$CC $shared_flag"' -o $output_objdir/$soname $l= ibobjs $deplibs '"\${wl}$no_entry_flag"' $compiler_flags ${wl}${allow_undef= ined_flag} '"\${wl}$exp_sym_flag:\$export_symbols" - else # Determine the default libpath from the value encoded in an # empty executable. cat confdefs.h - <<_ACEOF >conftest.$ac_ext @@ -9707,7 +9645,6 @@ if test -z "$aix_libpath"; then aix_libpath=3D"/usr/l= ib:/lib"; fi archive_cmds_need_lc=3Dyes # This is similar to how AIX traditionally builds its shared libraries. archive_expsym_cmds=3D"\$CC $shared_flag"' -o $output_objdir/$soname $l= ibobjs $deplibs ${wl}-bnoentry $compiler_flags ${wl}-bE:$export_symbols${al= low_undefined_flag}~$AR $AR_FLAGS $output_objdir/$libname$release.a $output= _objdir/$soname' - fi fi ;; =20 @@ -9856,9 +9793,6 @@ if test -z "$aix_libpath"; then aix_libpath=3D"/usr/l= ib:/lib"; fi hppa*64*) archive_cmds=3D'$CC -shared ${wl}+h ${wl}$soname ${wl}+nodefaultrpath -= o $lib $libobjs $deplibs $compiler_flags' ;; - ia64*) - archive_cmds=3D'$CC -shared -fPIC ${wl}+h ${wl}$soname ${wl}+nodefaultr= path -o $lib $libobjs $deplibs $compiler_flags' - ;; *) archive_cmds=3D'$CC -shared -fPIC ${wl}+h ${wl}$soname ${wl}+b ${wl}$in= stall_libdir -o $lib $libobjs $deplibs $compiler_flags' ;; @@ -9868,9 +9802,6 @@ if test -z "$aix_libpath"; then aix_libpath=3D"/usr/l= ib:/lib"; fi hppa*64*) archive_cmds=3D'$CC -b ${wl}+h ${wl}$soname ${wl}+nodefaultrpath -o $li= b $libobjs $deplibs $compiler_flags' ;; - ia64*) - archive_cmds=3D'$CC -b ${wl}+h ${wl}$soname ${wl}+nodefaultrpath -o $li= b $libobjs $deplibs $compiler_flags' - ;; *) =20 # Older versions of the 11.00 compiler do not understand -b yet @@ -9920,7 +9851,7 @@ fi hardcode_libdir_separator=3D: =20 case $host_cpu in - hppa*64*|ia64*) + hppa*64*) hardcode_direct=3Dno hardcode_shlibpath_var=3Dno ;; @@ -10557,11 +10488,6 @@ aix[4-9]*) need_lib_prefix=3Dno need_version=3Dno hardcode_into_libs=3Dyes - if test "$host_cpu" =3D ia64; then - # AIX 5 supports IA64 - library_names_spec=3D'${libname}${release}${shared_ext}$major ${libnam= e}${release}${shared_ext}$versuffix $libname${shared_ext}' - shlibpath_var=3DLD_LIBRARY_PATH - else # With GCC up to 2.95.x, collect2 would create an import file # for dependence libraries. The import file would start with # the line `#! .'. This would cause the generated library to @@ -10593,7 +10519,6 @@ aix[4-9]*) soname_spec=3D'${libname}${release}${shared_ext}$major' fi shlibpath_var=3DLIBPATH - fi ;; =20 amigaos*) @@ -10770,21 +10695,6 @@ hpux9* | hpux10* | hpux11*) need_lib_prefix=3Dno need_version=3Dno case $host_cpu in - ia64*) - shrext_cmds=3D'.so' - hardcode_into_libs=3Dyes - dynamic_linker=3D"$host_os dld.so" - shlibpath_var=3DLD_LIBRARY_PATH - shlibpath_overrides_runpath=3Dyes # Unless +noenvvar is specified. - library_names_spec=3D'${libname}${release}${shared_ext}$versuffix ${li= bname}${release}${shared_ext}$major $libname${shared_ext}' - soname_spec=3D'${libname}${release}${shared_ext}$major' - if test "X$HPUX_IA64_MODE" =3D X32; then - sys_lib_search_path_spec=3D"/usr/lib/hpux32 /usr/local/lib/hpux32 /u= sr/local/lib" - else - sys_lib_search_path_spec=3D"/usr/lib/hpux64 /usr/local/lib/hpux64" - fi - sys_lib_dlsearch_path_spec=3D$sys_lib_search_path_spec - ;; hppa*64*) shrext_cmds=3D'.sl' hardcode_into_libs=3Dyes @@ -11875,7 +11785,7 @@ $as_echo_n "checking whether to build shared librar= ies... " >&6; } ;; =20 aix[4-9]*) - if test "$host_cpu" !=3D ia64 && test "$aix_use_runtimelinking" =3D no= ; then + if test "$aix_use_runtimelinking" =3D no ; then test "$enable_shared" =3D yes && enable_static=3Dno fi ;; @@ -12391,14 +12301,12 @@ fi # If system-libunwind was not specifically set, pick a default setting. if test x$with_system_libunwind =3D x; then case ${target} in - ia64-*-hpux*) with_system_libunwind=3Dyes ;; *) with_system_libunwind=3Dno ;; esac fi # Based on system-libunwind and target, do we have ipinfo? if test x$with_system_libunwind =3D xyes; then case ${target} in - ia64-*-*) have_unwind_getipinfo=3Dno ;; *) have_unwind_getipinfo=3Dyes ;; esac else diff --git a/libctf/configure b/libctf/configure index 1faadefa068..63a40b63cfe 100755 --- a/libctf/configure +++ b/libctf/configure @@ -8511,10 +8511,6 @@ haiku*) hpux10.20* | hpux11*) lt_cv_file_magic_cmd=3D/usr/bin/file case $host_cpu in - ia64*) - lt_cv_deplibs_check_method=3D'file_magic (s[0-9][0-9][0-9]|ELF-[0-9][0= -9]) shared object file - IA64' - lt_cv_file_magic_test_file=3D/usr/lib/hpux32/libc.so - ;; hppa*64*) lt_cv_deplibs_check_method=3D'file_magic (s[0-9][0-9][0-9]|ELF[ -][0-9= ][0-9])(-bit)?( [LM]SB)? shared object( file)?[, -]* PA-RISC [0-9]\.[0-9]' lt_cv_file_magic_test_file=3D/usr/lib/pa20_64/libc.sl @@ -9073,11 +9069,6 @@ aix*) cygwin* | mingw* | pw32* | cegcc*) symcode=3D'[ABCDGISTW]' ;; -hpux*) - if test "$host_cpu" =3D ia64; then - symcode=3D'[ABCDEGRST]' - fi - ;; irix* | nonstopux*) symcode=3D'[BCDEGRST]' ;; @@ -9108,7 +9099,7 @@ case `$NM -V 2>&1` in esac =20 # Transform an extracted symbol line into a proper C declaration. -# Some systems (esp. on ia64) link data and code symbols differently, +# Some systems link data and code symbols differently, # so use this general approach. lt_cv_sys_global_symbol_to_cdecl=3D"sed -n -e 's/^T .* \(.*\)$/extern int = \1();/p' -e 's/^$symcode* .* \(.*\)$/extern char \1;/p'" =20 @@ -9308,25 +9299,6 @@ test "x$enable_libtool_lock" !=3D xno && enable_libt= ool_lock=3Dyes # Some flags need to be propagated to the compiler or linker for good # libtool support. case $host in -ia64-*-hpux*) - # Find out which ABI we are using. - echo 'int i;' > conftest.$ac_ext - if { { eval echo "\"\$as_me\":${as_lineno-$LINENO}: \"$ac_compile\""; } = >&5 - (eval $ac_compile) 2>&5 - ac_status=3D$? - $as_echo "$as_me:${as_lineno-$LINENO}: \$? =3D $ac_status" >&5 - test $ac_status =3D 0; }; then - case `/usr/bin/file conftest.$ac_objext` in - *ELF-32*) - HPUX_IA64_MODE=3D"32" - ;; - *ELF-64*) - HPUX_IA64_MODE=3D"64" - ;; - esac - fi - rm -rf conftest* - ;; *-*-irix6*) # Find out which ABI we are using. echo '#line '$LINENO' "configure"' > conftest.$ac_ext @@ -10631,10 +10603,6 @@ $as_echo_n "checking for $compiler option to produ= ce PIC... " >&6; } case $host_os in aix*) # All AIX code is PIC. - if test "$host_cpu" =3D ia64; then - # AIX 5 now supports IA64 processor - lt_prog_compiler_static=3D'-Bstatic' - fi lt_prog_compiler_pic=3D'-fPIC' ;; =20 @@ -10731,12 +10699,7 @@ $as_echo_n "checking for $compiler option to produ= ce PIC... " >&6; } case $host_os in aix*) lt_prog_compiler_wl=3D'-Wl,' - if test "$host_cpu" =3D ia64; then - # AIX 5 now supports IA64 processor - lt_prog_compiler_static=3D'-Bstatic' - else - lt_prog_compiler_static=3D'-bnso -bI:/lib/syscalls.exp' - fi + lt_prog_compiler_static=3D'-bnso -bI:/lib/syscalls.exp' ;; =20 mingw* | cygwin* | pw32* | os2* | cegcc*) @@ -10750,7 +10713,7 @@ $as_echo_n "checking for $compiler option to produc= e PIC... " >&6; } # PIC is the default for IA64 HP-UX and 64-bit HP-UX, but # not for PA HP-UX. case $host_cpu in - hppa*64*|ia64*) + hppa*64*) # +Z the default ;; *) @@ -11275,7 +11238,6 @@ $as_echo_n "checking whether the $compiler linker (= $LD) supports shared librarie case $host_os in aix[3-9]*) # On AIX/PPC, the GNU linker is very broken - if test "$host_cpu" !=3D ia64; then ld_shlibs=3Dno cat <<_LT_EOF 1>&2 =20 @@ -11287,7 +11249,6 @@ $as_echo_n "checking whether the $compiler linker (= $LD) supports shared librarie *** You will then need to restart the configuration process. =20 _LT_EOF - fi ;; =20 amigaos*) @@ -11383,10 +11344,6 @@ _LT_EOF # Portland Group f77 and f90 compilers whole_archive_flag_spec=3D'${wl}--whole-archive`for conv in $convenienc= e\"\"; do test -n \"$conv\" && new_convenience=3D\"$new_convenience,$conv\= "; done; func_echo_all \"$new_convenience\"` ${wl}--no-whole-archive' tmp_addflag=3D' $pic_flag -Mnomain' ;; - ecc*,ia64* | icc*,ia64*) # Intel C compiler on ia64 - tmp_addflag=3D' -i_dynamic' ;; - efc*,ia64* | ifort*,ia64*) # Intel Fortran compiler on ia64 - tmp_addflag=3D' -i_dynamic -nofor_main' ;; ifc* | ifort*) # Intel Fortran compiler tmp_addflag=3D' -nofor_main' ;; lf95*) # Lahey Fortran 8.1 @@ -11540,13 +11497,6 @@ _LT_EOF ;; =20 aix[4-9]*) - if test "$host_cpu" =3D ia64; then - # On IA64, the linker does run time linking by default, so we don't - # have to do anything special. - aix_use_runtimelinking=3Dno - exp_sym_flag=3D'-Bexport' - no_entry_flag=3D"" - else # If we're using GNU nm, then we don't want the "-C" option. # -C means demangle to AIX nm, but means don't demangle with GNU nm # Also, AIX nm treats weak defined symbols like other global @@ -11573,7 +11523,6 @@ _LT_EOF =20 exp_sym_flag=3D'-bexport' no_entry_flag=3D'-bnoentry' - fi =20 # When large executables or shared objects are built, AIX ld can # have problems creating the table of contents. If linking a library @@ -11616,17 +11565,11 @@ _LT_EOF fi else # not using gcc - if test "$host_cpu" =3D ia64; then - # VisualAge C++, Version 5.5 for AIX 5L for IA-64, Beta 3 Release - # chokes on -Wl,-G. The following line is correct: - shared_flag=3D'-G' - else if test "$aix_use_runtimelinking" =3D yes; then shared_flag=3D'${wl}-G' else shared_flag=3D'${wl}-bM:SRE' fi - fi fi =20 export_dynamic_flag_spec=3D'${wl}-bexpall' @@ -11672,11 +11615,6 @@ if test -z "$aix_libpath"; then aix_libpath=3D"/us= r/lib:/lib"; fi hardcode_libdir_flag_spec=3D'${wl}-blibpath:$libdir:'"$aix_libpath" archive_expsym_cmds=3D'$CC -o $output_objdir/$soname $libobjs $dep= libs '"\${wl}$no_entry_flag"' $compiler_flags `if test "x${allow_undefined_= flag}" !=3D "x"; then func_echo_all "${wl}${allow_undefined_flag}"; else :;= fi` '"\${wl}$exp_sym_flag:\$export_symbols $shared_flag" else - if test "$host_cpu" =3D ia64; then - hardcode_libdir_flag_spec=3D'${wl}-R $libdir:/usr/lib:/lib' - allow_undefined_flag=3D"-z nodefs" - archive_expsym_cmds=3D"\$CC $shared_flag"' -o $output_objdir/$soname $l= ibobjs $deplibs '"\${wl}$no_entry_flag"' $compiler_flags ${wl}${allow_undef= ined_flag} '"\${wl}$exp_sym_flag:\$export_symbols" - else # Determine the default libpath from the value encoded in an # empty executable. cat confdefs.h - <<_ACEOF >conftest.$ac_ext @@ -11724,7 +11662,6 @@ if test -z "$aix_libpath"; then aix_libpath=3D"/usr= /lib:/lib"; fi archive_cmds_need_lc=3Dyes # This is similar to how AIX traditionally builds its shared libraries. archive_expsym_cmds=3D"\$CC $shared_flag"' -o $output_objdir/$soname $l= ibobjs $deplibs ${wl}-bnoentry $compiler_flags ${wl}-bE:$export_symbols${al= low_undefined_flag}~$AR $AR_FLAGS $output_objdir/$libname$release.a $output= _objdir/$soname' - fi fi ;; =20 @@ -11873,9 +11810,6 @@ if test -z "$aix_libpath"; then aix_libpath=3D"/usr= /lib:/lib"; fi hppa*64*) archive_cmds=3D'$CC -shared ${wl}+h ${wl}$soname ${wl}+nodefaultrpath -= o $lib $libobjs $deplibs $compiler_flags' ;; - ia64*) - archive_cmds=3D'$CC -shared -fPIC ${wl}+h ${wl}$soname ${wl}+nodefaultr= path -o $lib $libobjs $deplibs $compiler_flags' - ;; *) archive_cmds=3D'$CC -shared -fPIC ${wl}+h ${wl}$soname ${wl}+b ${wl}$in= stall_libdir -o $lib $libobjs $deplibs $compiler_flags' ;; @@ -11885,9 +11819,6 @@ if test -z "$aix_libpath"; then aix_libpath=3D"/usr= /lib:/lib"; fi hppa*64*) archive_cmds=3D'$CC -b ${wl}+h ${wl}$soname ${wl}+nodefaultrpath -o $li= b $libobjs $deplibs $compiler_flags' ;; - ia64*) - archive_cmds=3D'$CC -b ${wl}+h ${wl}$soname ${wl}+nodefaultrpath -o $li= b $libobjs $deplibs $compiler_flags' - ;; *) =20 # Older versions of the 11.00 compiler do not understand -b yet @@ -11937,7 +11868,7 @@ fi hardcode_libdir_separator=3D: =20 case $host_cpu in - hppa*64*|ia64*) + hppa*64*) hardcode_direct=3Dno hardcode_shlibpath_var=3Dno ;; @@ -12574,11 +12505,6 @@ aix[4-9]*) need_lib_prefix=3Dno need_version=3Dno hardcode_into_libs=3Dyes - if test "$host_cpu" =3D ia64; then - # AIX 5 supports IA64 - library_names_spec=3D'${libname}${release}${shared_ext}$major ${libnam= e}${release}${shared_ext}$versuffix $libname${shared_ext}' - shlibpath_var=3DLD_LIBRARY_PATH - else # With GCC up to 2.95.x, collect2 would create an import file # for dependence libraries. The import file would start with # the line `#! .'. This would cause the generated library to @@ -12610,7 +12536,6 @@ aix[4-9]*) soname_spec=3D'${libname}${release}${shared_ext}$major' fi shlibpath_var=3DLIBPATH - fi ;; =20 amigaos*) @@ -12787,21 +12712,6 @@ hpux9* | hpux10* | hpux11*) need_lib_prefix=3Dno need_version=3Dno case $host_cpu in - ia64*) - shrext_cmds=3D'.so' - hardcode_into_libs=3Dyes - dynamic_linker=3D"$host_os dld.so" - shlibpath_var=3DLD_LIBRARY_PATH - shlibpath_overrides_runpath=3Dyes # Unless +noenvvar is specified. - library_names_spec=3D'${libname}${release}${shared_ext}$versuffix ${li= bname}${release}${shared_ext}$major $libname${shared_ext}' - soname_spec=3D'${libname}${release}${shared_ext}$major' - if test "X$HPUX_IA64_MODE" =3D X32; then - sys_lib_search_path_spec=3D"/usr/lib/hpux32 /usr/local/lib/hpux32 /u= sr/local/lib" - else - sys_lib_search_path_spec=3D"/usr/lib/hpux64 /usr/local/lib/hpux64" - fi - sys_lib_dlsearch_path_spec=3D$sys_lib_search_path_spec - ;; hppa*64*) shrext_cmds=3D'.sl' hardcode_into_libs=3Dyes @@ -13892,7 +13802,7 @@ $as_echo_n "checking whether to build shared librar= ies... " >&6; } ;; =20 aix[4-9]*) - if test "$host_cpu" !=3D ia64 && test "$aix_use_runtimelinking" =3D no= ; then + if test "$aix_use_runtimelinking" =3D no ; then test "$enable_shared" =3D yes && enable_static=3Dno fi ;; diff --git a/libiberty/configure b/libiberty/configure index 18e98b84bb5..ce55c13be1c 100755 --- a/libiberty/configure +++ b/libiberty/configure @@ -5353,11 +5353,6 @@ case "${host}" in i[34567]86-pc-msdosdjgpp*) # DJGPP does not support shared libraries at all. ;; - ia64*-*-hpux*) - # On IA64 HP-UX, PIC is the default but the pic flag - # sets the default TLS model and affects inlining. - PICFLAG=3D-fPIC - ;; loongarch*-*-*) PICFLAG=3D-fpic ;; diff --git a/libiberty/floatformat.c b/libiberty/floatformat.c index dd2f97119b6..4dacf5ddee4 100644 --- a/libiberty/floatformat.c +++ b/libiberty/floatformat.c @@ -269,22 +269,6 @@ const struct floatformat floatformat_arm_ext_littlebyt= e_bigword =3D floatformat_always_valid, NULL }; -const struct floatformat floatformat_ia64_spill_big =3D -{ - floatformat_big, 128, 0, 1, 17, 65535, 0x1ffff, 18, 64, - floatformat_intbit_yes, - "floatformat_ia64_spill_big", - floatformat_always_valid, - NULL -}; -const struct floatformat floatformat_ia64_spill_little =3D -{ - floatformat_little, 128, 0, 1, 17, 65535, 0x1ffff, 18, 64, - floatformat_intbit_yes, - "floatformat_ia64_spill_little", - floatformat_always_valid, - NULL -}; =20 static int floatformat_ibm_long_double_is_valid (const struct floatformat *fmt, diff --git a/libsframe/configure b/libsframe/configure index 8a9018c493e..dbd26300ea2 100755 --- a/libsframe/configure +++ b/libsframe/configure @@ -6432,10 +6432,6 @@ haiku*) hpux10.20* | hpux11*) lt_cv_file_magic_cmd=3D/usr/bin/file case $host_cpu in - ia64*) - lt_cv_deplibs_check_method=3D'file_magic (s[0-9][0-9][0-9]|ELF-[0-9][0= -9]) shared object file - IA64' - lt_cv_file_magic_test_file=3D/usr/lib/hpux32/libc.so - ;; hppa*64*) lt_cv_deplibs_check_method=3D'file_magic (s[0-9][0-9][0-9]|ELF[ -][0-9= ][0-9])(-bit)?( [LM]SB)? shared object( file)?[, -]* PA-RISC [0-9]\.[0-9]' lt_cv_file_magic_test_file=3D/usr/lib/pa20_64/libc.sl @@ -6994,11 +6990,6 @@ aix*) cygwin* | mingw* | pw32* | cegcc*) symcode=3D'[ABCDGISTW]' ;; -hpux*) - if test "$host_cpu" =3D ia64; then - symcode=3D'[ABCDEGRST]' - fi - ;; irix* | nonstopux*) symcode=3D'[BCDEGRST]' ;; @@ -7029,7 +7020,7 @@ case `$NM -V 2>&1` in esac =20 # Transform an extracted symbol line into a proper C declaration. -# Some systems (esp. on ia64) link data and code symbols differently, +# Some systems link data and code symbols differently, # so use this general approach. lt_cv_sys_global_symbol_to_cdecl=3D"sed -n -e 's/^T .* \(.*\)$/extern int = \1();/p' -e 's/^$symcode* .* \(.*\)$/extern char \1;/p'" =20 @@ -7229,25 +7220,6 @@ test "x$enable_libtool_lock" !=3D xno && enable_libt= ool_lock=3Dyes # Some flags need to be propagated to the compiler or linker for good # libtool support. case $host in -ia64-*-hpux*) - # Find out which ABI we are using. - echo 'int i;' > conftest.$ac_ext - if { { eval echo "\"\$as_me\":${as_lineno-$LINENO}: \"$ac_compile\""; } = >&5 - (eval $ac_compile) 2>&5 - ac_status=3D$? - $as_echo "$as_me:${as_lineno-$LINENO}: \$? =3D $ac_status" >&5 - test $ac_status =3D 0; }; then - case `/usr/bin/file conftest.$ac_objext` in - *ELF-32*) - HPUX_IA64_MODE=3D"32" - ;; - *ELF-64*) - HPUX_IA64_MODE=3D"64" - ;; - esac - fi - rm -rf conftest* - ;; *-*-irix6*) # Find out which ABI we are using. echo '#line '$LINENO' "configure"' > conftest.$ac_ext @@ -8552,10 +8524,6 @@ $as_echo_n "checking for $compiler option to produce= PIC... " >&6; } case $host_os in aix*) # All AIX code is PIC. - if test "$host_cpu" =3D ia64; then - # AIX 5 now supports IA64 processor - lt_prog_compiler_static=3D'-Bstatic' - fi lt_prog_compiler_pic=3D'-fPIC' ;; =20 @@ -8652,12 +8620,7 @@ $as_echo_n "checking for $compiler option to produce= PIC... " >&6; } case $host_os in aix*) lt_prog_compiler_wl=3D'-Wl,' - if test "$host_cpu" =3D ia64; then - # AIX 5 now supports IA64 processor - lt_prog_compiler_static=3D'-Bstatic' - else - lt_prog_compiler_static=3D'-bnso -bI:/lib/syscalls.exp' - fi + lt_prog_compiler_static=3D'-bnso -bI:/lib/syscalls.exp' ;; =20 mingw* | cygwin* | pw32* | os2* | cegcc*) @@ -8671,7 +8634,7 @@ $as_echo_n "checking for $compiler option to produce = PIC... " >&6; } # PIC is the default for IA64 HP-UX and 64-bit HP-UX, but # not for PA HP-UX. case $host_cpu in - hppa*64*|ia64*) + hppa*64*) # +Z the default ;; *) @@ -9196,7 +9159,6 @@ $as_echo_n "checking whether the $compiler linker ($L= D) supports shared librarie case $host_os in aix[3-9]*) # On AIX/PPC, the GNU linker is very broken - if test "$host_cpu" !=3D ia64; then ld_shlibs=3Dno cat <<_LT_EOF 1>&2 =20 @@ -9208,7 +9170,6 @@ $as_echo_n "checking whether the $compiler linker ($L= D) supports shared librarie *** You will then need to restart the configuration process. =20 _LT_EOF - fi ;; =20 amigaos*) @@ -9304,10 +9265,6 @@ _LT_EOF # Portland Group f77 and f90 compilers whole_archive_flag_spec=3D'${wl}--whole-archive`for conv in $convenienc= e\"\"; do test -n \"$conv\" && new_convenience=3D\"$new_convenience,$conv\= "; done; func_echo_all \"$new_convenience\"` ${wl}--no-whole-archive' tmp_addflag=3D' $pic_flag -Mnomain' ;; - ecc*,ia64* | icc*,ia64*) # Intel C compiler on ia64 - tmp_addflag=3D' -i_dynamic' ;; - efc*,ia64* | ifort*,ia64*) # Intel Fortran compiler on ia64 - tmp_addflag=3D' -i_dynamic -nofor_main' ;; ifc* | ifort*) # Intel Fortran compiler tmp_addflag=3D' -nofor_main' ;; lf95*) # Lahey Fortran 8.1 @@ -9461,13 +9418,6 @@ _LT_EOF ;; =20 aix[4-9]*) - if test "$host_cpu" =3D ia64; then - # On IA64, the linker does run time linking by default, so we don't - # have to do anything special. - aix_use_runtimelinking=3Dno - exp_sym_flag=3D'-Bexport' - no_entry_flag=3D"" - else # If we're using GNU nm, then we don't want the "-C" option. # -C means demangle to AIX nm, but means don't demangle with GNU nm # Also, AIX nm treats weak defined symbols like other global @@ -9494,7 +9444,6 @@ _LT_EOF =20 exp_sym_flag=3D'-bexport' no_entry_flag=3D'-bnoentry' - fi =20 # When large executables or shared objects are built, AIX ld can # have problems creating the table of contents. If linking a library @@ -9537,17 +9486,11 @@ _LT_EOF fi else # not using gcc - if test "$host_cpu" =3D ia64; then - # VisualAge C++, Version 5.5 for AIX 5L for IA-64, Beta 3 Release - # chokes on -Wl,-G. The following line is correct: - shared_flag=3D'-G' - else if test "$aix_use_runtimelinking" =3D yes; then shared_flag=3D'${wl}-G' else shared_flag=3D'${wl}-bM:SRE' fi - fi fi =20 export_dynamic_flag_spec=3D'${wl}-bexpall' @@ -9593,11 +9536,6 @@ if test -z "$aix_libpath"; then aix_libpath=3D"/usr/= lib:/lib"; fi hardcode_libdir_flag_spec=3D'${wl}-blibpath:$libdir:'"$aix_libpath" archive_expsym_cmds=3D'$CC -o $output_objdir/$soname $libobjs $dep= libs '"\${wl}$no_entry_flag"' $compiler_flags `if test "x${allow_undefined_= flag}" !=3D "x"; then func_echo_all "${wl}${allow_undefined_flag}"; else :;= fi` '"\${wl}$exp_sym_flag:\$export_symbols $shared_flag" else - if test "$host_cpu" =3D ia64; then - hardcode_libdir_flag_spec=3D'${wl}-R $libdir:/usr/lib:/lib' - allow_undefined_flag=3D"-z nodefs" - archive_expsym_cmds=3D"\$CC $shared_flag"' -o $output_objdir/$soname $l= ibobjs $deplibs '"\${wl}$no_entry_flag"' $compiler_flags ${wl}${allow_undef= ined_flag} '"\${wl}$exp_sym_flag:\$export_symbols" - else # Determine the default libpath from the value encoded in an # empty executable. cat confdefs.h - <<_ACEOF >conftest.$ac_ext @@ -9645,7 +9583,6 @@ if test -z "$aix_libpath"; then aix_libpath=3D"/usr/l= ib:/lib"; fi archive_cmds_need_lc=3Dyes # This is similar to how AIX traditionally builds its shared libraries. archive_expsym_cmds=3D"\$CC $shared_flag"' -o $output_objdir/$soname $l= ibobjs $deplibs ${wl}-bnoentry $compiler_flags ${wl}-bE:$export_symbols${al= low_undefined_flag}~$AR $AR_FLAGS $output_objdir/$libname$release.a $output= _objdir/$soname' - fi fi ;; =20 @@ -9794,9 +9731,6 @@ if test -z "$aix_libpath"; then aix_libpath=3D"/usr/l= ib:/lib"; fi hppa*64*) archive_cmds=3D'$CC -shared ${wl}+h ${wl}$soname ${wl}+nodefaultrpath -= o $lib $libobjs $deplibs $compiler_flags' ;; - ia64*) - archive_cmds=3D'$CC -shared -fPIC ${wl}+h ${wl}$soname ${wl}+nodefaultr= path -o $lib $libobjs $deplibs $compiler_flags' - ;; *) archive_cmds=3D'$CC -shared -fPIC ${wl}+h ${wl}$soname ${wl}+b ${wl}$in= stall_libdir -o $lib $libobjs $deplibs $compiler_flags' ;; @@ -9806,9 +9740,6 @@ if test -z "$aix_libpath"; then aix_libpath=3D"/usr/l= ib:/lib"; fi hppa*64*) archive_cmds=3D'$CC -b ${wl}+h ${wl}$soname ${wl}+nodefaultrpath -o $li= b $libobjs $deplibs $compiler_flags' ;; - ia64*) - archive_cmds=3D'$CC -b ${wl}+h ${wl}$soname ${wl}+nodefaultrpath -o $li= b $libobjs $deplibs $compiler_flags' - ;; *) =20 # Older versions of the 11.00 compiler do not understand -b yet @@ -9858,7 +9789,7 @@ fi hardcode_libdir_separator=3D: =20 case $host_cpu in - hppa*64*|ia64*) + hppa*64*) hardcode_direct=3Dno hardcode_shlibpath_var=3Dno ;; @@ -10495,11 +10426,6 @@ aix[4-9]*) need_lib_prefix=3Dno need_version=3Dno hardcode_into_libs=3Dyes - if test "$host_cpu" =3D ia64; then - # AIX 5 supports IA64 - library_names_spec=3D'${libname}${release}${shared_ext}$major ${libnam= e}${release}${shared_ext}$versuffix $libname${shared_ext}' - shlibpath_var=3DLD_LIBRARY_PATH - else # With GCC up to 2.95.x, collect2 would create an import file # for dependence libraries. The import file would start with # the line `#! .'. This would cause the generated library to @@ -10531,7 +10457,6 @@ aix[4-9]*) soname_spec=3D'${libname}${release}${shared_ext}$major' fi shlibpath_var=3DLIBPATH - fi ;; =20 amigaos*) @@ -10708,21 +10633,6 @@ hpux9* | hpux10* | hpux11*) need_lib_prefix=3Dno need_version=3Dno case $host_cpu in - ia64*) - shrext_cmds=3D'.so' - hardcode_into_libs=3Dyes - dynamic_linker=3D"$host_os dld.so" - shlibpath_var=3DLD_LIBRARY_PATH - shlibpath_overrides_runpath=3Dyes # Unless +noenvvar is specified. - library_names_spec=3D'${libname}${release}${shared_ext}$versuffix ${li= bname}${release}${shared_ext}$major $libname${shared_ext}' - soname_spec=3D'${libname}${release}${shared_ext}$major' - if test "X$HPUX_IA64_MODE" =3D X32; then - sys_lib_search_path_spec=3D"/usr/lib/hpux32 /usr/local/lib/hpux32 /u= sr/local/lib" - else - sys_lib_search_path_spec=3D"/usr/lib/hpux64 /usr/local/lib/hpux64" - fi - sys_lib_dlsearch_path_spec=3D$sys_lib_search_path_spec - ;; hppa*64*) shrext_cmds=3D'.sl' hardcode_into_libs=3Dyes @@ -11813,7 +11723,7 @@ $as_echo_n "checking whether to build shared librar= ies... " >&6; } ;; =20 aix[4-9]*) - if test "$host_cpu" !=3D ia64 && test "$aix_use_runtimelinking" =3D no= ; then + if test "$aix_use_runtimelinking" =3D no ; then test "$enable_shared" =3D yes && enable_static=3Dno fi ;; diff --git a/libtool.m4 b/libtool.m4 index e36fdd3c0e2..1d0d90d0d9f 100644 --- a/libtool.m4 +++ b/libtool.m4 @@ -1174,21 +1174,6 @@ test "x$enable_libtool_lock" !=3D xno && enable_libt= ool_lock=3Dyes # Some flags need to be propagated to the compiler or linker for good # libtool support. case $host in -ia64-*-hpux*) - # Find out which ABI we are using. - echo 'int i;' > conftest.$ac_ext - if AC_TRY_EVAL(ac_compile); then - case `/usr/bin/file conftest.$ac_objext` in - *ELF-32*) - HPUX_IA64_MODE=3D"32" - ;; - *ELF-64*) - HPUX_IA64_MODE=3D"64" - ;; - esac - fi - rm -rf conftest* - ;; *-*-irix6*) # Find out which ABI we are using. echo '[#]line '$LINENO' "configure"' > conftest.$ac_ext @@ -2162,11 +2147,6 @@ aix[[4-9]]*) need_lib_prefix=3Dno need_version=3Dno hardcode_into_libs=3Dyes - if test "$host_cpu" =3D ia64; then - # AIX 5 supports IA64 - library_names_spec=3D'${libname}${release}${shared_ext}$major ${libnam= e}${release}${shared_ext}$versuffix $libname${shared_ext}' - shlibpath_var=3DLD_LIBRARY_PATH - else # With GCC up to 2.95.x, collect2 would create an import file # for dependence libraries. The import file would start with # the line `#! .'. This would cause the generated library to @@ -2198,7 +2178,6 @@ aix[[4-9]]*) soname_spec=3D'${libname}${release}${shared_ext}$major' fi shlibpath_var=3DLIBPATH - fi ;; =20 amigaos*) @@ -2375,21 +2354,6 @@ hpux9* | hpux10* | hpux11*) need_lib_prefix=3Dno need_version=3Dno case $host_cpu in - ia64*) - shrext_cmds=3D'.so' - hardcode_into_libs=3Dyes - dynamic_linker=3D"$host_os dld.so" - shlibpath_var=3DLD_LIBRARY_PATH - shlibpath_overrides_runpath=3Dyes # Unless +noenvvar is specified. - library_names_spec=3D'${libname}${release}${shared_ext}$versuffix ${li= bname}${release}${shared_ext}$major $libname${shared_ext}' - soname_spec=3D'${libname}${release}${shared_ext}$major' - if test "X$HPUX_IA64_MODE" =3D X32; then - sys_lib_search_path_spec=3D"/usr/lib/hpux32 /usr/local/lib/hpux32 /u= sr/local/lib" - else - sys_lib_search_path_spec=3D"/usr/lib/hpux64 /usr/local/lib/hpux64" - fi - sys_lib_dlsearch_path_spec=3D$sys_lib_search_path_spec - ;; hppa*64*) shrext_cmds=3D'.sl' hardcode_into_libs=3Dyes @@ -3104,10 +3068,6 @@ haiku*) hpux10.20* | hpux11*) lt_cv_file_magic_cmd=3D/usr/bin/file case $host_cpu in - ia64*) - lt_cv_deplibs_check_method=3D'file_magic (s[[0-9]][[0-9]][[0-9]]|ELF-[= [0-9]][[0-9]]) shared object file - IA64' - lt_cv_file_magic_test_file=3D/usr/lib/hpux32/libc.so - ;; hppa*64*) [lt_cv_deplibs_check_method=3D'file_magic (s[0-9][0-9][0-9]|ELF[ -][0-= 9][0-9])(-bit)?( [LM]SB)? shared object( file)?[, -]* PA-RISC [0-9]\.[0-9]'] lt_cv_file_magic_test_file=3D/usr/lib/pa20_64/libc.sl @@ -3422,11 +3382,6 @@ aix*) cygwin* | mingw* | pw32* | cegcc*) symcode=3D'[[ABCDGISTW]]' ;; -hpux*) - if test "$host_cpu" =3D ia64; then - symcode=3D'[[ABCDEGRST]]' - fi - ;; irix* | nonstopux*) symcode=3D'[[BCDEGRST]]' ;; @@ -3457,7 +3412,7 @@ case `$NM -V 2>&1` in esac =20 # Transform an extracted symbol line into a proper C declaration. -# Some systems (esp. on ia64) link data and code symbols differently, +# Some systems link data and code symbols differently, # so use this general approach. lt_cv_sys_global_symbol_to_cdecl=3D"sed -n -e 's/^T .* \(.*\)$/extern int = \1();/p' -e 's/^$symcode* .* \(.*\)$/extern char \1;/p'" =20 @@ -3641,10 +3596,6 @@ m4_if([$1], [CXX], [ case $host_os in aix*) # All AIX code is PIC. - if test "$host_cpu" =3D ia64; then - # AIX 5 now supports IA64 processor - _LT_TAGVAR(lt_prog_compiler_static, $1)=3D'-Bstatic' - fi _LT_TAGVAR(lt_prog_compiler_pic, $1)=3D'-fPIC' ;; =20 @@ -3722,12 +3673,7 @@ m4_if([$1], [CXX], [ case $host_os in aix[[4-9]]*) # All AIX code is PIC. - if test "$host_cpu" =3D ia64; then - # AIX 5 now supports IA64 processor - _LT_TAGVAR(lt_prog_compiler_static, $1)=3D'-Bstatic' - else - _LT_TAGVAR(lt_prog_compiler_static, $1)=3D'-bnso -bI:/lib/syscalls.exp' - fi + _LT_TAGVAR(lt_prog_compiler_static, $1)=3D'-bnso -bI:/lib/syscalls.exp' ;; chorus*) case $cc_basename in @@ -3758,15 +3704,13 @@ m4_if([$1], [CXX], [ CC*) _LT_TAGVAR(lt_prog_compiler_wl, $1)=3D'-Wl,' _LT_TAGVAR(lt_prog_compiler_static, $1)=3D'${wl}-a ${wl}archive' - if test "$host_cpu" !=3D ia64; then - _LT_TAGVAR(lt_prog_compiler_pic, $1)=3D'+Z' - fi + _LT_TAGVAR(lt_prog_compiler_pic, $1)=3D'+Z' ;; aCC*) _LT_TAGVAR(lt_prog_compiler_wl, $1)=3D'-Wl,' _LT_TAGVAR(lt_prog_compiler_static, $1)=3D'${wl}-a ${wl}archive' case $host_cpu in - hppa*64*|ia64*) + hppa*64*) # +Z the default ;; *) @@ -3953,10 +3897,6 @@ m4_if([$1], [CXX], [ case $host_os in aix*) # All AIX code is PIC. - if test "$host_cpu" =3D ia64; then - # AIX 5 now supports IA64 processor - _LT_TAGVAR(lt_prog_compiler_static, $1)=3D'-Bstatic' - fi _LT_TAGVAR(lt_prog_compiler_pic, $1)=3D'-fPIC' ;; =20 @@ -4054,12 +3994,7 @@ m4_if([$1], [CXX], [ case $host_os in aix*) _LT_TAGVAR(lt_prog_compiler_wl, $1)=3D'-Wl,' - if test "$host_cpu" =3D ia64; then - # AIX 5 now supports IA64 processor - _LT_TAGVAR(lt_prog_compiler_static, $1)=3D'-Bstatic' - else - _LT_TAGVAR(lt_prog_compiler_static, $1)=3D'-bnso -bI:/lib/syscalls.exp' - fi + _LT_TAGVAR(lt_prog_compiler_static, $1)=3D'-bnso -bI:/lib/syscalls.e= xp' ;; =20 mingw* | cygwin* | pw32* | os2* | cegcc*) @@ -4074,7 +4009,7 @@ m4_if([$1], [CXX], [ # PIC is the default for IA64 HP-UX and 64-bit HP-UX, but # not for PA HP-UX. case $host_cpu in - hppa*64*|ia64*) + hppa*64*) # +Z the default ;; *) @@ -4421,7 +4356,6 @@ dnl Note also adjust exclude_expsyms for C++ above. case $host_os in aix[[3-9]]*) # On AIX/PPC, the GNU linker is very broken - if test "$host_cpu" !=3D ia64; then _LT_TAGVAR(ld_shlibs, $1)=3Dno cat <<_LT_EOF 1>&2 =20 @@ -4433,7 +4367,6 @@ dnl Note also adjust exclude_expsyms for C++ above. *** You will then need to restart the configuration process. =20 _LT_EOF - fi ;; =20 amigaos*) @@ -4529,10 +4462,6 @@ _LT_EOF # Portland Group f77 and f90 compilers _LT_TAGVAR(whole_archive_flag_spec, $1)=3D'${wl}--whole-archive`for con= v in $convenience\"\"; do test -n \"$conv\" && new_convenience=3D\"$new_co= nvenience,$conv\"; done; func_echo_all \"$new_convenience\"` ${wl}--no-whol= e-archive' tmp_addflag=3D' $pic_flag -Mnomain' ;; - ecc*,ia64* | icc*,ia64*) # Intel C compiler on ia64 - tmp_addflag=3D' -i_dynamic' ;; - efc*,ia64* | ifort*,ia64*) # Intel Fortran compiler on ia64 - tmp_addflag=3D' -i_dynamic -nofor_main' ;; ifc* | ifort*) # Intel Fortran compiler tmp_addflag=3D' -nofor_main' ;; lf95*) # Lahey Fortran 8.1 @@ -4686,13 +4615,6 @@ _LT_EOF ;; =20 aix[[4-9]]*) - if test "$host_cpu" =3D ia64; then - # On IA64, the linker does run time linking by default, so we don't - # have to do anything special. - aix_use_runtimelinking=3Dno - exp_sym_flag=3D'-Bexport' - no_entry_flag=3D"" - else # If we're using GNU nm, then we don't want the "-C" option. # -C means demangle to AIX nm, but means don't demangle with GNU nm # Also, AIX nm treats weak defined symbols like other global @@ -4719,7 +4641,6 @@ _LT_EOF =20 exp_sym_flag=3D'-bexport' no_entry_flag=3D'-bnoentry' - fi =20 # When large executables or shared objects are built, AIX ld can # have problems creating the table of contents. If linking a library @@ -4762,17 +4683,11 @@ _LT_EOF fi else # not using gcc - if test "$host_cpu" =3D ia64; then - # VisualAge C++, Version 5.5 for AIX 5L for IA-64, Beta 3 Release - # chokes on -Wl,-G. The following line is correct: - shared_flag=3D'-G' - else if test "$aix_use_runtimelinking" =3D yes; then shared_flag=3D'${wl}-G' else shared_flag=3D'${wl}-bM:SRE' fi - fi fi =20 _LT_TAGVAR(export_dynamic_flag_spec, $1)=3D'${wl}-bexpall' @@ -4789,11 +4704,6 @@ _LT_EOF _LT_TAGVAR(hardcode_libdir_flag_spec, $1)=3D'${wl}-blibpath:$libdi= r:'"$aix_libpath" _LT_TAGVAR(archive_expsym_cmds, $1)=3D'$CC -o $output_objdir/$sona= me $libobjs $deplibs '"\${wl}$no_entry_flag"' $compiler_flags `if test "x${= allow_undefined_flag}" !=3D "x"; then func_echo_all "${wl}${allow_undefined= _flag}"; else :; fi` '"\${wl}$exp_sym_flag:\$export_symbols $shared_flag" else - if test "$host_cpu" =3D ia64; then - _LT_TAGVAR(hardcode_libdir_flag_spec, $1)=3D'${wl}-R $libdir:/usr/lib:/= lib' - _LT_TAGVAR(allow_undefined_flag, $1)=3D"-z nodefs" - _LT_TAGVAR(archive_expsym_cmds, $1)=3D"\$CC $shared_flag"' -o $output_o= bjdir/$soname $libobjs $deplibs '"\${wl}$no_entry_flag"' $compiler_flags ${= wl}${allow_undefined_flag} '"\${wl}$exp_sym_flag:\$export_symbols" - else # Determine the default libpath from the value encoded in an # empty executable. _LT_SYS_MODULE_PATH_AIX @@ -4812,7 +4722,6 @@ _LT_EOF _LT_TAGVAR(archive_cmds_need_lc, $1)=3Dyes # This is similar to how AIX traditionally builds its shared libraries. _LT_TAGVAR(archive_expsym_cmds, $1)=3D"\$CC $shared_flag"' -o $output_o= bjdir/$soname $libobjs $deplibs ${wl}-bnoentry $compiler_flags ${wl}-bE:$ex= port_symbols${allow_undefined_flag}~$AR $AR_FLAGS $output_objdir/$libname$r= elease.a $output_objdir/$soname' - fi fi ;; =20 @@ -4934,9 +4843,6 @@ _LT_EOF hppa*64*) _LT_TAGVAR(archive_cmds, $1)=3D'$CC -shared ${wl}+h ${wl}$soname ${wl}+= nodefaultrpath -o $lib $libobjs $deplibs $compiler_flags' ;; - ia64*) - _LT_TAGVAR(archive_cmds, $1)=3D'$CC -shared -fPIC ${wl}+h ${wl}$soname = ${wl}+nodefaultrpath -o $lib $libobjs $deplibs $compiler_flags' - ;; *) _LT_TAGVAR(archive_cmds, $1)=3D'$CC -shared -fPIC ${wl}+h ${wl}$soname = ${wl}+b ${wl}$install_libdir -o $lib $libobjs $deplibs $compiler_flags' ;; @@ -4946,9 +4852,6 @@ _LT_EOF hppa*64*) _LT_TAGVAR(archive_cmds, $1)=3D'$CC -b ${wl}+h ${wl}$soname ${wl}+nodef= aultrpath -o $lib $libobjs $deplibs $compiler_flags' ;; - ia64*) - _LT_TAGVAR(archive_cmds, $1)=3D'$CC -b ${wl}+h ${wl}$soname ${wl}+nodef= aultrpath -o $lib $libobjs $deplibs $compiler_flags' - ;; *) m4_if($1, [], [ # Older versions of the 11.00 compiler do not understand -b yet @@ -4966,7 +4869,7 @@ _LT_EOF _LT_TAGVAR(hardcode_libdir_separator, $1)=3D: =20 case $host_cpu in - hppa*64*|ia64*) + hppa*64*) _LT_TAGVAR(hardcode_direct, $1)=3Dno _LT_TAGVAR(hardcode_shlibpath_var, $1)=3Dno ;; @@ -5458,7 +5361,7 @@ if test -n "$compiler"; then ;; =20 aix[[4-9]]*) - if test "$host_cpu" !=3D ia64 && test "$aix_use_runtimelinking" =3D no= ; then + if test "$aix_use_runtimelinking" =3D no ; then test "$enable_shared" =3D yes && enable_static=3Dno fi ;; @@ -5634,13 +5537,6 @@ if test "$_lt_caught_CXX_error" !=3D yes; then _LT_TAGVAR(ld_shlibs, $1)=3Dno ;; aix[[4-9]]*) - if test "$host_cpu" =3D ia64; then - # On IA64, the linker does run time linking by default, so we do= n't - # have to do anything special. - aix_use_runtimelinking=3Dno - exp_sym_flag=3D'-Bexport' - no_entry_flag=3D"" - else aix_use_runtimelinking=3Dno =20 # Test if we are trying to use run time linking or normal @@ -5660,7 +5556,6 @@ if test "$_lt_caught_CXX_error" !=3D yes; then =20 exp_sym_flag=3D'-bexport' no_entry_flag=3D'-bnoentry' - fi =20 # When large executables or shared objects are built, AIX ld can # have problems creating the table of contents. If linking a libr= ary @@ -5702,17 +5597,11 @@ if test "$_lt_caught_CXX_error" !=3D yes; then fi else # not using gcc - if test "$host_cpu" =3D ia64; then - # VisualAge C++, Version 5.5 for AIX 5L for IA-64, Beta 3 Release - # chokes on -Wl,-G. The following line is correct: - shared_flag=3D'-G' - else if test "$aix_use_runtimelinking" =3D yes; then shared_flag=3D'${wl}-G' else shared_flag=3D'${wl}-bM:SRE' fi - fi fi =20 _LT_TAGVAR(export_dynamic_flag_spec, $1)=3D'${wl}-bexpall' @@ -5731,11 +5620,6 @@ if test "$_lt_caught_CXX_error" !=3D yes; then =20 _LT_TAGVAR(archive_expsym_cmds, $1)=3D'$CC -o $output_objdir/$so= name $libobjs $deplibs '"\${wl}$no_entry_flag"' $compiler_flags `if test "x= ${allow_undefined_flag}" !=3D "x"; then func_echo_all "${wl}${allow_undefin= ed_flag}"; else :; fi` '"\${wl}$exp_sym_flag:\$export_symbols $shared_flag" else - if test "$host_cpu" =3D ia64; then - _LT_TAGVAR(hardcode_libdir_flag_spec, $1)=3D'${wl}-R $libdir:/usr/lib= :/lib' - _LT_TAGVAR(allow_undefined_flag, $1)=3D"-z nodefs" - _LT_TAGVAR(archive_expsym_cmds, $1)=3D"\$CC $shared_flag"' -o $output= _objdir/$soname $libobjs $deplibs '"\${wl}$no_entry_flag"' $compiler_flags = ${wl}${allow_undefined_flag} '"\${wl}$exp_sym_flag:\$export_symbols" - else # Determine the default libpath from the value encoded in an # empty executable. _LT_SYS_MODULE_PATH_AIX @@ -5755,7 +5639,6 @@ if test "$_lt_caught_CXX_error" !=3D yes; then # This is similar to how AIX traditionally builds its shared # libraries. _LT_TAGVAR(archive_expsym_cmds, $1)=3D"\$CC $shared_flag"' -o $output= _objdir/$soname $libobjs $deplibs ${wl}-bnoentry $compiler_flags ${wl}-bE:$= export_symbols${allow_undefined_flag}~$AR $AR_FLAGS $output_objdir/$libname= $release.a $output_objdir/$soname' - fi fi ;; =20 @@ -5892,7 +5775,7 @@ if test "$_lt_caught_CXX_error" !=3D yes; then _LT_TAGVAR(hardcode_libdir_separator, $1)=3D: =20 case $host_cpu in - hppa*64*|ia64*) + hppa*64*) ;; *) _LT_TAGVAR(export_dynamic_flag_spec, $1)=3D'${wl}-E' @@ -5900,7 +5783,7 @@ if test "$_lt_caught_CXX_error" !=3D yes; then esac fi case $host_cpu in - hppa*64*|ia64*) + hppa*64*) _LT_TAGVAR(hardcode_direct, $1)=3Dno _LT_TAGVAR(hardcode_shlibpath_var, $1)=3Dno ;; @@ -5923,9 +5806,6 @@ if test "$_lt_caught_CXX_error" !=3D yes; then hppa*64*) _LT_TAGVAR(archive_cmds, $1)=3D'$CC -b ${wl}+h ${wl}$soname ${wl}= +nodefaultrpath -o $lib $predep_objects $libobjs $deplibs $postdep_objects = $compiler_flags' ;; - ia64*) - _LT_TAGVAR(archive_cmds, $1)=3D'$CC -b ${wl}+h ${wl}$soname ${wl}= +nodefaultrpath -o $lib $predep_objects $libobjs $deplibs $postdep_objects = $compiler_flags' - ;; *) _LT_TAGVAR(archive_cmds, $1)=3D'$CC -b ${wl}+h ${wl}$soname ${wl}= +b ${wl}$install_libdir -o $lib $predep_objects $libobjs $deplibs $postdep_= objects $compiler_flags' ;; @@ -5947,9 +5827,6 @@ if test "$_lt_caught_CXX_error" !=3D yes; then hppa*64*) _LT_TAGVAR(archive_cmds, $1)=3D'$CC -shared -nostdlib -fPIC $= {wl}+h ${wl}$soname ${wl}+nodefaultrpath -o $lib $predep_objects $libobjs $= deplibs $postdep_objects $compiler_flags' ;; - ia64*) - _LT_TAGVAR(archive_cmds, $1)=3D'$CC -shared -nostdlib -fPIC $= {wl}+h ${wl}$soname ${wl}+nodefaultrpath -o $lib $predep_objects $libobjs $= deplibs $postdep_objects $compiler_flags' - ;; *) _LT_TAGVAR(archive_cmds, $1)=3D'$CC -shared -nostdlib -fPIC $= {wl}+h ${wl}$soname ${wl}+b ${wl}$install_libdir -o $lib $predep_objects $l= ibobjs $deplibs $postdep_objects $compiler_flags' ;; @@ -6045,9 +5922,6 @@ if test "$_lt_caught_CXX_error" !=3D yes; then ;; *) # Version 8.0 or newer tmp_idyn=3D - case $host_cpu in - ia64*) tmp_idyn=3D' -i_dynamic';; - esac _LT_TAGVAR(archive_cmds, $1)=3D'$CC -shared'"$tmp_idyn"' $libobjs= $deplibs $compiler_flags ${wl}-soname $wl$soname -o $lib' _LT_TAGVAR(archive_expsym_cmds, $1)=3D'$CC -shared'"$tmp_idyn"' $libobjs= $deplibs $compiler_flags ${wl}-soname $wl$soname ${wl}-retain-symbols-file= $wl$export_symbols -o $lib' ;; @@ -6818,7 +6692,7 @@ if test "$_lt_disable_F77" !=3D yes; then fi ;; aix[[4-9]]*) - if test "$host_cpu" !=3D ia64 && test "$aix_use_runtimelinking" =3D no ; = then + if test "$aix_use_runtimelinking" =3D no ; then test "$enable_shared" =3D yes && enable_static=3Dno fi ;; @@ -6950,7 +6824,7 @@ if test "$_lt_disable_FC" !=3D yes; then fi ;; aix[[4-9]]*) - if test "$host_cpu" !=3D ia64 && test "$aix_use_runtimelinking" =3D no ; = then + if test "$aix_use_runtimelinking" =3D no ; then test "$enable_shared" =3D yes && enable_static=3Dno fi ;; diff --git a/opcodes/Makefile.am b/opcodes/Makefile.am index a173c8e6f36..188b6682d16 100644 --- a/opcodes/Makefile.am +++ b/opcodes/Makefile.am @@ -64,8 +64,6 @@ HFILES =3D \ fr30-desc.h fr30-opc.h \ frv-desc.h frv-opc.h \ i386-opc.h \ - ia64-asmtab.h \ - ia64-opc.h \ ip2k-desc.h ip2k-opc.h \ iq2000-desc.h iq2000-opc.h \ lm32-desc.h \ @@ -95,8 +93,6 @@ TARGET64_LIBOPCODES_CFILES =3D \ alpha-opc.c \ bpf-dis.c \ bpf-opc.c \ - ia64-dis.c \ - ia64-opc.c \ loongarch-opc.c \ loongarch-dis.c \ loongarch-coder.c \ @@ -490,13 +486,13 @@ stamp-xstormy16: $(CGENDEPS) $(CPUDIR)/xstormy16.cpu = $(CPUDIR)/xstormy16.opc archfile=3D$(CPUDIR)/xstormy16.cpu opcfile=3D$(CPUDIR)/xstormy16.opc ext= rafiles=3D =20 MOSTLYCLEANFILES =3D aarch64-gen$(EXEEXT_FOR_BUILD) i386-gen$(EXEEXT_FOR_B= UILD) \ - ia64-gen$(EXEEXT_FOR_BUILD) s390-mkopc$(EXEEXT_FOR_BUILD) s390-opc.tab \ + s390-mkopc$(EXEEXT_FOR_BUILD) s390-opc.tab \ z8kgen$(EXEEXT_FOR_BUILD) opc2c$(EXEEXT_FOR_BUILD) =20 MAINTAINERCLEANFILES =3D $(srcdir)/aarch64-asm-2.c $(srcdir)/aarch64-dis-2= .c \ $(srcdir)/aarch64-opc-2.c \ $(srcdir)/i386-tbl.h $(srcdir)/i386-init.h $(srcdir)/i386-mnem.h \ - $(srcdir)/ia64-asmtab.c $(srcdir)/z8k-opc.h \ + $(srcdir)/z8k-opc.h \ $(srcdir)/msp430-decode.c \ $(srcdir)/rl78-decode.c \ $(srcdir)/rx-decode.c @@ -536,25 +532,6 @@ $(srcdir)/i386%tbl.h $(srcdir)/i386%init.h $(srcdir)/i= 386%mnem.h: \ # to make sure they are re-generated as necessary. i386-dis.lo: $(srcdir)/i386-tbl.h $(srcdir)/i386-init.h $(srcdir)/i386-mne= m.h =20 -ia64-gen$(EXEEXT_FOR_BUILD): ia64-gen.o $(BUILD_LIB_DEPS) - $(AM_V_CCLD)$(LINK_FOR_BUILD) ia64-gen.o $(BUILD_LIBS) - -ia64-gen.o: ia64-gen.c $(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/getopt.h \ - $(INCDIR)/libiberty.h $(INCDIR)/opcode/ia64.h $(INCDIR)/safe-ctype.h \ - $(INCDIR)/symcat.h config.h ia64-opc-a.c ia64-opc-b.c \ - ia64-opc-d.c ia64-opc-f.c ia64-opc-i.c ia64-opc-m.c \ - ia64-opc-x.c ia64-opc.h sysdep.h - $(AM_V_CC)$(COMPILE_FOR_BUILD) -c $(srcdir)/ia64-gen.c - -# Use a helper variable for the dependencies to avoid 'make' issues -# with continuations in comments, as @MAINT@ can be expanded to '#'. -ia64_asmtab_deps =3D ia64-gen$(EXEEXT_FOR_BUILD) ia64-ic.tbl \ - ia64-raw.tbl ia64-waw.tbl ia64-war.tbl -$(srcdir)/ia64-asmtab.c: @MAINT@ $(ia64_asmtab_deps) - $(AM_V_GEN)./ia64-gen$(EXEEXT_FOR_BUILD) --srcdir $(srcdir) > $@ - -ia64-opc.lo: $(srcdir)/ia64-asmtab.c - $(srcdir)/msp430-decode.c: @MAINT@ $(srcdir)/msp430-decode.opc opc2c$(EXEE= XT_FOR_BUILD) $(AM_V_GEN)./opc2c$(EXEEXT_FOR_BUILD) $(srcdir)/msp430-decode.opc > $(src= dir)/msp430-decode.c =20 diff --git a/opcodes/Makefile.in b/opcodes/Makefile.in index 57aaed26da8..9327b0f461e 100644 --- a/opcodes/Makefile.in +++ b/opcodes/Makefile.in @@ -466,8 +466,6 @@ HFILES =3D \ fr30-desc.h fr30-opc.h \ frv-desc.h frv-opc.h \ i386-opc.h \ - ia64-asmtab.h \ - ia64-opc.h \ ip2k-desc.h ip2k-opc.h \ iq2000-desc.h iq2000-opc.h \ lm32-desc.h \ @@ -498,8 +496,6 @@ TARGET64_LIBOPCODES_CFILES =3D \ alpha-opc.c \ bpf-dis.c \ bpf-opc.c \ - ia64-dis.c \ - ia64-opc.c \ loongarch-opc.c \ loongarch-dis.c \ loongarch-coder.c \ @@ -744,23 +740,17 @@ CGEN_CPUS =3D cris epiphany fr30 frv ip2k iq2000 lm32= m32c m32r mep mt or1k xstorm @CGEN_MAINT_FALSE@XSTORMY16_DEPS =3D=20 @CGEN_MAINT_TRUE@XSTORMY16_DEPS =3D stamp-xstormy16 MOSTLYCLEANFILES =3D aarch64-gen$(EXEEXT_FOR_BUILD) i386-gen$(EXEEXT_FOR_B= UILD) \ - ia64-gen$(EXEEXT_FOR_BUILD) s390-mkopc$(EXEEXT_FOR_BUILD) s390-opc.tab \ + s390-mkopc$(EXEEXT_FOR_BUILD) s390-opc.tab \ z8kgen$(EXEEXT_FOR_BUILD) opc2c$(EXEEXT_FOR_BUILD) =20 MAINTAINERCLEANFILES =3D $(srcdir)/aarch64-asm-2.c $(srcdir)/aarch64-dis-2= .c \ $(srcdir)/aarch64-opc-2.c \ $(srcdir)/i386-tbl.h $(srcdir)/i386-init.h $(srcdir)/i386-mnem.h \ - $(srcdir)/ia64-asmtab.c $(srcdir)/z8k-opc.h \ + $(srcdir)/z8k-opc.h \ $(srcdir)/msp430-decode.c \ $(srcdir)/rl78-decode.c \ $(srcdir)/rx-decode.c =20 - -# Use a helper variable for the dependencies to avoid 'make' issues -# with continuations in comments, as @MAINT@ can be expanded to '#'. -ia64_asmtab_deps =3D ia64-gen$(EXEEXT_FOR_BUILD) ia64-ic.tbl \ - ia64-raw.tbl ia64-waw.tbl ia64-war.tbl - MIPS_DEFS =3D `case \`cat ../bfd/ofiles\` in *elfxx-mips*) echo "-DHAVE_BF= D_MIPS_ELF_GET_ABIFLAGS=3D1";; esac` all: config.h $(MAKE) $(AM_MAKEFLAGS) all-recursive @@ -932,8 +922,6 @@ distclean-compile: @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/h8300-dis.Plo@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/hppa-dis.Plo@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/i386-dis.Plo@am__quote@ -@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/ia64-dis.Plo@am__quote@ -@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/ia64-opc.Plo@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/ip2k-asm.Plo@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/ip2k-desc.Plo@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/ip2k-dis.Plo@am__quote@ @@ -1519,20 +1507,6 @@ $(srcdir)/i386%tbl.h $(srcdir)/i386%init.h $(srcdir)= /i386%mnem.h: \ # to make sure they are re-generated as necessary. i386-dis.lo: $(srcdir)/i386-tbl.h $(srcdir)/i386-init.h $(srcdir)/i386-mne= m.h =20 -ia64-gen$(EXEEXT_FOR_BUILD): ia64-gen.o $(BUILD_LIB_DEPS) - $(AM_V_CCLD)$(LINK_FOR_BUILD) ia64-gen.o $(BUILD_LIBS) - -ia64-gen.o: ia64-gen.c $(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/getopt.h \ - $(INCDIR)/libiberty.h $(INCDIR)/opcode/ia64.h $(INCDIR)/safe-ctype.h \ - $(INCDIR)/symcat.h config.h ia64-opc-a.c ia64-opc-b.c \ - ia64-opc-d.c ia64-opc-f.c ia64-opc-i.c ia64-opc-m.c \ - ia64-opc-x.c ia64-opc.h sysdep.h - $(AM_V_CC)$(COMPILE_FOR_BUILD) -c $(srcdir)/ia64-gen.c -$(srcdir)/ia64-asmtab.c: @MAINT@ $(ia64_asmtab_deps) - $(AM_V_GEN)./ia64-gen$(EXEEXT_FOR_BUILD) --srcdir $(srcdir) > $@ - -ia64-opc.lo: $(srcdir)/ia64-asmtab.c - $(srcdir)/msp430-decode.c: @MAINT@ $(srcdir)/msp430-decode.opc opc2c$(EXEE= XT_FOR_BUILD) $(AM_V_GEN)./opc2c$(EXEEXT_FOR_BUILD) $(srcdir)/msp430-decode.opc > $(src= dir)/msp430-decode.c =20 diff --git a/opcodes/configure b/opcodes/configure index 9b3cc5ce4a1..4967c13b3d4 100755 --- a/opcodes/configure +++ b/opcodes/configure @@ -6007,10 +6007,6 @@ haiku*) hpux10.20* | hpux11*) lt_cv_file_magic_cmd=3D/usr/bin/file case $host_cpu in - ia64*) - lt_cv_deplibs_check_method=3D'file_magic (s[0-9][0-9][0-9]|ELF-[0-9][0= -9]) shared object file - IA64' - lt_cv_file_magic_test_file=3D/usr/lib/hpux32/libc.so - ;; hppa*64*) lt_cv_deplibs_check_method=3D'file_magic (s[0-9][0-9][0-9]|ELF[ -][0-9= ][0-9])(-bit)?( [LM]SB)? shared object( file)?[, -]* PA-RISC [0-9]\.[0-9]' lt_cv_file_magic_test_file=3D/usr/lib/pa20_64/libc.sl @@ -6569,11 +6565,6 @@ aix*) cygwin* | mingw* | pw32* | cegcc*) symcode=3D'[ABCDGISTW]' ;; -hpux*) - if test "$host_cpu" =3D ia64; then - symcode=3D'[ABCDEGRST]' - fi - ;; irix* | nonstopux*) symcode=3D'[BCDEGRST]' ;; @@ -6604,7 +6595,7 @@ case `$NM -V 2>&1` in esac =20 # Transform an extracted symbol line into a proper C declaration. -# Some systems (esp. on ia64) link data and code symbols differently, +# Some systems link data and code symbols differently, # so use this general approach. lt_cv_sys_global_symbol_to_cdecl=3D"sed -n -e 's/^T .* \(.*\)$/extern int = \1();/p' -e 's/^$symcode* .* \(.*\)$/extern char \1;/p'" =20 @@ -6804,25 +6795,6 @@ test "x$enable_libtool_lock" !=3D xno && enable_libt= ool_lock=3Dyes # Some flags need to be propagated to the compiler or linker for good # libtool support. case $host in -ia64-*-hpux*) - # Find out which ABI we are using. - echo 'int i;' > conftest.$ac_ext - if { { eval echo "\"\$as_me\":${as_lineno-$LINENO}: \"$ac_compile\""; } = >&5 - (eval $ac_compile) 2>&5 - ac_status=3D$? - $as_echo "$as_me:${as_lineno-$LINENO}: \$? =3D $ac_status" >&5 - test $ac_status =3D 0; }; then - case `/usr/bin/file conftest.$ac_objext` in - *ELF-32*) - HPUX_IA64_MODE=3D"32" - ;; - *ELF-64*) - HPUX_IA64_MODE=3D"64" - ;; - esac - fi - rm -rf conftest* - ;; *-*-irix6*) # Find out which ABI we are using. echo '#line '$LINENO' "configure"' > conftest.$ac_ext @@ -8127,10 +8099,6 @@ $as_echo_n "checking for $compiler option to produce= PIC... " >&6; } case $host_os in aix*) # All AIX code is PIC. - if test "$host_cpu" =3D ia64; then - # AIX 5 now supports IA64 processor - lt_prog_compiler_static=3D'-Bstatic' - fi lt_prog_compiler_pic=3D'-fPIC' ;; =20 @@ -8227,12 +8195,7 @@ $as_echo_n "checking for $compiler option to produce= PIC... " >&6; } case $host_os in aix*) lt_prog_compiler_wl=3D'-Wl,' - if test "$host_cpu" =3D ia64; then - # AIX 5 now supports IA64 processor - lt_prog_compiler_static=3D'-Bstatic' - else - lt_prog_compiler_static=3D'-bnso -bI:/lib/syscalls.exp' - fi + lt_prog_compiler_static=3D'-bnso -bI:/lib/syscalls.exp' ;; =20 mingw* | cygwin* | pw32* | os2* | cegcc*) @@ -8246,7 +8209,7 @@ $as_echo_n "checking for $compiler option to produce = PIC... " >&6; } # PIC is the default for IA64 HP-UX and 64-bit HP-UX, but # not for PA HP-UX. case $host_cpu in - hppa*64*|ia64*) + hppa*64*) # +Z the default ;; *) @@ -8771,7 +8734,6 @@ $as_echo_n "checking whether the $compiler linker ($L= D) supports shared librarie case $host_os in aix[3-9]*) # On AIX/PPC, the GNU linker is very broken - if test "$host_cpu" !=3D ia64; then ld_shlibs=3Dno cat <<_LT_EOF 1>&2 =20 @@ -8783,7 +8745,6 @@ $as_echo_n "checking whether the $compiler linker ($L= D) supports shared librarie *** You will then need to restart the configuration process. =20 _LT_EOF - fi ;; =20 amigaos*) @@ -8879,10 +8840,6 @@ _LT_EOF # Portland Group f77 and f90 compilers whole_archive_flag_spec=3D'${wl}--whole-archive`for conv in $convenienc= e\"\"; do test -n \"$conv\" && new_convenience=3D\"$new_convenience,$conv\= "; done; func_echo_all \"$new_convenience\"` ${wl}--no-whole-archive' tmp_addflag=3D' $pic_flag -Mnomain' ;; - ecc*,ia64* | icc*,ia64*) # Intel C compiler on ia64 - tmp_addflag=3D' -i_dynamic' ;; - efc*,ia64* | ifort*,ia64*) # Intel Fortran compiler on ia64 - tmp_addflag=3D' -i_dynamic -nofor_main' ;; ifc* | ifort*) # Intel Fortran compiler tmp_addflag=3D' -nofor_main' ;; lf95*) # Lahey Fortran 8.1 @@ -9036,13 +8993,6 @@ _LT_EOF ;; =20 aix[4-9]*) - if test "$host_cpu" =3D ia64; then - # On IA64, the linker does run time linking by default, so we don't - # have to do anything special. - aix_use_runtimelinking=3Dno - exp_sym_flag=3D'-Bexport' - no_entry_flag=3D"" - else # If we're using GNU nm, then we don't want the "-C" option. # -C means demangle to AIX nm, but means don't demangle with GNU nm # Also, AIX nm treats weak defined symbols like other global @@ -9069,7 +9019,6 @@ _LT_EOF =20 exp_sym_flag=3D'-bexport' no_entry_flag=3D'-bnoentry' - fi =20 # When large executables or shared objects are built, AIX ld can # have problems creating the table of contents. If linking a library @@ -9112,17 +9061,11 @@ _LT_EOF fi else # not using gcc - if test "$host_cpu" =3D ia64; then - # VisualAge C++, Version 5.5 for AIX 5L for IA-64, Beta 3 Release - # chokes on -Wl,-G. The following line is correct: - shared_flag=3D'-G' - else if test "$aix_use_runtimelinking" =3D yes; then shared_flag=3D'${wl}-G' else shared_flag=3D'${wl}-bM:SRE' fi - fi fi =20 export_dynamic_flag_spec=3D'${wl}-bexpall' @@ -9168,11 +9111,6 @@ if test -z "$aix_libpath"; then aix_libpath=3D"/usr/= lib:/lib"; fi hardcode_libdir_flag_spec=3D'${wl}-blibpath:$libdir:'"$aix_libpath" archive_expsym_cmds=3D'$CC -o $output_objdir/$soname $libobjs $dep= libs '"\${wl}$no_entry_flag"' $compiler_flags `if test "x${allow_undefined_= flag}" !=3D "x"; then func_echo_all "${wl}${allow_undefined_flag}"; else :;= fi` '"\${wl}$exp_sym_flag:\$export_symbols $shared_flag" else - if test "$host_cpu" =3D ia64; then - hardcode_libdir_flag_spec=3D'${wl}-R $libdir:/usr/lib:/lib' - allow_undefined_flag=3D"-z nodefs" - archive_expsym_cmds=3D"\$CC $shared_flag"' -o $output_objdir/$soname $l= ibobjs $deplibs '"\${wl}$no_entry_flag"' $compiler_flags ${wl}${allow_undef= ined_flag} '"\${wl}$exp_sym_flag:\$export_symbols" - else # Determine the default libpath from the value encoded in an # empty executable. cat confdefs.h - <<_ACEOF >conftest.$ac_ext @@ -9221,7 +9159,6 @@ if test -z "$aix_libpath"; then aix_libpath=3D"/usr/l= ib:/lib"; fi # This is similar to how AIX traditionally builds its shared libraries. archive_expsym_cmds=3D"\$CC $shared_flag"' -o $output_objdir/$soname $l= ibobjs $deplibs ${wl}-bnoentry $compiler_flags ${wl}-bE:$export_symbols${al= low_undefined_flag}~$AR $AR_FLAGS $output_objdir/$libname$release.a $output= _objdir/$soname' fi - fi ;; =20 amigaos*) @@ -9369,9 +9306,6 @@ if test -z "$aix_libpath"; then aix_libpath=3D"/usr/l= ib:/lib"; fi hppa*64*) archive_cmds=3D'$CC -shared ${wl}+h ${wl}$soname ${wl}+nodefaultrpath -= o $lib $libobjs $deplibs $compiler_flags' ;; - ia64*) - archive_cmds=3D'$CC -shared -fPIC ${wl}+h ${wl}$soname ${wl}+nodefaultr= path -o $lib $libobjs $deplibs $compiler_flags' - ;; *) archive_cmds=3D'$CC -shared -fPIC ${wl}+h ${wl}$soname ${wl}+b ${wl}$in= stall_libdir -o $lib $libobjs $deplibs $compiler_flags' ;; @@ -9381,9 +9315,6 @@ if test -z "$aix_libpath"; then aix_libpath=3D"/usr/l= ib:/lib"; fi hppa*64*) archive_cmds=3D'$CC -b ${wl}+h ${wl}$soname ${wl}+nodefaultrpath -o $li= b $libobjs $deplibs $compiler_flags' ;; - ia64*) - archive_cmds=3D'$CC -b ${wl}+h ${wl}$soname ${wl}+nodefaultrpath -o $li= b $libobjs $deplibs $compiler_flags' - ;; *) =20 # Older versions of the 11.00 compiler do not understand -b yet @@ -9433,7 +9364,7 @@ fi hardcode_libdir_separator=3D: =20 case $host_cpu in - hppa*64*|ia64*) + hppa*64*) hardcode_direct=3Dno hardcode_shlibpath_var=3Dno ;; @@ -10070,11 +10001,6 @@ aix[4-9]*) need_lib_prefix=3Dno need_version=3Dno hardcode_into_libs=3Dyes - if test "$host_cpu" =3D ia64; then - # AIX 5 supports IA64 - library_names_spec=3D'${libname}${release}${shared_ext}$major ${libnam= e}${release}${shared_ext}$versuffix $libname${shared_ext}' - shlibpath_var=3DLD_LIBRARY_PATH - else # With GCC up to 2.95.x, collect2 would create an import file # for dependence libraries. The import file would start with # the line `#! .'. This would cause the generated library to @@ -10106,7 +10032,6 @@ aix[4-9]*) soname_spec=3D'${libname}${release}${shared_ext}$major' fi shlibpath_var=3DLIBPATH - fi ;; =20 amigaos*) @@ -10283,21 +10208,6 @@ hpux9* | hpux10* | hpux11*) need_lib_prefix=3Dno need_version=3Dno case $host_cpu in - ia64*) - shrext_cmds=3D'.so' - hardcode_into_libs=3Dyes - dynamic_linker=3D"$host_os dld.so" - shlibpath_var=3DLD_LIBRARY_PATH - shlibpath_overrides_runpath=3Dyes # Unless +noenvvar is specified. - library_names_spec=3D'${libname}${release}${shared_ext}$versuffix ${li= bname}${release}${shared_ext}$major $libname${shared_ext}' - soname_spec=3D'${libname}${release}${shared_ext}$major' - if test "X$HPUX_IA64_MODE" =3D X32; then - sys_lib_search_path_spec=3D"/usr/lib/hpux32 /usr/local/lib/hpux32 /u= sr/local/lib" - else - sys_lib_search_path_spec=3D"/usr/lib/hpux64 /usr/local/lib/hpux64" - fi - sys_lib_dlsearch_path_spec=3D$sys_lib_search_path_spec - ;; hppa*64*) shrext_cmds=3D'.sl' hardcode_into_libs=3Dyes @@ -11388,7 +11298,7 @@ $as_echo_n "checking whether to build shared librar= ies... " >&6; } ;; =20 aix[4-9]*) - if test "$host_cpu" !=3D ia64 && test "$aix_use_runtimelinking" =3D no= ; then + if test "$aix_use_runtimelinking" =3D no ; then test "$enable_shared" =3D yes && enable_static=3Dno fi ;; @@ -14471,7 +14381,6 @@ if test x${all_targets} =3D xfalse ; then bfd_hppa_arch) ta=3D"$ta hppa-dis.lo" ;; bfd_i386_arch|bfd_iamcu_arch) ta=3D"$ta i386-dis.lo" ;; - bfd_ia64_arch) ta=3D"$ta ia64-dis.lo ia64-opc.lo" ;; bfd_ip2k_arch) ta=3D"$ta ip2k-asm.lo ip2k-desc.lo ip2k-dis.lo ip2k-ibld.= lo ip2k-opc.lo" using_cgen=3Dyes ;; bfd_epiphany_arch) ta=3D"$ta epiphany-asm.lo epiphany-desc.lo epiphany-di= s.lo epiphany-ibld.lo epiphany-opc.lo" using_cgen=3Dyes ;; bfd_iq2000_arch) ta=3D"$ta iq2000-asm.lo iq2000-desc.lo iq2000-dis.lo iq2= 000-ibld.lo iq2000-opc.lo" using_cgen=3Dyes ;; diff --git a/opcodes/configure.ac b/opcodes/configure.ac index d812ff54a95..afc46e9202d 100644 --- a/opcodes/configure.ac +++ b/opcodes/configure.ac @@ -286,7 +286,6 @@ if test x${all_targets} =3D xfalse ; then bfd_hppa_arch) ta=3D"$ta hppa-dis.lo" ;; bfd_i386_arch|bfd_iamcu_arch) ta=3D"$ta i386-dis.lo" ;; - bfd_ia64_arch) ta=3D"$ta ia64-dis.lo ia64-opc.lo" ;; bfd_ip2k_arch) ta=3D"$ta ip2k-asm.lo ip2k-desc.lo ip2k-dis.lo ip2k-ibld.= lo ip2k-opc.lo" using_cgen=3Dyes ;; bfd_epiphany_arch) ta=3D"$ta epiphany-asm.lo epiphany-desc.lo epiphany-di= s.lo epiphany-ibld.lo epiphany-opc.lo" using_cgen=3Dyes ;; bfd_iq2000_arch) ta=3D"$ta iq2000-asm.lo iq2000-desc.lo iq2000-dis.lo iq2= 000-ibld.lo iq2000-opc.lo" using_cgen=3Dyes ;; diff --git a/opcodes/configure.com b/opcodes/configure.com index 468fe916235..bf6af049b40 100644 --- a/opcodes/configure.com +++ b/opcodes/configure.com @@ -28,14 +28,6 @@ $ arch=3DF$EDIT(arch,"LOWERCASE") $! $ write sys$output "Generate opcodes/build.com" $! -$ if arch.eqs."ia64" -$ then -$ create build.com -$DECK -$ FILES=3D"ia64-dis,ia64-opc" -$ DEFS=3D"""ARCH_ia64""" -$EOD -$ endif $ if arch.eqs."alpha" $ then $ create build.com diff --git a/opcodes/disassemble.c b/opcodes/disassemble.c index 347f28e06a6..67c08ff9e8d 100644 --- a/opcodes/disassemble.c +++ b/opcodes/disassemble.c @@ -28,7 +28,6 @@ #define ARCH_aarch64 #define ARCH_alpha #define ARCH_bpf -#define ARCH_ia64 #define ARCH_loongarch #define ARCH_mips #define ARCH_mmix @@ -215,11 +214,6 @@ disassembler (enum bfd_architecture a, disassemble =3D print_insn_i386; break; #endif -#ifdef ARCH_ia64 - case bfd_arch_ia64: - disassemble =3D print_insn_ia64; - break; -#endif #ifdef ARCH_ip2k case bfd_arch_ip2k: disassemble =3D print_insn_ip2k; @@ -636,11 +630,6 @@ disassemble_init_for_target (struct disassemble_info *= info) info->created_styled_output =3D true; break; #endif -#ifdef ARCH_ia64 - case bfd_arch_ia64: - info->skip_zeroes =3D 16; - break; -#endif #ifdef ARCH_loongarch case bfd_arch_loongarch: info->created_styled_output =3D true; diff --git a/opcodes/disassemble.h b/opcodes/disassemble.h index b02e45268a2..8202959951a 100644 --- a/opcodes/disassemble.h +++ b/opcodes/disassemble.h @@ -48,7 +48,6 @@ extern int print_insn_hppa (bfd_vma, disassemble_info *); extern int print_insn_i386 (bfd_vma, disassemble_info *); extern int print_insn_i386_att (bfd_vma, disassemble_info *); extern int print_insn_i386_intel (bfd_vma, disassemble_info *); -extern int print_insn_ia64 (bfd_vma, disassemble_info *); extern int print_insn_ip2k (bfd_vma, disassemble_info *); extern int print_insn_iq2000 (bfd_vma, disassemble_info *); extern int print_insn_little_nios2 (bfd_vma, disassemble_info *); diff --git a/opcodes/ia64-asmtab.c b/opcodes/ia64-asmtab.c deleted file mode 100644 index 0cefb896d58..00000000000 --- a/opcodes/ia64-asmtab.c +++ /dev/null @@ -1,10669 +0,0 @@ -/* This file is automatically generated by ia64-gen. Do not edit! */ -/* Copyright (C) 2007-2024 Free Software Foundation, Inc. - - This file is part of the GNU opcodes library. - - This library is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3, or (at your option) - any later version. - - It is distributed in the hope that it will be useful, but WITHOUT - ANY WARRANTY; without even the implied warranty of MERCHANTABILITY - or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public - License for more details. - - You should have received a copy of the GNU General Public License - along with this program; see the file COPYING. If not, write to the - Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA - 02110-1301, USA. */ -static const char * const ia64_strings[] =3D { - "", "0", "1", "a", "acq", "add", "addl", "addp4", "adds", "alloc", "and", - "andcm", "b", "bias", "br", "break", "brl", "brp", "bsw", "c", "call", - "cexit", "chk", "cloop", "clr", "clrrrb", "clz", "cmp", "cmp4", - "cmp8xchg16", "cmpxchg1", "cmpxchg2", "cmpxchg4", "cmpxchg8", "cond", - "count", "cover", "ctop", "czx1", "czx2", "d", "d0", "d1", "d2", "d3", - "d4", "d5", "d6", "d7", "dep", "dpnt", "dptk", "e", "epc", "eq", "excl", - "exit", "exp", "extr", "f", "fabs", "fadd", "famax", "famin", "fand", - "fandcm", "fault", "fc", "fchkf", "fclass", "fclrf", "fcmp", "fcvt", - "fetchadd4", "fetchadd8", "few", "fill", "flushrs", "fma", "fmax", - "fmerge", "fmin", "fmix", "fmpy", "fms", "fneg", "fnegabs", "fnma", - "fnmpy", "fnorm", "for", "fpabs", "fpack", "fpamax", "fpamin", "fpcmp", - "fpcvt", "fpma", "fpmax", "fpmerge", "fpmin", "fpmpy", "fpms", "fpneg", - "fpnegabs", "fpnma", "fpnmpy", "fprcpa", "fprsqrta", "frcpa", "frsqrta", - "fselect", "fsetc", "fsub", "fswap", "fsxt", "fwb", "fx", "fxor", "fxu", - "g", "ga", "ge", "getf", "geu", "gt", "gtu", "h", "hint", "hu", "i", "ia= ", - "imp", "invala", "itc", "itr", "l", "ld1", "ld16", "ld2", "ld4", "ld8", - "ldf", "ldf8", "ldfd", "ldfe", "ldfp8", "ldfpd", "ldfps", "ldfs", "le", - "leu", "lfetch", "loadrs", "loop", "lr", "lt", "ltu", "lu", "m", "many", - "mf", "mix1", "mix2", "mix4", "mov", "movl", "mpy4", "mpyshl4", "mux1", - "mux2", "nc", "ne", "neq", "nge", "ngt", "nl", "nle", "nlt", "nm", "nop", - "nr", "ns", "nt1", "nt2", "nta", "nz", "or", "orcm", "ord", "pack2", - "pack4", "padd1", "padd2", "padd4", "pavg1", "pavg2", "pavgsub1", - "pavgsub2", "pcmp1", "pcmp2", "pcmp4", "pmax1", "pmax2", "pmin1", "pmin2= ", - "pmpy2", "pmpyshr2", "popcnt", "pr", "probe", "psad1", "pshl2", "pshl4", - "pshladd2", "pshr2", "pshr4", "pshradd2", "psub1", "psub2", "psub4", - "ptc", "ptr", "r", "raz", "rel", "ret", "rfi", "rsm", "rum", "rw", "s", - "s0", "s1", "s2", "s3", "sa", "se", "setf", "shl", "shladd", "shladdp4", - "shr", "shrp", "sig", "spill", "spnt", "sptk", "srlz", "ssm", "sss", - "st1", "st16", "st2", "st4", "st8", "stf", "stf8", "stfd", "stfe", "stfs= ", - "sub", "sum", "sxt1", "sxt2", "sxt4", "sync", "tak", "tbit", "tf", - "thash", "tnat", "tpa", "trunc", "ttag", "u", "unc", "unord", "unpack1", - "unpack2", "unpack4", "uss", "uus", "uuu", "vmsw", "w", "wexit", "wtop", - "x", "xchg1", "xchg2", "xchg4", "xchg8", "xf", "xma", "xmpy", "xor", - "xuf", "z", "zxt1", "zxt2", "zxt4", -}; - -static const struct ia64_dependency -dependencies[] =3D { - { "ALAT", 0, 0, 0, -1, NULL, }, - { "AR[BSP]", 28, 0, 2, 17, NULL, }, - { "AR[BSPSTORE]", 28, 0, 2, 18, NULL, }, - { "AR[CCV]", 28, 0, 2, 32, NULL, }, - { "AR[CFLG]", 28, 0, 2, 27, NULL, }, - { "AR[CSD]", 28, 0, 2, 25, NULL, }, - { "AR[EC]", 28, 0, 2, 66, NULL, }, - { "AR[EFLAG]", 28, 0, 2, 24, NULL, }, - { "AR[FCR]", 28, 0, 2, 21, NULL, }, - { "AR[FDR]", 28, 0, 2, 30, NULL, }, - { "AR[FIR]", 28, 0, 2, 29, NULL, }, - { "AR[FPSR].sf0.controls", 32, 0, 2, -1, NULL, }, - { "AR[FPSR].sf1.controls", 32, 0, 2, -1, NULL, }, - { "AR[FPSR].sf2.controls", 32, 0, 2, -1, NULL, }, - { "AR[FPSR].sf3.controls", 32, 0, 2, -1, NULL, }, - { "AR[FPSR].sf0.flags", 32, 0, 2, -1, NULL, }, - { "AR[FPSR].sf1.flags", 32, 0, 2, -1, NULL, }, - { "AR[FPSR].sf2.flags", 32, 0, 2, -1, NULL, }, - { "AR[FPSR].sf3.flags", 32, 0, 2, -1, NULL, }, - { "AR[FPSR].traps", 32, 0, 2, -1, NULL, }, - { "AR[FPSR].rv", 32, 0, 2, -1, NULL, }, - { "AR[FSR]", 28, 0, 2, 28, NULL, }, - { "AR[ITC]", 28, 0, 2, 44, NULL, }, - { "AR[K%], % in 0 - 7", 1, 0, 2, -1, NULL, }, - { "AR[LC]", 28, 0, 2, 65, NULL, }, - { "AR[PFS]", 28, 0, 2, 64, NULL, }, - { "AR[PFS]", 28, 0, 2, 64, NULL, }, - { "AR[PFS]", 28, 0, 0, 64, NULL, }, - { "AR[RNAT]", 28, 0, 2, 19, NULL, }, - { "AR[RSC]", 28, 0, 2, 16, NULL, }, - { "AR[RUC]", 28, 0, 2, 45, NULL, }, - { "AR[SSD]", 28, 0, 2, 26, NULL, }, - { "AR[UNAT]{%}, % in 0 - 63", 2, 0, 2, -1, NULL, }, - { "AR%, % in 8-15, 20, 22-23, 31, 33-35, 37-39, 41-43, 46-47, 67-111", 3= , 0, 0, -1, NULL, }, - { "AR%, % in 48-63, 112-127", 4, 0, 2, -1, NULL, }, - { "BR%, % in 0 - 7", 5, 0, 2, -1, NULL, }, - { "BR%, % in 0 - 7", 5, 0, 0, -1, NULL, }, - { "BR%, % in 0 - 7", 5, 0, 2, -1, NULL, }, - { "CFM", 6, 0, 2, -1, NULL, }, - { "CFM", 6, 0, 2, -1, NULL, }, - { "CFM", 6, 0, 2, -1, NULL, }, - { "CFM", 6, 0, 2, -1, NULL, }, - { "CFM", 6, 0, 0, -1, NULL, }, - { "CPUID#", 7, 0, 5, -1, NULL, }, - { "CR[CMCV]", 29, 0, 3, 74, NULL, }, - { "CR[DCR]", 29, 0, 3, 0, NULL, }, - { "CR[EOI]", 29, 0, 7, 67, "SC Section 5.8.3.4, \"End of External Interr= upt Register (EOI - CR67)\" on page 2:119", }, - { "CR[GPTA]", 29, 0, 3, 9, NULL, }, - { "CR[IFA]", 29, 0, 1, 20, NULL, }, - { "CR[IFA]", 29, 0, 3, 20, NULL, }, - { "CR[IFS]", 29, 0, 3, 23, NULL, }, - { "CR[IFS]", 29, 0, 1, 23, NULL, }, - { "CR[IFS]", 29, 0, 1, 23, NULL, }, - { "CR[IHA]", 29, 0, 3, 25, NULL, }, - { "CR[IIB%], % in 0 - 1", 8, 0, 3, -1, NULL, }, - { "CR[IIM]", 29, 0, 3, 24, NULL, }, - { "CR[IIP]", 29, 0, 3, 19, NULL, }, - { "CR[IIP]", 29, 0, 1, 19, NULL, }, - { "CR[IIPA]", 29, 0, 3, 22, NULL, }, - { "CR[IPSR]", 29, 0, 3, 16, NULL, }, - { "CR[IPSR]", 29, 0, 1, 16, NULL, }, - { "CR[IRR%], % in 0 - 3", 9, 0, 3, -1, NULL, }, - { "CR[ISR]", 29, 0, 3, 17, NULL, }, - { "CR[ITIR]", 29, 0, 3, 21, NULL, }, - { "CR[ITIR]", 29, 0, 1, 21, NULL, }, - { "CR[ITM]", 29, 0, 3, 1, NULL, }, - { "CR[ITV]", 29, 0, 3, 72, NULL, }, - { "CR[IVA]", 29, 0, 4, 2, NULL, }, - { "CR[IVR]", 29, 0, 7, 65, "SC Section 5.8.3.2, \"External Interrupt Vec= tor Register (IVR - CR65)\" on page 2:118", }, - { "CR[LID]", 29, 0, 7, 64, "SC Section 5.8.3.1, \"Local ID (LID - CR64)\= " on page 2:117", }, - { "CR[LRR%], % in 0 - 1", 10, 0, 3, -1, NULL, }, - { "CR[PMV]", 29, 0, 3, 73, NULL, }, - { "CR[PTA]", 29, 0, 3, 8, NULL, }, - { "CR[TPR]", 29, 0, 3, 66, NULL, }, - { "CR[TPR]", 29, 0, 7, 66, "SC Section 5.8.3.3, \"Task Priority Register= (TPR - CR66)\" on page 2:119", }, - { "CR[TPR]", 29, 0, 1, 66, NULL, }, - { "CR%, % in 3-7, 10-15, 18, 28-63, 75-79, 82-127", 11, 0, 0, -1, NULL, = }, - { "DAHR%, % in 0-7", 12, 0, 1, -1, NULL, }, - { "DBR#", 13, 0, 2, -1, NULL, }, - { "DBR#", 13, 0, 3, -1, NULL, }, - { "DTC", 0, 0, 3, -1, NULL, }, - { "DTC", 0, 0, 2, -1, NULL, }, - { "DTC", 0, 0, 0, -1, NULL, }, - { "DTC", 0, 0, 2, -1, NULL, }, - { "DTC_LIMIT*", 0, 0, 2, -1, NULL, }, - { "DTR", 0, 0, 3, -1, NULL, }, - { "DTR", 0, 0, 2, -1, NULL, }, - { "DTR", 0, 0, 3, -1, NULL, }, - { "DTR", 0, 0, 0, -1, NULL, }, - { "DTR", 0, 0, 2, -1, NULL, }, - { "FR%, % in 0 - 1", 14, 0, 0, -1, NULL, }, - { "FR%, % in 2 - 127", 15, 0, 2, -1, NULL, }, - { "FR%, % in 2 - 127", 15, 0, 0, -1, NULL, }, - { "GR0", 16, 0, 0, -1, NULL, }, - { "GR%, % in 1 - 127", 17, 0, 0, -1, NULL, }, - { "GR%, % in 1 - 127", 17, 0, 2, -1, NULL, }, - { "IBR#", 18, 0, 2, -1, NULL, }, - { "InService*", 19, 0, 3, -1, NULL, }, - { "InService*", 19, 0, 2, -1, NULL, }, - { "InService*", 19, 0, 2, -1, NULL, }, - { "IP", 0, 0, 0, -1, NULL, }, - { "ITC", 0, 0, 4, -1, NULL, }, - { "ITC", 0, 0, 2, -1, NULL, }, - { "ITC", 0, 0, 0, -1, NULL, }, - { "ITC", 0, 0, 4, -1, NULL, }, - { "ITC", 0, 0, 2, -1, NULL, }, - { "ITC_LIMIT*", 0, 0, 2, -1, NULL, }, - { "ITR", 0, 0, 2, -1, NULL, }, - { "ITR", 0, 0, 4, -1, NULL, }, - { "ITR", 0, 0, 2, -1, NULL, }, - { "ITR", 0, 0, 0, -1, NULL, }, - { "ITR", 0, 0, 4, -1, NULL, }, - { "memory", 0, 0, 0, -1, NULL, }, - { "MSR#", 20, 0, 5, -1, NULL, }, - { "PKR#", 21, 0, 3, -1, NULL, }, - { "PKR#", 21, 0, 0, -1, NULL, }, - { "PKR#", 21, 0, 2, -1, NULL, }, - { "PKR#", 21, 0, 2, -1, NULL, }, - { "PMC#", 22, 0, 2, -1, NULL, }, - { "PMC#", 22, 0, 7, -1, "SC Section 7.2.1, \"Generic Performance Counter= Registers\" for PMC[0].fr on page 2:150", }, - { "PMD#", 23, 0, 2, -1, NULL, }, - { "PR0", 0, 0, 0, -1, NULL, }, - { "PR%, % in 1 - 15", 24, 0, 2, -1, NULL, }, - { "PR%, % in 1 - 15", 24, 0, 2, -1, NULL, }, - { "PR%, % in 1 - 15", 24, 0, 0, -1, NULL, }, - { "PR%, % in 16 - 62", 25, 0, 2, -1, NULL, }, - { "PR%, % in 16 - 62", 25, 0, 2, -1, NULL, }, - { "PR%, % in 16 - 62", 25, 0, 0, -1, NULL, }, - { "PR63", 26, 0, 2, -1, NULL, }, - { "PR63", 26, 0, 2, -1, NULL, }, - { "PR63", 26, 0, 0, -1, NULL, }, - { "PSR.ac", 30, 0, 1, 3, NULL, }, - { "PSR.ac", 30, 0, 3, 3, NULL, }, - { "PSR.ac", 30, 0, 2, 3, NULL, }, - { "PSR.ac", 30, 0, 2, 3, NULL, }, - { "PSR.be", 30, 0, 1, 1, NULL, }, - { "PSR.be", 30, 0, 3, 1, NULL, }, - { "PSR.be", 30, 0, 2, 1, NULL, }, - { "PSR.be", 30, 0, 2, 1, NULL, }, - { "PSR.bn", 30, 0, 2, 44, NULL, }, - { "PSR.cpl", 30, 0, 1, 32, NULL, }, - { "PSR.cpl", 30, 0, 2, 32, NULL, }, - { "PSR.da", 30, 0, 2, 38, NULL, }, - { "PSR.db", 30, 0, 3, 24, NULL, }, - { "PSR.db", 30, 0, 2, 24, NULL, }, - { "PSR.db", 30, 0, 2, 24, NULL, }, - { "PSR.dd", 30, 0, 2, 39, NULL, }, - { "PSR.dfh", 30, 0, 3, 19, NULL, }, - { "PSR.dfh", 30, 0, 2, 19, NULL, }, - { "PSR.dfh", 30, 0, 2, 19, NULL, }, - { "PSR.dfl", 30, 0, 3, 18, NULL, }, - { "PSR.dfl", 30, 0, 2, 18, NULL, }, - { "PSR.dfl", 30, 0, 2, 18, NULL, }, - { "PSR.di", 30, 0, 3, 22, NULL, }, - { "PSR.di", 30, 0, 2, 22, NULL, }, - { "PSR.di", 30, 0, 2, 22, NULL, }, - { "PSR.dt", 30, 0, 3, 17, NULL, }, - { "PSR.dt", 30, 0, 2, 17, NULL, }, - { "PSR.dt", 30, 0, 2, 17, NULL, }, - { "PSR.ed", 30, 0, 2, 43, NULL, }, - { "PSR.i", 30, 0, 2, 14, NULL, }, - { "PSR.ia", 30, 0, 0, 14, NULL, }, - { "PSR.ic", 30, 0, 2, 13, NULL, }, - { "PSR.ic", 30, 0, 3, 13, NULL, }, - { "PSR.ic", 30, 0, 2, 13, NULL, }, - { "PSR.id", 30, 0, 0, 14, NULL, }, - { "PSR.is", 30, 0, 0, 14, NULL, }, - { "PSR.it", 30, 0, 2, 14, NULL, }, - { "PSR.lp", 30, 0, 2, 25, NULL, }, - { "PSR.lp", 30, 0, 3, 25, NULL, }, - { "PSR.lp", 30, 0, 2, 25, NULL, }, - { "PSR.mc", 30, 0, 2, 35, NULL, }, - { "PSR.mfh", 30, 0, 2, 5, NULL, }, - { "PSR.mfl", 30, 0, 2, 4, NULL, }, - { "PSR.pk", 30, 0, 3, 15, NULL, }, - { "PSR.pk", 30, 0, 2, 15, NULL, }, - { "PSR.pk", 30, 0, 2, 15, NULL, }, - { "PSR.pp", 30, 0, 2, 21, NULL, }, - { "PSR.ri", 30, 0, 0, 41, NULL, }, - { "PSR.rt", 30, 0, 2, 27, NULL, }, - { "PSR.rt", 30, 0, 3, 27, NULL, }, - { "PSR.rt", 30, 0, 2, 27, NULL, }, - { "PSR.si", 30, 0, 2, 23, NULL, }, - { "PSR.si", 30, 0, 3, 23, NULL, }, - { "PSR.si", 30, 0, 2, 23, NULL, }, - { "PSR.sp", 30, 0, 2, 20, NULL, }, - { "PSR.sp", 30, 0, 3, 20, NULL, }, - { "PSR.sp", 30, 0, 2, 20, NULL, }, - { "PSR.ss", 30, 0, 2, 40, NULL, }, - { "PSR.tb", 30, 0, 3, 26, NULL, }, - { "PSR.tb", 30, 0, 2, 26, NULL, }, - { "PSR.tb", 30, 0, 2, 26, NULL, }, - { "PSR.up", 30, 0, 2, 2, NULL, }, - { "PSR.vm", 30, 0, 1, 46, NULL, }, - { "PSR.vm", 30, 0, 2, 46, NULL, }, - { "RR#", 27, 0, 3, -1, NULL, }, - { "RR#", 27, 0, 2, -1, NULL, }, - { "RSE", 31, 0, 2, -1, NULL, }, - { "ALAT", 0, 1, 0, -1, NULL, }, - { "AR[BSP]", 28, 1, 2, 17, NULL, }, - { "AR[BSPSTORE]", 28, 1, 2, 18, NULL, }, - { "AR[CCV]", 28, 1, 2, 32, NULL, }, - { "AR[CFLG]", 28, 1, 2, 27, NULL, }, - { "AR[CSD]", 28, 1, 2, 25, NULL, }, - { "AR[EC]", 28, 1, 2, 66, NULL, }, - { "AR[EFLAG]", 28, 1, 2, 24, NULL, }, - { "AR[FCR]", 28, 1, 2, 21, NULL, }, - { "AR[FDR]", 28, 1, 2, 30, NULL, }, - { "AR[FIR]", 28, 1, 2, 29, NULL, }, - { "AR[FPSR].sf0.controls", 32, 1, 2, -1, NULL, }, - { "AR[FPSR].sf1.controls", 32, 1, 2, -1, NULL, }, - { "AR[FPSR].sf2.controls", 32, 1, 2, -1, NULL, }, - { "AR[FPSR].sf3.controls", 32, 1, 2, -1, NULL, }, - { "AR[FPSR].sf0.flags", 32, 1, 0, -1, NULL, }, - { "AR[FPSR].sf0.flags", 32, 1, 2, -1, NULL, }, - { "AR[FPSR].sf0.flags", 32, 1, 2, -1, NULL, }, - { "AR[FPSR].sf1.flags", 32, 1, 0, -1, NULL, }, - { "AR[FPSR].sf1.flags", 32, 1, 2, -1, NULL, }, - { "AR[FPSR].sf1.flags", 32, 1, 2, -1, NULL, }, - { "AR[FPSR].sf2.flags", 32, 1, 0, -1, NULL, }, - { "AR[FPSR].sf2.flags", 32, 1, 2, -1, NULL, }, - { "AR[FPSR].sf2.flags", 32, 1, 2, -1, NULL, }, - { "AR[FPSR].sf3.flags", 32, 1, 0, -1, NULL, }, - { "AR[FPSR].sf3.flags", 32, 1, 2, -1, NULL, }, - { "AR[FPSR].sf3.flags", 32, 1, 2, -1, NULL, }, - { "AR[FPSR].rv", 32, 1, 2, -1, NULL, }, - { "AR[FPSR].traps", 32, 1, 2, -1, NULL, }, - { "AR[FSR]", 28, 1, 2, 28, NULL, }, - { "AR[ITC]", 28, 1, 2, 44, NULL, }, - { "AR[K%], % in 0 - 7", 1, 1, 2, -1, NULL, }, - { "AR[LC]", 28, 1, 2, 65, NULL, }, - { "AR[PFS]", 28, 1, 0, 64, NULL, }, - { "AR[PFS]", 28, 1, 2, 64, NULL, }, - { "AR[PFS]", 28, 1, 2, 64, NULL, }, - { "AR[RNAT]", 28, 1, 2, 19, NULL, }, - { "AR[RSC]", 28, 1, 2, 16, NULL, }, - { "AR[RUC]", 28, 1, 2, 45, NULL, }, - { "AR[SSD]", 28, 1, 2, 26, NULL, }, - { "AR[UNAT]{%}, % in 0 - 63", 2, 1, 2, -1, NULL, }, - { "AR%, % in 8-15, 20, 22-23, 31, 33-35, 37-39, 41-43, 46-47, 67-111", 3= , 1, 0, -1, NULL, }, - { "AR%, % in 48 - 63, 112-127", 4, 1, 2, -1, NULL, }, - { "BR%, % in 0 - 7", 5, 1, 2, -1, NULL, }, - { "BR%, % in 0 - 7", 5, 1, 2, -1, NULL, }, - { "BR%, % in 0 - 7", 5, 1, 2, -1, NULL, }, - { "BR%, % in 0 - 7", 5, 1, 0, -1, NULL, }, - { "CFM", 6, 1, 2, -1, NULL, }, - { "CPUID#", 7, 1, 0, -1, NULL, }, - { "CR[CMCV]", 29, 1, 2, 74, NULL, }, - { "CR[DCR]", 29, 1, 2, 0, NULL, }, - { "CR[EOI]", 29, 1, 7, 67, "SC Section 5.8.3.4, \"End of External Interr= upt Register (EOI - CR67)\" on page 2:119", }, - { "CR[GPTA]", 29, 1, 2, 9, NULL, }, - { "CR[IFA]", 29, 1, 2, 20, NULL, }, - { "CR[IFS]", 29, 1, 2, 23, NULL, }, - { "CR[IHA]", 29, 1, 2, 25, NULL, }, - { "CR[IIB%], % in 0 - 1", 8, 1, 2, -1, NULL, }, - { "CR[IIM]", 29, 1, 2, 24, NULL, }, - { "CR[IIP]", 29, 1, 2, 19, NULL, }, - { "CR[IIPA]", 29, 1, 2, 22, NULL, }, - { "CR[IPSR]", 29, 1, 2, 16, NULL, }, - { "CR[IRR%], % in 0 - 3", 9, 1, 2, -1, NULL, }, - { "CR[ISR]", 29, 1, 2, 17, NULL, }, - { "CR[ITIR]", 29, 1, 2, 21, NULL, }, - { "CR[ITM]", 29, 1, 2, 1, NULL, }, - { "CR[ITV]", 29, 1, 2, 72, NULL, }, - { "CR[IVA]", 29, 1, 2, 2, NULL, }, - { "CR[IVR]", 29, 1, 7, 65, "SC", }, - { "CR[LID]", 29, 1, 7, 64, "SC", }, - { "CR[LRR%], % in 0 - 1", 10, 1, 2, -1, NULL, }, - { "CR[PMV]", 29, 1, 2, 73, NULL, }, - { "CR[PTA]", 29, 1, 2, 8, NULL, }, - { "CR[TPR]", 29, 1, 2, 66, NULL, }, - { "CR%, % in 3-7, 10-15, 18, 28-63, 75-79, 82-127", 11, 1, 0, -1, NULL, = }, - { "DAHR%, % in 0-7", 12, 1, 1, -1, NULL, }, - { "DBR#", 13, 1, 2, -1, NULL, }, - { "DTC", 0, 1, 0, -1, NULL, }, - { "DTC", 0, 1, 2, -1, NULL, }, - { "DTC", 0, 1, 2, -1, NULL, }, - { "DTC_LIMIT*", 0, 1, 2, -1, NULL, }, - { "DTR", 0, 1, 2, -1, NULL, }, - { "DTR", 0, 1, 2, -1, NULL, }, - { "DTR", 0, 1, 2, -1, NULL, }, - { "DTR", 0, 1, 0, -1, NULL, }, - { "FR%, % in 0 - 1", 14, 1, 0, -1, NULL, }, - { "FR%, % in 2 - 127", 15, 1, 2, -1, NULL, }, - { "GR0", 16, 1, 0, -1, NULL, }, - { "GR%, % in 1 - 127", 17, 1, 2, -1, NULL, }, - { "IBR#", 18, 1, 2, -1, NULL, }, - { "InService*", 19, 1, 7, -1, "SC", }, - { "IP", 0, 1, 0, -1, NULL, }, - { "ITC", 0, 1, 0, -1, NULL, }, - { "ITC", 0, 1, 2, -1, NULL, }, - { "ITC", 0, 1, 2, -1, NULL, }, - { "ITR", 0, 1, 2, -1, NULL, }, - { "ITR", 0, 1, 2, -1, NULL, }, - { "ITR", 0, 1, 0, -1, NULL, }, - { "memory", 0, 1, 0, -1, NULL, }, - { "MSR#", 20, 1, 7, -1, "SC", }, - { "PKR#", 21, 1, 0, -1, NULL, }, - { "PKR#", 21, 1, 0, -1, NULL, }, - { "PKR#", 21, 1, 2, -1, NULL, }, - { "PMC#", 22, 1, 2, -1, NULL, }, - { "PMD#", 23, 1, 2, -1, NULL, }, - { "PR0", 0, 1, 0, -1, NULL, }, - { "PR%, % in 1 - 15", 24, 1, 0, -1, NULL, }, - { "PR%, % in 1 - 15", 24, 1, 0, -1, NULL, }, - { "PR%, % in 1 - 15", 24, 1, 2, -1, NULL, }, - { "PR%, % in 1 - 15", 24, 1, 2, -1, NULL, }, - { "PR%, % in 16 - 62", 25, 1, 0, -1, NULL, }, - { "PR%, % in 16 - 62", 25, 1, 0, -1, NULL, }, - { "PR%, % in 16 - 62", 25, 1, 2, -1, NULL, }, - { "PR%, % in 16 - 62", 25, 1, 2, -1, NULL, }, - { "PR63", 26, 1, 0, -1, NULL, }, - { "PR63", 26, 1, 0, -1, NULL, }, - { "PR63", 26, 1, 2, -1, NULL, }, - { "PR63", 26, 1, 2, -1, NULL, }, - { "PSR.ac", 30, 1, 2, 3, NULL, }, - { "PSR.be", 30, 1, 2, 1, NULL, }, - { "PSR.bn", 30, 1, 2, 44, NULL, }, - { "PSR.cpl", 30, 1, 2, 32, NULL, }, - { "PSR.da", 30, 1, 2, 38, NULL, }, - { "PSR.db", 30, 1, 2, 24, NULL, }, - { "PSR.dd", 30, 1, 2, 39, NULL, }, - { "PSR.dfh", 30, 1, 2, 19, NULL, }, - { "PSR.dfl", 30, 1, 2, 18, NULL, }, - { "PSR.di", 30, 1, 2, 22, NULL, }, - { "PSR.dt", 30, 1, 2, 17, NULL, }, - { "PSR.ed", 30, 1, 2, 43, NULL, }, - { "PSR.i", 30, 1, 2, 14, NULL, }, - { "PSR.ia", 30, 1, 2, 14, NULL, }, - { "PSR.ic", 30, 1, 2, 13, NULL, }, - { "PSR.id", 30, 1, 2, 14, NULL, }, - { "PSR.is", 30, 1, 2, 14, NULL, }, - { "PSR.it", 30, 1, 2, 14, NULL, }, - { "PSR.lp", 30, 1, 2, 25, NULL, }, - { "PSR.mc", 30, 1, 2, 35, NULL, }, - { "PSR.mfh", 30, 1, 0, 5, NULL, }, - { "PSR.mfh", 30, 1, 2, 5, NULL, }, - { "PSR.mfh", 30, 1, 2, 5, NULL, }, - { "PSR.mfl", 30, 1, 0, 4, NULL, }, - { "PSR.mfl", 30, 1, 2, 4, NULL, }, - { "PSR.mfl", 30, 1, 2, 4, NULL, }, - { "PSR.pk", 30, 1, 2, 15, NULL, }, - { "PSR.pp", 30, 1, 2, 21, NULL, }, - { "PSR.ri", 30, 1, 2, 41, NULL, }, - { "PSR.rt", 30, 1, 2, 27, NULL, }, - { "PSR.si", 30, 1, 2, 23, NULL, }, - { "PSR.sp", 30, 1, 2, 20, NULL, }, - { "PSR.ss", 30, 1, 2, 40, NULL, }, - { "PSR.tb", 30, 1, 2, 26, NULL, }, - { "PSR.up", 30, 1, 2, 2, NULL, }, - { "PSR.vm", 30, 1, 2, 46, NULL, }, - { "RR#", 27, 1, 2, -1, NULL, }, - { "RSE", 31, 1, 2, -1, NULL, }, - { "PR63", 26, 2, 6, -1, NULL, }, -}; - -static const unsigned short dep0[] =3D { - 100, 288, 2143, 2333, -}; - -static const unsigned short dep1[] =3D { - 41, 42, 100, 161, 165, 178, 188, 288, 2141, 2142, 2143, 2169, 2170, 2173, - 2176, 2333, 4136, 20619, -}; - -static const unsigned short dep2[] =3D { - 100, 288, 2169, 2170, 2172, 2173, 2175, 2176, 2178, 2350, 2353, 2354, 23= 57, - 2358, 2361, 2362, -}; - -static const unsigned short dep3[] =3D { - 41, 42, 100, 161, 165, 178, 188, 288, 2141, 2142, 2143, 2169, 2170, 2173, - 2176, 2350, 2353, 2354, 2357, 2358, 2361, 2362, 4136, 20619, -}; - -static const unsigned short dep4[] =3D { - 100, 288, 22649, 22650, 22652, 22653, 22655, 22656, 22658, 22830, 22833,= 22834, - 22837, 22838, 22841, 22842, -}; - -static const unsigned short dep5[] =3D { - 41, 42, 100, 161, 165, 178, 188, 288, 2141, 2142, 2143, 2169, 2170, 2173, - 2176, 4136, 20619, 22830, 22833, 22834, 22837, 22838, 22841, 22842, -}; - -static const unsigned short dep6[] =3D { - 100, 288, 2169, 2170, 2172, 2173, 2175, 2176, 2178, 2350, 2351, 2353, 23= 55, - 2357, 2359, 2361, -}; - -static const unsigned short dep7[] =3D { - 41, 42, 100, 161, 165, 178, 188, 288, 2141, 2142, 2143, 2169, 2170, 2173, - 2176, 2350, 2351, 2354, 2355, 2358, 2359, 2362, 4136, 20619, -}; - -static const unsigned short dep8[] =3D { - 100, 288, 2169, 2170, 2172, 2173, 2175, 2176, 2178, 2350, 2352, 2354, 23= 56, - 2358, 2360, 2362, -}; - -static const unsigned short dep9[] =3D { - 41, 42, 100, 161, 165, 178, 188, 288, 2141, 2142, 2143, 2169, 2170, 2173, - 2176, 2350, 2352, 2353, 2356, 2357, 2360, 2361, 4136, 20619, -}; - -static const unsigned short dep10[] =3D { - 100, 288, 2169, 2170, 2172, 2173, 2175, 2176, 2178, 2350, 2351, 2352, 23= 53, - 2354, 2355, 2356, 2357, 2358, 2359, 2360, 2361, 2362, -}; - -static const unsigned short dep11[] =3D { - 41, 42, 100, 161, 165, 178, 188, 288, 2141, 2142, 2143, 2169, 2170, 2173, - 2176, 2350, 2351, 2352, 2353, 2354, 2355, 2356, 2357, 2358, 2359, 2360, = 2361, - 2362, 4136, 20619, -}; - -static const unsigned short dep12[] =3D { - 100, 288, 2401, -}; - -static const unsigned short dep13[] =3D { - 41, 42, 100, 161, 165, 167, 178, 188, 189, 191, 288, 2083, 2084, 2169, 2= 171, - 2172, 2174, 2175, 2177, 2178, 4136, -}; - -static const unsigned short dep14[] =3D { - 100, 166, 288, 331, 2401, 28869, 29024, -}; - -static const unsigned short dep15[] =3D { - 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 2= 1, - 22, 23, 24, 25, 26, 28, 29, 30, 31, 32, 33, 34, 41, 42, 100, 153, 155, 1= 61, - 165, 167, 178, 188, 189, 191, 288, 331, 2083, 2084, 2169, 2171, 2172, 21= 74, - 2175, 2177, 2178, 4136, 28869, 29024, -}; - -static const unsigned short dep16[] =3D { - 1, 6, 41, 77, 100, 140, 199, 204, 245, 272, 288, 318, 2401, 28869, 29024, -}; - -static const unsigned short dep17[] =3D { - 1, 25, 27, 39, 41, 42, 100, 161, 165, 167, 169, 170, 178, 188, 189, 191,= 199, - 204, 245, 272, 288, 318, 2083, 2084, 2169, 2171, 2172, 2174, 2175, 2177,= 2178, - 4136, 28869, 29024, -}; - -static const unsigned short dep18[] =3D { - 1, 41, 52, 100, 199, 245, 252, 288, 28869, 29024, -}; - -static const unsigned short dep19[] =3D { - 1, 39, 41, 42, 100, 161, 163, 164, 165, 178, 188, 193, 194, 199, 245, 25= 2, - 288, 4136, 28869, 29024, -}; - -static const unsigned short dep20[] =3D { - 41, 100, 245, 288, -}; - -static const unsigned short dep21[] =3D { - 100, 161, 165, 178, 188, 245, 288, -}; - -static const unsigned short dep22[] =3D { - 1, 41, 100, 134, 138, 139, 141, 142, 145, 146, 149, 152, 155, 158, 159, = 160, - 161, 164, 165, 166, 167, 170, 171, 172, 173, 176, 177, 178, 181, 184, 18= 7, - 188, 191, 192, 194, 199, 245, 272, 288, 315, 316, 317, 318, 319, 320, 32= 1, - 322, 323, 324, 325, 326, 327, 328, 329, 330, 331, 332, 333, 334, 336, 33= 7, - 339, 340, 341, 342, 343, 344, 345, 346, 347, 348, 349, 350, 28869, 29024, -}; - -static const unsigned short dep23[] =3D { - 1, 39, 41, 42, 51, 52, 57, 60, 75, 100, 140, 141, 161, 165, 178, 188, 19= 3, - 194, 199, 245, 272, 288, 315, 316, 317, 318, 319, 320, 321, 322, 323, 32= 4, - 325, 326, 327, 328, 329, 330, 331, 332, 333, 334, 336, 337, 339, 340, 34= 1, - 342, 343, 344, 345, 346, 347, 348, 349, 350, 4136, 28869, 29024, -}; - -static const unsigned short dep24[] =3D { - 100, 139, 288, 317, -}; - -static const unsigned short dep25[] =3D { - 100, 140, 141, 161, 165, 178, 188, 193, 194, 288, 317, -}; - -static const unsigned short dep26[] =3D { - 100, 140, 288, 318, -}; - -static const unsigned short dep27[] =3D { - 25, 26, 100, 101, 104, 108, 111, 140, 141, 161, 165, 167, 178, 188, 288,= 318, -}; - -static const unsigned short dep28[] =3D { - 100, 193, 288, 350, -}; - -static const unsigned short dep29[] =3D { - 100, 101, 104, 108, 111, 140, 141, 161, 165, 167, 178, 188, 288, 350, -}; - -static const unsigned short dep30[] =3D { - 41, 42, 100, 161, 165, 178, 188, 288, 2169, 2171, 2172, 2174, 2175, 2177, - 2178, 4136, -}; - -static const unsigned short dep31[] =3D { - 1, 25, 41, 77, 100, 199, 231, 232, 245, 272, 288, 2083, 2289, 2292, 2401, - 28869, 29024, -}; - -static const unsigned short dep32[] =3D { - 1, 6, 39, 41, 42, 77, 100, 140, 141, 161, 165, 167, 178, 188, 189, 191, = 199, - 231, 233, 245, 272, 288, 2083, 2084, 2169, 2171, 2172, 2174, 2175, 2177,= 2178, - 2290, 2292, 4136, 28869, 29024, -}; - -static const unsigned short dep33[] =3D { - 100, 288, -}; - -static const unsigned short dep34[] =3D { - 100, 161, 165, 178, 188, 288, 2083, 2085, -}; - -static const unsigned short dep35[] =3D { - 41, 42, 100, 161, 165, 167, 178, 188, 189, 191, 288, 2169, 2171, 2172, 2= 174, - 2175, 2177, 2178, 4136, -}; - -static const unsigned short dep36[] =3D { - 6, 38, 39, 40, 100, 128, 129, 204, 245, 288, 313, 314, 2401, -}; - -static const unsigned short dep37[] =3D { - 6, 38, 41, 42, 100, 161, 165, 167, 178, 188, 189, 191, 204, 245, 288, 31= 3, - 314, 353, 2169, 2171, 2172, 2174, 2175, 2177, 2178, 4136, -}; - -static const unsigned short dep38[] =3D { - 24, 100, 230, 288, 2401, -}; - -static const unsigned short dep39[] =3D { - 24, 41, 42, 100, 161, 165, 167, 178, 188, 189, 191, 230, 288, 2169, 2171, - 2172, 2174, 2175, 2177, 2178, 4136, -}; - -static const unsigned short dep40[] =3D { - 6, 24, 38, 39, 40, 100, 128, 129, 204, 230, 245, 288, 313, 314, 2401, -}; - -static const unsigned short dep41[] =3D { - 6, 24, 38, 41, 42, 100, 161, 165, 167, 178, 188, 189, 191, 204, 230, 245, - 288, 313, 314, 353, 2169, 2171, 2172, 2174, 2175, 2177, 2178, 4136, -}; - -static const unsigned short dep42[] =3D { - 1, 6, 39, 41, 42, 77, 100, 140, 141, 161, 165, 167, 178, 188, 189, 191, = 199, - 231, 233, 245, 272, 288, 2169, 2171, 2172, 2174, 2175, 2177, 2178, 2290,= 2292, - 4136, 28869, 29024, -}; - -static const unsigned short dep43[] =3D { - 100, 161, 165, 178, 188, 288, -}; - -static const unsigned short dep44[] =3D { - 15, 100, 213, 214, 288, 2139, 2331, 18604, 18605, 18767, 18768, 18770, 1= 8771, - 22649, 22650, 22651, 22653, 22654, 22656, 22657, 22830, 22833, 22834, 22= 837, - 22838, 22841, 22842, -}; - -static const unsigned short dep45[] =3D { - 11, 19, 20, 41, 42, 100, 161, 165, 178, 188, 213, 215, 288, 2138, 2139, = 2140, - 2169, 2170, 2173, 2176, 2331, 4136, 16531, 16533, 16534, 16536, 18767, 1= 8769, - 18770, 18772, 22830, 22833, 22834, 22837, 22838, 22841, 22842, -}; - -static const unsigned short dep46[] =3D { - 15, 16, 17, 18, 100, 213, 214, 216, 217, 219, 220, 222, 223, 288, 2139, = 2331, - 18604, 18605, 18767, 18768, 18770, 18771, 22649, 22650, 22651, 22653, 22= 654, - 22656, 22657, 22830, 22833, 22834, 22837, 22838, 22841, 22842, -}; - -static const unsigned short dep47[] =3D { - 11, 12, 13, 14, 19, 20, 41, 42, 100, 161, 165, 178, 188, 213, 215, 216, = 218, - 219, 221, 222, 224, 288, 2138, 2139, 2140, 2169, 2170, 2173, 2176, 2331,= 4136, - 16531, 16533, 16534, 16536, 18767, 18769, 18770, 18772, 22830, 22833, 22= 834, - 22837, 22838, 22841, 22842, -}; - -static const unsigned short dep48[] =3D { - 16, 100, 216, 217, 288, 2139, 2331, 18604, 18605, 18767, 18768, 18770, 1= 8771, - 22649, 22650, 22651, 22653, 22654, 22656, 22657, 22830, 22833, 22834, 22= 837, - 22838, 22841, 22842, -}; - -static const unsigned short dep49[] =3D { - 12, 19, 20, 41, 42, 100, 161, 165, 178, 188, 216, 218, 288, 2138, 2139, = 2140, - 2169, 2170, 2173, 2176, 2331, 4136, 16531, 16533, 16534, 16536, 18767, 1= 8769, - 18770, 18772, 22830, 22833, 22834, 22837, 22838, 22841, 22842, -}; - -static const unsigned short dep50[] =3D { - 17, 100, 219, 220, 288, 2139, 2331, 18604, 18605, 18767, 18768, 18770, 1= 8771, - 22649, 22650, 22651, 22653, 22654, 22656, 22657, 22830, 22833, 22834, 22= 837, - 22838, 22841, 22842, -}; - -static const unsigned short dep51[] =3D { - 13, 19, 20, 41, 42, 100, 161, 165, 178, 188, 219, 221, 288, 2138, 2139, = 2140, - 2169, 2170, 2173, 2176, 2331, 4136, 16531, 16533, 16534, 16536, 18767, 1= 8769, - 18770, 18772, 22830, 22833, 22834, 22837, 22838, 22841, 22842, -}; - -static const unsigned short dep52[] =3D { - 18, 100, 222, 223, 288, 2139, 2331, 18604, 18605, 18767, 18768, 18770, 1= 8771, - 22649, 22650, 22651, 22653, 22654, 22656, 22657, 22830, 22833, 22834, 22= 837, - 22838, 22841, 22842, -}; - -static const unsigned short dep53[] =3D { - 14, 19, 20, 41, 42, 100, 161, 165, 178, 188, 222, 224, 288, 2138, 2139, = 2140, - 2169, 2170, 2173, 2176, 2331, 4136, 16531, 16533, 16534, 16536, 18767, 1= 8769, - 18770, 18772, 22830, 22833, 22834, 22837, 22838, 22841, 22842, -}; - -static const unsigned short dep54[] =3D { - 15, 100, 213, 214, 288, 2139, 2331, 18604, 18605, 18767, 18768, 18770, 1= 8771, -}; - -static const unsigned short dep55[] =3D { - 11, 19, 20, 41, 42, 100, 161, 165, 178, 188, 213, 215, 288, 2138, 2139, = 2140, - 2169, 2170, 2173, 2176, 2331, 4136, 16531, 16533, 16534, 16536, 18767, 1= 8769, - 18770, 18772, -}; - -static const unsigned short dep56[] =3D { - 15, 16, 17, 18, 100, 213, 214, 216, 217, 219, 220, 222, 223, 288, 2139, = 2331, - 18604, 18605, 18767, 18768, 18770, 18771, -}; - -static const unsigned short dep57[] =3D { - 11, 12, 13, 14, 19, 20, 41, 42, 100, 161, 165, 178, 188, 213, 215, 216, = 218, - 219, 221, 222, 224, 288, 2138, 2139, 2140, 2169, 2170, 2173, 2176, 2331,= 4136, - 16531, 16533, 16534, 16536, 18767, 18769, 18770, 18772, -}; - -static const unsigned short dep58[] =3D { - 16, 100, 216, 217, 288, 2139, 2331, 18604, 18605, 18767, 18768, 18770, 1= 8771, -}; - -static const unsigned short dep59[] =3D { - 12, 19, 20, 41, 42, 100, 161, 165, 178, 188, 216, 218, 288, 2138, 2139, = 2140, - 2169, 2170, 2173, 2176, 2331, 4136, 16531, 16533, 16534, 16536, 18767, 1= 8769, - 18770, 18772, -}; - -static const unsigned short dep60[] =3D { - 17, 100, 219, 220, 288, 2139, 2331, 18604, 18605, 18767, 18768, 18770, 1= 8771, -}; - -static const unsigned short dep61[] =3D { - 13, 19, 20, 41, 42, 100, 161, 165, 178, 188, 219, 221, 288, 2138, 2139, = 2140, - 2169, 2170, 2173, 2176, 2331, 4136, 16531, 16533, 16534, 16536, 18767, 1= 8769, - 18770, 18772, -}; - -static const unsigned short dep62[] =3D { - 18, 100, 222, 223, 288, 2139, 2331, 18604, 18605, 18767, 18768, 18770, 1= 8771, -}; - -static const unsigned short dep63[] =3D { - 14, 19, 20, 41, 42, 100, 161, 165, 178, 188, 222, 224, 288, 2138, 2139, = 2140, - 2169, 2170, 2173, 2176, 2331, 4136, 16531, 16533, 16534, 16536, 18767, 1= 8769, - 18770, 18772, -}; - -static const unsigned short dep64[] =3D { - 100, 288, 2139, 2331, 18604, 18605, 18767, 18768, 18770, 18771, -}; - -static const unsigned short dep65[] =3D { - 41, 42, 100, 161, 165, 178, 188, 288, 2138, 2139, 2140, 2169, 2170, 2173, - 2176, 2331, 4136, 16531, 16533, 16534, 16536, 18767, 18769, 18770, 18772, -}; - -static const unsigned short dep66[] =3D { - 11, 100, 209, 288, -}; - -static const unsigned short dep67[] =3D { - 11, 41, 42, 100, 161, 165, 178, 188, 209, 288, 2169, 2170, 2173, 2176, 4= 136, -}; - -static const unsigned short dep68[] =3D { - 11, 41, 42, 100, 161, 165, 178, 188, 288, 2169, 2170, 2173, 2176, 4136, -}; - -static const unsigned short dep69[] =3D { - 12, 100, 210, 288, -}; - -static const unsigned short dep70[] =3D { - 11, 41, 42, 100, 161, 165, 178, 188, 210, 288, 2169, 2170, 2173, 2176, 4= 136, -}; - -static const unsigned short dep71[] =3D { - 13, 100, 211, 288, -}; - -static const unsigned short dep72[] =3D { - 11, 41, 42, 100, 161, 165, 178, 188, 211, 288, 2169, 2170, 2173, 2176, 4= 136, -}; - -static const unsigned short dep73[] =3D { - 14, 100, 212, 288, -}; - -static const unsigned short dep74[] =3D { - 11, 41, 42, 100, 161, 165, 178, 188, 212, 288, 2169, 2170, 2173, 2176, 4= 136, -}; - -static const unsigned short dep75[] =3D { - 15, 100, 214, 215, 288, -}; - -static const unsigned short dep76[] =3D { - 41, 42, 100, 161, 165, 178, 188, 214, 215, 288, 2169, 2170, 2173, 2176, = 4136, -}; - -static const unsigned short dep77[] =3D { - 41, 42, 100, 161, 165, 178, 188, 288, 2169, 2170, 2173, 2176, 4136, -}; - -static const unsigned short dep78[] =3D { - 16, 100, 217, 218, 288, -}; - -static const unsigned short dep79[] =3D { - 41, 42, 100, 161, 165, 178, 188, 217, 218, 288, 2169, 2170, 2173, 2176, = 4136, -}; - -static const unsigned short dep80[] =3D { - 17, 100, 220, 221, 288, -}; - -static const unsigned short dep81[] =3D { - 41, 42, 100, 161, 165, 178, 188, 220, 221, 288, 2169, 2170, 2173, 2176, = 4136, -}; - -static const unsigned short dep82[] =3D { - 18, 100, 223, 224, 288, -}; - -static const unsigned short dep83[] =3D { - 41, 42, 100, 161, 165, 178, 188, 223, 224, 288, 2169, 2170, 2173, 2176, = 4136, -}; - -static const unsigned short dep84[] =3D { - 15, 19, 20, 41, 42, 100, 161, 165, 167, 178, 188, 189, 191, 288, 2169, 2= 170, - 2173, 2176, 4136, -}; - -static const unsigned short dep85[] =3D { - 15, 16, 19, 20, 41, 42, 100, 161, 165, 167, 178, 188, 189, 191, 288, 216= 9, - 2170, 2173, 2176, 4136, -}; - -static const unsigned short dep86[] =3D { - 15, 17, 19, 20, 41, 42, 100, 161, 165, 167, 178, 188, 189, 191, 288, 216= 9, - 2170, 2173, 2176, 4136, -}; - -static const unsigned short dep87[] =3D { - 15, 18, 19, 20, 41, 42, 100, 161, 165, 167, 178, 188, 189, 191, 288, 216= 9, - 2170, 2173, 2176, 4136, -}; - -static const unsigned short dep88[] =3D { - 15, 100, 213, 214, 288, -}; - -static const unsigned short dep89[] =3D { - 11, 19, 20, 41, 42, 100, 161, 165, 178, 188, 213, 215, 288, 2169, 2170, = 2173, - 2176, 4136, -}; - -static const unsigned short dep90[] =3D { - 15, 16, 17, 18, 100, 213, 214, 216, 217, 219, 220, 222, 223, 288, -}; - -static const unsigned short dep91[] =3D { - 11, 12, 13, 14, 19, 20, 41, 42, 100, 161, 165, 178, 188, 213, 215, 216, = 218, - 219, 221, 222, 224, 288, 2169, 2170, 2173, 2176, 4136, -}; - -static const unsigned short dep92[] =3D { - 16, 100, 216, 217, 288, -}; - -static const unsigned short dep93[] =3D { - 12, 19, 20, 41, 42, 100, 161, 165, 178, 188, 216, 218, 288, 2169, 2170, = 2173, - 2176, 4136, -}; - -static const unsigned short dep94[] =3D { - 17, 100, 219, 220, 288, -}; - -static const unsigned short dep95[] =3D { - 13, 19, 20, 41, 42, 100, 161, 165, 178, 188, 219, 221, 288, 2169, 2170, = 2173, - 2176, 4136, -}; - -static const unsigned short dep96[] =3D { - 18, 100, 222, 223, 288, -}; - -static const unsigned short dep97[] =3D { - 14, 19, 20, 41, 42, 100, 161, 165, 178, 188, 222, 224, 288, 2169, 2170, = 2173, - 2176, 4136, -}; - -static const unsigned short dep98[] =3D { - 15, 100, 213, 214, 288, 2169, 2170, 2171, 2173, 2174, 2176, 2177, 2350, = 2353, - 2354, 2357, 2358, 2361, 2362, -}; - -static const unsigned short dep99[] =3D { - 11, 19, 20, 41, 42, 100, 161, 165, 178, 188, 213, 215, 288, 2138, 2139, = 2140, - 2169, 2170, 2173, 2176, 2350, 2353, 2354, 2357, 2358, 2361, 2362, 4136, = 16531, - 16533, 16534, 16536, -}; - -static const unsigned short dep100[] =3D { - 15, 16, 17, 18, 100, 213, 214, 216, 217, 219, 220, 222, 223, 288, 2169, = 2170, - 2171, 2173, 2174, 2176, 2177, 2350, 2353, 2354, 2357, 2358, 2361, 2362, -}; - -static const unsigned short dep101[] =3D { - 11, 12, 13, 14, 19, 20, 41, 42, 100, 161, 165, 178, 188, 213, 215, 216, = 218, - 219, 221, 222, 224, 288, 2138, 2139, 2140, 2169, 2170, 2173, 2176, 2350,= 2353, - 2354, 2357, 2358, 2361, 2362, 4136, 16531, 16533, 16534, 16536, -}; - -static const unsigned short dep102[] =3D { - 16, 100, 216, 217, 288, 2169, 2170, 2171, 2173, 2174, 2176, 2177, 2350, = 2353, - 2354, 2357, 2358, 2361, 2362, -}; - -static const unsigned short dep103[] =3D { - 12, 19, 20, 41, 42, 100, 161, 165, 178, 188, 216, 218, 288, 2138, 2139, = 2140, - 2169, 2170, 2173, 2176, 2350, 2353, 2354, 2357, 2358, 2361, 2362, 4136, = 16531, - 16533, 16534, 16536, -}; - -static const unsigned short dep104[] =3D { - 17, 100, 219, 220, 288, 2169, 2170, 2171, 2173, 2174, 2176, 2177, 2350, = 2353, - 2354, 2357, 2358, 2361, 2362, -}; - -static const unsigned short dep105[] =3D { - 13, 19, 20, 41, 42, 100, 161, 165, 178, 188, 219, 221, 288, 2138, 2139, = 2140, - 2169, 2170, 2173, 2176, 2350, 2353, 2354, 2357, 2358, 2361, 2362, 4136, = 16531, - 16533, 16534, 16536, -}; - -static const unsigned short dep106[] =3D { - 18, 100, 222, 223, 288, 2169, 2170, 2171, 2173, 2174, 2176, 2177, 2350, = 2353, - 2354, 2357, 2358, 2361, 2362, -}; - -static const unsigned short dep107[] =3D { - 14, 19, 20, 41, 42, 100, 161, 165, 178, 188, 222, 224, 288, 2138, 2139, = 2140, - 2169, 2170, 2173, 2176, 2350, 2353, 2354, 2357, 2358, 2361, 2362, 4136, = 16531, - 16533, 16534, 16536, -}; - -static const unsigned short dep108[] =3D { - 15, 100, 213, 214, 288, 22649, 22650, 22651, 22653, 22654, 22656, 22657,= 22830, - 22833, 22834, 22837, 22838, 22841, 22842, -}; - -static const unsigned short dep109[] =3D { - 11, 19, 20, 41, 42, 100, 161, 165, 178, 188, 213, 215, 288, 2138, 2139, = 2140, - 2169, 2170, 2173, 2176, 4136, 16531, 16533, 16534, 16536, 22830, 22833, = 22834, - 22837, 22838, 22841, 22842, -}; - -static const unsigned short dep110[] =3D { - 15, 16, 17, 18, 100, 213, 214, 216, 217, 219, 220, 222, 223, 288, 22649,= 22650, - 22651, 22653, 22654, 22656, 22657, 22830, 22833, 22834, 22837, 22838, 22= 841, - 22842, -}; - -static const unsigned short dep111[] =3D { - 11, 12, 13, 14, 19, 20, 41, 42, 100, 161, 165, 178, 188, 213, 215, 216, = 218, - 219, 221, 222, 224, 288, 2138, 2139, 2140, 2169, 2170, 2173, 2176, 4136,= 16531, - 16533, 16534, 16536, 22830, 22833, 22834, 22837, 22838, 22841, 22842, -}; - -static const unsigned short dep112[] =3D { - 16, 100, 216, 217, 288, 22649, 22650, 22651, 22653, 22654, 22656, 22657,= 22830, - 22833, 22834, 22837, 22838, 22841, 22842, -}; - -static const unsigned short dep113[] =3D { - 12, 19, 20, 41, 42, 100, 161, 165, 178, 188, 216, 218, 288, 2138, 2139, = 2140, - 2169, 2170, 2173, 2176, 4136, 16531, 16533, 16534, 16536, 22830, 22833, = 22834, - 22837, 22838, 22841, 22842, -}; - -static const unsigned short dep114[] =3D { - 17, 100, 219, 220, 288, 22649, 22650, 22651, 22653, 22654, 22656, 22657,= 22830, - 22833, 22834, 22837, 22838, 22841, 22842, -}; - -static const unsigned short dep115[] =3D { - 13, 19, 20, 41, 42, 100, 161, 165, 178, 188, 219, 221, 288, 2138, 2139, = 2140, - 2169, 2170, 2173, 2176, 4136, 16531, 16533, 16534, 16536, 22830, 22833, = 22834, - 22837, 22838, 22841, 22842, -}; - -static const unsigned short dep116[] =3D { - 18, 100, 222, 223, 288, 22649, 22650, 22651, 22653, 22654, 22656, 22657,= 22830, - 22833, 22834, 22837, 22838, 22841, 22842, -}; - -static const unsigned short dep117[] =3D { - 14, 19, 20, 41, 42, 100, 161, 165, 178, 188, 222, 224, 288, 2138, 2139, = 2140, - 2169, 2170, 2173, 2176, 4136, 16531, 16533, 16534, 16536, 22830, 22833, = 22834, - 22837, 22838, 22841, 22842, -}; - -static const unsigned short dep118[] =3D { - 100, 288, 2169, 2170, 2171, 2173, 2174, 2176, 2177, 2350, 2353, 2354, 23= 57, - 2358, 2361, 2362, -}; - -static const unsigned short dep119[] =3D { - 41, 42, 100, 161, 165, 178, 188, 288, 2138, 2139, 2140, 2169, 2170, 2173, - 2176, 2350, 2353, 2354, 2357, 2358, 2361, 2362, 4136, 16531, 16533, 1653= 4, - 16536, -}; - -static const unsigned short dep120[] =3D { - 100, 288, 22649, 22650, 22651, 22653, 22654, 22656, 22657, 22830, 22833,= 22834, - 22837, 22838, 22841, 22842, -}; - -static const unsigned short dep121[] =3D { - 41, 42, 100, 161, 165, 178, 188, 288, 2138, 2139, 2140, 2169, 2170, 2173, - 2176, 4136, 16531, 16533, 16534, 16536, 22830, 22833, 22834, 22837, 2283= 8, - 22841, 22842, -}; - -static const unsigned short dep122[] =3D { - 19, 20, 41, 42, 100, 161, 165, 178, 188, 288, 2138, 2139, 2140, 2169, 21= 70, - 2173, 2176, 2331, 4136, 16531, 16533, 16534, 16536, 18767, 18769, 18770,= 18772, -}; - -static const unsigned short dep123[] =3D { - 41, 42, 100, 161, 165, 167, 178, 188, 189, 191, 288, 2141, 2142, 2143, 2= 169, - 2170, 2173, 2176, 4136, 20619, -}; - -static const unsigned short dep124[] =3D { - 100, 288, 2084, 2085, 2290, 2291, -}; - -static const unsigned short dep125[] =3D { - 41, 42, 100, 161, 165, 178, 188, 288, 2141, 2142, 2143, 2169, 2170, 2173, - 2176, 2289, 2291, 4136, 20619, -}; - -static const unsigned short dep126[] =3D { - 41, 42, 100, 161, 165, 178, 188, 288, 2083, 2085, 2169, 2170, 2173, 2176, - 2333, 4136, 20619, -}; - -static const unsigned short dep127[] =3D { - 100, 288, 14458, 14460, 14461, 14463, 14464, 14466, 14641, 14642, 14645,= 14646, - 14649, 14650, -}; - -static const unsigned short dep128[] =3D { - 41, 42, 100, 161, 165, 178, 188, 288, 2141, 2142, 2143, 4136, 14641, 146= 42, - 14645, 14646, 14649, 14650, 20619, 24697, 24698, 24701, 24704, -}; - -static const unsigned short dep129[] =3D { - 100, 125, 127, 128, 130, 288, 309, 310, 313, 314, -}; - -static const unsigned short dep130[] =3D { - 41, 42, 100, 161, 165, 178, 188, 288, 309, 310, 313, 314, 4136, 24697, 2= 4698, - 24701, 24704, -}; - -static const unsigned short dep131[] =3D { - 41, 42, 100, 161, 165, 178, 188, 288, 2169, 2170, 2173, 2176, 2333, 4136, - 20619, -}; - -static const unsigned short dep132[] =3D { - 41, 42, 100, 122, 125, 128, 161, 165, 178, 188, 288, 2333, 4136, 20619, = 24697, -}; - -static const unsigned short dep133[] =3D { - 6, 24, 26, 27, 100, 204, 230, 233, 288, 2082, 2288, -}; - -static const unsigned short dep134[] =3D { - 41, 42, 100, 161, 165, 178, 188, 204, 230, 232, 288, 2141, 2142, 2143, 2= 169, - 2170, 2173, 2176, 2288, 4136, 20619, -}; - -static const unsigned short dep135[] =3D { - 6, 24, 25, 26, 41, 42, 100, 161, 165, 178, 188, 288, 2082, 2169, 2170, 2= 173, - 2176, 2333, 4136, 20619, -}; - -static const unsigned short dep136[] =3D { - 41, 42, 100, 161, 165, 178, 188, 288, 2169, 2170, 2173, 2176, 2350, 2353, - 2354, 2357, 2358, 2361, 2362, 4136, -}; - -static const unsigned short dep137[] =3D { - 41, 42, 100, 161, 165, 178, 188, 288, 2169, 2170, 2173, 2176, 4136, 2283= 0, - 22833, 22834, 22837, 22838, 22841, 22842, -}; - -static const unsigned short dep138[] =3D { - 41, 42, 100, 161, 165, 178, 188, 288, 2169, 2170, 2173, 2176, 2350, 2351, - 2354, 2355, 2358, 2359, 2362, 4136, -}; - -static const unsigned short dep139[] =3D { - 41, 42, 100, 161, 165, 178, 188, 288, 2169, 2170, 2173, 2176, 2350, 2352, - 2353, 2356, 2357, 2360, 2361, 4136, -}; - -static const unsigned short dep140[] =3D { - 41, 42, 100, 161, 165, 178, 188, 288, 2169, 2170, 2173, 2176, 2350, 2351, - 2352, 2353, 2354, 2355, 2356, 2357, 2358, 2359, 2360, 2361, 2362, 4136, -}; - -static const unsigned short dep141[] =3D { - 0, 41, 42, 100, 161, 165, 167, 178, 188, 189, 191, 288, 2169, 2170, 2173, - 2176, 4136, -}; - -static const unsigned short dep142[] =3D { - 0, 100, 198, 288, -}; - -static const unsigned short dep143[] =3D { - 0, 41, 42, 100, 161, 165, 167, 178, 188, 189, 191, 198, 288, 2169, 2170,= 2173, - 2176, 4136, -}; - -static const unsigned short dep144[] =3D { - 41, 42, 100, 161, 165, 178, 188, 198, 288, 2169, 2170, 2173, 2176, 4136, -}; - -static const unsigned short dep145[] =3D { - 2, 28, 100, 200, 234, 288, 28869, 29024, -}; - -static const unsigned short dep146[] =3D { - 1, 2, 28, 29, 100, 161, 165, 178, 180, 181, 188, 200, 234, 288, 28869, 2= 9024, -}; - -static const unsigned short dep147[] =3D { - 1, 28, 29, 39, 41, 42, 100, 161, 165, 178, 180, 181, 188, 200, 234, 288,= 4136, - 28869, 29024, -}; - -static const unsigned short dep148[] =3D { - 0, 41, 42, 100, 161, 165, 178, 188, 198, 288, 2169, 2170, 2173, 2176, 41= 36, -}; - -static const unsigned short dep149[] =3D { - 1, 2, 3, 4, 5, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, = 22, - 28, 29, 30, 31, 32, 100, 199, 200, 201, 202, 203, 205, 206, 207, 208, 20= 9, - 210, 211, 212, 214, 215, 217, 218, 220, 221, 223, 224, 225, 226, 227, 22= 8, - 234, 235, 236, 237, 238, 272, 288, 2071, 2082, 2277, 2288, 28869, 29024, -}; - -static const unsigned short dep150[] =3D { - 29, 41, 42, 100, 140, 141, 161, 165, 178, 188, 193, 194, 199, 200, 201, = 202, - 203, 205, 206, 207, 208, 209, 210, 211, 212, 214, 215, 217, 218, 220, 22= 1, - 223, 224, 225, 226, 227, 228, 234, 235, 236, 237, 238, 272, 288, 2141, 2= 142, - 2143, 2169, 2170, 2173, 2176, 2277, 2288, 4136, 20619, 28869, 29024, -}; - -static const unsigned short dep151[] =3D { - 77, 272, -}; - -static const unsigned short dep152[] =3D { - 272, -}; - -static const unsigned short dep153[] =3D { - 100, 288, 14467, 14469, 14471, 14473, 14508, 14509, 14528, 14651, 14652,= 14672, - 14673, 14675, 14676, 14685, -}; - -static const unsigned short dep154[] =3D { - 41, 42, 100, 161, 165, 178, 186, 187, 188, 288, 2169, 2170, 2173, 2176, = 4136, - 14651, 14652, 14672, 14673, 14675, 14676, 14685, -}; - -static const unsigned short dep155[] =3D { - 14467, 14469, 14471, 14473, 14508, 14509, 14528, 14651, 14652, 14672, 14= 673, - 14675, 14676, 14685, -}; - -static const unsigned short dep156[] =3D { - 186, 187, 14651, 14652, 14672, 14673, 14675, 14676, 14685, -}; - -static const unsigned short dep157[] =3D { - 100, 288, 14468, 14469, 14472, 14473, 14483, 14484, 14486, 14487, 14489,= 14490, - 14492, 14493, 14496, 14498, 14499, 14508, 14509, 14510, 14511, 14513, 14= 518, - 14519, 14521, 14522, 14528, 14651, 14652, 14658, 14659, 14660, 14661, 14= 663, - 14665, 14672, 14673, 14675, 14676, 14677, 14678, 14681, 14682, 14685, -}; - -static const unsigned short dep158[] =3D { - 41, 42, 100, 140, 141, 161, 165, 178, 188, 193, 194, 288, 2169, 2170, 21= 73, - 2176, 4136, 14651, 14652, 14658, 14659, 14660, 14661, 14663, 14665, 1467= 2, - 14673, 14675, 14676, 14677, 14678, 14681, 14682, 14685, 34890, -}; - -static const unsigned short dep159[] =3D { - 41, 42, 100, 140, 141, 161, 165, 178, 188, 193, 194, 288, 2169, 2170, 21= 73, - 2176, 4136, 14651, 14652, 14658, 14659, 14660, 14661, 14663, 14665, 1467= 2, - 14673, 14675, 14676, 14677, 14678, 14681, 14682, 14685, -}; - -static const unsigned short dep160[] =3D { - 1, 2, 3, 4, 5, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, = 22, - 28, 29, 30, 31, 32, 41, 42, 100, 140, 141, 161, 165, 178, 183, 184, 188,= 193, - 194, 288, 2071, 2082, 2169, 2170, 2173, 2176, 2333, 4136, 20619, 28869, -}; - -static const unsigned short dep161[] =3D { - 44, 45, 46, 47, 48, 49, 50, 51, 53, 54, 55, 56, 57, 58, 59, 60, 62, 63, = 64, - 65, 66, 67, 69, 71, 72, 73, 74, 75, 97, 99, 100, 247, 248, 249, 250, 251, - 252, 253, 254, 255, 256, 257, 258, 260, 261, 262, 263, 264, 266, 268, 26= 9, - 270, 287, 288, 2118, 2315, -}; - -static const unsigned short dep162[] =3D { - 41, 42, 99, 100, 140, 141, 161, 163, 164, 165, 178, 188, 193, 194, 247, = 248, - 249, 250, 251, 252, 253, 254, 255, 256, 257, 258, 260, 261, 262, 263, 26= 4, - 266, 268, 269, 270, 287, 288, 2141, 2142, 2143, 2169, 2170, 2173, 2176, = 2315, - 4136, 20619, -}; - -static const unsigned short dep163[] =3D { - 61, 98, 100, 259, 287, 288, 2143, 2333, -}; - -static const unsigned short dep164[] =3D { - 41, 42, 44, 45, 47, 49, 50, 52, 53, 54, 55, 56, 58, 59, 62, 63, 65, 66, = 67, - 68, 69, 71, 72, 73, 97, 98, 100, 140, 141, 161, 163, 164, 165, 178, 188,= 193, - 194, 259, 287, 288, 2109, 2118, 2169, 2170, 2173, 2176, 2333, 4136, 2061= 9, -}; - -static const unsigned short dep165[] =3D { - 2, 28, 42, 100, 200, 234, 245, 288, 2143, 2333, 28869, 29024, -}; - -static const unsigned short dep166[] =3D { - 2, 25, 26, 28, 29, 39, 41, 42, 100, 161, 165, 178, 180, 181, 188, 200, 2= 34, - 245, 288, 2333, 4136, 20619, 28869, 29024, -}; - -static const unsigned short dep167[] =3D { - 100, 132, 133, 136, 137, 143, 144, 147, 148, 150, 151, 153, 154, 156, 15= 7, - 160, 162, 163, 168, 169, 172, 173, 174, 175, 177, 179, 180, 182, 183, 18= 5, - 186, 189, 190, 192, 288, 315, 316, 320, 322, 323, 324, 325, 327, 329, 33= 3, - 336, 337, 339, 340, 341, 342, 344, 345, 346, 348, 349, -}; - -static const unsigned short dep168[] =3D { - 41, 42, 100, 140, 141, 161, 165, 178, 188, 193, 194, 288, 315, 316, 320,= 322, - 323, 324, 325, 327, 329, 333, 336, 337, 339, 340, 341, 342, 344, 345, 34= 6, - 348, 349, 2141, 2142, 2143, 2169, 2170, 2173, 2176, 4136, 20619, 34890, -}; - -static const unsigned short dep169[] =3D { - 100, 131, 133, 135, 137, 172, 173, 192, 288, 315, 316, 336, 337, 339, 34= 0, - 349, -}; - -static const unsigned short dep170[] =3D { - 41, 42, 100, 161, 165, 178, 186, 187, 188, 288, 315, 316, 336, 337, 339,= 340, - 349, 2141, 2142, 2143, 2169, 2170, 2173, 2176, 4136, 20619, -}; - -static const unsigned short dep171[] =3D { - 41, 42, 100, 133, 134, 137, 138, 140, 141, 144, 145, 148, 149, 151, 152,= 154, - 155, 157, 158, 160, 161, 162, 164, 165, 167, 168, 170, 171, 172, 173, 17= 5, - 176, 177, 178, 179, 181, 182, 184, 185, 187, 188, 190, 191, 192, 193, 19= 4, - 288, 2169, 2170, 2173, 2176, 2333, 4136, 20619, -}; - -static const unsigned short dep172[] =3D { - 41, 42, 100, 133, 134, 137, 138, 161, 165, 172, 173, 178, 188, 192, 288,= 2169, - 2170, 2173, 2176, 2333, 4136, 20619, -}; - -static const unsigned short dep173[] =3D { - 41, 42, 72, 79, 80, 85, 87, 100, 114, 140, 141, 156, 158, 161, 165, 174,= 176, - 178, 188, 195, 288, 2141, 2142, 2143, 2169, 2170, 2173, 2176, 2333, 4136, - 20619, -}; - -static const unsigned short dep174[] =3D { - 41, 42, 72, 79, 80, 85, 87, 100, 114, 140, 141, 142, 143, 145, 146, 156,= 158, - 161, 165, 174, 176, 178, 188, 195, 288, 2141, 2142, 2143, 2169, 2170, 21= 73, - 2176, 4136, 20619, -}; - -static const unsigned short dep175[] =3D { - 80, 81, 100, 104, 105, 275, 276, 288, 290, 291, -}; - -static const unsigned short dep176[] =3D { - 41, 42, 48, 64, 81, 83, 89, 100, 102, 105, 140, 141, 161, 163, 164, 165,= 178, - 188, 193, 194, 195, 275, 276, 288, 290, 291, 2141, 2142, 2143, 2169, 217= 0, - 2173, 2176, 4136, 20619, -}; - -static const unsigned short dep177[] =3D { - 41, 42, 48, 64, 81, 83, 100, 102, 105, 107, 109, 140, 141, 161, 163, 164, - 165, 178, 188, 193, 194, 195, 275, 276, 288, 290, 291, 2141, 2142, 2143,= 2169, - 2170, 2173, 2176, 4136, 20619, -}; - -static const unsigned short dep178[] =3D { - 100, 288, 12483, 12484, 12639, -}; - -static const unsigned short dep179[] =3D { - 41, 42, 100, 140, 141, 161, 165, 178, 188, 193, 194, 288, 2141, 2142, 21= 43, - 2169, 2170, 2173, 2176, 4136, 12639, 20619, -}; - -static const unsigned short dep180[] =3D { - 100, 288, 6222, 6223, 6417, -}; - -static const unsigned short dep181[] =3D { - 41, 42, 100, 140, 141, 161, 165, 178, 188, 193, 194, 288, 2141, 2142, 21= 43, - 2169, 2170, 2173, 2176, 4136, 6417, 20619, -}; - -static const unsigned short dep182[] =3D { - 100, 288, 6240, 6430, -}; - -static const unsigned short dep183[] =3D { - 41, 42, 100, 140, 141, 161, 165, 178, 188, 193, 194, 288, 2141, 2142, 21= 43, - 2169, 2170, 2173, 2176, 4136, 6430, 20619, -}; - -static const unsigned short dep184[] =3D { - 100, 288, 6258, 6259, 6260, 6261, 6441, 6443, 8490, -}; - -static const unsigned short dep185[] =3D { - 41, 42, 100, 140, 141, 161, 165, 178, 188, 193, 194, 288, 2141, 2142, 21= 43, - 2169, 2170, 2173, 2176, 4136, 6261, 6442, 6443, 8307, 8489, 20619, -}; - -static const unsigned short dep186[] =3D { - 100, 288, 6262, 6263, 6444, -}; - -static const unsigned short dep187[] =3D { - 41, 42, 100, 140, 141, 161, 165, 178, 188, 193, 194, 288, 2141, 2142, 21= 43, - 2169, 2170, 2173, 2176, 4136, 6444, 20619, -}; - -static const unsigned short dep188[] =3D { - 100, 288, 6264, 6445, -}; - -static const unsigned short dep189[] =3D { - 41, 42, 100, 140, 141, 161, 165, 178, 188, 193, 194, 288, 2141, 2142, 21= 43, - 2169, 2170, 2173, 2176, 4136, 6445, 20619, -}; - -static const unsigned short dep190[] =3D { - 100, 288, 10353, 10536, -}; - -static const unsigned short dep191[] =3D { - 41, 42, 100, 140, 141, 161, 165, 178, 188, 193, 194, 288, 2141, 2142, 21= 43, - 2169, 2170, 2173, 2176, 4136, 10536, 20619, -}; - -static const unsigned short dep192[] =3D { - 80, 81, 85, 86, 100, 104, 105, 275, 276, 278, 279, 288, 290, 291, -}; - -static const unsigned short dep193[] =3D { - 41, 42, 48, 64, 81, 83, 86, 89, 100, 102, 105, 140, 141, 161, 163, 164, = 165, - 178, 188, 193, 194, 195, 275, 276, 278, 280, 288, 290, 291, 2141, 2142, = 2143, - 2169, 2170, 2173, 2176, 4136, 20619, -}; - -static const unsigned short dep194[] =3D { - 80, 81, 100, 104, 105, 107, 108, 275, 276, 288, 290, 291, 292, 293, -}; - -static const unsigned short dep195[] =3D { - 41, 42, 48, 64, 81, 83, 100, 102, 105, 107, 109, 140, 141, 161, 163, 164, - 165, 178, 188, 193, 194, 195, 275, 276, 288, 290, 291, 292, 293, 2141, 2= 142, - 2143, 2169, 2170, 2173, 2176, 4136, 20619, -}; - -static const unsigned short dep196[] =3D { - 41, 42, 100, 140, 141, 161, 165, 178, 188, 193, 194, 288, 2141, 2142, 21= 43, - 2169, 2170, 2173, 2176, 2333, 4136, 12484, 20619, -}; - -static const unsigned short dep197[] =3D { - 41, 42, 100, 140, 141, 161, 165, 178, 188, 193, 194, 288, 2141, 2142, 21= 43, - 2169, 2170, 2173, 2176, 2333, 4136, 6222, 20619, -}; - -static const unsigned short dep198[] =3D { - 41, 42, 100, 140, 141, 161, 165, 178, 188, 193, 194, 288, 2141, 2142, 21= 43, - 2169, 2170, 2173, 2176, 2333, 4136, 6240, 20619, -}; - -static const unsigned short dep199[] =3D { - 41, 42, 100, 140, 141, 161, 165, 178, 188, 193, 194, 288, 2141, 2142, 21= 43, - 2169, 2170, 2173, 2176, 2333, 4136, 6260, 8306, 20619, -}; - -static const unsigned short dep200[] =3D { - 41, 42, 100, 140, 141, 161, 165, 178, 188, 193, 194, 288, 2141, 2142, 21= 43, - 2169, 2170, 2173, 2176, 2333, 4136, 6262, 20619, -}; - -static const unsigned short dep201[] =3D { - 41, 42, 100, 140, 141, 161, 165, 178, 186, 187, 188, 288, 2141, 2142, 21= 43, - 2169, 2170, 2173, 2176, 2333, 4136, 6263, 6264, 20619, -}; - -static const unsigned short dep202[] =3D { - 41, 42, 100, 161, 165, 178, 188, 288, 2141, 2142, 2143, 2169, 2170, 2173, - 2176, 2333, 4136, 10353, 20619, -}; - -static const unsigned short dep203[] =3D { - 41, 42, 100, 161, 165, 178, 188, 193, 194, 288, 2141, 2142, 2143, 2169, = 2170, - 2173, 2176, 2333, 4136, 6187, 20619, -}; - -static const unsigned short dep204[] =3D { - 80, 82, 83, 100, 101, 102, 103, 274, 275, 288, 289, 290, -}; - -static const unsigned short dep205[] =3D { - 41, 42, 81, 82, 86, 88, 100, 103, 105, 107, 110, 140, 141, 161, 165, 178, - 188, 193, 194, 195, 274, 276, 288, 289, 291, 2141, 2142, 2143, 2169, 217= 0, - 2173, 2176, 4136, 20619, -}; - -static const unsigned short dep206[] =3D { - 80, 82, 83, 84, 100, 101, 102, 103, 106, 274, 275, 277, 288, 289, 290, -}; - -static const unsigned short dep207[] =3D { - 41, 42, 81, 82, 84, 86, 88, 100, 103, 105, 106, 107, 110, 140, 141, 161,= 165, - 178, 188, 193, 194, 195, 274, 276, 277, 288, 289, 291, 2141, 2142, 2143,= 2169, - 2170, 2173, 2176, 4136, 20619, -}; - -static const unsigned short dep208[] =3D { - 80, 82, 83, 87, 88, 89, 100, 101, 102, 103, 274, 275, 280, 281, 288, 289, - 290, -}; - -static const unsigned short dep209[] =3D { - 41, 42, 81, 82, 86, 88, 100, 103, 105, 140, 141, 161, 165, 178, 188, 193, - 194, 195, 274, 276, 279, 281, 288, 289, 291, 2141, 2142, 2143, 2169, 217= 0, - 2173, 2176, 4136, 20619, -}; - -static const unsigned short dep210[] =3D { - 80, 82, 83, 100, 101, 102, 103, 109, 110, 111, 274, 275, 288, 289, 290, = 293, - 294, -}; - -static const unsigned short dep211[] =3D { - 41, 42, 81, 82, 100, 103, 105, 107, 110, 140, 141, 161, 165, 178, 188, 1= 93, - 194, 195, 274, 276, 288, 289, 291, 292, 294, 2141, 2142, 2143, 2169, 217= 0, - 2173, 2176, 4136, 20619, -}; - -static const unsigned short dep212[] =3D { - 41, 42, 47, 72, 100, 161, 165, 178, 188, 193, 194, 195, 288, 2141, 2142,= 2143, - 2169, 2170, 2173, 2176, 2333, 4136, 20619, -}; - -static const unsigned short dep213[] =3D { - 41, 42, 100, 161, 165, 178, 188, 193, 194, 195, 288, 2141, 2142, 2143, 2= 169, - 2170, 2173, 2176, 2333, 4136, 20619, -}; - -static const unsigned short dep214[] =3D { - 41, 42, 72, 80, 85, 87, 100, 140, 141, 156, 158, 161, 165, 178, 188, 193, - 194, 195, 288, 2141, 2142, 2143, 2169, 2170, 2173, 2176, 2333, 4136, 206= 19, -}; - -static const unsigned short dep215[] =3D { - 41, 42, 100, 161, 165, 167, 178, 188, 189, 191, 288, 2138, 2139, 2140, 2= 141, - 2142, 2143, 2169, 2170, 2173, 2176, 4136, 16531, 16533, 16534, 16536, 20= 619, -}; - -static const unsigned short dep216[] =3D { - 41, 42, 72, 80, 85, 87, 100, 156, 158, 161, 165, 178, 188, 195, 288, 214= 1, - 2142, 2143, 2169, 2170, 2173, 2176, 4136, 20619, -}; - -static const unsigned short dep217[] =3D { - 41, 42, 81, 82, 100, 103, 140, 141, 161, 165, 178, 188, 193, 194, 274, 2= 76, - 288, 289, 291, 2141, 2142, 2143, 2169, 2170, 2173, 2176, 4136, 20619, -}; - -static const unsigned short dep218[] =3D { - 41, 42, 72, 77, 79, 80, 85, 87, 100, 112, 114, 131, 132, 134, 135, 136, = 138, - 140, 141, 142, 143, 145, 146, 156, 158, 161, 165, 174, 176, 178, 188, 19= 3, - 194, 195, 288, 2141, 2142, 2143, 2169, 2170, 2173, 2176, 2333, 4136, 206= 19, -}; - -static const unsigned short dep219[] =3D { - 41, 42, 45, 72, 77, 79, 80, 85, 87, 100, 112, 114, 131, 132, 134, 135, 1= 36, - 138, 140, 141, 142, 143, 145, 146, 156, 158, 159, 161, 165, 174, 176, 17= 8, - 188, 193, 194, 195, 288, 2141, 2142, 2143, 2169, 2170, 2173, 2176, 2333,= 4136, - 20619, -}; - -static const unsigned short dep220[] =3D { - 0, 100, 198, 288, 2143, 2333, -}; - -static const unsigned short dep221[] =3D { - 0, 41, 42, 72, 77, 79, 80, 85, 87, 100, 112, 114, 131, 132, 134, 135, 13= 6, - 138, 140, 141, 142, 143, 145, 146, 156, 158, 161, 165, 174, 176, 178, 18= 8, - 193, 194, 195, 198, 288, 2141, 2142, 2143, 2169, 2170, 2173, 2176, 2333,= 4136, - 20619, -}; - -static const unsigned short dep222[] =3D { - 0, 41, 42, 45, 72, 77, 79, 80, 85, 87, 100, 112, 114, 131, 132, 134, 135, - 136, 138, 140, 141, 142, 143, 145, 146, 156, 158, 159, 161, 165, 174, 17= 6, - 178, 188, 193, 194, 195, 198, 288, 2141, 2142, 2143, 2169, 2170, 2173, 2= 176, - 2333, 4136, 20619, -}; - -static const unsigned short dep223[] =3D { - 32, 41, 42, 72, 77, 79, 80, 85, 87, 100, 112, 114, 131, 132, 134, 135, 1= 36, - 138, 140, 141, 142, 143, 145, 146, 156, 158, 161, 165, 174, 176, 178, 18= 8, - 193, 194, 195, 288, 2141, 2142, 2143, 2169, 2170, 2173, 2176, 2333, 4136, - 20619, -}; - -static const unsigned short dep224[] =3D { - 0, 100, 198, 288, 2333, 26718, -}; - -static const unsigned short dep225[] =3D { - 5, 100, 203, 288, 2143, 2333, -}; - -static const unsigned short dep226[] =3D { - 41, 42, 72, 77, 79, 80, 85, 87, 100, 112, 114, 131, 132, 134, 135, 136, = 138, - 140, 141, 142, 143, 145, 146, 156, 158, 161, 165, 174, 176, 178, 188, 19= 3, - 194, 195, 203, 288, 2141, 2142, 2143, 2169, 2170, 2173, 2176, 2333, 4136, - 20619, -}; - -static const unsigned short dep227[] =3D { - 0, 100, 112, 198, 288, 295, -}; - -static const unsigned short dep228[] =3D { - 0, 41, 42, 72, 77, 79, 80, 85, 87, 100, 114, 131, 132, 134, 135, 136, 13= 8, - 140, 141, 142, 143, 145, 146, 156, 158, 161, 165, 174, 176, 178, 188, 19= 3, - 194, 195, 198, 288, 295, 2141, 2142, 2143, 2169, 2170, 2173, 2176, 4136,= 20619, -}; - -static const unsigned short dep229[] =3D { - 0, 5, 41, 42, 72, 77, 79, 80, 85, 87, 100, 114, 131, 132, 134, 135, 136,= 138, - 140, 141, 142, 143, 145, 146, 156, 158, 161, 165, 174, 176, 178, 188, 19= 3, - 194, 195, 198, 288, 295, 2141, 2142, 2143, 2169, 2170, 2173, 2176, 4136,= 20619, -}; - -static const unsigned short dep230[] =3D { - 0, 32, 100, 112, 198, 238, 288, 295, -}; - -static const unsigned short dep231[] =3D { - 0, 41, 42, 72, 77, 79, 80, 85, 87, 100, 114, 131, 132, 134, 135, 136, 13= 8, - 140, 141, 142, 143, 145, 146, 156, 158, 161, 165, 174, 176, 178, 188, 19= 3, - 194, 195, 198, 238, 288, 295, 2141, 2142, 2143, 2169, 2170, 2173, 2176, = 4136, - 20619, -}; - -static const unsigned short dep232[] =3D { - 0, 100, 112, 198, 288, 295, 2143, 2333, -}; - -static const unsigned short dep233[] =3D { - 0, 3, 41, 42, 72, 77, 79, 80, 85, 87, 100, 112, 114, 131, 132, 134, 135,= 136, - 138, 140, 141, 142, 143, 145, 146, 156, 158, 161, 165, 174, 176, 178, 18= 8, - 193, 194, 195, 198, 288, 295, 2141, 2142, 2143, 2169, 2170, 2173, 2176, = 2333, - 4136, 20619, -}; - -static const unsigned short dep234[] =3D { - 0, 3, 5, 41, 42, 72, 77, 79, 80, 85, 87, 100, 112, 114, 131, 132, 134, 1= 35, - 136, 138, 140, 141, 142, 143, 145, 146, 156, 158, 161, 165, 174, 176, 17= 8, - 188, 193, 194, 195, 198, 288, 295, 2141, 2142, 2143, 2169, 2170, 2173, 2= 176, - 2333, 4136, 20619, -}; - -static const unsigned short dep235[] =3D { - 0, 41, 42, 72, 77, 79, 80, 85, 87, 100, 112, 114, 131, 132, 134, 135, 13= 6, - 138, 140, 141, 142, 143, 145, 146, 156, 158, 161, 165, 174, 176, 178, 18= 8, - 193, 194, 195, 198, 288, 295, 2141, 2142, 2143, 2169, 2170, 2173, 2176, = 2333, - 4136, 20619, -}; - -static const unsigned short dep236[] =3D { - 41, 42, 100, 161, 165, 178, 188, 288, 2138, 2139, 2140, 2169, 2170, 2173, - 2176, 2333, 4136, 16531, 16533, 16534, 16536, 20619, -}; - -static const unsigned short dep237[] =3D { - 0, 41, 42, 72, 77, 79, 80, 85, 87, 100, 114, 131, 132, 134, 135, 136, 13= 8, - 140, 141, 142, 143, 145, 146, 156, 158, 161, 165, 174, 176, 178, 188, 19= 3, - 194, 195, 198, 288, 295, 2141, 2142, 2143, 2169, 2170, 2173, 2176, 2333,= 4136, - 20619, -}; - -static const unsigned short dep238[] =3D { - 0, 32, 100, 112, 198, 238, 288, 295, 2143, 2333, -}; - -static const unsigned short dep239[] =3D { - 0, 41, 42, 72, 77, 79, 80, 85, 87, 100, 114, 131, 132, 134, 135, 136, 13= 8, - 140, 141, 142, 143, 145, 146, 156, 158, 161, 165, 174, 176, 178, 188, 19= 3, - 194, 195, 198, 238, 288, 295, 2141, 2142, 2143, 2169, 2170, 2173, 2176, = 2333, - 4136, 20619, -}; - -static const unsigned short dep240[] =3D { - 41, 42, 72, 77, 79, 80, 85, 87, 100, 112, 114, 131, 132, 134, 135, 136, = 138, - 140, 141, 142, 143, 145, 146, 156, 158, 161, 165, 174, 176, 178, 188, 19= 3, - 194, 195, 288, 2141, 2142, 2143, 2169, 2170, 2173, 2176, 2331, 4136, 165= 31, - 16533, 16534, 16536, 18767, 18769, 18770, 18772, 20619, -}; - -static const unsigned short dep241[] =3D { - 41, 42, 45, 72, 77, 79, 80, 85, 87, 100, 112, 114, 131, 132, 134, 135, 1= 36, - 138, 140, 141, 142, 143, 145, 146, 156, 158, 159, 161, 165, 174, 176, 17= 8, - 188, 193, 194, 195, 288, 2141, 2142, 2143, 2169, 2170, 2173, 2176, 2331,= 4136, - 16531, 16533, 16534, 16536, 18767, 18769, 18770, 18772, 20619, -}; - -static const unsigned short dep242[] =3D { - 0, 100, 198, 288, 2139, 2331, 18604, 18605, 18767, 18768, 18770, 18771, -}; - -static const unsigned short dep243[] =3D { - 0, 41, 42, 72, 77, 79, 80, 85, 87, 100, 112, 114, 131, 132, 134, 135, 13= 6, - 138, 140, 141, 142, 143, 145, 146, 156, 158, 161, 165, 174, 176, 178, 18= 8, - 193, 194, 195, 198, 288, 2141, 2142, 2143, 2169, 2170, 2173, 2176, 2331,= 4136, - 16531, 16533, 16534, 16536, 18767, 18769, 18770, 18772, 20619, -}; - -static const unsigned short dep244[] =3D { - 0, 41, 42, 45, 72, 77, 79, 80, 85, 87, 100, 112, 114, 131, 132, 134, 135, - 136, 138, 140, 141, 142, 143, 145, 146, 156, 158, 159, 161, 165, 174, 17= 6, - 178, 188, 193, 194, 195, 198, 288, 2141, 2142, 2143, 2169, 2170, 2173, 2= 176, - 2331, 4136, 16531, 16533, 16534, 16536, 18767, 18769, 18770, 18772, 2061= 9, -}; - -static const unsigned short dep245[] =3D { - 0, 100, 198, 288, 2140, 2331, 18604, 18605, 18767, 18768, 18770, 18771, -}; - -static const unsigned short dep246[] =3D { - 100, 288, 2139, 2143, 2331, 2333, 18604, 18605, 18767, 18768, 18770, 187= 71, -}; - -static const unsigned short dep247[] =3D { - 41, 42, 72, 77, 79, 80, 85, 87, 100, 112, 114, 131, 132, 134, 135, 136, = 138, - 140, 141, 142, 143, 145, 146, 156, 158, 161, 165, 174, 176, 178, 188, 19= 3, - 194, 195, 288, 2141, 2142, 2143, 2169, 2170, 2173, 2176, 2331, 2333, 413= 6, - 16531, 16533, 16534, 16536, 18767, 18769, 18770, 18772, 20619, -}; - -static const unsigned short dep248[] =3D { - 41, 42, 45, 72, 77, 79, 80, 85, 87, 100, 112, 114, 131, 132, 134, 135, 1= 36, - 138, 140, 141, 142, 143, 145, 146, 156, 158, 159, 161, 165, 174, 176, 17= 8, - 188, 193, 194, 195, 288, 2141, 2142, 2143, 2169, 2170, 2173, 2176, 2331,= 2333, - 4136, 16531, 16533, 16534, 16536, 18767, 18769, 18770, 18772, 20619, -}; - -static const unsigned short dep249[] =3D { - 0, 100, 198, 288, 2139, 2143, 2331, 2333, 18604, 18605, 18767, 18768, 18= 770, - 18771, -}; - -static const unsigned short dep250[] =3D { - 0, 41, 42, 72, 77, 79, 80, 85, 87, 100, 112, 114, 131, 132, 134, 135, 13= 6, - 138, 140, 141, 142, 143, 145, 146, 156, 158, 161, 165, 174, 176, 178, 18= 8, - 193, 194, 195, 198, 288, 2141, 2142, 2143, 2169, 2170, 2173, 2176, 2331,= 2333, - 4136, 16531, 16533, 16534, 16536, 18767, 18769, 18770, 18772, 20619, -}; - -static const unsigned short dep251[] =3D { - 0, 41, 42, 45, 72, 77, 79, 80, 85, 87, 100, 112, 114, 131, 132, 134, 135, - 136, 138, 140, 141, 142, 143, 145, 146, 156, 158, 159, 161, 165, 174, 17= 6, - 178, 188, 193, 194, 195, 198, 288, 2141, 2142, 2143, 2169, 2170, 2173, 2= 176, - 2331, 2333, 4136, 16531, 16533, 16534, 16536, 18767, 18769, 18770, 18772, - 20619, -}; - -static const unsigned short dep252[] =3D { - 0, 100, 198, 288, 2140, 2143, 2331, 2333, 18604, 18605, 18767, 18768, 18= 770, - 18771, -}; - -static const unsigned short dep253[] =3D { - 0, 41, 42, 72, 77, 79, 80, 85, 87, 100, 114, 131, 132, 134, 135, 136, 13= 8, - 140, 141, 142, 143, 145, 146, 156, 158, 161, 165, 174, 176, 178, 188, 19= 3, - 194, 195, 198, 288, 295, 2138, 2139, 2140, 2141, 2142, 2143, 2169, 2170,= 2173, - 2176, 4136, 16531, 16533, 16534, 16536, 20619, -}; - -static const unsigned short dep254[] =3D { - 41, 42, 72, 79, 80, 85, 87, 100, 140, 141, 142, 143, 145, 146, 156, 158,= 159, - 161, 165, 174, 176, 178, 188, 195, 288, 2169, 2170, 2173, 2176, 4136, -}; - -static const unsigned short dep255[] =3D { - 41, 42, 72, 79, 80, 85, 87, 100, 140, 141, 142, 143, 145, 146, 156, 158,= 159, - 161, 165, 174, 176, 178, 188, 195, 288, 2141, 2142, 2143, 2169, 2170, 21= 73, - 2176, 2333, 4136, 20619, -}; - -static const unsigned short dep256[] =3D { - 41, 42, 100, 161, 165, 178, 188, 288, 2141, 2142, 2143, 2169, 2170, 2173, - 2176, 2331, 4136, 16531, 16533, 16534, 16536, 18767, 18769, 18770, 18772, - 20619, -}; - -static const unsigned short dep257[] =3D { - 0, 41, 42, 72, 77, 79, 80, 85, 87, 100, 114, 131, 132, 134, 135, 136, 13= 8, - 140, 141, 142, 143, 145, 146, 156, 158, 161, 165, 174, 176, 178, 188, 19= 3, - 194, 195, 198, 288, 295, 2138, 2139, 2140, 2141, 2142, 2143, 2169, 2170,= 2173, - 2176, 2333, 4136, 16531, 16533, 16534, 16536, 20619, -}; - -static const unsigned short dep258[] =3D { - 1, 6, 39, 41, 42, 100, 140, 141, 161, 165, 167, 178, 188, 189, 191, 199,= 231, - 233, 245, 272, 288, 2169, 2171, 2172, 2174, 2175, 2177, 2178, 2290, 2292, - 4136, 28869, 29024, -}; - -static const unsigned short dep259[] =3D { - 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 2= 1, - 22, 24, 26, 27, 28, 29, 30, 31, 32, 100, 199, 200, 201, 202, 203, 204, 2= 05, - 206, 207, 208, 209, 210, 211, 212, 214, 215, 217, 218, 220, 221, 223, 22= 4, - 225, 226, 227, 228, 230, 233, 234, 235, 236, 237, 238, 272, 288, 2071, 2= 082, - 2143, 2277, 2288, 2333, 28869, 29024, -}; - -static const unsigned short dep260[] =3D { - 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 2= 1, - 22, 24, 25, 26, 28, 29, 30, 31, 32, 41, 42, 100, 140, 141, 161, 165, 178, - 183, 184, 188, 193, 194, 199, 200, 201, 202, 203, 204, 205, 206, 207, 20= 8, - 209, 210, 211, 212, 214, 215, 217, 218, 220, 221, 223, 224, 225, 226, 22= 7, - 228, 230, 232, 234, 235, 236, 237, 238, 272, 288, 2071, 2082, 2141, 2142, - 2143, 2169, 2170, 2173, 2176, 2277, 2288, 2333, 4136, 20619, 28869, 2902= 4, -}; - -#define NELS(X) (sizeof(X)/sizeof(X[0])) -static const struct ia64_opcode_dependency -op_dependencies[] =3D { - { NELS(dep1), dep1, NELS(dep0), dep0, }, - { NELS(dep3), dep3, NELS(dep2), dep2, }, - { NELS(dep5), dep5, NELS(dep4), dep4, }, - { NELS(dep7), dep7, NELS(dep6), dep6, }, - { NELS(dep9), dep9, NELS(dep8), dep8, }, - { NELS(dep11), dep11, NELS(dep10), dep10, }, - { NELS(dep13), dep13, NELS(dep12), dep12, }, - { NELS(dep15), dep15, NELS(dep14), dep14, }, - { NELS(dep17), dep17, NELS(dep16), dep16, }, - { NELS(dep19), dep19, NELS(dep18), dep18, }, - { NELS(dep21), dep21, NELS(dep20), dep20, }, - { NELS(dep23), dep23, NELS(dep22), dep22, }, - { NELS(dep25), dep25, NELS(dep24), dep24, }, - { NELS(dep27), dep27, NELS(dep26), dep26, }, - { NELS(dep29), dep29, NELS(dep28), dep28, }, - { NELS(dep30), dep30, NELS(dep12), dep12, }, - { NELS(dep32), dep32, NELS(dep31), dep31, }, - { NELS(dep34), dep34, NELS(dep33), dep33, }, - { NELS(dep35), dep35, NELS(dep12), dep12, }, - { NELS(dep37), dep37, NELS(dep36), dep36, }, - { NELS(dep39), dep39, NELS(dep38), dep38, }, - { NELS(dep41), dep41, NELS(dep40), dep40, }, - { NELS(dep42), dep42, NELS(dep31), dep31, }, - { NELS(dep43), dep43, NELS(dep33), dep33, }, - { NELS(dep45), dep45, NELS(dep44), dep44, }, - { NELS(dep47), dep47, NELS(dep46), dep46, }, - { NELS(dep49), dep49, NELS(dep48), dep48, }, - { NELS(dep51), dep51, NELS(dep50), dep50, }, - { NELS(dep53), dep53, NELS(dep52), dep52, }, - { NELS(dep55), dep55, NELS(dep54), dep54, }, - { NELS(dep57), dep57, NELS(dep56), dep56, }, - { NELS(dep59), dep59, NELS(dep58), dep58, }, - { NELS(dep61), dep61, NELS(dep60), dep60, }, - { NELS(dep63), dep63, NELS(dep62), dep62, }, - { NELS(dep65), dep65, NELS(dep64), dep64, }, - { NELS(dep67), dep67, NELS(dep66), dep66, }, - { NELS(dep68), dep68, NELS(dep33), dep33, }, - { NELS(dep70), dep70, NELS(dep69), dep69, }, - { NELS(dep72), dep72, NELS(dep71), dep71, }, - { NELS(dep74), dep74, NELS(dep73), dep73, }, - { NELS(dep76), dep76, NELS(dep75), dep75, }, - { NELS(dep77), dep77, NELS(dep33), dep33, }, - { NELS(dep79), dep79, NELS(dep78), dep78, }, - { NELS(dep81), dep81, NELS(dep80), dep80, }, - { NELS(dep83), dep83, NELS(dep82), dep82, }, - { NELS(dep84), dep84, NELS(dep33), dep33, }, - { NELS(dep85), dep85, NELS(dep33), dep33, }, - { NELS(dep86), dep86, NELS(dep33), dep33, }, - { NELS(dep87), dep87, NELS(dep33), dep33, }, - { NELS(dep89), dep89, NELS(dep88), dep88, }, - { NELS(dep91), dep91, NELS(dep90), dep90, }, - { NELS(dep93), dep93, NELS(dep92), dep92, }, - { NELS(dep95), dep95, NELS(dep94), dep94, }, - { NELS(dep97), dep97, NELS(dep96), dep96, }, - { NELS(dep99), dep99, NELS(dep98), dep98, }, - { NELS(dep101), dep101, NELS(dep100), dep100, }, - { NELS(dep103), dep103, NELS(dep102), dep102, }, - { NELS(dep105), dep105, NELS(dep104), dep104, }, - { NELS(dep107), dep107, NELS(dep106), dep106, }, - { NELS(dep109), dep109, NELS(dep108), dep108, }, - { NELS(dep111), dep111, NELS(dep110), dep110, }, - { NELS(dep113), dep113, NELS(dep112), dep112, }, - { NELS(dep115), dep115, NELS(dep114), dep114, }, - { NELS(dep117), dep117, NELS(dep116), dep116, }, - { NELS(dep119), dep119, NELS(dep118), dep118, }, - { NELS(dep121), dep121, NELS(dep120), dep120, }, - { NELS(dep122), dep122, NELS(dep64), dep64, }, - { NELS(dep123), dep123, NELS(dep33), dep33, }, - { NELS(dep125), dep125, NELS(dep124), dep124, }, - { NELS(dep126), dep126, NELS(dep0), dep0, }, - { NELS(dep128), dep128, NELS(dep127), dep127, }, - { NELS(dep130), dep130, NELS(dep129), dep129, }, - { NELS(dep131), dep131, NELS(dep0), dep0, }, - { NELS(dep132), dep132, NELS(dep0), dep0, }, - { NELS(dep134), dep134, NELS(dep133), dep133, }, - { NELS(dep135), dep135, NELS(dep0), dep0, }, - { NELS(dep136), dep136, NELS(dep2), dep2, }, - { NELS(dep137), dep137, NELS(dep4), dep4, }, - { NELS(dep138), dep138, NELS(dep6), dep6, }, - { NELS(dep139), dep139, NELS(dep8), dep8, }, - { NELS(dep140), dep140, NELS(dep10), dep10, }, - { 0, NULL, 0, NULL, }, - { NELS(dep141), dep141, NELS(dep33), dep33, }, - { NELS(dep143), dep143, NELS(dep142), dep142, }, - { NELS(dep144), dep144, NELS(dep142), dep142, }, - { NELS(dep146), dep146, NELS(dep145), dep145, }, - { NELS(dep147), dep147, NELS(dep145), dep145, }, - { NELS(dep148), dep148, NELS(dep142), dep142, }, - { NELS(dep150), dep150, NELS(dep149), dep149, }, - { NELS(dep152), dep152, NELS(dep151), dep151, }, - { NELS(dep154), dep154, NELS(dep153), dep153, }, - { NELS(dep156), dep156, NELS(dep155), dep155, }, - { NELS(dep158), dep158, NELS(dep157), dep157, }, - { NELS(dep159), dep159, NELS(dep157), dep157, }, - { NELS(dep160), dep160, NELS(dep0), dep0, }, - { NELS(dep162), dep162, NELS(dep161), dep161, }, - { NELS(dep164), dep164, NELS(dep163), dep163, }, - { NELS(dep166), dep166, NELS(dep165), dep165, }, - { NELS(dep168), dep168, NELS(dep167), dep167, }, - { NELS(dep170), dep170, NELS(dep169), dep169, }, - { NELS(dep171), dep171, NELS(dep0), dep0, }, - { NELS(dep172), dep172, NELS(dep0), dep0, }, - { NELS(dep173), dep173, NELS(dep0), dep0, }, - { NELS(dep174), dep174, NELS(dep33), dep33, }, - { NELS(dep176), dep176, NELS(dep175), dep175, }, - { NELS(dep177), dep177, NELS(dep175), dep175, }, - { NELS(dep179), dep179, NELS(dep178), dep178, }, - { NELS(dep181), dep181, NELS(dep180), dep180, }, - { NELS(dep183), dep183, NELS(dep182), dep182, }, - { NELS(dep185), dep185, NELS(dep184), dep184, }, - { NELS(dep187), dep187, NELS(dep186), dep186, }, - { NELS(dep189), dep189, NELS(dep188), dep188, }, - { NELS(dep191), dep191, NELS(dep190), dep190, }, - { NELS(dep193), dep193, NELS(dep192), dep192, }, - { NELS(dep195), dep195, NELS(dep194), dep194, }, - { NELS(dep196), dep196, NELS(dep0), dep0, }, - { NELS(dep197), dep197, NELS(dep0), dep0, }, - { NELS(dep198), dep198, NELS(dep0), dep0, }, - { NELS(dep199), dep199, NELS(dep0), dep0, }, - { NELS(dep200), dep200, NELS(dep0), dep0, }, - { NELS(dep201), dep201, NELS(dep0), dep0, }, - { NELS(dep202), dep202, NELS(dep0), dep0, }, - { NELS(dep203), dep203, NELS(dep0), dep0, }, - { NELS(dep205), dep205, NELS(dep204), dep204, }, - { NELS(dep207), dep207, NELS(dep206), dep206, }, - { NELS(dep209), dep209, NELS(dep208), dep208, }, - { NELS(dep211), dep211, NELS(dep210), dep210, }, - { NELS(dep212), dep212, NELS(dep0), dep0, }, - { NELS(dep213), dep213, NELS(dep0), dep0, }, - { NELS(dep214), dep214, NELS(dep0), dep0, }, - { NELS(dep215), dep215, NELS(dep33), dep33, }, - { NELS(dep216), dep216, NELS(dep33), dep33, }, - { NELS(dep217), dep217, NELS(dep204), dep204, }, - { NELS(dep218), dep218, NELS(dep0), dep0, }, - { NELS(dep219), dep219, NELS(dep0), dep0, }, - { NELS(dep221), dep221, NELS(dep220), dep220, }, - { NELS(dep222), dep222, NELS(dep220), dep220, }, - { NELS(dep223), dep223, NELS(dep0), dep0, }, - { NELS(dep221), dep221, NELS(dep224), dep224, }, - { NELS(dep226), dep226, NELS(dep225), dep225, }, - { NELS(dep228), dep228, NELS(dep227), dep227, }, - { NELS(dep229), dep229, NELS(dep227), dep227, }, - { NELS(dep231), dep231, NELS(dep230), dep230, }, - { NELS(dep233), dep233, NELS(dep232), dep232, }, - { NELS(dep234), dep234, NELS(dep232), dep232, }, - { NELS(dep235), dep235, NELS(dep232), dep232, }, - { NELS(dep236), dep236, NELS(dep0), dep0, }, - { NELS(dep237), dep237, NELS(dep232), dep232, }, - { NELS(dep239), dep239, NELS(dep238), dep238, }, - { NELS(dep240), dep240, NELS(dep64), dep64, }, - { NELS(dep241), dep241, NELS(dep64), dep64, }, - { NELS(dep243), dep243, NELS(dep242), dep242, }, - { NELS(dep244), dep244, NELS(dep242), dep242, }, - { NELS(dep243), dep243, NELS(dep245), dep245, }, - { NELS(dep247), dep247, NELS(dep246), dep246, }, - { NELS(dep248), dep248, NELS(dep246), dep246, }, - { NELS(dep250), dep250, NELS(dep249), dep249, }, - { NELS(dep251), dep251, NELS(dep249), dep249, }, - { NELS(dep250), dep250, NELS(dep252), dep252, }, - { NELS(dep253), dep253, NELS(dep227), dep227, }, - { NELS(dep254), dep254, NELS(dep33), dep33, }, - { NELS(dep255), dep255, NELS(dep0), dep0, }, - { NELS(dep256), dep256, NELS(dep64), dep64, }, - { NELS(dep257), dep257, NELS(dep232), dep232, }, - { NELS(dep258), dep258, NELS(dep31), dep31, }, - { NELS(dep260), dep260, NELS(dep259), dep259, }, -}; - -static const struct ia64_completer_table -completer_table[] =3D { - { 0x0, 0x0, 0, -1, -1, 0, 1, 0 }, - { 0x0, 0x0, 0, -1, -1, 0, 1, 0 }, - { 0x0, 0x0, 0, -1, -1, 0, 1, 0 }, - { 0x0, 0x0, 0, -1, -1, 0, 1, 0 }, - { 0x0, 0x0, 0, -1, -1, 0, 1, 0 }, - { 0x0, 0x0, 0, -1, -1, 0, 1, 0 }, - { 0x0, 0x0, 0, -1, -1, 0, 1, 0 }, - { 0x0, 0x0, 0, -1, -1, 0, 1, 0 }, - { 0x0, 0x0, 0, -1, -1, 0, 1, 97 }, - { 0x0, 0x0, 0, -1, -1, 0, 1, 97 }, - { 0x0, 0x0, 0, -1, -1, 0, 1, 0 }, - { 0x0, 0x0, 0, -1, -1, 0, 1, 0 }, - { 0x0, 0x0, 0, -1, -1, 0, 1, 0 }, - { 0x0, 0x0, 0, -1, -1, 0, 1, 0 }, - { 0x0, 0x0, 0, 628, -1, 0, 1, 6 }, - { 0x0, 0x0, 0, 691, -1, 0, 1, 18 }, - { 0x0, 0x0, 0, -1, -1, 0, 1, 81 }, - { 0x0, 0x0, 0, 790, -1, 0, 1, 18 }, - { 0x0, 0x0, 0, 3058, -1, 0, 1, 10 }, - { 0x0, 0x0, 0, -1, -1, 0, 1, 0 }, - { 0x0, 0x0, 0, -1, -1, 0, 1, 9 }, - { 0x0, 0x0, 0, -1, -1, 0, 1, 0 }, - { 0x0, 0x0, 0, -1, -1, 0, 1, 0 }, - { 0x0, 0x0, 0, -1, -1, 0, 1, 13 }, - { 0x1, 0x1, 0, -1, -1, 13, 1, 0 }, - { 0x0, 0x0, 0, -1, -1, 0, 1, 34 }, - { 0x0, 0x0, 0, 3279, -1, 0, 1, 30 }, - { 0x0, 0x0, 0, -1, -1, 0, 1, 30 }, - { 0x0, 0x0, 0, -1, -1, 0, 1, 30 }, - { 0x0, 0x0, 0, -1, -1, 0, 1, 34 }, - { 0x0, 0x0, 0, -1, -1, 0, 1, 34 }, - { 0x0, 0x0, 0, 1887, -1, 0, 1, 131 }, - { 0x0, 0x0, 0, -1, -1, 0, 1, 45 }, - { 0x0, 0x0, 0, -1, -1, 0, 1, 41 }, - { 0x0, 0x0, 0, -1, -1, 0, 1, 85 }, - { 0x0, 0x0, 0, 3111, -1, 0, 1, 30 }, - { 0x0, 0x0, 0, -1, -1, 0, 1, 30 }, - { 0x0, 0x0, 0, -1, -1, 0, 1, 30 }, - { 0x0, 0x0, 0, 3346, -1, 0, 1, 30 }, - { 0x0, 0x0, 0, 3115, -1, 0, 1, 30 }, - { 0x0, 0x0, 0, -1, -1, 0, 1, 34 }, - { 0x0, 0x0, 0, -1, -1, 0, 1, 34 }, - { 0x0, 0x0, 0, 3117, -1, 0, 1, 30 }, - { 0x0, 0x0, 0, 3355, -1, 0, 1, 30 }, - { 0x0, 0x0, 0, 3358, -1, 0, 1, 30 }, - { 0x0, 0x0, 0, -1, -1, 0, 1, 34 }, - { 0x0, 0x0, 0, -1, -1, 0, 1, 34 }, - { 0x0, 0x0, 0, -1, -1, 0, 1, 34 }, - { 0x0, 0x0, 0, -1, -1, 0, 1, 30 }, - { 0x0, 0x0, 0, -1, -1, 0, 1, 30 }, - { 0x0, 0x0, 0, -1, -1, 0, 1, 30 }, - { 0x0, 0x0, 0, -1, -1, 0, 1, 30 }, - { 0x0, 0x0, 0, -1, -1, 0, 1, 30 }, - { 0x0, 0x0, 0, 3380, -1, 0, 1, 30 }, - { 0x0, 0x0, 0, -1, -1, 0, 1, 30 }, - { 0x0, 0x0, 0, -1, -1, 0, 1, 34 }, - { 0x0, 0x0, 0, -1, -1, 0, 1, 34 }, - { 0x0, 0x0, 0, -1, -1, 0, 1, 30 }, - { 0x0, 0x0, 0, 3383, -1, 0, 1, 30 }, - { 0x0, 0x0, 0, -1, -1, 0, 1, 25 }, - { 0x0, 0x0, 0, -1, -1, 0, 1, 25 }, - { 0x0, 0x0, 0, -1, -1, 0, 1, 25 }, - { 0x0, 0x0, 0, -1, -1, 0, 1, 25 }, - { 0x0, 0x0, 0, -1, -1, 0, 1, 34 }, - { 0x0, 0x0, 0, -1, -1, 0, 1, 36 }, - { 0x0, 0x0, 0, 3391, -1, 0, 1, 30 }, - { 0x0, 0x0, 0, 2164, -1, 0, 1, 34 }, - { 0x0, 0x0, 0, -1, -1, 0, 1, 41 }, - { 0x0, 0x0, 0, -1, -1, 0, 1, 34 }, - { 0x0, 0x0, 0, -1, -1, 0, 1, 81 }, - { 0x0, 0x0, 0, -1, -1, 0, 1, 84 }, - { 0x0, 0x0, 0, 2212, -1, 0, 1, 133 }, - { 0x0, 0x0, 0, 2221, -1, 0, 1, 133 }, - { 0x0, 0x0, 0, 2230, -1, 0, 1, 133 }, - { 0x0, 0x0, 0, 2232, -1, 0, 1, 139 }, - { 0x0, 0x0, 0, 2234, -1, 0, 1, 139 }, - { 0x0, 0x0, 0, 2243, -1, 0, 1, 133 }, - { 0x0, 0x0, 0, 2252, -1, 0, 1, 133 }, - { 0x0, 0x0, 0, 2261, -1, 0, 1, 133 }, - { 0x0, 0x0, 0, 2270, -1, 0, 1, 133 }, - { 0x0, 0x0, 0, 2279, -1, 0, 1, 133 }, - { 0x0, 0x0, 0, 2288, -1, 0, 1, 133 }, - { 0x0, 0x0, 0, 2298, -1, 0, 1, 133 }, - { 0x0, 0x0, 0, 2308, -1, 0, 1, 133 }, - { 0x0, 0x0, 0, 2318, -1, 0, 1, 133 }, - { 0x0, 0x0, 0, 2327, -1, 0, 1, 149 }, - { 0x0, 0x0, 0, 2333, -1, 0, 1, 154 }, - { 0x0, 0x0, 0, 2339, -1, 0, 1, 154 }, - { 0x0, 0x0, 0, 2345, -1, 0, 1, 149 }, - { 0x0, 0x0, 0, 2351, -1, 0, 1, 154 }, - { 0x0, 0x0, 0, 2357, -1, 0, 1, 154 }, - { 0x0, 0x0, 0, 2363, -1, 0, 1, 149 }, - { 0x0, 0x0, 0, 2369, -1, 0, 1, 154 }, - { 0x0, 0x0, 0, 2375, -1, 0, 1, 154 }, - { 0x0, 0x0, 0, 2381, -1, 0, 1, 149 }, - { 0x0, 0x0, 0, 2387, -1, 0, 1, 154 }, - { 0x0, 0x0, 0, 2393, -1, 0, 1, 149 }, - { 0x0, 0x0, 0, 2399, -1, 0, 1, 154 }, - { 0x0, 0x0, 0, 2405, -1, 0, 1, 149 }, - { 0x0, 0x0, 0, 2411, -1, 0, 1, 154 }, - { 0x0, 0x0, 0, 2417, -1, 0, 1, 149 }, - { 0x0, 0x0, 0, 2423, -1, 0, 1, 154 }, - { 0x0, 0x0, 0, 2429, -1, 0, 1, 154 }, - { 0x0, 0x0, 0, 2430, -1, 0, 1, 160 }, - { 0x0, 0x0, 0, 2438, -1, 0, 1, 161 }, - { 0x0, 0x0, 0, 2442, -1, 0, 1, 161 }, - { 0x0, 0x0, 0, -1, -1, 0, 1, 86 }, - { 0x0, 0x0, 0, 271, -1, 0, 1, 41 }, - { 0x0, 0x0, 0, -1, -1, 0, 1, 0 }, - { 0x0, 0x0, 0, -1, -1, 0, 1, 0 }, - { 0x0, 0x0, 0, -1, -1, 0, 1, 34 }, - { 0x0, 0x0, 0, -1, -1, 0, 1, 68 }, - { 0x1, 0x1, 0, 1913, -1, 20, 1, 68 }, - { 0x0, 0x0, 0, -1, -1, 0, 1, 69 }, - { 0x0, 0x0, 0, -1, -1, 0, 1, 70 }, - { 0x0, 0x0, 0, -1, -1, 0, 1, 70 }, - { 0x0, 0x0, 0, -1, -1, 0, 1, 71 }, - { 0x0, 0x0, 0, -1, -1, 0, 1, 72 }, - { 0x0, 0x0, 0, -1, -1, 0, 1, 73 }, - { 0x0, 0x0, 0, -1, -1, 0, 1, 89 }, - { 0x0, 0x0, 0, -1, -1, 0, 1, 95 }, - { 0x0, 0x0, 0, -1, -1, 0, 1, 96 }, - { 0x0, 0x0, 0, -1, -1, 0, 1, 98 }, - { 0x0, 0x0, 0, -1, -1, 0, 1, 99 }, - { 0x0, 0x0, 0, -1, -1, 0, 1, 100 }, - { 0x0, 0x0, 0, -1, -1, 0, 1, 101 }, - { 0x0, 0x0, 0, -1, -1, 0, 1, 106 }, - { 0x0, 0x0, 0, -1, -1, 0, 1, 107 }, - { 0x0, 0x0, 0, -1, -1, 0, 1, 108 }, - { 0x0, 0x0, 0, -1, -1, 0, 1, 109 }, - { 0x0, 0x0, 0, -1, -1, 0, 1, 110 }, - { 0x0, 0x0, 0, -1, -1, 0, 1, 111 }, - { 0x0, 0x0, 0, -1, -1, 0, 1, 112 }, - { 0x0, 0x0, 0, -1, -1, 0, 1, 115 }, - { 0x0, 0x0, 0, -1, -1, 0, 1, 116 }, - { 0x0, 0x0, 0, -1, -1, 0, 1, 117 }, - { 0x0, 0x0, 0, -1, -1, 0, 1, 118 }, - { 0x0, 0x0, 0, -1, -1, 0, 1, 119 }, - { 0x0, 0x0, 0, -1, -1, 0, 1, 120 }, - { 0x0, 0x0, 0, -1, -1, 0, 1, 121 }, - { 0x0, 0x0, 0, -1, -1, 0, 1, 122 }, - { 0x0, 0x0, 0, -1, -1, 0, 1, 81 }, - { 0x0, 0x0, 0, -1, -1, 0, 1, 165 }, - { 0x0, 0x0, 0, -1, -1, 0, 1, 165 }, - { 0x0, 0x0, 0, -1, -1, 0, 1, 165 }, - { 0x0, 0x0, 0, -1, -1, 0, 1, 72 }, - { 0x0, 0x0, 0, -1, -1, 0, 1, 81 }, - { 0x0, 0x0, 0, -1, -1, 0, 1, 81 }, - { 0x0, 0x0, 0, -1, -1, 0, 1, 0 }, - { 0x0, 0x0, 0, -1, -1, 0, 1, 0 }, - { 0x0, 0x0, 0, -1, -1, 0, 1, 81 }, - { 0x0, 0x0, 0, -1, -1, 0, 1, 0 }, - { 0x0, 0x0, 0, -1, -1, 0, 1, 0 }, - { 0x0, 0x0, 0, 3741, -1, 0, 1, 0 }, - { 0x0, 0x0, 0, 3742, -1, 0, 1, 0 }, - { 0x0, 0x0, 0, -1, -1, 0, 1, 0 }, - { 0x0, 0x0, 0, 3070, -1, 0, 1, 0 }, - { 0x0, 0x0, 0, 3071, -1, 0, 1, 0 }, - { 0x0, 0x0, 0, -1, -1, 0, 1, 0 }, - { 0x0, 0x0, 0, -1, -1, 0, 1, 0 }, - { 0x0, 0x0, 0, -1, -1, 0, 1, 0 }, - { 0x0, 0x0, 0, -1, -1, 0, 1, 0 }, - { 0x0, 0x0, 0, 3756, -1, 0, 1, 0 }, - { 0x0, 0x0, 0, -1, -1, 0, 1, 0 }, - { 0x0, 0x0, 0, -1, -1, 0, 1, 0 }, - { 0x0, 0x0, 0, -1, -1, 0, 1, 0 }, - { 0x0, 0x0, 0, -1, -1, 0, 1, 0 }, - { 0x0, 0x0, 0, -1, -1, 0, 1, 0 }, - { 0x0, 0x0, 0, -1, -1, 0, 1, 0 }, - { 0x0, 0x0, 0, -1, -1, 0, 1, 0 }, - { 0x0, 0x0, 0, 3757, -1, 0, 1, 0 }, - { 0x0, 0x0, 0, 3758, -1, 0, 1, 0 }, - { 0x0, 0x0, 0, 3759, -1, 0, 1, 0 }, - { 0x0, 0x0, 0, 3760, -1, 0, 1, 0 }, - { 0x0, 0x0, 0, -1, -1, 0, 1, 0 }, - { 0x0, 0x0, 0, 3743, -1, 0, 1, 0 }, - { 0x0, 0x0, 0, 3744, -1, 0, 1, 0 }, - { 0x0, 0x0, 0, -1, -1, 0, 1, 0 }, - { 0x0, 0x0, 0, -1, -1, 0, 1, 11 }, - { 0x0, 0x0, 0, -1, -1, 0, 1, 93 }, - { 0x0, 0x0, 0, -1, -1, 0, 1, 91 }, - { 0x0, 0x0, 0, -1, -1, 0, 1, 0 }, - { 0x0, 0x0, 0, -1, -1, 0, 1, 0 }, - { 0x0, 0x0, 0, -1, -1, 0, 1, 0 }, - { 0x0, 0x0, 0, -1, -1, 0, 1, 0 }, - { 0x1, 0x1, 0, -1, -1, 13, 1, 0 }, - { 0x0, 0x0, 0, 3762, -1, 0, 1, 0 }, - { 0x0, 0x0, 0, -1, -1, 0, 1, 0 }, - { 0x0, 0x0, 0, -1, -1, 0, 1, 92 }, - { 0x0, 0x0, 0, 988, -1, 0, 1, 140 }, - { 0x0, 0x0, 0, 2828, -1, 0, 1, 147 }, - { 0x0, 0x0, 0, 990, -1, 0, 1, 141 }, - { 0x0, 0x0, 0, 992, -1, 0, 1, 141 }, - { 0x0, 0x0, 0, 994, -1, 0, 1, 140 }, - { 0x0, 0x0, 0, 2836, -1, 0, 1, 147 }, - { 0x0, 0x0, 0, 996, -1, 0, 1, 140 }, - { 0x0, 0x0, 0, 2840, -1, 0, 1, 147 }, - { 0x0, 0x0, 0, 999, -1, 0, 1, 140 }, - { 0x0, 0x0, 0, 2846, -1, 0, 1, 147 }, - { 0x0, 0x0, 0, 1001, -1, 0, 1, 159 }, - { 0x0, 0x0, 0, 2850, -1, 0, 1, 163 }, - { 0x0, 0x0, 0, 1002, -1, 0, 1, 159 }, - { 0x0, 0x0, 0, 2852, -1, 0, 1, 163 }, - { 0x0, 0x0, 0, 1003, -1, 0, 1, 159 }, - { 0x0, 0x0, 0, 2854, -1, 0, 1, 163 }, - { 0x0, 0x0, 0, 1004, -1, 0, 1, 159 }, - { 0x0, 0x0, 0, 2856, -1, 0, 1, 163 }, - { 0x0, 0x0, 0, -1, -1, 0, 1, 0 }, - { 0x0, 0x0, 0, -1, -1, 0, 1, 0 }, - { 0x0, 0x0, 0, -1, -1, 0, 1, 0 }, - { 0x0, 0x0, 0, -1, -1, 0, 1, 90 }, - { 0x0, 0x0, 0, -1, -1, 0, 1, 0 }, - { 0x0, 0x0, 0, -1, -1, 0, 1, 0 }, - { 0x0, 0x0, 0, -1, -1, 0, 1, 0 }, - { 0x0, 0x0, 0, -1, -1, 0, 1, 129 }, - { 0x0, 0x0, 0, -1, -1, 0, 1, 127 }, - { 0x0, 0x0, 0, -1, -1, 0, 1, 129 }, - { 0x0, 0x0, 0, -1, -1, 0, 1, 128 }, - { 0x0, 0x0, 0, 2461, -1, 0, 1, 145 }, - { 0x0, 0x0, 0, 2462, -1, 0, 1, 145 }, - { 0x0, 0x0, 0, 2463, -1, 0, 1, 145 }, - { 0x0, 0x0, 0, 2464, -1, 0, 1, 145 }, - { 0x0, 0x0, 0, -1, -1, 0, 1, 0 }, - { 0x0, 0x0, 0, -1, -1, 0, 1, 0 }, - { 0x0, 0x0, 0, -1, -1, 0, 1, 0 }, - { 0x0, 0x0, 0, -1, -1, 0, 1, 0 }, - { 0x0, 0x0, 0, -1, -1, 0, 1, 0 }, - { 0x0, 0x0, 1, 229, -1, 0, 1, 12 }, - { 0x0, 0x0, 1, 230, -1, 0, 1, 14 }, - { 0x1, 0x1, 2, -1, -1, 27, 1, 12 }, - { 0x1, 0x1, 2, -1, -1, 27, 1, 14 }, - { 0x0, 0x0, 3, -1, 2087, 0, 0, -1 }, - { 0x0, 0x0, 3, -1, 2088, 0, 0, -1 }, - { 0x1, 0x1, 3, 3622, 2205, 33, 1, 135 }, - { 0x0, 0x0, 3, 3623, 909, 0, 0, -1 }, - { 0x1, 0x1, 3, 3624, 2214, 33, 1, 135 }, - { 0x1, 0x1, 3, 3625, 2223, 33, 1, 135 }, - { 0x1, 0x1, 3, 3626, 2236, 33, 1, 135 }, - { 0x0, 0x0, 3, 3627, 922, 0, 0, -1 }, - { 0x1, 0x1, 3, 3628, 2245, 33, 1, 135 }, - { 0x1, 0x1, 3, 3629, 2254, 33, 1, 135 }, - { 0x1, 0x1, 3, 3630, 2263, 33, 1, 135 }, - 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33, 1, 151 }, - { 0x1, 0x1, 3, 3655, 2407, 33, 1, 156 }, - { 0x1, 0x1, 3, 3656, 2413, 33, 1, 151 }, - { 0x0, 0x0, 3, 3657, 969, 0, 0, -1 }, - { 0x1, 0x1, 3, 3658, 2419, 33, 1, 156 }, - { 0x1, 0x1, 3, 3659, 2425, 33, 1, 156 }, - { 0x1, 0x1, 3, -1, -1, 27, 1, 41 }, - { 0x0, 0x0, 4, 3072, 2180, 0, 1, 144 }, - { 0x0, 0x0, 4, 3073, 2182, 0, 1, 144 }, - { 0x0, 0x0, 4, 3074, 2184, 0, 1, 143 }, - { 0x0, 0x0, 4, 3075, 2186, 0, 1, 143 }, - { 0x0, 0x0, 4, 3076, 2188, 0, 1, 143 }, - { 0x0, 0x0, 4, 3077, 2190, 0, 1, 143 }, - { 0x0, 0x0, 4, 3078, 2192, 0, 1, 143 }, - { 0x0, 0x0, 4, 3079, 2194, 0, 1, 143 }, - { 0x0, 0x0, 4, 3080, 2196, 0, 1, 143 }, - { 0x0, 0x0, 4, 3081, 2198, 0, 1, 143 }, - { 0x0, 0x0, 4, 3082, 2200, 0, 1, 145 }, - { 0x0, 0x0, 4, 3083, 2202, 0, 1, 145 }, - { 0x1, 0x1, 4, -1, 2209, 33, 1, 138 }, - { 0x5, 0x5, 4, 578, 2208, 32, 1, 133 }, - { 0x0, 0x0, 4, -1, 913, 0, 0, -1 }, - { 0x0, 0x0, 4, 579, 912, 0, 0, -1 }, - { 0x1, 0x1, 4, -1, 2218, 33, 1, 138 }, - { 0x5, 0x5, 4, 580, 2217, 32, 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1, 66 }, - { 0x3, 0x3, 235, -1, -1, 34, 1, 33 }, - { 0x3, 0x3, 235, 3113, -1, 34, 1, 33 }, - { 0x7, 0x7, 235, -1, -1, 34, 1, 66 }, - { 0xb, 0xb, 235, -1, -1, 34, 1, 33 }, - { 0x3, 0x3, 235, 3114, -1, 34, 1, 33 }, - { 0x7, 0x7, 235, -1, -1, 34, 1, 66 }, - { 0xb, 0xb, 235, -1, -1, 34, 1, 33 }, - { 0x3, 0x3, 235, 3116, -1, 34, 1, 33 }, - { 0x3, 0x3, 235, -1, -1, 34, 1, 66 }, - { 0x3, 0x3, 235, -1, -1, 34, 1, 33 }, - { 0x3, 0x3, 235, 3118, -1, 34, 1, 33 }, - { 0x3, 0x3, 235, -1, -1, 34, 1, 66 }, - { 0x3, 0x3, 235, -1, -1, 34, 1, 33 }, - { 0x3, 0x3, 235, 3119, -1, 34, 1, 33 }, - { 0x3, 0x3, 235, -1, -1, 34, 1, 33 }, - { 0x3, 0x3, 235, -1, -1, 34, 1, 33 }, - { 0x3, 0x3, 235, -1, -1, 34, 1, 53 }, - { 0x181, 0x181, 235, -1, -1, 27, 1, 53 }, - { 0xc1, 0xc1, 235, -1, -1, 28, 1, 53 }, - { 0x183, 0x183, 235, -1, -1, 27, 1, 53 }, - { 0x61, 0x61, 235, -1, -1, 29, 1, 53 }, - { 0x185, 0x185, 235, -1, -1, 27, 1, 53 }, - { 0xc3, 0xc3, 235, -1, -1, 28, 1, 53 }, - { 0x187, 0x187, 235, -1, -1, 27, 1, 53 }, - { 0x3, 0x3, 235, -1, -1, 34, 1, 53 }, - { 0x3, 0x3, 235, -1, -1, 34, 1, 53 }, - { 0x3, 0x3, 235, -1, -1, 34, 1, 53 }, - { 0x3, 0x3, 235, -1, -1, 34, 1, 53 }, - { 0xc1, 0xc1, 235, -1, -1, 28, 1, 33 }, - { 0x3, 0x3, 235, 3749, -1, 34, 1, 33 }, - { 0x183, 0x183, 235, -1, -1, 27, 1, 33 }, - { 0x181, 0x181, 235, 3750, -1, 27, 1, 33 }, - { 0x3, 0x3, 235, -1, -1, 34, 1, 33 }, - { 0x3, 0x3, 235, -1, -1, 34, 1, 33 }, - { 0x3, 0x3, 235, -1, -1, 34, 1, 33 }, - { 0x3, 0x3, 235, -1, -1, 34, 1, 33 }, - { 0x3, 0x3, 235, -1, -1, 34, 1, 33 }, - { 0x3, 0x3, 235, -1, -1, 34, 1, 33 }, - { 0x3, 0x3, 235, -1, -1, 34, 1, 33 }, - { 0x3, 0x3, 235, -1, -1, 34, 1, 28 }, - { 0x3, 0x3, 235, -1, -1, 34, 1, 28 }, - { 0x3, 0x3, 235, -1, -1, 34, 1, 28 }, - { 0x3, 0x3, 235, -1, -1, 34, 1, 28 }, - { 0x3, 0x3, 235, -1, -1, 34, 1, 39 }, - { 0x3, 0x3, 235, -1, -1, 34, 1, 66 }, - { 0x3, 0x3, 235, -1, -1, 34, 1, 33 }, - { 0x3, 0x3, 235, 3121, -1, 34, 1, 33 }, - { 0x3, 0x3, 236, 562, 2206, 32, 1, 136 }, - { 0x0, 0x0, 236, 563, 910, 0, 0, -1 }, - { 0x3, 0x3, 236, 564, 2215, 32, 1, 136 }, - { 0x3, 0x3, 236, 565, 2224, 32, 1, 136 }, - { 0x3, 0x3, 236, 566, 2237, 32, 1, 136 }, - { 0x0, 0x0, 236, 567, 923, 0, 0, -1 }, - { 0x3, 0x3, 236, 568, 2246, 32, 1, 136 }, - { 0x3, 0x3, 236, 569, 2255, 32, 1, 136 }, - { 0x3, 0x3, 236, 570, 2264, 32, 1, 136 }, - { 0x0, 0x0, 236, 571, 932, 0, 0, -1 }, - { 0x3, 0x3, 236, 572, 2273, 32, 1, 136 }, - { 0x3, 0x3, 236, 573, 2282, 32, 1, 136 }, - { 0x3, 0x3, 236, 574, 2291, 32, 1, 136 }, - { 0x0, 0x0, 236, 575, 941, 0, 0, -1 }, - { 0x3, 0x3, 236, 576, 2301, 32, 1, 136 }, - { 0x3, 0x3, 236, 577, 2311, 32, 1, 136 }, - { 0x3, 0x3, 236, 594, 2324, 32, 1, 152 }, - { 0x0, 0x0, 236, 595, 952, 0, 0, -1 }, - { 0x3, 0x3, 236, 596, 2330, 32, 1, 157 }, - { 0x3, 0x3, 236, 597, 2336, 32, 1, 157 }, - { 0x3, 0x3, 236, 598, 2342, 32, 1, 152 }, - { 0x0, 0x0, 236, 599, 958, 0, 0, -1 }, - { 0x3, 0x3, 236, 600, 2348, 32, 1, 157 }, - { 0x3, 0x3, 236, 601, 2354, 32, 1, 157 }, - { 0x3, 0x3, 236, 602, 2360, 32, 1, 152 }, - { 0x0, 0x0, 236, 603, 964, 0, 0, -1 }, - { 0x3, 0x3, 236, 604, 2366, 32, 1, 157 }, - { 0x3, 0x3, 236, 605, 2372, 32, 1, 157 }, - { 0x3, 0x3, 236, 606, 2378, 32, 1, 152 }, - { 0x3, 0x3, 236, 607, 2384, 32, 1, 157 }, - { 0x3, 0x3, 236, 608, 2390, 32, 1, 152 }, - { 0x3, 0x3, 236, 609, 2396, 32, 1, 157 }, - { 0x3, 0x3, 236, 610, 2402, 32, 1, 152 }, - { 0x3, 0x3, 236, 611, 2408, 32, 1, 157 }, - { 0x3, 0x3, 236, 612, 2414, 32, 1, 152 }, - { 0x0, 0x0, 236, 613, 970, 0, 0, -1 }, - { 0x3, 0x3, 236, 614, 2420, 32, 1, 157 }, - { 0x3, 0x3, 236, 615, 2426, 32, 1, 157 }, - { 0x1, 0x1, 237, -1, -1, 28, 1, 34 }, - { 0x1, 0x1, 237, -1, -1, 28, 1, 34 }, - { 0x0, 0x0, 244, 1700, -1, 0, 1, 146 }, - { 0x0, 0x0, 244, 1701, -1, 0, 1, 162 }, - { 0x1, 0x1, 245, -1, 998, 33, 1, 142 }, - { 0x0, 0x0, 245, -1, 2454, 0, 0, -1 }, - { 0x1, 0x1, 245, -1, 2845, 33, 1, 148 }, - { 0x0, 0x0, 245, -1, 1000, 0, 1, 159 }, - { 0x0, 0x0, 245, -1, 2456, 0, 0, -1 }, - { 0x0, 0x0, 245, -1, 2848, 0, 1, 163 }, - { 0x0, 0x0, 246, 1619, 1716, 0, 0, -1 }, - { 0x0, 0x0, 246, 1620, 1724, 0, 0, -1 }, - { 0x0, 0x0, 246, 1621, 1720, 0, 0, -1 }, - { 0x1, 0x1, 246, 1622, 654, 33, 1, 6 }, - { 0x8000001, 0x8000001, 246, 1623, 662, 6, 1, 7 }, - { 0x1, 0x1, 246, 1624, 658, 33, 1, 6 }, - { 0x0, 0x0, 246, 1625, 1728, 0, 0, -1 }, - { 0x1, 0x1, 246, 1626, 674, 33, 1, 8 }, - { 0x0, 0x0, 246, 1627, 1732, 0, 0, -1 }, - { 0x1, 0x1, 246, 1628, 686, 33, 1, 16 }, - { 0x0, 0x0, 246, 1629, 1737, 0, 0, -1 }, - { 0x0, 0x0, 246, 1630, 1741, 0, 0, -1 }, - { 0x1, 0x1, 246, 1631, 709, 33, 1, 18 }, - { 0x1, 0x1, 246, 1632, 713, 33, 1, 18 }, - { 0x0, 0x0, 246, 1633, 1745, 0, 0, -1 }, - { 0x0, 0x0, 246, 1634, 1749, 0, 0, -1 }, - { 0x1, 0x1, 246, 1635, 733, 33, 1, 19 }, - { 0x8000001, 0x8000001, 246, 1636, 737, 6, 1, 19 }, - { 0x0, 0x0, 246, 1637, 1753, 0, 0, -1 }, - { 0x1, 0x1, 246, 1638, 749, 33, 1, 20 }, - { 0x0, 0x0, 246, 1639, 1757, 0, 0, -1 }, - { 0x0, 0x0, 246, 1640, 1761, 0, 0, -1 }, - { 0x1, 0x1, 246, 1641, 769, 33, 1, 21 }, - { 0x8000001, 0x8000001, 246, 1642, 773, 6, 1, 21 }, - { 0x0, 0x0, 246, 1643, 1765, 0, 0, -1 }, - { 0x1, 0x1, 246, 1644, 785, 33, 1, 22 }, - { 0x0, 0x0, 246, 1645, 1770, 0, 0, -1 }, - { 0x0, 0x0, 246, 1646, 1774, 0, 0, -1 }, - { 0x1, 0x1, 246, 1647, 808, 33, 1, 18 }, - { 0x1, 0x1, 246, 1648, 812, 33, 1, 18 }, - { 0x0, 0x0, 246, 1649, 1778, 0, 0, -1 }, - { 0x1, 0x1, 246, 1650, 824, 33, 1, 164 }, - { 0x0, 0x0, 247, 3670, 1715, 0, 0, -1 }, - { 0x0, 0x0, 247, 3671, 1723, 0, 0, -1 }, - { 0x0, 0x0, 247, 3672, 1719, 0, 0, -1 }, - { 0x0, 0x0, 247, 3673, 653, 0, 1, 6 }, - { 0x1, 0x1, 247, 3674, 661, 6, 1, 7 }, - { 0x0, 0x0, 247, 3675, 657, 0, 1, 6 }, - { 0x0, 0x0, 247, 3676, 1727, 0, 0, -1 }, - { 0x0, 0x0, 247, 3677, 673, 0, 1, 8 }, - { 0x0, 0x0, 247, 3678, 1731, 0, 0, -1 }, - { 0x0, 0x0, 247, 3679, 685, 0, 1, 16 }, - { 0x0, 0x0, 247, 3680, 1736, 0, 0, -1 }, - { 0x0, 0x0, 247, 3681, 1740, 0, 0, -1 }, - { 0x0, 0x0, 247, 3682, 708, 0, 1, 18 }, - { 0x0, 0x0, 247, 3683, 712, 0, 1, 18 }, - { 0x0, 0x0, 247, 3684, 1744, 0, 0, -1 }, - { 0x0, 0x0, 247, 3685, 1748, 0, 0, -1 }, - { 0x0, 0x0, 247, 3686, 732, 0, 1, 19 }, - { 0x1, 0x1, 247, 3687, 736, 6, 1, 19 }, - { 0x0, 0x0, 247, 3688, 1752, 0, 0, -1 }, - { 0x0, 0x0, 247, 3689, 748, 0, 1, 20 }, - { 0x0, 0x0, 247, 3690, 1756, 0, 0, -1 }, - { 0x0, 0x0, 247, 3691, 1760, 0, 0, -1 }, - { 0x0, 0x0, 247, 3692, 768, 0, 1, 21 }, - { 0x1, 0x1, 247, 3693, 772, 6, 1, 21 }, - { 0x0, 0x0, 247, 3694, 1764, 0, 0, -1 }, - { 0x0, 0x0, 247, 3695, 784, 0, 1, 22 }, - { 0x0, 0x0, 247, 3696, 1769, 0, 0, -1 }, - { 0x0, 0x0, 247, 3697, 1773, 0, 0, -1 }, - { 0x0, 0x0, 247, 3698, 807, 0, 1, 18 }, - { 0x0, 0x0, 247, 3699, 811, 0, 1, 18 }, - { 0x0, 0x0, 247, 3700, 1777, 0, 0, -1 }, - { 0x0, 0x0, 247, 3701, 823, 0, 1, 164 }, - { 0x1, 0x1, 247, 1651, 1902, 27, 1, 17 }, - { 0x0, 0x0, 247, 1652, 1900, 0, 1, 17 }, - { 0x0, 0x0, 247, 1967, 1904, 0, 1, 23 }, - { 0x0, 0x1, 247, 1912, 1910, 20, 1, 68 }, - { 0x0, 0x0, 247, 112, 1908, 0, 1, 68 }, - { 0x1, 0x1, 250, -1, -1, 29, 1, 0 }, - { 0x0, 0x0, 250, -1, -1, 0, 1, 0 }, - { 0x1, 0x1, 250, 3905, -1, 27, 1, 0 }, - { 0x1, 0x1, 250, 3906, -1, 27, 1, 0 }, - { 0x1, 0x1, 250, 3907, -1, 27, 1, 0 }, - { 0x1, 0x1, 250, 3908, -1, 27, 1, 0 }, - { 0x0, 0x0, 273, -1, 3217, 0, 0, -1 }, - { 0x0, 0x0, 273, -1, 3219, 0, 0, -1 }, - { 0x1, 0x1, 273, -1, -1, 28, 1, 30 }, - { 0x1, 0x1, 273, -1, -1, 28, 1, 30 }, - { 0x0, 0x0, 273, -1, 3258, 0, 0, -1 }, - { 0x0, 0x0, 273, -1, 3260, 0, 0, -1 }, - { 0x1, 0x1, 273, -1, -1, 28, 1, 30 }, - { 0x1, 0x1, 273, -1, -1, 28, 1, 30 }, - { 0x0, 0x0, 275, 24, -1, 0, 1, 0 }, - { 0x0, 0x0, 275, -1, -1, 0, 1, 0 }, - { 0x0, 0x0, 275, -1, -1, 0, 1, 0 }, - { 0x0, 0x1, 275, -1, -1, 29, 1, 0 }, - { 0x0, 0x1, 275, -1, -1, 29, 1, 0 }, - { 0x0, 0x1, 275, -1, -1, 29, 1, 0 }, - { 0x0, 0x1, 275, -1, -1, 29, 1, 0 }, - { 0x0, 0x1, 275, -1, -1, 29, 1, 0 }, - { 0x0, 0x0, 275, 185, -1, 0, 1, 0 }, - { 0x0, 0x1, 275, -1, -1, 29, 1, 0 }, - { 0x1, 0x1, 276, -1, -1, 12, 1, 2 }, - { 0x1, 0x1, 276, -1, -1, 12, 1, 2 }, - { 0x1, 0x1, 276, -1, -1, 12, 1, 2 }, - { 0x1, 0x1, 276, -1, -1, 12, 1, 2 }, - { 0x1, 0x1, 276, -1, -1, 12, 1, 2 }, - { 0x1, 0x1, 276, -1, -1, 12, 1, 2 }, - { 0x1, 0x1, 276, -1, -1, 12, 1, 2 }, - { 0x1, 0x1, 276, -1, -1, 12, 1, 2 }, - { 0x1, 0x1, 276, -1, -1, 12, 1, 2 }, - { 0x1, 0x1, 276, -1, -1, 12, 1, 2 }, - { 0x1, 0x1, 276, -1, -1, 12, 1, 2 }, - { 0x1, 0x1, 276, -1, -1, 12, 1, 2 }, - { 0x1, 0x1, 276, -1, -1, 12, 1, 2 }, - { 0x1, 0x1, 276, -1, -1, 12, 1, 2 }, - { 0x1, 0x1, 276, -1, -1, 12, 1, 2 }, - { 0x1, 0x1, 276, -1, -1, 12, 1, 2 }, - { 0x1, 0x1, 276, -1, -1, 12, 1, 2 }, - { 0x1, 0x1, 276, -1, -1, 12, 1, 2 }, - { 0x1, 0x1, 276, -1, -1, 12, 1, 2 }, - { 0x1, 0x1, 276, 323, -1, 12, 1, 2 }, - { 0x1, 0x1, 276, -1, -1, 12, 1, 2 }, - { 0x1, 0x1, 276, -1, -1, 12, 1, 2 }, - { 0x1, 0x1, 276, -1, -1, 12, 1, 2 }, - { 0x1, 0x1, 276, -1, -1, 12, 1, 2 }, - { 0x1, 0x1, 276, -1, -1, 12, 1, 2 }, - { 0x1, 0x1, 276, -1, -1, 12, 1, 2 }, - { 0x1, 0x1, 276, -1, -1, 12, 1, 2 }, - { 0x1, 0x1, 276, -1, -1, 12, 1, 2 }, - { 0x1, 0x1, 276, -1, -1, 12, 1, 2 }, - { 0x1, 0x1, 276, -1, -1, 12, 1, 2 }, - { 0x1, 0x1, 276, -1, -1, 12, 1, 2 }, - { 0x1, 0x1, 276, -1, -1, 12, 1, 2 }, - { 0x1, 0x1, 276, -1, -1, 12, 1, 2 }, - { 0x1, 0x1, 276, -1, -1, 12, 1, 2 }, - { 0x1, 0x1, 276, -1, -1, 12, 1, 2 }, - { 0x1, 0x1, 276, 345, -1, 12, 1, 2 }, - { 0x1, 0x1, 276, -1, -1, 12, 1, 2 }, - { 0x1, 0x1, 276, -1, -1, 12, 1, 2 }, - { 0x1, 0x1, 276, -1, -1, 12, 1, 2 }, - { 0x1, 0x1, 276, -1, -1, 12, 1, 2 }, - { 0x1, 0x1, 276, -1, -1, 12, 1, 2 }, - { 0x1, 0x1, 276, -1, -1, 12, 1, 2 }, - { 0x1, 0x1, 276, -1, -1, 12, 1, 2 }, - { 0x1, 0x1, 276, -1, -1, 12, 1, 2 }, - { 0x1, 0x1, 276, -1, -1, 12, 1, 2 }, - { 0x1, 0x1, 276, -1, -1, 12, 1, 2 }, - { 0x1, 0x1, 276, -1, -1, 12, 1, 2 }, - { 0x1, 0x1, 276, -1, -1, 12, 1, 2 }, - { 0x1, 0x1, 276, -1, -1, 12, 1, 2 }, - { 0x1, 0x1, 276, -1, -1, 12, 1, 2 }, - { 0x1, 0x1, 276, -1, -1, 12, 1, 2 }, - { 0x1, 0x1, 276, -1, -1, 12, 1, 2 }, - { 0x1, 0x1, 276, -1, -1, 12, 1, 2 }, - { 0x1, 0x1, 276, -1, -1, 12, 1, 2 }, - { 0x1, 0x1, 276, -1, -1, 12, 1, 2 }, - { 0x1, 0x1, 276, -1, -1, 12, 1, 2 }, - { 0x1, 0x1, 276, -1, -1, 12, 1, 2 }, - { 0x1, 0x1, 276, -1, -1, 12, 1, 2 }, - { 0x1, 0x1, 276, -1, -1, 12, 1, 2 }, - { 0x1, 0x1, 276, 371, -1, 12, 1, 2 }, - { 0x1, 0x1, 276, -1, -1, 12, 1, 2 }, - { 0x1, 0x1, 276, -1, -1, 12, 1, 2 }, - { 0x1, 0x1, 276, -1, -1, 12, 1, 2 }, - { 0x1, 0x1, 276, -1, -1, 12, 1, 2 }, - { 0x1, 0x1, 276, -1, -1, 12, 1, 2 }, - { 0x1, 0x1, 276, -1, -1, 12, 1, 2 }, - { 0x1, 0x1, 276, -1, -1, 12, 1, 2 }, - { 0x1, 0x1, 276, -1, -1, 12, 1, 2 }, - { 0x1, 0x1, 276, -1, -1, 12, 1, 2 }, - { 0x1, 0x1, 276, -1, -1, 12, 1, 2 }, - { 0x1, 0x1, 276, -1, -1, 12, 1, 2 }, - { 0x1, 0x1, 276, 393, -1, 12, 1, 2 }, - { 0x1, 0x1, 276, -1, -1, 12, 1, 2 }, - { 0x1, 0x1, 276, -1, -1, 12, 1, 2 }, - { 0x1, 0x1, 276, -1, -1, 12, 1, 2 }, - { 0x1, 0x1, 276, -1, -1, 12, 1, 2 }, - { 0x1, 0x1, 276, -1, -1, 12, 1, 2 }, - { 0x1, 0x1, 276, -1, -1, 12, 1, 2 }, - { 0x1, 0x1, 276, -1, -1, 12, 1, 2 }, - { 0x1, 0x1, 276, -1, -1, 12, 1, 2 }, - { 0x1, 0x1, 276, -1, -1, 12, 1, 65 }, - { 0x1, 0x1, 276, -1, -1, 12, 1, 65 }, - { 0x1, 0x1, 276, -1, -1, 12, 1, 65 }, - { 0x1, 0x1, 276, -1, -1, 12, 1, 65 }, - { 0x0, 0x0, 276, -1, 3169, 0, 0, -1 }, - { 0x0, 0x0, 276, -1, 3171, 0, 0, -1 }, - { 0x0, 0x0, 276, -1, 3173, 0, 0, -1 }, - { 0x0, 0x0, 276, -1, 3175, 0, 0, -1 }, - { 0x1, 0x1, 276, -1, 3177, 12, 1, 60 }, - { 0x1, 0x1, 276, -1, 3179, 12, 1, 60 }, - { 0x1, 0x1, 276, -1, 3181, 12, 1, 60 }, - { 0x1, 0x1, 276, -1, 3183, 12, 1, 50 }, - { 0x1, 0x1, 276, -1, -1, 12, 1, 60 }, - { 0x1, 0x1, 276, -1, -1, 12, 1, 60 }, - { 0x1, 0x1, 276, -1, -1, 12, 1, 60 }, - { 0x1, 0x1, 276, -1, -1, 12, 1, 50 }, - { 0x0, 0x0, 276, -1, 3185, 0, 0, -1 }, - { 0x0, 0x0, 276, -1, 3187, 0, 0, -1 }, - { 0x1, 0x1, 276, -1, 3189, 12, 1, 60 }, - { 0x1, 0x1, 276, -1, 3191, 12, 1, 60 }, - { 0x1, 0x1, 276, -1, -1, 12, 1, 60 }, - { 0x1, 0x1, 276, -1, -1, 12, 1, 60 }, - { 0x0, 0x0, 276, -1, 3193, 0, 0, -1 }, - { 0x0, 0x0, 276, -1, 3195, 0, 0, -1 }, - { 0x0, 0x0, 276, -1, 3197, 0, 0, -1 }, - { 0x0, 0x0, 276, -1, 3199, 0, 0, -1 }, - { 0x1, 0x1, 276, -1, 3201, 12, 1, 60 }, - { 0x1, 0x1, 276, -1, 3203, 12, 1, 60 }, - { 0x1, 0x1, 276, -1, 3205, 12, 1, 60 }, - { 0x1, 0x1, 276, -1, 3207, 12, 1, 50 }, - { 0x1, 0x1, 276, -1, -1, 12, 1, 60 }, - { 0x1, 0x1, 276, -1, -1, 12, 1, 60 }, - { 0x1, 0x1, 276, -1, -1, 12, 1, 60 }, - { 0x1, 0x1, 276, -1, -1, 12, 1, 50 }, - { 0x0, 0x0, 276, -1, 3209, 0, 0, -1 }, - { 0x0, 0x0, 276, -1, 3211, 0, 0, -1 }, - { 0x1, 0x1, 276, -1, 3213, 12, 1, 60 }, - { 0x1, 0x1, 276, -1, 3215, 12, 1, 60 }, - { 0x1, 0x1, 276, -1, -1, 12, 1, 60 }, - { 0x1, 0x1, 276, -1, -1, 12, 1, 60 }, - { 0x1, 0x1, 276, 415, -1, 12, 1, 2 }, - { 0x1, 0x1, 276, 417, -1, 12, 1, 2 }, - { 0x1, 0x1, 276, 539, -1, 12, 1, 2 }, - { 0x1, 0x1, 276, 541, -1, 12, 1, 2 }, - { 0x1, 0x1, 276, 423, -1, 12, 1, 77 }, - { 0x1, 0x1, 276, 425, -1, 12, 1, 77 }, - { 0x1, 0x1, 276, 547, -1, 12, 1, 77 }, - { 0x1, 0x1, 276, 549, -1, 12, 1, 77 }, - { 0x1, 0x1, 276, 431, -1, 12, 1, 2 }, - { 0x1, 0x1, 276, 433, -1, 12, 1, 2 }, - { 0x1, 0x1, 276, 555, -1, 12, 1, 2 }, - { 0x1, 0x1, 276, 557, -1, 12, 1, 2 }, - { 0x0, 0x0, 277, -1, 3176, 0, 0, -1 }, - { 0x9, 0x9, 277, -1, 3184, 33, 1, 50 }, - { 0x9, 0x9, 277, -1, 3858, 33, 1, 50 }, - { 0x0, 0x0, 277, 2154, 3249, 0, 0, -1 }, - { 0x3, 0x3, 277, 2155, -1, 27, 1, 50 }, - { 0x0, 0x0, 281, 3739, -1, 0, 1, 0 }, - { 0x3, 0x3, 282, -1, -1, 27, 1, 0 }, - { 0x3, 0x3, 282, -1, -1, 27, 1, 0 }, - { 0x3, 0x3, 282, -1, -1, 27, 1, 0 }, - { 0x3, 0x3, 282, -1, -1, 27, 1, 0 }, - { 0x1, 0x1, 283, 3901, -1, 28, 1, 0 }, - { 0x1, 0x1, 283, 3902, -1, 28, 1, 0 }, - { 0x1, 0x1, 283, 3903, -1, 28, 1, 0 }, - { 0x1, 0x1, 283, 3904, -1, 28, 1, 0 }, - { 0x1, 0x1, 285, -1, -1, 27, 1, 102 }, - { 0x1, 0x1, 285, -1, -1, 27, 1, 102 }, - { 0x0, 0x0, 285, -1, 1713, 0, 0, -1 }, - { 0x0, 0x0, 286, 3914, 3716, 0, 0, -1 }, - { 0x0, 0x0, 286, 3915, 3718, 0, 0, -1 }, - { 0x0, 0x0, 287, -1, 3717, 0, 0, -1 }, - { 0x0, 0x0, 287, -1, 3719, 0, 0, -1 }, - { 0x0, 0x0, 288, -1, -1, 0, 1, 41 }, - { 0x0, 0x0, 288, -1, -1, 0, 1, 41 }, - { 0x0, 0x0, 288, -1, -1, 0, 1, 41 }, - { 0x0, 0x0, 293, -1, -1, 0, 1, 34 }, - { 0x0, 0x0, 297, -1, 3223, 0, 1, 30 }, - { 0x0, 0x0, 298, -1, -1, 0, 1, 0 }, - { 0x0, 0x0, 298, -1, -1, 0, 1, 72 }, - { 0x0, 0x0, 298, 2861, 3883, 0, 1, 1 }, - { 0x0, 0x0, 298, 2862, 3884, 0, 1, 1 }, - { 0x0, 0x0, 298, -1, 540, 0, 0, -1 }, - { 0x0, 0x0, 298, -1, 542, 0, 0, -1 }, - { 0x0, 0x0, 298, 2865, 3887, 0, 1, 76 }, - { 0x0, 0x0, 298, 2866, 3888, 0, 1, 76 }, - { 0x0, 0x0, 298, -1, 548, 0, 0, -1 }, - { 0x0, 0x0, 298, -1, 550, 0, 0, -1 }, - { 0x0, 0x0, 298, 2869, 3891, 0, 1, 1 }, - { 0x0, 0x0, 298, 2870, 3892, 0, 1, 1 }, - { 0x0, 0x0, 298, -1, 556, 0, 0, -1 }, - { 0x0, 0x0, 298, -1, 558, 0, 0, -1 }, -}; - -static const struct ia64_main_table -main_table[] =3D { - { 5, 1, 1, 0x0000010000000000ull, 0x000001eff8000000ull, { 24, 25, 26, 0= , 0 }, 0x0, 0, }, - { 5, 1, 1, 0x0000010008000000ull, 0x000001eff8000000ull, { 24, 25, 26, 4= , 0 }, 0x0, 1, }, - { 5, 7, 1, 0x0000000000000000ull, 0x0000000000000000ull, { 24, 71, 27, 0= , 0 }, 0x0, 2, }, - { 5, 7, 1, 0x0000000000000000ull, 0x0000000000000000ull, { 24, 66, 26, 0= , 0 }, 0x0, 3, }, - { 6, 1, 1, 0x0000012000000000ull, 0x000001e000000000ull, { 24, 71, 27, 0= , 0 }, 0x0, 4, }, - { 7, 1, 1, 0x0000010040000000ull, 0x000001eff8000000ull, { 24, 25, 26, 0= , 0 }, 0x0, 5, }, - { 7, 1, 1, 0x0000010c00000000ull, 0x000001ee00000000ull, { 24, 66, 26, 0= , 0 }, 0x0, 6, }, - { 8, 1, 1, 0x0000010800000000ull, 0x000001ee00000000ull, { 24, 66, 26, 0= , 0 }, 0x0, 7, }, - { 9, 3, 1, 0x0000002c00000000ull, 0x000001ee00000000ull, { 24, 3, 55, 56= , 57 }, 0x221, 8, }, - { 9, 3, 1, 0x0000002c00000000ull, 0x000001ee00000000ull, { 24, 55, 56, 5= 7, 0 }, 0x261, 9, }, - { 10, 1, 1, 0x0000010060000000ull, 0x000001eff8000000ull, { 24, 25, 26, = 0, 0 }, 0x0, 10, }, - { 10, 1, 1, 0x0000010160000000ull, 0x000001eff8000000ull, { 24, 58, 26, = 0, 0 }, 0x0, 11, }, - { 11, 1, 1, 0x0000010068000000ull, 0x000001eff8000000ull, { 24, 25, 26, = 0, 0 }, 0x0, 12, }, - { 11, 1, 1, 0x0000010168000000ull, 0x000001eff8000000ull, { 24, 58, 26, = 0, 0 }, 0x0, 13, }, - { 14, 4, 0, 0x0000000100000000ull, 0x000001eff80011ffull, { 16, 0, 0, 0,= 0 }, 0x40, 1714, }, - { 14, 4, 0, 0x0000000100000000ull, 0x000001eff80011c0ull, { 16, 0, 0, 0,= 0 }, 0x0, 867, }, - { 14, 4, 0, 0x0000000100000000ull, 0x000001eff80011c0ull, { 16, 0, 0, 0,= 0 }, 0x40, 868, }, - { 14, 4, 0, 0x0000000108000100ull, 0x000001eff80011c0ull, { 16, 0, 0, 0,= 0 }, 0x200, 3099, }, - { 14, 4, 0, 0x0000000108000100ull, 0x000001eff80011c0ull, { 16, 0, 0, 0,= 0 }, 0x240, 3100, }, - { 14, 4, 1, 0x0000002100000000ull, 0x000001ef00001000ull, { 15, 16, 0, 0= , 0 }, 0x0, 616, }, - { 14, 4, 1, 0x0000002100000000ull, 0x000001ef00001000ull, { 15, 16, 0, 0= , 0 }, 0x40, 617, }, - { 14, 4, 0, 0x0000008000000000ull, 0x000001ee000011ffull, { 86, 0, 0, 0,= 0 }, 0x40, 1735, }, - { 14, 4, 0, 0x0000008000000000ull, 0x000001ee000011c0ull, { 86, 0, 0, 0,= 0 }, 0x0, 869, }, - { 14, 4, 0, 0x0000008000000000ull, 0x000001ee000011c0ull, { 86, 0, 0, 0,= 0 }, 0x40, 870, }, - { 14, 4, 0, 0x0000008000000080ull, 0x000001ee000011c0ull, { 86, 0, 0, 0,= 0 }, 0x210, 3912, }, - { 14, 4, 0, 0x0000008000000080ull, 0x000001ee000011c0ull, { 86, 0, 0, 0,= 0 }, 0x250, 3913, }, - { 14, 4, 0, 0x0000008000000140ull, 0x000001ee000011c0ull, { 86, 0, 0, 0,= 0 }, 0x30, 624, }, - { 14, 4, 0, 0x0000008000000140ull, 0x000001ee000011c0ull, { 86, 0, 0, 0,= 0 }, 0x70, 625, }, - { 14, 4, 0, 0x0000008000000180ull, 0x000001ee000011c0ull, { 86, 0, 0, 0,= 0 }, 0x230, 622, }, - { 14, 4, 0, 0x0000008000000180ull, 0x000001ee000011c0ull, { 86, 0, 0, 0,= 0 }, 0x270, 623, }, - { 14, 4, 1, 0x000000a000000000ull, 0x000001ee00001000ull, { 15, 86, 0, 0= , 0 }, 0x0, 618, }, - { 14, 4, 1, 0x000000a000000000ull, 0x000001ee00001000ull, { 15, 86, 0, 0= , 0 }, 0x40, 619, }, - { 15, 4, 0, 0x0000000000000000ull, 0x000001e1f8000000ull, { 70, 0, 0, 0,= 0 }, 0x0, 559, }, - { 15, 5, 0, 0x0000000000000000ull, 0x000001e3f8000000ull, { 70, 0, 0, 0,= 0 }, 0x0, 1702, }, - { 15, 2, 0, 0x0000000000000000ull, 0x000001eff8000000ull, { 70, 0, 0, 0,= 0 }, 0x2, 1885, }, - { 15, 3, 0, 0x0000000000000000ull, 0x000001eff8000000ull, { 70, 0, 0, 0,= 0 }, 0x0, 2010, }, - { 15, 6, 0, 0x0000000000000000ull, 0x000001eff8000000ull, { 74, 0, 0, 0,= 0 }, 0x0, 3916, }, - { 15, 7, 0, 0x0000000000000000ull, 0x0000000000000000ull, { 70, 0, 0, 0,= 0 }, 0x0, 16, }, - { 16, 6, 0, 0x0000018000000000ull, 0x000001ee000011ffull, { 87, 0, 0, 0,= 0 }, 0x40, 1768, }, - { 16, 6, 0, 0x0000018000000000ull, 0x000001ee000011c0ull, { 87, 0, 0, 0,= 0 }, 0x0, 871, }, - { 16, 6, 0, 0x0000018000000000ull, 0x000001ee000011c0ull, { 87, 0, 0, 0,= 0 }, 0x40, 872, }, - { 16, 6, 1, 0x000001a000000000ull, 0x000001ee00001000ull, { 15, 87, 0, 0= , 0 }, 0x0, 620, }, - { 16, 6, 1, 0x000001a000000000ull, 0x000001ee00001000ull, { 15, 87, 0, 0= , 0 }, 0x40, 621, }, - { 17, 4, 0, 0x0000004080000000ull, 0x000001e9f8000018ull, { 16, 82, 0, 0= , 0 }, 0x20, 3735, }, - { 17, 4, 0, 0x000000e000000000ull, 0x000001e800000018ull, { 86, 82, 0, 0= , 0 }, 0x20, 3736, }, - { 18, 4, 0, 0x0000000060000000ull, 0x000001e1f8000000ull, { 0, 0, 0, 0, = 0 }, 0x2c, 227, }, - { 22, 2, 0, 0x0000000200000000ull, 0x000001ee00000000ull, { 25, 85, 0, 0= , 0 }, 0x0, 3104, }, - { 22, 3, 0, 0x0000000800000000ull, 0x000001ee00000000ull, { 24, 86, 0, 0= , 0 }, 0x0, 231, }, - { 22, 3, 0, 0x0000000c00000000ull, 0x000001ee00000000ull, { 18, 86, 0, 0= , 0 }, 0x0, 232, }, - { 22, 3, 0, 0x0000002200000000ull, 0x000001ee00000000ull, { 25, 85, 0, 0= , 0 }, 0x0, 3105, }, - { 22, 3, 0, 0x0000002600000000ull, 0x000001ee00000000ull, { 19, 85, 0, 0= , 0 }, 0x0, 3106, }, - { 22, 7, 0, 0x0000000000000000ull, 0x0000000000000000ull, { 25, 85, 0, 0= , 0 }, 0x0, 3107, }, - { 25, 4, 0, 0x0000000020000000ull, 0x000001e1f8000000ull, { 0, 0, 0, 0, = 0 }, 0x224, 18, }, - { 26, 2, 1, 0x000000e6d0000000ull, 0x000001fff0000000ull, { 24, 26, 0, 0= , 0 }, 0x0, 19, }, - { 27, 1, 2, 0x0000018000000000ull, 0x000001fe00001000ull, { 22, 23, 25, = 26, 0 }, 0x0, 1969, }, - { 27, 1, 1, 0x0000018000000000ull, 0x000001fe00001000ull, { 22, 25, 26, = 0, 0 }, 0x40, 1970, }, - { 27, 1, 2, 0x0000018000000000ull, 0x000001fe00001000ull, { 23, 22, 26, = 25, 0 }, 0x0, 1928, }, - { 27, 1, 1, 0x0000018000000000ull, 0x000001fe00001000ull, { 23, 26, 25, = 0, 0 }, 0x40, 1929, }, - { 27, 1, 2, 0x0000018000000000ull, 0x000001fe00001000ull, { 22, 23, 26, = 25, 0 }, 0x0, 1837, }, - { 27, 1, 1, 0x0000018000000000ull, 0x000001fe00001000ull, { 22, 26, 25, = 0, 0 }, 0x40, 1838, }, - { 27, 1, 2, 0x0000018000000000ull, 0x000001fe00001000ull, { 23, 22, 25, = 26, 0 }, 0x0, 1799, }, - { 27, 1, 1, 0x0000018000000000ull, 0x000001fe00001000ull, { 23, 25, 26, = 0, 0 }, 0x40, 1800, }, - { 27, 1, 2, 0x0000018200000000ull, 0x000001fe00001000ull, { 22, 23, 25, = 26, 0 }, 0x40, 2131, }, - { 27, 1, 2, 0x0000019000000000ull, 0x000001fe00001000ull, { 22, 23, 7, 2= 6, 0 }, 0x0, 1839, }, - { 27, 1, 1, 0x0000019000000000ull, 0x000001fe00001000ull, { 22, 7, 26, 0= , 0 }, 0x40, 1840, }, - { 27, 1, 2, 0x0000019000000000ull, 0x000001fe00001000ull, { 22, 23, 26, = 7, 0 }, 0x40, 1973, }, - { 27, 1, 1, 0x0000019000000000ull, 0x000001fe00001000ull, { 22, 26, 7, 0= , 0 }, 0x40, 1974, }, - { 27, 1, 2, 0x0000019000000000ull, 0x000001fe00001000ull, { 22, 23, 7, 2= 6, 0 }, 0x40, 1934, }, - { 27, 1, 2, 0x0000018800000000ull, 0x000001ee00001000ull, { 22, 23, 58, = 26, 0 }, 0x0, 1976, }, - { 27, 1, 1, 0x0000018800000000ull, 0x000001ee00001000ull, { 22, 58, 26, = 0, 0 }, 0x40, 1977, }, - { 27, 1, 2, 0x0000018800000000ull, 0x000001ee00001000ull, { 22, 23, 60, = 26, 0 }, 0x0, 1935, }, - { 27, 1, 1, 0x0000018800000000ull, 0x000001ee00001000ull, { 22, 60, 26, = 0, 0 }, 0x40, 1936, }, - { 27, 1, 2, 0x0000018800000000ull, 0x000001ee00001000ull, { 23, 22, 60, = 26, 0 }, 0x0, 1844, }, - { 27, 1, 1, 0x0000018800000000ull, 0x000001ee00001000ull, { 23, 60, 26, = 0, 0 }, 0x40, 1845, }, - { 27, 1, 2, 0x0000018800000000ull, 0x000001ee00001000ull, { 23, 22, 58, = 26, 0 }, 0x0, 1806, }, - { 27, 1, 1, 0x0000018800000000ull, 0x000001ee00001000ull, { 23, 58, 26, = 0, 0 }, 0x40, 1807, }, - { 27, 1, 2, 0x0000018a00000000ull, 0x000001ee00001000ull, { 22, 23, 58, = 26, 0 }, 0x40, 2136, }, - { 27, 1, 2, 0x000001a800000000ull, 0x000001ee00001000ull, { 22, 23, 62, = 26, 0 }, 0x0, 1961, }, - { 27, 1, 1, 0x000001a800000000ull, 0x000001ee00001000ull, { 22, 62, 26, = 0, 0 }, 0x40, 1962, }, - { 27, 1, 2, 0x000001a800000000ull, 0x000001ee00001000ull, { 23, 22, 62, = 26, 0 }, 0x0, 1872, }, - { 27, 1, 1, 0x000001a800000000ull, 0x000001ee00001000ull, { 23, 62, 26, = 0, 0 }, 0x40, 1873, }, - { 27, 1, 2, 0x000001c200000000ull, 0x000001fe00001000ull, { 23, 22, 25, = 26, 0 }, 0x40, 2137, }, - { 27, 1, 2, 0x000001d000000000ull, 0x000001fe00001000ull, { 23, 22, 7, 2= 6, 0 }, 0x40, 1937, }, - { 27, 1, 1, 0x000001d000000000ull, 0x000001fe00001000ull, { 23, 7, 26, 0= , 0 }, 0x40, 1938, }, - { 27, 1, 2, 0x000001d000000000ull, 0x000001fe00001000ull, { 23, 22, 26, = 7, 0 }, 0x40, 1810, }, - { 27, 1, 1, 0x000001d000000000ull, 0x000001fe00001000ull, { 23, 26, 7, 0= , 0 }, 0x40, 1811, }, - { 27, 1, 2, 0x000001ca00000000ull, 0x000001ee00001000ull, { 23, 22, 58, = 26, 0 }, 0x40, 2138, }, - { 28, 1, 2, 0x0000018400000000ull, 0x000001fe00001000ull, { 22, 23, 25, = 26, 0 }, 0x0, 1982, }, - { 28, 1, 1, 0x0000018400000000ull, 0x000001fe00001000ull, { 22, 25, 26, = 0, 0 }, 0x40, 1983, }, - { 28, 1, 2, 0x0000018400000000ull, 0x000001fe00001000ull, { 23, 22, 26, = 25, 0 }, 0x0, 1941, }, - { 28, 1, 1, 0x0000018400000000ull, 0x000001fe00001000ull, { 23, 26, 25, = 0, 0 }, 0x40, 1942, }, - { 28, 1, 2, 0x0000018400000000ull, 0x000001fe00001000ull, { 22, 23, 26, = 25, 0 }, 0x0, 1850, }, - { 28, 1, 1, 0x0000018400000000ull, 0x000001fe00001000ull, { 22, 26, 25, = 0, 0 }, 0x40, 1851, }, - { 28, 1, 2, 0x0000018400000000ull, 0x000001fe00001000ull, { 23, 22, 25, = 26, 0 }, 0x0, 1812, }, - { 28, 1, 1, 0x0000018400000000ull, 0x000001fe00001000ull, { 23, 25, 26, = 0, 0 }, 0x40, 1813, }, - { 28, 1, 2, 0x0000018600000000ull, 0x000001fe00001000ull, { 22, 23, 25, = 26, 0 }, 0x40, 2143, }, - { 28, 1, 2, 0x0000019400000000ull, 0x000001fe00001000ull, { 22, 23, 7, 2= 6, 0 }, 0x0, 1852, }, - { 28, 1, 1, 0x0000019400000000ull, 0x000001fe00001000ull, { 22, 7, 26, 0= , 0 }, 0x40, 1853, }, - { 28, 1, 2, 0x0000019400000000ull, 0x000001fe00001000ull, { 22, 23, 26, = 7, 0 }, 0x40, 1986, }, - { 28, 1, 1, 0x0000019400000000ull, 0x000001fe00001000ull, { 22, 26, 7, 0= , 0 }, 0x40, 1987, }, - { 28, 1, 2, 0x0000019400000000ull, 0x000001fe00001000ull, { 22, 23, 7, 2= 6, 0 }, 0x40, 1947, }, - { 28, 1, 2, 0x0000018c00000000ull, 0x000001ee00001000ull, { 22, 23, 58, = 26, 0 }, 0x0, 1989, }, - { 28, 1, 1, 0x0000018c00000000ull, 0x000001ee00001000ull, { 22, 58, 26, = 0, 0 }, 0x40, 1990, }, - { 28, 1, 2, 0x0000018c00000000ull, 0x000001ee00001000ull, { 22, 23, 60, = 26, 0 }, 0x0, 1948, }, - { 28, 1, 1, 0x0000018c00000000ull, 0x000001ee00001000ull, { 22, 60, 26, = 0, 0 }, 0x40, 1949, }, - { 28, 1, 2, 0x0000018c00000000ull, 0x000001ee00001000ull, { 23, 22, 60, = 26, 0 }, 0x0, 1857, }, - { 28, 1, 1, 0x0000018c00000000ull, 0x000001ee00001000ull, { 23, 60, 26, = 0, 0 }, 0x40, 1858, }, - { 28, 1, 2, 0x0000018c00000000ull, 0x000001ee00001000ull, { 23, 22, 58, = 26, 0 }, 0x0, 1819, }, - { 28, 1, 1, 0x0000018c00000000ull, 0x000001ee00001000ull, { 23, 58, 26, = 0, 0 }, 0x40, 1820, }, - { 28, 1, 2, 0x0000018e00000000ull, 0x000001ee00001000ull, { 22, 23, 58, = 26, 0 }, 0x40, 2148, }, - { 28, 1, 2, 0x000001ac00000000ull, 0x000001ee00001000ull, { 22, 23, 59, = 26, 0 }, 0x0, 2006, }, - { 28, 1, 1, 0x000001ac00000000ull, 0x000001ee00001000ull, { 22, 59, 26, = 0, 0 }, 0x40, 2007, }, - { 28, 1, 2, 0x000001ac00000000ull, 0x000001ee00001000ull, { 22, 23, 61, = 26, 0 }, 0x0, 1965, }, - { 28, 1, 1, 0x000001ac00000000ull, 0x000001ee00001000ull, { 22, 61, 26, = 0, 0 }, 0x40, 1966, }, - { 28, 1, 2, 0x000001ac00000000ull, 0x000001ee00001000ull, { 23, 22, 61, = 26, 0 }, 0x0, 1876, }, - { 28, 1, 1, 0x000001ac00000000ull, 0x000001ee00001000ull, { 23, 61, 26, = 0, 0 }, 0x40, 1877, }, - { 28, 1, 2, 0x000001ac00000000ull, 0x000001ee00001000ull, { 23, 22, 59, = 26, 0 }, 0x0, 1835, }, - { 28, 1, 1, 0x000001ac00000000ull, 0x000001ee00001000ull, { 23, 59, 26, = 0, 0 }, 0x40, 1836, }, - { 28, 1, 2, 0x000001c600000000ull, 0x000001fe00001000ull, { 23, 22, 25, = 26, 0 }, 0x40, 2149, }, - { 28, 1, 2, 0x000001d400000000ull, 0x000001fe00001000ull, { 23, 22, 7, 2= 6, 0 }, 0x40, 1950, }, - { 28, 1, 1, 0x000001d400000000ull, 0x000001fe00001000ull, { 23, 7, 26, 0= , 0 }, 0x40, 1951, }, - { 28, 1, 2, 0x000001d400000000ull, 0x000001fe00001000ull, { 23, 22, 26, = 7, 0 }, 0x40, 1823, }, - { 28, 1, 1, 0x000001d400000000ull, 0x000001fe00001000ull, { 23, 26, 7, 0= , 0 }, 0x40, 1824, }, - { 28, 1, 2, 0x000001ce00000000ull, 0x000001ee00001000ull, { 23, 22, 58, = 26, 0 }, 0x40, 2150, }, - { 29, 3, 1, 0x0000008808000000ull, 0x000001fff8000000ull, { 24, 29, 25, = 1, 2 }, 0x0, 272, }, - { 29, 3, 1, 0x0000008808000000ull, 0x000001fff8000000ull, { 24, 29, 25, = 0, 0 }, 0x40, 273, }, - { 30, 3, 1, 0x0000008008000000ull, 0x000001fff8000000ull, { 24, 29, 25, = 2, 0 }, 0x0, 274, }, - { 30, 3, 1, 0x0000008008000000ull, 0x000001fff8000000ull, { 24, 29, 25, = 0, 0 }, 0x40, 275, }, - { 31, 3, 1, 0x0000008048000000ull, 0x000001fff8000000ull, { 24, 29, 25, = 2, 0 }, 0x0, 276, }, - { 31, 3, 1, 0x0000008048000000ull, 0x000001fff8000000ull, { 24, 29, 25, = 0, 0 }, 0x40, 277, }, - { 32, 3, 1, 0x0000008088000000ull, 0x000001fff8000000ull, { 24, 29, 25, = 2, 0 }, 0x0, 278, }, - { 32, 3, 1, 0x0000008088000000ull, 0x000001fff8000000ull, { 24, 29, 25, = 0, 0 }, 0x40, 279, }, - { 33, 3, 1, 0x00000080c8000000ull, 0x000001fff8000000ull, { 24, 29, 25, = 2, 0 }, 0x0, 280, }, - { 33, 3, 1, 0x00000080c8000000ull, 0x000001fff8000000ull, { 24, 29, 25, = 0, 0 }, 0x40, 281, }, - { 36, 4, 0, 0x0000000010000000ull, 0x000001e1f8000000ull, { 0, 0, 0, 0, = 0 }, 0x224, 20, }, - { 38, 2, 1, 0x00000000c0000000ull, 0x000001eff8000000ull, { 24, 26, 0, 0= , 0 }, 0x0, 1914, }, - { 39, 2, 1, 0x00000000c8000000ull, 0x000001eff8000000ull, { 24, 26, 0, 0= , 0 }, 0x0, 1915, }, - { 49, 2, 1, 0x0000008000000000ull, 0x000001e000000000ull, { 24, 25, 26, = 49, 77 }, 0x0, 21, }, - { 49, 2, 1, 0x000000a600000000ull, 0x000001ee04000000ull, { 24, 25, 47, = 78, 0 }, 0x0, 3921, }, - { 49, 2, 1, 0x000000a604000000ull, 0x000001ee04000000ull, { 24, 58, 47, = 78, 0 }, 0x0, 3922, }, - { 49, 2, 1, 0x000000ae00000000ull, 0x000001ee00000000ull, { 24, 50, 26, = 48, 78 }, 0x0, 22, }, - { 53, 4, 0, 0x0000000080000000ull, 0x000001e1f8000000ull, { 0, 0, 0, 0, = 0 }, 0x20, 23, }, - { 58, 2, 1, 0x000000a400000000ull, 0x000001ee00002000ull, { 24, 26, 81, = 78, 0 }, 0x0, 3753, }, - { 60, 5, 1, 0x0000000080000000ull, 0x000001e3f80fe000ull, { 18, 20, 0, 0= , 0 }, 0x40, 25, }, - { 61, 5, 1, 0x0000010008000000ull, 0x000001fff8000000ull, { 18, 20, 19, = 0, 0 }, 0x40, 3164, }, - { 62, 5, 1, 0x00000000b8000000ull, 0x000001eff8000000ull, { 18, 19, 20, = 0, 0 }, 0x0, 3165, }, - { 62, 5, 1, 0x00000000b8000000ull, 0x000001eff8000000ull, { 18, 19, 20, = 0, 0 }, 0x40, 27, }, - { 63, 5, 1, 0x00000000b0000000ull, 0x000001eff8000000ull, { 18, 19, 20, = 0, 0 }, 0x0, 3166, }, - { 63, 5, 1, 0x00000000b0000000ull, 0x000001eff8000000ull, { 18, 19, 20, = 0, 0 }, 0x40, 28, }, - { 64, 5, 1, 0x0000000160000000ull, 0x000001e3f8000000ull, { 18, 19, 20, = 0, 0 }, 0x0, 29, }, - { 65, 5, 1, 0x0000000168000000ull, 0x000001e3f8000000ull, { 18, 19, 20, = 0, 0 }, 0x0, 30, }, - { 67, 3, 0, 0x0000002180000000ull, 0x000001fff8000000ull, { 26, 0, 0, 0,= 0 }, 0x0, 31, }, - { 68, 5, 0, 0x0000000040000000ull, 0x000001eff8000000ull, { 84, 0, 0, 0,= 0 }, 0x0, 3167, }, - { 68, 5, 0, 0x0000000040000000ull, 0x000001eff8000000ull, { 84, 0, 0, 0,= 0 }, 0x40, 32, }, - { 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{ 24, 29, 25,= 0, 0 }, 0x0, 218, }, - { 290, 3, 1, 0x0000008248000000ull, 0x000001fff8000000ull, { 24, 29, 25,= 0, 0 }, 0x0, 219, }, - { 291, 3, 1, 0x0000008288000000ull, 0x000001fff8000000ull, { 24, 29, 25,= 0, 0 }, 0x0, 220, }, - { 292, 3, 1, 0x00000082c8000000ull, 0x000001fff8000000ull, { 24, 29, 25,= 0, 0 }, 0x0, 221, }, - { 294, 5, 1, 0x000001d000000000ull, 0x000001fc00000000ull, { 18, 20, 21,= 19, 0 }, 0x0, 1926, }, - { 294, 5, 1, 0x000001d000000000ull, 0x000001fc00000000ull, { 18, 20, 21,= 19, 0 }, 0x40, 2008, }, - { 295, 5, 1, 0x000001d000000000ull, 0x000001fc000fe000ull, { 18, 20, 21,= 0, 0 }, 0x40, 1927, }, - { 296, 1, 1, 0x0000010078000000ull, 0x000001eff8000000ull, { 24, 25, 26,= 0, 0 }, 0x0, 222, }, - { 296, 1, 1, 0x0000010178000000ull, 0x000001eff8000000ull, { 24, 58, 26,= 0, 0 }, 0x0, 223, }, - { 299, 2, 1, 0x0000000080000000ull, 0x000001eff8000000ull, { 24, 26, 0, = 0, 0 }, 0x0, 224, }, - { 300, 2, 1, 0x0000000088000000ull, 0x000001eff8000000ull, { 24, 26, 0, = 0, 0 }, 0x0, 225, }, - { 301, 2, 1, 0x0000000090000000ull, 0x000001eff8000000ull, { 24, 26, 0, = 0, 0 }, 0x0, 226, }, -}; - -static const char dis_table[] =3D { - 0xa1, 0x02, 0x78, 0xa0, 0x2f, 0x28, 0xa0, 0x2d, 0x10, 0xa0, 0x1c, 0x40, - 0x98, 0xb0, 0x02, 0x50, 0x90, 0x50, 0x90, 0x28, 0x24, 0x52, 0x40, 0x24, - 0x52, 0x38, 0x90, 0x28, 0x24, 0x52, 0x30, 0x24, 0x52, 0x28, 0x91, 0x60, - 0x90, 0x28, 0x24, 0x52, 0x18, 0x10, 0x10, 0x58, 0x41, 0x62, 0x90, 0x80, - 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, - 0x10, 0x10, 0x52, 0xc0, 0xc0, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, - 0x10, 0x10, 0x10, 0x24, 0x3d, 0x90, 0x90, 0x28, 0x24, 0x52, 0x08, 0x24, - 0x52, 0x00, 0xa8, 0x0b, 0x88, 0x15, 0x60, 0x97, 0x60, 0x96, 0x08, 0x9a, - 0xf8, 0x05, 0x78, 0x91, 0x58, 0x90, 0xe0, 0x90, 0xa0, 0x80, 0x90, 0x20, - 0x37, 0xc9, 0x90, 0x20, 0x37, 0xc6, 0xcb, 0xa1, 0xf1, 0x00, 0xa4, 0x37, - 0xf8, 0x37, 0x00, 0x80, 0xa4, 0x4f, 0xb8, 0x39, 0xfc, 0x90, 0x50, 0x90, - 0x28, 0x80, 0x39, 0xf2, 0x80, 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0x3b, 0xca, 0xe5, 0x22, 0xf0, 0x80, 0x3b, - 0xd8, -}; - -static const struct ia64_dis_names ia64_dis_names[] =3D { -{ 0x51, 41, 0, 10 }, -{ 0x31, 41, 1, 20 }, -{ 0x11, 42, 0, 19 }, -{ 0x29, 41, 0, 12 }, -{ 0x19, 41, 1, 24 }, -{ 0x9, 42, 0, 23 }, -{ 0x15, 41, 0, 14 }, -{ 0xd, 41, 1, 28 }, -{ 0x5, 42, 0, 27 }, -{ 0xb, 41, 0, 16 }, -{ 0x7, 41, 1, 32 }, -{ 0x3, 42, 0, 31 }, -{ 0x51, 39, 1, 58 }, -{ 0x50, 39, 0, 34 }, -{ 0xd1, 39, 1, 57 }, -{ 0xd0, 39, 0, 33 }, -{ 0x31, 39, 1, 68 }, -{ 0x30, 39, 1, 44 }, -{ 0x11, 40, 1, 67 }, -{ 0x10, 40, 0, 43 }, -{ 0x71, 39, 1, 66 }, -{ 0x70, 39, 1, 42 }, -{ 0x31, 40, 1, 65 }, -{ 0x30, 40, 0, 41 }, -{ 0x29, 39, 1, 60 }, -{ 0x28, 39, 0, 36 }, -{ 0x69, 39, 1, 59 }, -{ 0x68, 39, 0, 35 }, -{ 0x19, 39, 1, 72 }, -{ 0x18, 39, 1, 48 }, -{ 0x9, 40, 1, 71 }, -{ 0x8, 40, 0, 47 }, -{ 0x39, 39, 1, 70 }, -{ 0x38, 39, 1, 46 }, -{ 0x19, 40, 1, 69 }, -{ 0x18, 40, 0, 45 }, -{ 0x15, 39, 1, 62 }, -{ 0x14, 39, 0, 38 }, -{ 0x35, 39, 1, 61 }, -{ 0x34, 39, 0, 37 }, -{ 0xd, 39, 1, 76 }, -{ 0xc, 39, 1, 52 }, -{ 0x5, 40, 1, 75 }, -{ 0x4, 40, 0, 51 }, -{ 0x1d, 39, 1, 74 }, -{ 0x1c, 39, 1, 50 }, -{ 0xd, 40, 1, 73 }, -{ 0xc, 40, 0, 49 }, -{ 0xb, 39, 1, 64 }, -{ 0xa, 39, 0, 40 }, -{ 0x1b, 39, 1, 63 }, -{ 0x1a, 39, 0, 39 }, -{ 0x7, 39, 1, 80 }, -{ 0x6, 39, 1, 56 }, -{ 0x3, 40, 1, 79 }, -{ 0x2, 40, 0, 55 }, -{ 0xf, 39, 1, 78 }, -{ 0xe, 39, 1, 54 }, -{ 0x7, 40, 1, 77 }, -{ 0x6, 40, 0, 53 }, -{ 0x8, 38, 0, 82 }, -{ 0x18, 38, 0, 81 }, -{ 0x1, 38, 1, 86 }, -{ 0x2, 38, 0, 85 }, -{ 0x3, 38, 1, 84 }, -{ 0x4, 38, 0, 83 }, -{ 0x1, 356, 0, 87 }, -{ 0x200, 306, 1, 114 }, -{ 0x60, 307, 0, 113 }, -{ 0x20200, 306, 1, 102 }, -{ 0xc20, 307, 0, 101 }, -{ 0x1020200, 306, 0, 91 }, -{ 0x820200, 306, 0, 92 }, -{ 0x420200, 306, 0, 93 }, -{ 0x220200, 306, 0, 94 }, -{ 0x120200, 306, 1, 96 }, -{ 0x4420, 307, 0, 95 }, -{ 0xa0200, 306, 1, 98 }, -{ 0x2420, 307, 0, 97 }, -{ 0x60200, 306, 1, 100 }, -{ 0x1420, 307, 0, 99 }, -{ 0x10200, 306, 0, 103 }, -{ 0x8200, 306, 0, 104 }, -{ 0x4200, 306, 0, 105 }, -{ 0x2200, 306, 0, 106 }, -{ 0x1200, 306, 1, 108 }, -{ 0x220, 307, 0, 107 }, -{ 0xa00, 306, 1, 110 }, -{ 0x120, 307, 0, 109 }, -{ 0x600, 306, 1, 112 }, -{ 0xa0, 307, 0, 111 }, -{ 0x100, 306, 1, 126 }, -{ 0x30, 307, 0, 125 }, -{ 0x8100, 306, 0, 115 }, -{ 0x4100, 306, 0, 116 }, -{ 0x2100, 306, 0, 117 }, -{ 0x1100, 306, 0, 118 }, -{ 0x900, 306, 1, 120 }, -{ 0x110, 307, 0, 119 }, -{ 0x500, 306, 1, 122 }, -{ 0x90, 307, 0, 121 }, -{ 0x300, 306, 1, 124 }, -{ 0x50, 307, 0, 123 }, -{ 0x80, 306, 0, 127 }, -{ 0x40, 306, 0, 128 }, -{ 0x20, 306, 0, 129 }, -{ 0x10, 306, 0, 130 }, -{ 0x8, 306, 1, 132 }, -{ 0x8, 307, 0, 131 }, -{ 0x4, 306, 1, 134 }, -{ 0x4, 307, 0, 133 }, -{ 0x2, 306, 1, 136 }, -{ 0x2, 307, 0, 135 }, -{ 0x1, 306, 1, 138 }, -{ 0x1, 307, 0, 137 }, -{ 0x1, 439, 0, 140 }, -{ 0x3, 439, 0, 139 }, -{ 0x2, 448, 0, 141 }, -{ 0x1, 448, 0, 142 }, -{ 0x2, 442, 0, 143 }, -{ 0x1, 442, 0, 144 }, -{ 0x2, 445, 0, 145 }, -{ 0x1, 445, 0, 146 }, -{ 0x2, 451, 0, 147 }, -{ 0x1, 451, 0, 148 }, -{ 0x1, 275, 0, 175 }, -{ 0x5, 275, 0, 173 }, -{ 0x3, 275, 0, 174 }, -{ 0x140, 287, 0, 151 }, -{ 0x540, 287, 0, 149 }, -{ 0x340, 287, 0, 150 }, -{ 0xc0, 287, 0, 163 }, -{ 0x2c0, 287, 0, 161 }, -{ 0x1c0, 287, 0, 162 }, -{ 0x20, 287, 0, 178 }, -{ 0xa0, 287, 0, 176 }, -{ 0x60, 287, 0, 177 }, -{ 0x10, 287, 0, 190 }, -{ 0x50, 287, 0, 188 }, -{ 0x30, 287, 0, 189 }, -{ 0x8, 287, 0, 202 }, -{ 0x28, 287, 0, 200 }, -{ 0x18, 287, 0, 201 }, -{ 0x4, 287, 0, 212 }, -{ 0x2, 287, 0, 213 }, -{ 0x1, 287, 0, 214 }, -{ 0x140, 279, 0, 154 }, -{ 0x540, 279, 0, 152 }, -{ 0x340, 279, 0, 153 }, -{ 0xc0, 279, 0, 166 }, -{ 0x2c0, 279, 0, 164 }, -{ 0x1c0, 279, 0, 165 }, -{ 0x20, 279, 0, 181 }, -{ 0xa0, 279, 0, 179 }, -{ 0x60, 279, 0, 180 }, -{ 0x10, 279, 0, 193 }, -{ 0x50, 279, 0, 191 }, -{ 0x30, 279, 0, 192 }, -{ 0x8, 279, 0, 205 }, -{ 0x28, 279, 0, 203 }, -{ 0x18, 279, 0, 204 }, -{ 0x4, 279, 0, 215 }, -{ 0x2, 279, 0, 216 }, -{ 0x1, 279, 0, 217 }, -{ 0x140, 283, 0, 157 }, -{ 0x540, 283, 0, 155 }, -{ 0x340, 283, 0, 156 }, -{ 0xc0, 283, 0, 169 }, -{ 0x2c0, 283, 0, 167 }, -{ 0x1c0, 283, 0, 168 }, -{ 0x20, 283, 0, 184 }, -{ 0xa0, 283, 0, 182 }, -{ 0x60, 283, 0, 183 }, -{ 0x10, 283, 0, 196 }, -{ 0x50, 283, 0, 194 }, -{ 0x30, 283, 0, 195 }, -{ 0x8, 283, 0, 208 }, -{ 0x28, 283, 0, 206 }, -{ 0x18, 283, 0, 207 }, -{ 0x4, 283, 0, 218 }, -{ 0x2, 283, 0, 219 }, -{ 0x1, 283, 0, 220 }, -{ 0x140, 297, 0, 160 }, -{ 0x540, 297, 0, 158 }, -{ 0x340, 297, 0, 159 }, -{ 0xc0, 297, 0, 172 }, -{ 0x2c0, 297, 0, 170 }, -{ 0x1c0, 297, 0, 171 }, -{ 0x20, 297, 0, 187 }, -{ 0xa0, 297, 0, 185 }, -{ 0x60, 297, 0, 186 }, -{ 0x10, 297, 0, 199 }, -{ 0x50, 297, 0, 197 }, -{ 0x30, 297, 0, 198 }, -{ 0x8, 297, 0, 211 }, -{ 0x28, 297, 0, 209 }, -{ 0x18, 297, 0, 210 }, -{ 0x4, 297, 0, 221 }, -{ 0x2, 297, 0, 222 }, -{ 0x1, 297, 0, 223 }, -{ 0x8, 412, 0, 224 }, -{ 0x4, 412, 0, 225 }, -{ 0x2, 412, 0, 226 }, -{ 0x1, 412, 0, 227 }, -{ 0x200, 304, 1, 251 }, -{ 0x60, 305, 0, 250 }, -{ 0x20200, 304, 1, 239 }, -{ 0xc20, 305, 0, 238 }, -{ 0x1020200, 304, 0, 228 }, -{ 0x820200, 304, 0, 229 }, -{ 0x420200, 304, 0, 230 }, -{ 0x220200, 304, 0, 231 }, -{ 0x120200, 304, 1, 233 }, -{ 0x4420, 305, 0, 232 }, -{ 0xa0200, 304, 1, 235 }, -{ 0x2420, 305, 0, 234 }, -{ 0x60200, 304, 1, 237 }, -{ 0x1420, 305, 0, 236 }, -{ 0x10200, 304, 0, 240 }, -{ 0x8200, 304, 0, 241 }, -{ 0x4200, 304, 0, 242 }, -{ 0x2200, 304, 0, 243 }, -{ 0x1200, 304, 1, 245 }, -{ 0x220, 305, 0, 244 }, -{ 0xa00, 304, 1, 247 }, -{ 0x120, 305, 0, 246 }, -{ 0x600, 304, 1, 249 }, -{ 0xa0, 305, 0, 248 }, -{ 0x100, 304, 1, 263 }, -{ 0x30, 305, 0, 262 }, -{ 0x8100, 304, 0, 252 }, -{ 0x4100, 304, 0, 253 }, -{ 0x2100, 304, 0, 254 }, -{ 0x1100, 304, 0, 255 }, -{ 0x900, 304, 1, 257 }, -{ 0x110, 305, 0, 256 }, -{ 0x500, 304, 1, 259 }, -{ 0x90, 305, 0, 258 }, -{ 0x300, 304, 1, 261 }, -{ 0x50, 305, 0, 260 }, -{ 0x80, 304, 0, 264 }, -{ 0x40, 304, 0, 265 }, -{ 0x20, 304, 0, 266 }, -{ 0x10, 304, 0, 267 }, -{ 0x8, 304, 1, 269 }, -{ 0x8, 305, 0, 268 }, -{ 0x4, 304, 1, 271 }, -{ 0x4, 305, 0, 270 }, -{ 0x2, 304, 1, 273 }, -{ 0x2, 305, 0, 272 }, -{ 0x1, 304, 1, 275 }, -{ 0x1, 305, 0, 274 }, -{ 0x1, 302, 1, 287 }, -{ 0x3, 303, 0, 286 }, -{ 0x81, 302, 0, 276 }, -{ 0x41, 302, 0, 277 }, -{ 0x21, 302, 0, 278 }, -{ 0x11, 302, 0, 279 }, -{ 0x9, 302, 1, 281 }, -{ 0x11, 303, 0, 280 }, -{ 0x5, 302, 1, 283 }, -{ 0x9, 303, 0, 282 }, -{ 0x3, 302, 1, 285 }, -{ 0x5, 303, 0, 284 }, -{ 0x2, 300, 1, 311 }, -{ 0x6, 301, 0, 310 }, -{ 0x202, 300, 1, 299 }, -{ 0xc2, 301, 0, 298 }, -{ 0x10202, 300, 0, 288 }, -{ 0x8202, 300, 0, 289 }, -{ 0x4202, 300, 0, 290 }, -{ 0x2202, 300, 0, 291 }, -{ 0x1202, 300, 1, 293 }, -{ 0x442, 301, 0, 292 }, -{ 0xa02, 300, 1, 295 }, -{ 0x242, 301, 0, 294 }, -{ 0x602, 300, 1, 297 }, -{ 0x142, 301, 0, 296 }, -{ 0x102, 300, 0, 300 }, -{ 0x82, 300, 0, 301 }, -{ 0x42, 300, 0, 302 }, -{ 0x22, 300, 0, 303 }, -{ 0x12, 300, 1, 305 }, -{ 0x22, 301, 0, 304 }, -{ 0xa, 300, 1, 307 }, -{ 0x12, 301, 0, 306 }, -{ 0x6, 300, 1, 309 }, -{ 0xa, 301, 0, 308 }, -{ 0x1, 300, 1, 323 }, -{ 0x3, 301, 0, 322 }, -{ 0x81, 300, 0, 312 }, -{ 0x41, 300, 0, 313 }, -{ 0x21, 300, 0, 314 }, -{ 0x11, 300, 0, 315 }, -{ 0x9, 300, 1, 317 }, -{ 0x11, 301, 0, 316 }, -{ 0x5, 300, 1, 319 }, -{ 0x9, 301, 0, 318 }, -{ 0x3, 300, 1, 321 }, -{ 0x5, 301, 0, 320 }, -{ 0x80, 298, 0, 324 }, -{ 0x40, 298, 0, 325 }, -{ 0x20, 298, 0, 326 }, -{ 0x10, 298, 0, 327 }, -{ 0x8, 298, 1, 329 }, -{ 0x8, 299, 0, 328 }, -{ 0x4, 298, 1, 331 }, -{ 0x4, 299, 0, 330 }, -{ 0x2, 298, 1, 333 }, -{ 0x2, 299, 0, 332 }, -{ 0x1, 298, 1, 335 }, -{ 0x1, 299, 0, 334 }, -{ 0x140, 289, 0, 338 }, -{ 0x540, 289, 0, 336 }, -{ 0x340, 289, 0, 337 }, -{ 0xc0, 289, 0, 347 }, -{ 0x2c0, 289, 0, 345 }, -{ 0x1c0, 289, 0, 346 }, -{ 0x20, 289, 0, 356 }, -{ 0xa0, 289, 0, 354 }, -{ 0x60, 289, 0, 355 }, -{ 0x10, 289, 0, 365 }, -{ 0x50, 289, 0, 363 }, -{ 0x30, 289, 0, 364 }, -{ 0x8, 289, 0, 374 }, -{ 0x28, 289, 0, 372 }, -{ 0x18, 289, 0, 373 }, -{ 0x4, 289, 0, 381 }, -{ 0x2, 289, 0, 382 }, -{ 0x1, 289, 0, 383 }, -{ 0x140, 291, 0, 341 }, -{ 0x540, 291, 0, 339 }, -{ 0x340, 291, 0, 340 }, -{ 0xc0, 291, 0, 350 }, -{ 0x2c0, 291, 0, 348 }, -{ 0x1c0, 291, 0, 349 }, -{ 0x20, 291, 0, 359 }, -{ 0xa0, 291, 0, 357 }, -{ 0x60, 291, 0, 358 }, -{ 0x10, 291, 0, 368 }, -{ 0x50, 291, 0, 366 }, -{ 0x30, 291, 0, 367 }, -{ 0x8, 291, 0, 377 }, -{ 0x28, 291, 0, 375 }, -{ 0x18, 291, 0, 376 }, -{ 0x4, 291, 0, 384 }, -{ 0x2, 291, 0, 385 }, -{ 0x1, 291, 0, 386 }, -{ 0x140, 293, 0, 344 }, -{ 0x540, 293, 0, 342 }, -{ 0x340, 293, 0, 343 }, -{ 0xc0, 293, 0, 353 }, -{ 0x2c0, 293, 0, 351 }, -{ 0x1c0, 293, 0, 352 }, -{ 0x20, 293, 0, 362 }, -{ 0xa0, 293, 0, 360 }, -{ 0x60, 293, 0, 361 }, -{ 0x10, 293, 0, 371 }, -{ 0x50, 293, 0, 369 }, -{ 0x30, 293, 0, 370 }, -{ 0x8, 293, 0, 380 }, -{ 0x28, 293, 0, 378 }, -{ 0x18, 293, 0, 379 }, -{ 0x4, 293, 0, 387 }, -{ 0x2, 293, 0, 388 }, -{ 0x1, 293, 0, 389 }, -{ 0x140, 288, 0, 392 }, -{ 0x540, 288, 0, 390 }, -{ 0x340, 288, 0, 391 }, -{ 0xc0, 288, 0, 401 }, -{ 0x2c0, 288, 0, 399 }, -{ 0x1c0, 288, 0, 400 }, -{ 0x20, 288, 0, 410 }, -{ 0xa0, 288, 0, 408 }, -{ 0x60, 288, 0, 409 }, -{ 0x10, 288, 0, 419 }, -{ 0x50, 288, 0, 417 }, -{ 0x30, 288, 0, 418 }, -{ 0x8, 288, 0, 428 }, -{ 0x28, 288, 0, 426 }, -{ 0x18, 288, 0, 427 }, -{ 0x4, 288, 0, 435 }, -{ 0x2, 288, 0, 436 }, -{ 0x1, 288, 0, 437 }, -{ 0x140, 290, 0, 395 }, -{ 0x540, 290, 0, 393 }, -{ 0x340, 290, 0, 394 }, -{ 0xc0, 290, 0, 404 }, -{ 0x2c0, 290, 0, 402 }, -{ 0x1c0, 290, 0, 403 }, -{ 0x20, 290, 0, 413 }, -{ 0xa0, 290, 0, 411 }, -{ 0x60, 290, 0, 412 }, -{ 0x10, 290, 0, 422 }, -{ 0x50, 290, 0, 420 }, -{ 0x30, 290, 0, 421 }, -{ 0x8, 290, 0, 431 }, -{ 0x28, 290, 0, 429 }, -{ 0x18, 290, 0, 430 }, -{ 0x4, 290, 0, 438 }, -{ 0x2, 290, 0, 439 }, -{ 0x1, 290, 0, 440 }, -{ 0x140, 292, 0, 398 }, -{ 0x540, 292, 0, 396 }, -{ 0x340, 292, 0, 397 }, -{ 0xc0, 292, 0, 407 }, -{ 0x2c0, 292, 0, 405 }, -{ 0x1c0, 292, 0, 406 }, -{ 0x20, 292, 0, 416 }, -{ 0xa0, 292, 0, 414 }, -{ 0x60, 292, 0, 415 }, -{ 0x10, 292, 0, 425 }, -{ 0x50, 292, 0, 423 }, -{ 0x30, 292, 0, 424 }, -{ 0x8, 292, 0, 434 }, -{ 0x28, 292, 0, 432 }, -{ 0x18, 292, 0, 433 }, -{ 0x4, 292, 0, 441 }, -{ 0x2, 292, 0, 442 }, -{ 0x1, 292, 0, 443 }, -{ 0x1, 437, 0, 454 }, -{ 0x81, 437, 0, 444 }, -{ 0x41, 437, 0, 445 }, -{ 0x21, 437, 0, 446 }, -{ 0x11, 437, 0, 447 }, -{ 0x9, 437, 1, 449 }, -{ 0x9, 438, 0, 448 }, -{ 0x5, 437, 1, 451 }, -{ 0x5, 438, 0, 450 }, -{ 0x3, 437, 1, 453 }, -{ 0x3, 438, 0, 452 }, -{ 0x80, 446, 0, 455 }, -{ 0x40, 446, 0, 456 }, -{ 0x20, 446, 0, 457 }, -{ 0x10, 446, 0, 458 }, -{ 0x8, 446, 1, 460 }, -{ 0x4, 447, 0, 459 }, -{ 0x4, 446, 1, 462 }, -{ 0x2, 447, 0, 461 }, -{ 0x2, 446, 1, 464 }, -{ 0x1, 447, 0, 463 }, -{ 0x1, 446, 0, 465 }, -{ 0x80, 440, 0, 466 }, -{ 0x40, 440, 0, 467 }, -{ 0x20, 440, 0, 468 }, -{ 0x10, 440, 0, 469 }, -{ 0x8, 440, 1, 471 }, -{ 0x4, 441, 0, 470 }, -{ 0x4, 440, 1, 473 }, -{ 0x2, 441, 0, 472 }, -{ 0x2, 440, 1, 475 }, -{ 0x1, 441, 0, 474 }, -{ 0x1, 440, 0, 476 }, -{ 0x80, 443, 0, 477 }, -{ 0x40, 443, 0, 478 }, -{ 0x20, 443, 0, 479 }, -{ 0x10, 443, 0, 480 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3017 }, -{ 0x6, 108, 0, 3016 }, -{ 0xa, 101, 1, 3143 }, -{ 0x12, 102, 1, 3142 }, -{ 0x24, 102, 1, 3140 }, -{ 0x5, 109, 1, 3141 }, -{ 0x71, 41, 1, 18 }, -{ 0x31, 42, 0, 17 }, -{ 0x1a, 101, 1, 3015 }, -{ 0x32, 102, 1, 3014 }, -{ 0x1a, 108, 1, 3012 }, -{ 0x7, 123, 0, 3013 }, -{ 0x6, 101, 1, 3303 }, -{ 0x6, 102, 1, 3302 }, -{ 0xc, 102, 1, 3300 }, -{ 0x3, 109, 0, 3301 }, -{ 0x1, 101, 1, 3319 }, -{ 0x1, 102, 1, 3318 }, -{ 0x1, 103, 1, 3317 }, -{ 0x1, 104, 1, 3316 }, -{ 0x1, 105, 1, 3315 }, -{ 0x1, 106, 1, 3314 }, -{ 0x1, 107, 1, 3313 }, -{ 0x1, 108, 0, 3312 }, -{ 0x3, 101, 1, 3311 }, -{ 0x3, 102, 1, 3310 }, -{ 0x3, 103, 1, 3309 }, -{ 0x3, 104, 1, 3308 }, -{ 0x3, 105, 1, 3307 }, -{ 0x3, 106, 1, 3306 }, -{ 0x3, 107, 1, 3305 }, -{ 0x3, 108, 0, 3304 }, -{ 0x8, 68, 1, 3183 }, -{ 0x8, 69, 1, 3182 }, -{ 0x2, 74, 1, 3177 }, -{ 0x2, 75, 1, 3176 }, -{ 0x1, 77, 1, 3181 }, -{ 0x1, 78, 1, 3180 }, -{ 0x1, 79, 1, 3179 }, -{ 0x1, 80, 1, 3178 }, -{ 0xf, 41, 1, 30 }, -{ 0x7, 42, 0, 29 }, -{ 0x18, 68, 1, 3175 }, -{ 0x18, 69, 1, 3174 }, -{ 0x6, 74, 1, 3169 }, -{ 0x6, 75, 1, 3168 }, -{ 0x3, 77, 1, 3173 }, -{ 0x3, 78, 1, 3172 }, -{ 0x3, 79, 1, 3171 }, -{ 0x3, 80, 1, 3170 }, -{ 0x1b, 41, 0, 15 }, -{ 0x14, 68, 1, 3163 }, -{ 0x22, 69, 1, 3160 }, -{ 0x44, 69, 1, 3162 }, -{ 0xa, 76, 1, 3161 }, -{ 0x35, 41, 0, 13 }, -{ 0x34, 68, 1, 3027 }, -{ 0xc4, 69, 1, 3026 }, -{ 0x38, 75, 1, 3024 }, -{ 0xe, 86, 0, 3025 }, -{ 0xc, 68, 1, 3323 }, -{ 0xa, 69, 1, 3320 }, -{ 0x14, 69, 1, 3322 }, -{ 0x6, 76, 0, 3321 }, -{ 0x2, 68, 1, 3039 }, -{ 0x2, 69, 1, 3038 }, -{ 0x4, 74, 1, 3037 }, -{ 0x4, 75, 0, 3036 }, -{ 0x12, 68, 1, 3035 }, -{ 0x42, 69, 1, 3034 }, -{ 0xc, 74, 1, 3033 }, -{ 0xc, 75, 0, 3032 }, -{ 0xa, 68, 1, 3167 }, -{ 0x12, 69, 1, 3166 }, -{ 0x24, 69, 1, 3164 }, -{ 0x5, 76, 1, 3165 }, -{ 0x1d, 41, 1, 26 }, -{ 0xd, 42, 0, 25 }, -{ 0x1a, 68, 1, 3031 }, -{ 0x32, 69, 1, 3030 }, -{ 0x34, 75, 1, 3028 }, -{ 0x7, 86, 0, 3029 }, -{ 0x6, 68, 1, 3327 }, -{ 0x6, 69, 1, 3326 }, -{ 0xc, 69, 1, 3324 }, -{ 0x3, 76, 0, 3325 }, -{ 0x1, 68, 1, 3343 }, -{ 0x1, 69, 1, 3342 }, -{ 0x1, 70, 1, 3341 }, -{ 0x1, 71, 1, 3340 }, -{ 0x1, 72, 1, 3339 }, -{ 0x1, 73, 1, 3338 }, -{ 0x1, 74, 1, 3337 }, -{ 0x1, 75, 0, 3336 }, -{ 0x3, 68, 1, 3335 }, -{ 0x3, 69, 1, 3334 }, -{ 0x3, 70, 1, 3333 }, -{ 0x3, 71, 1, 3332 }, -{ 0x3, 72, 1, 3331 }, -{ 0x3, 73, 1, 3330 }, -{ 0x3, 74, 1, 3329 }, -{ 0x3, 75, 0, 3328 }, -{ 0x28, 96, 1, 3191 }, -{ 0x44, 97, 1, 3186 }, -{ 0x88, 97, 1, 3190 }, -{ 0x44, 98, 1, 3185 }, -{ 0x88, 98, 1, 3189 }, -{ 0x44, 99, 1, 3184 }, -{ 0x88, 99, 1, 3188 }, -{ 0x28, 100, 0, 3187 }, -{ 0x68, 96, 1, 3047 }, -{ 0x188, 97, 1, 3046 }, -{ 0x188, 98, 1, 3045 }, -{ 0x188, 99, 1, 3044 }, -{ 0x38, 119, 1, 3043 }, -{ 0x38, 120, 1, 3042 }, -{ 0x38, 121, 1, 3041 }, -{ 0x38, 122, 0, 3040 }, -{ 0x18, 96, 1, 3351 }, -{ 0x14, 97, 1, 3346 }, -{ 0x28, 97, 1, 3350 }, -{ 0x14, 98, 1, 3345 }, -{ 0x28, 98, 1, 3349 }, -{ 0x14, 99, 1, 3344 }, -{ 0x28, 99, 1, 3348 }, -{ 0x18, 100, 0, 3347 }, -{ 0x14, 96, 1, 3199 }, -{ 0x24, 97, 1, 3198 }, -{ 0x48, 97, 1, 3194 }, -{ 0x24, 98, 1, 3197 }, -{ 0x48, 98, 1, 3193 }, -{ 0x24, 99, 1, 3196 }, -{ 0x48, 99, 1, 3192 }, -{ 0x14, 100, 0, 3195 }, -{ 0x34, 96, 1, 3055 }, -{ 0x64, 97, 1, 3054 }, -{ 0x64, 98, 1, 3053 }, -{ 0x64, 99, 1, 3052 }, -{ 0x1c, 119, 1, 3051 }, -{ 0x1c, 120, 1, 3050 }, -{ 0x1c, 121, 1, 3049 }, -{ 0x1c, 122, 0, 3048 }, -{ 0xc, 96, 1, 3359 }, -{ 0xc, 97, 1, 3358 }, -{ 0x18, 97, 1, 3354 }, -{ 0xc, 98, 1, 3357 }, -{ 0x18, 98, 1, 3353 }, -{ 0xc, 99, 1, 3356 }, -{ 0x18, 99, 1, 3352 }, -{ 0xc, 100, 0, 3355 }, -{ 0xa, 96, 1, 3207 }, -{ 0x11, 97, 1, 3202 }, -{ 0x22, 97, 1, 3206 }, -{ 0x11, 98, 1, 3201 }, -{ 0x22, 98, 1, 3205 }, -{ 0x11, 99, 1, 3200 }, -{ 0x22, 99, 1, 3204 }, -{ 0xa, 100, 0, 3203 }, -{ 0x1a, 96, 1, 3063 }, -{ 0x62, 97, 1, 3062 }, -{ 0x62, 98, 1, 3061 }, -{ 0x62, 99, 1, 3060 }, -{ 0xe, 119, 1, 3059 }, -{ 0xe, 120, 1, 3058 }, -{ 0xe, 121, 1, 3057 }, -{ 0xe, 122, 0, 3056 }, -{ 0x6, 96, 1, 3367 }, -{ 0x5, 97, 1, 3362 }, -{ 0xa, 97, 1, 3366 }, -{ 0x5, 98, 1, 3361 }, -{ 0xa, 98, 1, 3365 }, -{ 0x5, 99, 1, 3360 }, -{ 0xa, 99, 1, 3364 }, -{ 0x6, 100, 0, 3363 }, -{ 0x5, 96, 1, 3215 }, -{ 0x9, 97, 1, 3214 }, -{ 0x12, 97, 1, 3210 }, -{ 0x9, 98, 1, 3213 }, -{ 0x12, 98, 1, 3209 }, -{ 0x9, 99, 1, 3212 }, -{ 0x12, 99, 1, 3208 }, -{ 0x5, 100, 0, 3211 }, -{ 0xd, 96, 1, 3071 }, -{ 0x19, 97, 1, 3070 }, -{ 0x19, 98, 1, 3069 }, -{ 0x19, 99, 1, 3068 }, -{ 0x7, 119, 1, 3067 }, -{ 0x7, 120, 1, 3066 }, -{ 0x7, 121, 1, 3065 }, -{ 0x7, 122, 0, 3064 }, -{ 0x3, 96, 1, 3375 }, -{ 0x3, 97, 1, 3374 }, -{ 0x6, 97, 1, 3370 }, -{ 0x3, 98, 1, 3373 }, -{ 0x6, 98, 1, 3369 }, -{ 0x3, 99, 1, 3372 }, -{ 0x6, 99, 1, 3368 }, -{ 0x3, 100, 0, 3371 }, -{ 0x28, 63, 1, 3223 }, -{ 0x44, 64, 1, 3218 }, -{ 0x88, 64, 1, 3222 }, -{ 0x44, 65, 1, 3217 }, -{ 0x88, 65, 1, 3221 }, -{ 0x44, 66, 1, 3216 }, -{ 0x88, 66, 1, 3220 }, -{ 0x28, 67, 0, 3219 }, -{ 0x68, 63, 1, 3079 }, -{ 0x188, 64, 1, 3078 }, -{ 0x188, 65, 1, 3077 }, -{ 0x188, 66, 1, 3076 }, -{ 0x38, 82, 1, 3075 }, -{ 0x38, 83, 1, 3074 }, -{ 0x38, 84, 1, 3073 }, -{ 0x38, 85, 0, 3072 }, -{ 0x18, 63, 1, 3383 }, -{ 0x14, 64, 1, 3378 }, -{ 0x28, 64, 1, 3382 }, -{ 0x14, 65, 1, 3377 }, -{ 0x28, 65, 1, 3381 }, -{ 0x14, 66, 1, 3376 }, -{ 0x28, 66, 1, 3380 }, -{ 0x18, 67, 0, 3379 }, -{ 0x14, 63, 1, 3231 }, -{ 0x24, 64, 1, 3230 }, -{ 0x48, 64, 1, 3226 }, -{ 0x24, 65, 1, 3229 }, -{ 0x48, 65, 1, 3225 }, -{ 0x24, 66, 1, 3228 }, -{ 0x48, 66, 1, 3224 }, -{ 0x14, 67, 0, 3227 }, -{ 0x34, 63, 1, 3087 }, -{ 0x64, 64, 1, 3086 }, -{ 0x64, 65, 1, 3085 }, -{ 0x64, 66, 1, 3084 }, -{ 0x1c, 82, 1, 3083 }, -{ 0x1c, 83, 1, 3082 }, -{ 0x1c, 84, 1, 3081 }, -{ 0x1c, 85, 0, 3080 }, -{ 0xc, 63, 1, 3391 }, -{ 0xc, 64, 1, 3390 }, -{ 0x18, 64, 1, 3386 }, -{ 0xc, 65, 1, 3389 }, -{ 0x18, 65, 1, 3385 }, -{ 0xc, 66, 1, 3388 }, -{ 0x18, 66, 1, 3384 }, -{ 0xc, 67, 0, 3387 }, -{ 0xa, 63, 1, 3239 }, -{ 0x11, 64, 1, 3234 }, -{ 0x22, 64, 1, 3238 }, -{ 0x11, 65, 1, 3233 }, -{ 0x22, 65, 1, 3237 }, -{ 0x11, 66, 1, 3232 }, -{ 0x22, 66, 1, 3236 }, -{ 0xa, 67, 0, 3235 }, -{ 0x1a, 63, 1, 3095 }, -{ 0x62, 64, 1, 3094 }, -{ 0x62, 65, 1, 3093 }, -{ 0x62, 66, 1, 3092 }, -{ 0xe, 82, 1, 3091 }, -{ 0xe, 83, 1, 3090 }, -{ 0xe, 84, 1, 3089 }, -{ 0xe, 85, 0, 3088 }, -{ 0x6, 63, 1, 3399 }, -{ 0x5, 64, 1, 3394 }, -{ 0xa, 64, 1, 3398 }, -{ 0x5, 65, 1, 3393 }, -{ 0xa, 65, 1, 3397 }, -{ 0x5, 66, 1, 3392 }, -{ 0xa, 66, 1, 3396 }, -{ 0x6, 67, 0, 3395 }, -{ 0x5, 63, 1, 3247 }, -{ 0x9, 64, 1, 3246 }, -{ 0x12, 64, 1, 3242 }, -{ 0x9, 65, 1, 3245 }, -{ 0x12, 65, 1, 3241 }, -{ 0x9, 66, 1, 3244 }, -{ 0x12, 66, 1, 3240 }, -{ 0x5, 67, 0, 3243 }, -{ 0xd, 63, 1, 3103 }, -{ 0x19, 64, 1, 3102 }, -{ 0x19, 65, 1, 3101 }, -{ 0x19, 66, 1, 3100 }, -{ 0x7, 82, 1, 3099 }, -{ 0x7, 83, 1, 3098 }, -{ 0x7, 84, 1, 3097 }, -{ 0x7, 85, 0, 3096 }, -{ 0x3, 63, 1, 3407 }, -{ 0x3, 64, 1, 3406 }, -{ 0x6, 64, 1, 3402 }, -{ 0x3, 65, 1, 3405 }, -{ 0x6, 65, 1, 3401 }, -{ 0x3, 66, 1, 3404 }, -{ 0x6, 66, 1, 3400 }, -{ 0x3, 67, 0, 3403 }, -{ 0x8, 87, 1, 3271 }, -{ 0x8, 88, 1, 3270 }, -{ 0x2, 89, 1, 3269 }, -{ 0x2, 90, 1, 3268 }, -{ 0x2, 91, 1, 3267 }, -{ 0x2, 92, 1, 3266 }, -{ 0x2, 93, 1, 3265 }, -{ 0x2, 94, 0, 3264 }, -{ 0x18, 87, 1, 3263 }, -{ 0x18, 88, 1, 3262 }, -{ 0x6, 89, 1, 3261 }, -{ 0x6, 90, 1, 3260 }, -{ 0x6, 91, 1, 3259 }, -{ 0x6, 92, 1, 3258 }, -{ 0x6, 93, 1, 3257 }, -{ 0x6, 94, 0, 3256 }, -{ 0x14, 87, 1, 3251 }, -{ 0x22, 88, 1, 3248 }, -{ 0x44, 88, 1, 3250 }, -{ 0xa, 95, 0, 3249 }, -{ 0x34, 87, 1, 3107 }, -{ 0xc4, 88, 1, 3106 }, -{ 0x38, 94, 1, 3104 }, -{ 0xe, 118, 0, 3105 }, -{ 0xc, 87, 1, 3411 }, -{ 0xa, 88, 1, 3408 }, -{ 0x14, 88, 1, 3410 }, -{ 0x6, 95, 0, 3409 }, -{ 0x2, 87, 1, 3119 }, -{ 0x2, 88, 1, 3118 }, -{ 0x4, 93, 1, 3117 }, -{ 0x4, 94, 0, 3116 }, -{ 0x12, 87, 1, 3115 }, -{ 0x42, 88, 1, 3114 }, -{ 0xc, 93, 1, 3113 }, -{ 0xc, 94, 0, 3112 }, -{ 0xa, 87, 1, 3255 }, -{ 0x12, 88, 1, 3254 }, -{ 0x24, 88, 1, 3252 }, -{ 0x5, 95, 0, 3253 }, -{ 0x1a, 87, 1, 3111 }, -{ 0x32, 88, 1, 3110 }, -{ 0x34, 94, 1, 3108 }, -{ 0x7, 118, 0, 3109 }, -{ 0x6, 87, 1, 3415 }, -{ 0x6, 88, 1, 3414 }, -{ 0xc, 88, 1, 3412 }, -{ 0x3, 95, 0, 3413 }, -{ 0x1, 87, 1, 3431 }, -{ 0x1, 88, 1, 3430 }, -{ 0x1, 89, 1, 3429 }, -{ 0x1, 90, 1, 3428 }, -{ 0x1, 91, 1, 3427 }, -{ 0x1, 92, 1, 3426 }, -{ 0x1, 93, 1, 3425 }, -{ 0x1, 94, 0, 3424 }, -{ 0x3, 87, 1, 3423 }, -{ 0x3, 88, 1, 3422 }, -{ 0x3, 89, 1, 3421 }, -{ 0x3, 90, 1, 3420 }, -{ 0x3, 91, 1, 3419 }, -{ 0x3, 92, 1, 3418 }, -{ 0x3, 93, 1, 3417 }, -{ 0x3, 94, 0, 3416 }, -{ 0x8, 54, 1, 3295 }, -{ 0x8, 55, 1, 3294 }, -{ 0x2, 56, 1, 3293 }, -{ 0x2, 57, 1, 3292 }, -{ 0x2, 58, 1, 3291 }, -{ 0x2, 59, 1, 3290 }, -{ 0x2, 60, 1, 3289 }, -{ 0x2, 61, 0, 3288 }, -{ 0x18, 54, 1, 3287 }, -{ 0x18, 55, 1, 3286 }, -{ 0x6, 56, 1, 3285 }, -{ 0x6, 57, 1, 3284 }, -{ 0x6, 58, 1, 3283 }, -{ 0x6, 59, 1, 3282 }, -{ 0x6, 60, 1, 3281 }, -{ 0x6, 61, 0, 3280 }, -{ 0x14, 54, 1, 3275 }, -{ 0x22, 55, 1, 3272 }, -{ 0x44, 55, 1, 3274 }, -{ 0xa, 62, 0, 3273 }, -{ 0x34, 54, 1, 3123 }, -{ 0xc4, 55, 1, 3122 }, -{ 0x38, 61, 1, 3120 }, -{ 0xe, 81, 0, 3121 }, -{ 0xc, 54, 1, 3435 }, -{ 0xa, 55, 1, 3432 }, -{ 0x14, 55, 1, 3434 }, -{ 0x6, 62, 0, 3433 }, -{ 0x2, 54, 1, 3135 }, -{ 0x2, 55, 1, 3134 }, -{ 0x4, 60, 1, 3133 }, -{ 0x4, 61, 0, 3132 }, -{ 0x12, 54, 1, 3131 }, -{ 0x42, 55, 1, 3130 }, -{ 0xc, 60, 1, 3129 }, -{ 0xc, 61, 0, 3128 }, -{ 0xa, 54, 1, 3279 }, -{ 0x12, 55, 1, 3278 }, -{ 0x24, 55, 1, 3276 }, -{ 0x5, 62, 0, 3277 }, -{ 0x1a, 54, 1, 3127 }, -{ 0x32, 55, 1, 3126 }, -{ 0x34, 61, 1, 3124 }, -{ 0x7, 81, 0, 3125 }, -{ 0x6, 54, 1, 3439 }, -{ 0x6, 55, 1, 3438 }, -{ 0xc, 55, 1, 3436 }, -{ 0x3, 62, 0, 3437 }, -{ 0x1, 54, 1, 3455 }, -{ 0x1, 55, 1, 3454 }, -{ 0x1, 56, 1, 3453 }, -{ 0x1, 57, 1, 3452 }, -{ 0x1, 58, 1, 3451 }, -{ 0x1, 59, 1, 3450 }, -{ 0x1, 60, 1, 3449 }, -{ 0x1, 61, 0, 3448 }, -{ 0x3, 54, 1, 3447 }, -{ 0x3, 55, 1, 3446 }, -{ 0x3, 56, 1, 3445 }, -{ 0x3, 57, 1, 3444 }, -{ 0x3, 58, 1, 3443 }, -{ 0x3, 59, 1, 3442 }, -{ 0x3, 60, 1, 3441 }, -{ 0x3, 61, 0, 3440 }, -{ 0x1, 4, 0, 3456 }, -{ 0x1, 314, 0, 3457 }, -{ 0x1, 401, 0, 3458 }, -{ 0x1, 396, 0, 3459 }, -{ 0x2, 380, 0, 3460 }, -{ 0x1, 380, 0, 3463 }, -{ 0x2, 379, 0, 3461 }, -{ 0x1, 379, 0, 3464 }, -{ 0x2, 378, 0, 3462 }, -{ 0x1, 378, 0, 3465 }, -{ 0x1, 377, 0, 3466 }, -{ 0x1, 376, 0, 3467 }, -{ 0x2, 375, 0, 3468 }, -{ 0x1, 375, 0, 3470 }, -{ 0x2, 374, 0, 3469 }, -{ 0x1, 374, 0, 3471 }, -{ 0x1, 404, 0, 3478 }, -{ 0x8, 403, 0, 3472 }, -{ 0x4, 403, 0, 3474 }, -{ 0x2, 403, 0, 3476 }, -{ 0x1, 403, 0, 3479 }, -{ 0x8, 402, 0, 3473 }, -{ 0x4, 402, 0, 3475 }, -{ 0x2, 402, 0, 3477 }, -{ 0x1, 402, 0, 3480 }, -{ 0x1, 373, 0, 3487 }, -{ 0x8, 372, 0, 3481 }, -{ 0x4, 372, 0, 3483 }, -{ 0x2, 372, 0, 3485 }, -{ 0x1, 372, 0, 3488 }, -{ 0x8, 371, 0, 3482 }, -{ 0x4, 371, 0, 3484 }, -{ 0x2, 371, 1, 3486 }, -{ 0x4, 144, 0, 2180 }, -{ 0x1, 371, 0, 3489 }, -{ 0x1, 6, 0, 3490 }, -{ 0x1, 7, 0, 3491 }, -{ 0x1, 313, 0, 3492 }, -{ 0x1, 488, 0, 3493 }, -{ 0x1, 368, 0, 3494 }, -{ 0x1, 13, 0, 3495 }, -{ 0x1, 11, 0, 3496 }, -{ 0x1, 454, 0, 3497 }, -{ 0x1, 416, 0, 3498 }, -{ 0x1, 415, 0, 3499 }, -{ 0x1, 487, 0, 3500 }, -{ 0x1, 367, 0, 3501 }, -{ 0x1, 12, 0, 3502 }, -{ 0x1, 10, 0, 3503 }, -{ 0x1, 5, 0, 3504 }, -{ 0x1, 453, 0, 3505 }, -{ 0x1, 452, 0, 3506 }, -{ 0x1, 1, 0, 3507 }, -{ 0x1, 0, 0, 3508 }, -}; - diff --git a/opcodes/ia64-asmtab.h b/opcodes/ia64-asmtab.h deleted file mode 100644 index 28e346a9f9f..00000000000 --- a/opcodes/ia64-asmtab.h +++ /dev/null @@ -1,148 +0,0 @@ -/* ia64-asmtab.h -- Header for compacted IA-64 opcode tables. - Copyright (C) 1999-2024 Free Software Foundation, Inc. - Contributed by Bob Manson of Cygnus Support - - This file is part of the GNU opcodes library. - - This library is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3, or (at your option) - any later version. - - It is distributed in the hope that it will be useful, but WITHOUT - ANY WARRANTY; without even the implied warranty of MERCHANTABILITY - or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public - License for more details. - - You should have received a copy of the GNU General Public License - along with this file; see the file COPYING. If not, write to the - Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston, - MA 02110-1301, USA. */ - -#ifndef IA64_ASMTAB_H -#define IA64_ASMTAB_H - -#include "opcode/ia64.h" - -/* The primary opcode table is made up of the following: */ -struct ia64_main_table -{ - /* The entry in the string table that corresponds to the name of this - opcode. */ - unsigned short name_index; - - /* The type of opcode; corresponds to the TYPE field in - struct ia64_opcode. */ - unsigned char opcode_type; - - /* The number of outputs for this opcode. */ - unsigned char num_outputs; - - /* The base insn value for this opcode. It may be modified by completer= s. */ - ia64_insn opcode; - - /* The mask of valid bits in OPCODE. Zeros indicate operand fields. */ - ia64_insn mask; - - /* The operands of this instruction. Corresponds to the OPERANDS field - in struct ia64_opcode. */ - unsigned char operands[5]; - - /* The flags for this instruction. Corresponds to the FLAGS field in - struct ia64_opcode. */ - short flags; - - /* The tree of completers for this instruction; this is an offset into - completer_table. */ - short completers; -}; - -/* Each instruction has a set of possible "completers", or additional - suffixes that can alter the instruction's behavior, and which has - potentially different dependencies. - - The completer entries modify certain bits in the instruction opcode. - Which bits are to be modified are marked by the BITS, MASK and - OFFSET fields. The completer entry may also note dependencies for the - opcode. - - These completers are arranged in a DAG; the pointers are indexes - into the completer_table array. The completer DAG is searched by - find_completer () and ia64_find_matching_opcode (). - - Note that each completer needs to be applied in turn, so that if we - have the instruction - cmp.lt.unc - the completer entries for both "lt" and "unc" would need to be applied - to the opcode's value. - - Some instructions do not require any completers; these contain an - empty completer entry. Instructions that require a completer do - not contain an empty entry. - - Terminal completers (those completers that validly complete an - instruction) are marked by having the TERMINAL_COMPLETER flag set. - - Only dependencies listed in the terminal completer for an opcode are - considered to apply to that opcode instance. */ - -struct ia64_completer_table -{ - /* The bit value that this completer sets. */ - unsigned int bits; - - /* And its mask. 1s are bits that are to be modified in the - instruction. */ - unsigned int mask; - - /* The entry in the string table that corresponds to the name of this - completer. */ - unsigned short name_index; - - /* An alternative completer, or -1 if this is the end of the chain. */ - short alternative; - - /* A pointer to the DAG of completers that can potentially follow - this one, or -1. */ - short subentries; - - /* The bit offset in the instruction where BITS and MASK should be - applied. */ - unsigned char offset : 7; - - unsigned char terminal_completer : 1; - - /* Index into the dependency list table */ - short dependencies; -}; - -/* This contains sufficient information for the disassembler to resolve - the complete name of the original instruction. */ -struct ia64_dis_names -{ - /* COMPLETER_INDEX represents the tree of completers that make up - the instruction. The LSB represents the top of the tree for the - specified instruction. - - A 0 bit indicates to go to the next alternate completer via the - alternative field; a 1 bit indicates that the current completer - is part of the instruction, and to go down the subentries index. - We know we've reached the final completer when we run out of 1 - bits. - - There is always at least one 1 bit. */ - unsigned int completer_index ; - - /* The index in the main_table[] array for the instruction. */ - unsigned short insn_index : 11; - - /* If set, the next entry in this table is an alternate possibility - for this instruction encoding. Which one to use is determined by - the instruction type and other factors (see opcode_verify ()). */ - unsigned int next_flag : 1; - - /* The disassembly priority of this entry among instructions. */ - unsigned short priority; -}; - -#endif diff --git a/opcodes/ia64-dis.c b/opcodes/ia64-dis.c deleted file mode 100644 index c478653734f..00000000000 --- a/opcodes/ia64-dis.c +++ /dev/null @@ -1,320 +0,0 @@ -/* ia64-dis.c -- Disassemble ia64 instructions - Copyright (C) 1998-2024 Free Software Foundation, Inc. - Contributed by David Mosberger-Tang - - This file is part of the GNU opcodes library. - - This library is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3, or (at your option) - any later version. - - It is distributed in the hope that it will be useful, but WITHOUT - ANY WARRANTY; without even the implied warranty of MERCHANTABILITY - or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public - License for more details. - - You should have received a copy of the GNU General Public License - along with this file; see the file COPYING. If not, write to the - Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA - 02110-1301, USA. */ - -#include "sysdep.h" -#include - -#include "disassemble.h" -#include "opcode/ia64.h" - -#define NELEMS(a) ((int) (sizeof (a) / sizeof (a[0]))) - -/* Disassemble ia64 instruction. */ - -/* Return the instruction type for OPCODE found in unit UNIT. */ - -static enum ia64_insn_type -unit_to_type (ia64_insn opcode, enum ia64_unit unit) -{ - enum ia64_insn_type type; - int op; - - op =3D IA64_OP (opcode); - - if (op >=3D 8 && (unit =3D=3D IA64_UNIT_I || unit =3D=3D IA64_UNIT_M)) - { - type =3D IA64_TYPE_A; - } - else - { - switch (unit) - { - case IA64_UNIT_I: - type =3D IA64_TYPE_I; break; - case IA64_UNIT_M: - type =3D IA64_TYPE_M; break; - case IA64_UNIT_B: - type =3D IA64_TYPE_B; break; - case IA64_UNIT_F: - type =3D IA64_TYPE_F; break; - case IA64_UNIT_L: - case IA64_UNIT_X: - type =3D IA64_TYPE_X; break; - default: - type =3D -1; - } - } - return type; -} - -int -print_insn_ia64 (bfd_vma memaddr, struct disassemble_info *info) -{ - ia64_insn t0, t1, slot[3], template_val, s_bit, insn; - int slotnum, j, status, need_comma, retval, slot_multiplier; - const struct ia64_operand *odesc; - const struct ia64_opcode *idesc; - const char *err, *str, *tname; - uint64_t value; - bfd_byte bundle[16]; - enum ia64_unit unit; - char regname[16]; - - if (info->bytes_per_line =3D=3D 0) - info->bytes_per_line =3D 6; - info->display_endian =3D info->endian; - - slot_multiplier =3D info->bytes_per_line; - retval =3D slot_multiplier; - - slotnum =3D (((long) memaddr) & 0xf) / slot_multiplier; - if (slotnum > 2) - return -1; - - memaddr -=3D (memaddr & 0xf); - status =3D (*info->read_memory_func) (memaddr, bundle, sizeof (bundle), = info); - if (status !=3D 0) - { - (*info->memory_error_func) (status, memaddr, info); - return -1; - } - /* bundles are always in little-endian byte order */ - t0 =3D bfd_getl64 (bundle); - t1 =3D bfd_getl64 (bundle + 8); - s_bit =3D t0 & 1; - template_val =3D (t0 >> 1) & 0xf; - slot[0] =3D (t0 >> 5) & 0x1ffffffffffLL; - slot[1] =3D ((t0 >> 46) & 0x3ffff) | ((t1 & 0x7fffff) << 18); - slot[2] =3D (t1 >> 23) & 0x1ffffffffffLL; - - tname =3D ia64_templ_desc[template_val].name; - if (slotnum =3D=3D 0) - (*info->fprintf_func) (info->stream, "[%s] ", tname); - else - (*info->fprintf_func) (info->stream, " "); - - unit =3D ia64_templ_desc[template_val].exec_unit[slotnum]; - - if (template_val =3D=3D 2 && slotnum =3D=3D 1) - { - /* skip L slot in MLI template: */ - slotnum =3D 2; - retval +=3D slot_multiplier; - } - - insn =3D slot[slotnum]; - - if (unit =3D=3D IA64_UNIT_NIL) - goto decoding_failed; - - idesc =3D ia64_dis_opcode (insn, unit_to_type (insn, unit)); - if (idesc =3D=3D NULL) - goto decoding_failed; - - /* print predicate, if any: */ - - if ((idesc->flags & IA64_OPCODE_NO_PRED) - || (insn & 0x3f) =3D=3D 0) - (*info->fprintf_func) (info->stream, " "); - else - (*info->fprintf_func) (info->stream, "(p%02d) ", (int)(insn & 0x3f)); - - /* now the actual instruction: */ - - (*info->fprintf_func) (info->stream, "%s", idesc->name); - if (idesc->operands[0]) - (*info->fprintf_func) (info->stream, " "); - - need_comma =3D 0; - for (j =3D 0; j < NELEMS (idesc->operands) && idesc->operands[j]; ++j) - { - odesc =3D elf64_ia64_operands + idesc->operands[j]; - - if (need_comma) - (*info->fprintf_func) (info->stream, ","); - - if (odesc - elf64_ia64_operands =3D=3D IA64_OPND_IMMU64) - { - /* special case of 64 bit immediate load: */ - value =3D ((insn >> 13) & 0x7f) | (((insn >> 27) & 0x1ff) << 7) - | (((insn >> 22) & 0x1f) << 16) | (((insn >> 21) & 0x1) << 21) - | (slot[1] << 22) | (((insn >> 36) & 0x1) << 63); - } - else if (odesc - elf64_ia64_operands =3D=3D IA64_OPND_IMMU62) - { - /* 62-bit immediate for nop.x/break.x */ - value =3D ((slot[1] & 0x1ffffffffffLL) << 21) - | (((insn >> 36) & 0x1) << 20) - | ((insn >> 6) & 0xfffff); - } - else if (odesc - elf64_ia64_operands =3D=3D IA64_OPND_TGT64) - { - /* 60-bit immediate for long branches. */ - value =3D (((insn >> 13) & 0xfffff) - | (((insn >> 36) & 1) << 59) - | (((slot[1] >> 2) & 0x7fffffffffLL) << 20)) << 4; - } - else - { - err =3D (*odesc->extract) (odesc, insn, &value); - if (err) - { - (*info->fprintf_func) (info->stream, "%s", err); - goto done; - } - } - - switch (odesc->op_class) - { - case IA64_OPND_CLASS_CST: - (*info->fprintf_func) (info->stream, "%s", odesc->str); - break; - - case IA64_OPND_CLASS_REG: - if (odesc->str[0] =3D=3D 'a' && odesc->str[1] =3D=3D 'r') - { - switch (value) - { - case 0: case 1: case 2: case 3: - case 4: case 5: case 6: case 7: - sprintf (regname, "ar.k%u", (unsigned int) value); - break; - case 16: strcpy (regname, "ar.rsc"); break; - case 17: strcpy (regname, "ar.bsp"); break; - case 18: strcpy (regname, "ar.bspstore"); break; - case 19: strcpy (regname, "ar.rnat"); break; - case 21: strcpy (regname, "ar.fcr"); break; - case 24: strcpy (regname, "ar.eflag"); break; - case 25: strcpy (regname, "ar.csd"); break; - case 26: strcpy (regname, "ar.ssd"); break; - case 27: strcpy (regname, "ar.cflg"); break; - case 28: strcpy (regname, "ar.fsr"); break; - case 29: strcpy (regname, "ar.fir"); break; - case 30: strcpy (regname, "ar.fdr"); break; - case 32: strcpy (regname, "ar.ccv"); break; - case 36: strcpy (regname, "ar.unat"); break; - case 40: strcpy (regname, "ar.fpsr"); break; - case 44: strcpy (regname, "ar.itc"); break; - case 45: strcpy (regname, "ar.ruc"); break; - case 64: strcpy (regname, "ar.pfs"); break; - case 65: strcpy (regname, "ar.lc"); break; - case 66: strcpy (regname, "ar.ec"); break; - default: - sprintf (regname, "ar%u", (unsigned int) value); - break; - } - (*info->fprintf_func) (info->stream, "%s", regname); - } - else if (odesc->str[0] =3D=3D 'c' && odesc->str[1] =3D=3D 'r') - { - switch (value) - { - case 0: strcpy (regname, "cr.dcr"); break; - case 1: strcpy (regname, "cr.itm"); break; - case 2: strcpy (regname, "cr.iva"); break; - case 8: strcpy (regname, "cr.pta"); break; - case 16: strcpy (regname, "cr.ipsr"); break; - case 17: strcpy (regname, "cr.isr"); break; - case 19: strcpy (regname, "cr.iip"); break; - case 20: strcpy (regname, "cr.ifa"); break; - case 21: strcpy (regname, "cr.itir"); break; - case 22: strcpy (regname, "cr.iipa"); break; - case 23: strcpy (regname, "cr.ifs"); break; - case 24: strcpy (regname, "cr.iim"); break; - case 25: strcpy (regname, "cr.iha"); break; - case 26: strcpy (regname, "cr.iib0"); break; - case 27: strcpy (regname, "cr.iib1"); break; - case 64: strcpy (regname, "cr.lid"); break; - case 65: strcpy (regname, "cr.ivr"); break; - case 66: strcpy (regname, "cr.tpr"); break; - case 67: strcpy (regname, "cr.eoi"); break; - case 68: strcpy (regname, "cr.irr0"); break; - case 69: strcpy (regname, "cr.irr1"); break; - case 70: strcpy (regname, "cr.irr2"); break; - case 71: strcpy (regname, "cr.irr3"); break; - case 72: strcpy (regname, "cr.itv"); break; - case 73: strcpy (regname, "cr.pmv"); break; - case 74: strcpy (regname, "cr.cmcv"); break; - case 80: strcpy (regname, "cr.lrr0"); break; - case 81: strcpy (regname, "cr.lrr1"); break; - default: - sprintf (regname, "cr%u", (unsigned int) value); - break; - } - (*info->fprintf_func) (info->stream, "%s", regname); - } - else - (*info->fprintf_func) (info->stream, "%s%d", odesc->str, (int)value= ); - break; - - case IA64_OPND_CLASS_IND: - (*info->fprintf_func) (info->stream, "%s[r%d]", odesc->str, (int)valu= e); - break; - - case IA64_OPND_CLASS_ABS: - str =3D 0; - if (odesc - elf64_ia64_operands =3D=3D IA64_OPND_MBTYPE4) - switch (value) - { - case 0x0: str =3D "@brcst"; break; - case 0x8: str =3D "@mix"; break; - case 0x9: str =3D "@shuf"; break; - case 0xa: str =3D "@alt"; break; - case 0xb: str =3D "@rev"; break; - } - - if (str) - (*info->fprintf_func) (info->stream, "%s", str); - else if (odesc->flags & IA64_OPND_FLAG_DECIMAL_SIGNED) - (*info->fprintf_func) (info->stream, "%lld", (long long) value); - else if (odesc->flags & IA64_OPND_FLAG_DECIMAL_UNSIGNED) - (*info->fprintf_func) (info->stream, "%llu", (long long) value); - else - (*info->fprintf_func) (info->stream, "0x%llx", (long long) value); - break; - - case IA64_OPND_CLASS_REL: - (*info->print_address_func) (memaddr + value, info); - break; - } - - need_comma =3D 1; - if (j + 1 =3D=3D idesc->num_outputs) - { - (*info->fprintf_func) (info->stream, "=3D"); - need_comma =3D 0; - } - } - if (slotnum + 1 =3D=3D ia64_templ_desc[template_val].group_boundary - || ((slotnum =3D=3D 2) && s_bit)) - (*info->fprintf_func) (info->stream, ";;"); - - done: - ia64_free_opcode ((struct ia64_opcode *)idesc); - failed: - if (slotnum =3D=3D 2) - retval +=3D 16 - 3*slot_multiplier; - return retval; - - decoding_failed: - (*info->fprintf_func) (info->stream, " data8 %#011llx", (long long)= insn); - goto failed; -} diff --git a/opcodes/ia64-gen.c b/opcodes/ia64-gen.c deleted file mode 100644 index f19e505bf7c..00000000000 --- a/opcodes/ia64-gen.c +++ /dev/null @@ -1,2865 +0,0 @@ -/* ia64-gen.c -- Generate a shrunk set of opcode tables - Copyright (C) 1999-2024 Free Software Foundation, Inc. - Written by Bob Manson, Cygnus Solutions, - - This file is part of the GNU opcodes library. - - This library is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3, or (at your option) - any later version. - - It is distributed in the hope that it will be useful, but WITHOUT - ANY WARRANTY; without even the implied warranty of MERCHANTABILITY - or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public - License for more details. - - You should have received a copy of the GNU General Public License - along with this file; see the file COPYING. If not, write to the - Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA - 02110-1301, USA. */ - - -/* While the ia64-opc-* set of opcode tables are easy to maintain, - they waste a tremendous amount of space. ia64-gen rearranges the - instructions into a directed acyclic graph (DAG) of instruction opcodes= and - their possible completers, as well as compacting the set of strings use= d. - - The disassembler table consists of a state machine that does - branching based on the bits of the opcode being disassembled. The - state encodings have been chosen to minimize the amount of space - required. - - The resource table is constructed based on some text dependency tables, - which are also easier to maintain than the final representation. */ - -#include "sysdep.h" -#include -#include -#include - -#include "libiberty.h" -#include "safe-ctype.h" -#include "getopt.h" -#include "ia64-opc.h" -#include "ia64-opc-a.c" -#include "ia64-opc-i.c" -#include "ia64-opc-m.c" -#include "ia64-opc-b.c" -#include "ia64-opc-f.c" -#include "ia64-opc-x.c" -#include "ia64-opc-d.c" - -#include -#define _(String) gettext (String) - -const char * program_name =3D NULL; -int debug =3D 0; - -#define NELEMS(a) (sizeof (a) / sizeof ((a)[0])) -#define tmalloc(X) (X *) xmalloc (sizeof (X)) - -typedef unsigned long long ci_t; -/* The main opcode table entry. Each entry is a unique combination of - name and flags (no two entries in the table compare as being equal - via opcodes_eq). */ -struct main_entry -{ - /* The base name of this opcode. The names of its completers are - appended to it to generate the full instruction name. */ - struct string_entry *name; - /* The base opcode entry. Which one to use is a fairly arbitrary choice; - it uses the first one passed to add_opcode_entry. */ - struct ia64_opcode *opcode; - /* The list of completers that can be applied to this opcode. */ - struct completer_entry *completers; - /* Next entry in the chain. */ - struct main_entry *next; - /* Index in the main table. */ - int main_index; -} *maintable, **ordered_table; - -int otlen =3D 0; -int ottotlen =3D 0; -int opcode_count =3D 0; - -/* The set of possible completers for an opcode. */ -struct completer_entry -{ - /* This entry's index in the ia64_completer_table[] array. */ - int num; - - /* The name of the completer. */ - struct string_entry *name; - - /* This entry's parent. */ - struct completer_entry *parent; - - /* Set if this is a terminal completer (occurs at the end of an - opcode). */ - int is_terminal; - - /* An alternative completer. */ - struct completer_entry *alternative; - - /* Additional completers that can be appended to this one. */ - struct completer_entry *addl_entries; - - /* Before compute_completer_bits () is invoked, this contains the actual - instruction opcode for this combination of opcode and completers. - Afterwards, it contains those bits that are different from its - parent opcode. */ - ia64_insn bits; - - /* Bits set to 1 correspond to those bits in this completer's opcode - that are different from its parent completer's opcode (or from - the base opcode if the entry is the root of the opcode's completer - list). This field is filled in by compute_completer_bits (). */ - ia64_insn mask; - - /* Index into the opcode dependency list, or -1 if none. */ - int dependencies; - - /* Remember the order encountered in the opcode tables. */ - int order; -}; - -/* One entry in the disassembler name table. */ -struct disent -{ - /* The index into the ia64_name_dis array for this entry. */ - int ournum; - - /* The index into the main_table[] array. */ - int insn; - - /* The disassmbly priority of this entry. */ - int priority; - - /* The completer_index value for this entry. */ - ci_t completer_index; - - /* How many other entries share this decode. */ - int nextcnt; - - /* The next entry sharing the same decode. */ - struct disent *nexte; - - /* The next entry in the name list. */ - struct disent *next_ent; -} *disinsntable =3D NULL; - -/* A state machine that will eventually be used to generate the - disassembler table. */ -struct bittree -{ - struct disent *disent; - struct bittree *bits[3]; /* 0, 1, and X (don't care). */ - int bits_to_skip; - int skip_flag; -} *bittree; - -/* The string table contains all opcodes and completers sorted in - alphabetical order. */ - -/* One entry in the string table. */ -struct string_entry -{ - /* The index in the ia64_strings[] array for this entry. */ - int num; - /* And the string. */ - char *s; -} **string_table =3D NULL; - -int strtablen =3D 0; -int strtabtotlen =3D 0; - -=0C -/* Resource dependency entries. */ -struct rdep -{ - char *name; /* Resource name. */ - unsigned - mode:2, /* RAW, WAW, or WAR. */ - semantics:3; /* Dependency semantics. */ - char *extra; /* Additional semantics info. */ - int nchks; - int total_chks; /* Total #of terminal insns. */ - int *chks; /* Insn classes which read (RAW), write - (WAW), or write (WAR) this rsrc. */ - int *chknotes; /* Dependency notes for each class. */ - int nregs; - int total_regs; /* Total #of terminal insns. */ - int *regs; /* Insn class which write (RAW), write2 - (WAW), or read (WAR) this rsrc. */ - int *regnotes; /* Dependency notes for each class. */ - - int waw_special; /* Special WAW dependency note. */ -} **rdeps =3D NULL; - -static int rdepslen =3D 0; -static int rdepstotlen =3D 0; - -/* Array of all instruction classes. */ -struct iclass -{ - char *name; /* Instruction class name. */ - int is_class; /* Is a class, not a terminal. */ - int nsubs; - int *subs; /* Other classes within this class. */ - int nxsubs; - int xsubs[4]; /* Exclusions. */ - char *comment; /* Optional comment. */ - int note; /* Optional note. */ - int terminal_resolved; /* Did we match this with anything? */ - int orphan; /* Detect class orphans. */ -} **ics =3D NULL; - -static int iclen =3D 0; -static int ictotlen =3D 0; - -/* An opcode dependency (chk/reg pair of dependency lists). */ -struct opdep -{ - int chk; /* index into dlists */ - int reg; /* index into dlists */ -} **opdeps; - -static int opdeplen =3D 0; -static int opdeptotlen =3D 0; - -/* A generic list of dependencies w/notes encoded. These may be shared. = */ -struct deplist -{ - int len; - unsigned short *deps; -} **dlists; - -static int dlistlen =3D 0; -static int dlisttotlen =3D 0; - - -static void fail (const char *, ...) ATTRIBUTE_PRINTF_1; -static void warn (const char *, ...) ATTRIBUTE_PRINTF_1; -static struct rdep * insert_resource (const char *, enum ia64_dependency_m= ode); -static int deplist_equals (struct deplist *, struct deplist *); -static short insert_deplist (int, unsigned short *); -static short insert_dependencies (int, unsigned short *, int, unsigned sho= rt *); -static void mark_used (struct iclass *, int); -static int fetch_insn_class (const char *, int); -static int sub_compare (const void *, const void *); -static void load_insn_classes (void); -static void parse_resource_users (const char *, int **, int *, int **); -static int parse_semantics (char *); -static void add_dep (const char *, const char *, const char *, int, int, c= har *, int); -static void load_depfile (const char *, enum ia64_dependency_mode); -static void load_dependencies (void); -static int irf_operand (int, const char *); -static int in_iclass_mov_x (struct ia64_opcode *, struct iclass *, const = char *, const char *); -static int in_iclass (struct ia64_opcode *, struct iclass *, const char *= , const char *, int *); -static int lookup_regindex (const char *, int); -static int lookup_specifier (const char *); -static void print_dependency_table (void); -static struct string_entry * insert_string (char *); -static void gen_dis_table (struct bittree *); -static void print_dis_table (void); -static void generate_disassembler (void); -static void print_string_table (void); -static int completer_entries_eq (struct completer_entry *, struct complet= er_entry *); -static struct completer_entry * insert_gclist (struct completer_entry *); -static int get_prefix_len (const char *); -static void compute_completer_bits (struct main_entry *, struct completer_= entry *); -static void collapse_redundant_completers (void); -static int insert_opcode_dependencies (struct ia64_opcode *, struct compl= eter_entry *); -static void insert_completer_entry (struct ia64_opcode *, struct main_entr= y *, int); -static void print_completer_entry (struct completer_entry *); -static void print_completer_table (void); -static int opcodes_eq (struct ia64_opcode *, struct ia64_opcode *); -static void add_opcode_entry (struct ia64_opcode *); -static void print_main_table (void); -static void shrink (struct ia64_opcode *); -static void print_version (void); -static void usage (FILE *, int); -static void finish_distable (void); -static void insert_bit_table_ent (struct bittree *, int, ia64_insn, ia64_i= nsn, int, int, ci_t); -static void add_dis_entry (struct bittree *, ia64_insn, ia64_insn, int, st= ruct completer_entry *, ci_t); -static void compact_distree (struct bittree *); -static struct bittree * make_bittree_entry (void); -static struct disent * add_dis_table_ent (struct disent *, int, int, ci_t); - -=0C -static void -fail (const char *message, ...) -{ - va_list args; - - va_start (args, message); - fprintf (stderr, _("%s: Error: "), program_name); - vfprintf (stderr, message, args); - va_end (args); - xexit (1); -} - -static void -warn (const char *message, ...) -{ - va_list args; - - va_start (args, message); - - fprintf (stderr, _("%s: Warning: "), program_name); - vfprintf (stderr, message, args); - va_end (args); -} - -/* Add NAME to the resource table, where TYPE is RAW or WAW. */ -static struct rdep * -insert_resource (const char *name, enum ia64_dependency_mode type) -{ - if (rdepslen =3D=3D rdepstotlen) - { - rdepstotlen +=3D 20; - rdeps =3D (struct rdep **) - xrealloc (rdeps, sizeof(struct rdep **) * rdepstotlen); - } - rdeps[rdepslen] =3D tmalloc(struct rdep); - memset((void *)rdeps[rdepslen], 0, sizeof(struct rdep)); - rdeps[rdepslen]->name =3D xstrdup (name); - rdeps[rdepslen]->mode =3D type; - rdeps[rdepslen]->waw_special =3D 0; - - return rdeps[rdepslen++]; -} - -/* Are the lists of dependency indexes equivalent? */ -static int -deplist_equals (struct deplist *d1, struct deplist *d2) -{ - int i; - - if (d1->len !=3D d2->len) - return 0; - - for (i =3D 0; i < d1->len; i++) - if (d1->deps[i] !=3D d2->deps[i]) - return 0; - - return 1; -} - -/* Add the list of dependencies to the list of dependency lists. */ -static short -insert_deplist (int count, unsigned short *deps) -{ - /* Sort the list, then see if an equivalent list exists already. - this results in a much smaller set of dependency lists. */ - struct deplist *list; - char set[0x10000]; - int i; - - memset ((void *)set, 0, sizeof (set)); - for (i =3D 0; i < count; i++) - set[deps[i]] =3D 1; - - count =3D 0; - for (i =3D 0; i < (int) sizeof (set); i++) - if (set[i]) - ++count; - - list =3D tmalloc (struct deplist); - list->len =3D count; - list->deps =3D (unsigned short *) malloc (sizeof (unsigned short) * coun= t); - - for (i =3D 0, count =3D 0; i < (int) sizeof (set); i++) - if (set[i]) - list->deps[count++] =3D i; - - /* Does this list exist already? */ - for (i =3D 0; i < dlistlen; i++) - if (deplist_equals (list, dlists[i])) - { - free (list->deps); - free (list); - return i; - } - - if (dlistlen =3D=3D dlisttotlen) - { - dlisttotlen +=3D 20; - dlists =3D (struct deplist **) - xrealloc (dlists, sizeof(struct deplist **) * dlisttotlen); - } - dlists[dlistlen] =3D list; - - return dlistlen++; -} - -/* Add the given pair of dependency lists to the opcode dependency list. = */ -static short -insert_dependencies (int nchks, unsigned short *chks, - int nregs, unsigned short *regs) -{ - struct opdep *pair; - int i; - int regind =3D -1; - int chkind =3D -1; - - if (nregs > 0) - regind =3D insert_deplist (nregs, regs); - if (nchks > 0) - chkind =3D insert_deplist (nchks, chks); - - for (i =3D 0; i < opdeplen; i++) - if (opdeps[i]->chk =3D=3D chkind - && opdeps[i]->reg =3D=3D regind) - return i; - - pair =3D tmalloc (struct opdep); - pair->chk =3D chkind; - pair->reg =3D regind; - - if (opdeplen =3D=3D opdeptotlen) - { - opdeptotlen +=3D 20; - opdeps =3D (struct opdep **) - xrealloc (opdeps, sizeof(struct opdep **) * opdeptotlen); - } - opdeps[opdeplen] =3D pair; - - return opdeplen++; -} - -static void -mark_used (struct iclass *ic, int clear_terminals) -{ - int i; - - ic->orphan =3D 0; - if (clear_terminals) - ic->terminal_resolved =3D 1; - - for (i =3D 0; i < ic->nsubs; i++) - mark_used (ics[ic->subs[i]], clear_terminals); - - for (i =3D 0; i < ic->nxsubs; i++) - mark_used (ics[ic->xsubs[i]], clear_terminals); -} - -/* Look up an instruction class; if CREATE make a new one if none found; - returns the index into the insn class array. */ -static int -fetch_insn_class (const char *full_name, int create) -{ - char *name; - char *notestr; - char *xsect; - char *comment; - int i, note =3D 0; - int ind; - int is_class =3D 0; - - if (startswith (full_name, "IC:")) - { - name =3D xstrdup (full_name + 3); - is_class =3D 1; - } - else - name =3D xstrdup (full_name); - - if ((xsect =3D strchr(name, '\\')) !=3D NULL) - is_class =3D 1; - if ((comment =3D strchr(name, '[')) !=3D NULL) - is_class =3D 1; - if ((notestr =3D strchr(name, '+')) !=3D NULL) - is_class =3D 1; - - /* If it is a composite class, then ignore comments and notes that come = after - the '\\', since they don't apply to the part we are decoding now. */ - if (xsect) - { - if (comment > xsect) - comment =3D 0; - if (notestr > xsect) - notestr =3D 0; - } - - if (notestr) - { - char *nextnotestr; - - note =3D atoi (notestr + 1); - if ((nextnotestr =3D strchr (notestr + 1, '+')) !=3D NULL) - { - if (strcmp (notestr, "+1+13") =3D=3D 0) - note =3D 13; - else if (!xsect || nextnotestr < xsect) - warn (_("multiple note %s not handled\n"), notestr); - } - } - - /* If it's a composite class, leave the notes and comments in place so t= hat - we have a unique name for the composite class. Otherwise, we remove - them. */ - if (!xsect) - { - if (notestr) - *notestr =3D 0; - if (comment) - *comment =3D 0; - } - - for (i =3D 0; i < iclen; i++) - if (strcmp (name, ics[i]->name) =3D=3D 0 - && ((comment =3D=3D NULL && ics[i]->comment =3D=3D NULL) - || (comment !=3D NULL && ics[i]->comment !=3D NULL - && strncmp (ics[i]->comment, comment, - strlen (ics[i]->comment)) =3D=3D 0)) - && note =3D=3D ics[i]->note) - return i; - - if (!create) - return -1; - - /* Doesn't exist, so make a new one. */ - if (iclen =3D=3D ictotlen) - { - ictotlen +=3D 20; - ics =3D (struct iclass **) - xrealloc (ics, (ictotlen) * sizeof (struct iclass *)); - } - - ind =3D iclen++; - ics[ind] =3D tmalloc (struct iclass); - memset ((void *)ics[ind], 0, sizeof (struct iclass)); - ics[ind]->name =3D xstrdup (name); - ics[ind]->is_class =3D is_class; - ics[ind]->orphan =3D 1; - - if (comment) - { - ics[ind]->comment =3D xstrdup (comment + 1); - ics[ind]->comment[strlen (ics[ind]->comment)-1] =3D 0; - } - - if (notestr) - ics[ind]->note =3D note; - - /* If it's a composite class, there's a comment or note, look for an - existing class or terminal with the same name. */ - if ((xsect || comment || notestr) && is_class) - { - /* First, populate with the class we're based on. */ - char *subname =3D name; - - if (xsect) - *xsect =3D 0; - else if (comment) - *comment =3D 0; - else if (notestr) - *notestr =3D 0; - - ics[ind]->nsubs =3D 1; - ics[ind]->subs =3D tmalloc(int); - ics[ind]->subs[0] =3D fetch_insn_class (subname, 1); - } - - while (xsect) - { - char *subname =3D xsect + 1; - - xsect =3D strchr (subname, '\\'); - if (xsect) - *xsect =3D 0; - ics[ind]->xsubs[ics[ind]->nxsubs] =3D fetch_insn_class (subname,1); - ics[ind]->nxsubs++; - } - free (name); - - return ind; -} - -/* For sorting a class's sub-class list only; make sure classes appear bef= ore - terminals. */ -static int -sub_compare (const void *e1, const void *e2) -{ - struct iclass *ic1 =3D ics[*(int *)e1]; - struct iclass *ic2 =3D ics[*(int *)e2]; - - if (ic1->is_class) - { - if (!ic2->is_class) - return -1; - } - else if (ic2->is_class) - return 1; - - return strcmp (ic1->name, ic2->name); -} - -static void -load_insn_classes (void) -{ - FILE *fp =3D fopen ("ia64-ic.tbl", "r"); - char buf[2048]; - - if (fp =3D=3D NULL) - fail (_("can't find ia64-ic.tbl for reading\n")); - - /* Discard first line. */ - if (fgets (buf, sizeof(buf), fp) =3D=3D NULL) - return; - - while (!feof (fp)) - { - int iclass; - char *name; - char *tmp; - - if (fgets (buf, sizeof (buf), fp) =3D=3D NULL) - break; - - while (ISSPACE (buf[strlen (buf) - 1])) - buf[strlen (buf) - 1] =3D '\0'; - - name =3D tmp =3D buf; - while (*tmp !=3D ';') - { - ++tmp; - if (tmp =3D=3D buf + sizeof (buf)) - abort (); - } - *tmp++ =3D '\0'; - - iclass =3D fetch_insn_class (name, 1); - ics[iclass]->is_class =3D 1; - - if (strcmp (name, "none") =3D=3D 0) - { - ics[iclass]->is_class =3D 0; - ics[iclass]->terminal_resolved =3D 1; - continue; - } - - /* For this class, record all sub-classes. */ - while (*tmp) - { - char *subname; - int sub; - - while (*tmp && ISSPACE (*tmp)) - { - ++tmp; - if (tmp =3D=3D buf + sizeof (buf)) - abort (); - } - subname =3D tmp; - while (*tmp && *tmp !=3D ',') - { - ++tmp; - if (tmp =3D=3D buf + sizeof (buf)) - abort (); - } - if (*tmp =3D=3D ',') - *tmp++ =3D '\0'; - - ics[iclass]->subs =3D (int *) - xrealloc ((void *)ics[iclass]->subs, - (ics[iclass]->nsubs + 1) * sizeof (int)); - - sub =3D fetch_insn_class (subname, 1); - ics[iclass]->subs =3D (int *) - xrealloc (ics[iclass]->subs, (ics[iclass]->nsubs + 1) * sizeof= (int)); - ics[iclass]->subs[ics[iclass]->nsubs++] =3D sub; - } - - /* Make sure classes come before terminals. */ - qsort ((void *)ics[iclass]->subs, - ics[iclass]->nsubs, sizeof(int), sub_compare); - } - fclose (fp); - - if (debug) - printf ("%d classes\n", iclen); -} - -/* Extract the insn classes from the given line. */ -static void -parse_resource_users (const char *ref, int **usersp, int *nusersp, - int **notesp) -{ - int c; - char *line =3D xstrdup (ref); - char *tmp =3D line; - int *users =3D *usersp; - int count =3D *nusersp; - int *notes =3D *notesp; - - c =3D *tmp; - while (c !=3D 0) - { - char *notestr; - int note; - char *xsect; - int iclass; - int create =3D 0; - char *name; - - while (ISSPACE (*tmp)) - ++tmp; - name =3D tmp; - while (*tmp && *tmp !=3D ',') - ++tmp; - c =3D *tmp; - *tmp++ =3D '\0'; - - xsect =3D strchr (name, '\\'); - if ((notestr =3D strstr (name, "+")) !=3D NULL) - { - char *nextnotestr; - - note =3D atoi (notestr + 1); - if ((nextnotestr =3D strchr (notestr + 1, '+')) !=3D NULL) - { - /* Note 13 always implies note 1. */ - if (strcmp (notestr, "+1+13") =3D=3D 0) - note =3D 13; - else if (!xsect || nextnotestr < xsect) - warn (_("multiple note %s not handled\n"), notestr); - } - if (!xsect) - *notestr =3D '\0'; - } - else - note =3D 0; - - /* All classes are created when the insn class table is parsed; - Individual instructions might not appear until the dependency tab= les - are read. Only create new classes if it's *not* an insn class, - or if it's a composite class (which wouldn't necessarily be in th= e IC - table). */ - if (! startswith (name, "IC:") || xsect !=3D NULL) - create =3D 1; - - iclass =3D fetch_insn_class (name, create); - if (iclass !=3D -1) - { - users =3D (int *) - xrealloc ((void *) users,(count + 1) * sizeof (int)); - notes =3D (int *) - xrealloc ((void *) notes,(count + 1) * sizeof (int)); - notes[count] =3D note; - users[count++] =3D iclass; - mark_used (ics[iclass], 0); - } - else if (debug) - printf("Class %s not found\n", name); - } - /* Update the return values. */ - *usersp =3D users; - *nusersp =3D count; - *notesp =3D notes; - - free (line); -} - -static int -parse_semantics (char *sem) -{ - if (strcmp (sem, "none") =3D=3D 0) - return IA64_DVS_NONE; - else if (strcmp (sem, "implied") =3D=3D 0) - return IA64_DVS_IMPLIED; - else if (strcmp (sem, "impliedF") =3D=3D 0) - return IA64_DVS_IMPLIEDF; - else if (strcmp (sem, "data") =3D=3D 0) - return IA64_DVS_DATA; - else if (strcmp (sem, "instr") =3D=3D 0) - return IA64_DVS_INSTR; - else if (strcmp (sem, "specific") =3D=3D 0) - return IA64_DVS_SPECIFIC; - else if (strcmp (sem, "stop") =3D=3D 0) - return IA64_DVS_STOP; - else - return IA64_DVS_OTHER; -} - -static void -add_dep (const char *name, const char *chk, const char *reg, - int semantics, int mode, char *extra, int flag) -{ - struct rdep *rs; - - rs =3D insert_resource (name, mode); - - parse_resource_users (chk, &rs->chks, &rs->nchks, &rs->chknotes); - parse_resource_users (reg, &rs->regs, &rs->nregs, &rs->regnotes); - - rs->semantics =3D semantics; - rs->extra =3D extra; - rs->waw_special =3D flag; -} - -static void -load_depfile (const char *filename, enum ia64_dependency_mode mode) -{ - FILE *fp =3D fopen (filename, "r"); - char buf[1024]; - - if (fp =3D=3D NULL) - fail (_("can't find %s for reading\n"), filename); - - if (fgets (buf, sizeof(buf), fp) =3D=3D NULL) - return; - while (!feof (fp)) - { - char *name, *tmp; - int semantics; - char *extra; - char *regp, *chkp; - - if (fgets (buf, sizeof(buf), fp) =3D=3D NULL) - break; - - while (ISSPACE (buf[strlen (buf) - 1])) - buf[strlen (buf) - 1] =3D '\0'; - - name =3D tmp =3D buf; - while (*tmp !=3D ';') - ++tmp; - *tmp++ =3D '\0'; - - while (ISSPACE (*tmp)) - ++tmp; - regp =3D tmp; - tmp =3D strchr (tmp, ';'); - if (!tmp) - abort (); - *tmp++ =3D 0; - while (ISSPACE (*tmp)) - ++tmp; - chkp =3D tmp; - tmp =3D strchr (tmp, ';'); - if (!tmp) - abort (); - *tmp++ =3D 0; - while (ISSPACE (*tmp)) - ++tmp; - semantics =3D parse_semantics (tmp); - extra =3D semantics =3D=3D IA64_DVS_OTHER ? xstrdup (tmp) : NULL; - - /* For WAW entries, if the chks and regs differ, we need to enter the - entries in both positions so that the tables will be parsed prope= rly, - without a lot of extra work. */ - if (mode =3D=3D IA64_DV_WAW && strcmp (regp, chkp) !=3D 0) - { - add_dep (name, chkp, regp, semantics, mode, extra, 0); - add_dep (name, regp, chkp, semantics, mode, extra, 1); - } - else - { - add_dep (name, chkp, regp, semantics, mode, extra, 0); - } - } - fclose (fp); -} - -static void -load_dependencies (void) -{ - load_depfile ("ia64-raw.tbl", IA64_DV_RAW); - load_depfile ("ia64-waw.tbl", IA64_DV_WAW); - load_depfile ("ia64-war.tbl", IA64_DV_WAR); - - if (debug) - printf ("%d RAW/WAW/WAR dependencies\n", rdepslen); -} - -/* Is the given operand an indirect register file operand? */ -static int -irf_operand (int op, const char *field) -{ - if (!field) - { - return op =3D=3D IA64_OPND_RR_R3 || op =3D=3D IA64_OPND_DBR_R3 - || op =3D=3D IA64_OPND_IBR_R3 || op =3D=3D IA64_OPND_PKR_R3 - || op =3D=3D IA64_OPND_PMC_R3 || op =3D=3D IA64_OPND_PMD_R3 - || op =3D=3D IA64_OPND_MSR_R3 || op =3D=3D IA64_OPND_CPUID_R3; - } - else - { - return ((op =3D=3D IA64_OPND_RR_R3 && strstr (field, "rr")) - || (op =3D=3D IA64_OPND_DBR_R3 && strstr (field, "dbr")) - || (op =3D=3D IA64_OPND_IBR_R3 && strstr (field, "ibr")) - || (op =3D=3D IA64_OPND_PKR_R3 && strstr (field, "pkr")) - || (op =3D=3D IA64_OPND_PMC_R3 && strstr (field, "pmc")) - || (op =3D=3D IA64_OPND_PMD_R3 && strstr (field, "pmd")) - || (op =3D=3D IA64_OPND_MSR_R3 && strstr (field, "msr")) - || (op =3D=3D IA64_OPND_CPUID_R3 && strstr (field, "cpuid")) - || (op =3D=3D IA64_OPND_DAHR_R3 && strstr (field, "dahr"))); - } -} - -/* Handle mov_ar, mov_br, mov_cr, move_dahr, mov_indirect, mov_ip, mov_pr, - * mov_psr, and mov_um insn classes. */ -static int -in_iclass_mov_x (struct ia64_opcode *idesc, struct iclass *ic, - const char *format, const char *field) -{ - int plain_mov =3D strcmp (idesc->name, "mov") =3D=3D 0; - - if (!format) - return 0; - - switch (ic->name[4]) - { - default: - abort (); - case 'a': - { - int i =3D strcmp (idesc->name, "mov.i") =3D=3D 0; - int m =3D strcmp (idesc->name, "mov.m") =3D=3D 0; - int i2627 =3D i && idesc->operands[0] =3D=3D IA64_OPND_AR3; - int i28 =3D i && idesc->operands[1] =3D=3D IA64_OPND_AR3; - int m2930 =3D m && idesc->operands[0] =3D=3D IA64_OPND_AR3; - int m31 =3D m && idesc->operands[1] =3D=3D IA64_OPND_AR3; - int pseudo0 =3D plain_mov && idesc->operands[1] =3D=3D IA64_OPND_A= R3; - int pseudo1 =3D plain_mov && idesc->operands[0] =3D=3D IA64_OPND_A= R3; - - /* IC:mov ar */ - if (i2627) - return strstr (format, "I26") || strstr (format, "I27"); - if (i28) - return strstr (format, "I28") !=3D NULL; - if (m2930) - return strstr (format, "M29") || strstr (format, "M30"); - if (m31) - return strstr (format, "M31") !=3D NULL; - if (pseudo0 || pseudo1) - return 1; - } - break; - case 'b': - { - int i21 =3D idesc->operands[0] =3D=3D IA64_OPND_B1; - int i22 =3D plain_mov && idesc->operands[1] =3D=3D IA64_OPND_B2; - if (i22) - return strstr (format, "I22") !=3D NULL; - if (i21) - return strstr (format, "I21") !=3D NULL; - } - break; - case 'c': - { - int m32 =3D plain_mov && idesc->operands[0] =3D=3D IA64_OPND_CR3; - int m33 =3D plain_mov && idesc->operands[1] =3D=3D IA64_OPND_CR3; - if (m32) - return strstr (format, "M32") !=3D NULL; - if (m33) - return strstr (format, "M33") !=3D NULL; - } - break; - case 'd': - { - int m50 =3D plain_mov && idesc->operands[0] =3D=3D IA64_OPND_DAHR3; - if (m50) - return strstr (format, "M50") !=3D NULL; - } - break; - case 'i': - if (ic->name[5] =3D=3D 'n') - { - int m42 =3D plain_mov && irf_operand (idesc->operands[0], field); - int m43 =3D plain_mov && irf_operand (idesc->operands[1], field); - if (m42) - return strstr (format, "M42") !=3D NULL; - if (m43) - return strstr (format, "M43") !=3D NULL; - } - else if (ic->name[5] =3D=3D 'p') - { - return idesc->operands[1] =3D=3D IA64_OPND_IP; - } - else - abort (); - break; - case 'p': - if (ic->name[5] =3D=3D 'r') - { - int i25 =3D plain_mov && idesc->operands[1] =3D=3D IA64_OPND_PR; - int i23 =3D plain_mov && idesc->operands[0] =3D=3D IA64_OPND_PR; - int i24 =3D plain_mov && idesc->operands[0] =3D=3D IA64_OPND_PR_= ROT; - if (i23) - return strstr (format, "I23") !=3D NULL; - if (i24) - return strstr (format, "I24") !=3D NULL; - if (i25) - return strstr (format, "I25") !=3D NULL; - } - else if (ic->name[5] =3D=3D 's') - { - int m35 =3D plain_mov && idesc->operands[0] =3D=3D IA64_OPND_PSR= _L; - int m36 =3D plain_mov && idesc->operands[1] =3D=3D IA64_OPND_PSR; - if (m35) - return strstr (format, "M35") !=3D NULL; - if (m36) - return strstr (format, "M36") !=3D NULL; - } - else - abort (); - break; - case 'u': - { - int m35 =3D plain_mov && idesc->operands[0] =3D=3D IA64_OPND_PSR_U= M; - int m36 =3D plain_mov && idesc->operands[1] =3D=3D IA64_OPND_PSR_U= M; - if (m35) - return strstr (format, "M35") !=3D NULL; - if (m36) - return strstr (format, "M36") !=3D NULL; - } - break; - } - return 0; -} - -/* Is the given opcode in the given insn class? */ -static int -in_iclass (struct ia64_opcode *idesc, struct iclass *ic, - const char *format, const char *field, int *notep) -{ - int i; - int resolved =3D 0; - - if (ic->comment) - { - if (startswith (ic->comment, "Format")) - { - /* Assume that the first format seen is the most restrictive, and - only keep a later one if it looks like it's more restrictive.= */ - if (format) - { - if (strlen (ic->comment) < strlen (format)) - { - warn (_("most recent format '%s'\nappears more restricti= ve than '%s'\n"), - ic->comment, format); - format =3D ic->comment; - } - } - else - format =3D ic->comment; - } - else if (startswith (ic->comment, "Field")) - { - if (field) - warn (_("overlapping field %s->%s\n"), - ic->comment, field); - field =3D ic->comment; - } - } - - /* An insn class matches anything that is the same followed by completer= s, - except when the absence and presence of completers constitutes differ= ent - instructions. */ - if (ic->nsubs =3D=3D 0 && ic->nxsubs =3D=3D 0) - { - int is_mov =3D startswith (idesc->name, "mov"); - int plain_mov =3D strcmp (idesc->name, "mov") =3D=3D 0; - int len =3D strlen(ic->name); - - resolved =3D ((strncmp (ic->name, idesc->name, len) =3D=3D 0) - && (idesc->name[len] =3D=3D '\0' - || idesc->name[len] =3D=3D '.')); - - /* All break, nop, and hint variations must match exactly. */ - if (resolved && - (strcmp (ic->name, "break") =3D=3D 0 - || strcmp (ic->name, "nop") =3D=3D 0 - || strcmp (ic->name, "hint") =3D=3D 0)) - resolved =3D strcmp (ic->name, idesc->name) =3D=3D 0; - - /* Assume restrictions in the FORMAT/FIELD negate resolution, - unless specifically allowed by clauses in this block. */ - if (resolved && field) - { - /* Check Field(sf)=3D=3DsN against opcode sN. */ - if (strstr(field, "(sf)=3D=3D") !=3D NULL) - { - char *sf; - - if ((sf =3D strstr (idesc->name, ".s")) !=3D 0) - resolved =3D strcmp (sf + 1, strstr (field, "=3D=3D") + 2) =3D=3D 0; - } - /* Check Field(lftype)=3D=3DXXX. */ - else if (strstr (field, "(lftype)") !=3D NULL) - { - if (strstr (idesc->name, "fault") !=3D NULL) - resolved =3D strstr (field, "fault") !=3D NULL; - else - resolved =3D strstr (field, "fault") =3D=3D NULL; - } - /* Handle Field(ctype)=3D=3DXXX. */ - else if (strstr (field, "(ctype)") !=3D NULL) - { - if (strstr (idesc->name, "or.andcm")) - resolved =3D strstr (field, "or.andcm") !=3D NULL; - else if (strstr (idesc->name, "and.orcm")) - resolved =3D strstr (field, "and.orcm") !=3D NULL; - else if (strstr (idesc->name, "orcm")) - resolved =3D strstr (field, "or orcm") !=3D NULL; - else if (strstr (idesc->name, "or")) - resolved =3D strstr (field, "or orcm") !=3D NULL; - else if (strstr (idesc->name, "andcm")) - resolved =3D strstr (field, "and andcm") !=3D NULL; - else if (strstr (idesc->name, "and")) - resolved =3D strstr (field, "and andcm") !=3D NULL; - else if (strstr (idesc->name, "unc")) - resolved =3D strstr (field, "unc") !=3D NULL; - else - resolved =3D strcmp (field, "Field(ctype)=3D=3D") =3D=3D 0; - } - } - - if (resolved && format) - { - if (startswith (idesc->name, "dep") - && strstr (format, "I13") !=3D NULL) - resolved =3D idesc->operands[1] =3D=3D IA64_OPND_IMM8; - else if (startswith (idesc->name, "chk") - && strstr (format, "M21") !=3D NULL) - resolved =3D idesc->operands[0] =3D=3D IA64_OPND_F2; - else if (startswith (idesc->name, "lfetch")) - resolved =3D (strstr (format, "M14 M15") !=3D NULL - && (idesc->operands[1] =3D=3D IA64_OPND_R2 - || idesc->operands[1] =3D=3D IA64_OPND_IMM9b)); - else if (startswith (idesc->name, "br.call") - && strstr (format, "B5") !=3D NULL) - resolved =3D idesc->operands[1] =3D=3D IA64_OPND_B2; - else if (startswith (idesc->name, "br.call") - && strstr (format, "B3") !=3D NULL) - resolved =3D idesc->operands[1] =3D=3D IA64_OPND_TGT25c; - else if (startswith (idesc->name, "brp") - && strstr (format, "B7") !=3D NULL) - resolved =3D idesc->operands[0] =3D=3D IA64_OPND_B2; - else if (strcmp (ic->name, "invala") =3D=3D 0) - resolved =3D strcmp (idesc->name, ic->name) =3D=3D 0; - else if (startswith (idesc->name, "st") - && (strstr (format, "M5") !=3D NULL - || strstr (format, "M10") !=3D NULL)) - resolved =3D idesc->flags & IA64_OPCODE_POSTINC; - else if (startswith (idesc->name, "ld") - && (strstr (format, "M2 M3") !=3D NULL - || strstr (format, "M12") !=3D NULL - || strstr (format, "M7 M8") !=3D NULL)) - resolved =3D idesc->flags & IA64_OPCODE_POSTINC; - else - resolved =3D 0; - } - - /* Misc brl variations ('.cond' is optional); - plain brl matches brl.cond. */ - if (!resolved - && (strcmp (idesc->name, "brl") =3D=3D 0 - || startswith (idesc->name, "brl.")) - && strcmp (ic->name, "brl.cond") =3D=3D 0) - { - resolved =3D 1; - } - - /* Misc br variations ('.cond' is optional). */ - if (!resolved - && (strcmp (idesc->name, "br") =3D=3D 0 - || startswith (idesc->name, "br.")) - && strcmp (ic->name, "br.cond") =3D=3D 0) - { - if (format) - resolved =3D (strstr (format, "B4") !=3D NULL - && idesc->operands[0] =3D=3D IA64_OPND_B2) - || (strstr (format, "B1") !=3D NULL - && idesc->operands[0] =3D=3D IA64_OPND_TGT25c); - else - resolved =3D 1; - } - - /* probe variations. */ - if (!resolved && startswith (idesc->name, "probe")) - { - resolved =3D strcmp (ic->name, "probe") =3D=3D 0 - && !((strstr (idesc->name, "fault") !=3D NULL) - ^ (format && strstr (format, "M40") !=3D NULL)); - } - - /* mov variations. */ - if (!resolved && is_mov) - { - if (plain_mov) - { - /* mov alias for fmerge. */ - if (strcmp (ic->name, "fmerge") =3D=3D 0) - { - resolved =3D idesc->operands[0] =3D=3D IA64_OPND_F1 - && idesc->operands[1] =3D=3D IA64_OPND_F3; - } - /* mov alias for adds (r3 or imm14). */ - else if (strcmp (ic->name, "adds") =3D=3D 0) - { - resolved =3D (idesc->operands[0] =3D=3D IA64_OPND_R1 - && (idesc->operands[1] =3D=3D IA64_OPND_R3 - || (idesc->operands[1] =3D=3D IA64_OPND_= IMM14))); - } - /* mov alias for addl. */ - else if (strcmp (ic->name, "addl") =3D=3D 0) - { - resolved =3D idesc->operands[0] =3D=3D IA64_OPND_R1 - && idesc->operands[1] =3D=3D IA64_OPND_IMM22; - } - } - - /* Some variants of mov and mov.[im]. */ - if (!resolved && startswith (ic->name, "mov_")) - resolved =3D in_iclass_mov_x (idesc, ic, format, field); - } - - /* Keep track of this so we can flag any insn classes which aren't - mapped onto at least one real insn. */ - if (resolved) - ic->terminal_resolved =3D 1; - } - else for (i =3D 0; i < ic->nsubs; i++) - { - if (in_iclass (idesc, ics[ic->subs[i]], format, field, notep)) - { - int j; - - for (j =3D 0; j < ic->nxsubs; j++) - if (in_iclass (idesc, ics[ic->xsubs[j]], NULL, NULL, NULL)) - return 0; - - if (debug > 1) - printf ("%s is in IC %s\n", idesc->name, ic->name); - - resolved =3D 1; - break; - } - } - - /* If it's in this IC, add the IC note (if any) to the insn. */ - if (resolved) - { - if (ic->note && notep) - { - if (*notep && *notep !=3D ic->note) - warn (_("overwriting note %d with note %d (IC:%s)\n"), - *notep, ic->note, ic->name); - - *notep =3D ic->note; - } - } - - return resolved; -} - -=0C -static int -lookup_regindex (const char *name, int specifier) -{ - switch (specifier) - { - case IA64_RS_ARX: - if (strstr (name, "[RSC]")) - return 16; - if (strstr (name, "[BSP]")) - return 17; - else if (strstr (name, "[BSPSTORE]")) - return 18; - else if (strstr (name, "[RNAT]")) - return 19; - else if (strstr (name, "[FCR]")) - return 21; - else if (strstr (name, "[EFLAG]")) - return 24; - else if (strstr (name, "[CSD]")) - return 25; - else if (strstr (name, "[SSD]")) - return 26; - else if (strstr (name, "[CFLG]")) - return 27; - else if (strstr (name, "[FSR]")) - return 28; - else if (strstr (name, "[FIR]")) - return 29; - else if (strstr (name, "[FDR]")) - return 30; - else if (strstr (name, "[CCV]")) - return 32; - else if (strstr (name, "[ITC]")) - return 44; - else if (strstr (name, "[RUC]")) - return 45; - else if (strstr (name, "[PFS]")) - return 64; - else if (strstr (name, "[LC]")) - return 65; - else if (strstr (name, "[EC]")) - return 66; - abort (); - case IA64_RS_CRX: - if (strstr (name, "[DCR]")) - return 0; - else if (strstr (name, "[ITM]")) - return 1; - else if (strstr (name, "[IVA]")) - return 2; - else if (strstr (name, "[PTA]")) - return 8; - else if (strstr (name, "[GPTA]")) - return 9; - else if (strstr (name, "[IPSR]")) - return 16; - else if (strstr (name, "[ISR]")) - return 17; - else if (strstr (name, "[IIP]")) - return 19; - else if (strstr (name, "[IFA]")) - return 20; - else if (strstr (name, "[ITIR]")) - return 21; - else if (strstr (name, "[IIPA]")) - return 22; - else if (strstr (name, "[IFS]")) - return 23; - else if (strstr (name, "[IIM]")) - return 24; - else if (strstr (name, "[IHA]")) - return 25; - else if (strstr (name, "[LID]")) - return 64; - else if (strstr (name, "[IVR]")) - return 65; - else if (strstr (name, "[TPR]")) - return 66; - else if (strstr (name, "[EOI]")) - return 67; - else if (strstr (name, "[ITV]")) - return 72; - else if (strstr (name, "[PMV]")) - return 73; - else if (strstr (name, "[CMCV]")) - return 74; - abort (); - case IA64_RS_PSR: - if (strstr (name, ".be")) - return 1; - else if (strstr (name, ".up")) - return 2; - else if (strstr (name, ".ac")) - return 3; - else if (strstr (name, ".mfl")) - return 4; - else if (strstr (name, ".mfh")) - return 5; - else if (strstr (name, ".ic")) - return 13; - else if (strstr (name, ".i")) - return 14; - else if (strstr (name, ".pk")) - return 15; - else if (strstr (name, ".dt")) - return 17; - else if (strstr (name, ".dfl")) - return 18; - else if (strstr (name, ".dfh")) - return 19; - else if (strstr (name, ".sp")) - return 20; - else if (strstr (name, ".pp")) - return 21; - else if (strstr (name, ".di")) - return 22; - else if (strstr (name, ".si")) - return 23; - else if (strstr (name, ".db")) - return 24; - else if (strstr (name, ".lp")) - return 25; - else if (strstr (name, ".tb")) - return 26; - else if (strstr (name, ".rt")) - return 27; - else if (strstr (name, ".cpl")) - return 32; - else if (strstr (name, ".rs")) - return 34; - else if (strstr (name, ".mc")) - return 35; - else if (strstr (name, ".it")) - return 36; - else if (strstr (name, ".id")) - return 37; - else if (strstr (name, ".da")) - return 38; - else if (strstr (name, ".dd")) - return 39; - else if (strstr (name, ".ss")) - return 40; - else if (strstr (name, ".ri")) - return 41; - else if (strstr (name, ".ed")) - return 43; - else if (strstr (name, ".bn")) - return 44; - else if (strstr (name, ".ia")) - return 45; - else if (strstr (name, ".vm")) - return 46; - else - abort (); - default: - break; - } - return REG_NONE; -} - -static int -lookup_specifier (const char *name) -{ - if (strchr (name, '%')) - { - if (strstr (name, "AR[K%]") !=3D NULL) - return IA64_RS_AR_K; - if (strstr (name, "AR[UNAT]") !=3D NULL) - return IA64_RS_AR_UNAT; - if (strstr (name, "AR%, % in 8") !=3D NULL) - return IA64_RS_AR; - if (strstr (name, "AR%, % in 48") !=3D NULL) - return IA64_RS_ARb; - if (strstr (name, "BR%") !=3D NULL) - return IA64_RS_BR; - if (strstr (name, "CR[IIB%]") !=3D NULL) - return IA64_RS_CR_IIB; - if (strstr (name, "CR[IRR%]") !=3D NULL) - return IA64_RS_CR_IRR; - if (strstr (name, "CR[LRR%]") !=3D NULL) - return IA64_RS_CR_LRR; - if (strstr (name, "CR%") !=3D NULL) - return IA64_RS_CR; - if (strstr (name, "DAHR%, % in 0") !=3D NULL) - return IA64_RS_DAHR; - if (strstr (name, "FR%, % in 0") !=3D NULL) - return IA64_RS_FR; - if (strstr (name, "FR%, % in 2") !=3D NULL) - return IA64_RS_FRb; - if (strstr (name, "GR%") !=3D NULL) - return IA64_RS_GR; - if (strstr (name, "PR%, % in 1 ") !=3D NULL) - return IA64_RS_PR; - if (strstr (name, "PR%, % in 16 ") !=3D NULL) - return IA64_RS_PRr; - - warn (_("don't know how to specify %% dependency %s\n"), - name); - } - else if (strchr (name, '#')) - { - if (strstr (name, "CPUID#") !=3D NULL) - return IA64_RS_CPUID; - if (strstr (name, "DBR#") !=3D NULL) - return IA64_RS_DBR; - if (strstr (name, "IBR#") !=3D NULL) - return IA64_RS_IBR; - if (strstr (name, "MSR#") !=3D NULL) - return IA64_RS_MSR; - if (strstr (name, "PKR#") !=3D NULL) - return IA64_RS_PKR; - if (strstr (name, "PMC#") !=3D NULL) - return IA64_RS_PMC; - if (strstr (name, "PMD#") !=3D NULL) - return IA64_RS_PMD; - if (strstr (name, "RR#") !=3D NULL) - return IA64_RS_RR; - - warn (_("Don't know how to specify # dependency %s\n"), - name); - } - else if (startswith (name, "AR[FPSR]")) - return IA64_RS_AR_FPSR; - else if (startswith (name, "AR[")) - return IA64_RS_ARX; - else if (startswith (name, "CR[")) - return IA64_RS_CRX; - else if (startswith (name, "PSR.")) - return IA64_RS_PSR; - else if (strcmp (name, "InService*") =3D=3D 0) - return IA64_RS_INSERVICE; - else if (strcmp (name, "GR0") =3D=3D 0) - return IA64_RS_GR0; - else if (strcmp (name, "CFM") =3D=3D 0) - return IA64_RS_CFM; - else if (strcmp (name, "PR63") =3D=3D 0) - return IA64_RS_PR63; - else if (strcmp (name, "RSE") =3D=3D 0) - return IA64_RS_RSE; - - return IA64_RS_ANY; -} - -static void -print_dependency_table (void) -{ - int i, j; - - if (debug) - { - for (i=3D0;i < iclen;i++) - { - if (ics[i]->is_class) - { - if (!ics[i]->nsubs) - { - if (ics[i]->comment) - warn (_("IC:%s [%s] has no terminals or sub-classes\n"), - ics[i]->name, ics[i]->comment); - else - warn (_("IC:%s has no terminals or sub-classes\n"), - ics[i]->name); - } - } - else - { - if (!ics[i]->terminal_resolved && !ics[i]->orphan) - { - if (ics[i]->comment) - warn (_("no insns mapped directly to terminal IC %s [%s]"), - ics[i]->name, ics[i]->comment); - else - warn (_("no insns mapped directly to terminal IC %s\n"), - ics[i]->name); - } - } - } - - for (i =3D 0; i < iclen; i++) - { - if (ics[i]->orphan) - { - mark_used (ics[i], 1); - warn (_("class %s is defined but not used\n"), - ics[i]->name); - } - } - - if (debug > 1) - for (i =3D 0; i < rdepslen; i++) - { - static const char *mode_str[] =3D { "RAW", "WAW", "WAR" }; - - if (rdeps[i]->total_chks =3D=3D 0) - { - if (rdeps[i]->total_regs) - warn (_("Warning: rsrc %s (%s) has no chks\n"), - rdeps[i]->name, mode_str[rdeps[i]->mode]); - else - warn (_("Warning: rsrc %s (%s) has no chks or regs\n"), - rdeps[i]->name, mode_str[rdeps[i]->mode]); - } - else if (rdeps[i]->total_regs =3D=3D 0) - warn (_("rsrc %s (%s) has no regs\n"), - rdeps[i]->name, mode_str[rdeps[i]->mode]); - } - } - - /* The dependencies themselves. */ - printf ("static const struct ia64_dependency\ndependencies[] =3D {\n"); - for (i =3D 0; i < rdepslen; i++) - { - /* '%', '#', AR[], CR[], or PSR. indicates we need to specify the ac= tual - resource used. */ - int specifier =3D lookup_specifier (rdeps[i]->name); - int regindex =3D lookup_regindex (rdeps[i]->name, specifier); - - printf (" { \"%s\", %d, %d, %d, %d, ", - rdeps[i]->name, specifier, - (int)rdeps[i]->mode, (int)rdeps[i]->semantics, regindex); - if (rdeps[i]->semantics =3D=3D IA64_DVS_OTHER) - { - const char *quote, *rest; - - putchar ('\"'); - rest =3D rdeps[i]->extra; - quote =3D strchr (rest, '\"'); - while (quote !=3D NULL) - { - printf ("%.*s\\\"", (int) (quote - rest), rest); - rest =3D quote + 1; - quote =3D strchr (rest, '\"'); - } - printf ("%s\", ", rest); - } - else - printf ("NULL, "); - printf("},\n"); - } - printf ("};\n\n"); - - /* And dependency lists. */ - for (i=3D0;i < dlistlen;i++) - { - unsigned int len =3D (unsigned) -1; - printf ("static const unsigned short dep%d[] =3D {", i); - for (j=3D0;j < dlists[i]->len; j++) - { - if (len > 74) - { - printf("\n "); - len =3D 1; - } - len +=3D printf (" %d,", dlists[i]->deps[j]); - } - printf ("\n};\n\n"); - } - - /* And opcode dependency list. */ - printf ("#define NELS(X) (sizeof(X)/sizeof(X[0]))\n"); - printf ("static const struct ia64_opcode_dependency\n"); - printf ("op_dependencies[] =3D {\n"); - for (i =3D 0; i < opdeplen; i++) - { - printf (" { "); - if (opdeps[i]->chk =3D=3D -1) - printf ("0, NULL, "); - else - printf ("NELS(dep%d), dep%d, ", opdeps[i]->chk, opdeps[i]->chk); - if (opdeps[i]->reg =3D=3D -1) - printf ("0, NULL, "); - else - printf ("NELS(dep%d), dep%d, ", opdeps[i]->reg, opdeps[i]->reg); - printf ("},\n"); - } - printf ("};\n\n"); -} - -=0C -/* Add STR to the string table. */ -static struct string_entry * -insert_string (char *str) -{ - int start =3D 0, end =3D strtablen; - int i, x; - - if (strtablen =3D=3D strtabtotlen) - { - strtabtotlen +=3D 20; - string_table =3D (struct string_entry **) - xrealloc (string_table, - sizeof (struct string_entry **) * strtabtotlen); - } - - if (strtablen =3D=3D 0) - { - strtablen =3D 1; - string_table[0] =3D tmalloc (struct string_entry); - string_table[0]->s =3D xstrdup (str); - string_table[0]->num =3D 0; - return string_table[0]; - } - - if (strcmp (str, string_table[strtablen - 1]->s) > 0) - i =3D end; - else if (strcmp (str, string_table[0]->s) < 0) - i =3D 0; - else - { - while (1) - { - int c; - - i =3D (start + end) / 2; - c =3D strcmp (str, string_table[i]->s); - - if (c < 0) - end =3D i - 1; - else if (c =3D=3D 0) - return string_table[i]; - else - start =3D i + 1; - - if (start > end) - break; - } - } - - for (; i > 0 && i < strtablen; i--) - if (strcmp (str, string_table[i - 1]->s) > 0) - break; - - for (; i < strtablen; i++) - if (strcmp (str, string_table[i]->s) < 0) - break; - - for (x =3D strtablen - 1; x >=3D i; x--) - { - string_table[x + 1] =3D string_table[x]; - string_table[x + 1]->num =3D x + 1; - } - - string_table[i] =3D tmalloc (struct string_entry); - string_table[i]->s =3D xstrdup (str); - string_table[i]->num =3D i; - strtablen++; - - return string_table[i]; -} -=0C -static struct bittree * -make_bittree_entry (void) -{ - struct bittree *res =3D tmalloc (struct bittree); - - res->disent =3D NULL; - res->bits[0] =3D NULL; - res->bits[1] =3D NULL; - res->bits[2] =3D NULL; - res->skip_flag =3D 0; - res->bits_to_skip =3D 0; - return res; -} - -=0C -static struct disent * -add_dis_table_ent (struct disent *which, int insn, int order, - ci_t completer_index) -{ - int ci =3D 0; - struct disent *ent; - - if (which !=3D NULL) - { - ent =3D which; - - ent->nextcnt++; - while (ent->nexte !=3D NULL) - ent =3D ent->nexte; - - ent =3D (ent->nexte =3D tmalloc (struct disent)); - } - else - { - ent =3D tmalloc (struct disent); - ent->next_ent =3D disinsntable; - disinsntable =3D ent; - which =3D ent; - } - ent->nextcnt =3D 0; - ent->nexte =3D NULL; - ent->insn =3D insn; - ent->priority =3D order; - - while (completer_index !=3D 1) - { - ci =3D (ci << 1) | (completer_index & 1); - completer_index >>=3D 1; - } - ent->completer_index =3D ci; - return which; -} -=0C -static void -finish_distable (void) -{ - struct disent *ent =3D disinsntable; - struct disent *prev =3D ent; - - ent->ournum =3D 32768; - while ((ent =3D ent->next_ent) !=3D NULL) - { - ent->ournum =3D prev->ournum + prev->nextcnt + 1; - prev =3D ent; - } -} -=0C -static void -insert_bit_table_ent (struct bittree *curr_ent, int bit, ia64_insn opcode, - ia64_insn mask, int opcodenum, int order, - ci_t completer_index) -{ - ia64_insn m; - int b; - struct bittree *next; - - if (bit =3D=3D -1) - { - struct disent *nent =3D add_dis_table_ent (curr_ent->disent, - opcodenum, order, - completer_index); - curr_ent->disent =3D nent; - return; - } - - m =3D ((ia64_insn) 1) << bit; - - if (mask & m) - b =3D (opcode & m) ? 1 : 0; - else - b =3D 2; - - next =3D curr_ent->bits[b]; - if (next =3D=3D NULL) - { - next =3D make_bittree_entry (); - curr_ent->bits[b] =3D next; - } - insert_bit_table_ent (next, bit - 1, opcode, mask, opcodenum, order, - completer_index); -} -=0C -static void -add_dis_entry (struct bittree *first, ia64_insn opcode, ia64_insn mask, - int opcodenum, struct completer_entry *ent, ci_t completer_= index) -{ - if (completer_index & ((ci_t)1 << 32) ) - abort (); - - while (ent !=3D NULL) - { - ia64_insn newopcode =3D (opcode & (~ ent->mask)) | ent->bits; - add_dis_entry (first, newopcode, mask, opcodenum, ent->addl_entries, - (completer_index << 1) | 1); - - if (ent->is_terminal) - { - insert_bit_table_ent (bittree, 40, newopcode, mask, - opcodenum, opcode_count - ent->order - 1, - (completer_index << 1) | 1); - } - completer_index <<=3D 1; - ent =3D ent->alternative; - } -} -=0C -/* This optimization pass combines multiple "don't care" nodes. */ -static void -compact_distree (struct bittree *ent) -{ -#define IS_SKIP(ent) \ - ((ent->bits[2] !=3DNULL) \ - && (ent->bits[0] =3D=3D NULL && ent->bits[1] =3D=3D NULL && ent->skip= _flag =3D=3D 0)) - - int bitcnt =3D 0; - struct bittree *nent =3D ent; - int x; - - while (IS_SKIP (nent)) - { - bitcnt++; - nent =3D nent->bits[2]; - } - - if (bitcnt) - { - struct bittree *next =3D ent->bits[2]; - - ent->bits[0] =3D nent->bits[0]; - ent->bits[1] =3D nent->bits[1]; - ent->bits[2] =3D nent->bits[2]; - ent->disent =3D nent->disent; - ent->skip_flag =3D 1; - ent->bits_to_skip =3D bitcnt; - while (next !=3D nent) - { - struct bittree *b =3D next; - next =3D next->bits[2]; - free (b); - } - free (nent); - } - - for (x =3D 0; x < 3; x++) - { - struct bittree *i =3D ent->bits[x]; - - if (i !=3D NULL) - compact_distree (i); - } -} -=0C -static unsigned char *insn_list; -static int insn_list_len =3D 0; -static int tot_insn_list_len =3D 0; - -/* Generate the disassembler state machine corresponding to the tree - in ENT. */ -static void -gen_dis_table (struct bittree *ent) -{ - int x; - int our_offset =3D insn_list_len; - int bitsused =3D 5; - int totbits =3D bitsused; - int needed_bytes; - int zero_count =3D 0; - int zero_dest =3D 0; /* Initialize this with 0 to keep gcc quiet... */ - - /* If this is a terminal entry, there's no point in skipping any - bits. */ - if (ent->skip_flag && ent->bits[0] =3D=3D NULL && ent->bits[1] =3D=3D NU= LL && - ent->bits[2] =3D=3D NULL) - { - if (ent->disent =3D=3D NULL) - abort (); - else - ent->skip_flag =3D 0; - } - - /* Calculate the amount of space needed for this entry, or at least - a conservatively large approximation. */ - if (ent->skip_flag) - totbits +=3D 5; - - for (x =3D 1; x < 3; x++) - if (ent->bits[x] !=3D NULL) - totbits +=3D 16; - - if (ent->disent !=3D NULL) - { - if (ent->bits[2] !=3D NULL) - abort (); - - totbits +=3D 16; - } - - /* Now allocate the space. */ - needed_bytes =3D (totbits + 7) / 8; - if ((needed_bytes + insn_list_len) > tot_insn_list_len) - { - tot_insn_list_len +=3D 256; - insn_list =3D (unsigned char *) xrealloc (insn_list, tot_insn_list_l= en); - } - our_offset =3D insn_list_len; - insn_list_len +=3D needed_bytes; - memset (insn_list + our_offset, 0, needed_bytes); - - /* Encode the skip entry by setting bit 6 set in the state op field, - and store the # of bits to skip immediately after. */ - if (ent->skip_flag) - { - bitsused +=3D 5; - insn_list[our_offset + 0] |=3D 0x40 | ((ent->bits_to_skip >> 2) & 0x= f); - insn_list[our_offset + 1] |=3D ((ent->bits_to_skip & 3) << 6); - } - -#define IS_ONLY_IFZERO(ENT) \ - ((ENT)->bits[0] !=3D NULL && (ENT)->bits[1] =3D=3D NULL && (ENT)->bits[2= ] =3D=3D NULL \ - && (ENT)->disent =3D=3D NULL && (ENT)->skip_flag =3D=3D 0) - - /* Store an "if (bit is zero)" instruction by setting bit 7 in the - state op field. */ - if (ent->bits[0] !=3D NULL) - { - struct bittree *nent =3D ent->bits[0]; - zero_count =3D 0; - - insn_list[our_offset] |=3D 0x80; - - /* We can encode sequences of multiple "if (bit is zero)" tests - by storing the # of zero bits to check in the lower 3 bits of - the instruction. However, this only applies if the state - solely tests for a zero bit. */ - - if (IS_ONLY_IFZERO (ent)) - { - while (IS_ONLY_IFZERO (nent) && zero_count < 7) - { - nent =3D nent->bits[0]; - zero_count++; - } - - insn_list[our_offset + 0] |=3D zero_count; - } - zero_dest =3D insn_list_len; - gen_dis_table (nent); - } - - /* Now store the remaining tests. We also handle a sole "termination - entry" by storing it as an "any bit" test. */ - - for (x =3D 1; x < 3; x++) - { - if (ent->bits[x] !=3D NULL || (x =3D=3D 2 && ent->disent !=3D NULL)) - { - struct bittree *i =3D ent->bits[x]; - int idest; - int currbits =3D 15; - - if (i !=3D NULL) - { - /* If the instruction being branched to only consists of - a termination entry, use the termination entry as the - place to branch to instead. */ - if (i->bits[0] =3D=3D NULL && i->bits[1] =3D=3D NULL - && i->bits[2] =3D=3D NULL && i->disent !=3D NULL) - { - idest =3D i->disent->ournum; - i =3D NULL; - } - else - idest =3D insn_list_len - our_offset; - } - else - idest =3D ent->disent->ournum; - - /* If the destination offset for the if (bit is 1) test is less - than 256 bytes away, we can store it as 8-bits instead of 16; - the instruction has bit 5 set for the 16-bit address, and bit - 4 for the 8-bit address. Since we've already allocated 16 - bits for the address we need to deallocate the space. - - Note that branchings within the table are relative, and - there are no branches that branch past our instruction yet - so we do not need to adjust any other offsets. */ - if (x =3D=3D 1) - { - if (idest <=3D 256) - { - int start =3D our_offset + bitsused / 8 + 1; - - memmove (insn_list + start, - insn_list + start + 1, - insn_list_len - (start + 1)); - currbits =3D 7; - totbits -=3D 8; - needed_bytes--; - insn_list_len--; - insn_list[our_offset] |=3D 0x10; - idest--; - } - else - insn_list[our_offset] |=3D 0x20; - } - else - { - /* An instruction which solely consists of a termination - marker and whose disassembly name index is < 4096 - can be stored in 16 bits. The encoding is slightly - odd; the upper 4 bits of the instruction are 0x3, and - bit 3 loses its normal meaning. */ - - if (ent->bits[0] =3D=3D NULL && ent->bits[1] =3D=3D NULL - && ent->bits[2] =3D=3D NULL && ent->skip_flag =3D=3D 0 - && ent->disent !=3D NULL - && ent->disent->ournum < (32768 + 4096)) - { - int start =3D our_offset + bitsused / 8 + 1; - - memmove (insn_list + start, - insn_list + start + 1, - insn_list_len - (start + 1)); - currbits =3D 11; - totbits -=3D 5; - bitsused--; - needed_bytes--; - insn_list_len--; - insn_list[our_offset] |=3D 0x30; - idest &=3D ~32768; - } - else - insn_list[our_offset] |=3D 0x08; - } - - if (debug) - { - int id =3D idest; - - if (i =3D=3D NULL) - id |=3D 32768; - else if (! (id & 32768)) - id +=3D our_offset; - - if (x =3D=3D 1) - printf ("%d: if (1) goto %d\n", our_offset, id); - else - printf ("%d: try %d\n", our_offset, id); - } - - /* Store the address of the entry being branched to. */ - while (currbits >=3D 0) - { - unsigned char *byte =3D insn_list + our_offset + bitsused / 8; - - if (idest & (1 << currbits)) - *byte |=3D (1 << (7 - (bitsused % 8))); - - bitsused++; - currbits--; - } - - /* Now generate the states for the entry being branched to. */ - if (i !=3D NULL) - gen_dis_table (i); - } - } - - if (debug) - { - if (ent->skip_flag) - printf ("%d: skipping %d\n", our_offset, ent->bits_to_skip); - - if (ent->bits[0] !=3D NULL) - printf ("%d: if (0:%d) goto %d\n", our_offset, zero_count + 1, - zero_dest); - } - - if (bitsused !=3D totbits) - abort (); -} -=0C -static void -print_dis_table (void) -{ - int x; - struct disent *cent =3D disinsntable; - - printf ("static const char dis_table[] =3D {"); - for (x =3D 0; x < insn_list_len; x++) - { - if (x % 12 =3D=3D 0) - printf ("\n "); - - printf (" 0x%02x,", insn_list[x]); - } - printf ("\n};\n\n"); - - printf ("static const struct ia64_dis_names ia64_dis_names[] =3D {\n"); - while (cent !=3D NULL) - { - struct disent *ent =3D cent; - - while (ent !=3D NULL) - { - printf ("{ 0x%lx, %d, %d, %d },\n", ( long ) ent->completer_index, - ent->insn, (ent->nexte !=3D NULL ? 1 : 0), - ent->priority); - ent =3D ent->nexte; - } - cent =3D cent->next_ent; - } - printf ("};\n\n"); -} -=0C -static void -generate_disassembler (void) -{ - int i; - - bittree =3D make_bittree_entry (); - - for (i =3D 0; i < otlen; i++) - { - struct main_entry *ptr =3D ordered_table[i]; - - if (ptr->opcode->type !=3D IA64_TYPE_DYN) - add_dis_entry (bittree, - ptr->opcode->opcode, ptr->opcode->mask, - ptr->main_index, - ptr->completers, 1); - } - - compact_distree (bittree); - finish_distable (); - gen_dis_table (bittree); - - print_dis_table (); -} -=0C -static void -print_string_table (void) -{ - int x; - char lbuf[80], buf[80]; - int blen =3D 0; - - printf ("static const char * const ia64_strings[] =3D {\n"); - lbuf[0] =3D '\0'; - - for (x =3D 0; x < strtablen; x++) - { - int len; - - if (strlen (string_table[x]->s) > 75) - abort (); - - sprintf (buf, " \"%s\",", string_table[x]->s); - len =3D strlen (buf); - - if ((blen + len) > 75) - { - printf (" %s\n", lbuf); - lbuf[0] =3D '\0'; - blen =3D 0; - } - strcat (lbuf, buf); - blen +=3D len; - } - - if (blen > 0) - printf (" %s\n", lbuf); - - printf ("};\n\n"); -} -=0C -static struct completer_entry **glist; -static int glistlen =3D 0; -static int glisttotlen =3D 0; - -/* If the completer trees ENT1 and ENT2 are equal, return 1. */ - -static int -completer_entries_eq (struct completer_entry *ent1, - struct completer_entry *ent2) -{ - while (ent1 !=3D NULL && ent2 !=3D NULL) - { - if (ent1->name->num !=3D ent2->name->num - || ent1->bits !=3D ent2->bits - || ent1->mask !=3D ent2->mask - || ent1->is_terminal !=3D ent2->is_terminal - || ent1->dependencies !=3D ent2->dependencies - || ent1->order !=3D ent2->order) - return 0; - - if (! completer_entries_eq (ent1->addl_entries, ent2->addl_entries)) - return 0; - - ent1 =3D ent1->alternative; - ent2 =3D ent2->alternative; - } - - return ent1 =3D=3D ent2; -} -=0C -/* Insert ENT into the global list of completers and return it. If an - equivalent entry (according to completer_entries_eq) already exists, - it is returned instead. */ -static struct completer_entry * -insert_gclist (struct completer_entry *ent) -{ - if (ent !=3D NULL) - { - int i; - int x; - int start =3D 0, end; - - ent->addl_entries =3D insert_gclist (ent->addl_entries); - ent->alternative =3D insert_gclist (ent->alternative); - - i =3D glistlen / 2; - end =3D glistlen; - - if (glisttotlen =3D=3D glistlen) - { - glisttotlen +=3D 20; - glist =3D (struct completer_entry **) - xrealloc (glist, sizeof (struct completer_entry *) * glisttotlen); - } - - if (glistlen =3D=3D 0) - { - glist[0] =3D ent; - glistlen =3D 1; - return ent; - } - - if (ent->name->num < glist[0]->name->num) - i =3D 0; - else if (ent->name->num > glist[end - 1]->name->num) - i =3D end; - else - { - int c; - - while (1) - { - i =3D (start + end) / 2; - c =3D ent->name->num - glist[i]->name->num; - - if (c < 0) - end =3D i - 1; - else if (c =3D=3D 0) - { - while (i > 0 - && ent->name->num =3D=3D glist[i - 1]->name->num) - i--; - - break; - } - else - start =3D i + 1; - - if (start > end) - break; - } - - if (c =3D=3D 0) - { - while (i < glistlen) - { - if (ent->name->num !=3D glist[i]->name->num) - break; - - if (completer_entries_eq (ent, glist[i])) - return glist[i]; - - i++; - } - } - } - - for (; i > 0 && i < glistlen; i--) - if (ent->name->num >=3D glist[i - 1]->name->num) - break; - - for (; i < glistlen; i++) - if (ent->name->num < glist[i]->name->num) - break; - - for (x =3D glistlen - 1; x >=3D i; x--) - glist[x + 1] =3D glist[x]; - - glist[i] =3D ent; - glistlen++; - } - return ent; -} -=0C -static int -get_prefix_len (const char *name) -{ - char *c; - - if (name[0] =3D=3D '\0') - return 0; - - c =3D strchr (name, '.'); - if (c !=3D NULL) - return c - name; - else - return strlen (name); -} -=0C -static void -compute_completer_bits (struct main_entry *ment, struct completer_entry *e= nt) -{ - while (ent !=3D NULL) - { - compute_completer_bits (ment, ent->addl_entries); - - if (ent->is_terminal) - { - ia64_insn mask =3D 0; - ia64_insn our_bits =3D ent->bits; - struct completer_entry *p =3D ent->parent; - ia64_insn p_bits; - int x; - - while (p !=3D NULL && ! p->is_terminal) - p =3D p->parent; - - if (p !=3D NULL) - p_bits =3D p->bits; - else - p_bits =3D ment->opcode->opcode; - - for (x =3D 0; x < 64; x++) - { - ia64_insn m =3D ((ia64_insn) 1) << x; - - if ((p_bits & m) !=3D (our_bits & m)) - mask |=3D m; - else - our_bits &=3D ~m; - } - ent->bits =3D our_bits; - ent->mask =3D mask; - } - else - { - ent->bits =3D 0; - ent->mask =3D 0; - } - - ent =3D ent->alternative; - } -} -=0C -/* Find identical completer trees that are used in different - instructions and collapse their entries. */ -static void -collapse_redundant_completers (void) -{ - struct main_entry *ptr; - int x; - - for (ptr =3D maintable; ptr !=3D NULL; ptr =3D ptr->next) - { - if (ptr->completers =3D=3D NULL) - abort (); - - compute_completer_bits (ptr, ptr->completers); - ptr->completers =3D insert_gclist (ptr->completers); - } - - /* The table has been finalized, now number the indexes. */ - for (x =3D 0; x < glistlen; x++) - glist[x]->num =3D x; -} -=0C - -/* Attach two lists of dependencies to each opcode. - 1) all resources which, when already marked in use, conflict with this - opcode (chks) - 2) all resources which must be marked in use when this opcode is used - (regs). */ -static int -insert_opcode_dependencies (struct ia64_opcode *opc, - struct completer_entry *cmp ATTRIBUTE_UNUSED) -{ - /* Note all resources which point to this opcode. rfi has the most chks - (79) and cmpxchng has the most regs (54) so 100 here should be enough= . */ - int i; - int nregs =3D 0; - unsigned short regs[256]; - int nchks =3D 0; - unsigned short chks[256]; - /* Flag insns for which no class matched; there should be none. */ - int no_class_found =3D 1; - - for (i =3D 0; i < rdepslen; i++) - { - struct rdep *rs =3D rdeps[i]; - int j; - - if (strcmp (opc->name, "cmp.eq.and") =3D=3D 0 - && startswith (rs->name, "PR%") - && rs->mode =3D=3D 1) - no_class_found =3D 99; - - for (j=3D0; j < rs->nregs;j++) - { - int ic_note =3D 0; - - if (in_iclass (opc, ics[rs->regs[j]], NULL, NULL, &ic_note)) - { - /* We can ignore ic_note 11 for non PR resources. */ - if (ic_note =3D=3D 11 && ! startswith (rs->name, "PR")) - ic_note =3D 0; - - if (ic_note !=3D 0 && rs->regnotes[j] !=3D 0 - && ic_note !=3D rs->regnotes[j] - && !(ic_note =3D=3D 11 && rs->regnotes[j] =3D=3D 1)) - warn (_("IC note %d in opcode %s (IC:%s) conflicts with re= source %s note %d\n"), - ic_note, opc->name, ics[rs->regs[j]]->name, - rs->name, rs->regnotes[j]); - /* Instruction class notes override resource notes. - So far, only note 11 applies to an IC instead of a resour= ce, - and note 11 implies note 1. */ - if (ic_note) - regs[nregs++] =3D RDEP(ic_note, i); - else - regs[nregs++] =3D RDEP(rs->regnotes[j], i); - no_class_found =3D 0; - ++rs->total_regs; - } - } - - for (j =3D 0; j < rs->nchks; j++) - { - int ic_note =3D 0; - - if (in_iclass (opc, ics[rs->chks[j]], NULL, NULL, &ic_note)) - { - /* We can ignore ic_note 11 for non PR resources. */ - if (ic_note =3D=3D 11 && ! startswith (rs->name, "PR")) - ic_note =3D 0; - - if (ic_note !=3D 0 && rs->chknotes[j] !=3D 0 - && ic_note !=3D rs->chknotes[j] - && !(ic_note =3D=3D 11 && rs->chknotes[j] =3D=3D 1)) - warn (_("IC note %d for opcode %s (IC:%s) conflicts with r= esource %s note %d\n"), - ic_note, opc->name, ics[rs->chks[j]]->name, - rs->name, rs->chknotes[j]); - if (ic_note) - chks[nchks++] =3D RDEP(ic_note, i); - else - chks[nchks++] =3D RDEP(rs->chknotes[j], i); - no_class_found =3D 0; - ++rs->total_chks; - } - } - } - - if (no_class_found) - warn (_("opcode %s has no class (ops %d %d %d)\n"), - opc->name, - opc->operands[0], opc->operands[1], opc->operands[2]); - - return insert_dependencies (nchks, chks, nregs, regs); -} -=0C -static void -insert_completer_entry (struct ia64_opcode *opc, struct main_entry *tabent, - int order) -{ - struct completer_entry **ptr =3D &tabent->completers; - struct completer_entry *parent =3D NULL; - char pcopy[129], *prefix; - int at_end =3D 0; - - if (strlen (opc->name) > 128) - abort (); - - strcpy (pcopy, opc->name); - prefix =3D pcopy + get_prefix_len (pcopy); - - if (prefix[0] !=3D '\0') - prefix++; - - while (! at_end) - { - int need_new_ent =3D 1; - int plen =3D get_prefix_len (prefix); - struct string_entry *sent; - - at_end =3D (prefix[plen] =3D=3D '\0'); - prefix[plen] =3D '\0'; - sent =3D insert_string (prefix); - - while (*ptr !=3D NULL) - { - int cmpres =3D sent->num - (*ptr)->name->num; - - if (cmpres =3D=3D 0) - { - need_new_ent =3D 0; - break; - } - else - ptr =3D &((*ptr)->alternative); - } - - if (need_new_ent) - { - struct completer_entry *nent =3D tmalloc (struct completer_entry); - - nent->name =3D sent; - nent->parent =3D parent; - nent->addl_entries =3D NULL; - nent->alternative =3D *ptr; - *ptr =3D nent; - nent->is_terminal =3D 0; - nent->dependencies =3D -1; - } - - if (! at_end) - { - parent =3D *ptr; - ptr =3D &((*ptr)->addl_entries); - prefix +=3D plen + 1; - } - } - - if ((*ptr)->is_terminal) - abort (); - - (*ptr)->is_terminal =3D 1; - (*ptr)->mask =3D (ia64_insn)-1; - (*ptr)->bits =3D opc->opcode; - (*ptr)->dependencies =3D insert_opcode_dependencies (opc, *ptr); - (*ptr)->order =3D order; -} -=0C -static void -print_completer_entry (struct completer_entry *ent) -{ - int moffset =3D 0; - ia64_insn mask =3D ent->mask, bits =3D ent->bits; - - if (mask !=3D 0) - { - while (! (mask & 1)) - { - moffset++; - mask =3D mask >> 1; - bits =3D bits >> 1; - } - - if (bits & 0xffffffff00000000LL) - abort (); - } - - printf (" { 0x%x, 0x%x, %d, %d, %d, %d, %d, %d },\n", - (int)bits, - (int)mask, - ent->name->num, - ent->alternative !=3D NULL ? ent->alternative->num : -1, - ent->addl_entries !=3D NULL ? ent->addl_entries->num : -1, - moffset, - ent->is_terminal ? 1 : 0, - ent->dependencies); -} -=0C -static void -print_completer_table (void) -{ - int x; - - printf ("static const struct ia64_completer_table\ncompleter_table[] =3D= {\n"); - for (x =3D 0; x < glistlen; x++) - print_completer_entry (glist[x]); - printf ("};\n\n"); -} -=0C -static int -opcodes_eq (struct ia64_opcode *opc1, struct ia64_opcode *opc2) -{ - int x; - int plen1, plen2; - - if ((opc1->mask !=3D opc2->mask) || (opc1->type !=3D opc2->type) - || (opc1->num_outputs !=3D opc2->num_outputs) - || (opc1->flags !=3D opc2->flags)) - return 0; - - for (x =3D 0; x < 5; x++) - if (opc1->operands[x] !=3D opc2->operands[x]) - return 0; - - plen1 =3D get_prefix_len (opc1->name); - plen2 =3D get_prefix_len (opc2->name); - - if (plen1 =3D=3D plen2 && (memcmp (opc1->name, opc2->name, plen1) =3D=3D= 0)) - return 1; - - return 0; -} -=0C -static void -add_opcode_entry (struct ia64_opcode *opc) -{ - struct main_entry **place; - struct string_entry *name; - char prefix[129]; - int found_it =3D 0; - - if (strlen (opc->name) > 128) - abort (); - - place =3D &maintable; - strcpy (prefix, opc->name); - prefix[get_prefix_len (prefix)] =3D '\0'; - name =3D insert_string (prefix); - - /* Walk the list of opcode table entries. If it's a new - instruction, allocate and fill in a new entry. Note - the main table is alphabetical by opcode name. */ - - while (*place !=3D NULL) - { - if ((*place)->name->num =3D=3D name->num - && opcodes_eq ((*place)->opcode, opc)) - { - found_it =3D 1; - break; - } - if ((*place)->name->num > name->num) - break; - - place =3D &((*place)->next); - } - if (! found_it) - { - struct main_entry *nent =3D tmalloc (struct main_entry); - - nent->name =3D name; - nent->opcode =3D opc; - nent->next =3D *place; - nent->completers =3D 0; - *place =3D nent; - - if (otlen =3D=3D ottotlen) - { - ottotlen +=3D 20; - ordered_table =3D (struct main_entry **) - xrealloc (ordered_table, sizeof (struct main_entry *) * ottotl= en); - } - ordered_table[otlen++] =3D nent; - } - - insert_completer_entry (opc, *place, opcode_count++); -} -=0C -static void -print_main_table (void) -{ - struct main_entry *ptr =3D maintable; - int tindex =3D 0; - - printf ("static const struct ia64_main_table\nmain_table[] =3D {\n"); - while (ptr !=3D NULL) - { - printf (" { %d, %d, %d, 0x%016" PRIx64 "ull, 0x%016" PRIx64 - "ull, { %d, %d, %d, %d, %d }, 0x%x, %d, },\n", - ptr->name->num, - ptr->opcode->type, - ptr->opcode->num_outputs, - ptr->opcode->opcode, - ptr->opcode->mask, - ptr->opcode->operands[0], - ptr->opcode->operands[1], - ptr->opcode->operands[2], - ptr->opcode->operands[3], - ptr->opcode->operands[4], - ptr->opcode->flags, - ptr->completers->num); - - ptr->main_index =3D tindex++; - - ptr =3D ptr->next; - } - printf ("};\n\n"); -} -=0C -static void -shrink (struct ia64_opcode *table) -{ - int curr_opcode; - - for (curr_opcode =3D 0; table[curr_opcode].name !=3D NULL; curr_opcode++) - { - add_opcode_entry (table + curr_opcode); - if (table[curr_opcode].num_outputs =3D=3D 2 - && ((table[curr_opcode].operands[0] =3D=3D IA64_OPND_P1 - && table[curr_opcode].operands[1] =3D=3D IA64_OPND_P2) - || (table[curr_opcode].operands[0] =3D=3D IA64_OPND_P2 - && table[curr_opcode].operands[1] =3D=3D IA64_OPND_P1))) - { - struct ia64_opcode *alias =3D tmalloc(struct ia64_opcode); - unsigned i; - - *alias =3D table[curr_opcode]; - for (i =3D 2; i < NELEMS (alias->operands); ++i) - alias->operands[i - 1] =3D alias->operands[i]; - alias->operands[NELEMS (alias->operands) - 1] =3D IA64_OPND_NIL; - --alias->num_outputs; - alias->flags |=3D PSEUDO; - add_opcode_entry (alias); - } - } -} -=0C - -/* Program options. */ -#define OPTION_SRCDIR 200 - -struct option long_options[] =3D -{ - {"srcdir", required_argument, NULL, OPTION_SRCDIR}, - {"debug", no_argument, NULL, 'd'}, - {"version", no_argument, NULL, 'V'}, - {"help", no_argument, NULL, 'h'}, - {0, no_argument, NULL, 0} -}; - -static void -print_version (void) -{ - printf ("%s: version 1.0\n", program_name); - xexit (0); -} - -static void -usage (FILE * stream, int status) -{ - fprintf (stream, "Usage: %s [-V | --version] [-d | --debug] [--srcdir=3D= dirname] [--help]\n", - program_name); - xexit (status); -} - -int -main (int argc, char **argv) -{ - extern int chdir (char *); - char *srcdir =3D NULL; - int c; - - program_name =3D *argv; - xmalloc_set_program_name (program_name); - - while ((c =3D getopt_long (argc, argv, "vVdh", long_options, 0)) !=3D EO= F) - switch (c) - { - case OPTION_SRCDIR: - srcdir =3D optarg; - break; - case 'V': - case 'v': - print_version (); - break; - case 'd': - debug =3D 1; - break; - case 'h': - case '?': - usage (stderr, 0); - default: - case 0: - break; - } - - if (optind !=3D argc) - usage (stdout, 1); - - if (srcdir !=3D NULL) - if (chdir (srcdir) !=3D 0) - fail (_("unable to change directory to \"%s\", errno =3D %s\n"), - srcdir, strerror (errno)); - - load_insn_classes (); - load_dependencies (); - - shrink (ia64_opcodes_a); - shrink (ia64_opcodes_b); - shrink (ia64_opcodes_f); - shrink (ia64_opcodes_i); - shrink (ia64_opcodes_m); - shrink (ia64_opcodes_x); - shrink (ia64_opcodes_d); - - collapse_redundant_completers (); - - printf ("/* This file is automatically generated by ia64-gen. Do not ed= it! */\n"); - printf ("/* Copyright (C) 2007-2024 Free Software Foundation, Inc.\n\ -\n\ - This file is part of the GNU opcodes library.\n\ -\n\ - This library is free software; you can redistribute it and/or modify\n\ - it under the terms of the GNU General Public License as published by\n\ - the Free Software Foundation; either version 3, or (at your option)\n\ - any later version.\n\ -\n\ - It is distributed in the hope that it will be useful, but WITHOUT\n\ - ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\n\ - or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public\n\ - License for more details.\n\ -\n\ - You should have received a copy of the GNU General Public License\n\ - along with this program; see the file COPYING. If not, write to the\n\ - Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA\= n\ - 02110-1301, USA. */\n"); - - print_string_table (); - print_dependency_table (); - print_completer_table (); - print_main_table (); - - generate_disassembler (); - - exit (0); -} diff --git a/opcodes/ia64-ic.tbl b/opcodes/ia64-ic.tbl deleted file mode 100644 index 14fe7dead70..00000000000 --- a/opcodes/ia64-ic.tbl +++ /dev/null @@ -1,258 +0,0 @@ -Class; Events/Instructions -all; IC:predicatable-instructions, IC:unpredicatable-instructions -branches; IC:indirect-brs, IC:ip-rel-brs -cfm-readers; IC:fr-readers, IC:fr-writers, IC:gr-readers, IC:gr-writers, I= C:mod-sched-brs, IC:predicatable-instructions, IC:pr-writers, alloc, br.cal= l, brl.call, br.ret, cover, loadrs, rfi, IC:chk-a, invala.e -chk-a; chk.a.clr, chk.a.nc -cmpxchg; cmpxchg1, cmpxchg2, cmpxchg4, cmpxchg8, cmp8xchg16 -czx; czx1, czx2 -fcmp-s0; fcmp[Field(sf)=3D=3Ds0] -fcmp-s1; fcmp[Field(sf)=3D=3Ds1] -fcmp-s2; fcmp[Field(sf)=3D=3Ds2] -fcmp-s3; fcmp[Field(sf)=3D=3Ds3] -fetchadd; fetchadd4, fetchadd8 -fp-arith; fadd, famax, famin, fcvt.fx, fcvt.fxu, fcvt.xuf, fma, fmax, fmin= , fmpy, fms, fnma, fnmpy, fnorm, fpamax, fpamin, fpcvt.fx, fpcvt.fxu, fpma,= fpmax, fpmin, fpmpy, fpms, fpnma, fpnmpy, fprcpa, fprsqrta, frcpa, frsqrta= , fsub -fp-arith-s0; IC:fp-arith[Field(sf)=3D=3Ds0] -fp-arith-s1; IC:fp-arith[Field(sf)=3D=3Ds1] -fp-arith-s2; IC:fp-arith[Field(sf)=3D=3Ds2] -fp-arith-s3; IC:fp-arith[Field(sf)=3D=3Ds3] -fp-non-arith; fabs, fand, fandcm, fclass, fcvt.xf, fmerge, fmix, fneg, fne= gabs, for, fpabs, fpmerge, fpack, fpneg, fpnegabs, fselect, fswap, fsxt, fx= or, xma, xmpy -fpcmp-s0; fpcmp[Field(sf)=3D=3Ds0] -fpcmp-s1; fpcmp[Field(sf)=3D=3Ds1] -fpcmp-s2; fpcmp[Field(sf)=3D=3Ds2] -fpcmp-s3; fpcmp[Field(sf)=3D=3Ds3] -fr-readers; IC:fp-arith, IC:fp-non-arith, IC:mem-writers-fp, IC:pr-writers= -fp, chk.s[Format in {M21}], getf -fr-writers; IC:fp-arith, IC:fp-non-arith\fclass, IC:mem-readers-fp, setf -gr-readers; IC:gr-readers-writers, IC:mem-readers, IC:mem-writers, chk.s, = cmp, cmp4, fc, itc.i, itc.d, itr.i, itr.d, IC:mov-to-AR-gr, IC:mov-to-BR, I= C:mov-to-CR, IC:mov-to-IND, IC:mov-from-IND, IC:mov-to-PR-allreg, IC:mov-to= -PSR-l, IC:mov-to-PSR-um, IC:probe-all, ptc.e, ptc.g, ptc.ga, ptc.l, ptr.i,= ptr.d, setf, tbit, tnat -gr-readers-writers; IC:mov-from-IND, add, addl, addp4, adds, and, andcm, c= lz, IC:czx, dep\dep[Format in {I13}], extr, IC:mem-readers-int, IC:ld-all-p= ostinc, IC:lfetch-postinc, IC:mix, IC:mux, or, IC:pack, IC:padd, IC:pavg, I= C:pavgsub, IC:pcmp, IC:pmax, IC:pmin, IC:pmpy, IC:pmpyshr, popcnt, IC:probe= -nofault, IC:psad, IC:pshl, IC:pshladd, IC:pshr, IC:pshradd, IC:psub, shl, = shladd, shladdp4, shr, shrp, shrp4, IC:st-postinc, sub, IC:sxt, tak, thash,= tpa, ttag, IC:unpack, xor, IC:zxt -gr-writers; alloc, dep, getf, IC:gr-readers-writers, IC:mem-readers-int, I= C:mov-from-AR, IC:mov-from-BR, IC:mov-from-CR, IC:mov-from-PR, IC:mov-from-= PSR, IC:mov-from-PSR-um, IC:mov-ip, movl -indirect-brp; brp[Format in {B7}] -indirect-brs; br.call[Format in {B5}], br.cond[Format in {B4}], br.ia, br.= ret -invala-all; invala[Format in {M24}], invala.e -ip-rel-brs; IC:mod-sched-brs, br.call[Format in {B3}], brl.call, brl.cond,= br.cond[Format in {B1}], br.cloop -ld; ld1, ld2, ld4, ld8, ld8.fill, ld16 -ld-a; ld1.a, ld2.a, ld4.a, ld8.a -ld-all-postinc; IC:ld[Format in {M2 M3}], IC:ldfp[Format in {M12}], IC:ldf= [Format in {M7 M8}] -ld-c; IC:ld-c-nc, IC:ld-c-clr -ld-c-clr; ld1.c.clr, ld2.c.clr, ld4.c.clr, ld8.c.clr, IC:ld-c-clr-acq -ld-c-clr-acq; ld1.c.clr.acq, ld2.c.clr.acq, ld4.c.clr.acq, ld8.c.clr.acq -ld-c-nc; ld1.c.nc, ld2.c.nc, ld4.c.nc, ld8.c.nc -ld-s; ld1.s, ld2.s, ld4.s, ld8.s -ld-sa; ld1.sa, ld2.sa, ld4.sa, ld8.sa -ldf; ldfs, ldfd, ldfe, ldf8, ldf.fill -ldf-a; ldfs.a, ldfd.a, ldfe.a, ldf8.a -ldf-c; IC:ldf-c-nc, IC:ldf-c-clr -ldf-c-clr; ldfs.c.clr, ldfd.c.clr, ldfe.c.clr, ldf8.c.clr -ldf-c-nc; ldfs.c.nc, ldfd.c.nc, ldfe.c.nc, ldf8.c.nc -ldf-s; ldfs.s, ldfd.s, ldfe.s, ldf8.s -ldf-sa; ldfs.sa, ldfd.sa, ldfe.sa, ldf8.sa -ldfp; ldfps, ldfpd, ldfp8 -ldfp-a; ldfps.a, ldfpd.a, ldfp8.a -ldfp-c; IC:ldfp-c-nc, IC:ldfp-c-clr -ldfp-c-clr; ldfps.c.clr, ldfpd.c.clr, ldfp8.c.clr -ldfp-c-nc; ldfps.c.nc, ldfpd.c.nc, ldfp8.c.nc -ldfp-s; ldfps.s, ldfpd.s, ldfp8.s -ldfp-sa; ldfps.sa, ldfpd.sa, ldfp8.sa -lfetch-all; lfetch -lfetch-fault; lfetch[Field(lftype)=3D=3Dfault] -lfetch-nofault; lfetch[Field(lftype)=3D=3D] -lfetch-postinc; lfetch[Format in {M14 M15}] -mem-readers; IC:mem-readers-fp, IC:mem-readers-int -mem-readers-alat; IC:ld-a, IC:ldf-a, IC:ldfp-a, IC:ld-sa, IC:ldf-sa, IC:ld= fp-sa, IC:ld-c, IC:ldf-c, IC:ldfp-c -mem-readers-fp; IC:ldf, IC:ldfp -mem-readers-int; IC:cmpxchg, IC:fetchadd, IC:xchg, IC:ld -mem-readers-spec; IC:ld-s, IC:ld-sa, IC:ldf-s, IC:ldf-sa, IC:ldfp-s, IC:ld= fp-sa -mem-writers; IC:mem-writers-fp, IC:mem-writers-int -mem-writers-fp; IC:stf -mem-writers-int; IC:cmpxchg, IC:fetchadd, IC:xchg, IC:st -mix; mix1, mix2, mix4 -mod-sched-brs; br.cexit, br.ctop, br.wexit, br.wtop -mod-sched-brs-counted; br.cexit, br.cloop, br.ctop -mov-from-AR; IC:mov-from-AR-M, IC:mov-from-AR-I, IC:mov-from-AR-IM -mov-from-AR-BSP; IC:mov-from-AR-M[Field(ar3) =3D=3D BSP] -mov-from-AR-BSPSTORE; IC:mov-from-AR-M[Field(ar3) =3D=3D BSPSTORE] -mov-from-AR-CCV; IC:mov-from-AR-M[Field(ar3) =3D=3D CCV] -mov-from-AR-CFLG; IC:mov-from-AR-M[Field(ar3) =3D=3D CFLG] -mov-from-AR-CSD; IC:mov-from-AR-M[Field(ar3) =3D=3D CSD] -mov-from-AR-EC; IC:mov-from-AR-I[Field(ar3) =3D=3D EC] -mov-from-AR-EFLAG; IC:mov-from-AR-M[Field(ar3) =3D=3D EFLAG] -mov-from-AR-FCR; IC:mov-from-AR-M[Field(ar3) =3D=3D FCR] -mov-from-AR-FDR; IC:mov-from-AR-M[Field(ar3) =3D=3D FDR] -mov-from-AR-FIR; IC:mov-from-AR-M[Field(ar3) =3D=3D FIR] -mov-from-AR-FPSR; IC:mov-from-AR-M[Field(ar3) =3D=3D FPSR] -mov-from-AR-FSR; IC:mov-from-AR-M[Field(ar3) =3D=3D FSR] -mov-from-AR-I; mov_ar[Format in {I28}] -mov-from-AR-ig; IC:mov-from-AR-IM[Field(ar3) in {48-63 112-127}] -mov-from-AR-IM; mov_ar[Format in {I28 M31}] -mov-from-AR-ITC; IC:mov-from-AR-M[Field(ar3) =3D=3D ITC] -mov-from-AR-K; IC:mov-from-AR-M[Field(ar3) in {K0 K1 K2 K3 K4 K5 K6 K7}] -mov-from-AR-LC; IC:mov-from-AR-I[Field(ar3) =3D=3D LC] -mov-from-AR-M; mov_ar[Format in {M31}] -mov-from-AR-PFS; IC:mov-from-AR-I[Field(ar3) =3D=3D PFS] -mov-from-AR-RNAT; IC:mov-from-AR-M[Field(ar3) =3D=3D RNAT] -mov-from-AR-RSC; IC:mov-from-AR-M[Field(ar3) =3D=3D RSC] -mov-from-AR-RUC; IC:mov-from-AR-M[Field(ar3) =3D=3D RUC] -mov-from-AR-rv; IC:none -mov-from-AR-SSD; IC:mov-from-AR-M[Field(ar3) =3D=3D SSD] -mov-from-AR-UNAT; IC:mov-from-AR-M[Field(ar3) =3D=3D UNAT] -mov-from-BR; mov_br[Format in {I22}] -mov-from-CR; mov_cr[Format in {M33}] -mov-from-CR-CMCV; IC:mov-from-CR[Field(cr3) =3D=3D CMCV] -mov-from-CR-DCR; IC:mov-from-CR[Field(cr3) =3D=3D DCR] -mov-from-CR-EOI; IC:mov-from-CR[Field(cr3) =3D=3D EOI] -mov-from-CR-GPTA; IC:mov-from-CR[Field(cr3) =3D=3D GPTA] -mov-from-CR-IFA; IC:mov-from-CR[Field(cr3) =3D=3D IFA] -mov-from-CR-IFS; IC:mov-from-CR[Field(cr3) =3D=3D IFS] -mov-from-CR-IHA; IC:mov-from-CR[Field(cr3) =3D=3D IHA] -mov-from-CR-IIB; IC:mov-from-CR[Field(cr3) in {IIB0 IIB1}] -mov-from-CR-IIM; IC:mov-from-CR[Field(cr3) =3D=3D IIM] -mov-from-CR-IIP; IC:mov-from-CR[Field(cr3) =3D=3D IIP] -mov-from-CR-IIPA; IC:mov-from-CR[Field(cr3) =3D=3D IIPA] -mov-from-CR-IPSR; IC:mov-from-CR[Field(cr3) =3D=3D IPSR] -mov-from-CR-IRR; IC:mov-from-CR[Field(cr3) in {IRR0 IRR1 IRR2 IRR3}] -mov-from-CR-ISR; IC:mov-from-CR[Field(cr3) =3D=3D ISR] -mov-from-CR-ITIR; IC:mov-from-CR[Field(cr3) =3D=3D ITIR] -mov-from-CR-ITM; IC:mov-from-CR[Field(cr3) =3D=3D ITM] -mov-from-CR-ITV; IC:mov-from-CR[Field(cr3) =3D=3D ITV] -mov-from-CR-IVA; IC:mov-from-CR[Field(cr3) =3D=3D IVA] -mov-from-CR-IVR; IC:mov-from-CR[Field(cr3) =3D=3D IVR] -mov-from-CR-LID; IC:mov-from-CR[Field(cr3) =3D=3D LID] -mov-from-CR-LRR; IC:mov-from-CR[Field(cr3) in {LRR0 LRR1}] -mov-from-CR-PMV; IC:mov-from-CR[Field(cr3) =3D=3D PMV] -mov-from-CR-PTA; IC:mov-from-CR[Field(cr3) =3D=3D PTA] -mov-from-CR-rv; IC:none -mov-from-CR-TPR; IC:mov-from-CR[Field(cr3) =3D=3D TPR] -mov-from-IND; mov_indirect[Format in {M43}] -mov-from-IND-CPUID; IC:mov-from-IND[Field(ireg) =3D=3D cpuid] -mov-from-IND-DBR; IC:mov-from-IND[Field(ireg) =3D=3D dbr] -mov-from-IND-IBR; IC:mov-from-IND[Field(ireg) =3D=3D ibr] -mov-from-IND-MSR; IC:mov-from-IND[Field(ireg) =3D=3D msr] -mov-from-IND-PKR; IC:mov-from-IND[Field(ireg) =3D=3D pkr] -mov-from-IND-PMC; IC:mov-from-IND[Field(ireg) =3D=3D pmc] -mov-from-IND-PMD; IC:mov-from-IND[Field(ireg) =3D=3D pmd] -mov-from-IND-priv; IC:mov-from-IND[Field(ireg) in {dbr ibr pkr pmc rr}] -mov-from-IND-RR; IC:mov-from-IND[Field(ireg) =3D=3D rr] -mov-from-interruption-CR; IC:mov-from-CR-ITIR, IC:mov-from-CR-IFS, IC:mov-= from-CR-IIB, IC:mov-from-CR-IIM, IC:mov-from-CR-IIP, IC:mov-from-CR-IPSR, I= C:mov-from-CR-ISR, IC:mov-from-CR-IFA, IC:mov-from-CR-IHA, IC:mov-from-CR-I= IPA -mov-from-PR; mov_pr[Format in {I25}] -mov-from-PSR; mov_psr[Format in {M36}] -mov-from-PSR-um; mov_um[Format in {M36}] -mov-ip; mov_ip[Format in {I25}] -mov-to-AR; IC:mov-to-AR-M, IC:mov-to-AR-I -mov-to-AR-BSP; IC:mov-to-AR-M[Field(ar3) =3D=3D BSP] -mov-to-AR-BSPSTORE; IC:mov-to-AR-M[Field(ar3) =3D=3D BSPSTORE] -mov-to-AR-CCV; IC:mov-to-AR-M[Field(ar3) =3D=3D CCV] -mov-to-AR-CFLG; IC:mov-to-AR-M[Field(ar3) =3D=3D CFLG] -mov-to-AR-CSD; IC:mov-to-AR-M[Field(ar3) =3D=3D CSD] -mov-to-AR-EC; IC:mov-to-AR-I[Field(ar3) =3D=3D EC] -mov-to-AR-EFLAG; IC:mov-to-AR-M[Field(ar3) =3D=3D EFLAG] -mov-to-AR-FCR; IC:mov-to-AR-M[Field(ar3) =3D=3D FCR] -mov-to-AR-FDR; IC:mov-to-AR-M[Field(ar3) =3D=3D FDR] -mov-to-AR-FIR; IC:mov-to-AR-M[Field(ar3) =3D=3D FIR] -mov-to-AR-FPSR; IC:mov-to-AR-M[Field(ar3) =3D=3D FPSR] -mov-to-AR-FSR; IC:mov-to-AR-M[Field(ar3) =3D=3D FSR] -mov-to-AR-gr; IC:mov-to-AR-M[Format in {M29}], IC:mov-to-AR-I[Format in {I= 26}] -mov-to-AR-I; mov_ar[Format in {I26 I27}] -mov-to-AR-ig; IC:mov-to-AR-IM[Field(ar3) in {48-63 112-127}] -mov-to-AR-IM; mov_ar[Format in {I26 I27 M29 M30}] -mov-to-AR-ITC; IC:mov-to-AR-M[Field(ar3) =3D=3D ITC] -mov-to-AR-K; IC:mov-to-AR-M[Field(ar3) in {K0 K1 K2 K3 K4 K5 K6 K7}] -mov-to-AR-LC; IC:mov-to-AR-I[Field(ar3) =3D=3D LC] -mov-to-AR-M; mov_ar[Format in {M29 M30}] -mov-to-AR-PFS; IC:mov-to-AR-I[Field(ar3) =3D=3D PFS] -mov-to-AR-RNAT; IC:mov-to-AR-M[Field(ar3) =3D=3D RNAT] -mov-to-AR-RSC; IC:mov-to-AR-M[Field(ar3) =3D=3D RSC] -mov-to-AR-RUC; IC:mov-to-AR-M[Field(ar3) =3D=3D RUC] -mov-to-AR-SSD; IC:mov-to-AR-M[Field(ar3) =3D=3D SSD] -mov-to-AR-UNAT; IC:mov-to-AR-M[Field(ar3) =3D=3D UNAT] -mov-to-BR; mov_br[Format in {I21}] -mov-to-CR; mov_cr[Format in {M32}] -mov-to-CR-CMCV; IC:mov-to-CR[Field(cr3) =3D=3D CMCV] -mov-to-CR-DCR; IC:mov-to-CR[Field(cr3) =3D=3D DCR] -mov-to-CR-EOI; IC:mov-to-CR[Field(cr3) =3D=3D EOI] -mov-to-CR-GPTA; IC:mov-to-CR[Field(cr3) =3D=3D GPTA] -mov-to-CR-IFA; IC:mov-to-CR[Field(cr3) =3D=3D IFA] -mov-to-CR-IFS; IC:mov-to-CR[Field(cr3) =3D=3D IFS] -mov-to-CR-IHA; IC:mov-to-CR[Field(cr3) =3D=3D IHA] -mov-to-CR-IIB; IC:mov-to-CR[Field(cr3) in {IIB0 IIB1}] -mov-to-CR-IIM; IC:mov-to-CR[Field(cr3) =3D=3D IIM] -mov-to-CR-IIP; IC:mov-to-CR[Field(cr3) =3D=3D IIP] -mov-to-CR-IIPA; IC:mov-to-CR[Field(cr3) =3D=3D IIPA] -mov-to-CR-IPSR; IC:mov-to-CR[Field(cr3) =3D=3D IPSR] -mov-to-CR-IRR; IC:mov-to-CR[Field(cr3) in {IRR0 IRR1 IRR2 IRR3}] -mov-to-CR-ISR; IC:mov-to-CR[Field(cr3) =3D=3D ISR] -mov-to-CR-ITIR; IC:mov-to-CR[Field(cr3) =3D=3D ITIR] -mov-to-CR-ITM; IC:mov-to-CR[Field(cr3) =3D=3D ITM] -mov-to-CR-ITV; IC:mov-to-CR[Field(cr3) =3D=3D ITV] -mov-to-CR-IVA; IC:mov-to-CR[Field(cr3) =3D=3D IVA] -mov-to-CR-IVR; IC:mov-to-CR[Field(cr3) =3D=3D IVR] -mov-to-CR-LID; IC:mov-to-CR[Field(cr3) =3D=3D LID] -mov-to-CR-LRR; IC:mov-to-CR[Field(cr3) in {LRR0 LRR1}] -mov-to-CR-PMV; IC:mov-to-CR[Field(cr3) =3D=3D PMV] -mov-to-CR-PTA; IC:mov-to-CR[Field(cr3) =3D=3D PTA] -mov-to-CR-TPR; IC:mov-to-CR[Field(cr3) =3D=3D TPR] -mov-to-DAHR; mov_dahr[Format in {M50}] -mov-to-IND; mov_indirect[Format in {M42}] -mov-to-IND-CPUID; IC:mov-to-IND[Field(ireg) =3D=3D cpuid] -mov-to-IND-DBR; IC:mov-to-IND[Field(ireg) =3D=3D dbr] -mov-to-IND-IBR; IC:mov-to-IND[Field(ireg) =3D=3D ibr] -mov-to-IND-MSR; IC:mov-to-IND[Field(ireg) =3D=3D msr] -mov-to-IND-PKR; IC:mov-to-IND[Field(ireg) =3D=3D pkr] -mov-to-IND-PMC; IC:mov-to-IND[Field(ireg) =3D=3D pmc] -mov-to-IND-PMD; IC:mov-to-IND[Field(ireg) =3D=3D pmd] -mov-to-IND-priv; IC:mov-to-IND -mov-to-IND-RR; IC:mov-to-IND[Field(ireg) =3D=3D rr] -mov-to-interruption-CR; IC:mov-to-CR-ITIR, IC:mov-to-CR-IFS, IC:mov-to-CR-= IIB, IC:mov-to-CR-IIM, IC:mov-to-CR-IIP, IC:mov-to-CR-IPSR, IC:mov-to-CR-IS= R, IC:mov-to-CR-IFA, IC:mov-to-CR-IHA, IC:mov-to-CR-IIPA -mov-to-PR; IC:mov-to-PR-allreg, IC:mov-to-PR-rotreg -mov-to-PR-allreg; mov_pr[Format in {I23}] -mov-to-PR-rotreg; mov_pr[Format in {I24}] -mov-to-PSR-l; mov_psr[Format in {M35}] -mov-to-PSR-um; mov_um[Format in {M35}] -mux; mux1, mux2 -non-access; fc, lfetch, IC:probe-all, tpa, tak -none; - -pack; pack2, pack4 -padd; padd1, padd2, padd4 -pavg; pavg1, pavg2 -pavgsub; pavgsub1, pavgsub2 -pcmp; pcmp1, pcmp2, pcmp4 -pmax; pmax1, pmax2 -pmin; pmin1, pmin2 -pmpy; pmpy2 -pmpyshr; pmpyshr2 -pr-and-writers; IC:pr-gen-writers-int[Field(ctype) in {and andcm}], IC:pr-= gen-writers-int[Field(ctype) in {or.andcm and.orcm}] -pr-gen-writers-fp; fclass, fcmp -pr-gen-writers-int; cmp, cmp4, tbit, tf, tnat -pr-norm-writers-fp; IC:pr-gen-writers-fp[Field(ctype)=3D=3D] -pr-norm-writers-int; IC:pr-gen-writers-int[Field(ctype)=3D=3D] -pr-or-writers; IC:pr-gen-writers-int[Field(ctype) in {or orcm}], IC:pr-gen= -writers-int[Field(ctype) in {or.andcm and.orcm}] -pr-readers-br; br.call, br.cond, brl.call, brl.cond, br.ret, br.wexit, br.= wtop, break.b, hint.b, nop.b, IC:ReservedBQP -pr-readers-nobr-nomovpr; add, addl, addp4, adds, and, andcm, break.f, brea= k.i, break.m, break.x, chk.s, IC:chk-a, cmp, cmp4, IC:cmpxchg, clz, IC:czx,= dep, extr, IC:fp-arith, IC:fp-non-arith, fc, fchkf, fclrf, fcmp, IC:fetcha= dd, fpcmp, fsetc, fwb, getf, hint.f, hint.i, hint.m, hint.x, IC:invala-all,= itc.i, itc.d, itr.i, itr.d, IC:ld, IC:ldf, IC:ldfp, IC:lfetch-all, mf, IC:= mix, IC:mov-from-AR-M, IC:mov-from-AR-IM, IC:mov-from-AR-I, IC:mov-to-AR-M,= IC:mov-to-AR-I, IC:mov-to-AR-IM, IC:mov-to-BR, IC:mov-from-BR, IC:mov-to-C= R, IC:mov-from-CR, IC:mov-to-IND, IC:mov-from-IND, IC:mov-ip, IC:mov-to-PSR= -l, IC:mov-to-PSR-um, IC:mov-from-PSR, IC:mov-from-PSR-um, movl, IC:mux, no= p.f, nop.i, nop.m, nop.x, or, IC:pack, IC:padd, IC:pavg, IC:pavgsub, IC:pcm= p, IC:pmax, IC:pmin, IC:pmpy, IC:pmpyshr, popcnt, IC:probe-all, IC:psad, IC= :pshl, IC:pshladd, IC:pshr, IC:pshradd, IC:psub, ptc.e, ptc.g, ptc.ga, ptc.= l, ptr.d, ptr.i, IC:ReservedQP, rsm, setf, shl, shladd, shladdp4, shr, shrp= , shrp4, srlz.i, srlz.d, ssm, IC:st, IC:stf, sub, sum, IC:sxt, sync, tak, t= bit, tf, thash, tnat, tpa, ttag, IC:unpack, IC:xchg, xma, xmpy, xor, IC:zxt -pr-unc-writers-fp; IC:pr-gen-writers-fp[Field(ctype)=3D=3Dunc]+11, fprcpa+= 11, fprsqrta+11, frcpa+11, frsqrta+11 -pr-unc-writers-int; IC:pr-gen-writers-int[Field(ctype)=3D=3Dunc]+11 -pr-writers; IC:pr-writers-int, IC:pr-writers-fp -pr-writers-fp; IC:pr-norm-writers-fp, IC:pr-unc-writers-fp -pr-writers-int; IC:pr-norm-writers-int, IC:pr-unc-writers-int, IC:pr-and-w= riters, IC:pr-or-writers -predicatable-instructions; IC:mov-from-PR, IC:mov-to-PR, IC:pr-readers-br,= IC:pr-readers-nobr-nomovpr -priv-ops; IC:mov-to-IND-priv, bsw, itc.i, itc.d, itr.i, itr.d, IC:mov-to-C= R, IC:mov-from-CR, IC:mov-to-PSR-l, IC:mov-from-PSR, IC:mov-from-IND-priv, = ptc.e, ptc.g, ptc.ga, ptc.l, ptr.i, ptr.d, rfi, rsm, ssm, tak, tpa, vmsw -probe-all; IC:probe-fault, IC:probe-nofault -probe-fault; probe[Format in {M40}] -probe-nofault; probe[Format in {M38 M39}] -psad; psad1 -pshl; pshl2, pshl4 -pshladd; pshladd2 -pshr; pshr2, pshr4 -pshradd; pshradd2 -psub; psub1, psub2, psub4 -ReservedBQP; -+15 -ReservedQP; -+16 -rse-readers; alloc, br.call, br.ia, br.ret, brl.call, cover, flushrs, load= rs, IC:mov-from-AR-BSP, IC:mov-from-AR-BSPSTORE, IC:mov-to-AR-BSPSTORE, IC:= mov-from-AR-RNAT, IC:mov-to-AR-RNAT, rfi -rse-writers; alloc, br.call, br.ia, br.ret, brl.call, cover, flushrs, load= rs, IC:mov-to-AR-BSPSTORE, rfi -st; st1, st2, st4, st8, st8.spill, st16 -st-postinc; IC:stf[Format in {M10}], IC:st[Format in {M5}] -stf; stfs, stfd, stfe, stf8, stf.spill -sxt; sxt1, sxt2, sxt4 -sys-mask-writers-partial; rsm, ssm -unpack; unpack1, unpack2, unpack4 -unpredicatable-instructions; alloc, br.cloop, br.ctop, br.cexit, br.ia, br= p, bsw, clrrrb, cover, epc, flushrs, loadrs, rfi, vmsw -user-mask-writers-partial; rum, sum -xchg; xchg1, xchg2, xchg4, xchg8 -zxt; zxt1, zxt2, zxt4 diff --git a/opcodes/ia64-opc-a.c b/opcodes/ia64-opc-a.c deleted file mode 100644 index c3a63b564c2..00000000000 --- a/opcodes/ia64-opc-a.c +++ /dev/null @@ -1,418 +0,0 @@ -/* ia64-opc-a.c -- IA-64 `A' opcode table. - Copyright (C) 1998-2024 Free Software Foundation, Inc. - Contributed by David Mosberger-Tang - - This file is part of the GNU opcodes library. - - This library is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3, or (at your option) - any later version. - - It is distributed in the hope that it will be useful, but WITHOUT - ANY WARRANTY; without even the implied warranty of MERCHANTABILITY - or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public - License for more details. - - You should have received a copy of the GNU General Public License - along with this file; see the file COPYING. If not, write to the - Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston, - MA 02110-1301, USA. */ - -#include "ia64-opc.h" - -#define A IA64_TYPE_A, 1 -#define A2 IA64_TYPE_A, 2 - -/* instruction bit fields: */ -#define bC(x) (((ia64_insn) ((x) & 0x1)) << 12) -#define bImm14(x) ((((ia64_insn) (((x) >> 0) & 0x7f)) << 13) | \ - (((ia64_insn) (((x) >> 7) & 0x3f)) << 27) | \ - (((ia64_insn) (((x) >> 13) & 0x01)) << 36)) -#define bR3a(x) (((ia64_insn) ((x) & 0x7f)) << 20) -#define bR3b(x) (((ia64_insn) ((x) & 0x3)) << 20) -#define bTa(x) (((ia64_insn) ((x) & 0x1)) << 33) -#define bTb(x) (((ia64_insn) ((x) & 0x1)) << 36) -#define bVe(x) (((ia64_insn) ((x) & 0x1)) << 33) -#define bX(x) (((ia64_insn) ((x) & 0x1)) << 33) -#define bX2(x) (((ia64_insn) ((x) & 0x3)) << 34) -#define bX2a(x) (((ia64_insn) ((x) & 0x3)) << 34) -#define bX2b(x) (((ia64_insn) ((x) & 0x3)) << 27) -#define bX4(x) (((ia64_insn) ((x) & 0xf)) << 29) -#define bZa(x) (((ia64_insn) ((x) & 0x1)) << 36) -#define bZb(x) (((ia64_insn) ((x) & 0x1)) << 33) - -/* instruction bit masks: */ -#define mC bC (-1) -#define mImm14 bImm14 (-1) -#define mR3a bR3a (-1) -#define mR3b bR3b (-1) -#define mTa bTa (-1) -#define mTb bTb (-1) -#define mVe bVe (-1) -#define mX bX (-1) -#define mX2 bX2 (-1) -#define mX2a bX2a (-1) -#define mX2b bX2b (-1) -#define mX4 bX4 (-1) -#define mZa bZa (-1) -#define mZb bZb (-1) - -#define OpR3b(a,b) (bOp (a) | bR3b (b)), (mOp | mR3b) -#define OpX2aVe(a,b,c) (bOp (a) | bX2a (b) | bVe (c)), \ - (mOp | mX2a | mVe) -#define OpX2aVeR3a(a,b,c,d) (bOp (a) | bX2a (b) | bVe (c) | bR3a (d)), \ - (mOp | mX2a | mVe | mR3a) -#define OpX2aVeImm14(a,b,c,d) (bOp (a) | bX2a (b) | bVe (c) | bImm14 (d)),= \ - (mOp | mX2a | mVe | mImm14) -#define OpX2aVeX4(a,b,c,d) (bOp (a) | bX2a (b) | bVe (c) | bX4 (d)), \ - (mOp | mX2a | mVe | mX4) -#define OpX2aVeX4X2b(a,b,c,d,e) \ - (bOp (a) | bX2a (b) | bVe (c) | bX4 (d) | bX2b (e)), \ - (mOp | mX2a | mVe | mX4 | mX2b) -#define OpX2TbTaC(a,b,c,d,e) \ - (bOp (a) | bX2 (b) | bTb (c) | bTa (d) | bC (e)), \ - (mOp | mX2 | mTb | mTa | mC) -#define OpX2TaC(a,b,c,d) (bOp (a) | bX2 (b) | bTa (c) | bC (d)), \ - (mOp | mX2 | mTa | mC) -#define OpX2aZaZbX4(a,b,c,d,e) \ - (bOp (a) | bX2a (b) | bZa (c) | bZb (d) | bX4 (e)), \ - (mOp | mX2a | mZa | mZb | mX4) -#define OpX2aZaZbX4X2b(a,b,c,d,e,f) \ - (bOp (a) | bX2a (b) | bZa (c) | bZb (d) | bX4 (e) | bX2b (f)), \ - (mOp | mX2a | mZa | mZb | mX4 | mX2b) - -/* Used to initialise unused fields in ia64_opcode struct, - in order to stop gcc from complaining. */ -#define EMPTY 0,0,NULL - -struct ia64_opcode ia64_opcodes_a[] =3D - { - /* A-type instruction encodings (sorted according to major opcode). */ - - {"add", A, OpX2aVeX4X2b (8, 0, 0, 0, 0), {R1, R2, R3}, EMPTY}, - {"add", A, OpX2aVeX4X2b (8, 0, 0, 0, 1), {R1, R2, R3, C1}, EMPTY}, - {"sub", A, OpX2aVeX4X2b (8, 0, 0, 1, 1), {R1, R2, R3}, EMPTY}, - {"sub", A, OpX2aVeX4X2b (8, 0, 0, 1, 0), {R1, R2, R3, C1}, EMPTY}, - {"addp4", A, OpX2aVeX4X2b (8, 0, 0, 2, 0), {R1, R2, R3}, EMPTY}, - {"and", A, OpX2aVeX4X2b (8, 0, 0, 3, 0), {R1, R2, R3}, EMPTY}, - {"andcm", A, OpX2aVeX4X2b (8, 0, 0, 3, 1), {R1, R2, R3}, EMPTY}, - {"or", A, OpX2aVeX4X2b (8, 0, 0, 3, 2), {R1, R2, R3}, EMPTY}, - {"xor", A, OpX2aVeX4X2b (8, 0, 0, 3, 3), {R1, R2, R3}, EMPTY}, - {"shladd", A, OpX2aVeX4 (8, 0, 0, 4), {R1, R2, CNT2a, R3}, EMPTY}, - {"shladdp4", A, OpX2aVeX4 (8, 0, 0, 6), {R1, R2, CNT2a, R3}, EMPTY}, - {"sub", A, OpX2aVeX4X2b (8, 0, 0, 9, 1), {R1, IMM8, R3}, EMPTY}, - {"and", A, OpX2aVeX4X2b (8, 0, 0, 0xb, 0), {R1, IMM8, R3}, EMPTY}, - {"andcm", A, OpX2aVeX4X2b (8, 0, 0, 0xb, 1), {R1, IMM8, R3}, EMPTY}, - {"or", A, OpX2aVeX4X2b (8, 0, 0, 0xb, 2), {R1, IMM8, R3}, EMPTY}, - {"xor", A, OpX2aVeX4X2b (8, 0, 0, 0xb, 3), {R1, IMM8, R3}, EMPTY}, - {"mov", A, OpX2aVeImm14 (8, 2, 0, 0), {R1, R3}, EMPTY}, - /* A mov immediate pseudo for adds was deleted. It failed for immedia= te - operands requiring relocs, e.g. @pltoff(a). */ - {"adds", A, OpX2aVe (8, 2, 0), {R1, IMM14, R3}, EMPTY}, - {"addp4", A, OpX2aVe (8, 3, 0), {R1, IMM14, R3}, EMPTY}, - {"padd1", A, OpX2aZaZbX4X2b (8, 1, 0, 0, 0, 0), {R1, R2, R3}, EMPTY}, - {"padd2", A, OpX2aZaZbX4X2b (8, 1, 0, 1, 0, 0), {R1, R2, R3}, EMPTY}, - {"padd4", A, OpX2aZaZbX4X2b (8, 1, 1, 0, 0, 0), {R1, R2, R3}, EMPTY}, - {"padd1.sss", A, OpX2aZaZbX4X2b (8, 1, 0, 0, 0, 1), {R1, R2, R3}, EMP= TY}, - {"padd2.sss", A, OpX2aZaZbX4X2b (8, 1, 0, 1, 0, 1), {R1, R2, R3}, EMP= TY}, - {"padd1.uuu", A, OpX2aZaZbX4X2b (8, 1, 0, 0, 0, 2), {R1, R2, R3}, EMP= TY}, - {"padd2.uuu", A, OpX2aZaZbX4X2b (8, 1, 0, 1, 0, 2), {R1, R2, R3}, EMP= TY}, - {"padd1.uus", A, OpX2aZaZbX4X2b (8, 1, 0, 0, 0, 3), {R1, R2, R3}, EMP= TY}, - {"padd2.uus", A, OpX2aZaZbX4X2b (8, 1, 0, 1, 0, 3), {R1, R2, R3}, EMP= TY}, - {"psub1", A, OpX2aZaZbX4X2b (8, 1, 0, 0, 1, 0), {R1, R2, R3}, EMPTY}, - {"psub2", A, OpX2aZaZbX4X2b (8, 1, 0, 1, 1, 0), {R1, R2, R3}, EMPTY}, - {"psub4", A, OpX2aZaZbX4X2b (8, 1, 1, 0, 1, 0), {R1, R2, R3}, EMPTY}, - {"psub1.sss", A, OpX2aZaZbX4X2b (8, 1, 0, 0, 1, 1), {R1, R2, R3}, EMP= TY}, - {"psub2.sss", A, OpX2aZaZbX4X2b (8, 1, 0, 1, 1, 1), {R1, R2, R3}, EMP= TY}, - {"psub1.uuu", A, OpX2aZaZbX4X2b (8, 1, 0, 0, 1, 2), {R1, R2, R3}, EMP= TY}, - {"psub2.uuu", A, OpX2aZaZbX4X2b (8, 1, 0, 1, 1, 2), {R1, R2, R3}, EMP= TY}, - {"psub1.uus", A, OpX2aZaZbX4X2b (8, 1, 0, 0, 1, 3), {R1, R2, R3}, EMP= TY}, - {"psub2.uus", A, OpX2aZaZbX4X2b (8, 1, 0, 1, 1, 3), {R1, R2, R3}, EMP= TY}, - {"pavg1", A, OpX2aZaZbX4X2b (8, 1, 0, 0, 2, 2), {R1, R2, R3}, EMPTY}, - {"pavg2", A, OpX2aZaZbX4X2b (8, 1, 0, 1, 2, 2), {R1, R2, R3}, EMPTY}, - {"pavg1.raz", A, OpX2aZaZbX4X2b (8, 1, 0, 0, 2, 3), {R1, R2, R3}, EMP= TY}, - {"pavg2.raz", A, OpX2aZaZbX4X2b (8, 1, 0, 1, 2, 3), {R1, R2, R3}, EMP= TY}, - {"pavgsub1", A, OpX2aZaZbX4X2b (8, 1, 0, 0, 3, 2), {R1, R2, R3}, EMPT= Y}, - {"pavgsub2", A, OpX2aZaZbX4X2b (8, 1, 0, 1, 3, 2), {R1, R2, R3}, EMPT= Y}, - {"pcmp1.eq", A, OpX2aZaZbX4X2b (8, 1, 0, 0, 9, 0), {R1, R2, R3}, EMPT= Y}, - {"pcmp2.eq", A, OpX2aZaZbX4X2b (8, 1, 0, 1, 9, 0), {R1, R2, R3}, EMPT= Y}, - {"pcmp4.eq", A, OpX2aZaZbX4X2b (8, 1, 1, 0, 9, 0), {R1, R2, R3}, EMPT= Y}, - {"pcmp1.gt", A, OpX2aZaZbX4X2b (8, 1, 0, 0, 9, 1), {R1, R2, R3}, EMPT= Y}, - {"pcmp2.gt", A, OpX2aZaZbX4X2b (8, 1, 0, 1, 9, 1), {R1, R2, R3}, EMPT= Y}, - {"pcmp4.gt", A, OpX2aZaZbX4X2b (8, 1, 1, 0, 9, 1), {R1, R2, R3}, EMPT= Y}, - {"pshladd2", A, OpX2aZaZbX4 (8, 1, 0, 1, 4), {R1, R2, CNT2b, R3}, EMP= TY}, - {"pshradd2", A, OpX2aZaZbX4 (8, 1, 0, 1, 6), {R1, R2, CNT2b, R3}, EMP= TY}, - - {"mov", A, OpR3b (9, 0), {R1, IMM22}, PSEUDO, 0, NULL}, - {"addl", A, Op (9), {R1, IMM22, R3_2}, EMPTY}, - - {"cmp.lt", A2, OpX2TbTaC (0xc, 0, 0, 0, 0), {P1, P2, R2, R3}, EMPTY}, - {"cmp.le", A2, OpX2TbTaC (0xc, 0, 0, 0, 0), {P2, P1, R3, R2}, EMPTY}, - {"cmp.gt", A2, OpX2TbTaC (0xc, 0, 0, 0, 0), {P1, P2, R3, R2}, EMPTY}, - {"cmp.ge", A2, OpX2TbTaC (0xc, 0, 0, 0, 0), {P2, P1, R2, R3}, EMPTY}, - {"cmp.lt.unc", A2, OpX2TbTaC (0xc, 0, 0, 0, 1), {P1, P2, R2, R3}, EMP= TY}, - {"cmp.le.unc", A2, OpX2TbTaC (0xc, 0, 0, 0, 1), {P2, P1, R3, R2}, EMP= TY}, - {"cmp.gt.unc", A2, OpX2TbTaC (0xc, 0, 0, 0, 1), {P1, P2, R3, R2}, EMP= TY}, - {"cmp.ge.unc", A2, OpX2TbTaC (0xc, 0, 0, 0, 1), {P2, P1, R2, R3}, EMP= TY}, - {"cmp.eq.and", A2, OpX2TbTaC (0xc, 0, 0, 1, 0), {P1, P2, R2, R3}, EMP= TY}, - {"cmp.ne.andcm", A2, OpX2TbTaC (0xc, 0, 0, 1, 0), {P1, P2, R2, R3}, P= SEUDO, 0, NULL}, - {"cmp.ne.and", A2, OpX2TbTaC (0xc, 0, 0, 1, 1), {P1, P2, R2, R3}, EMP= TY}, - {"cmp.eq.andcm", A2, OpX2TbTaC (0xc, 0, 0, 1, 1), {P1, P2, R2, R3}, P= SEUDO, 0, NULL}, - {"cmp4.lt", A2, OpX2TbTaC (0xc, 1, 0, 0, 0), {P1, P2, R2, R3}, EMPTY= }, - {"cmp4.le", A2, OpX2TbTaC (0xc, 1, 0, 0, 0), {P2, P1, R3, R2}, EMPTY= }, - {"cmp4.gt", A2, OpX2TbTaC (0xc, 1, 0, 0, 0), {P1, P2, R3, R2}, EMPTY= }, - {"cmp4.ge", A2, OpX2TbTaC (0xc, 1, 0, 0, 0), {P2, P1, R2, R3}, EMPTY= }, - {"cmp4.lt.unc", A2, OpX2TbTaC (0xc, 1, 0, 0, 1), {P1, P2, R2, R3}, EM= PTY}, - {"cmp4.le.unc", A2, OpX2TbTaC (0xc, 1, 0, 0, 1), {P2, P1, R3, R2}, EM= PTY}, - {"cmp4.gt.unc", A2, OpX2TbTaC (0xc, 1, 0, 0, 1), {P1, P2, R3, R2}, EM= PTY}, - {"cmp4.ge.unc", A2, OpX2TbTaC (0xc, 1, 0, 0, 1), {P2, P1, R2, R3}, EM= PTY}, - {"cmp4.eq.and", A2, OpX2TbTaC (0xc, 1, 0, 1, 0), {P1, P2, R2, R3}, EM= PTY}, - {"cmp4.ne.andcm", A2, OpX2TbTaC (0xc, 1, 0, 1, 0), {P1, P2, R2, R3}, = PSEUDO, 0, NULL}, - {"cmp4.ne.and", A2, OpX2TbTaC (0xc, 1, 0, 1, 1), {P1, P2, R2, R3}, EM= PTY}, - {"cmp4.eq.andcm", A2, OpX2TbTaC (0xc, 1, 0, 1, 1), {P1, P2, R2, R3}, = PSEUDO, 0, NULL}, - {"cmp.gt.and", A2, OpX2TbTaC (0xc, 0, 1, 0, 0), {P1, P2, GR0, R3}, EM= PTY}, - {"cmp.lt.and", A2, OpX2TbTaC (0xc, 0, 1, 0, 0), {P1, P2, R3, GR0}, PS= EUDO, 0, NULL}, - {"cmp.le.andcm", A2, OpX2TbTaC (0xc, 0, 1, 0, 0), {P1, P2, GR0, R3}, = PSEUDO, 0, NULL}, - {"cmp.ge.andcm", A2, OpX2TbTaC (0xc, 0, 1, 0, 0), {P1, P2, R3, GR0}, = PSEUDO, 0, NULL}, - {"cmp.le.and", A2, OpX2TbTaC (0xc, 0, 1, 0, 1), {P1, P2, GR0, R3}, EM= PTY}, - {"cmp.ge.and", A2, OpX2TbTaC (0xc, 0, 1, 0, 1), {P1, P2, R3, GR0}, PS= EUDO, 0, NULL}, - {"cmp.gt.andcm", A2, OpX2TbTaC (0xc, 0, 1, 0, 1), {P1, P2, GR0, R3}, = PSEUDO, 0, NULL}, - {"cmp.lt.andcm", A2, OpX2TbTaC (0xc, 0, 1, 0, 1), {P1, P2, R3, GR0}, = PSEUDO, 0, NULL}, - {"cmp.ge.and", A2, OpX2TbTaC (0xc, 0, 1, 1, 0), {P1, P2, GR0, R3}, EM= PTY}, - {"cmp.le.and", A2, OpX2TbTaC (0xc, 0, 1, 1, 0), {P1, P2, R3, GR0}, PS= EUDO, 0, NULL}, - {"cmp.lt.andcm", A2, OpX2TbTaC (0xc, 0, 1, 1, 0), {P1, P2, GR0, R3}, = PSEUDO, 0, NULL}, - {"cmp.gt.andcm", A2, OpX2TbTaC (0xc, 0, 1, 1, 0), {P1, P2, R3, GR0}, = PSEUDO, 0, NULL}, - {"cmp.lt.and", A2, OpX2TbTaC (0xc, 0, 1, 1, 1), {P1, P2, GR0, R3}, EM= PTY}, - {"cmp.gt.and", A2, OpX2TbTaC (0xc, 0, 1, 1, 1), {P1, P2, R3, GR0}, PS= EUDO, 0, NULL}, - {"cmp.ge.andcm", A2, OpX2TbTaC (0xc, 0, 1, 1, 1), {P1, P2, GR0, R3}, = PSEUDO, 0, NULL}, - {"cmp.le.andcm", A2, OpX2TbTaC (0xc, 0, 1, 1, 1), {P1, P2, R3, GR0}, = PSEUDO, 0, NULL}, - {"cmp4.gt.and", A2, OpX2TbTaC (0xc, 1, 1, 0, 0), {P1, P2, GR0, R3}, E= MPTY}, - {"cmp4.lt.and", A2, OpX2TbTaC (0xc, 1, 1, 0, 0), {P1, P2, R3, GR0}, P= SEUDO, 0, NULL}, - {"cmp4.le.andcm", A2, OpX2TbTaC (0xc, 1, 1, 0, 0), {P1, P2, GR0, R3},= PSEUDO, 0, NULL}, - {"cmp4.ge.andcm", A2, OpX2TbTaC (0xc, 1, 1, 0, 0), {P1, P2, R3, GR0},= PSEUDO, 0, NULL}, - {"cmp4.le.and", A2, OpX2TbTaC (0xc, 1, 1, 0, 1), {P1, P2, GR0, R3}, E= MPTY}, - {"cmp4.ge.and", A2, OpX2TbTaC (0xc, 1, 1, 0, 1), {P1, P2, R3, GR0}, P= SEUDO, 0, NULL}, - {"cmp4.gt.andcm", A2, OpX2TbTaC (0xc, 1, 1, 0, 1), {P1, P2, GR0, R3},= PSEUDO, 0, NULL}, - {"cmp4.lt.andcm", A2, OpX2TbTaC (0xc, 1, 1, 0, 1), {P1, P2, R3, GR0},= PSEUDO, 0, NULL}, - {"cmp4.ge.and", A2, OpX2TbTaC (0xc, 1, 1, 1, 0), {P1, P2, GR0, R3}, E= MPTY}, - {"cmp4.le.and", A2, OpX2TbTaC (0xc, 1, 1, 1, 0), {P1, P2, R3, GR0}, P= SEUDO, 0, NULL}, - {"cmp4.lt.andcm", A2, OpX2TbTaC (0xc, 1, 1, 1, 0), {P1, P2, GR0, R3},= PSEUDO, 0, NULL}, - {"cmp4.gt.andcm", A2, OpX2TbTaC (0xc, 1, 1, 1, 0), {P1, P2, R3, GR0},= PSEUDO, 0, NULL}, - {"cmp4.lt.and", A2, OpX2TbTaC (0xc, 1, 1, 1, 1), {P1, P2, GR0, R3}, E= MPTY}, - {"cmp4.gt.and", A2, OpX2TbTaC (0xc, 1, 1, 1, 1), {P1, P2, R3, GR0}, P= SEUDO, 0, NULL}, - {"cmp4.ge.andcm", A2, OpX2TbTaC (0xc, 1, 1, 1, 1), {P1, P2, GR0, R3},= PSEUDO, 0, NULL}, - {"cmp4.le.andcm", A2, OpX2TbTaC (0xc, 1, 1, 1, 1), {P1, P2, R3, GR0},= PSEUDO, 0, NULL}, - {"cmp.lt", A2, OpX2TaC (0xc, 2, 0, 0), {P1, P2, IMM8, R3}, EMPTY}, - {"cmp.le", A2, OpX2TaC (0xc, 2, 0, 0), {P1, P2, IMM8M1, R3}, EMPTY= }, - {"cmp.gt", A2, OpX2TaC (0xc, 2, 0, 0), {P2, P1, IMM8M1, R3}, EMPTY= }, - {"cmp.ge", A2, OpX2TaC (0xc, 2, 0, 0), {P2, P1, IMM8, R3}, EMPTY}, - {"cmp.lt.unc", A2, OpX2TaC (0xc, 2, 0, 1), {P1, P2, IMM8, R3}, EMPT= Y}, - {"cmp.le.unc", A2, OpX2TaC (0xc, 2, 0, 1), {P1, P2, IMM8M1, R3}, EM= PTY}, - {"cmp.gt.unc", A2, OpX2TaC (0xc, 2, 0, 1), {P2, P1, IMM8M1, R3}, EM= PTY}, - {"cmp.ge.unc", A2, OpX2TaC (0xc, 2, 0, 1), {P2, P1, IMM8, R3}, EMPT= Y}, - {"cmp.eq.and", A2, OpX2TaC (0xc, 2, 1, 0), {P1, P2, IMM8, R3}, EMPT= Y}, - {"cmp.ne.andcm", A2, OpX2TaC (0xc, 2, 1, 0), {P1, P2, IMM8, R3}, PS= EUDO, 0, NULL}, - {"cmp.ne.and", A2, OpX2TaC (0xc, 2, 1, 1), {P1, P2, IMM8, R3}, EMPT= Y}, - {"cmp.eq.andcm", A2, OpX2TaC (0xc, 2, 1, 1), {P1, P2, IMM8, R3}, PS= EUDO, 0, NULL}, - {"cmp4.lt", A2, OpX2TaC (0xc, 3, 0, 0), {P1, P2, IMM8, R3}, EMPTY}, - {"cmp4.le", A2, OpX2TaC (0xc, 3, 0, 0), {P1, P2, IMM8M1, R3}, EMPT= Y}, - {"cmp4.gt", A2, OpX2TaC (0xc, 3, 0, 0), {P2, P1, IMM8M1, R3}, EMPT= Y}, - {"cmp4.ge", A2, OpX2TaC (0xc, 3, 0, 0), {P2, P1, IMM8, R3}, EMPTY}, - {"cmp4.lt.unc", A2, OpX2TaC (0xc, 3, 0, 1), {P1, P2, IMM8, R3}, EMP= TY}, - {"cmp4.le.unc", A2, OpX2TaC (0xc, 3, 0, 1), {P1, P2, IMM8M1, R3}, E= MPTY}, - {"cmp4.gt.unc", A2, OpX2TaC (0xc, 3, 0, 1), {P2, P1, IMM8M1, R3}, E= MPTY}, - {"cmp4.ge.unc", A2, OpX2TaC (0xc, 3, 0, 1), {P2, P1, IMM8, R3}, EMP= TY}, - {"cmp4.eq.and", A2, OpX2TaC (0xc, 3, 1, 0), {P1, P2, IMM8, R3}, EMP= TY}, - {"cmp4.ne.andcm", A2, OpX2TaC (0xc, 3, 1, 0), {P1, P2, IMM8, R3}, P= SEUDO, 0, NULL}, - {"cmp4.ne.and", A2, OpX2TaC (0xc, 3, 1, 1), {P1, P2, IMM8, R3}, EMP= TY}, - {"cmp4.eq.andcm", A2, OpX2TaC (0xc, 3, 1, 1), {P1, P2, IMM8, R3}, P= SEUDO, 0, NULL}, - {"cmp.ltu", A2, OpX2TbTaC (0xd, 0, 0, 0, 0), {P1, P2, R2, R3}, EMPTY= }, - {"cmp.leu", A2, OpX2TbTaC (0xd, 0, 0, 0, 0), {P2, P1, R3, R2}, EMPTY= }, - {"cmp.gtu", A2, OpX2TbTaC (0xd, 0, 0, 0, 0), {P1, P2, R3, R2}, EMPTY= }, - {"cmp.geu", A2, OpX2TbTaC (0xd, 0, 0, 0, 0), {P2, P1, R2, R3}, EMPTY= }, - {"cmp.ltu.unc", A2, OpX2TbTaC (0xd, 0, 0, 0, 1), {P1, P2, R2, R3}, EM= PTY}, - {"cmp.leu.unc", A2, OpX2TbTaC (0xd, 0, 0, 0, 1), {P2, P1, R3, R2}, EM= PTY}, - {"cmp.gtu.unc", A2, OpX2TbTaC (0xd, 0, 0, 0, 1), {P1, P2, R3, R2}, EM= PTY}, - {"cmp.geu.unc", A2, OpX2TbTaC (0xd, 0, 0, 0, 1), {P2, P1, R2, R3}, EM= PTY}, - {"cmp.eq.or", A2, OpX2TbTaC (0xd, 0, 0, 1, 0), {P1, P2, R2, R3}, EMPT= Y}, - {"cmp.ne.orcm", A2, OpX2TbTaC (0xd, 0, 0, 1, 0), {P1, P2, R2, R3}, PS= EUDO, 0, NULL}, - {"cmp.ne.or", A2, OpX2TbTaC (0xd, 0, 0, 1, 1), {P1, P2, R2, R3}, EMPT= Y}, - {"cmp.eq.orcm", A2, OpX2TbTaC (0xd, 0, 0, 1, 1), {P1, P2, R2, R3}, PS= EUDO, 0, NULL}, - {"cmp4.ltu", A2, OpX2TbTaC (0xd, 1, 0, 0, 0), {P1, P2, R2, R3}, EMPTY= }, - {"cmp4.leu", A2, OpX2TbTaC (0xd, 1, 0, 0, 0), {P2, P1, R3, R2}, EMPTY= }, - {"cmp4.gtu", A2, OpX2TbTaC (0xd, 1, 0, 0, 0), {P1, P2, R3, R2}, EMPTY= }, - {"cmp4.geu", A2, OpX2TbTaC (0xd, 1, 0, 0, 0), {P2, P1, R2, R3}, EMPTY= }, - {"cmp4.ltu.unc", A2, OpX2TbTaC (0xd, 1, 0, 0, 1), {P1, P2, R2, R3}, E= MPTY}, - {"cmp4.leu.unc", A2, OpX2TbTaC (0xd, 1, 0, 0, 1), {P2, P1, R3, R2}, E= MPTY}, - {"cmp4.gtu.unc", A2, OpX2TbTaC (0xd, 1, 0, 0, 1), {P1, P2, R3, R2}, E= MPTY}, - {"cmp4.geu.unc", A2, OpX2TbTaC (0xd, 1, 0, 0, 1), {P2, P1, R2, R3}, E= MPTY}, - {"cmp4.eq.or", A2, OpX2TbTaC (0xd, 1, 0, 1, 0), {P1, P2, R2, R3}, EMP= TY}, - {"cmp4.ne.orcm", A2, OpX2TbTaC (0xd, 1, 0, 1, 0), {P1, P2, R2, R3}, P= SEUDO, 0, NULL}, - {"cmp4.ne.or", A2, OpX2TbTaC (0xd, 1, 0, 1, 1), {P1, P2, R2, R3}, EMP= TY}, - {"cmp4.eq.orcm", A2, OpX2TbTaC (0xd, 1, 0, 1, 1), {P1, P2, R2, R3}, P= SEUDO, 0, NULL}, - {"cmp.gt.or", A2, OpX2TbTaC (0xd, 0, 1, 0, 0), {P1, P2, GR0, R3}, EMP= TY}, - {"cmp.lt.or", A2, OpX2TbTaC (0xd, 0, 1, 0, 0), {P1, P2, R3, GR0}, PSE= UDO, 0, NULL}, - {"cmp.le.orcm", A2, OpX2TbTaC (0xd, 0, 1, 0, 0), {P1, P2, GR0, R3}, P= SEUDO, 0, NULL}, - {"cmp.ge.orcm", A2, OpX2TbTaC (0xd, 0, 1, 0, 0), {P1, P2, R3, GR0}, P= SEUDO, 0, NULL}, - {"cmp.le.or", A2, OpX2TbTaC (0xd, 0, 1, 0, 1), {P1, P2, GR0, R3}, EMP= TY}, - {"cmp.ge.or", A2, OpX2TbTaC (0xd, 0, 1, 0, 1), {P1, P2, R3, GR0}, PSE= UDO, 0, NULL}, - {"cmp.gt.orcm", A2, OpX2TbTaC (0xd, 0, 1, 0, 1), {P1, P2, GR0, R3}, P= SEUDO, 0, NULL}, - {"cmp.lt.orcm", A2, OpX2TbTaC (0xd, 0, 1, 0, 1), {P1, P2, R3, GR0}, P= SEUDO, 0, NULL}, - {"cmp.ge.or", A2, OpX2TbTaC (0xd, 0, 1, 1, 0), {P1, P2, GR0, R3}, EMP= TY}, - {"cmp.le.or", A2, OpX2TbTaC (0xd, 0, 1, 1, 0), {P1, P2, R3, GR0}, PSE= UDO, 0, NULL}, - {"cmp.lt.orcm", A2, OpX2TbTaC (0xd, 0, 1, 1, 0), {P1, P2, GR0, R3}, P= SEUDO, 0, NULL}, - {"cmp.gt.orcm", A2, OpX2TbTaC (0xd, 0, 1, 1, 0), {P1, P2, R3, GR0}, P= SEUDO, 0, NULL}, - {"cmp.lt.or", A2, OpX2TbTaC (0xd, 0, 1, 1, 1), {P1, P2, GR0, R3}, EMP= TY}, - {"cmp.gt.or", A2, OpX2TbTaC (0xd, 0, 1, 1, 1), {P1, P2, R3, GR0}, PSE= UDO, 0, NULL}, - {"cmp.ge.orcm", A2, OpX2TbTaC (0xd, 0, 1, 1, 1), {P1, P2, GR0, R3}, P= SEUDO, 0, NULL}, - {"cmp.le.orcm", A2, OpX2TbTaC (0xd, 0, 1, 1, 1), {P1, P2, R3, GR0}, P= SEUDO, 0, NULL}, - {"cmp4.gt.or", A2, OpX2TbTaC (0xd, 1, 1, 0, 0), {P1, P2, GR0, R3}, EM= PTY}, - {"cmp4.lt.or", A2, OpX2TbTaC (0xd, 1, 1, 0, 0), {P1, P2, R3, GR0}, PS= EUDO, 0, NULL}, - {"cmp4.le.orcm", A2, OpX2TbTaC (0xd, 1, 1, 0, 0), {P1, P2, GR0, R3}, = PSEUDO, 0, NULL}, - {"cmp4.ge.orcm", A2, OpX2TbTaC (0xd, 1, 1, 0, 0), {P1, P2, R3, GR0}, = PSEUDO, 0, NULL}, - {"cmp4.le.or", A2, OpX2TbTaC (0xd, 1, 1, 0, 1), {P1, P2, GR0, R3}, EM= PTY}, - {"cmp4.ge.or", A2, OpX2TbTaC (0xd, 1, 1, 0, 1), {P1, P2, R3, GR0}, PS= EUDO, 0, NULL}, - {"cmp4.gt.orcm", A2, OpX2TbTaC (0xd, 1, 1, 0, 1), {P1, P2, GR0, R3}, = PSEUDO, 0, NULL}, - {"cmp4.lt.orcm", A2, OpX2TbTaC (0xd, 1, 1, 0, 1), {P1, P2, R3, GR0}, = PSEUDO, 0, NULL}, - {"cmp4.ge.or", A2, OpX2TbTaC (0xd, 1, 1, 1, 0), {P1, P2, GR0, R3}, EM= PTY}, - {"cmp4.le.or", A2, OpX2TbTaC (0xd, 1, 1, 1, 0), {P1, P2, R3, GR0}, PS= EUDO, 0, NULL}, - {"cmp4.lt.orcm", A2, OpX2TbTaC (0xd, 1, 1, 1, 0), {P1, P2, GR0, R3}, = PSEUDO, 0, NULL}, - {"cmp4.gt.orcm", A2, OpX2TbTaC (0xd, 1, 1, 1, 0), {P1, P2, R3, GR0}, = PSEUDO, 0, NULL}, - {"cmp4.lt.or", A2, OpX2TbTaC (0xd, 1, 1, 1, 1), {P1, P2, GR0, R3}, EM= PTY}, - {"cmp4.gt.or", A2, OpX2TbTaC (0xd, 1, 1, 1, 1), {P1, P2, R3, GR0}, PS= EUDO, 0, NULL}, - {"cmp4.ge.orcm", A2, OpX2TbTaC (0xd, 1, 1, 1, 1), {P1, P2, GR0, R3}, = PSEUDO, 0, NULL}, - {"cmp4.le.orcm", A2, OpX2TbTaC (0xd, 1, 1, 1, 1), {P1, P2, R3, GR0}, = PSEUDO, 0, NULL}, - {"cmp.ltu", A2, OpX2TaC (0xd, 2, 0, 0), {P1, P2, IMM8, R3}, EMPTY}, - {"cmp.leu", A2, OpX2TaC (0xd, 2, 0, 0), {P1, P2, IMM8M1U8, R3}, EM= PTY}, - {"cmp.gtu", A2, OpX2TaC (0xd, 2, 0, 0), {P2, P1, IMM8M1U8, R3}, EM= PTY}, - {"cmp.geu", A2, OpX2TaC (0xd, 2, 0, 0), {P2, P1, IMM8, R3}, EMPTY}, - {"cmp.ltu.unc", A2, OpX2TaC (0xd, 2, 0, 1), {P1, P2, IMM8, R3}, EMP= TY}, - {"cmp.leu.unc", A2, OpX2TaC (0xd, 2, 0, 1), {P1, P2, IMM8M1U8, R3},= EMPTY}, - {"cmp.gtu.unc", A2, OpX2TaC (0xd, 2, 0, 1), {P2, P1, IMM8M1U8, R3},= EMPTY}, - {"cmp.geu.unc", A2, OpX2TaC (0xd, 2, 0, 1), {P2, P1, IMM8, R3}, EMP= TY}, - {"cmp.eq.or", A2, OpX2TaC (0xd, 2, 1, 0), {P1, P2, IMM8, R3}, EMPTY= }, - {"cmp.ne.orcm", A2, OpX2TaC (0xd, 2, 1, 0), {P1, P2, IMM8, R3}, PSE= UDO, 0, NULL}, - {"cmp.ne.or", A2, OpX2TaC (0xd, 2, 1, 1), {P1, P2, IMM8, R3}, EMPTY= }, - {"cmp.eq.orcm", A2, OpX2TaC (0xd, 2, 1, 1), {P1, P2, IMM8, R3}, PSE= UDO, 0, NULL}, - {"cmp4.ltu", A2, OpX2TaC (0xd, 3, 0, 0), {P1, P2, IMM8U4, R3}, EMPT= Y}, - {"cmp4.leu", A2, OpX2TaC (0xd, 3, 0, 0), {P1, P2, IMM8M1U4, R3}, EM= PTY}, - {"cmp4.gtu", A2, OpX2TaC (0xd, 3, 0, 0), {P2, P1, IMM8M1U4, R3}, EM= PTY}, - {"cmp4.geu", A2, OpX2TaC (0xd, 3, 0, 0), {P2, P1, IMM8U4, R3}, EMPT= Y}, - {"cmp4.ltu.unc", A2, OpX2TaC (0xd, 3, 0, 1), {P1, P2, IMM8U4, R3}, = EMPTY}, - {"cmp4.leu.unc", A2, OpX2TaC (0xd, 3, 0, 1), {P1, P2, IMM8M1U4, R3}= , EMPTY}, - {"cmp4.gtu.unc", A2, OpX2TaC (0xd, 3, 0, 1), {P2, P1, IMM8M1U4, R3}= , EMPTY}, - {"cmp4.geu.unc", A2, OpX2TaC (0xd, 3, 0, 1), {P2, P1, IMM8U4, R3}, = EMPTY}, - {"cmp4.eq.or", A2, OpX2TaC (0xd, 3, 1, 0), {P1, P2, IMM8, R3}, EMPT= Y}, - {"cmp4.ne.orcm", A2, OpX2TaC (0xd, 3, 1, 0), {P1, P2, IMM8, R3}, PS= EUDO, 0, NULL}, - {"cmp4.ne.or", A2, OpX2TaC (0xd, 3, 1, 1), {P1, P2, IMM8, R3}, EMPT= Y}, - {"cmp4.eq.orcm", A2, OpX2TaC (0xd, 3, 1, 1), {P1, P2, IMM8, R3}, PS= EUDO, 0, NULL}, - {"cmp.eq", A2, OpX2TbTaC (0xe, 0, 0, 0, 0), {P1, P2, R2, R3}, EMPTY}, - {"cmp.ne", A2, OpX2TbTaC (0xe, 0, 0, 0, 0), {P2, P1, R2, R3}, EMPTY}, - {"cmp.eq.unc", A2, OpX2TbTaC (0xe, 0, 0, 0, 1), {P1, P2, R2, R3}, EMP= TY}, - {"cmp.ne.unc", A2, OpX2TbTaC (0xe, 0, 0, 0, 1), {P2, P1, R2, R3}, EMP= TY}, - {"cmp.eq.or.andcm", A2, OpX2TbTaC (0xe, 0, 0, 1, 0), {P1, P2, R2, R3}= , EMPTY}, - {"cmp.ne.and.orcm", A2, OpX2TbTaC (0xe, 0, 0, 1, 0), {P2, P1, R2, R3}= , PSEUDO, 0, NULL}, - {"cmp.ne.or.andcm", A2, OpX2TbTaC (0xe, 0, 0, 1, 1), {P1, P2, R2, R3}= , EMPTY}, - {"cmp.eq.and.orcm", A2, OpX2TbTaC (0xe, 0, 0, 1, 1), {P2, P1, R2, R3}= , PSEUDO, 0, NULL}, - {"cmp4.eq", A2, OpX2TbTaC (0xe, 1, 0, 0, 0), {P1, P2, R2, R3}, EMPTY= }, - {"cmp4.ne", A2, OpX2TbTaC (0xe, 1, 0, 0, 0), {P2, P1, R2, R3}, EMPTY= }, - {"cmp4.eq.unc", A2, OpX2TbTaC (0xe, 1, 0, 0, 1), {P1, P2, R2, R3}, EM= PTY}, - {"cmp4.ne.unc", A2, OpX2TbTaC (0xe, 1, 0, 0, 1), {P2, P1, R2, R3}, EM= PTY}, - {"cmp4.eq.or.andcm", A2, OpX2TbTaC (0xe, 1, 0, 1, 0), {P1, P2, R2, R3}= , EMPTY}, - {"cmp4.ne.and.orcm", A2, OpX2TbTaC (0xe, 1, 0, 1, 0), {P2, P1, R2, R3}= , PSEUDO, 0, NULL}, - {"cmp4.ne.or.andcm", A2, OpX2TbTaC (0xe, 1, 0, 1, 1), {P1, P2, R2, R3}= , EMPTY}, - {"cmp4.eq.and.orcm", A2, OpX2TbTaC (0xe, 1, 0, 1, 1), {P2, P1, R2, R3}= , PSEUDO, 0, NULL}, - {"cmp.gt.or.andcm", A2, OpX2TbTaC (0xe, 0, 1, 0, 0), {P1, P2, GR0, R3= }, EMPTY}, - {"cmp.lt.or.andcm", A2, OpX2TbTaC (0xe, 0, 1, 0, 0), {P1, P2, R3, GR0= }, PSEUDO, 0, NULL}, - {"cmp.le.and.orcm", A2, OpX2TbTaC (0xe, 0, 1, 0, 0), {P2, P1, GR0, R3= }, PSEUDO, 0, NULL}, - {"cmp.ge.and.orcm", A2, OpX2TbTaC (0xe, 0, 1, 0, 0), {P2, P1, R3, GR0= }, PSEUDO, 0, NULL}, - {"cmp.le.or.andcm", A2, OpX2TbTaC (0xe, 0, 1, 0, 1), {P1, P2, GR0, R3= }, EMPTY}, - {"cmp.ge.or.andcm", A2, OpX2TbTaC (0xe, 0, 1, 0, 1), {P1, P2, R3, GR0= }, PSEUDO, 0, NULL}, - {"cmp.gt.and.orcm", A2, OpX2TbTaC (0xe, 0, 1, 0, 1), {P2, P1, GR0, R3= }, PSEUDO, 0, NULL}, - {"cmp.lt.and.orcm", A2, OpX2TbTaC (0xe, 0, 1, 0, 1), {P2, P1, R3, GR0= }, PSEUDO, 0, NULL}, - {"cmp.ge.or.andcm", A2, OpX2TbTaC (0xe, 0, 1, 1, 0), {P1, P2, GR0, R3= }, EMPTY}, - {"cmp.le.or.andcm", A2, OpX2TbTaC (0xe, 0, 1, 1, 0), {P1, P2, R3, GR0= }, PSEUDO, 0, NULL}, - {"cmp.lt.and.orcm", A2, OpX2TbTaC (0xe, 0, 1, 1, 0), {P2, P1, GR0, R3= }, PSEUDO, 0, NULL}, - {"cmp.gt.and.orcm", A2, OpX2TbTaC (0xe, 0, 1, 1, 0), {P2, P1, R3, GR0= }, PSEUDO, 0, NULL}, - {"cmp.lt.or.andcm", A2, OpX2TbTaC (0xe, 0, 1, 1, 1), {P1, P2, GR0, R3= }, EMPTY}, - {"cmp.gt.or.andcm", A2, OpX2TbTaC (0xe, 0, 1, 1, 1), {P1, P2, R3, GR0= }, PSEUDO, 0, NULL}, - {"cmp.ge.and.orcm", A2, OpX2TbTaC (0xe, 0, 1, 1, 1), {P2, P1, GR0, R3= }, PSEUDO, 0, NULL}, - {"cmp.le.and.orcm", A2, OpX2TbTaC (0xe, 0, 1, 1, 1), {P2, P1, R3, GR0= }, PSEUDO, 0, NULL}, - {"cmp4.gt.or.andcm", A2, OpX2TbTaC (0xe, 1, 1, 0, 0), {P1, P2, GR0, R3= }, EMPTY}, - {"cmp4.lt.or.andcm", A2, OpX2TbTaC (0xe, 1, 1, 0, 0), {P1, P2, R3, GR0= }, PSEUDO, 0, NULL}, - {"cmp4.le.and.orcm", A2, OpX2TbTaC (0xe, 1, 1, 0, 0), {P2, P1, GR0, R3= }, PSEUDO, 0, NULL}, - {"cmp4.ge.and.orcm", A2, OpX2TbTaC (0xe, 1, 1, 0, 0), {P2, P1, R3, GR0= }, PSEUDO, 0, NULL}, - {"cmp4.le.or.andcm", A2, OpX2TbTaC (0xe, 1, 1, 0, 1), {P1, P2, GR0, R3= }, EMPTY}, - {"cmp4.ge.or.andcm", A2, OpX2TbTaC (0xe, 1, 1, 0, 1), {P1, P2, R3, GR0= }, PSEUDO, 0, NULL}, - {"cmp4.gt.and.orcm", A2, OpX2TbTaC (0xe, 1, 1, 0, 1), {P2, P1, GR0, R3= }, PSEUDO, 0, NULL}, - {"cmp4.lt.and.orcm", A2, OpX2TbTaC (0xe, 1, 1, 0, 1), {P2, P1, R3, GR0= }, PSEUDO, 0, NULL}, - {"cmp4.ge.or.andcm", A2, OpX2TbTaC (0xe, 1, 1, 1, 0), {P1, P2, GR0, R3= }, EMPTY}, - {"cmp4.le.or.andcm", A2, OpX2TbTaC (0xe, 1, 1, 1, 0), {P1, P2, R3, GR0= }, PSEUDO, 0, NULL}, - {"cmp4.lt.and.orcm", A2, OpX2TbTaC (0xe, 1, 1, 1, 0), {P2, P1, GR0, R3= }, PSEUDO, 0, NULL}, - {"cmp4.gt.and.orcm", A2, OpX2TbTaC (0xe, 1, 1, 1, 0), {P2, P1, R3, GR0= }, PSEUDO, 0, NULL}, - {"cmp4.lt.or.andcm", A2, OpX2TbTaC (0xe, 1, 1, 1, 1), {P1, P2, GR0, R3= }, EMPTY}, - {"cmp4.gt.or.andcm", A2, OpX2TbTaC (0xe, 1, 1, 1, 1), {P1, P2, R3, GR0= }, PSEUDO, 0, NULL}, - {"cmp4.ge.and.orcm", A2, OpX2TbTaC (0xe, 1, 1, 1, 1), {P2, P1, GR0, R3= }, PSEUDO, 0, NULL}, - {"cmp4.le.and.orcm", A2, OpX2TbTaC (0xe, 1, 1, 1, 1), {P2, P1, R3, GR0= }, PSEUDO, 0, NULL}, - {"cmp.eq", A2, OpX2TaC (0xe, 2, 0, 0), {P1, P2, IMM8, R3}, EMPTY}, - {"cmp.ne", A2, OpX2TaC (0xe, 2, 0, 0), {P2, P1, IMM8, R3}, EMPTY}, - {"cmp.eq.unc", A2, OpX2TaC (0xe, 2, 0, 1), {P1, P2, IMM8, R3}, EMPT= Y}, - {"cmp.ne.unc", A2, OpX2TaC (0xe, 2, 0, 1), {P2, P1, IMM8, R3}, EMPT= Y}, - {"cmp.eq.or.andcm", A2, OpX2TaC (0xe, 2, 1, 0), {P1, P2, IMM8, R3},= EMPTY}, - {"cmp.ne.and.orcm", A2, OpX2TaC (0xe, 2, 1, 0), {P2, P1, IMM8, R3},= PSEUDO, 0, NULL}, - {"cmp.ne.or.andcm", A2, OpX2TaC (0xe, 2, 1, 1), {P1, P2, IMM8, R3},= EMPTY}, - {"cmp.eq.and.orcm", A2, OpX2TaC (0xe, 2, 1, 1), {P2, P1, IMM8, R3},= PSEUDO, 0, NULL}, - {"cmp4.eq", A2, OpX2TaC (0xe, 3, 0, 0), {P1, P2, IMM8, R3}, EMPTY}, - {"cmp4.ne", A2, OpX2TaC (0xe, 3, 0, 0), {P2, P1, IMM8, R3}, EMPTY}, - {"cmp4.eq.unc", A2, OpX2TaC (0xe, 3, 0, 1), {P1, P2, IMM8, R3}, EMP= TY}, - {"cmp4.ne.unc", A2, OpX2TaC (0xe, 3, 0, 1), {P2, P1, IMM8, R3}, EMP= TY}, - {"cmp4.eq.or.andcm", A2, OpX2TaC (0xe, 3, 1, 0), {P1, P2, IMM8, R3},= EMPTY}, - {"cmp4.ne.and.orcm", A2, OpX2TaC (0xe, 3, 1, 0), {P2, P1, IMM8, R3},= PSEUDO, 0, NULL}, - {"cmp4.ne.or.andcm", A2, OpX2TaC (0xe, 3, 1, 1), {P1, P2, IMM8, R3},= EMPTY}, - {"cmp4.eq.and.orcm", A2, OpX2TaC (0xe, 3, 1, 1), {P2, P1, IMM8, R3},= PSEUDO, 0, NULL}, - - {NULL, 0, 0, 0, 0, {0}, 0, 0, NULL} - }; - -#undef A -#undef A2 -#undef bC -#undef bImm14 -#undef bR3a -#undef bR3b -#undef bTa -#undef bTb -#undef bVe -#undef bX -#undef bX2 -#undef bX2a -#undef bX2b -#undef bX4 -#undef bZa -#undef bZb -#undef mC -#undef mImm14 -#undef mR3a -#undef mR3b -#undef mTa -#undef mTb -#undef mVe -#undef mX -#undef mX2 -#undef mX2a -#undef mX2b -#undef mX4 -#undef mZa -#undef mZb -#undef OpR3a -#undef OpR3b -#undef OpX2aVe -#undef OpX2aVeImm14 -#undef OpX2aVeX4 -#undef OpX2aVeX4X2b -#undef OpX2TbTaC -#undef OpX2TaC -#undef OpX2aZaZbX4 -#undef OpX2aZaZbX4X2b -#undef EMPTY diff --git a/opcodes/ia64-opc-b.c b/opcodes/ia64-opc-b.c deleted file mode 100644 index 194129249ca..00000000000 --- a/opcodes/ia64-opc-b.c +++ /dev/null @@ -1,511 +0,0 @@ -/* ia64-opc-b.c -- IA-64 `B' opcode table. - Copyright (C) 1998-2024 Free Software Foundation, Inc. - Contributed by David Mosberger-Tang - - This file is part of the GNU opcodes library. - - This library is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3, or (at your option) - any later version. - - It is distributed in the hope that it will be useful, but WITHOUT - ANY WARRANTY; without even the implied warranty of MERCHANTABILITY - or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public - License for more details. - - You should have received a copy of the GNU General Public License - along with this file; see the file COPYING. If not, write to the - Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston, - MA 02110-1301, USA. */ - -#include "ia64-opc.h" - -#define B0 IA64_TYPE_B, 0 -#define B IA64_TYPE_B, 1 - -/* instruction bit fields: */ -#define bBtype(x) (((ia64_insn) ((x) & 0x7)) << 6) -#define bD(x) (((ia64_insn) ((x) & 0x1)) << 35) -#define bIh(x) (((ia64_insn) ((x) & 0x1)) << 35) -#define bPa(x) (((ia64_insn) ((x) & 0x1)) << 12) -#define bPr(x) (((ia64_insn) ((x) & 0x3f)) << 0) -#define bWha(x) (((ia64_insn) ((x) & 0x3)) << 33) -#define bWhb(x) (((ia64_insn) ((x) & 0x3)) << 3) -#define bWhc(x) (((ia64_insn) ((x) & 0x7)) << 32) -#define bX6(x) (((ia64_insn) ((x) & 0x3f)) << 27) - -#define mBtype bBtype (-1) -#define mD bD (-1) -#define mIh bIh (-1) -#define mPa bPa (-1) -#define mPr bPr (-1) -#define mWha bWha (-1) -#define mWhb bWhb (-1) -#define mWhc bWhc (-1) -#define mX6 bX6 (-1) - -#define OpX6(a,b) (bOp (a) | bX6 (b)), (mOp | mX6) -#define OpPaWhaD(a,b,c,d) \ - (bOp (a) | bPa (b) | bWha (c) | bD (d)), (mOp | mPa | mWha | mD) -#define OpPaWhcD(a,b,c,d) \ - (bOp (a) | bPa (b) | bWhc (c) | bD (d)), (mOp | mPa | mWhc | mD) -#define OpBtypePaWhaD(a,b,c,d,e) \ - (bOp (a) | bBtype (b) | bPa (c) | bWha (d) | bD (e)), \ - (mOp | mBtype | mPa | mWha | mD) -#define OpBtypePaWhaDPr(a,b,c,d,e,f) \ - (bOp (a) | bBtype (b) | bPa (c) | bWha (d) | bD (e) | bPr (f)), \ - (mOp | mBtype | mPa | mWha | mD | mPr) -#define OpX6BtypePaWhaD(a,b,c,d,e,f) \ - (bOp (a) | bX6 (b) | bBtype (c) | bPa (d) | bWha (e) | bD (f)), \ - (mOp | mX6 | mBtype | mPa | mWha | mD) -#define OpX6BtypePaWhaDPr(a,b,c,d,e,f,g) \ - (bOp (a) | bX6 (b) | bBtype (c) | bPa (d) | bWha (e) | bD (f) | bPr (g)= ), \ - (mOp | mX6 | mBtype | mPa | mWha | mD | mPr) -#define OpIhWhb(a,b,c) \ - (bOp (a) | bIh (b) | bWhb (c)), \ - (mOp | mIh | mWhb) -#define OpX6IhWhb(a,b,c,d) \ - (bOp (a) | bX6 (b) | bIh (c) | bWhb (d)), \ - (mOp | mX6 | mIh | mWhb) - -/* Used to initialise unused fields in ia64_opcode struct, - in order to stop gcc from complaining. */ -#define EMPTY 0,0,NULL - -struct ia64_opcode ia64_opcodes_b[] =3D - { - /* B-type instruction encodings (sorted according to major opcode) */ - -#define BR(a,b) \ - B0, OpX6BtypePaWhaDPr (0, 0x20, 0, a, 0, b, 0), {B2}, PSEUDO, 0, NULL - {"br.few", BR (0, 0)}, - {"br", BR (0, 0)}, - {"br.few.clr", BR (0, 1)}, - {"br.clr", BR (0, 1)}, - {"br.many", BR (1, 0)}, - {"br.many.clr", BR (1, 1)}, -#undef BR - -#define BR(a,b,c,d,e) B0, OpX6BtypePaWhaD (0, a, b, c, d, e), {B2}, EMPTY -#define BRP(a,b,c,d,e) B0, OpX6BtypePaWhaD (0, a, b, c, d, e), {B2}, PSEUD= O, 0, NULL -#define BRT(a,b,c,d,e,f) B0, OpX6BtypePaWhaD (0, a, b, c, d, e), {B2}, f, = 0, NULL - {"br.cond.sptk.few", BR (0x20, 0, 0, 0, 0)}, - {"br.cond.sptk", BRP (0x20, 0, 0, 0, 0)}, - {"br.cond.sptk.few.clr", BR (0x20, 0, 0, 0, 1)}, - {"br.cond.sptk.clr", BRP (0x20, 0, 0, 0, 1)}, - {"br.cond.spnt.few", BR (0x20, 0, 0, 1, 0)}, - {"br.cond.spnt", BRP (0x20, 0, 0, 1, 0)}, - {"br.cond.spnt.few.clr", BR (0x20, 0, 0, 1, 1)}, - {"br.cond.spnt.clr", BRP (0x20, 0, 0, 1, 1)}, - {"br.cond.dptk.few", BR (0x20, 0, 0, 2, 0)}, - {"br.cond.dptk", BRP (0x20, 0, 0, 2, 0)}, - {"br.cond.dptk.few.clr", BR (0x20, 0, 0, 2, 1)}, - {"br.cond.dptk.clr", BRP (0x20, 0, 0, 2, 1)}, - {"br.cond.dpnt.few", BR (0x20, 0, 0, 3, 0)}, - {"br.cond.dpnt", BRP (0x20, 0, 0, 3, 0)}, - {"br.cond.dpnt.few.clr", BR (0x20, 0, 0, 3, 1)}, - {"br.cond.dpnt.clr", BRP (0x20, 0, 0, 3, 1)}, - {"br.cond.sptk.many", BR (0x20, 0, 1, 0, 0)}, - {"br.cond.sptk.many.clr", BR (0x20, 0, 1, 0, 1)}, - {"br.cond.spnt.many", BR (0x20, 0, 1, 1, 0)}, - {"br.cond.spnt.many.clr", BR (0x20, 0, 1, 1, 1)}, - {"br.cond.dptk.many", BR (0x20, 0, 1, 2, 0)}, - {"br.cond.dptk.many.clr", BR (0x20, 0, 1, 2, 1)}, - {"br.cond.dpnt.many", BR (0x20, 0, 1, 3, 0)}, - {"br.cond.dpnt.many.clr", BR (0x20, 0, 1, 3, 1)}, - {"br.sptk.few", BR (0x20, 0, 0, 0, 0)}, - {"br.sptk", BRP (0x20, 0, 0, 0, 0)}, - {"br.sptk.few.clr", BR (0x20, 0, 0, 0, 1)}, - {"br.sptk.clr", BRP (0x20, 0, 0, 0, 1)}, - {"br.spnt.few", BR (0x20, 0, 0, 1, 0)}, - {"br.spnt", BRP (0x20, 0, 0, 1, 0)}, - {"br.spnt.few.clr", BR (0x20, 0, 0, 1, 1)}, - {"br.spnt.clr", BRP (0x20, 0, 0, 1, 1)}, - {"br.dptk.few", BR (0x20, 0, 0, 2, 0)}, - {"br.dptk", BRP (0x20, 0, 0, 2, 0)}, - {"br.dptk.few.clr", BR (0x20, 0, 0, 2, 1)}, - {"br.dptk.clr", BRP (0x20, 0, 0, 2, 1)}, - {"br.dpnt.few", BR (0x20, 0, 0, 3, 0)}, - {"br.dpnt", BRP (0x20, 0, 0, 3, 0)}, - {"br.dpnt.few.clr", BR (0x20, 0, 0, 3, 1)}, - {"br.dpnt.clr", BRP (0x20, 0, 0, 3, 1)}, - {"br.sptk.many", BR (0x20, 0, 1, 0, 0)}, - {"br.sptk.many.clr", BR (0x20, 0, 1, 0, 1)}, - {"br.spnt.many", BR (0x20, 0, 1, 1, 0)}, - {"br.spnt.many.clr", BR (0x20, 0, 1, 1, 1)}, - {"br.dptk.many", BR (0x20, 0, 1, 2, 0)}, - {"br.dptk.many.clr", BR (0x20, 0, 1, 2, 1)}, - {"br.dpnt.many", BR (0x20, 0, 1, 3, 0)}, - {"br.dpnt.many.clr", BR (0x20, 0, 1, 3, 1)}, - {"br.ia.sptk.few", BR (0x20, 1, 0, 0, 0)}, - {"br.ia.sptk", BRP (0x20, 1, 0, 0, 0)}, - {"br.ia.sptk.few.clr", BR (0x20, 1, 0, 0, 1)}, - {"br.ia.sptk.clr", BRP (0x20, 1, 0, 0, 1)}, - {"br.ia.spnt.few", BR (0x20, 1, 0, 1, 0)}, - {"br.ia.spnt", BRP (0x20, 1, 0, 1, 0)}, - {"br.ia.spnt.few.clr", BR (0x20, 1, 0, 1, 1)}, - {"br.ia.spnt.clr", BRP (0x20, 1, 0, 1, 1)}, - {"br.ia.dptk.few", BR (0x20, 1, 0, 2, 0)}, - {"br.ia.dptk", BRP (0x20, 1, 0, 2, 0)}, - {"br.ia.dptk.few.clr", BR (0x20, 1, 0, 2, 1)}, - {"br.ia.dptk.clr", BRP (0x20, 1, 0, 2, 1)}, - {"br.ia.dpnt.few", BR (0x20, 1, 0, 3, 0)}, - {"br.ia.dpnt", BRP (0x20, 1, 0, 3, 0)}, - {"br.ia.dpnt.few.clr", BR (0x20, 1, 0, 3, 1)}, - {"br.ia.dpnt.clr", BRP (0x20, 1, 0, 3, 1)}, - {"br.ia.sptk.many", BR (0x20, 1, 1, 0, 0)}, - {"br.ia.sptk.many.clr", BR (0x20, 1, 1, 0, 1)}, - {"br.ia.spnt.many", BR (0x20, 1, 1, 1, 0)}, - {"br.ia.spnt.many.clr", BR (0x20, 1, 1, 1, 1)}, - {"br.ia.dptk.many", BR (0x20, 1, 1, 2, 0)}, - {"br.ia.dptk.many.clr", BR (0x20, 1, 1, 2, 1)}, - {"br.ia.dpnt.many", BR (0x20, 1, 1, 3, 0)}, - {"br.ia.dpnt.many.clr", BR (0x20, 1, 1, 3, 1)}, - {"br.ret.sptk.few", BRT (0x21, 4, 0, 0, 0, MOD_RRBS)}, - {"br.ret.sptk", BRT (0x21, 4, 0, 0, 0, PSEUDO | MOD_RRBS)}, - {"br.ret.sptk.few.clr", BRT (0x21, 4, 0, 0, 1, MOD_RRBS)}, - {"br.ret.sptk.clr", BRT (0x21, 4, 0, 0, 1, PSEUDO | MOD_RRBS)}, - {"br.ret.spnt.few", BRT (0x21, 4, 0, 1, 0, MOD_RRBS)}, - {"br.ret.spnt", BRT (0x21, 4, 0, 1, 0, PSEUDO | MOD_RRBS)}, - {"br.ret.spnt.few.clr", BRT (0x21, 4, 0, 1, 1, MOD_RRBS)}, - {"br.ret.spnt.clr", BRT (0x21, 4, 0, 1, 1, PSEUDO | MOD_RRBS)}, - {"br.ret.dptk.few", BRT (0x21, 4, 0, 2, 0, MOD_RRBS)}, - {"br.ret.dptk", BRT (0x21, 4, 0, 2, 0, PSEUDO | MOD_RRBS)}, - {"br.ret.dptk.few.clr", BRT (0x21, 4, 0, 2, 1, MOD_RRBS)}, - {"br.ret.dptk.clr", BRT (0x21, 4, 0, 2, 1, PSEUDO | MOD_RRBS)}, - {"br.ret.dpnt.few", BRT (0x21, 4, 0, 3, 0, MOD_RRBS)}, - {"br.ret.dpnt", BRT (0x21, 4, 0, 3, 0, PSEUDO | MOD_RRBS)}, - {"br.ret.dpnt.few.clr", BRT (0x21, 4, 0, 3, 1, MOD_RRBS)}, - {"br.ret.dpnt.clr", BRT (0x21, 4, 0, 3, 1, PSEUDO | MOD_RRBS)}, - {"br.ret.sptk.many", BRT (0x21, 4, 1, 0, 0, MOD_RRBS)}, - {"br.ret.sptk.many.clr", BRT (0x21, 4, 1, 0, 1, MOD_RRBS)}, - {"br.ret.spnt.many", BRT (0x21, 4, 1, 1, 0, MOD_RRBS)}, - {"br.ret.spnt.many.clr", BRT (0x21, 4, 1, 1, 1, MOD_RRBS)}, - {"br.ret.dptk.many", BRT (0x21, 4, 1, 2, 0, MOD_RRBS)}, - {"br.ret.dptk.many.clr", BRT (0x21, 4, 1, 2, 1, MOD_RRBS)}, - {"br.ret.dpnt.many", BRT (0x21, 4, 1, 3, 0, MOD_RRBS)}, - {"br.ret.dpnt.many.clr", BRT (0x21, 4, 1, 3, 1, MOD_RRBS)}, -#undef BR -#undef BRP -#undef BRT - - {"cover", B0, OpX6 (0, 0x02), {0, }, NO_PRED | LAST | MOD_RRBS, 0, NU= LL}, - {"clrrrb", B0, OpX6 (0, 0x04), {0, }, NO_PRED | LAST | MOD_RRBS, 0, N= ULL}, - {"clrrrb.pr", B0, OpX6 (0, 0x05), {0, }, NO_PRED | LAST | MOD_RRBS, 0,= NULL}, - {"rfi", B0, OpX6 (0, 0x08), {0, }, NO_PRED | LAST | PRIV | MOD_RRBS, = 0, NULL}, - {"bsw.0", B0, OpX6 (0, 0x0c), {0, }, NO_PRED | LAST | PRIV, 0, NULL}, - {"bsw.1", B0, OpX6 (0, 0x0d), {0, }, NO_PRED | LAST | PRIV, 0, NULL}, - {"epc", B0, OpX6 (0, 0x10), {0, }, NO_PRED, 0, NULL}, - {"vmsw.0", B0, OpX6 (0, 0x18), {0, }, NO_PRED | PRIV, 0, NULL}, - {"vmsw.1", B0, OpX6 (0, 0x19), {0, }, NO_PRED | PRIV, 0, NULL}, - - {"break.b", B0, OpX6 (0, 0x00), {IMMU21}, EMPTY}, - - {"br.call.sptk.few", B, OpPaWhcD (1, 0, 1, 0), {B1, B2}, EMPTY}, - {"br.call.sptk", B, OpPaWhcD (1, 0, 1, 0), {B1, B2}, PSEUDO, 0, NULL}, - {"br.call.sptk.few.clr", B, OpPaWhcD (1, 0, 1, 1), {B1, B2}, EMPTY}, - {"br.call.sptk.clr", B, OpPaWhcD (1, 0, 1, 1), {B1, B2}, PSEUDO, 0, NU= LL}, - {"br.call.spnt.few", B, OpPaWhcD (1, 0, 3, 0), {B1, B2}, EMPTY}, - {"br.call.spnt", B, OpPaWhcD (1, 0, 3, 0), {B1, B2}, PSEUDO, 0, NULL}, - {"br.call.spnt.few.clr", B, OpPaWhcD (1, 0, 3, 1), {B1, B2}, EMPTY}, - {"br.call.spnt.clr", B, OpPaWhcD (1, 0, 3, 1), {B1, B2}, PSEUDO, 0, NU= LL}, - {"br.call.dptk.few", B, OpPaWhcD (1, 0, 5, 0), {B1, B2}, EMPTY}, - {"br.call.dptk", B, OpPaWhcD (1, 0, 5, 0), {B1, B2}, PSEUDO, 0, NULL}, - {"br.call.dptk.few.clr", B, OpPaWhcD (1, 0, 5, 1), {B1, B2}, EMPTY}, - {"br.call.dptk.clr", B, OpPaWhcD (1, 0, 5, 1), {B1, B2}, PSEUDO, 0, NU= LL}, - {"br.call.dpnt.few", B, OpPaWhcD (1, 0, 7, 0), {B1, B2}, EMPTY}, - {"br.call.dpnt", B, OpPaWhcD (1, 0, 7, 0), {B1, B2}, PSEUDO, 0, NULL}, - {"br.call.dpnt.few.clr", B, OpPaWhcD (1, 0, 7, 1), {B1, B2}, EMPTY}, - {"br.call.dpnt.clr", B, OpPaWhcD (1, 0, 7, 1), {B1, B2}, PSEUDO, 0, NU= LL}, - {"br.call.sptk.many", B, OpPaWhcD (1, 1, 1, 0), {B1, B2}, EMPTY}, - {"br.call.sptk.many.clr", B, OpPaWhcD (1, 1, 1, 1), {B1, B2}, EMPTY}, - {"br.call.spnt.many", B, OpPaWhcD (1, 1, 3, 0), {B1, B2}, EMPTY}, - {"br.call.spnt.many.clr", B, OpPaWhcD (1, 1, 3, 1), {B1, B2}, EMPTY}, - {"br.call.dptk.many", B, OpPaWhcD (1, 1, 5, 0), {B1, B2}, EMPTY}, - {"br.call.dptk.many.clr", B, OpPaWhcD (1, 1, 5, 1), {B1, B2}, EMPTY}, - {"br.call.dpnt.many", B, OpPaWhcD (1, 1, 7, 0), {B1, B2}, EMPTY}, - {"br.call.dpnt.many.clr", B, OpPaWhcD (1, 1, 7, 1), {B1, B2}, EMPTY}, - -#define BRP(a,b,c) \ - B0, OpX6IhWhb (2, a, b, c), {B2, TAG13}, NO_PRED, 0, NULL - {"brp.sptk", BRP (0x10, 0, 0)}, - {"brp.dptk", BRP (0x10, 0, 2)}, - {"brp.sptk.imp", BRP (0x10, 1, 0)}, - {"brp.dptk.imp", BRP (0x10, 1, 2)}, - {"brp.ret.sptk", BRP (0x11, 0, 0)}, - {"brp.ret.dptk", BRP (0x11, 0, 2)}, - {"brp.ret.sptk.imp", BRP (0x11, 1, 0)}, - {"brp.ret.dptk.imp", BRP (0x11, 1, 2)}, -#undef BRP - - {"nop.b", B0, OpX6 (2, 0x00), {IMMU21}, EMPTY}, - {"hint.b", B0, OpX6 (2, 0x01), {IMMU21}, EMPTY}, - -#define BR(a,b) \ - B0, OpBtypePaWhaDPr (4, 0, a, 0, b, 0), {TGT25c}, PSEUDO, 0, NULL - {"br.few", BR (0, 0)}, - {"br", BR (0, 0)}, - {"br.few.clr", BR (0, 1)}, - {"br.clr", BR (0, 1)}, - {"br.many", BR (1, 0)}, - {"br.many.clr", BR (1, 1)}, -#undef BR - -#define BR(a,b,c) \ - B0, OpBtypePaWhaD (4, 0, a, b, c), {TGT25c}, EMPTY -#define BRP(a,b,c) \ - B0, OpBtypePaWhaD (4, 0, a, b, c), {TGT25c}, PSEUDO, 0, NULL - {"br.cond.sptk.few", BR (0, 0, 0)}, - {"br.cond.sptk", BRP (0, 0, 0)}, - {"br.cond.sptk.few.clr", BR (0, 0, 1)}, - {"br.cond.sptk.clr", BRP (0, 0, 1)}, - {"br.cond.spnt.few", BR (0, 1, 0)}, - {"br.cond.spnt", BRP (0, 1, 0)}, - {"br.cond.spnt.few.clr", BR (0, 1, 1)}, - {"br.cond.spnt.clr", BRP (0, 1, 1)}, - {"br.cond.dptk.few", BR (0, 2, 0)}, - {"br.cond.dptk", BRP (0, 2, 0)}, - {"br.cond.dptk.few.clr", BR (0, 2, 1)}, - {"br.cond.dptk.clr", BRP (0, 2, 1)}, - {"br.cond.dpnt.few", BR (0, 3, 0)}, - {"br.cond.dpnt", BRP (0, 3, 0)}, - {"br.cond.dpnt.few.clr", BR (0, 3, 1)}, - {"br.cond.dpnt.clr", BRP (0, 3, 1)}, - {"br.cond.sptk.many", BR (1, 0, 0)}, - {"br.cond.sptk.many.clr", BR (1, 0, 1)}, - {"br.cond.spnt.many", BR (1, 1, 0)}, - {"br.cond.spnt.many.clr", BR (1, 1, 1)}, - {"br.cond.dptk.many", BR (1, 2, 0)}, - {"br.cond.dptk.many.clr", BR (1, 2, 1)}, - {"br.cond.dpnt.many", BR (1, 3, 0)}, - {"br.cond.dpnt.many.clr", BR (1, 3, 1)}, - {"br.sptk.few", BR (0, 0, 0)}, - {"br.sptk", BRP (0, 0, 0)}, - {"br.sptk.few.clr", BR (0, 0, 1)}, - {"br.sptk.clr", BRP (0, 0, 1)}, - {"br.spnt.few", BR (0, 1, 0)}, - {"br.spnt", BRP (0, 1, 0)}, - {"br.spnt.few.clr", BR (0, 1, 1)}, - {"br.spnt.clr", BRP (0, 1, 1)}, - {"br.dptk.few", BR (0, 2, 0)}, - {"br.dptk", BRP (0, 2, 0)}, - {"br.dptk.few.clr", BR (0, 2, 1)}, - {"br.dptk.clr", BRP (0, 2, 1)}, - {"br.dpnt.few", BR (0, 3, 0)}, - {"br.dpnt", BRP (0, 3, 0)}, - {"br.dpnt.few.clr", BR (0, 3, 1)}, - {"br.dpnt.clr", BRP (0, 3, 1)}, - {"br.sptk.many", BR (1, 0, 0)}, - {"br.sptk.many.clr", BR (1, 0, 1)}, - {"br.spnt.many", BR (1, 1, 0)}, - {"br.spnt.many.clr", BR (1, 1, 1)}, - {"br.dptk.many", BR (1, 2, 0)}, - {"br.dptk.many.clr", BR (1, 2, 1)}, - {"br.dpnt.many", BR (1, 3, 0)}, - {"br.dpnt.many.clr", BR (1, 3, 1)}, -#undef BR -#undef BRP - -#define BR(a,b,c,d, e) \ - B0, OpBtypePaWhaD (4, a, b, c, d), {TGT25c}, SLOT2 | e, 0, NULL - {"br.wexit.sptk.few", BR (2, 0, 0, 0, MOD_RRBS)}, - {"br.wexit.sptk", BR (2, 0, 0, 0, PSEUDO | MOD_RRBS)}, - {"br.wexit.sptk.few.clr", BR (2, 0, 0, 1, MOD_RRBS)}, - {"br.wexit.sptk.clr", BR (2, 0, 0, 1, PSEUDO | MOD_RRBS)}, - {"br.wexit.spnt.few", BR (2, 0, 1, 0, MOD_RRBS)}, - {"br.wexit.spnt", BR (2, 0, 1, 0, PSEUDO | MOD_RRBS)}, - {"br.wexit.spnt.few.clr", BR (2, 0, 1, 1, MOD_RRBS)}, - {"br.wexit.spnt.clr", BR (2, 0, 1, 1, PSEUDO | MOD_RRBS)}, - {"br.wexit.dptk.few", BR (2, 0, 2, 0, MOD_RRBS)}, - {"br.wexit.dptk", BR (2, 0, 2, 0, PSEUDO | MOD_RRBS)}, - {"br.wexit.dptk.few.clr", BR (2, 0, 2, 1, MOD_RRBS)}, - {"br.wexit.dptk.clr", BR (2, 0, 2, 1, PSEUDO | MOD_RRBS)}, - {"br.wexit.dpnt.few", BR (2, 0, 3, 0, MOD_RRBS)}, - {"br.wexit.dpnt", BR (2, 0, 3, 0, PSEUDO | MOD_RRBS)}, - {"br.wexit.dpnt.few.clr", BR (2, 0, 3, 1, MOD_RRBS)}, - {"br.wexit.dpnt.clr", BR (2, 0, 3, 1, PSEUDO | MOD_RRBS)}, - {"br.wexit.sptk.many", BR (2, 1, 0, 0, MOD_RRBS)}, - {"br.wexit.sptk.many.clr", BR (2, 1, 0, 1, MOD_RRBS)}, - {"br.wexit.spnt.many", BR (2, 1, 1, 0, MOD_RRBS)}, - {"br.wexit.spnt.many.clr", BR (2, 1, 1, 1, MOD_RRBS)}, - {"br.wexit.dptk.many", BR (2, 1, 2, 0, MOD_RRBS)}, - {"br.wexit.dptk.many.clr", BR (2, 1, 2, 1, MOD_RRBS)}, - {"br.wexit.dpnt.many", BR (2, 1, 3, 0, MOD_RRBS)}, - {"br.wexit.dpnt.many.clr", BR (2, 1, 3, 1, MOD_RRBS)}, - {"br.wtop.sptk.few", BR (3, 0, 0, 0, MOD_RRBS)}, - {"br.wtop.sptk", BR (3, 0, 0, 0, PSEUDO | MOD_RRBS)}, - {"br.wtop.sptk.few.clr", BR (3, 0, 0, 1, MOD_RRBS)}, - {"br.wtop.sptk.clr", BR (3, 0, 0, 1, PSEUDO | MOD_RRBS)}, - {"br.wtop.spnt.few", BR (3, 0, 1, 0, MOD_RRBS)}, - {"br.wtop.spnt", BR (3, 0, 1, 0, PSEUDO | MOD_RRBS)}, - {"br.wtop.spnt.few.clr", BR (3, 0, 1, 1, MOD_RRBS)}, - {"br.wtop.spnt.clr", BR (3, 0, 1, 1, PSEUDO | MOD_RRBS)}, - {"br.wtop.dptk.few", BR (3, 0, 2, 0, MOD_RRBS)}, - {"br.wtop.dptk", BR (3, 0, 2, 0, PSEUDO | MOD_RRBS)}, - {"br.wtop.dptk.few.clr", BR (3, 0, 2, 1, MOD_RRBS)}, - {"br.wtop.dptk.clr", BR (3, 0, 2, 1, PSEUDO | MOD_RRBS)}, - {"br.wtop.dpnt.few", BR (3, 0, 3, 0, MOD_RRBS)}, - {"br.wtop.dpnt", BR (3, 0, 3, 0, PSEUDO | MOD_RRBS)}, - {"br.wtop.dpnt.few.clr", BR (3, 0, 3, 1, MOD_RRBS)}, - {"br.wtop.dpnt.clr", BR (3, 0, 3, 1, PSEUDO | MOD_RRBS)}, - {"br.wtop.sptk.many", BR (3, 1, 0, 0, MOD_RRBS)}, - {"br.wtop.sptk.many.clr", BR (3, 1, 0, 1, MOD_RRBS)}, - {"br.wtop.spnt.many", BR (3, 1, 1, 0, MOD_RRBS)}, - {"br.wtop.spnt.many.clr", BR (3, 1, 1, 1, MOD_RRBS)}, - {"br.wtop.dptk.many", BR (3, 1, 2, 0, MOD_RRBS)}, - {"br.wtop.dptk.many.clr", BR (3, 1, 2, 1, MOD_RRBS)}, - {"br.wtop.dpnt.many", BR (3, 1, 3, 0, MOD_RRBS)}, - {"br.wtop.dpnt.many.clr", BR (3, 1, 3, 1, MOD_RRBS)}, - -#undef BR -#define BR(a,b,c,d) \ - B0, OpBtypePaWhaD (4, a, b, c, d), {TGT25c}, SLOT2 | NO_PRED, 0, NULL -#define BRT(a,b,c,d,e) \ - B0, OpBtypePaWhaD (4, a, b, c, d), {TGT25c}, SLOT2 | NO_PRED | e, 0, NULL - {"br.cloop.sptk.few", BR (5, 0, 0, 0)}, - {"br.cloop.sptk", BRT (5, 0, 0, 0, PSEUDO)}, - {"br.cloop.sptk.few.clr", BR (5, 0, 0, 1)}, - {"br.cloop.sptk.clr", BRT (5, 0, 0, 1, PSEUDO)}, - {"br.cloop.spnt.few", BR (5, 0, 1, 0)}, - {"br.cloop.spnt", BRT (5, 0, 1, 0, PSEUDO)}, - {"br.cloop.spnt.few.clr", BR (5, 0, 1, 1)}, - {"br.cloop.spnt.clr", BRT (5, 0, 1, 1, PSEUDO)}, - {"br.cloop.dptk.few", BR (5, 0, 2, 0)}, - {"br.cloop.dptk", BRT (5, 0, 2, 0, PSEUDO)}, - {"br.cloop.dptk.few.clr", BR (5, 0, 2, 1)}, - {"br.cloop.dptk.clr", BRT (5, 0, 2, 1, PSEUDO)}, - {"br.cloop.dpnt.few", BR (5, 0, 3, 0)}, - {"br.cloop.dpnt", BRT (5, 0, 3, 0, PSEUDO)}, - {"br.cloop.dpnt.few.clr", BR (5, 0, 3, 1)}, - {"br.cloop.dpnt.clr", BRT (5, 0, 3, 1, PSEUDO)}, - {"br.cloop.sptk.many", BR (5, 1, 0, 0)}, - {"br.cloop.sptk.many.clr", BR (5, 1, 0, 1)}, - {"br.cloop.spnt.many", BR (5, 1, 1, 0)}, - {"br.cloop.spnt.many.clr", BR (5, 1, 1, 1)}, - {"br.cloop.dptk.many", BR (5, 1, 2, 0)}, - {"br.cloop.dptk.many.clr", BR (5, 1, 2, 1)}, - {"br.cloop.dpnt.many", BR (5, 1, 3, 0)}, - {"br.cloop.dpnt.many.clr", BR (5, 1, 3, 1)}, - {"br.cexit.sptk.few", BRT (6, 0, 0, 0, MOD_RRBS)}, - {"br.cexit.sptk", BRT (6, 0, 0, 0, PSEUDO | MOD_RRBS)}, - {"br.cexit.sptk.few.clr", BRT (6, 0, 0, 1, MOD_RRBS)}, - {"br.cexit.sptk.clr", BRT (6, 0, 0, 1, PSEUDO | MOD_RRBS)}, - {"br.cexit.spnt.few", BRT (6, 0, 1, 0, MOD_RRBS)}, - {"br.cexit.spnt", BRT (6, 0, 1, 0, PSEUDO | MOD_RRBS)}, - {"br.cexit.spnt.few.clr", BRT (6, 0, 1, 1, MOD_RRBS)}, - {"br.cexit.spnt.clr", BRT (6, 0, 1, 1, PSEUDO | MOD_RRBS)}, - {"br.cexit.dptk.few", BRT (6, 0, 2, 0, MOD_RRBS)}, - {"br.cexit.dptk", BRT (6, 0, 2, 0, PSEUDO | MOD_RRBS)}, - {"br.cexit.dptk.few.clr", BRT (6, 0, 2, 1, MOD_RRBS)}, - {"br.cexit.dptk.clr", BRT (6, 0, 2, 1, PSEUDO | MOD_RRBS)}, - {"br.cexit.dpnt.few", BRT (6, 0, 3, 0, MOD_RRBS)}, - {"br.cexit.dpnt", BRT (6, 0, 3, 0, PSEUDO | MOD_RRBS)}, - {"br.cexit.dpnt.few.clr", BRT (6, 0, 3, 1, MOD_RRBS)}, - {"br.cexit.dpnt.clr", BRT (6, 0, 3, 1, PSEUDO | MOD_RRBS)}, - {"br.cexit.sptk.many", BRT (6, 1, 0, 0, MOD_RRBS)}, - {"br.cexit.sptk.many.clr", BRT (6, 1, 0, 1, MOD_RRBS)}, - {"br.cexit.spnt.many", BRT (6, 1, 1, 0, MOD_RRBS)}, - {"br.cexit.spnt.many.clr", BRT (6, 1, 1, 1, MOD_RRBS)}, - {"br.cexit.dptk.many", BRT (6, 1, 2, 0, MOD_RRBS)}, - {"br.cexit.dptk.many.clr", BRT (6, 1, 2, 1, MOD_RRBS)}, - {"br.cexit.dpnt.many", BRT (6, 1, 3, 0, MOD_RRBS)}, - {"br.cexit.dpnt.many.clr", BRT (6, 1, 3, 1, MOD_RRBS)}, - {"br.ctop.sptk.few", BRT (7, 0, 0, 0, MOD_RRBS)}, - {"br.ctop.sptk", BRT (7, 0, 0, 0, PSEUDO | MOD_RRBS)}, - {"br.ctop.sptk.few.clr", BRT (7, 0, 0, 1, MOD_RRBS)}, - {"br.ctop.sptk.clr", BRT (7, 0, 0, 1, PSEUDO | MOD_RRBS)}, - {"br.ctop.spnt.few", BRT (7, 0, 1, 0, MOD_RRBS)}, - {"br.ctop.spnt", BRT (7, 0, 1, 0, PSEUDO | MOD_RRBS)}, - {"br.ctop.spnt.few.clr", BRT (7, 0, 1, 1, MOD_RRBS)}, - {"br.ctop.spnt.clr", BRT (7, 0, 1, 1, PSEUDO | MOD_RRBS)}, - {"br.ctop.dptk.few", BRT (7, 0, 2, 0, MOD_RRBS)}, - {"br.ctop.dptk", BRT (7, 0, 2, 0, PSEUDO | MOD_RRBS)}, - {"br.ctop.dptk.few.clr", BRT (7, 0, 2, 1, MOD_RRBS)}, - {"br.ctop.dptk.clr", BRT (7, 0, 2, 1, PSEUDO | MOD_RRBS)}, - {"br.ctop.dpnt.few", BRT (7, 0, 3, 0, MOD_RRBS)}, - {"br.ctop.dpnt", BRT (7, 0, 3, 0, PSEUDO | MOD_RRBS)}, - {"br.ctop.dpnt.few.clr", BRT (7, 0, 3, 1, MOD_RRBS)}, - {"br.ctop.dpnt.clr", BRT (7, 0, 3, 1, PSEUDO | MOD_RRBS)}, - {"br.ctop.sptk.many", BRT (7, 1, 0, 0, MOD_RRBS)}, - {"br.ctop.sptk.many.clr", BRT (7, 1, 0, 1, MOD_RRBS)}, - {"br.ctop.spnt.many", BRT (7, 1, 1, 0, MOD_RRBS)}, - {"br.ctop.spnt.many.clr", BRT (7, 1, 1, 1, MOD_RRBS)}, - {"br.ctop.dptk.many", BRT (7, 1, 2, 0, MOD_RRBS)}, - {"br.ctop.dptk.many.clr", BRT (7, 1, 2, 1, MOD_RRBS)}, - {"br.ctop.dpnt.many", BRT (7, 1, 3, 0, MOD_RRBS)}, - {"br.ctop.dpnt.many.clr", BRT (7, 1, 3, 1, MOD_RRBS)}, -#undef BR -#undef BRT - - {"br.call.sptk.few", B, OpPaWhaD (5, 0, 0, 0), {B1, TGT25c}, EMPTY}, - {"br.call.sptk", B, OpPaWhaD (5, 0, 0, 0), {B1, TGT25c}, PSEUDO, 0, N= ULL}, - {"br.call.sptk.few.clr", B, OpPaWhaD (5, 0, 0, 1), {B1, TGT25c}, EMPTY= }, - {"br.call.sptk.clr", B, OpPaWhaD (5, 0, 0, 1), {B1, TGT25c}, PSEUDO, 0= , NULL}, - {"br.call.spnt.few", B, OpPaWhaD (5, 0, 1, 0), {B1, TGT25c}, EMPTY}, - {"br.call.spnt", B, OpPaWhaD (5, 0, 1, 0), {B1, TGT25c}, PSEUDO, 0, N= ULL}, - {"br.call.spnt.few.clr", B, OpPaWhaD (5, 0, 1, 1), {B1, TGT25c}, EMPTY= }, - {"br.call.spnt.clr", B, OpPaWhaD (5, 0, 1, 1), {B1, TGT25c}, PSEUDO, 0= , NULL}, - {"br.call.dptk.few", B, OpPaWhaD (5, 0, 2, 0), {B1, TGT25c}, EMPTY}, - {"br.call.dptk", B, OpPaWhaD (5, 0, 2, 0), {B1, TGT25c}, PSEUDO, 0, N= ULL}, - {"br.call.dptk.few.clr", B, OpPaWhaD (5, 0, 2, 1), {B1, TGT25c}, EMPTY= }, - {"br.call.dptk.clr", B, OpPaWhaD (5, 0, 2, 1), {B1, TGT25c}, PSEUDO, 0= , NULL}, - {"br.call.dpnt.few", B, OpPaWhaD (5, 0, 3, 0), {B1, TGT25c}, EMPTY}, - {"br.call.dpnt", B, OpPaWhaD (5, 0, 3, 0), {B1, TGT25c}, PSEUDO, 0, N= ULL}, - {"br.call.dpnt.few.clr", B, OpPaWhaD (5, 0, 3, 1), {B1, TGT25c}, EMPTY= }, - {"br.call.dpnt.clr", B, OpPaWhaD (5, 0, 3, 1), {B1, TGT25c}, PSEUDO, 0= , NULL}, - {"br.call.sptk.many", B, OpPaWhaD (5, 1, 0, 0), {B1, TGT25c}, EMPTY}, - {"br.call.sptk.many.clr", B, OpPaWhaD (5, 1, 0, 1), {B1, TGT25c}, EMPT= Y}, - {"br.call.spnt.many", B, OpPaWhaD (5, 1, 1, 0), {B1, TGT25c}, EMPTY}, - {"br.call.spnt.many.clr", B, OpPaWhaD (5, 1, 1, 1), {B1, TGT25c}, EMPT= Y}, - {"br.call.dptk.many", B, OpPaWhaD (5, 1, 2, 0), {B1, TGT25c}, EMPTY}, - {"br.call.dptk.many.clr", B, OpPaWhaD (5, 1, 2, 1), {B1, TGT25c}, EMPT= Y}, - {"br.call.dpnt.many", B, OpPaWhaD (5, 1, 3, 0), {B1, TGT25c}, EMPTY}, - {"br.call.dpnt.many.clr", B, OpPaWhaD (5, 1, 3, 1), {B1, TGT25c}, EMPT= Y}, - - /* Branch predict. */ -#define BRP(a,b) \ - B0, OpIhWhb (7, a, b), {TGT25c, TAG13}, NO_PRED, 0, NULL - {"brp.sptk", BRP (0, 0)}, - {"brp.loop", BRP (0, 1)}, - {"brp.dptk", BRP (0, 2)}, - {"brp.exit", BRP (0, 3)}, - {"brp.sptk.imp", BRP (1, 0)}, - {"brp.loop.imp", BRP (1, 1)}, - {"brp.dptk.imp", BRP (1, 2)}, - {"brp.exit.imp", BRP (1, 3)}, -#undef BRP - - {NULL, 0, 0, 0, 0, {0}, 0, 0, NULL} - }; - -#undef B0 -#undef B -#undef bBtype -#undef bD -#undef bIh -#undef bPa -#undef bPr -#undef bWha -#undef bWhb -#undef bWhc -#undef bX6 -#undef mBtype -#undef mD -#undef mIh -#undef mPa -#undef mPr -#undef mWha -#undef mWhb -#undef mWhc -#undef mX6 -#undef OpX6 -#undef OpPaWhaD -#undef OpPaWhcD -#undef OpBtypePaWhaD -#undef OpBtypePaWhaDPr -#undef OpX6BtypePaWhaD -#undef OpX6BtypePaWhaDPr -#undef OpIhWhb -#undef OpX6IhWhb -#undef EMPTY diff --git a/opcodes/ia64-opc-d.c b/opcodes/ia64-opc-d.c deleted file mode 100644 index ca93605c40f..00000000000 --- a/opcodes/ia64-opc-d.c +++ /dev/null @@ -1,34 +0,0 @@ -/* ia64-opc-d.c -- IA-64 `D' opcode table. - Copyright (C) 1998-2024 Free Software Foundation, Inc. - Contributed by David Mosberger-Tang - - This file is part of the GNU opcodes library. - - This library is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3, or (at your option) - any later version. - - It is distributed in the hope that it will be useful, but WITHOUT - ANY WARRANTY; without even the implied warranty of MERCHANTABILITY - or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public - License for more details. - - You should have received a copy of the GNU General Public License - along with this file; see the file COPYING. If not, write to the - Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston, - MA 02110-1301, USA. */ - -struct ia64_opcode ia64_opcodes_d[] =3D - { - {"add", IA64_TYPE_DYN, 1, 0, 0, {IA64_OPND_R1, IA64_OPND_IMM22, IA64= _OPND_R3_2}, 0, 0, NULL}, - {"add", IA64_TYPE_DYN, 1, 0, 0, {IA64_OPND_R1, IA64_OPND_IMM14, IA64= _OPND_R3}, 0, 0, NULL}, - {"break", IA64_TYPE_DYN, 0, 0, 0, {IA64_OPND_IMMU21}, 0, 0, NULL}, - {"chk.s", IA64_TYPE_DYN, 0, 0, 0, {IA64_OPND_R2, IA64_OPND_TGT25b}, 0,= 0, NULL}, - {"hint", IA64_TYPE_DYN, 0, 0, 0, {IA64_OPND_IMMU21}, 0, 0, NULL}, - {"mov", IA64_TYPE_DYN, 1, 0, 0, {IA64_OPND_R1, IA64_OPND_AR3}, 0, 0= , NULL}, - {"mov", IA64_TYPE_DYN, 1, 0, 0, {IA64_OPND_AR3, IA64_OPND_IMM8}, 0, = 0, NULL}, - {"mov", IA64_TYPE_DYN, 1, 0, 0, {IA64_OPND_AR3, IA64_OPND_R2}, 0, 0,= NULL}, - {"nop", IA64_TYPE_DYN, 0, 0, 0, {IA64_OPND_IMMU21}, 0, 0, NULL}, - {NULL, 0, 0, 0, 0, {0}, 0, 0, NULL} - }; diff --git a/opcodes/ia64-opc-f.c b/opcodes/ia64-opc-f.c deleted file mode 100644 index a374d784ff2..00000000000 --- a/opcodes/ia64-opc-f.c +++ /dev/null @@ -1,656 +0,0 @@ -/* ia64-opc-f.c -- IA-64 `F' opcode table. - Copyright (C) 1998-2024 Free Software Foundation, Inc. - Contributed by David Mosberger-Tang - - This file is part of the GNU opcodes library. - - This library is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3, or (at your option) - any later version. - - It is distributed in the hope that it will be useful, but WITHOUT - ANY WARRANTY; without even the implied warranty of MERCHANTABILITY - or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public - License for more details. - - You should have received a copy of the GNU General Public License - along with this file; see the file COPYING. If not, write to the - Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston, - MA 02110-1301, USA. */ - -#include "ia64-opc.h" - -#define f0 IA64_TYPE_F, 0 -#define f IA64_TYPE_F, 1 -#define f2 IA64_TYPE_F, 2 - -#define bF2(x) (((ia64_insn) ((x) & 0x7f)) << 13) -#define bF4(x) (((ia64_insn) ((x) & 0x7f)) << 27) -#define bQ(x) (((ia64_insn) ((x) & 0x1)) << 36) -#define bRa(x) (((ia64_insn) ((x) & 0x1)) << 33) -#define bRb(x) (((ia64_insn) ((x) & 0x1)) << 36) -#define bSf(x) (((ia64_insn) ((x) & 0x3)) << 34) -#define bTa(x) (((ia64_insn) ((x) & 0x1)) << 12) -#define bXa(x) (((ia64_insn) ((x) & 0x1)) << 36) -#define bXb(x) (((ia64_insn) ((x) & 0x1)) << 33) -#define bX2(x) (((ia64_insn) ((x) & 0x3)) << 34) -#define bX6(x) (((ia64_insn) ((x) & 0x3f)) << 27) -#define bY(x) (((ia64_insn) ((x) & 0x1)) << 26) - -#define mF2 bF2 (-1) -#define mF4 bF4 (-1) -#define mQ bQ (-1) -#define mRa bRa (-1) -#define mRb bRb (-1) -#define mSf bSf (-1) -#define mTa bTa (-1) -#define mXa bXa (-1) -#define mXb bXb (-1) -#define mX2 bX2 (-1) -#define mX6 bX6 (-1) -#define mY bY (-1) - -#define OpXa(a,b) (bOp (a) | bXa (b)), (mOp | mXa) -#define OpXaSf(a,b,c) (bOp (a) | bXa (b) | bSf (c)), (mOp | mXa | mSf) -#define OpXaSfF2(a,b,c,d) \ - (bOp (a) | bXa (b) | bSf (c) | bF2 (d)), (mOp | mXa | mSf | mF2) -#define OpXaSfF4(a,b,c,d) \ - (bOp (a) | bXa (b) | bSf (c) | bF4 (d)), (mOp | mXa | mSf | mF4) -#define OpXaSfF2F4(a,b,c,d,e) \ - (bOp (a) | bXa (b) | bSf (c) | bF2 (d) | bF4 (e)), \ - (mOp | mXa | mSf | mF2 | mF4) -#define OpXaX2(a,b,c) (bOp (a) | bXa (b) | bX2 (c)), (mOp | mXa | mX2) -#define OpXaX2F2(a,b,c,d) \ - (bOp (a) | bXa (b) | bX2 (c) | bF2 (d)), (mOp | mXa | mX2 | mF2) -#define OpRaRbTaSf(a,b,c,d,e) \ - (bOp (a) | bRa (b) | bRb (c) | bTa (d) | bSf (e)), \ - (mOp | mRa | mRb | mTa | mSf) -#define OpTa(a,b) (bOp (a) | bTa (b)), (mOp | mTa) -#define OpXbQSf(a,b,c,d) \ - (bOp (a) | bXb (b) | bQ (c) | bSf (d)), (mOp | mXb | mQ | mSf) -#define OpXbX6(a,b,c) \ - (bOp (a) | bXb (b) | bX6 (c)), (mOp | mXb | mX6) -#define OpXbX6Y(a,b,c,d) \ - (bOp (a) | bXb (b) | bX6 (c) | bY (d)), (mOp | mXb | mX6 | mY) -#define OpXbX6F2(a,b,c,d) \ - (bOp (a) | bXb (b) | bX6 (c) | bF2 (d)), (mOp | mXb | mX6 | mF2) -#define OpXbX6Sf(a,b,c,d) \ - (bOp (a) | bXb (b) | bX6 (c) | bSf (d)), (mOp | mXb | mX6 | mSf) - -/* Used to initialise unused fields in ia64_opcode struct, - in order to stop gcc from complaining. */ -#define EMPTY 0,0,NULL - -struct ia64_opcode ia64_opcodes_f[] =3D - { - /* F-type instruction encodings (sorted according to major opcode). */ - - {"frcpa.s0", f2, OpXbQSf (0, 1, 0, 0), {F1, P2, F2, F3}, EMPTY}, - {"frcpa", f2, OpXbQSf (0, 1, 0, 0), {F1, P2, F2, F3}, PSEUDO, 0, NULL= }, - {"frcpa.s1", f2, OpXbQSf (0, 1, 0, 1), {F1, P2, F2, F3}, EMPTY}, - {"frcpa.s2", f2, OpXbQSf (0, 1, 0, 2), {F1, P2, F2, F3}, EMPTY}, - {"frcpa.s3", f2, OpXbQSf (0, 1, 0, 3), {F1, P2, F2, F3}, EMPTY}, - - {"frsqrta.s0", f2, OpXbQSf (0, 1, 1, 0), {F1, P2, F3}, EMPTY}, - {"frsqrta", f2, OpXbQSf (0, 1, 1, 0), {F1, P2, F3}, PSEUDO, 0, NULL}, - {"frsqrta.s1", f2, OpXbQSf (0, 1, 1, 1), {F1, P2, F3}, EMPTY}, - {"frsqrta.s2", f2, OpXbQSf (0, 1, 1, 2), {F1, P2, F3}, EMPTY}, - {"frsqrta.s3", f2, OpXbQSf (0, 1, 1, 3), {F1, P2, F3}, EMPTY}, - - {"fmin.s0", f, OpXbX6Sf (0, 0, 0x14, 0), {F1, F2, F3}, EMPTY}, - {"fmin", f, OpXbX6Sf (0, 0, 0x14, 0), {F1, F2, F3}, PSEUDO, 0, NULL}, - {"fmin.s1", f, OpXbX6Sf (0, 0, 0x14, 1), {F1, F2, F3}, EMPTY}, - {"fmin.s2", f, OpXbX6Sf (0, 0, 0x14, 2), {F1, F2, F3}, EMPTY}, - {"fmin.s3", f, OpXbX6Sf (0, 0, 0x14, 3), {F1, F2, F3}, EMPTY}, - {"fmax.s0", f, OpXbX6Sf (0, 0, 0x15, 0), {F1, F2, F3}, EMPTY}, - {"fmax", f, OpXbX6Sf (0, 0, 0x15, 0), {F1, F2, F3}, PSEUDO, 0, NULL}, - {"fmax.s1", f, OpXbX6Sf (0, 0, 0x15, 1), {F1, F2, F3}, EMPTY}, - {"fmax.s2", f, OpXbX6Sf (0, 0, 0x15, 2), {F1, F2, F3}, EMPTY}, - {"fmax.s3", f, OpXbX6Sf (0, 0, 0x15, 3), {F1, F2, F3}, EMPTY}, - {"famin.s0", f, OpXbX6Sf (0, 0, 0x16, 0), {F1, F2, F3}, EMPTY}, - {"famin", f, OpXbX6Sf (0, 0, 0x16, 0), {F1, F2, F3}, PSEUDO, 0, NULL}, - {"famin.s1", f, OpXbX6Sf (0, 0, 0x16, 1), {F1, F2, F3}, EMPTY}, - {"famin.s2", f, OpXbX6Sf (0, 0, 0x16, 2), {F1, F2, F3}, EMPTY}, - {"famin.s3", f, OpXbX6Sf (0, 0, 0x16, 3), {F1, F2, F3}, EMPTY}, - {"famax.s0", f, OpXbX6Sf (0, 0, 0x17, 0), {F1, F2, F3}, EMPTY}, - {"famax", f, OpXbX6Sf (0, 0, 0x17, 0), {F1, F2, F3}, PSEUDO, 0, NULL}, - {"famax.s1", f, OpXbX6Sf (0, 0, 0x17, 1), {F1, F2, F3}, EMPTY}, - {"famax.s2", f, OpXbX6Sf (0, 0, 0x17, 2), {F1, F2, F3}, EMPTY}, - {"famax.s3", f, OpXbX6Sf (0, 0, 0x17, 3), {F1, F2, F3}, EMPTY}, - - {"mov", f, OpXbX6 (0, 0, 0x10), {F1, F3}, PSEUDO | F2_EQ_F3, 0, NULL}, - {"fabs", f, OpXbX6F2 (0, 0, 0x10, 0), {F1, F3}, PSEUDO, 0, NULL}, - {"fneg", f, OpXbX6 (0, 0, 0x11), {F1, F3}, PSEUDO | F2_EQ_F3, 0, NU= LL}, - {"fnegabs", f, OpXbX6F2 (0, 0, 0x11, 0), {F1, F3}, PSEUDO, 0, NULL}, - {"fmerge.s", f, OpXbX6 (0, 0, 0x10), {F1, F2, F3}, EMPTY}, - {"fmerge.ns", f, OpXbX6 (0, 0, 0x11), {F1, F2, F3}, EMPTY}, - - {"fmerge.se", f, OpXbX6 (0, 0, 0x12), {F1, F2, F3}, EMPTY}, - {"fmix.lr", f, OpXbX6 (0, 0, 0x39), {F1, F2, F3}, EMPTY}, - {"fmix.r", f, OpXbX6 (0, 0, 0x3a), {F1, F2, F3}, EMPTY}, - {"fmix.l", f, OpXbX6 (0, 0, 0x3b), {F1, F2, F3}, EMPTY}, - {"fsxt.r", f, OpXbX6 (0, 0, 0x3c), {F1, F2, F3}, EMPTY}, - {"fsxt.l", f, OpXbX6 (0, 0, 0x3d), {F1, F2, F3}, EMPTY}, - {"fpack", f, OpXbX6 (0, 0, 0x28), {F1, F2, F3}, EMPTY}, - {"fswap", f, OpXbX6 (0, 0, 0x34), {F1, F2, F3}, EMPTY}, - {"fswap.nl", f, OpXbX6 (0, 0, 0x35), {F1, F2, F3}, EMPTY}, - {"fswap.nr", f, OpXbX6 (0, 0, 0x36), {F1, F2, F3}, EMPTY}, - {"fand", f, OpXbX6 (0, 0, 0x2c), {F1, F2, F3}, EMPTY}, - {"fandcm", f, OpXbX6 (0, 0, 0x2d), {F1, F2, F3}, EMPTY}, - {"for", f, OpXbX6 (0, 0, 0x2e), {F1, F2, F3}, EMPTY}, - {"fxor", f, OpXbX6 (0, 0, 0x2f), {F1, F2, F3}, EMPTY}, - - {"fcvt.fx.s0", f, OpXbX6Sf (0, 0, 0x18, 0), {F1, F2}, EMPTY}, - {"fcvt.fx", f, OpXbX6Sf (0, 0, 0x18, 0), {F1, F2}, PSEUDO, 0, NULL}, - {"fcvt.fx.s1", f, OpXbX6Sf (0, 0, 0x18, 1), {F1, F2}, EMPTY}, - {"fcvt.fx.s2", f, OpXbX6Sf (0, 0, 0x18, 2), {F1, F2}, EMPTY}, - {"fcvt.fx.s3", f, OpXbX6Sf (0, 0, 0x18, 3), {F1, F2}, EMPTY}, - {"fcvt.fxu.s0", f, OpXbX6Sf (0, 0, 0x19, 0), {F1, F2}, EMPTY}, - {"fcvt.fxu", f, OpXbX6Sf (0, 0, 0x19, 0), {F1, F2}, PSEUDO, 0, NULL}, - {"fcvt.fxu.s1", f, OpXbX6Sf (0, 0, 0x19, 1), {F1, F2}, EMPTY}, - {"fcvt.fxu.s2", f, OpXbX6Sf (0, 0, 0x19, 2), {F1, F2}, EMPTY}, - {"fcvt.fxu.s3", f, OpXbX6Sf (0, 0, 0x19, 3), {F1, F2}, EMPTY}, - {"fcvt.fx.trunc.s0", f, OpXbX6Sf (0, 0, 0x1a, 0), {F1, F2}, EMPTY}, - {"fcvt.fx.trunc", f, OpXbX6Sf (0, 0, 0x1a, 0), {F1, F2}, PSEUDO, 0, N= ULL}, - {"fcvt.fx.trunc.s1", f, OpXbX6Sf (0, 0, 0x1a, 1), {F1, F2}, EMPTY}, - {"fcvt.fx.trunc.s2", f, OpXbX6Sf (0, 0, 0x1a, 2), {F1, F2}, EMPTY}, - {"fcvt.fx.trunc.s3", f, OpXbX6Sf (0, 0, 0x1a, 3), {F1, F2}, EMPTY}, - {"fcvt.fxu.trunc.s0", f, OpXbX6Sf (0, 0, 0x1b, 0), {F1, F2}, EMPTY}, - {"fcvt.fxu.trunc", f, OpXbX6Sf (0, 0, 0x1b, 0), {F1, F2}, PSEUDO, 0, = NULL}, - {"fcvt.fxu.trunc.s1", f, OpXbX6Sf (0, 0, 0x1b, 1), {F1, F2}, EMPTY}, - {"fcvt.fxu.trunc.s2", f, OpXbX6Sf (0, 0, 0x1b, 2), {F1, F2}, EMPTY}, - {"fcvt.fxu.trunc.s3", f, OpXbX6Sf (0, 0, 0x1b, 3), {F1, F2}, EMPTY}, - - {"fcvt.xf", f, OpXbX6 (0, 0, 0x1c), {F1, F2}, EMPTY}, - - {"fsetc.s0", f0, OpXbX6Sf (0, 0, 0x04, 0), {IMMU7a, IMMU7b}, EMPTY}, - {"fsetc", f0, OpXbX6Sf (0, 0, 0x04, 0), {IMMU7a, IMMU7b}, PSEUDO, 0, = NULL}, - {"fsetc.s1", f0, OpXbX6Sf (0, 0, 0x04, 1), {IMMU7a, IMMU7b}, EMPTY}, - {"fsetc.s2", f0, OpXbX6Sf (0, 0, 0x04, 2), {IMMU7a, IMMU7b}, EMPTY}, - {"fsetc.s3", f0, OpXbX6Sf (0, 0, 0x04, 3), {IMMU7a, IMMU7b}, EMPTY}, - {"fclrf.s0", f0, OpXbX6Sf (0, 0, 0x05, 0), {}, EMPTY}, - {"fclrf", f0, OpXbX6Sf (0, 0, 0x05, 0), {0}, PSEUDO, 0, NULL}, - {"fclrf.s1", f0, OpXbX6Sf (0, 0, 0x05, 1), {}, EMPTY}, - {"fclrf.s2", f0, OpXbX6Sf (0, 0, 0x05, 2), {}, EMPTY}, - {"fclrf.s3", f0, OpXbX6Sf (0, 0, 0x05, 3), {}, EMPTY}, - {"fchkf.s0", f0, OpXbX6Sf (0, 0, 0x08, 0), {TGT25}, EMPTY}, - {"fchkf", f0, OpXbX6Sf (0, 0, 0x08, 0), {TGT25}, PSEUDO, 0, NULL}, - {"fchkf.s1", f0, OpXbX6Sf (0, 0, 0x08, 1), {TGT25}, EMPTY}, - {"fchkf.s2", f0, OpXbX6Sf (0, 0, 0x08, 2), {TGT25}, EMPTY}, - {"fchkf.s3", f0, OpXbX6Sf (0, 0, 0x08, 3), {TGT25}, EMPTY}, - - {"break.f", f0, OpXbX6 (0, 0, 0x00), {IMMU21}, EMPTY}, - {"nop.f", f0, OpXbX6Y (0, 0, 0x01, 0), {IMMU21}, EMPTY}, - {"hint.f", f0, OpXbX6Y (0, 0, 0x01, 1), {IMMU21}, EMPTY}, - - {"fprcpa.s0", f2, OpXbQSf (1, 1, 0, 0), {F1, P2, F2, F3}, EMPTY}, - {"fprcpa", f2, OpXbQSf (1, 1, 0, 0), {F1, P2, F2, F3}, PSEUDO, 0, NUL= L}, - {"fprcpa.s1", f2, OpXbQSf (1, 1, 0, 1), {F1, P2, F2, F3}, EMPTY}, - {"fprcpa.s2", f2, OpXbQSf (1, 1, 0, 2), {F1, P2, F2, F3}, EMPTY}, - {"fprcpa.s3", f2, OpXbQSf (1, 1, 0, 3), {F1, P2, F2, F3}, EMPTY}, - - {"fprsqrta.s0", f2, OpXbQSf (1, 1, 1, 0), {F1, P2, F3}, EMPTY}, - {"fprsqrta", f2, OpXbQSf (1, 1, 1, 0), {F1, P2, F3}, PSEUDO, 0, NULL}, - {"fprsqrta.s1", f2, OpXbQSf (1, 1, 1, 1), {F1, P2, F3}, EMPTY}, - {"fprsqrta.s2", f2, OpXbQSf (1, 1, 1, 2), {F1, P2, F3}, EMPTY}, - {"fprsqrta.s3", f2, OpXbQSf (1, 1, 1, 3), {F1, P2, F3}, EMPTY}, - - {"fpmin.s0", f, OpXbX6Sf (1, 0, 0x14, 0), {F1, F2, F3}, EMPTY}, - {"fpmin", f, OpXbX6Sf (1, 0, 0x14, 0), {F1, F2, F3}, PSEUDO, 0, NULL}, - {"fpmin.s1", f, OpXbX6Sf (1, 0, 0x14, 1), {F1, F2, F3}, EMPTY}, - {"fpmin.s2", f, OpXbX6Sf (1, 0, 0x14, 2), {F1, F2, F3}, EMPTY}, - {"fpmin.s3", f, OpXbX6Sf (1, 0, 0x14, 3), {F1, F2, F3}, EMPTY}, - {"fpmax.s0", f, OpXbX6Sf (1, 0, 0x15, 0), {F1, F2, F3}, EMPTY}, - {"fpmax", f, OpXbX6Sf (1, 0, 0x15, 0), {F1, F2, F3}, PSEUDO, 0, NULL}, - {"fpmax.s1", f, OpXbX6Sf (1, 0, 0x15, 1), {F1, F2, F3}, EMPTY}, - {"fpmax.s2", f, OpXbX6Sf (1, 0, 0x15, 2), {F1, F2, F3}, EMPTY}, - {"fpmax.s3", f, OpXbX6Sf (1, 0, 0x15, 3), {F1, F2, F3}, EMPTY}, - {"fpamin.s0", f, OpXbX6Sf (1, 0, 0x16, 0), {F1, F2, F3}, EMPTY}, - {"fpamin", f, OpXbX6Sf (1, 0, 0x16, 0), {F1, F2, F3}, PSEUDO, 0, NULL= }, - {"fpamin.s1", f, OpXbX6Sf (1, 0, 0x16, 1), {F1, F2, F3}, EMPTY}, - {"fpamin.s2", f, OpXbX6Sf (1, 0, 0x16, 2), {F1, F2, F3}, EMPTY}, - {"fpamin.s3", f, OpXbX6Sf (1, 0, 0x16, 3), {F1, F2, F3}, EMPTY}, - {"fpamax.s0", f, OpXbX6Sf (1, 0, 0x17, 0), {F1, F2, F3}, EMPTY}, - {"fpamax", f, OpXbX6Sf (1, 0, 0x17, 0), {F1, F2, F3}, PSEUDO, 0, NULL= }, - {"fpamax.s1", f, OpXbX6Sf (1, 0, 0x17, 1), {F1, F2, F3}, EMPTY}, - {"fpamax.s2", f, OpXbX6Sf (1, 0, 0x17, 2), {F1, F2, F3}, EMPTY}, - {"fpamax.s3", f, OpXbX6Sf (1, 0, 0x17, 3), {F1, F2, F3}, EMPTY}, - - {"fpcmp.eq.s0", f, OpXbX6Sf (1, 0, 0x30, 0), {F1, F2, F3}, EMPTY}, - {"fpcmp.eq", f, OpXbX6Sf (1, 0, 0x30, 0), {F1, F2, F3}, PSEUDO, 0, NUL= L}, - {"fpcmp.eq.s1", f, OpXbX6Sf (1, 0, 0x30, 1), {F1, F2, F3}, EMPTY}, - {"fpcmp.eq.s2", f, OpXbX6Sf (1, 0, 0x30, 2), {F1, F2, F3}, EMPTY}, - {"fpcmp.eq.s3", f, OpXbX6Sf (1, 0, 0x30, 3), {F1, F2, F3}, EMPTY}, - {"fpcmp.lt.s0", f, OpXbX6Sf (1, 0, 0x31, 0), {F1, F2, F3}, EMPTY}, - {"fpcmp.lt", f, OpXbX6Sf (1, 0, 0x31, 0), {F1, F2, F3}, PSEUDO, 0, NUL= L}, - {"fpcmp.lt.s1", f, OpXbX6Sf (1, 0, 0x31, 1), {F1, F2, F3}, EMPTY}, - {"fpcmp.lt.s2", f, OpXbX6Sf (1, 0, 0x31, 2), {F1, F2, F3}, EMPTY}, - {"fpcmp.lt.s3", f, OpXbX6Sf (1, 0, 0x31, 3), {F1, F2, F3}, EMPTY}, - {"fpcmp.le.s0", f, OpXbX6Sf (1, 0, 0x32, 0), {F1, F2, F3}, EMPTY}, - {"fpcmp.le", f, OpXbX6Sf (1, 0, 0x32, 0), {F1, F2, F3}, PSEUDO, 0, NUL= L}, - {"fpcmp.le.s1", f, OpXbX6Sf (1, 0, 0x32, 1), {F1, F2, F3}, EMPTY}, - {"fpcmp.le.s2", f, OpXbX6Sf (1, 0, 0x32, 2), {F1, F2, F3}, EMPTY}, - {"fpcmp.le.s3", f, OpXbX6Sf (1, 0, 0x32, 3), {F1, F2, F3}, EMPTY}, - {"fpcmp.gt.s0", f, OpXbX6Sf (1, 0, 0x31, 0), {F1, F3, F2}, PSEUDO, 0, = NULL}, - {"fpcmp.gt", f, OpXbX6Sf (1, 0, 0x31, 0), {F1, F3, F2}, PSEUDO, 0, NUL= L}, - {"fpcmp.gt.s1", f, OpXbX6Sf (1, 0, 0x31, 1), {F1, F3, F2}, PSEUDO, 0, = NULL}, - {"fpcmp.gt.s2", f, OpXbX6Sf (1, 0, 0x31, 2), {F1, F3, F2}, PSEUDO, 0, = NULL}, - {"fpcmp.gt.s3", f, OpXbX6Sf (1, 0, 0x31, 3), {F1, F3, F2}, PSEUDO, 0, = NULL}, - {"fpcmp.ge.s0", f, OpXbX6Sf (1, 0, 0x32, 0), {F1, F3, F2}, PSEUDO, 0, = NULL}, - {"fpcmp.ge", f, OpXbX6Sf (1, 0, 0x32, 0), {F1, F3, F2}, PSEUDO, 0, NUL= L}, - {"fpcmp.ge.s1", f, OpXbX6Sf (1, 0, 0x32, 1), {F1, F3, F2}, PSEUDO, 0, = NULL}, - {"fpcmp.ge.s2", f, OpXbX6Sf (1, 0, 0x32, 2), {F1, F3, F2}, PSEUDO, 0, = NULL}, - {"fpcmp.ge.s3", f, OpXbX6Sf (1, 0, 0x32, 3), {F1, F3, F2}, PSEUDO, 0, = NULL}, - {"fpcmp.unord.s0", f, OpXbX6Sf (1, 0, 0x33, 0), {F1, F2, F3}, EMPTY}, - {"fpcmp.unord", f, OpXbX6Sf (1, 0, 0x33, 0), {F1, F2, F3}, PSEUDO, 0, = NULL}, - {"fpcmp.unord.s1", f, OpXbX6Sf (1, 0, 0x33, 1), {F1, F2, F3}, EMPTY}, - {"fpcmp.unord.s2", f, OpXbX6Sf (1, 0, 0x33, 2), {F1, F2, F3}, EMPTY}, - {"fpcmp.unord.s3", f, OpXbX6Sf (1, 0, 0x33, 3), {F1, F2, F3}, EMPTY}, - {"fpcmp.neq.s0", f, OpXbX6Sf (1, 0, 0x34, 0), {F1, F2, F3}, EMPTY}, - {"fpcmp.neq", f, OpXbX6Sf (1, 0, 0x34, 0), {F1, F2, F3}, PSEUDO, 0, NU= LL}, - {"fpcmp.neq.s1", f, OpXbX6Sf (1, 0, 0x34, 1), {F1, F2, F3}, EMPTY}, - {"fpcmp.neq.s2", f, OpXbX6Sf (1, 0, 0x34, 2), {F1, F2, F3}, EMPTY}, - {"fpcmp.neq.s3", f, OpXbX6Sf (1, 0, 0x34, 3), {F1, F2, F3}, EMPTY}, - {"fpcmp.nlt.s0", f, OpXbX6Sf (1, 0, 0x35, 0), {F1, F2, F3}, EMPTY}, - {"fpcmp.nlt", f, OpXbX6Sf (1, 0, 0x35, 0), {F1, F2, F3}, PSEUDO, 0, NU= LL}, - {"fpcmp.nlt.s1", f, OpXbX6Sf (1, 0, 0x35, 1), {F1, F2, F3}, EMPTY}, - {"fpcmp.nlt.s2", f, OpXbX6Sf (1, 0, 0x35, 2), {F1, F2, F3}, EMPTY}, - {"fpcmp.nlt.s3", f, OpXbX6Sf (1, 0, 0x35, 3), {F1, F2, F3}, EMPTY}, - {"fpcmp.nle.s0", f, OpXbX6Sf (1, 0, 0x36, 0), {F1, F2, F3}, EMPTY}, - {"fpcmp.nle", f, OpXbX6Sf (1, 0, 0x36, 0), {F1, F2, F3}, PSEUDO, 0, NU= LL}, - {"fpcmp.nle.s1", f, OpXbX6Sf (1, 0, 0x36, 1), {F1, F2, F3}, EMPTY}, - {"fpcmp.nle.s2", f, OpXbX6Sf (1, 0, 0x36, 2), {F1, F2, F3}, EMPTY}, - {"fpcmp.nle.s3", f, OpXbX6Sf (1, 0, 0x36, 3), {F1, F2, F3}, EMPTY}, - {"fpcmp.ngt.s0", f, OpXbX6Sf (1, 0, 0x35, 0), {F1, F3, F2}, PSEUDO, 0,= NULL}, - {"fpcmp.ngt", f, OpXbX6Sf (1, 0, 0x35, 0), {F1, F3, F2}, PSEUDO, 0, NU= LL}, - {"fpcmp.ngt.s1", f, OpXbX6Sf (1, 0, 0x35, 1), {F1, F3, F2}, PSEUDO, 0,= NULL}, - {"fpcmp.ngt.s2", f, OpXbX6Sf (1, 0, 0x35, 2), {F1, F3, F2}, PSEUDO, 0,= NULL}, - {"fpcmp.ngt.s3", f, OpXbX6Sf (1, 0, 0x35, 3), {F1, F3, F2}, PSEUDO, 0,= NULL}, - {"fpcmp.nge.s0", f, OpXbX6Sf (1, 0, 0x36, 0), {F1, F3, F2}, PSEUDO, 0,= NULL}, - {"fpcmp.nge", f, OpXbX6Sf (1, 0, 0x36, 0), {F1, F3, F2}, PSEUDO, 0, NU= LL}, - {"fpcmp.nge.s1", f, OpXbX6Sf (1, 0, 0x36, 1), {F1, F3, F2}, PSEUDO, 0,= NULL}, - {"fpcmp.nge.s2", f, OpXbX6Sf (1, 0, 0x36, 2), {F1, F3, F2}, PSEUDO, 0,= NULL}, - {"fpcmp.nge.s3", f, OpXbX6Sf (1, 0, 0x36, 3), {F1, F3, F2}, PSEUDO, 0,= NULL}, - {"fpcmp.ord.s0", f, OpXbX6Sf (1, 0, 0x37, 0), {F1, F2, F3}, EMPTY}, - {"fpcmp.ord", f, OpXbX6Sf (1, 0, 0x37, 0), {F1, F2, F3}, PSEUDO, 0, NU= LL}, - {"fpcmp.ord.s1", f, OpXbX6Sf (1, 0, 0x37, 1), {F1, F2, F3}, EMPTY}, - {"fpcmp.ord.s2", f, OpXbX6Sf (1, 0, 0x37, 2), {F1, F2, F3}, EMPTY}, - {"fpcmp.ord.s3", f, OpXbX6Sf (1, 0, 0x37, 3), {F1, F2, F3}, EMPTY}, - - {"fpabs", f, OpXbX6F2 (1, 0, 0x10, 0), {F1, F3}, PSEUDO, 0, NULL}, - {"fpneg", f, OpXbX6 (1, 0, 0x11), {F1, F3}, PSEUDO | F2_EQ_F3, 0, N= ULL}, - {"fpnegabs", f, OpXbX6F2 (1, 0, 0x11, 0), {F1, F3}, PSEUDO, 0, NULL}, - {"fpmerge.s", f, OpXbX6 (1, 0, 0x10), {F1, F2, F3}, EMPTY}, - {"fpmerge.ns", f, OpXbX6 (1, 0, 0x11), {F1, F2, F3}, EMPTY}, - {"fpmerge.se", f, OpXbX6 (1, 0, 0x12), {F1, F2, F3}, EMPTY}, - - {"fpcvt.fx.s0", f, OpXbX6Sf (1, 0, 0x18, 0), {F1, F2}, EMPTY}, - {"fpcvt.fx", f, OpXbX6Sf (1, 0, 0x18, 0), {F1, F2}, PSEUDO, 0, NULL}, - {"fpcvt.fx.s1", f, OpXbX6Sf (1, 0, 0x18, 1), {F1, F2}, EMPTY}, - {"fpcvt.fx.s2", f, OpXbX6Sf (1, 0, 0x18, 2), {F1, F2}, EMPTY}, - {"fpcvt.fx.s3", f, OpXbX6Sf (1, 0, 0x18, 3), {F1, F2}, EMPTY}, - {"fpcvt.fxu.s0", f, OpXbX6Sf (1, 0, 0x19, 0), {F1, F2}, EMPTY}, - {"fpcvt.fxu", f, OpXbX6Sf (1, 0, 0x19, 0), {F1, F2}, PSEUDO, 0, NULL}, - {"fpcvt.fxu.s1", f, OpXbX6Sf (1, 0, 0x19, 1), {F1, F2}, EMPTY}, - {"fpcvt.fxu.s2", f, OpXbX6Sf (1, 0, 0x19, 2), {F1, F2}, EMPTY}, - {"fpcvt.fxu.s3", f, OpXbX6Sf (1, 0, 0x19, 3), {F1, F2}, EMPTY}, - {"fpcvt.fx.trunc.s0", f, OpXbX6Sf (1, 0, 0x1a, 0), {F1, F2}, EMPTY}, - {"fpcvt.fx.trunc", f, OpXbX6Sf (1, 0, 0x1a, 0), {F1, F2}, PSEUDO, 0, = NULL}, - {"fpcvt.fx.trunc.s1", f, OpXbX6Sf (1, 0, 0x1a, 1), {F1, F2}, EMPTY}, - {"fpcvt.fx.trunc.s2", f, OpXbX6Sf (1, 0, 0x1a, 2), {F1, F2}, EMPTY}, - {"fpcvt.fx.trunc.s3", f, OpXbX6Sf (1, 0, 0x1a, 3), {F1, F2}, EMPTY}, - {"fpcvt.fxu.trunc.s0", f, OpXbX6Sf (1, 0, 0x1b, 0), {F1, F2}, EMPTY}, - {"fpcvt.fxu.trunc", f, OpXbX6Sf (1, 0, 0x1b, 0), {F1, F2}, PSEUDO, 0,= NULL}, - {"fpcvt.fxu.trunc.s1", f, OpXbX6Sf (1, 0, 0x1b, 1), {F1, F2}, EMPTY}, - {"fpcvt.fxu.trunc.s2", f, OpXbX6Sf (1, 0, 0x1b, 2), {F1, F2}, EMPTY}, - {"fpcvt.fxu.trunc.s3", f, OpXbX6Sf (1, 0, 0x1b, 3), {F1, F2}, EMPTY}, - - {"fcmp.eq.s0", f2, OpRaRbTaSf (4, 0, 0, 0, 0), {P1, P2, F2, F3}, EMP= TY}, - {"fcmp.eq", f2, OpRaRbTaSf (4, 0, 0, 0, 0), {P1, P2, F2, F3}, PSEUD= O, 0, NULL}, - {"fcmp.eq.s1", f2, OpRaRbTaSf (4, 0, 0, 0, 1), {P1, P2, F2, F3}, EMP= TY}, - {"fcmp.eq.s2", f2, OpRaRbTaSf (4, 0, 0, 0, 2), {P1, P2, F2, F3}, EMP= TY}, - {"fcmp.eq.s3", f2, OpRaRbTaSf (4, 0, 0, 0, 3), {P1, P2, F2, F3}, EMP= TY}, - {"fcmp.lt.s0", f2, OpRaRbTaSf (4, 0, 1, 0, 0), {P1, P2, F2, F3}, EMP= TY}, - {"fcmp.lt", f2, OpRaRbTaSf (4, 0, 1, 0, 0), {P1, P2, F2, F3}, PSEUD= O, 0, NULL}, - {"fcmp.lt.s1", f2, OpRaRbTaSf (4, 0, 1, 0, 1), {P1, P2, F2, F3}, EMP= TY}, - {"fcmp.lt.s2", f2, OpRaRbTaSf (4, 0, 1, 0, 2), {P1, P2, F2, F3}, EMP= TY}, - {"fcmp.lt.s3", f2, OpRaRbTaSf (4, 0, 1, 0, 3), {P1, P2, F2, F3}, EMP= TY}, - {"fcmp.le.s0", f2, OpRaRbTaSf (4, 1, 0, 0, 0), {P1, P2, F2, F3}, EMP= TY}, - {"fcmp.le", f2, OpRaRbTaSf (4, 1, 0, 0, 0), {P1, P2, F2, F3}, PSEUD= O, 0, NULL}, - {"fcmp.le.s1", f2, OpRaRbTaSf (4, 1, 0, 0, 1), {P1, P2, F2, F3}, EMP= TY}, - {"fcmp.le.s2", f2, OpRaRbTaSf (4, 1, 0, 0, 2), {P1, P2, F2, F3}, EMP= TY}, - {"fcmp.le.s3", f2, OpRaRbTaSf (4, 1, 0, 0, 3), {P1, P2, F2, F3}, EMP= TY}, - {"fcmp.unord.s0", f2, OpRaRbTaSf (4, 1, 1, 0, 0), {P1, P2, F2, F3}, = EMPTY}, - {"fcmp.unord", f2, OpRaRbTaSf (4, 1, 1, 0, 0), {P1, P2, F2, F3}, PSE= UDO, 0, NULL}, - {"fcmp.unord.s1", f2, OpRaRbTaSf (4, 1, 1, 0, 1), {P1, P2, F2, F3}, = EMPTY}, - {"fcmp.unord.s2", f2, OpRaRbTaSf (4, 1, 1, 0, 2), {P1, P2, F2, F3}, = EMPTY}, - {"fcmp.unord.s3", f2, OpRaRbTaSf (4, 1, 1, 0, 3), {P1, P2, F2, F3}, = EMPTY}, - {"fcmp.eq.unc.s0", f2, OpRaRbTaSf (4, 0, 0, 1, 0), {P1, P2, F2, F3},= EMPTY}, - {"fcmp.eq.unc", f2, OpRaRbTaSf (4, 0, 0, 1, 0), {P1, P2, F2, F3}, PS= EUDO, 0, NULL}, - {"fcmp.eq.unc.s1", f2, OpRaRbTaSf (4, 0, 0, 1, 1), {P1, P2, F2, F3},= EMPTY}, - {"fcmp.eq.unc.s2", f2, OpRaRbTaSf (4, 0, 0, 1, 2), {P1, P2, F2, F3},= EMPTY}, - {"fcmp.eq.unc.s3", f2, OpRaRbTaSf (4, 0, 0, 1, 3), {P1, P2, F2, F3},= EMPTY}, - {"fcmp.lt.unc.s0", f2, OpRaRbTaSf (4, 0, 1, 1, 0), {P1, P2, F2, F3},= EMPTY}, - {"fcmp.lt.unc", f2, OpRaRbTaSf (4, 0, 1, 1, 0), {P1, P2, F2, F3}, PS= EUDO, 0, NULL}, - {"fcmp.lt.unc.s1", f2, OpRaRbTaSf (4, 0, 1, 1, 1), {P1, P2, F2, F3},= EMPTY}, - {"fcmp.lt.unc.s2", f2, OpRaRbTaSf (4, 0, 1, 1, 2), {P1, P2, F2, F3},= EMPTY}, - {"fcmp.lt.unc.s3", f2, OpRaRbTaSf (4, 0, 1, 1, 3), {P1, P2, F2, F3},= EMPTY}, - {"fcmp.le.unc.s0", f2, OpRaRbTaSf (4, 1, 0, 1, 0), {P1, P2, F2, F3},= EMPTY}, - {"fcmp.le.unc", f2, OpRaRbTaSf (4, 1, 0, 1, 0), {P1, P2, F2, F3}, PS= EUDO, 0, NULL}, - {"fcmp.le.unc.s1", f2, OpRaRbTaSf (4, 1, 0, 1, 1), {P1, P2, F2, F3},= EMPTY}, - {"fcmp.le.unc.s2", f2, OpRaRbTaSf (4, 1, 0, 1, 2), {P1, P2, F2, F3},= EMPTY}, - {"fcmp.le.unc.s3", f2, OpRaRbTaSf (4, 1, 0, 1, 3), {P1, P2, F2, F3},= EMPTY}, - {"fcmp.unord.unc.s0", f2, OpRaRbTaSf (4, 1, 1, 1, 0), {P1, P2, F2, F3}= , EMPTY}, - {"fcmp.unord.unc", f2, OpRaRbTaSf (4, 1, 1, 1, 0), {P1, P2, F2, F3}= , PSEUDO, 0, NULL}, - {"fcmp.unord.unc.s1", f2, OpRaRbTaSf (4, 1, 1, 1, 1), {P1, P2, F2, F3}= , EMPTY}, - {"fcmp.unord.unc.s2", f2, OpRaRbTaSf (4, 1, 1, 1, 2), {P1, P2, F2, F3}= , EMPTY}, - {"fcmp.unord.unc.s3", f2, OpRaRbTaSf (4, 1, 1, 1, 3), {P1, P2, F2, F3}= , EMPTY}, - - /* pseudo-ops of the above */ - {"fcmp.gt.s0", f2, OpRaRbTaSf (4, 0, 1, 0, 0), {P1, P2, F3, F2}, EMP= TY}, - {"fcmp.gt", f2, OpRaRbTaSf (4, 0, 1, 0, 0), {P1, P2, F3, F2}, PSEUD= O, 0, NULL}, - {"fcmp.gt.s1", f2, OpRaRbTaSf (4, 0, 1, 0, 1), {P1, P2, F3, F2}, EMP= TY}, - {"fcmp.gt.s2", f2, OpRaRbTaSf (4, 0, 1, 0, 2), {P1, P2, F3, F2}, EMP= TY}, - {"fcmp.gt.s3", f2, OpRaRbTaSf (4, 0, 1, 0, 3), {P1, P2, F3, F2}, EMP= TY}, - {"fcmp.ge.s0", f2, OpRaRbTaSf (4, 1, 0, 0, 0), {P1, P2, F3, F2}, EMP= TY}, - {"fcmp.ge", f2, OpRaRbTaSf (4, 1, 0, 0, 0), {P1, P2, F3, F2}, PSEUD= O, 0, NULL}, - {"fcmp.ge.s1", f2, OpRaRbTaSf (4, 1, 0, 0, 1), {P1, P2, F3, F2}, EMP= TY}, - {"fcmp.ge.s2", f2, OpRaRbTaSf (4, 1, 0, 0, 2), {P1, P2, F3, F2}, EMP= TY}, - {"fcmp.ge.s3", f2, OpRaRbTaSf (4, 1, 0, 0, 3), {P1, P2, F3, F2}, EMP= TY}, - {"fcmp.neq.s0", f2, OpRaRbTaSf (4, 0, 0, 0, 0), {P2, P1, F2, F3}, EM= PTY}, - {"fcmp.neq", f2, OpRaRbTaSf (4, 0, 0, 0, 0), {P2, P1, F2, F3}, PSEUD= O, 0, NULL}, - {"fcmp.neq.s1", f2, OpRaRbTaSf (4, 0, 0, 0, 1), {P2, P1, F2, F3}, EM= PTY}, - {"fcmp.neq.s2", f2, OpRaRbTaSf (4, 0, 0, 0, 2), {P2, P1, F2, F3}, EM= PTY}, - {"fcmp.neq.s3", f2, OpRaRbTaSf (4, 0, 0, 0, 3), {P2, P1, F2, F3}, EM= PTY}, - {"fcmp.nlt.s0", f2, OpRaRbTaSf (4, 0, 1, 0, 0), {P2, P1, F2, F3}, EM= PTY}, - {"fcmp.nlt", f2, OpRaRbTaSf (4, 0, 1, 0, 0), {P2, P1, F2, F3}, PSEUD= O, 0, NULL}, - {"fcmp.nlt.s1", f2, OpRaRbTaSf (4, 0, 1, 0, 1), {P2, P1, F2, F3}, EM= PTY}, - {"fcmp.nlt.s2", f2, OpRaRbTaSf (4, 0, 1, 0, 2), {P2, P1, F2, F3}, EM= PTY}, - {"fcmp.nlt.s3", f2, OpRaRbTaSf (4, 0, 1, 0, 3), {P2, P1, F2, F3}, EM= PTY}, - {"fcmp.nle.s0", f2, OpRaRbTaSf (4, 1, 0, 0, 0), {P2, P1, F2, F3}, EM= PTY}, - {"fcmp.nle", f2, OpRaRbTaSf (4, 1, 0, 0, 0), {P2, P1, F2, F3}, PSEUD= O, 0, NULL}, - {"fcmp.nle.s1", f2, OpRaRbTaSf (4, 1, 0, 0, 1), {P2, P1, F2, F3}, EM= PTY}, - {"fcmp.nle.s2", f2, OpRaRbTaSf (4, 1, 0, 0, 2), {P2, P1, F2, F3}, EM= PTY}, - {"fcmp.nle.s3", f2, OpRaRbTaSf (4, 1, 0, 0, 3), {P2, P1, F2, F3}, EM= PTY}, - {"fcmp.ngt.s0", f2, OpRaRbTaSf (4, 0, 1, 0, 0), {P2, P1, F3, F2}, EM= PTY}, - {"fcmp.ngt", f2, OpRaRbTaSf (4, 0, 1, 0, 0), {P2, P1, F3, F2}, PSEUD= O, 0, NULL}, - {"fcmp.ngt.s1", f2, OpRaRbTaSf (4, 0, 1, 0, 1), {P2, P1, F3, F2}, EM= PTY}, - {"fcmp.ngt.s2", f2, OpRaRbTaSf (4, 0, 1, 0, 2), {P2, P1, F3, F2}, EM= PTY}, - {"fcmp.ngt.s3", f2, OpRaRbTaSf (4, 0, 1, 0, 3), {P2, P1, F3, F2}, EM= PTY}, - {"fcmp.nge.s0", f2, OpRaRbTaSf (4, 1, 0, 0, 0), {P2, P1, F3, F2}, EM= PTY}, - {"fcmp.nge", f2, OpRaRbTaSf (4, 1, 0, 0, 0), {P2, P1, F3, F2}, PSEUD= O, 0, NULL}, - {"fcmp.nge.s1", f2, OpRaRbTaSf (4, 1, 0, 0, 1), {P2, P1, F3, F2}, EM= PTY}, - {"fcmp.nge.s2", f2, OpRaRbTaSf (4, 1, 0, 0, 2), {P2, P1, F3, F2}, EM= PTY}, - {"fcmp.nge.s3", f2, OpRaRbTaSf (4, 1, 0, 0, 3), {P2, P1, F3, F2}, EM= PTY}, - {"fcmp.ord.s0", f2, OpRaRbTaSf (4, 1, 1, 0, 0), {P2, P1, F2, F3}, EM= PTY}, - {"fcmp.ord", f2, OpRaRbTaSf (4, 1, 1, 0, 0), {P2, P1, F2, F3}, PSEUD= O, 0, NULL}, - {"fcmp.ord.s1", f2, OpRaRbTaSf (4, 1, 1, 0, 1), {P2, P1, F2, F3}, EM= PTY}, - {"fcmp.ord.s2", f2, OpRaRbTaSf (4, 1, 1, 0, 2), {P2, P1, F2, F3}, EM= PTY}, - {"fcmp.ord.s3", f2, OpRaRbTaSf (4, 1, 1, 0, 3), {P2, P1, F2, F3}, EM= PTY}, - {"fcmp.gt.unc.s0", f2, OpRaRbTaSf (4, 0, 1, 1, 0), {P1, P2, F3, F2},= EMPTY}, - {"fcmp.gt.unc", f2, OpRaRbTaSf (4, 0, 1, 1, 0), {P1, P2, F3, F2}, PS= EUDO, 0, NULL}, - {"fcmp.gt.unc.s1", f2, OpRaRbTaSf (4, 0, 1, 1, 1), {P1, P2, F3, F2},= EMPTY}, - {"fcmp.gt.unc.s2", f2, OpRaRbTaSf (4, 0, 1, 1, 2), {P1, P2, F3, F2},= EMPTY}, - {"fcmp.gt.unc.s3", f2, OpRaRbTaSf (4, 0, 1, 1, 3), {P1, P2, F3, F2},= EMPTY}, - {"fcmp.ge.unc.s0", f2, OpRaRbTaSf (4, 1, 0, 1, 0), {P1, P2, F3, F2},= EMPTY}, - {"fcmp.ge.unc", f2, OpRaRbTaSf (4, 1, 0, 1, 0), {P1, P2, F3, F2}, PS= EUDO, 0, NULL}, - {"fcmp.ge.unc.s1", f2, OpRaRbTaSf (4, 1, 0, 1, 1), {P1, P2, F3, F2},= EMPTY}, - {"fcmp.ge.unc.s2", f2, OpRaRbTaSf (4, 1, 0, 1, 2), {P1, P2, F3, F2},= EMPTY}, - {"fcmp.ge.unc.s3", f2, OpRaRbTaSf (4, 1, 0, 1, 3), {P1, P2, F3, F2},= EMPTY}, - {"fcmp.neq.unc.s0", f2, OpRaRbTaSf (4, 0, 0, 1, 0), {P2, P1, F2, F3}= , EMPTY}, - {"fcmp.neq.unc", f2, OpRaRbTaSf (4, 0, 0, 1, 0), {P2, P1, F2, F3}, P= SEUDO, 0, NULL}, - {"fcmp.neq.unc.s1", f2, OpRaRbTaSf (4, 0, 0, 1, 1), {P2, P1, F2, F3}= , EMPTY}, - {"fcmp.neq.unc.s2", f2, OpRaRbTaSf (4, 0, 0, 1, 2), {P2, P1, F2, F3}= , EMPTY}, - {"fcmp.neq.unc.s3", f2, OpRaRbTaSf (4, 0, 0, 1, 3), {P2, P1, F2, F3}= , EMPTY}, - {"fcmp.nlt.unc.s0", f2, OpRaRbTaSf (4, 0, 1, 1, 0), {P2, P1, F2, F3}= , EMPTY}, - {"fcmp.nlt.unc", f2, OpRaRbTaSf (4, 0, 1, 1, 0), {P2, P1, F2, F3}, P= SEUDO, 0, NULL}, - {"fcmp.nlt.unc.s1", f2, OpRaRbTaSf (4, 0, 1, 1, 1), {P2, P1, F2, F3}= , EMPTY}, - {"fcmp.nlt.unc.s2", f2, OpRaRbTaSf (4, 0, 1, 1, 2), {P2, P1, F2, F3}= , EMPTY}, - {"fcmp.nlt.unc.s3", f2, OpRaRbTaSf (4, 0, 1, 1, 3), {P2, P1, F2, F3}= , EMPTY}, - {"fcmp.nle.unc.s0", f2, OpRaRbTaSf (4, 1, 0, 1, 0), {P2, P1, F2, F3}= , EMPTY}, - {"fcmp.nle.unc", f2, OpRaRbTaSf (4, 1, 0, 1, 0), {P2, P1, F2, F3}, P= SEUDO, 0, NULL}, - {"fcmp.nle.unc.s1", f2, OpRaRbTaSf (4, 1, 0, 1, 1), {P2, P1, F2, F3}= , EMPTY}, - {"fcmp.nle.unc.s2", f2, OpRaRbTaSf (4, 1, 0, 1, 2), {P2, P1, F2, F3}= , EMPTY}, - {"fcmp.nle.unc.s3", f2, OpRaRbTaSf (4, 1, 0, 1, 3), {P2, P1, F2, F3}= , EMPTY}, - {"fcmp.ngt.unc.s0", f2, OpRaRbTaSf (4, 0, 1, 1, 0), {P2, P1, F3, F2}= , EMPTY}, - {"fcmp.ngt.unc", f2, OpRaRbTaSf (4, 0, 1, 1, 0), {P2, P1, F3, F2}, P= SEUDO, 0, NULL}, - {"fcmp.ngt.unc.s1", f2, OpRaRbTaSf (4, 0, 1, 1, 1), {P2, P1, F3, F2}= , EMPTY}, - {"fcmp.ngt.unc.s2", f2, OpRaRbTaSf (4, 0, 1, 1, 2), {P2, P1, F3, F2}= , EMPTY}, - {"fcmp.ngt.unc.s3", f2, OpRaRbTaSf (4, 0, 1, 1, 3), {P2, P1, F3, F2}= , EMPTY}, - {"fcmp.nge.unc.s0", f2, OpRaRbTaSf (4, 1, 0, 1, 0), {P2, P1, F3, F2}= , EMPTY}, - {"fcmp.nge.unc", f2, OpRaRbTaSf (4, 1, 0, 1, 0), {P2, P1, F3, F2}, P= SEUDO, 0, NULL}, - {"fcmp.nge.unc.s1", f2, OpRaRbTaSf (4, 1, 0, 1, 1), {P2, P1, F3, F2}= , EMPTY}, - {"fcmp.nge.unc.s2", f2, OpRaRbTaSf (4, 1, 0, 1, 2), {P2, P1, F3, F2}= , EMPTY}, - {"fcmp.nge.unc.s3", f2, OpRaRbTaSf (4, 1, 0, 1, 3), {P2, P1, F3, F2}= , EMPTY}, - {"fcmp.ord.unc.s0", f2, OpRaRbTaSf (4, 1, 1, 1, 0), {P2, P1, F2, F3}= , EMPTY}, - {"fcmp.ord.unc", f2, OpRaRbTaSf (4, 1, 1, 1, 0), {P2, P1, F2, F3}, P= SEUDO, 0, NULL}, - {"fcmp.ord.unc.s1", f2, OpRaRbTaSf (4, 1, 1, 1, 1), {P2, P1, F2, F3}= , EMPTY}, - {"fcmp.ord.unc.s2", f2, OpRaRbTaSf (4, 1, 1, 1, 2), {P2, P1, F2, F3}= , EMPTY}, - {"fcmp.ord.unc.s3", f2, OpRaRbTaSf (4, 1, 1, 1, 3), {P2, P1, F2, F3}= , EMPTY}, - - {"fclass.m", f2, OpTa (5, 0), {P1, P2, F2, IMMU9}, EMPTY}, - {"fclass.nm", f2, OpTa (5, 0), {P2, P1, F2, IMMU9}, PSEUDO, 0, NULL}, - {"fclass.m.unc", f2, OpTa (5, 1), {P1, P2, F2, IMMU9}, EMPTY}, - {"fclass.nm.unc", f2, OpTa (5, 1), {P2, P1, F2, IMMU9}, PSEUDO, 0, NUL= L}, - - /* note: fnorm and fcvt.xuf have identical encodings! */ - {"fnorm.s0", f, OpXaSfF2F4 (0x8, 0, 0, 0, 1), {F1, F3}, PSEUDO, 0, NUL= L}, - {"fnorm", f, OpXaSfF2F4 (0x8, 0, 0, 0, 1), {F1, F3}, PSEUDO, 0, NULL}, - {"fnorm.s1", f, OpXaSfF2F4 (0x8, 0, 1, 0, 1), {F1, F3}, PSEUDO, 0, NUL= L}, - {"fnorm.s2", f, OpXaSfF2F4 (0x8, 0, 2, 0, 1), {F1, F3}, PSEUDO, 0, NUL= L}, - {"fnorm.s3", f, OpXaSfF2F4 (0x8, 0, 3, 0, 1), {F1, F3}, PSEUDO, 0, NUL= L}, - {"fnorm.s.s0", f, OpXaSfF2F4 (0x8, 1, 0, 0, 1), {F1, F3}, PSEUDO, 0, N= ULL}, - {"fnorm.s", f, OpXaSfF2F4 (0x8, 1, 0, 0, 1), {F1, F3}, PSEUDO, 0, NUL= L}, - {"fnorm.s.s1", f, OpXaSfF2F4 (0x8, 1, 1, 0, 1), {F1, F3}, PSEUDO, 0, N= ULL}, - {"fnorm.s.s2", f, OpXaSfF2F4 (0x8, 1, 2, 0, 1), {F1, F3}, PSEUDO, 0, N= ULL}, - {"fnorm.s.s3", f, OpXaSfF2F4 (0x8, 1, 3, 0, 1), {F1, F3}, PSEUDO, 0, N= ULL}, - {"fcvt.xuf.s0", f, OpXaSfF2F4 (0x8, 0, 0, 0, 1), {F1, F3}, PSEUDO, 0, = NULL}, - {"fcvt.xuf", f, OpXaSfF2F4 (0x8, 0, 0, 0, 1), {F1, F3}, PSEUDO, 0, NUL= L}, - {"fcvt.xuf.s1", f, OpXaSfF2F4 (0x8, 0, 1, 0, 1), {F1, F3}, PSEUDO, 0, = NULL}, - {"fcvt.xuf.s2", f, OpXaSfF2F4 (0x8, 0, 2, 0, 1), {F1, F3}, PSEUDO, 0, = NULL}, - {"fcvt.xuf.s3", f, OpXaSfF2F4 (0x8, 0, 3, 0, 1), {F1, F3}, PSEUDO, 0, = NULL}, - {"fcvt.xuf.s.s0", f, OpXaSfF2F4 (0x8, 1, 0, 0, 1), {F1, F3}, PSEUDO, 0= , NULL}, - {"fcvt.xuf.s", f, OpXaSfF2F4 (0x8, 1, 0, 0, 1), {F1, F3}, PSEUDO, 0, N= ULL}, - {"fcvt.xuf.s.s1", f, OpXaSfF2F4 (0x8, 1, 1, 0, 1), {F1, F3}, PSEUDO, 0= , NULL}, - {"fcvt.xuf.s.s2", f, OpXaSfF2F4 (0x8, 1, 2, 0, 1), {F1, F3}, PSEUDO, 0= , NULL}, - {"fcvt.xuf.s.s3", f, OpXaSfF2F4 (0x8, 1, 3, 0, 1), {F1, F3}, PSEUDO, 0= , NULL}, - {"fadd.s0", f, OpXaSfF4 (0x8, 0, 0, 1), {F1, F3, F2}, PSEUDO, 0, NULL= }, - {"fadd", f, OpXaSfF4 (0x8, 0, 0, 1), {F1, F3, F2}, PSEUDO, 0, NULL}, - {"fadd.s1", f, OpXaSfF4 (0x8, 0, 1, 1), {F1, F3, F2}, PSEUDO, 0, NULL= }, - {"fadd.s2", f, OpXaSfF4 (0x8, 0, 2, 1), {F1, F3, F2}, PSEUDO, 0, NULL= }, - {"fadd.s3", f, OpXaSfF4 (0x8, 0, 3, 1), {F1, F3, F2}, PSEUDO, 0, NULL= }, - {"fadd.s.s0", f, OpXaSfF4 (0x8, 1, 0, 1), {F1, F3, F2}, PSEUDO, 0, NUL= L}, - {"fadd.s", f, OpXaSfF4 (0x8, 1, 0, 1), {F1, F3, F2}, PSEUDO, 0, NULL}, - {"fadd.s.s1", f, OpXaSfF4 (0x8, 1, 1, 1), {F1, F3, F2}, PSEUDO, 0, NUL= L}, - {"fadd.s.s2", f, OpXaSfF4 (0x8, 1, 2, 1), {F1, F3, F2}, PSEUDO, 0, NUL= L}, - {"fadd.s.s3", f, OpXaSfF4 (0x8, 1, 3, 1), {F1, F3, F2}, PSEUDO, 0, NUL= L}, - {"fmpy.s0", f, OpXaSfF2 (0x8, 0, 0, 0), {F1, F3, F4}, PSEUDO, 0, NULL= }, - {"fmpy", f, OpXaSfF2 (0x8, 0, 0, 0), {F1, F3, F4}, PSEUDO, 0, NULL}, - {"fmpy.s1", f, OpXaSfF2 (0x8, 0, 1, 0), {F1, F3, F4}, PSEUDO, 0, NULL= }, - {"fmpy.s2", f, OpXaSfF2 (0x8, 0, 2, 0), {F1, F3, F4}, PSEUDO, 0, NULL= }, - {"fmpy.s3", f, OpXaSfF2 (0x8, 0, 3, 0), {F1, F3, F4}, PSEUDO, 0, NULL= }, - {"fmpy.s.s0", f, OpXaSfF2 (0x8, 1, 0, 0), {F1, F3, F4}, PSEUDO, 0, NUL= L}, - {"fmpy.s", f, OpXaSfF2 (0x8, 1, 0, 0), {F1, F3, F4}, PSEUDO, 0, NULL}, - {"fmpy.s.s1", f, OpXaSfF2 (0x8, 1, 1, 0), {F1, F3, F4}, PSEUDO, 0, NUL= L}, - {"fmpy.s.s2", f, OpXaSfF2 (0x8, 1, 2, 0), {F1, F3, F4}, PSEUDO, 0, NUL= L}, - {"fmpy.s.s3", f, OpXaSfF2 (0x8, 1, 3, 0), {F1, F3, F4}, PSEUDO, 0, NUL= L}, - {"fma.s0", f, OpXaSf (0x8, 0, 0), {F1, F3, F4, F2}, EMPTY}, - {"fma", f, OpXaSf (0x8, 0, 0), {F1, F3, F4, F2}, PSEUDO, 0, NULL}, - {"fma.s1", f, OpXaSf (0x8, 0, 1), {F1, F3, F4, F2}, EMPTY}, - {"fma.s2", f, OpXaSf (0x8, 0, 2), {F1, F3, F4, F2}, EMPTY}, - {"fma.s3", f, OpXaSf (0x8, 0, 3), {F1, F3, F4, F2}, EMPTY}, - {"fma.s.s0", f, OpXaSf (0x8, 1, 0), {F1, F3, F4, F2}, EMPTY}, - {"fma.s", f, OpXaSf (0x8, 1, 0), {F1, F3, F4, F2}, PSEUDO, 0, NULL}, - {"fma.s.s1", f, OpXaSf (0x8, 1, 1), {F1, F3, F4, F2}, EMPTY}, - {"fma.s.s2", f, OpXaSf (0x8, 1, 2), {F1, F3, F4, F2}, EMPTY}, - {"fma.s.s3", f, OpXaSf (0x8, 1, 3), {F1, F3, F4, F2}, EMPTY}, - - {"fnorm.d.s0", f, OpXaSfF2F4 (0x9, 0, 0, 0, 1), {F1, F3}, PSEUDO, 0, N= ULL}, - {"fnorm.d", f, OpXaSfF2F4 (0x9, 0, 0, 0, 1), {F1, F3}, PSEUDO, 0, NUL= L}, - {"fnorm.d.s1", f, OpXaSfF2F4 (0x9, 0, 1, 0, 1), {F1, F3}, PSEUDO, 0, N= ULL}, - {"fnorm.d.s2", f, OpXaSfF2F4 (0x9, 0, 2, 0, 1), {F1, F3}, PSEUDO, 0, N= ULL}, - {"fnorm.d.s3", f, OpXaSfF2F4 (0x9, 0, 3, 0, 1), {F1, F3}, PSEUDO, 0, N= ULL}, - {"fcvt.xuf.d.s0", f, OpXaSfF2F4 (0x9, 0, 0, 0, 1), {F1, F3}, PSEUDO, 0= , NULL}, - {"fcvt.xuf.d", f, OpXaSfF2F4 (0x9, 0, 0, 0, 1), {F1, F3}, PSEUDO, 0, N= ULL}, - {"fcvt.xuf.d.s1", f, OpXaSfF2F4 (0x9, 0, 1, 0, 1), {F1, F3}, PSEUDO, 0= , NULL}, - {"fcvt.xuf.d.s2", f, OpXaSfF2F4 (0x9, 0, 2, 0, 1), {F1, F3}, PSEUDO, 0= , NULL}, - {"fcvt.xuf.d.s3", f, OpXaSfF2F4 (0x9, 0, 3, 0, 1), {F1, F3}, PSEUDO, 0= , NULL}, - {"fadd.d.s0", f, OpXaSfF4 (0x9, 0, 0, 1), {F1, F3, F2}, PSEUDO, 0, NUL= L}, - {"fadd.d", f, OpXaSfF4 (0x9, 0, 0, 1), {F1, F3, F2}, PSEUDO, 0, NULL}, - {"fadd.d.s1", f, OpXaSfF4 (0x9, 0, 1, 1), {F1, F3, F2}, PSEUDO, 0, NUL= L}, - {"fadd.d.s2", f, OpXaSfF4 (0x9, 0, 2, 1), {F1, F3, F2}, PSEUDO, 0, NUL= L}, - {"fadd.d.s3", f, OpXaSfF4 (0x9, 0, 3, 1), {F1, F3, F2}, PSEUDO, 0, NUL= L}, - {"fmpy.d.s0", f, OpXaSfF2 (0x9, 0, 0, 0), {F1, F3, F4}, PSEUDO, 0, NUL= L}, - {"fmpy.d", f, OpXaSfF2 (0x9, 0, 0, 0), {F1, F3, F4}, PSEUDO, 0, NULL}, - {"fmpy.d.s1", f, OpXaSfF2 (0x9, 0, 1, 0), {F1, F3, F4}, PSEUDO, 0, NUL= L}, - {"fmpy.d.s2", f, OpXaSfF2 (0x9, 0, 2, 0), {F1, F3, F4}, PSEUDO, 0, NUL= L}, - {"fmpy.d.s3", f, OpXaSfF2 (0x9, 0, 3, 0), {F1, F3, F4}, PSEUDO, 0, NUL= L}, - {"fma.d.s0", f, OpXaSf (0x9, 0, 0), {F1, F3, F4, F2}, EMPTY}, - {"fma.d", f, OpXaSf (0x9, 0, 0), {F1, F3, F4, F2}, PSEUDO, 0, NULL}, - {"fma.d.s1", f, OpXaSf (0x9, 0, 1), {F1, F3, F4, F2}, EMPTY}, - {"fma.d.s2", f, OpXaSf (0x9, 0, 2), {F1, F3, F4, F2}, EMPTY}, - {"fma.d.s3", f, OpXaSf (0x9, 0, 3), {F1, F3, F4, F2}, EMPTY}, - - {"fpmpy.s0", f, OpXaSfF2 (0x9, 1, 0, 0), {F1, F3, F4}, PSEUDO, 0, NULL= }, - {"fpmpy", f, OpXaSfF2 (0x9, 1, 0, 0), {F1, F3, F4}, PSEUDO, 0, NULL}, - {"fpmpy.s1", f, OpXaSfF2 (0x9, 1, 1, 0), {F1, F3, F4}, PSEUDO, 0, NULL= }, - {"fpmpy.s2", f, OpXaSfF2 (0x9, 1, 2, 0), {F1, F3, F4}, PSEUDO, 0, NULL= }, - {"fpmpy.s3", f, OpXaSfF2 (0x9, 1, 3, 0), {F1, F3, F4}, PSEUDO, 0, NULL= }, - {"fpma.s0", f, OpXaSf (0x9, 1, 0), {F1, F3, F4, F2}, EMPTY}, - {"fpma", f, OpXaSf (0x9, 1, 0), {F1, F3, F4, F2}, PSEUDO, 0, NULL}, - {"fpma.s1", f, OpXaSf (0x9, 1, 1), {F1, F3, F4, F2}, EMPTY}, - {"fpma.s2", f, OpXaSf (0x9, 1, 2), {F1, F3, F4, F2}, EMPTY}, - {"fpma.s3", f, OpXaSf (0x9, 1, 3), {F1, F3, F4, F2}, EMPTY}, - - {"fsub.s0", f, OpXaSfF4 (0xa, 0, 0, 1), {F1, F3, F2}, PSEUDO, 0, NULL= }, - {"fsub", f, OpXaSfF4 (0xa, 0, 0, 1), {F1, F3, F2}, PSEUDO, 0, NULL}, - {"fsub.s1", f, OpXaSfF4 (0xa, 0, 1, 1), {F1, F3, F2}, PSEUDO, 0, NULL= }, - {"fsub.s2", f, OpXaSfF4 (0xa, 0, 2, 1), {F1, F3, F2}, PSEUDO, 0, NULL= }, - {"fsub.s3", f, OpXaSfF4 (0xa, 0, 3, 1), {F1, F3, F2}, PSEUDO, 0, NULL= }, - {"fsub.s.s0", f, OpXaSfF4 (0xa, 1, 0, 1), {F1, F3, F2}, PSEUDO, 0, NUL= L}, - {"fsub.s", f, OpXaSfF4 (0xa, 1, 0, 1), {F1, F3, F2}, PSEUDO, 0, NULL}, - {"fsub.s.s1", f, OpXaSfF4 (0xa, 1, 1, 1), {F1, F3, F2}, PSEUDO, 0, NUL= L}, - {"fsub.s.s2", f, OpXaSfF4 (0xa, 1, 2, 1), {F1, F3, F2}, PSEUDO, 0, NUL= L}, - {"fsub.s.s3", f, OpXaSfF4 (0xa, 1, 3, 1), {F1, F3, F2}, PSEUDO, 0, NUL= L}, - {"fms.s0", f, OpXaSf (0xa, 0, 0), {F1, F3, F4, F2}, EMPTY}, - {"fms", f, OpXaSf (0xa, 0, 0), {F1, F3, F4, F2}, PSEUDO, 0, NULL}, - {"fms.s1", f, OpXaSf (0xa, 0, 1), {F1, F3, F4, F2}, EMPTY}, - {"fms.s2", f, OpXaSf (0xa, 0, 2), {F1, F3, F4, F2}, EMPTY}, - {"fms.s3", f, OpXaSf (0xa, 0, 3), {F1, F3, F4, F2}, EMPTY}, - {"fms.s.s0", f, OpXaSf (0xa, 1, 0), {F1, F3, F4, F2}, EMPTY}, - {"fms.s", f, OpXaSf (0xa, 1, 0), {F1, F3, F4, F2}, PSEUDO, 0, NULL}, - {"fms.s.s1", f, OpXaSf (0xa, 1, 1), {F1, F3, F4, F2}, EMPTY}, - {"fms.s.s2", f, OpXaSf (0xa, 1, 2), {F1, F3, F4, F2}, EMPTY}, - {"fms.s.s3", f, OpXaSf (0xa, 1, 3), {F1, F3, F4, F2}, EMPTY}, - {"fsub.d.s0", f, OpXaSfF4 (0xb, 0, 0, 1), {F1, F3, F2}, PSEUDO, 0, NUL= L}, - {"fsub.d", f, OpXaSfF4 (0xb, 0, 0, 1), {F1, F3, F2}, PSEUDO, 0, NULL}, - {"fsub.d.s1", f, OpXaSfF4 (0xb, 0, 1, 1), {F1, F3, F2}, PSEUDO, 0, NUL= L}, - {"fsub.d.s2", f, OpXaSfF4 (0xb, 0, 2, 1), {F1, F3, F2}, PSEUDO, 0, NUL= L}, - {"fsub.d.s3", f, OpXaSfF4 (0xb, 0, 3, 1), {F1, F3, F2}, PSEUDO, 0, NUL= L}, - {"fms.d.s0", f, OpXaSf (0xb, 0, 0), {F1, F3, F4, F2}, EMPTY}, - {"fms.d", f, OpXaSf (0xb, 0, 0), {F1, F3, F4, F2}, PSEUDO, 0, NULL}, - {"fms.d.s1", f, OpXaSf (0xb, 0, 1), {F1, F3, F4, F2}, EMPTY}, - {"fms.d.s2", f, OpXaSf (0xb, 0, 2), {F1, F3, F4, F2}, EMPTY}, - {"fms.d.s3", f, OpXaSf (0xb, 0, 3), {F1, F3, F4, F2}, EMPTY}, - - {"fpms.s0", f, OpXaSf (0xb, 1, 0), {F1, F3, F4, F2}, EMPTY}, - {"fpms", f, OpXaSf (0xb, 1, 0), {F1, F3, F4, F2}, PSEUDO, 0, NULL}, - {"fpms.s1", f, OpXaSf (0xb, 1, 1), {F1, F3, F4, F2}, EMPTY}, - {"fpms.s2", f, OpXaSf (0xb, 1, 2), {F1, F3, F4, F2}, EMPTY}, - {"fpms.s3", f, OpXaSf (0xb, 1, 3), {F1, F3, F4, F2}, EMPTY}, - - {"fnmpy.s0", f, OpXaSfF2 (0xc, 0, 0, 0), {F1, F3, F4}, PSEUDO, 0, NULL= }, - {"fnmpy", f, OpXaSfF2 (0xc, 0, 0, 0), {F1, F3, F4}, PSEUDO, 0, NULL}, - {"fnmpy.s1", f, OpXaSfF2 (0xc, 0, 1, 0), {F1, F3, F4}, PSEUDO, 0, NULL= }, - {"fnmpy.s2", f, OpXaSfF2 (0xc, 0, 2, 0), {F1, F3, F4}, PSEUDO, 0, NULL= }, - {"fnmpy.s3", f, OpXaSfF2 (0xc, 0, 3, 0), {F1, F3, F4}, PSEUDO, 0, NULL= }, - {"fnmpy.s.s0", f, OpXaSfF2 (0xc, 1, 0, 0), {F1, F3, F4}, PSEUDO, 0, NU= LL}, - {"fnmpy.s", f, OpXaSfF2 (0xc, 1, 0, 0), {F1, F3, F4}, PSEUDO, 0, NULL= }, - {"fnmpy.s.s1", f, OpXaSfF2 (0xc, 1, 1, 0), {F1, F3, F4}, PSEUDO, 0, NU= LL}, - {"fnmpy.s.s2", f, OpXaSfF2 (0xc, 1, 2, 0), {F1, F3, F4}, PSEUDO, 0, NU= LL}, - {"fnmpy.s.s3", f, OpXaSfF2 (0xc, 1, 3, 0), {F1, F3, F4}, PSEUDO, 0, NU= LL}, - {"fnma.s0", f, OpXaSf (0xc, 0, 0), {F1, F3, F4, F2}, EMPTY}, - {"fnma", f, OpXaSf (0xc, 0, 0), {F1, F3, F4, F2}, PSEUDO, 0, NULL}, - {"fnma.s1", f, OpXaSf (0xc, 0, 1), {F1, F3, F4, F2}, EMPTY}, - {"fnma.s2", f, OpXaSf (0xc, 0, 2), {F1, F3, F4, F2}, EMPTY}, - {"fnma.s3", f, OpXaSf (0xc, 0, 3), {F1, F3, F4, F2}, EMPTY}, - {"fnma.s.s0", f, OpXaSf (0xc, 1, 0), {F1, F3, F4, F2}, EMPTY}, - {"fnma.s", f, OpXaSf (0xc, 1, 0), {F1, F3, F4, F2}, PSEUDO, 0, NULL}, - {"fnma.s.s1", f, OpXaSf (0xc, 1, 1), {F1, F3, F4, F2}, EMPTY}, - {"fnma.s.s2", f, OpXaSf (0xc, 1, 2), {F1, F3, F4, F2}, EMPTY}, - {"fnma.s.s3", f, OpXaSf (0xc, 1, 3), {F1, F3, F4, F2}, EMPTY}, - {"fnmpy.d.s0", f, OpXaSfF2 (0xd, 0, 0, 0), {F1, F3, F4}, PSEUDO, 0, NU= LL}, - {"fnmpy.d", f, OpXaSfF2 (0xd, 0, 0, 0), {F1, F3, F4}, PSEUDO, 0, NULL= }, - {"fnmpy.d.s1", f, OpXaSfF2 (0xd, 0, 1, 0), {F1, F3, F4}, PSEUDO, 0, NU= LL}, - {"fnmpy.d.s2", f, OpXaSfF2 (0xd, 0, 2, 0), {F1, F3, F4}, PSEUDO, 0, NU= LL}, - {"fnmpy.d.s3", f, OpXaSfF2 (0xd, 0, 3, 0), {F1, F3, F4}, PSEUDO, 0, NU= LL}, - {"fnma.d.s0", f, OpXaSf (0xd, 0, 0), {F1, F3, F4, F2}, EMPTY}, - {"fnma.d", f, OpXaSf (0xd, 0, 0), {F1, F3, F4, F2}, PSEUDO, 0, NULL}, - {"fnma.d.s1", f, OpXaSf (0xd, 0, 1), {F1, F3, F4, F2}, EMPTY}, - {"fnma.d.s2", f, OpXaSf (0xd, 0, 2), {F1, F3, F4, F2}, EMPTY}, - {"fnma.d.s3", f, OpXaSf (0xd, 0, 3), {F1, F3, F4, F2}, EMPTY}, - - {"fpnmpy.s0", f, OpXaSfF2 (0xd, 1, 0, 0), {F1, F3, F4}, PSEUDO, 0, NUL= L}, - {"fpnmpy", f, OpXaSfF2 (0xd, 1, 0, 0), {F1, F3, F4}, PSEUDO, 0, NULL}, - {"fpnmpy.s1", f, OpXaSfF2 (0xd, 1, 1, 0), {F1, F3, F4}, PSEUDO, 0, NUL= L}, - {"fpnmpy.s2", f, OpXaSfF2 (0xd, 1, 2, 0), {F1, F3, F4}, PSEUDO, 0, NUL= L}, - {"fpnmpy.s3", f, OpXaSfF2 (0xd, 1, 3, 0), {F1, F3, F4}, PSEUDO, 0, NUL= L}, - {"fpnma.s0", f, OpXaSf (0xd, 1, 0), {F1, F3, F4, F2}, EMPTY}, - {"fpnma", f, OpXaSf (0xd, 1, 0), {F1, F3, F4, F2}, PSEUDO, 0, NULL}, - {"fpnma.s1", f, OpXaSf (0xd, 1, 1), {F1, F3, F4, F2}, EMPTY}, - {"fpnma.s2", f, OpXaSf (0xd, 1, 2), {F1, F3, F4, F2}, EMPTY}, - {"fpnma.s3", f, OpXaSf (0xd, 1, 3), {F1, F3, F4, F2}, EMPTY}, - - {"xmpy.l", f, OpXaX2F2 (0xe, 1, 0, 0), {F1, F3, F4}, PSEUDO, 0, NULL}, - {"xmpy.lu", f, OpXaX2F2 (0xe, 1, 0, 0), {F1, F3, F4}, PSEUDO, 0, NULL= }, - {"xmpy.h", f, OpXaX2F2 (0xe, 1, 3, 0), {F1, F3, F4}, PSEUDO, 0, NULL}, - {"xmpy.hu", f, OpXaX2F2 (0xe, 1, 2, 0), {F1, F3, F4}, PSEUDO, 0, NULL= }, - {"xma.l", f, OpXaX2 (0xe, 1, 0), {F1, F3, F4, F2}, EMPTY}, - {"xma.lu", f, OpXaX2 (0xe, 1, 0), {F1, F3, F4, F2}, PSEUDO, 0, NULL}, - {"xma.h", f, OpXaX2 (0xe, 1, 3), {F1, F3, F4, F2}, EMPTY}, - {"xma.hu", f, OpXaX2 (0xe, 1, 2), {F1, F3, F4, F2}, EMPTY}, - - {"fselect", f, OpXa (0xe, 0), {F1, F3, F4, F2}, EMPTY}, - - {NULL, 0, 0, 0, 0, {0}, 0, 0, NULL} - }; - -#undef f0 -#undef f -#undef f2 -#undef bF2 -#undef bF4 -#undef bQ -#undef bRa -#undef bRb -#undef bSf -#undef bTa -#undef bXa -#undef bXb -#undef bX2 -#undef bX6 -#undef mF2 -#undef mF4 -#undef mQ -#undef mRa -#undef mRb -#undef mSf -#undef mTa -#undef mXa -#undef mXb -#undef mX2 -#undef mX6 -#undef OpXa -#undef OpXaSf -#undef OpXaSfF2 -#undef OpXaSfF4 -#undef OpXaSfF2F4 -#undef OpXaX2 -#undef OpRaRbTaSf -#undef OpTa -#undef OpXbQSf -#undef OpXbX6 -#undef OpXbX6F2 -#undef OpXbX6Sf -#undef EMPTY diff --git a/opcodes/ia64-opc-i.c b/opcodes/ia64-opc-i.c deleted file mode 100644 index 5bf817027d5..00000000000 --- a/opcodes/ia64-opc-i.c +++ /dev/null @@ -1,340 +0,0 @@ -/* ia64-opc-i.c -- IA-64 `I' opcode table. - Copyright (C) 1998-2024 Free Software Foundation, Inc. - Contributed by David Mosberger-Tang - - This file is part of the GNU opcodes library. - - This library is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3, or (at your option) - any later version. - - It is distributed in the hope that it will be useful, but WITHOUT - ANY WARRANTY; without even the implied warranty of MERCHANTABILITY - or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public - License for more details. - - You should have received a copy of the GNU General Public License - along with this file; see the file COPYING. If not, write to the - Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston, - MA 02110-1301, USA. */ - -#include "ia64-opc.h" - -#define I0 IA64_TYPE_I, 0 -#define I IA64_TYPE_I, 1 -#define I2 IA64_TYPE_I, 2 - -/* instruction bit fields: */ -#define bC(x) (((ia64_insn) ((x) & 0x1)) << 12) -#define bIh(x) (((ia64_insn) ((x) & 0x1)) << 23) -#define bTa(x) (((ia64_insn) ((x) & 0x1)) << 33) -#define bTag13(x) (((ia64_insn) ((x) & 0x1)) << 33) -#define bTb(x) (((ia64_insn) ((x) & 0x1)) << 36) -#define bVc(x) (((ia64_insn) ((x) & 0x1)) << 20) -#define bVe(x) (((ia64_insn) ((x) & 0x1)) << 32) -#define bWh(x) (((ia64_insn) ((x) & 0x3)) << 20) -#define bX(x) (((ia64_insn) ((x) & 0x1)) << 33) -#define bXb(x) (((ia64_insn) ((x) & 0x1)) << 22) -#define bXc(x) (((ia64_insn) ((x) & 0x1)) << 19) -#define bX2(x) (((ia64_insn) ((x) & 0x3)) << 34) -#define bX2a(x) (((ia64_insn) ((x) & 0x3)) << 34) -#define bX2b(x) (((ia64_insn) ((x) & 0x3)) << 28) -#define bX2c(x) (((ia64_insn) ((x) & 0x3)) << 30) -#define bX3(x) (((ia64_insn) ((x) & 0x7)) << 33) -#define bX6(x) (((ia64_insn) ((x) & 0x3f)) << 27) -#define bYa(x) (((ia64_insn) ((x) & 0x1)) << 13) -#define bYb(x) (((ia64_insn) ((x) & 0x1)) << 26) -#define bZa(x) (((ia64_insn) ((x) & 0x1)) << 36) -#define bZb(x) (((ia64_insn) ((x) & 0x1)) << 33) - -/* instruction bit masks: */ -#define mC bC (-1) -#define mIh bIh (-1) -#define mTa bTa (-1) -#define mTag13 bTag13 (-1) -#define mTb bTb (-1) -#define mVc bVc (-1) -#define mVe bVe (-1) -#define mWh bWh (-1) -#define mX bX (-1) -#define mXb bXb (-1) -#define mXc bXc (-1) -#define mX2 bX2 (-1) -#define mX2a bX2a (-1) -#define mX2b bX2b (-1) -#define mX2c bX2c (-1) -#define mX3 bX3 (-1) -#define mX6 bX6 (-1) -#define mYa bYa (-1) -#define mYb bYb (-1) -#define mZa bZa (-1) -#define mZb bZb (-1) - -#define OpZaZbVeX2aX2b(a,b,c,d,e,f) \ - (bOp (a) | bZa (b) | bZb (c) | bVe (d) | bX2a (e) | bX2b (f)), \ - (mOp | mZa | mZb | mVe | mX2a | mX2b) -#define OpZaZbVeX2aX2bX2c(a,b,c,d,e,f,g) \ - (bOp (a) | bZa (b) | bZb (c) | bVe (d) | bX2a (e) | bX2b (f) | bX2c (g))= , \ - (mOp | mZa | mZb | mVe | mX2a | mX2b | mX2c) -#define OpX2X(a,b,c) (bOp (a) | bX2 (b) | bX (c)), (mOp | mX2 | mX) -#define OpX2XYa(a,b,c,d) (bOp (a) | bX2 (b) | bX (c) | bYa (d)), \ - (mOp | mX2 | mX | mYa) -#define OpX2XYb(a,b,c,d) (bOp (a) | bX2 (b) | bX (c) | bYb (d)), \ - (mOp | mX2 | mX | mYb) -#define OpX2TaTbYaC(a,b,c,d,e,f) \ - (bOp (a) | bX2 (b) | bTa (c) | bTb (d) | bYa (e) | bC (f)), \ - (mOp | mX2 | mTa | mTb | mYa | mC) -#define OpX2TaTbYaXcC(a,b,c,d,e,f,g) \ - (bOp (a) | bX2 (b) | bTa (c) | bTb (d) | bYa (e) | bXc (f) | bC (g)), \ - (mOp | mX2 | mTa | mTb | mYa | mXc | mC) -#define OpX3(a,b) (bOp (a) | bX3 (b)), (mOp | mX3) -#define OpX3X6(a,b,c) (bOp (a) | bX3 (b) | bX6(c)), \ - (mOp | mX3 | mX6) -#define OpX3X6Yb(a,b,c,d) (bOp (a) | bX3 (b) | bX6(c) | bYb(d)), \ - (mOp | mX3 | mX6 | mYb) -#define OpX3XbIhWh(a,b,c,d,e) \ - (bOp (a) | bX3 (b) | bXb (c) | bIh (d) | bWh (e)), \ - (mOp | mX3 | mXb | mIh | mWh) -#define OpX3XbIhWhTag13(a,b,c,d,e,f) \ - (bOp (a) | bX3 (b) | bXb (c) | bIh (d) | bWh (e) | bTag13 (f)), \ - (mOp | mX3 | mXb | mIh | mWh | mTag13) - -#define FULL17 ((ia64_insn)0x10ff001fc0LL) - -/* Used to initialise unused fields in ia64_opcode struct, - in order to stop gcc from complaining. */ -#define EMPTY 0,0,NULL - -struct ia64_opcode ia64_opcodes_i[] =3D - { - /* I-type instruction encodings (sorted according to major opcode). */ - - {"break.i", I0, OpX3X6 (0, 0, 0x00), {IMMU21}, X_IN_MLX, 0, NULL}, - {"nop.i", I0, OpX3X6Yb (0, 0, 0x01, 0), {IMMU21}, X_IN_MLX, 0, NULL}, - {"hint.i", I0, OpX3X6Yb (0, 0, 0x01, 1), {IMMU21}, X_IN_MLX, 0, NULL}, - {"chk.s.i", I0, OpX3 (0, 1), {R2, TGT25b}, EMPTY}, - - {"mov", I, OpX3XbIhWhTag13 (0, 7, 0, 0, 1, 0), {B1, R2}, PSEUDO, 0, NU= LL}, -#define MOV(a,b,c,d) \ - I, OpX3XbIhWh (0, a, b, c, d), {B1, R2, TAG13b}, EMPTY - {"mov.sptk", MOV (7, 0, 0, 0)}, - {"mov.sptk.imp", MOV (7, 0, 1, 0)}, - {"mov", MOV (7, 0, 0, 1)}, - {"mov.imp", MOV (7, 0, 1, 1)}, - {"mov.dptk", MOV (7, 0, 0, 2)}, - {"mov.dptk.imp", MOV (7, 0, 1, 2)}, - {"mov.ret.sptk", MOV (7, 1, 0, 0)}, - {"mov.ret.sptk.imp", MOV (7, 1, 1, 0)}, - {"mov.ret", MOV (7, 1, 0, 1)}, - {"mov.ret.imp", MOV (7, 1, 1, 1)}, - {"mov.ret.dptk", MOV (7, 1, 0, 2)}, - {"mov.ret.dptk.imp", MOV (7, 1, 1, 2)}, -#undef MOV - {"mov", I, OpX3X6 (0, 0, 0x31), {R1, B2}, EMPTY}, - {"mov", I, OpX3 (0, 3), {PR, R2, IMM17}, EMPTY}, - /* Don't remove one of the seemingly redundant FULL17-s. */ - {"mov", I, FULL17 | OpX3 (0, 3) | FULL17, {PR, R2}, PSEUDO, 0, NULL}, - {"mov", I, OpX3 (0, 2), {PR_ROT, IMM44}, EMPTY}, - {"mov", I, OpX3X6 (0, 0, 0x30), {R1, IP}, EMPTY}, - {"mov", I, OpX3X6 (0, 0, 0x33), {R1, PR}, EMPTY}, - {"mov.i", I, OpX3X6 (0, 0, 0x2a), {AR3, R2}, EMPTY}, - {"mov.i", I, OpX3X6 (0, 0, 0x0a), {AR3, IMM8}, EMPTY}, - {"mov.i", I, OpX3X6 (0, 0, 0x32), {R1, AR3}, EMPTY}, - {"zxt1", I, OpX3X6 (0, 0, 0x10), {R1, R3}, EMPTY}, - {"zxt2", I, OpX3X6 (0, 0, 0x11), {R1, R3}, EMPTY}, - {"zxt4", I, OpX3X6 (0, 0, 0x12), {R1, R3}, EMPTY}, - {"sxt1", I, OpX3X6 (0, 0, 0x14), {R1, R3}, EMPTY}, - {"sxt2", I, OpX3X6 (0, 0, 0x15), {R1, R3}, EMPTY}, - {"sxt4", I, OpX3X6 (0, 0, 0x16), {R1, R3}, EMPTY}, - {"czx1.l", I, OpX3X6 (0, 0, 0x18), {R1, R3}, EMPTY}, - {"czx2.l", I, OpX3X6 (0, 0, 0x19), {R1, R3}, EMPTY}, - {"czx1.r", I, OpX3X6 (0, 0, 0x1c), {R1, R3}, EMPTY}, - {"czx2.r", I, OpX3X6 (0, 0, 0x1d), {R1, R3}, EMPTY}, - - {"dep", I, Op (4), {R1, R2, R3, CPOS6c, LEN4}, EMPTY}, - - {"shrp", I, OpX2X (5, 3, 0), {R1, R2, R3, CNT6}, EMPTY}, - - {"shr.u", I, OpX2XYa (5, 1, 0, 0), {R1, R3, POS6}, - PSEUDO | LEN_EQ_64MCNT, 0, NULL}, - {"extr.u", I, OpX2XYa (5, 1, 0, 0), {R1, R3, POS6, LEN6}, EMPTY}, - - {"shr", I, OpX2XYa (5, 1, 0, 1), {R1, R3, POS6}, - PSEUDO | LEN_EQ_64MCNT, 0, NULL}, - {"extr", I, OpX2XYa (5, 1, 0, 1), {R1, R3, POS6, LEN6}, EMPTY}, - - {"shl", I, OpX2XYb (5, 1, 1, 0), {R1, R2, CPOS6a}, - PSEUDO | LEN_EQ_64MCNT, 0, NULL}, - {"dep.z", I, OpX2XYb (5, 1, 1, 0), {R1, R2, CPOS6a, LEN6}, EMPTY}, - {"dep.z", I, OpX2XYb (5, 1, 1, 1), {R1, IMM8, CPOS6a, LEN6}, EMPTY}, - {"dep", I, OpX2X (5, 3, 1), {R1, IMM1, R3, CPOS6b, LEN6}, EMPTY}, -#define TF(a,b,c) \ - I2, OpX2TaTbYaXcC (5, 0, a, b, 1, 1, c), {P1, P2, IMMU5b}, EMPTY -#define TFCM(a,b,c) \ - I2, OpX2TaTbYaXcC (5, 0, a, b, 1, 1, c), {P2, P1, IMMU5b}, PSEUDO, 0, NULL - {"tf.z", TF (0, 0, 0)}, - {"tf.nz", TFCM (0, 0, 0)}, - {"tf.z.unc", TF (0, 0, 1)}, - {"tf.nz.unc", TFCM (0, 0, 1)}, - {"tf.z.and", TF (0, 1, 0)}, - {"tf.nz.andcm", TFCM (0, 1, 0)}, - {"tf.nz.and", TF (0, 1, 1)}, - {"tf.z.andcm", TFCM (0, 1, 1)}, - {"tf.z.or", TF (1, 0, 0)}, - {"tf.nz.orcm", TFCM (1, 0, 0)}, - {"tf.nz.or", TF (1, 0, 1)}, - {"tf.z.orcm", TFCM (1, 0, 1)}, - {"tf.z.or.andcm", TF (1, 1, 0)}, - {"tf.nz.and.orcm", TFCM (1, 1, 0)}, - {"tf.nz.or.andcm", TF (1, 1, 1)}, - {"tf.z.and.orcm", TFCM (1, 1, 1)}, -#undef TF -#undef TFCM -#define TBIT(a,b,c,d) \ - I2, OpX2TaTbYaC (5, 0, a, b, c, d), {P1, P2, R3, POS6}, EMPTY -#define TBITCM(a,b,c,d) \ - I2, OpX2TaTbYaC (5, 0, a, b, c, d), {P2, P1, R3, POS6}, PSEUDO, 0,= NULL - {"tbit.z", TBIT (0, 0, 0, 0)}, - {"tbit.nz", TBITCM (0, 0, 0, 0)}, - {"tbit.z.unc", TBIT (0, 0, 0, 1)}, - {"tbit.nz.unc", TBITCM (0, 0, 0, 1)}, - {"tbit.z.and", TBIT (0, 1, 0, 0)}, - {"tbit.nz.andcm", TBITCM (0, 1, 0, 0)}, - {"tbit.nz.and", TBIT (0, 1, 0, 1)}, - {"tbit.z.andcm", TBITCM (0, 1, 0, 1)}, - {"tbit.z.or", TBIT (1, 0, 0, 0)}, - {"tbit.nz.orcm", TBITCM (1, 0, 0, 0)}, - {"tbit.nz.or", TBIT (1, 0, 0, 1)}, - {"tbit.z.orcm", TBITCM (1, 0, 0, 1)}, - {"tbit.z.or.andcm", TBIT (1, 1, 0, 0)}, - {"tbit.nz.and.orcm", TBITCM (1, 1, 0, 0)}, - {"tbit.nz.or.andcm", TBIT (1, 1, 0, 1)}, - {"tbit.z.and.orcm", TBITCM (1, 1, 0, 1)}, -#undef TBIT -#undef TBITCM -#define TNAT(a,b,c,d) \ - I2, OpX2TaTbYaC (5, 0, a, b, c, d), {P1, P2, R3}, EMPTY -#define TNATCM(a,b,c,d) \ - I2, OpX2TaTbYaC (5, 0, a, b, c, d), {P2, P1, R3}, PSEUDO, 0, NULL - {"tnat.z", TNAT (0, 0, 1, 0)}, - {"tnat.nz", TNATCM (0, 0, 1, 0)}, - {"tnat.z.unc", TNAT (0, 0, 1, 1)}, - {"tnat.nz.unc", TNATCM (0, 0, 1, 1)}, - {"tnat.z.and", TNAT (0, 1, 1, 0)}, - {"tnat.nz.andcm", TNATCM (0, 1, 1, 0)}, - {"tnat.nz.and", TNAT (0, 1, 1, 1)}, - {"tnat.z.andcm", TNATCM (0, 1, 1, 1)}, - {"tnat.z.or", TNAT (1, 0, 1, 0)}, - {"tnat.nz.orcm", TNATCM (1, 0, 1, 0)}, - {"tnat.nz.or", TNAT (1, 0, 1, 1)}, - {"tnat.z.orcm", TNATCM (1, 0, 1, 1)}, - {"tnat.z.or.andcm", TNAT (1, 1, 1, 0)}, - {"tnat.nz.and.orcm", TNATCM (1, 1, 1, 0)}, - {"tnat.nz.or.andcm", TNAT (1, 1, 1, 1)}, - {"tnat.z.and.orcm", TNATCM (1, 1, 1, 1)}, -#undef TNAT -#undef TNATCM - - {"pmpyshr2", I, OpZaZbVeX2aX2b (7, 0, 1, 0, 0, 3), {R1, R2, R3, CNT2= c}, EMPTY}, - {"pmpyshr2.u", I, OpZaZbVeX2aX2b (7, 0, 1, 0, 0, 1), {R1, R2, R3, CNT2= c}, EMPTY}, - {"pmpy2.r", I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 2, 1, 3), {R1, R2, R3= }, EMPTY}, - {"pmpy2.l", I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 2, 3, 3), {R1, R2, R3= }, EMPTY}, - {"mix1.r", I, OpZaZbVeX2aX2bX2c (7, 0, 0, 0, 2, 0, 2), {R1, R2, R3}= , EMPTY}, - {"mix2.r", I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 2, 0, 2), {R1, R2, R3}= , EMPTY}, - {"mix4.r", I, OpZaZbVeX2aX2bX2c (7, 1, 0, 0, 2, 0, 2), {R1, R2, R3}= , EMPTY}, - {"mix1.l", I, OpZaZbVeX2aX2bX2c (7, 0, 0, 0, 2, 2, 2), {R1, R2, R3}= , EMPTY}, - {"mix2.l", I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 2, 2, 2), {R1, R2, R3}= , EMPTY}, - {"mix4.l", I, OpZaZbVeX2aX2bX2c (7, 1, 0, 0, 2, 2, 2), {R1, R2, R3}= , EMPTY}, - {"pack2.uss", I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 2, 0, 0), {R1, R2, R3= }, EMPTY}, - {"pack2.sss", I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 2, 2, 0), {R1, R2, R3= }, EMPTY}, - {"pack4.sss", I, OpZaZbVeX2aX2bX2c (7, 1, 0, 0, 2, 2, 0), {R1, R2, R3= }, EMPTY}, - {"unpack1.h", I, OpZaZbVeX2aX2bX2c (7, 0, 0, 0, 2, 0, 1), {R1, R2, R3= }, EMPTY}, - {"unpack2.h", I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 2, 0, 1), {R1, R2, R3= }, EMPTY}, - {"unpack4.h", I, OpZaZbVeX2aX2bX2c (7, 1, 0, 0, 2, 0, 1), {R1, R2, R3= }, EMPTY}, - {"unpack1.l", I, OpZaZbVeX2aX2bX2c (7, 0, 0, 0, 2, 2, 1), {R1, R2, R3= }, EMPTY}, - {"unpack2.l", I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 2, 2, 1), {R1, R2, R3= }, EMPTY}, - {"unpack4.l", I, OpZaZbVeX2aX2bX2c (7, 1, 0, 0, 2, 2, 1), {R1, R2, R3= }, EMPTY}, - {"pmin1.u", I, OpZaZbVeX2aX2bX2c (7, 0, 0, 0, 2, 1, 0), {R1, R2, R3= }, EMPTY}, - {"pmax1.u", I, OpZaZbVeX2aX2bX2c (7, 0, 0, 0, 2, 1, 1), {R1, R2, R3= }, EMPTY}, - {"pmin2", I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 2, 3, 0), {R1, R2, R3},= EMPTY}, - {"pmax2", I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 2, 3, 1), {R1, R2, R3},= EMPTY}, - {"psad1", I, OpZaZbVeX2aX2bX2c (7, 0, 0, 0, 2, 3, 2), {R1, R2, R3},= EMPTY}, - {"mux1", I, OpZaZbVeX2aX2bX2c (7, 0, 0, 0, 3, 2, 2), {R1, R2, MBTYP= E4}, EMPTY}, - {"mux2", I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 3, 2, 2), {R1, R2, MHTYP= E8}, EMPTY}, - {"pshr2", I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 0, 2, 0), {R1, R3, R2}, EM= PTY}, - {"pshr4", I, OpZaZbVeX2aX2bX2c (7, 1, 0, 0, 0, 2, 0), {R1, R3, R2}, EM= PTY}, - {"shr", I, OpZaZbVeX2aX2bX2c (7, 1, 1, 0, 0, 2, 0), {R1, R3, R2}, EMPT= Y}, - {"pshr2.u", I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 0, 0, 0), {R1, R3, R2}, = EMPTY}, - {"pshr4.u", I, OpZaZbVeX2aX2bX2c (7, 1, 0, 0, 0, 0, 0), {R1, R3, R2}, = EMPTY}, - {"shr.u", I, OpZaZbVeX2aX2bX2c (7, 1, 1, 0, 0, 0, 0), {R1, R3, R2}, EM= PTY}, - {"pshr2", I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 1, 3, 0), {R1, R3, CNT5}, = EMPTY}, - {"pshr4", I, OpZaZbVeX2aX2bX2c (7, 1, 0, 0, 1, 3, 0), {R1, R3, CNT5}, = EMPTY}, - {"pshr2.u", I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 1, 1, 0), {R1, R3, CNT5}= , EMPTY}, - {"pshr4.u", I, OpZaZbVeX2aX2bX2c (7, 1, 0, 0, 1, 1, 0), {R1, R3, CNT5}= , EMPTY}, - {"pshl2", I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 0, 0, 1), {R1, R2, R3}, EM= PTY}, - {"pshl4", I, OpZaZbVeX2aX2bX2c (7, 1, 0, 0, 0, 0, 1), {R1, R2, R3}, EM= PTY}, - {"shl", I, OpZaZbVeX2aX2bX2c (7, 1, 1, 0, 0, 0, 1), {R1, R2, R3}, EMPT= Y}, - {"mpy4", I, OpZaZbVeX2aX2bX2c (7, 1, 0, 0, 0, 1, 3), {R1, R2, R3}, = EMPTY}, - {"mpyshl4", I, OpZaZbVeX2aX2bX2c (7, 1, 0, 0, 0, 3, 3), {R1, R2, R3}, = EMPTY}, - {"pshl2", I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 3, 1, 1), {R1, R2, CCNT5},= EMPTY}, - {"pshl4", I, OpZaZbVeX2aX2bX2c (7, 1, 0, 0, 3, 1, 1), {R1, R2, CCNT5},= EMPTY}, - {"popcnt", I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 1, 1, 2), {R1, R3}, EMPTY= }, - {"clz", I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 1, 1, 3), {R1, R3}, EMPT= Y}, - - {NULL, 0, 0, 0, 0, {0}, 0, 0, NULL} - }; - -#undef I0 -#undef I -#undef I2 -#undef L -#undef bC -#undef bIh -#undef bTa -#undef bTag13 -#undef bTb -#undef bVc -#undef bVe -#undef bWh -#undef bX -#undef bXb -#undef bX2 -#undef bX2a -#undef bX2b -#undef bX2c -#undef bX3 -#undef bX6 -#undef bY -#undef bZa -#undef bZb -#undef mC -#undef mIh -#undef mTa -#undef mTag13 -#undef mTb -#undef mVc -#undef mVe -#undef mWh -#undef mX -#undef mXb -#undef mX2 -#undef mX2a -#undef mX2b -#undef mX2c -#undef mX3 -#undef mX6 -#undef mY -#undef mZa -#undef mZb -#undef OpZaZbVeX2aX2b -#undef OpZaZbVeX2aX2bX2c -#undef OpX2X -#undef OpX2XYa -#undef OpX2XYb -#undef OpX2TaTbYaC -#undef OpX3 -#undef OpX3X6 -#undef OpX3XbIhWh -#undef OpX3XbIhWhTag13 -#undef EMPTY diff --git a/opcodes/ia64-opc-m.c b/opcodes/ia64-opc-m.c deleted file mode 100644 index b701f457f29..00000000000 --- a/opcodes/ia64-opc-m.c +++ /dev/null @@ -1,2235 +0,0 @@ -/* ia64-opc-m.c -- IA-64 `M' opcode table. - Copyright (C) 1998-2024 Free Software Foundation, Inc. - Contributed by David Mosberger-Tang - - This file is part of the GNU opcodes library. - - This library is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3, or (at your option) - any later version. - - It is distributed in the hope that it will be useful, but WITHOUT - ANY WARRANTY; without even the implied warranty of MERCHANTABILITY - or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public - License for more details. - - You should have received a copy of the GNU General Public License - along with this file; see the file COPYING. If not, write to the - Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston, - MA 02110-1301, USA. */ - -#include "ia64-opc.h" - -#define M0 IA64_TYPE_M, 0 -#define M IA64_TYPE_M, 1 -#define M2 IA64_TYPE_M, 2 - -/* instruction bit fields: */ -#define bM(x) (((ia64_insn) ((x) & 0x1)) << 36) -#define bX(x) (((ia64_insn) ((x) & 0x1)) << 27) -#define bX2(x) (((ia64_insn) ((x) & 0x3)) << 31) -#define bX3(x) (((ia64_insn) ((x) & 0x7)) << 33) -#define bX4(x) (((ia64_insn) ((x) & 0xf)) << 27) -#define bX6a(x) (((ia64_insn) ((x) & 0x3f)) << 30) -#define bX6b(x) (((ia64_insn) ((x) & 0x3f)) << 27) -#define bX7(x) (((ia64_insn) ((x) & 0x1)) << 36) /* note: alias for bM() = */ -#define bY(x) (((ia64_insn) ((x) & 0x1)) << 26) -#define bY1(x) (((ia64_insn) ((x) & 0x1)) << 19) -#define bZ(x) (((ia64_insn) ((x) & 0x3)) << 10) -#define bHint(x) (((ia64_insn) ((x) & 0x3)) << 28) -#define bHlf(x) (((ia64_insn) ((x) & 0x1)) << 12) -#define bHlfa(x) (((ia64_insn) ((x) & 0x1)) << 19) - -#define mM bM (-1) -#define mX bX (-1) -#define mX2 bX2 (-1) -#define mX3 bX3 (-1) -#define mX4 bX4 (-1) -#define mX6a bX6a (-1) -#define mX6b bX6b (-1) -#define mX7 bX7 (-1) -#define mY bY (-1) -#define mY1 bY1 (-1) -#define mZ bZ (-1) -#define mHint bHint (-1) -#define mHlf bHlf (-1) -#define mHlfa bHlfa(-1) - -#define OpX3(a,b) (bOp (a) | bX3 (b)), (mOp | mX3) -#define OpX3X6b(a,b,c) (bOp (a) | bX3 (b) | bX6b (c)), \ - (mOp | mX3 | mX6b) -#define OpX3X6bX7(a,b,c,d) (bOp (a) | bX3 (b) | bX6b (c) | bX7 (d)), \ - (mOp | mX3 | mX6b | mX7) -#define OpX3X4(a,b,c) (bOp (a) | bX3 (b) | bX4 (c)), \ - (mOp | mX3 | mX4) -#define OpX3X4X2(a,b,c,d) (bOp (a) | bX3 (b) | bX4 (c) | bX2 (d)), \ - (mOp | mX3 | mX4 | mX2) -#define OpX3X4X2Y(a,b,c,d,e) (bOp (a) | bX3 (b) | bX4 (c) | bX2 (d) | bY (= e)), \ - (mOp | mX3 | mX4 | mX2 | mY) -#define OpX3X4X2YZ(a,b,c,d,e,f) (bOp (a) | bX3 (b) | bX4 (c) | bX2 (d) | b= Y (e) | bZ(f)), \ - (mOp | mX3 | mX4 | mX2 | mY | mZ ) -#define OpX6aHint(a,b,c) (bOp (a) | bX6a (b) | bHint (c)), \ - (mOp | mX6a | mHint) -#define OpX6aHintHlf(a,b,c,d) (bOp (a) | bX6a (b) | bHint (c) | bHlf(d))= , \ - (mOp | mX6a | mHint | mHlf) -#define OpXX6aHint(a,b,c,d) (bOp (a) | bX (b) | bX6a (c) | bHint (d)), \ - (mOp | mX | mX6a | mHint) -#define OpMXX6a(a,b,c,d) \ - (bOp (a) | bM (b) | bX (c) | bX6a (d)), (mOp | mM | mX | mX6a) -#define OpMXX6aHint(a,b,c,d,e) \ - (bOp (a) | bM (b) | bX (c) | bX6a (d) | bHint (e)), \ - (mOp | mM | mX | mX6a | mHint) -#define OpMXX6aHintHlf(a,b,c,d,e,f) \ - (bOp (a) | bM (b) | bX (c) | bX6a (d) | bHint (e) | bHlf= (f)), \ - (mOp | mM | mX | mX6a | mHint | mHlf) -#define OpMXX6aHintHlfa(a,b,c,d,e,f) \ - (bOp (a) | bM (b) | bX (c) | bX6a (d) | bHint (e) | bHlf= a(f)), \ - (mOp | mM | mX | mX6a | mHint | mHlfa) -#define OpMXY1X6aHintHlf(a,b,c, cY, d,e,f) \ - (bOp (a) | bM (b) | bX (c) | bY1(cY) | bX6a (d) | bHint (e) | bHlf= (f)), \ - (mOp | mM | mX | mY1 | mX6a | mHint | mHlf) -#define OpX6aHintHlf(a,b,c,d) \ - (bOp (a) | bX6a (b) | bHint (c) | bHlf(d)), \ - (mOp | mX6a | mHint | mHlf) - -/* Used to initialise unused fields in ia64_opcode struct, - in order to stop gcc from complaining. */ -#define EMPTY 0,0,NULL - -struct ia64_opcode ia64_opcodes_m[] =3D - { - /* M-type instruction encodings (sorted according to major opcode). */ - - {"chk.a.nc", M0, OpX3 (0, 4), {R1, TGT25c}, EMPTY}, - {"chk.a.clr", M0, OpX3 (0, 5), {R1, TGT25c}, EMPTY}, - {"chk.a.nc", M0, OpX3 (0, 6), {F1, TGT25c}, EMPTY}, - {"chk.a.clr", M0, OpX3 (0, 7), {F1, TGT25c}, EMPTY}, - - {"invala", M0, OpX3X4X2 (0, 0, 0, 1), {}, EMPTY}, - {"fwb", M0, OpX3X4X2 (0, 0, 0, 2), {}, EMPTY}, - {"mf", M0, OpX3X4X2 (0, 0, 2, 2), {}, EMPTY}, - {"mf.a", M0, OpX3X4X2 (0, 0, 3, 2), {}, EMPTY}, - {"srlz.d", M0, OpX3X4X2 (0, 0, 0, 3), {}, EMPTY}, - {"srlz.i", M0, OpX3X4X2 (0, 0, 1, 3), {}, EMPTY}, - {"sync.i", M0, OpX3X4X2 (0, 0, 3, 3), {}, EMPTY}, - {"flushrs", M0, OpX3X4X2 (0, 0, 0xc, 0), {}, FIRST | NO_PRED, 0, NULL= }, - {"loadrs", M0, OpX3X4X2 (0, 0, 0xa, 0), {}, FIRST | NO_PRED, 0, NULL}, - {"invala.e", M0, OpX3X4X2 (0, 0, 2, 1), {R1}, EMPTY}, - {"invala.e", M0, OpX3X4X2 (0, 0, 3, 1), {F1}, EMPTY}, - {"mov.m", M, OpX3X4X2 (0, 0, 8, 2), {AR3, IMM8}, EMPTY}, - - {"break.m", M0, OpX3X4X2 (0, 0, 0, 0), {IMMU21}, EMPTY}, - {"nop.m", M0, OpX3X4X2Y (0, 0, 1, 0, 0), {IMMU21}, EMPTY}, - {"hint.m", M0, OpX3X4X2YZ(0, 0, 1, 0, 1, 0), {IMMU19}, EMPTY}, - {"mov", M, OpX3X4X2YZ(0, 0, 1, 0, 1, 1), {DAHR, IMMU16}, EMPTY}, - - {"sum", M0, OpX3X4 (0, 0, 4), {IMMU24}, EMPTY}, - {"rum", M0, OpX3X4 (0, 0, 5), {IMMU24}, EMPTY}, - {"ssm", M0, OpX3X4 (0, 0, 6), {IMMU24}, PRIV, 0, NULL}, - {"rsm", M0, OpX3X4 (0, 0, 7), {IMMU24}, PRIV, 0, NULL}, - - {"mov.m", M, OpX3X6b (1, 0, 0x2a), {AR3, R2}, EMPTY}, - {"mov.m", M, OpX3X6b (1, 0, 0x22), {R1, AR3}, EMPTY}, - {"mov", M, OpX3X6b (1, 0, 0x2c), {CR3, R2}, PRIV, 0, NULL}, - {"mov", M, OpX3X6b (1, 0, 0x24), {R1, CR3}, PRIV, 0, NULL}, - - {"alloc", M, OpX3 (1, 6), {R1, AR_PFS, SOF, SOL, SOR}, FIRST|NO_PRED|M= OD_RRBS, 0, NULL}, - {"alloc", M, OpX3 (1, 6), {R1, SOF, SOL, SOR}, PSEUDO|FIRST|NO_PRED|MO= D_RRBS, 0, NULL}, - - {"mov", M, OpX3X6b (1, 0, 0x2d), {PSR_L, R2}, PRIV, 0, NULL}, - {"mov", M, OpX3X6b (1, 0, 0x29), {PSR_UM, R2}, EMPTY}, - {"mov", M, OpX3X6b (1, 0, 0x25), {R1, PSR}, PRIV, 0, NULL}, - {"mov", M, OpX3X6b (1, 0, 0x21), {R1, PSR_UM}, EMPTY}, - {"probe.r", M, OpX3X6b (1, 0, 0x38), {R1, R3, R2}, EMPTY}, - {"probe.w", M, OpX3X6b (1, 0, 0x39), {R1, R3, R2}, EMPTY}, - {"probe.r", M, OpX3X6b (1, 0, 0x18), {R1, R3, IMMU2}, EMPTY}, - {"probe.w", M, OpX3X6b (1, 0, 0x19), {R1, R3, IMMU2}, EMPTY}, - {"probe.rw.fault", M0, OpX3X6b (1, 0, 0x31), {R3, IMMU2}, EMPTY}, - {"probe.r.fault", M0, OpX3X6b (1, 0, 0x32), {R3, IMMU2}, EMPTY}, - {"probe.w.fault", M0, OpX3X6b (1, 0, 0x33), {R3, IMMU2}, EMPTY}, - {"itc.d", M0, OpX3X6b (1, 0, 0x2e), {R2}, LAST | PRIV, 0, NULL}, - {"itc.i", M0, OpX3X6b (1, 0, 0x2f), {R2}, LAST | PRIV, 0, NULL}, - - {"mov", M, OpX3X6b (1, 0, 0x00), {RR_R3, R2}, PRIV, 0, NULL}, - {"mov", M, OpX3X6b (1, 0, 0x01), {DBR_R3, R2}, PRIV, 0, NULL}, - {"mov", M, OpX3X6b (1, 0, 0x02), {IBR_R3, R2}, PRIV, 0, NULL}, - {"mov", M, OpX3X6b (1, 0, 0x03), {PKR_R3, R2}, PRIV, 0, NULL}, - {"mov", M, OpX3X6b (1, 0, 0x04), {PMC_R3, R2}, PRIV, 0, NULL}, - {"mov", M, OpX3X6b (1, 0, 0x05), {PMD_R3, R2}, PRIV, 0, NULL}, - {"mov", M, OpX3X6b (1, 0, 0x06), {MSR_R3, R2}, PRIV, 0, NULL}, - {"itr.d", M, OpX3X6b (1, 0, 0x0e), {DTR_R3, R2}, PRIV, 0, NULL}, - {"itr.i", M, OpX3X6b (1, 0, 0x0f), {ITR_R3, R2}, PRIV, 0, NULL}, - - {"mov", M, OpX3X6b (1, 0, 0x10), {R1, RR_R3}, PRIV, 0, NULL}, - {"mov", M, OpX3X6b (1, 0, 0x11), {R1, DBR_R3}, PRIV, 0, NULL}, - {"mov", M, OpX3X6b (1, 0, 0x12), {R1, IBR_R3}, PRIV, 0, NULL}, - {"mov", M, OpX3X6b (1, 0, 0x13), {R1, PKR_R3}, PRIV, 0, NULL}, - {"mov", M, OpX3X6b (1, 0, 0x14), {R1, PMC_R3}, PRIV, 0, NULL}, - {"mov", M, OpX3X6b (1, 0, 0x15), {R1, PMD_R3}, EMPTY}, - {"mov", M, OpX3X6b (1, 0, 0x16), {R1, MSR_R3}, PRIV, 0, NULL}, - {"mov", M, OpX3X6b (1, 0, 0x17), {R1, CPUID_R3}, EMPTY}, - {"mov", M, OpX3X6b (1, 0, 0x20), {R1, DAHR_R3}, EMPTY}, - - {"ptc.l", M0, OpX3X6b (1, 0, 0x09), {R3, R2}, PRIV, 0, NULL}, - {"ptc.g", M0, OpX3X6b (1, 0, 0x0a), {R3, R2}, LAST | PRIV, 0, NULL}, - {"ptc.ga", M0, OpX3X6b (1, 0, 0x0b), {R3, R2}, LAST | PRIV, 0, NULL}, - {"ptr.d", M0, OpX3X6b (1, 0, 0x0c), {R3, R2}, PRIV, 0, NULL}, - {"ptr.i", M0, OpX3X6b (1, 0, 0x0d), {R3, R2}, PRIV, 0, NULL}, - - {"thash", M, OpX3X6b (1, 0, 0x1a), {R1, R3}, EMPTY}, - {"ttag", M, OpX3X6b (1, 0, 0x1b), {R1, R3}, EMPTY}, - {"tpa", M, OpX3X6b (1, 0, 0x1e), {R1, R3}, PRIV, 0, NULL}, - {"tak", M, OpX3X6b (1, 0, 0x1f), {R1, R3}, PRIV, 0, NULL}, - - {"chk.s.m", M0, OpX3 (1, 1), {R2, TGT25b}, EMPTY}, - {"chk.s", M0, OpX3 (1, 3), {F2, TGT25b}, EMPTY}, - - {"fc", M0, OpX3X6bX7 (1, 0, 0x30, 0), {R3}, EMPTY}, - {"fc.i", M0, OpX3X6bX7 (1, 0, 0x30, 1), {R3}, EMPTY}, - {"ptc.e", M0, OpX3X6b (1, 0, 0x34), {R3}, PRIV, 0, NULL}, - -#if 0 -// old pre-psn variant with 2-bit hints; -// saved for reference - /* integer load */ - {"ld1", M, OpMXX6aHint (4, 0, 0, 0x00, 0), {R1, MR3}, EMPTY}, - {"ld1.nt1", M, OpMXX6aHint (4, 0, 0, 0x00, 1), {R1, MR3}, EMPTY}, - {"ld1.nta", M, OpMXX6aHint (4, 0, 0, 0x00, 3), {R1, MR3}, EMPTY}, - {"ld2", M, OpMXX6aHint (4, 0, 0, 0x01, 0), {R1, MR3}, EMPTY}, - {"ld2.nt1", M, OpMXX6aHint (4, 0, 0, 0x01, 1), {R1, MR3}, EMPTY}, - {"ld2.nta", M, OpMXX6aHint (4, 0, 0, 0x01, 3), {R1, MR3}, EMPTY}, - {"ld4", M, OpMXX6aHint (4, 0, 0, 0x02, 0), {R1, MR3}, EMPTY}, - {"ld4.nt1", M, OpMXX6aHint (4, 0, 0, 0x02, 1), {R1, MR3}, EMPTY}, - {"ld4.nta", M, OpMXX6aHint (4, 0, 0, 0x02, 3), {R1, MR3}, EMPTY}, - {"ld8", M, OpMXX6aHint (4, 0, 0, 0x03, 0), {R1, MR3}, EMPTY}, - {"ld8.nt1", M, OpMXX6aHint (4, 0, 0, 0x03, 1), {R1, MR3}, EMPTY}, - {"ld8.nta", M, OpMXX6aHint (4, 0, 0, 0x03, 3), {R1, MR3}, EMPTY}, - {"ld16", M2, OpMXX6aHint (4, 0, 1, 0x28, 0), {R1, AR_CSD, MR3}, EMPTY= }, - {"ld16", M, OpMXX6aHint (4, 0, 1, 0x28, 0), {R1, MR3}, PSEUDO, 0, NUL= L}, - {"ld16.nt1", M2, OpMXX6aHint (4, 0, 1, 0x28, 1), {R1, AR_CSD, MR3}, EM= PTY}, - {"ld16.nt1", M, OpMXX6aHint (4, 0, 1, 0x28, 1), {R1, MR3}, PSEUDO, 0, = NULL}, - {"ld16.nta", M2, OpMXX6aHint (4, 0, 1, 0x28, 3), {R1, AR_CSD, MR3}, EM= PTY}, - {"ld16.nta", M, OpMXX6aHint (4, 0, 1, 0x28, 3), {R1, MR3}, PSEUDO, 0, = NULL}, - {"ld1.s", M, OpMXX6aHint (4, 0, 0, 0x04, 0), {R1, MR3}, EMPTY}, - {"ld1.s.nt1", M, OpMXX6aHint (4, 0, 0, 0x04, 1), {R1, MR3}, EMPTY}, - {"ld1.s.nta", M, OpMXX6aHint (4, 0, 0, 0x04, 3), {R1, MR3}, EMPTY}, - {"ld2.s", M, OpMXX6aHint (4, 0, 0, 0x05, 0), {R1, MR3}, EMPTY}, - {"ld2.s.nt1", M, OpMXX6aHint (4, 0, 0, 0x05, 1), {R1, MR3}, EMPTY}, - {"ld2.s.nta", M, OpMXX6aHint (4, 0, 0, 0x05, 3), {R1, MR3}, EMPTY}, - {"ld4.s", M, OpMXX6aHint (4, 0, 0, 0x06, 0), {R1, MR3}, EMPTY}, - {"ld4.s.nt1", M, OpMXX6aHint (4, 0, 0, 0x06, 1), {R1, MR3}, EMPTY}, - {"ld4.s.nta", M, OpMXX6aHint (4, 0, 0, 0x06, 3), {R1, MR3}, EMPTY}, - {"ld8.s", M, OpMXX6aHint (4, 0, 0, 0x07, 0), {R1, MR3}, EMPTY}, - {"ld8.s.nt1", M, OpMXX6aHint (4, 0, 0, 0x07, 1), {R1, MR3}, EMPTY}, - {"ld8.s.nta", M, OpMXX6aHint (4, 0, 0, 0x07, 3), {R1, MR3}, EMPTY}, - {"ld1.a", M, OpMXX6aHint (4, 0, 0, 0x08, 0), {R1, MR3}, EMPTY}, - {"ld1.a.nt1", M, OpMXX6aHint (4, 0, 0, 0x08, 1), {R1, MR3}, EMPTY}, - {"ld1.a.nta", M, OpMXX6aHint (4, 0, 0, 0x08, 3), {R1, MR3}, EMPTY}, - {"ld2.a", M, OpMXX6aHint (4, 0, 0, 0x09, 0), {R1, MR3}, EMPTY}, - {"ld2.a.nt1", M, OpMXX6aHint (4, 0, 0, 0x09, 1), {R1, MR3}, EMPTY}, - {"ld2.a.nta", M, OpMXX6aHint (4, 0, 0, 0x09, 3), {R1, MR3}, EMPTY}, - {"ld4.a", M, OpMXX6aHint (4, 0, 0, 0x0a, 0), {R1, MR3}, EMPTY}, - {"ld4.a.nt1", M, OpMXX6aHint (4, 0, 0, 0x0a, 1), {R1, MR3}, EMPTY}, - {"ld4.a.nta", M, OpMXX6aHint (4, 0, 0, 0x0a, 3), {R1, MR3}, EMPTY}, - {"ld8.a", M, OpMXX6aHint (4, 0, 0, 0x0b, 0), {R1, MR3}, EMPTY}, - {"ld8.a.nt1", M, OpMXX6aHint (4, 0, 0, 0x0b, 1), {R1, MR3}, EMPTY}, - {"ld8.a.nta", M, OpMXX6aHint (4, 0, 0, 0x0b, 3), {R1, MR3}, EMPTY}, - {"ld1.sa", M, OpMXX6aHint (4, 0, 0, 0x0c, 0), {R1, MR3}, EMPTY}, - {"ld1.sa.nt1", M, OpMXX6aHint (4, 0, 0, 0x0c, 1), {R1, MR3}, EMPTY}, - {"ld1.sa.nta", M, OpMXX6aHint (4, 0, 0, 0x0c, 3), {R1, MR3}, EMPTY}, - {"ld2.sa", M, OpMXX6aHint (4, 0, 0, 0x0d, 0), {R1, MR3}, EMPTY}, - {"ld2.sa.nt1", M, OpMXX6aHint (4, 0, 0, 0x0d, 1), {R1, MR3}, EMPTY}, - {"ld2.sa.nta", M, OpMXX6aHint (4, 0, 0, 0x0d, 3), {R1, MR3}, EMPTY}, - {"ld4.sa", M, OpMXX6aHint (4, 0, 0, 0x0e, 0), {R1, MR3}, EMPTY}, - {"ld4.sa.nt1", M, OpMXX6aHint (4, 0, 0, 0x0e, 1), {R1, MR3}, EMPTY}, - {"ld4.sa.nta", M, OpMXX6aHint (4, 0, 0, 0x0e, 3), {R1, MR3}, EMPTY}, - {"ld8.sa", M, OpMXX6aHint (4, 0, 0, 0x0f, 0), {R1, MR3}, EMPTY}, - {"ld8.sa.nt1", M, OpMXX6aHint (4, 0, 0, 0x0f, 1), {R1, MR3}, EMPTY}, - {"ld8.sa.nta", M, OpMXX6aHint (4, 0, 0, 0x0f, 3), {R1, MR3}, EMPTY}, - {"ld1.bias", M, OpMXX6aHint (4, 0, 0, 0x10, 0), {R1, MR3}, EMPTY}, - {"ld1.bias.nt1", M, OpMXX6aHint (4, 0, 0, 0x10, 1), {R1, MR3}, EMPTY}, - {"ld1.bias.nta", M, OpMXX6aHint (4, 0, 0, 0x10, 3), {R1, MR3}, EMPTY}, - {"ld2.bias", M, OpMXX6aHint (4, 0, 0, 0x11, 0), {R1, MR3}, EMPTY}, - {"ld2.bias.nt1", M, OpMXX6aHint (4, 0, 0, 0x11, 1), {R1, MR3}, EMPTY}, - {"ld2.bias.nta", M, OpMXX6aHint (4, 0, 0, 0x11, 3), {R1, MR3}, EMPTY}, - {"ld4.bias", M, OpMXX6aHint (4, 0, 0, 0x12, 0), {R1, MR3}, EMPTY}, - {"ld4.bias.nt1", M, OpMXX6aHint (4, 0, 0, 0x12, 1), {R1, MR3}, EMPTY}, - {"ld4.bias.nta", M, OpMXX6aHint (4, 0, 0, 0x12, 3), {R1, MR3}, EMPTY}, - {"ld8.bias", M, OpMXX6aHint (4, 0, 0, 0x13, 0), {R1, MR3}, EMPTY}, - {"ld8.bias.nt1", M, OpMXX6aHint (4, 0, 0, 0x13, 1), {R1, MR3}, EMPTY}, - {"ld8.bias.nta", M, OpMXX6aHint (4, 0, 0, 0x13, 3), {R1, MR3}, EMPTY}, - {"ld1.acq", M, OpMXX6aHint (4, 0, 0, 0x14, 0), {R1, MR3}, EMPTY}, - {"ld1.acq.nt1", M, OpMXX6aHint (4, 0, 0, 0x14, 1), {R1, MR3}, EMPTY}, - {"ld1.acq.nta", M, OpMXX6aHint (4, 0, 0, 0x14, 3), {R1, MR3}, EMPTY}, - {"ld2.acq", M, OpMXX6aHint (4, 0, 0, 0x15, 0), {R1, MR3}, EMPTY}, - {"ld2.acq.nt1", M, OpMXX6aHint (4, 0, 0, 0x15, 1), {R1, MR3}, EMPTY}, - {"ld2.acq.nta", M, OpMXX6aHint (4, 0, 0, 0x15, 3), {R1, MR3}, EMPTY}, - {"ld4.acq", M, OpMXX6aHint (4, 0, 0, 0x16, 0), {R1, MR3}, EMPTY}, - {"ld4.acq.nt1", M, OpMXX6aHint (4, 0, 0, 0x16, 1), {R1, MR3}, EMPTY}, - {"ld4.acq.nta", M, OpMXX6aHint (4, 0, 0, 0x16, 3), {R1, MR3}, EMPTY}, - {"ld8.acq", M, OpMXX6aHint (4, 0, 0, 0x17, 0), {R1, MR3}, EMPTY}, - {"ld8.acq.nt1", M, OpMXX6aHint (4, 0, 0, 0x17, 1), {R1, MR3}, EMPTY}, - {"ld8.acq.nta", M, OpMXX6aHint (4, 0, 0, 0x17, 3), {R1, MR3}, EMPTY}, - {"ld16.acq", M2, OpMXX6aHint (4, 0, 1, 0x2c, 0), {R1, AR_CSD, MR3}, EM= PTY}, - {"ld16.acq", M, OpMXX6aHint (4, 0, 1, 0x2c, 0), {R1, MR3}, PSEUDO, 0, = NULL}, - {"ld16.acq.nt1", M2, OpMXX6aHint (4, 0, 1, 0x2c, 1), {R1, AR_CSD, MR3}= , EMPTY}, - {"ld16.acq.nt1", M, OpMXX6aHint (4, 0, 1, 0x2c, 1), {R1, MR3}, PSEUDO,= 0, NULL}, - {"ld16.acq.nta", M2, OpMXX6aHint (4, 0, 1, 0x2c, 3), {R1, AR_CSD, MR3}= , EMPTY}, - {"ld16.acq.nta", M, OpMXX6aHint (4, 0, 1, 0x2c, 3), {R1, MR3}, PSEUDO,= 0, NULL}, - {"ld8.fill", M, OpMXX6aHint (4, 0, 0, 0x1b, 0), {R1, MR3}, EMPTY}, - {"ld8.fill.nt1", M, OpMXX6aHint (4, 0, 0, 0x1b, 1), {R1, MR3}, EMPTY}, - {"ld8.fill.nta", M, OpMXX6aHint (4, 0, 0, 0x1b, 3), {R1, MR3}, EMPTY}, - {"ld1.c.clr", M, OpMXX6aHint (4, 0, 0, 0x20, 0), {R1, MR3}, EMPTY}, - {"ld1.c.clr.nt1", M, OpMXX6aHint (4, 0, 0, 0x20, 1), {R1, MR3}, EMPTY}, - {"ld1.c.clr.nta", M, OpMXX6aHint (4, 0, 0, 0x20, 3), {R1, MR3}, EMPTY}, - {"ld2.c.clr", M, OpMXX6aHint (4, 0, 0, 0x21, 0), {R1, MR3}, EMPTY}, - {"ld2.c.clr.nt1", M, OpMXX6aHint (4, 0, 0, 0x21, 1), {R1, MR3}, EMPTY}, - {"ld2.c.clr.nta", M, OpMXX6aHint (4, 0, 0, 0x21, 3), {R1, MR3}, EMPTY}, - {"ld4.c.clr", M, OpMXX6aHint (4, 0, 0, 0x22, 0), {R1, MR3}, EMPTY}, - {"ld4.c.clr.nt1", M, OpMXX6aHint (4, 0, 0, 0x22, 1), {R1, MR3}, EMPTY}, - {"ld4.c.clr.nta", M, OpMXX6aHint (4, 0, 0, 0x22, 3), {R1, MR3}, EMPTY}, - {"ld8.c.clr", M, OpMXX6aHint (4, 0, 0, 0x23, 0), {R1, MR3}, EMPTY}, - {"ld8.c.clr.nt1", M, OpMXX6aHint (4, 0, 0, 0x23, 1), {R1, MR3}, EMPTY}, - {"ld8.c.clr.nta", M, OpMXX6aHint (4, 0, 0, 0x23, 3), {R1, MR3}, EMPTY}, - {"ld1.c.nc", M, OpMXX6aHint (4, 0, 0, 0x24, 0), {R1, MR3}, EMPTY}, - {"ld1.c.nc.nt1", M, OpMXX6aHint (4, 0, 0, 0x24, 1), {R1, MR3}, EMPTY}, - {"ld1.c.nc.nta", M, OpMXX6aHint (4, 0, 0, 0x24, 3), {R1, MR3}, EMPTY}, - {"ld2.c.nc", M, OpMXX6aHint (4, 0, 0, 0x25, 0), {R1, MR3}, EMPTY}, - {"ld2.c.nc.nt1", M, OpMXX6aHint (4, 0, 0, 0x25, 1), {R1, MR3}, EMPTY}, - {"ld2.c.nc.nta", M, OpMXX6aHint (4, 0, 0, 0x25, 3), {R1, MR3}, EMPTY}, - {"ld4.c.nc", M, OpMXX6aHint (4, 0, 0, 0x26, 0), {R1, MR3}, EMPTY}, - {"ld4.c.nc.nt1", M, OpMXX6aHint (4, 0, 0, 0x26, 1), {R1, MR3}, EMPTY}, - {"ld4.c.nc.nta", M, OpMXX6aHint (4, 0, 0, 0x26, 3), {R1, MR3}, EMPTY}, - {"ld8.c.nc", M, OpMXX6aHint (4, 0, 0, 0x27, 0), {R1, MR3}, EMPTY}, - {"ld8.c.nc.nt1", M, OpMXX6aHint (4, 0, 0, 0x27, 1), {R1, MR3}, EMPTY}, - {"ld8.c.nc.nta", M, OpMXX6aHint (4, 0, 0, 0x27, 3), {R1, MR3}, EMPTY}, - {"ld1.c.clr.acq", M, OpMXX6aHint (4, 0, 0, 0x28, 0), {R1, MR3}, EMPT= Y}, - {"ld1.c.clr.acq.nt1", M, OpMXX6aHint (4, 0, 0, 0x28, 1), {R1, MR3}, EM= PTY}, - {"ld1.c.clr.acq.nta", M, OpMXX6aHint (4, 0, 0, 0x28, 3), {R1, MR3}, EM= PTY}, - {"ld2.c.clr.acq", M, OpMXX6aHint (4, 0, 0, 0x29, 0), {R1, MR3}, EMPT= Y}, - {"ld2.c.clr.acq.nt1", M, OpMXX6aHint (4, 0, 0, 0x29, 1), {R1, MR3}, EM= PTY}, - {"ld2.c.clr.acq.nta", M, OpMXX6aHint (4, 0, 0, 0x29, 3), {R1, MR3}, EM= PTY}, - {"ld4.c.clr.acq", M, OpMXX6aHint (4, 0, 0, 0x2a, 0), {R1, MR3}, EMPT= Y}, - {"ld4.c.clr.acq.nt1", M, OpMXX6aHint (4, 0, 0, 0x2a, 1), {R1, MR3}, EM= PTY}, - {"ld4.c.clr.acq.nta", M, OpMXX6aHint (4, 0, 0, 0x2a, 3), {R1, MR3}, EM= PTY}, - {"ld8.c.clr.acq", M, OpMXX6aHint (4, 0, 0, 0x2b, 0), {R1, MR3}, EMPT= Y}, - {"ld8.c.clr.acq.nt1", M, OpMXX6aHint (4, 0, 0, 0x2b, 1), {R1, MR3}, EM= PTY}, - {"ld8.c.clr.acq.nta", M, OpMXX6aHint (4, 0, 0, 0x2b, 3), {R1, MR3}, EM= PTY}, -#endif - -#if 1 - /* integer load */ - {"ld1", M, OpMXX6aHintHlfa (4, 0, 0, 0x00, 0, 0), {R1, MR3}, EMPTY}, - {"ld1.nt1", M, OpMXX6aHintHlfa (4, 0, 0, 0x00, 1, 0), {R1, MR3}, EMPT= Y}, - {"ld1.d1", M, OpMXX6aHintHlfa (4, 0, 0, 0x00, 1, 0), {R1, MR3}, PSEUD= O, 0, NULL}, - {"ld1.d2", M, OpMXX6aHintHlfa (4, 0, 0, 0x00, 2, 0), {R1, MR3}, EMPTY= }, - {"ld1.nt2", M, OpMXX6aHintHlfa (4, 0, 0, 0x00, 2, 0), {R1, MR3}, PSEU= DO, 0, NULL}, - {"ld1.nta", M, OpMXX6aHintHlfa (4, 0, 0, 0x00, 3, 0), {R1, MR3}, EMPT= Y}, - {"ld1.d3", M, OpMXX6aHintHlfa (4, 0, 0, 0x00, 3, 0), {R1, MR3}, PSEUD= O, 0, NULL}, - {"ld1.d4", M, OpMXX6aHintHlfa (4, 0, 0, 0x00, 0, 1), {R1, MR3}, EMPTY= }, - {"ld1.d5", M, OpMXX6aHintHlfa (4, 0, 0, 0x00, 1, 1), {R1, MR3}, EMPTY= }, - {"ld1.d6", M, OpMXX6aHintHlfa (4, 0, 0, 0x00, 2, 1), {R1, MR3}, EMPTY= }, - {"ld1.d7", M, OpMXX6aHintHlfa (4, 0, 0, 0x00, 3, 1), {R1, MR3}, EMPTY= }, - {"ld2", M, OpMXX6aHintHlfa (4, 0, 0, 0x01, 0, 0), {R1, MR3}, EMPTY}, - {"ld2.nt1", M, OpMXX6aHintHlfa (4, 0, 0, 0x01, 1, 0), {R1, MR3}, EMPT= Y}, - {"ld2.d1", M, OpMXX6aHintHlfa (4, 0, 0, 0x01, 1, 0), {R1, MR3}, PSEUD= O, 0, NULL}, - {"ld2.d2", M, OpMXX6aHintHlfa (4, 0, 0, 0x01, 2, 0), {R1, MR3}, EMPTY= }, - {"ld2.nt2", M, OpMXX6aHintHlfa (4, 0, 0, 0x01, 2, 0), {R1, MR3}, PSEU= DO, 0, NULL}, - {"ld2.nta", M, OpMXX6aHintHlfa (4, 0, 0, 0x01, 3, 0), {R1, MR3}, EMPT= Y}, - {"ld2.d3", M, OpMXX6aHintHlfa (4, 0, 0, 0x01, 3, 0), {R1, MR3}, PSEUD= O, 0, NULL}, - {"ld2.d4", M, OpMXX6aHintHlfa (4, 0, 0, 0x01, 0, 1), {R1, MR3}, EMPTY= }, - {"ld2.d5", M, OpMXX6aHintHlfa (4, 0, 0, 0x01, 1, 1), {R1, MR3}, EMPTY= }, - {"ld2.d6", M, OpMXX6aHintHlfa (4, 0, 0, 0x01, 2, 1), {R1, MR3}, EMPTY= }, - {"ld2.d7", M, OpMXX6aHintHlfa (4, 0, 0, 0x01, 3, 1), {R1, MR3}, EMPTY= }, - {"ld4", M, OpMXX6aHintHlfa (4, 0, 0, 0x02, 0, 0), {R1, MR3}, EMPTY}, - {"ld4.nt1", M, OpMXX6aHintHlfa (4, 0, 0, 0x02, 1, 0), {R1, MR3}, EMPT= Y}, - {"ld4.d1", M, OpMXX6aHintHlfa (4, 0, 0, 0x02, 1, 0), {R1, MR3}, PSEUD= O, 0, NULL}, - {"ld4.d2", M, OpMXX6aHintHlfa (4, 0, 0, 0x02, 2, 0), {R1, MR3}, EMPTY= }, - {"ld4.nt2", M, OpMXX6aHintHlfa (4, 0, 0, 0x02, 2, 0), {R1, MR3}, PSEU= DO, 0, NULL}, - {"ld4.nta", M, OpMXX6aHintHlfa (4, 0, 0, 0x02, 3, 0), {R1, MR3}, EMPT= Y}, - {"ld4.d3", M, OpMXX6aHintHlfa (4, 0, 0, 0x02, 3, 0), {R1, MR3}, PSEUD= O, 0, NULL}, - {"ld4.d4", M, OpMXX6aHintHlfa (4, 0, 0, 0x02, 0, 1), {R1, MR3}, EMPTY= }, - {"ld4.d5", M, OpMXX6aHintHlfa (4, 0, 0, 0x02, 1, 1), {R1, MR3}, EMPTY= }, - {"ld4.d6", M, OpMXX6aHintHlfa (4, 0, 0, 0x02, 2, 1), {R1, MR3}, EMPTY= }, - {"ld4.d7", M, OpMXX6aHintHlfa (4, 0, 0, 0x02, 3, 1), {R1, MR3}, EMPTY= }, - {"ld8", M, OpMXX6aHintHlfa (4, 0, 0, 0x03, 0, 0), {R1, MR3}, EMPTY}, - {"ld8.nt1", M, OpMXX6aHintHlfa (4, 0, 0, 0x03, 1, 0), {R1, MR3}, EMPT= Y}, - {"ld8.d1", M, OpMXX6aHintHlfa (4, 0, 0, 0x03, 1, 0), {R1, MR3}, PSEUD= O, 0, NULL}, - {"ld8.d2", M, OpMXX6aHintHlfa (4, 0, 0, 0x03, 2, 0), {R1, MR3}, EMPTY= }, - {"ld8.nt2", M, OpMXX6aHintHlfa (4, 0, 0, 0x03, 2, 0), {R1, MR3}, PSEU= DO, 0, NULL}, - {"ld8.nta", M, OpMXX6aHintHlfa (4, 0, 0, 0x03, 3, 0), {R1, MR3}, EMPT= Y}, - {"ld8.d3", M, OpMXX6aHintHlfa (4, 0, 0, 0x03, 3, 0), {R1, MR3}, PSEUD= O, 0, NULL}, - {"ld8.d4", M, OpMXX6aHintHlfa (4, 0, 0, 0x03, 0, 1), {R1, MR3}, EMPTY= }, - {"ld8.d5", M, OpMXX6aHintHlfa (4, 0, 0, 0x03, 1, 1), {R1, MR3}, EMPTY= }, - {"ld8.d6", M, OpMXX6aHintHlfa (4, 0, 0, 0x03, 2, 1), {R1, MR3}, EMPTY= }, - {"ld8.d7", M, OpMXX6aHintHlfa (4, 0, 0, 0x03, 3, 1), {R1, MR3}, EMPTY= }, - {"ld1.s", M, OpMXX6aHintHlfa (4, 0, 0, 0x04, 0, 0), {R1, MR3}, EMPTY}, - {"ld1.s.nt1", M, OpMXX6aHintHlfa (4, 0, 0, 0x04, 1, 0), {R1, MR3}, EMP= TY}, - {"ld1.s.d1", M, OpMXX6aHintHlfa (4, 0, 0, 0x04, 1, 0), {R1, MR3}, PSEU= DO, 0, NULL}, - {"ld1.s.d2", M, OpMXX6aHintHlfa (4, 0, 0, 0x04, 2, 0), {R1, MR3}, EMPT= Y}, - {"ld1.s.nt2", M, OpMXX6aHintHlfa (4, 0, 0, 0x04, 2, 0), {R1, MR3}, PSE= UDO, 0, NULL}, - {"ld1.s.nta", M, OpMXX6aHintHlfa (4, 0, 0, 0x04, 3, 0), {R1, MR3}, EMP= TY}, - {"ld1.s.d3", M, OpMXX6aHintHlfa (4, 0, 0, 0x04, 3, 0), {R1, MR3}, PSEU= DO, 0, NULL}, - {"ld1.s.d4", M, OpMXX6aHintHlfa (4, 0, 0, 0x04, 0, 1), {R1, MR3}, EMPT= Y}, - {"ld1.s.d5", M, OpMXX6aHintHlfa (4, 0, 0, 0x04, 1, 1), {R1, MR3}, EMPT= Y}, - {"ld1.s.d6", M, OpMXX6aHintHlfa (4, 0, 0, 0x04, 2, 1), {R1, MR3}, EMPT= Y}, - {"ld1.s.d7", M, OpMXX6aHintHlfa (4, 0, 0, 0x04, 3, 1), {R1, MR3}, EMPT= Y}, - {"ld2.s", M, OpMXX6aHintHlfa (4, 0, 0, 0x05, 0, 0), {R1, MR3}, EMPTY}, - {"ld2.s.nt1", M, OpMXX6aHintHlfa (4, 0, 0, 0x05, 1, 0), {R1, MR3}, EMP= TY}, - {"ld2.s.d1", M, OpMXX6aHintHlfa (4, 0, 0, 0x05, 1, 0), {R1, MR3}, PSEU= DO, 0, NULL}, - {"ld2.s.d2", M, OpMXX6aHintHlfa (4, 0, 0, 0x05, 2, 0), {R1, MR3}, EMPT= Y}, - {"ld2.s.nt2", M, OpMXX6aHintHlfa (4, 0, 0, 0x05, 2, 0), {R1, MR3}, PSE= UDO, 0, NULL}, - {"ld2.s.nta", M, OpMXX6aHintHlfa (4, 0, 0, 0x05, 3, 0), {R1, MR3}, EMP= TY}, - {"ld2.s.d3", M, OpMXX6aHintHlfa (4, 0, 0, 0x05, 3, 0), {R1, MR3}, PSEU= DO, 0, NULL}, - {"ld2.s.d4", M, OpMXX6aHintHlfa (4, 0, 0, 0x05, 0, 1), {R1, MR3}, EMPT= Y}, - {"ld2.s.d5", M, OpMXX6aHintHlfa (4, 0, 0, 0x05, 1, 1), {R1, MR3}, EMPT= Y}, - {"ld2.s.d6", M, OpMXX6aHintHlfa (4, 0, 0, 0x05, 2, 1), {R1, MR3}, EMPT= Y}, - {"ld2.s.d7", M, OpMXX6aHintHlfa (4, 0, 0, 0x05, 3, 1), {R1, MR3}, EMPT= Y}, - {"ld4.s", M, OpMXX6aHintHlfa (4, 0, 0, 0x06, 0, 0), {R1, MR3}, EMPTY}, - {"ld4.s.nt1", M, OpMXX6aHintHlfa (4, 0, 0, 0x06, 1, 0), {R1, MR3}, EMP= TY}, - {"ld4.s.d1", M, OpMXX6aHintHlfa (4, 0, 0, 0x06, 1, 0), {R1, MR3}, PSEU= DO, 0, NULL}, - {"ld4.s.d2", M, OpMXX6aHintHlfa (4, 0, 0, 0x06, 2, 0), {R1, MR3}, EMPT= Y}, - {"ld4.s.nt2", M, OpMXX6aHintHlfa (4, 0, 0, 0x06, 2, 0), {R1, MR3}, PSE= UDO, 0, NULL}, - {"ld4.s.nta", M, OpMXX6aHintHlfa (4, 0, 0, 0x06, 3, 0), {R1, MR3}, EMP= TY}, - {"ld4.s.d3", M, OpMXX6aHintHlfa (4, 0, 0, 0x06, 3, 0), {R1, MR3}, PSEU= DO, 0, NULL}, - {"ld4.s.d4", M, OpMXX6aHintHlfa (4, 0, 0, 0x06, 0, 1), {R1, MR3}, EMPT= Y}, - {"ld4.s.d5", M, OpMXX6aHintHlfa (4, 0, 0, 0x06, 1, 1), {R1, MR3}, EMPT= Y}, - {"ld4.s.d6", M, OpMXX6aHintHlfa (4, 0, 0, 0x06, 2, 1), {R1, MR3}, EMPT= Y}, - {"ld4.s.d7", M, OpMXX6aHintHlfa (4, 0, 0, 0x06, 3, 1), {R1, MR3}, EMPT= Y}, - {"ld8.s", M, OpMXX6aHintHlfa (4, 0, 0, 0x07, 0, 0), {R1, MR3}, EMPTY}, - {"ld8.s.nt1", M, OpMXX6aHintHlfa (4, 0, 0, 0x07, 1, 0), {R1, MR3}, EMP= TY}, - {"ld8.s.d1", M, OpMXX6aHintHlfa (4, 0, 0, 0x07, 1, 0), {R1, MR3}, PSEU= DO, 0, NULL}, - {"ld8.s.d2", M, OpMXX6aHintHlfa (4, 0, 0, 0x07, 2, 0), {R1, MR3}, EMPT= Y}, - {"ld8.s.nt2", M, OpMXX6aHintHlfa (4, 0, 0, 0x07, 2, 0), {R1, MR3}, PSE= UDO, 0, NULL}, - {"ld8.s.nta", M, OpMXX6aHintHlfa (4, 0, 0, 0x07, 3, 0), {R1, MR3}, EMP= TY}, - {"ld8.s.d3", M, OpMXX6aHintHlfa (4, 0, 0, 0x07, 3, 0), {R1, MR3}, PSEU= DO, 0, NULL}, - {"ld8.s.d4", M, OpMXX6aHintHlfa (4, 0, 0, 0x07, 0, 1), {R1, MR3}, EMPT= Y}, - {"ld8.s.d5", M, OpMXX6aHintHlfa (4, 0, 0, 0x07, 1, 1), {R1, MR3}, EMPT= Y}, - {"ld8.s.d6", M, OpMXX6aHintHlfa (4, 0, 0, 0x07, 2, 1), {R1, MR3}, EMPT= Y}, - {"ld8.s.d7", M, OpMXX6aHintHlfa (4, 0, 0, 0x07, 3, 1), {R1, MR3}, EMPT= Y}, - {"ld1.a", M, OpMXX6aHintHlfa (4, 0, 0, 0x08, 0, 0), {R1, MR3}, EMPTY}, - {"ld1.a.nt1", M, OpMXX6aHintHlfa (4, 0, 0, 0x08, 1, 0), {R1, MR3}, EMP= TY}, - {"ld1.a.d1", M, OpMXX6aHintHlfa (4, 0, 0, 0x08, 1, 0), {R1, MR3}, PSEU= DO, 0, NULL}, - {"ld1.a.d2", M, OpMXX6aHintHlfa (4, 0, 0, 0x08, 2, 0), {R1, MR3}, EMPT= Y}, - {"ld1.a.nt2", M, OpMXX6aHintHlfa (4, 0, 0, 0x08, 2, 0), {R1, MR3}, PSE= UDO, 0, NULL}, - {"ld1.a.nta", M, OpMXX6aHintHlfa (4, 0, 0, 0x08, 3, 0), {R1, MR3}, EMP= TY}, - {"ld1.a.d3", M, OpMXX6aHintHlfa (4, 0, 0, 0x08, 3, 0), {R1, MR3}, PSEU= DO, 0, NULL}, - {"ld1.a.d4", M, OpMXX6aHintHlfa (4, 0, 0, 0x08, 0, 1), {R1, MR3}, EMPT= Y}, - {"ld1.a.d5", M, OpMXX6aHintHlfa (4, 0, 0, 0x08, 1, 1), {R1, MR3}, EMPT= Y}, - {"ld1.a.d6", M, OpMXX6aHintHlfa (4, 0, 0, 0x08, 2, 1), {R1, MR3}, EMPT= Y}, - {"ld1.a.d7", M, OpMXX6aHintHlfa (4, 0, 0, 0x08, 3, 1), {R1, MR3}, EMPT= Y}, - {"ld2.a", M, OpMXX6aHintHlfa (4, 0, 0, 0x09, 0, 0), {R1, MR3}, EMPTY}, - {"ld2.a.nt1", M, OpMXX6aHintHlfa (4, 0, 0, 0x09, 1, 0), {R1, MR3}, EMP= TY}, - {"ld2.a.d1", M, OpMXX6aHintHlfa (4, 0, 0, 0x09, 1, 0), {R1, MR3}, PSEU= DO, 0, NULL}, - {"ld2.a.d2", M, OpMXX6aHintHlfa (4, 0, 0, 0x09, 2, 0), {R1, MR3}, EMPT= Y}, - {"ld2.a.nt2", M, OpMXX6aHintHlfa (4, 0, 0, 0x09, 2, 0), {R1, MR3}, PSE= UDO, 0, NULL}, - {"ld2.a.nta", M, OpMXX6aHintHlfa (4, 0, 0, 0x09, 3, 0), {R1, MR3}, EMP= TY}, - {"ld2.a.d3", M, OpMXX6aHintHlfa (4, 0, 0, 0x09, 3, 0), {R1, MR3}, PSEU= DO, 0, NULL}, - {"ld2.a.d4", M, OpMXX6aHintHlfa (4, 0, 0, 0x09, 0, 1), {R1, MR3}, EMPT= Y}, - {"ld2.a.d5", M, OpMXX6aHintHlfa (4, 0, 0, 0x09, 1, 1), {R1, MR3}, EMPT= Y}, - {"ld2.a.d6", M, OpMXX6aHintHlfa (4, 0, 0, 0x09, 2, 1), {R1, MR3}, EMPT= Y}, - {"ld2.a.d7", M, OpMXX6aHintHlfa (4, 0, 0, 0x09, 3, 1), {R1, MR3}, EMPT= Y}, - {"ld4.a", M, OpMXX6aHintHlfa (4, 0, 0, 0x0a, 0, 0), {R1, MR3}, EMPTY}, - {"ld4.a.nt1", M, OpMXX6aHintHlfa (4, 0, 0, 0x0a, 1, 0), {R1, MR3}, EMP= TY}, - {"ld4.a.d1", M, OpMXX6aHintHlfa (4, 0, 0, 0x0a, 1, 0), {R1, MR3}, PSEU= DO, 0, NULL}, - {"ld4.a.d2", M, OpMXX6aHintHlfa (4, 0, 0, 0x0a, 2, 0), {R1, MR3}, EMPT= Y}, - {"ld4.a.nt2", M, OpMXX6aHintHlfa (4, 0, 0, 0x0a, 2, 0), {R1, MR3}, PSE= UDO, 0, NULL}, - {"ld4.a.nta", M, OpMXX6aHintHlfa (4, 0, 0, 0x0a, 3, 0), {R1, MR3}, EMP= TY}, - {"ld4.a.d3", M, OpMXX6aHintHlfa (4, 0, 0, 0x0a, 3, 0), {R1, MR3}, PSEU= DO, 0, NULL}, - {"ld4.a.d4", M, OpMXX6aHintHlfa (4, 0, 0, 0x0a, 0, 1), {R1, MR3}, EMPT= Y}, - {"ld4.a.d5", M, OpMXX6aHintHlfa (4, 0, 0, 0x0a, 1, 1), {R1, MR3}, EMPT= Y}, - {"ld4.a.d6", M, OpMXX6aHintHlfa (4, 0, 0, 0x0a, 2, 1), {R1, MR3}, EMPT= Y}, - {"ld4.a.d7", M, OpMXX6aHintHlfa (4, 0, 0, 0x0a, 3, 1), {R1, MR3}, EMPT= Y}, - {"ld8.a", M, OpMXX6aHintHlfa (4, 0, 0, 0x0b, 0, 0), {R1, MR3}, EMPTY}, - {"ld8.a.nt1", M, OpMXX6aHintHlfa (4, 0, 0, 0x0b, 1, 0), {R1, MR3}, EMP= TY}, - {"ld8.a.d1", M, OpMXX6aHintHlfa (4, 0, 0, 0x0b, 1, 0), {R1, MR3}, PSEU= DO, 0, NULL}, - {"ld8.a.d2", M, OpMXX6aHintHlfa (4, 0, 0, 0x0b, 2, 0), {R1, MR3}, EMPT= Y}, - {"ld8.a.nt2", M, OpMXX6aHintHlfa (4, 0, 0, 0x0b, 2, 0), {R1, MR3}, PSE= UDO, 0, NULL}, - {"ld8.a.nta", M, OpMXX6aHintHlfa (4, 0, 0, 0x0b, 3, 0), {R1, MR3}, EMP= TY}, - {"ld8.a.d3", M, OpMXX6aHintHlfa (4, 0, 0, 0x0b, 3, 0), {R1, MR3}, PSEU= DO, 0, NULL}, - {"ld8.a.d4", M, OpMXX6aHintHlfa (4, 0, 0, 0x0b, 0, 1), {R1, MR3}, EMPT= Y}, - {"ld8.a.d5", M, OpMXX6aHintHlfa (4, 0, 0, 0x0b, 1, 1), {R1, MR3}, EMPT= Y}, - {"ld8.a.d6", M, OpMXX6aHintHlfa (4, 0, 0, 0x0b, 2, 1), {R1, MR3}, EMPT= Y}, - {"ld8.a.d7", M, OpMXX6aHintHlfa (4, 0, 0, 0x0b, 3, 1), {R1, MR3}, EMPT= Y}, - {"ld1.sa", M, OpMXX6aHintHlfa (4, 0, 0, 0x0c, 0, 0), {R1, MR3}, EMPTY= }, - {"ld1.sa.nt1", M, OpMXX6aHintHlfa (4, 0, 0, 0x0c, 1, 0), {R1, MR3}, EM= PTY}, - {"ld1.sa.d1", M, OpMXX6aHintHlfa (4, 0, 0, 0x0c, 1, 0), {R1, MR3}, PSE= UDO, 0, NULL}, - {"ld1.sa.d2", M, OpMXX6aHintHlfa (4, 0, 0, 0x0c, 2, 0), {R1, MR3}, EMP= TY}, - {"ld1.sa.nt2", M, OpMXX6aHintHlfa (4, 0, 0, 0x0c, 2, 0), {R1, MR3}, PS= EUDO, 0, NULL}, - {"ld1.sa.nta", M, OpMXX6aHintHlfa (4, 0, 0, 0x0c, 3, 0), {R1, MR3}, EM= PTY}, - {"ld1.sa.d3", M, OpMXX6aHintHlfa (4, 0, 0, 0x0c, 3, 0), {R1, MR3}, PSE= UDO, 0, NULL}, - {"ld1.sa.d4", M, OpMXX6aHintHlfa (4, 0, 0, 0x0c, 0, 1), {R1, MR3}, EMP= TY}, - {"ld1.sa.d5", M, OpMXX6aHintHlfa (4, 0, 0, 0x0c, 1, 1), {R1, MR3}, EMP= TY}, - {"ld1.sa.d6", M, OpMXX6aHintHlfa (4, 0, 0, 0x0c, 2, 1), {R1, MR3}, EMP= TY}, - {"ld1.sa.d7", M, OpMXX6aHintHlfa (4, 0, 0, 0x0c, 3, 1), {R1, MR3}, EMP= TY}, - {"ld2.sa", M, OpMXX6aHintHlfa (4, 0, 0, 0x0d, 0, 0), {R1, MR3}, EMPTY= }, - {"ld2.sa.nt1", M, OpMXX6aHintHlfa (4, 0, 0, 0x0d, 1, 0), {R1, MR3}, EM= PTY}, - {"ld2.sa.d1", M, OpMXX6aHintHlfa (4, 0, 0, 0x0d, 1, 0), {R1, MR3}, PSE= UDO, 0, NULL}, - {"ld2.sa.d2", M, OpMXX6aHintHlfa (4, 0, 0, 0x0d, 2, 0), {R1, MR3}, EMP= TY}, - {"ld2.sa.nt2", M, OpMXX6aHintHlfa (4, 0, 0, 0x0d, 2, 0), {R1, MR3}, PS= EUDO, 0, NULL}, - {"ld2.sa.nta", M, OpMXX6aHintHlfa (4, 0, 0, 0x0d, 3, 0), {R1, MR3}, EM= PTY}, - {"ld2.sa.d3", M, OpMXX6aHintHlfa (4, 0, 0, 0x0d, 3, 0), {R1, MR3}, PSE= UDO, 0, NULL}, - {"ld2.sa.d4", M, OpMXX6aHintHlfa (4, 0, 0, 0x0d, 0, 1), {R1, MR3}, EMP= TY}, - {"ld2.sa.d5", M, OpMXX6aHintHlfa (4, 0, 0, 0x0d, 1, 1), {R1, MR3}, EMP= TY}, - {"ld2.sa.d6", M, OpMXX6aHintHlfa (4, 0, 0, 0x0d, 2, 1), {R1, MR3}, EMP= TY}, - {"ld2.sa.d7", M, OpMXX6aHintHlfa (4, 0, 0, 0x0d, 3, 1), {R1, MR3}, EMP= TY}, - {"ld4.sa", M, OpMXX6aHintHlfa (4, 0, 0, 0x0e, 0, 0), {R1, MR3}, EMPTY= }, - {"ld4.sa.nt1", M, OpMXX6aHintHlfa (4, 0, 0, 0x0e, 1, 0), {R1, MR3}, EM= PTY}, - {"ld4.sa.d1", M, OpMXX6aHintHlfa (4, 0, 0, 0x0e, 1, 0), {R1, MR3}, PSE= UDO, 0, NULL}, - {"ld4.sa.d2", M, OpMXX6aHintHlfa (4, 0, 0, 0x0e, 2, 0), {R1, MR3}, EMP= TY}, - {"ld4.sa.nt2", M, OpMXX6aHintHlfa (4, 0, 0, 0x0e, 2, 0), {R1, MR3}, PS= EUDO, 0, NULL}, - {"ld4.sa.nta", M, OpMXX6aHintHlfa (4, 0, 0, 0x0e, 3, 0), {R1, MR3}, EM= PTY}, - {"ld4.sa.d3", M, OpMXX6aHintHlfa (4, 0, 0, 0x0e, 3, 0), {R1, MR3}, PSE= UDO, 0, NULL}, - {"ld4.sa.d4", M, OpMXX6aHintHlfa (4, 0, 0, 0x0e, 0, 1), {R1, MR3}, EMP= TY}, - {"ld4.sa.d5", M, OpMXX6aHintHlfa (4, 0, 0, 0x0e, 1, 1), {R1, MR3}, EMP= TY}, - {"ld4.sa.d6", M, OpMXX6aHintHlfa (4, 0, 0, 0x0e, 2, 1), {R1, MR3}, EMP= TY}, - {"ld4.sa.d7", M, OpMXX6aHintHlfa (4, 0, 0, 0x0e, 3, 1), {R1, MR3}, EMP= TY}, - {"ld8.sa", M, OpMXX6aHintHlfa (4, 0, 0, 0x0f, 0, 0), {R1, MR3}, EMPTY= }, - {"ld8.sa.nt1", M, OpMXX6aHintHlfa (4, 0, 0, 0x0f, 1, 0), {R1, MR3}, EM= PTY}, - {"ld8.sa.d1", M, OpMXX6aHintHlfa (4, 0, 0, 0x0f, 1, 0), {R1, MR3}, PSE= UDO, 0, NULL}, - {"ld8.sa.d2", M, OpMXX6aHintHlfa (4, 0, 0, 0x0f, 2, 0), {R1, MR3}, EMP= TY}, - {"ld8.sa.nt2", M, OpMXX6aHintHlfa (4, 0, 0, 0x0f, 2, 0), {R1, MR3}, PS= EUDO, 0, NULL}, - {"ld8.sa.nta", M, OpMXX6aHintHlfa (4, 0, 0, 0x0f, 3, 0), {R1, MR3}, EM= PTY}, - {"ld8.sa.d3", M, OpMXX6aHintHlfa (4, 0, 0, 0x0f, 3, 0), {R1, MR3}, PSE= UDO, 0, NULL}, - {"ld8.sa.d4", M, OpMXX6aHintHlfa (4, 0, 0, 0x0f, 0, 1), {R1, MR3}, EMP= TY}, - {"ld8.sa.d5", M, OpMXX6aHintHlfa (4, 0, 0, 0x0f, 1, 1), {R1, MR3}, EMP= TY}, - {"ld8.sa.d6", M, OpMXX6aHintHlfa (4, 0, 0, 0x0f, 2, 1), {R1, MR3}, EMP= TY}, - {"ld8.sa.d7", M, OpMXX6aHintHlfa (4, 0, 0, 0x0f, 3, 1), {R1, MR3}, EMP= TY}, - {"ld1.bias", M, OpMXX6aHintHlfa (4, 0, 0, 0x10, 0, 0), {R1, MR3}, EMPT= Y}, - {"ld1.bias.nt1", M, OpMXX6aHintHlfa (4, 0, 0, 0x10, 1, 0), {R1, MR3}, = EMPTY}, - {"ld1.bias.d1", M, OpMXX6aHintHlfa (4, 0, 0, 0x10, 1, 0), {R1, MR3}, P= SEUDO, 0, NULL}, - {"ld1.bias.d2", M, OpMXX6aHintHlfa (4, 0, 0, 0x10, 2, 0), {R1, MR3}, E= MPTY}, - {"ld1.bias.nt2", M, OpMXX6aHintHlfa (4, 0, 0, 0x10, 2, 0), {R1, MR3}, = PSEUDO, 0, NULL}, - {"ld1.bias.nta", M, OpMXX6aHintHlfa (4, 0, 0, 0x10, 3, 0), {R1, MR3}, = EMPTY}, - {"ld1.bias.d3", M, OpMXX6aHintHlfa (4, 0, 0, 0x10, 3, 0), {R1, MR3}, P= SEUDO, 0, NULL}, - {"ld1.bias.d4", M, OpMXX6aHintHlfa (4, 0, 0, 0x10, 0, 1), {R1, MR3}, E= MPTY}, - {"ld1.bias.d5", M, OpMXX6aHintHlfa (4, 0, 0, 0x10, 1, 1), {R1, MR3}, E= MPTY}, - {"ld1.bias.d6", M, OpMXX6aHintHlfa (4, 0, 0, 0x10, 2, 1), {R1, MR3}, E= MPTY}, - {"ld1.bias.d7", M, OpMXX6aHintHlfa (4, 0, 0, 0x10, 3, 1), {R1, MR3}, E= MPTY}, - {"ld2.bias", M, OpMXX6aHintHlfa (4, 0, 0, 0x11, 0, 0), {R1, MR3}, EMPT= Y}, - {"ld2.bias.nt1", M, OpMXX6aHintHlfa (4, 0, 0, 0x11, 1, 0), {R1, MR3}, = EMPTY}, - {"ld2.bias.d1", M, OpMXX6aHintHlfa (4, 0, 0, 0x11, 1, 0), {R1, MR3}, P= SEUDO, 0, NULL}, - {"ld2.bias.d2", M, OpMXX6aHintHlfa (4, 0, 0, 0x11, 2, 0), {R1, MR3}, E= MPTY}, - {"ld2.bias.nt2", M, OpMXX6aHintHlfa (4, 0, 0, 0x11, 2, 0), {R1, MR3}, = PSEUDO, 0, NULL}, - {"ld2.bias.nta", M, OpMXX6aHintHlfa (4, 0, 0, 0x11, 3, 0), {R1, MR3}, = EMPTY}, - {"ld2.bias.d3", M, OpMXX6aHintHlfa (4, 0, 0, 0x11, 3, 0), {R1, MR3}, P= SEUDO, 0, NULL}, - {"ld2.bias.d4", M, OpMXX6aHintHlfa (4, 0, 0, 0x11, 0, 1), {R1, MR3}, E= MPTY}, - {"ld2.bias.d5", M, OpMXX6aHintHlfa (4, 0, 0, 0x11, 1, 1), {R1, MR3}, E= MPTY}, - {"ld2.bias.d6", M, OpMXX6aHintHlfa (4, 0, 0, 0x11, 2, 1), {R1, MR3}, E= MPTY}, - {"ld2.bias.d7", M, OpMXX6aHintHlfa (4, 0, 0, 0x11, 3, 1), {R1, MR3}, E= MPTY}, - {"ld4.bias", M, OpMXX6aHintHlfa (4, 0, 0, 0x12, 0, 0), {R1, MR3}, EMPT= Y}, - {"ld4.bias.nt1", M, OpMXX6aHintHlfa (4, 0, 0, 0x12, 1, 0), {R1, MR3}, = EMPTY}, - {"ld4.bias.d1", M, OpMXX6aHintHlfa (4, 0, 0, 0x12, 1, 0), {R1, MR3}, P= SEUDO, 0, NULL}, - {"ld4.bias.d2", M, OpMXX6aHintHlfa (4, 0, 0, 0x12, 2, 0), {R1, MR3}, E= MPTY}, - {"ld4.bias.nt2", M, OpMXX6aHintHlfa (4, 0, 0, 0x12, 2, 0), {R1, MR3}, = PSEUDO, 0, NULL}, - {"ld4.bias.nta", M, OpMXX6aHintHlfa (4, 0, 0, 0x12, 3, 0), {R1, MR3}, = EMPTY}, - {"ld4.bias.d3", M, OpMXX6aHintHlfa (4, 0, 0, 0x12, 3, 0), {R1, MR3}, P= SEUDO, 0, NULL}, - {"ld4.bias.d4", M, OpMXX6aHintHlfa (4, 0, 0, 0x12, 0, 1), {R1, MR3}, E= MPTY}, - {"ld4.bias.d5", M, OpMXX6aHintHlfa (4, 0, 0, 0x12, 1, 1), {R1, MR3}, E= MPTY}, - {"ld4.bias.d6", M, OpMXX6aHintHlfa (4, 0, 0, 0x12, 2, 1), {R1, MR3}, E= MPTY}, - {"ld4.bias.d7", M, OpMXX6aHintHlfa (4, 0, 0, 0x12, 3, 1), {R1, MR3}, E= MPTY}, - {"ld8.bias", M, OpMXX6aHintHlfa (4, 0, 0, 0x13, 0, 0), {R1, MR3}, EMPT= Y}, - {"ld8.bias.nt1", M, OpMXX6aHintHlfa (4, 0, 0, 0x13, 1, 0), {R1, MR3}, = EMPTY}, - {"ld8.bias.d1", M, OpMXX6aHintHlfa (4, 0, 0, 0x13, 1, 0), {R1, MR3}, P= SEUDO, 0, NULL}, - {"ld8.bias.d2", M, OpMXX6aHintHlfa (4, 0, 0, 0x13, 2, 0), {R1, MR3}, E= MPTY}, - {"ld8.bias.nt2", M, OpMXX6aHintHlfa (4, 0, 0, 0x13, 2, 0), {R1, MR3}, = PSEUDO, 0, NULL}, - {"ld8.bias.nta", M, OpMXX6aHintHlfa (4, 0, 0, 0x13, 3, 0), {R1, MR3}, = EMPTY}, - {"ld8.bias.d3", M, OpMXX6aHintHlfa (4, 0, 0, 0x13, 3, 0), {R1, MR3}, P= SEUDO, 0, NULL}, - {"ld8.bias.d4", M, OpMXX6aHintHlfa (4, 0, 0, 0x13, 0, 1), {R1, MR3}, E= MPTY}, - {"ld8.bias.d5", M, OpMXX6aHintHlfa (4, 0, 0, 0x13, 1, 1), {R1, MR3}, E= MPTY}, - {"ld8.bias.d6", M, OpMXX6aHintHlfa (4, 0, 0, 0x13, 2, 1), {R1, MR3}, E= MPTY}, - {"ld8.bias.d7", M, OpMXX6aHintHlfa (4, 0, 0, 0x13, 3, 1), {R1, MR3}, E= MPTY}, - {"ld1.acq", M, OpMXX6aHintHlfa (4, 0, 0, 0x14, 0, 0), {R1, MR3}, EMPT= Y}, - {"ld1.acq.nt1", M, OpMXX6aHintHlfa (4, 0, 0, 0x14, 1, 0), {R1, MR3}, E= MPTY}, - {"ld1.acq.d1", M, OpMXX6aHintHlfa (4, 0, 0, 0x14, 1, 0), {R1, MR3}, PS= EUDO, 0, NULL}, - {"ld1.acq.d2", M, OpMXX6aHintHlfa (4, 0, 0, 0x14, 2, 0), {R1, MR3}, EM= PTY}, - {"ld1.acq.nt2", M, OpMXX6aHintHlfa (4, 0, 0, 0x14, 2, 0), {R1, MR3}, P= SEUDO, 0, NULL}, - {"ld1.acq.nta", M, OpMXX6aHintHlfa (4, 0, 0, 0x14, 3, 0), {R1, MR3}, E= MPTY}, - {"ld1.acq.d3", M, OpMXX6aHintHlfa (4, 0, 0, 0x14, 3, 0), {R1, MR3}, PS= EUDO, 0, NULL}, - {"ld1.acq.d4", M, OpMXX6aHintHlfa (4, 0, 0, 0x14, 0, 1), {R1, MR3}, EM= PTY}, - {"ld1.acq.d5", M, OpMXX6aHintHlfa (4, 0, 0, 0x14, 1, 1), {R1, MR3}, EM= PTY}, - {"ld1.acq.d6", M, OpMXX6aHintHlfa (4, 0, 0, 0x14, 2, 1), {R1, MR3}, EM= PTY}, - {"ld1.acq.d7", M, OpMXX6aHintHlfa (4, 0, 0, 0x14, 3, 1), {R1, MR3}, EM= PTY}, - {"ld2.acq", M, OpMXX6aHintHlfa (4, 0, 0, 0x15, 0, 0), {R1, MR3}, EMPT= Y}, - {"ld2.acq.nt1", M, OpMXX6aHintHlfa (4, 0, 0, 0x15, 1, 0), {R1, MR3}, E= MPTY}, - {"ld2.acq.d1", M, OpMXX6aHintHlfa (4, 0, 0, 0x15, 1, 0), {R1, MR3}, PS= EUDO, 0, NULL}, - {"ld2.acq.d2", M, OpMXX6aHintHlfa (4, 0, 0, 0x15, 2, 0), {R1, MR3}, EM= PTY}, - {"ld2.acq.nt2", M, OpMXX6aHintHlfa (4, 0, 0, 0x15, 2, 0), {R1, MR3}, P= SEUDO, 0, NULL}, - {"ld2.acq.nta", M, OpMXX6aHintHlfa (4, 0, 0, 0x15, 3, 0), {R1, MR3}, E= MPTY}, - {"ld2.acq.d3", M, OpMXX6aHintHlfa (4, 0, 0, 0x15, 3, 0), {R1, MR3}, PS= EUDO, 0, NULL}, - {"ld2.acq.d4", M, OpMXX6aHintHlfa (4, 0, 0, 0x15, 0, 1), {R1, MR3}, EM= PTY}, - {"ld2.acq.d5", M, OpMXX6aHintHlfa (4, 0, 0, 0x15, 1, 1), {R1, MR3}, EM= PTY}, - {"ld2.acq.d6", M, OpMXX6aHintHlfa (4, 0, 0, 0x15, 2, 1), {R1, MR3}, EM= PTY}, - {"ld2.acq.d7", M, OpMXX6aHintHlfa (4, 0, 0, 0x15, 3, 1), {R1, MR3}, EM= PTY}, - {"ld4.acq", M, OpMXX6aHintHlfa (4, 0, 0, 0x16, 0, 0), {R1, MR3}, EMPT= Y}, - {"ld4.acq.nt1", M, OpMXX6aHintHlfa (4, 0, 0, 0x16, 1, 0), {R1, MR3}, E= MPTY}, - {"ld4.acq.d1", M, OpMXX6aHintHlfa (4, 0, 0, 0x16, 1, 0), {R1, MR3}, PS= EUDO, 0, NULL}, - {"ld4.acq.d2", M, OpMXX6aHintHlfa (4, 0, 0, 0x16, 2, 0), {R1, MR3}, EM= PTY}, - {"ld4.acq.nt2", M, OpMXX6aHintHlfa (4, 0, 0, 0x16, 2, 0), {R1, MR3}, P= SEUDO, 0, NULL}, - {"ld4.acq.nta", M, OpMXX6aHintHlfa (4, 0, 0, 0x16, 3, 0), {R1, MR3}, E= MPTY}, - {"ld4.acq.d3", M, OpMXX6aHintHlfa (4, 0, 0, 0x16, 3, 0), {R1, MR3}, PS= EUDO, 0, NULL}, - {"ld4.acq.d4", M, OpMXX6aHintHlfa (4, 0, 0, 0x16, 0, 1), {R1, MR3}, EM= PTY}, - {"ld4.acq.d5", M, OpMXX6aHintHlfa (4, 0, 0, 0x16, 1, 1), {R1, MR3}, EM= PTY}, - {"ld4.acq.d6", M, OpMXX6aHintHlfa (4, 0, 0, 0x16, 2, 1), {R1, MR3}, EM= PTY}, - {"ld4.acq.d7", M, OpMXX6aHintHlfa (4, 0, 0, 0x16, 3, 1), {R1, MR3}, EM= PTY}, - {"ld8.acq", M, OpMXX6aHintHlfa (4, 0, 0, 0x17, 0, 0), {R1, MR3}, EMPT= Y}, - {"ld8.acq.nt1", M, OpMXX6aHintHlfa (4, 0, 0, 0x17, 1, 0), {R1, MR3}, E= MPTY}, - {"ld8.acq.d1", M, OpMXX6aHintHlfa (4, 0, 0, 0x17, 1, 0), {R1, MR3}, PS= EUDO, 0, NULL}, - {"ld8.acq.d2", M, OpMXX6aHintHlfa (4, 0, 0, 0x17, 2, 0), {R1, MR3}, EM= PTY}, - {"ld8.acq.nt2", M, OpMXX6aHintHlfa (4, 0, 0, 0x17, 2, 0), {R1, MR3}, P= SEUDO, 0, NULL}, - {"ld8.acq.nta", M, OpMXX6aHintHlfa (4, 0, 0, 0x17, 3, 0), {R1, MR3}, E= MPTY}, - {"ld8.acq.d3", M, OpMXX6aHintHlfa (4, 0, 0, 0x17, 3, 0), {R1, MR3}, PS= EUDO, 0, NULL}, - {"ld8.acq.d4", M, OpMXX6aHintHlfa (4, 0, 0, 0x17, 0, 1), {R1, MR3}, EM= PTY}, - {"ld8.acq.d5", M, OpMXX6aHintHlfa (4, 0, 0, 0x17, 1, 1), {R1, MR3}, EM= PTY}, - {"ld8.acq.d6", M, OpMXX6aHintHlfa (4, 0, 0, 0x17, 2, 1), {R1, MR3}, EM= PTY}, - {"ld8.acq.d7", M, OpMXX6aHintHlfa (4, 0, 0, 0x17, 3, 1), {R1, MR3}, EM= PTY}, - {"ld8.fill", M, OpMXX6aHintHlfa (4, 0, 0, 0x1b, 0, 0), {R1, MR3}, EMPT= Y}, - {"ld8.fill.nt1", M, OpMXX6aHintHlfa (4, 0, 0, 0x1b, 1, 0), {R1, MR3}, = EMPTY}, - {"ld8.fill.d1", M, OpMXX6aHintHlfa (4, 0, 0, 0x1b, 1, 0), {R1, MR3}, P= SEUDO, 0, NULL}, - {"ld8.fill.d2", M, OpMXX6aHintHlfa (4, 0, 0, 0x1b, 2, 0), {R1, MR3}, E= MPTY}, - {"ld8.fill.nt2", M, OpMXX6aHintHlfa (4, 0, 0, 0x1b, 2, 0), {R1, MR3}, = PSEUDO, 0, NULL}, - {"ld8.fill.nta", M, OpMXX6aHintHlfa (4, 0, 0, 0x1b, 3, 0), {R1, MR3}, = EMPTY}, - {"ld8.fill.d3", M, OpMXX6aHintHlfa (4, 0, 0, 0x1b, 3, 0), {R1, MR3}, P= SEUDO, 0, NULL}, - {"ld8.fill.d4", M, OpMXX6aHintHlfa (4, 0, 0, 0x1b, 0, 1), {R1, MR3}, E= MPTY}, - {"ld8.fill.d5", M, OpMXX6aHintHlfa (4, 0, 0, 0x1b, 1, 1), {R1, MR3}, E= MPTY}, - {"ld8.fill.d6", M, OpMXX6aHintHlfa (4, 0, 0, 0x1b, 2, 1), {R1, MR3}, E= MPTY}, - {"ld8.fill.d7", M, OpMXX6aHintHlfa (4, 0, 0, 0x1b, 3, 1), {R1, MR3}, E= MPTY}, - {"ld1.c.clr", M, OpMXX6aHintHlfa (4, 0, 0, 0x20, 0, 0), {R1, MR3}, EMP= TY}, - {"ld1.c.clr.nt1", M, OpMXX6aHintHlfa (4, 0, 0, 0x20, 1, 0), {R1, MR3},= EMPTY}, - {"ld1.c.clr.d1", M, OpMXX6aHintHlfa (4, 0, 0, 0x20, 1, 0), {R1, MR3}, = PSEUDO, 0, NULL}, - {"ld1.c.clr.d2", M, OpMXX6aHintHlfa (4, 0, 0, 0x20, 2, 0), {R1, MR3}, = EMPTY}, - {"ld1.c.clr.nt2", M, OpMXX6aHintHlfa (4, 0, 0, 0x20, 2, 0), {R1, MR3},= PSEUDO, 0, NULL}, - {"ld1.c.clr.nta", M, OpMXX6aHintHlfa (4, 0, 0, 0x20, 3, 0), {R1, MR3},= EMPTY}, - {"ld1.c.clr.d3", M, OpMXX6aHintHlfa (4, 0, 0, 0x20, 3, 0), {R1, MR3}, = PSEUDO, 0, NULL}, - {"ld1.c.clr.d4", M, OpMXX6aHintHlfa (4, 0, 0, 0x20, 0, 1), {R1, MR3}, = EMPTY}, - {"ld1.c.clr.d5", M, OpMXX6aHintHlfa (4, 0, 0, 0x20, 1, 1), {R1, MR3}, = EMPTY}, - {"ld1.c.clr.d6", M, OpMXX6aHintHlfa (4, 0, 0, 0x20, 2, 1), {R1, MR3}, = EMPTY}, - {"ld1.c.clr.d7", M, OpMXX6aHintHlfa (4, 0, 0, 0x20, 3, 1), {R1, MR3}, = EMPTY}, - {"ld2.c.clr", M, OpMXX6aHintHlfa (4, 0, 0, 0x21, 0, 0), {R1, MR3}, EMP= TY}, - {"ld2.c.clr.nt1", M, OpMXX6aHintHlfa (4, 0, 0, 0x21, 1, 0), {R1, MR3},= EMPTY}, - {"ld2.c.clr.d1", M, OpMXX6aHintHlfa (4, 0, 0, 0x21, 1, 0), {R1, MR3}, = PSEUDO, 0, NULL}, - {"ld2.c.clr.d2", M, OpMXX6aHintHlfa (4, 0, 0, 0x21, 2, 0), {R1, MR3}, = EMPTY}, - {"ld2.c.clr.nt2", M, OpMXX6aHintHlfa (4, 0, 0, 0x21, 2, 0), {R1, MR3},= PSEUDO, 0, NULL}, - {"ld2.c.clr.nta", M, OpMXX6aHintHlfa (4, 0, 0, 0x21, 3, 0), {R1, MR3},= EMPTY}, - {"ld2.c.clr.d3", M, OpMXX6aHintHlfa (4, 0, 0, 0x21, 3, 0), {R1, MR3}, = PSEUDO, 0, NULL}, - {"ld2.c.clr.d4", M, OpMXX6aHintHlfa (4, 0, 0, 0x21, 0, 1), {R1, MR3}, = EMPTY}, - {"ld2.c.clr.d5", M, OpMXX6aHintHlfa (4, 0, 0, 0x21, 1, 1), {R1, MR3}, = EMPTY}, - {"ld2.c.clr.d6", M, OpMXX6aHintHlfa (4, 0, 0, 0x21, 2, 1), {R1, MR3}, = EMPTY}, - {"ld2.c.clr.d7", M, OpMXX6aHintHlfa (4, 0, 0, 0x21, 3, 1), {R1, MR3}, = EMPTY}, - {"ld4.c.clr", M, OpMXX6aHintHlfa (4, 0, 0, 0x22, 0, 0), {R1, MR3}, EMP= TY}, - {"ld4.c.clr.nt1", M, OpMXX6aHintHlfa (4, 0, 0, 0x22, 1, 0), {R1, MR3},= EMPTY}, - {"ld4.c.clr.d1", M, OpMXX6aHintHlfa (4, 0, 0, 0x22, 1, 0), {R1, MR3}, = PSEUDO, 0, NULL}, - {"ld4.c.clr.d2", M, OpMXX6aHintHlfa (4, 0, 0, 0x22, 2, 0), {R1, MR3}, = EMPTY}, - {"ld4.c.clr.nt2", M, OpMXX6aHintHlfa (4, 0, 0, 0x22, 2, 0), {R1, MR3},= PSEUDO, 0, NULL}, - {"ld4.c.clr.nta", M, OpMXX6aHintHlfa (4, 0, 0, 0x22, 3, 0), {R1, MR3},= EMPTY}, - {"ld4.c.clr.d3", M, OpMXX6aHintHlfa (4, 0, 0, 0x22, 3, 0), {R1, MR3}, = PSEUDO, 0, NULL}, - {"ld4.c.clr.d4", M, OpMXX6aHintHlfa (4, 0, 0, 0x22, 0, 1), {R1, MR3}, = EMPTY}, - {"ld4.c.clr.d5", M, OpMXX6aHintHlfa (4, 0, 0, 0x22, 1, 1), {R1, MR3}, = EMPTY}, - {"ld4.c.clr.d6", M, OpMXX6aHintHlfa (4, 0, 0, 0x22, 2, 1), {R1, MR3}, = EMPTY}, - {"ld4.c.clr.d7", M, OpMXX6aHintHlfa (4, 0, 0, 0x22, 3, 1), {R1, MR3}, = EMPTY}, - {"ld8.c.clr", M, OpMXX6aHintHlfa (4, 0, 0, 0x23, 0, 0), {R1, MR3}, EMP= TY}, - {"ld8.c.clr.nt1", M, OpMXX6aHintHlfa (4, 0, 0, 0x23, 1, 0), {R1, MR3},= EMPTY}, - {"ld8.c.clr.d1", M, OpMXX6aHintHlfa (4, 0, 0, 0x23, 1, 0), {R1, MR3}, = PSEUDO, 0, NULL}, - {"ld8.c.clr.d2", M, OpMXX6aHintHlfa (4, 0, 0, 0x23, 2, 0), {R1, MR3}, = EMPTY}, - {"ld8.c.clr.nt2", M, OpMXX6aHintHlfa (4, 0, 0, 0x23, 2, 0), {R1, MR3},= PSEUDO, 0, NULL}, - {"ld8.c.clr.nta", M, OpMXX6aHintHlfa (4, 0, 0, 0x23, 3, 0), {R1, MR3},= EMPTY}, - {"ld8.c.clr.d3", M, OpMXX6aHintHlfa (4, 0, 0, 0x23, 3, 0), {R1, MR3}, = PSEUDO, 0, NULL}, - {"ld8.c.clr.d4", M, OpMXX6aHintHlfa (4, 0, 0, 0x23, 0, 1), {R1, MR3}, = EMPTY}, - {"ld8.c.clr.d5", M, OpMXX6aHintHlfa (4, 0, 0, 0x23, 1, 1), {R1, MR3}, = EMPTY}, - {"ld8.c.clr.d6", M, OpMXX6aHintHlfa (4, 0, 0, 0x23, 2, 1), {R1, MR3}, = EMPTY}, - {"ld8.c.clr.d7", M, OpMXX6aHintHlfa (4, 0, 0, 0x23, 3, 1), {R1, MR3}, = EMPTY}, - {"ld1.c.nc", M, OpMXX6aHintHlfa (4, 0, 0, 0x24, 0, 0), {R1, MR3}, EMPT= Y}, - {"ld1.c.nc.nt1", M, OpMXX6aHintHlfa (4, 0, 0, 0x24, 1, 0), {R1, MR3}, = EMPTY}, - {"ld1.c.nc.d1", M, OpMXX6aHintHlfa (4, 0, 0, 0x24, 1, 0), {R1, MR3}, P= SEUDO, 0, NULL}, - {"ld1.c.nc.d2", M, OpMXX6aHintHlfa (4, 0, 0, 0x24, 2, 0), {R1, MR3}, E= MPTY}, - {"ld1.c.nc.nt2", M, OpMXX6aHintHlfa (4, 0, 0, 0x24, 2, 0), {R1, MR3}, = PSEUDO, 0, NULL}, - {"ld1.c.nc.nta", M, OpMXX6aHintHlfa (4, 0, 0, 0x24, 3, 0), {R1, MR3}, = EMPTY}, - {"ld1.c.nc.d3", M, OpMXX6aHintHlfa (4, 0, 0, 0x24, 3, 0), {R1, MR3}, P= SEUDO, 0, NULL}, - {"ld1.c.nc.d4", M, OpMXX6aHintHlfa (4, 0, 0, 0x24, 0, 1), {R1, MR3}, E= MPTY}, - {"ld1.c.nc.d5", M, OpMXX6aHintHlfa (4, 0, 0, 0x24, 1, 1), {R1, MR3}, E= MPTY}, - {"ld1.c.nc.d6", M, OpMXX6aHintHlfa (4, 0, 0, 0x24, 2, 1), {R1, MR3}, E= MPTY}, - {"ld1.c.nc.d7", M, OpMXX6aHintHlfa (4, 0, 0, 0x24, 3, 1), {R1, MR3}, E= MPTY}, - {"ld2.c.nc", M, OpMXX6aHintHlfa (4, 0, 0, 0x25, 0, 0), {R1, MR3}, EMPT= Y}, - {"ld2.c.nc.nt1", M, OpMXX6aHintHlfa (4, 0, 0, 0x25, 1, 0), {R1, MR3}, = EMPTY}, - {"ld2.c.nc.d1", M, OpMXX6aHintHlfa (4, 0, 0, 0x25, 1, 0), {R1, MR3}, P= SEUDO, 0, NULL}, - {"ld2.c.nc.d2", M, OpMXX6aHintHlfa (4, 0, 0, 0x25, 2, 0), {R1, MR3}, E= MPTY}, - {"ld2.c.nc.nt2", M, OpMXX6aHintHlfa (4, 0, 0, 0x25, 2, 0), {R1, MR3}, = PSEUDO, 0, NULL}, - {"ld2.c.nc.nta", M, OpMXX6aHintHlfa (4, 0, 0, 0x25, 3, 0), {R1, MR3}, = EMPTY}, - {"ld2.c.nc.d3", M, OpMXX6aHintHlfa (4, 0, 0, 0x25, 3, 0), {R1, MR3}, P= SEUDO, 0, NULL}, - {"ld2.c.nc.d4", M, OpMXX6aHintHlfa (4, 0, 0, 0x25, 0, 1), {R1, MR3}, E= MPTY}, - {"ld2.c.nc.d5", M, OpMXX6aHintHlfa (4, 0, 0, 0x25, 1, 1), {R1, MR3}, E= MPTY}, - {"ld2.c.nc.d6", M, OpMXX6aHintHlfa (4, 0, 0, 0x25, 2, 1), {R1, MR3}, E= MPTY}, - {"ld2.c.nc.d7", M, OpMXX6aHintHlfa (4, 0, 0, 0x25, 3, 1), {R1, MR3}, E= MPTY}, - {"ld4.c.nc", M, OpMXX6aHintHlfa (4, 0, 0, 0x26, 0, 0), {R1, MR3}, EMPT= Y}, - {"ld4.c.nc.nt1", M, OpMXX6aHintHlfa (4, 0, 0, 0x26, 1, 0), {R1, MR3}, = EMPTY}, - {"ld4.c.nc.d1", M, OpMXX6aHintHlfa (4, 0, 0, 0x26, 1, 0), {R1, MR3}, P= SEUDO, 0, NULL}, - {"ld4.c.nc.d2", M, OpMXX6aHintHlfa (4, 0, 0, 0x26, 2, 0), {R1, MR3}, E= MPTY}, - {"ld4.c.nc.nt2", M, OpMXX6aHintHlfa (4, 0, 0, 0x26, 2, 0), {R1, MR3}, = PSEUDO, 0, NULL}, - {"ld4.c.nc.nta", M, OpMXX6aHintHlfa (4, 0, 0, 0x26, 3, 0), {R1, MR3}, = EMPTY}, - {"ld4.c.nc.d3", M, OpMXX6aHintHlfa (4, 0, 0, 0x26, 3, 0), {R1, MR3}, P= SEUDO, 0, NULL}, - {"ld4.c.nc.d4", M, OpMXX6aHintHlfa (4, 0, 0, 0x26, 0, 1), {R1, MR3}, E= MPTY}, - {"ld4.c.nc.d5", M, OpMXX6aHintHlfa (4, 0, 0, 0x26, 1, 1), {R1, MR3}, E= MPTY}, - {"ld4.c.nc.d6", M, OpMXX6aHintHlfa (4, 0, 0, 0x26, 2, 1), {R1, MR3}, E= MPTY}, - {"ld4.c.nc.d7", M, OpMXX6aHintHlfa (4, 0, 0, 0x26, 3, 1), {R1, MR3}, E= MPTY}, - {"ld8.c.nc", M, OpMXX6aHintHlfa (4, 0, 0, 0x27, 0, 0), {R1, MR3}, EMPT= Y}, - {"ld8.c.nc.nt1", M, OpMXX6aHintHlfa (4, 0, 0, 0x27, 1, 0), {R1, MR3}, = EMPTY}, - {"ld8.c.nc.d1", M, OpMXX6aHintHlfa (4, 0, 0, 0x27, 1, 0), {R1, MR3}, P= SEUDO, 0, NULL}, - {"ld8.c.nc.d2", M, OpMXX6aHintHlfa (4, 0, 0, 0x27, 2, 0), {R1, MR3}, E= MPTY}, - {"ld8.c.nc.nt2", M, OpMXX6aHintHlfa (4, 0, 0, 0x27, 2, 0), {R1, MR3}, = PSEUDO, 0, NULL}, - {"ld8.c.nc.nta", M, OpMXX6aHintHlfa (4, 0, 0, 0x27, 3, 0), {R1, MR3}, = EMPTY}, - {"ld8.c.nc.d3", M, OpMXX6aHintHlfa (4, 0, 0, 0x27, 3, 0), {R1, MR3}, P= SEUDO, 0, NULL}, - {"ld8.c.nc.d4", M, OpMXX6aHintHlfa (4, 0, 0, 0x27, 0, 1), {R1, MR3}, E= MPTY}, - {"ld8.c.nc.d5", M, OpMXX6aHintHlfa (4, 0, 0, 0x27, 1, 1), {R1, MR3}, E= MPTY}, - {"ld8.c.nc.d6", M, OpMXX6aHintHlfa (4, 0, 0, 0x27, 2, 1), {R1, MR3}, E= MPTY}, - {"ld8.c.nc.d7", M, OpMXX6aHintHlfa (4, 0, 0, 0x27, 3, 1), {R1, MR3}, E= MPTY}, - {"ld1.c.clr.acq", M, OpMXX6aHintHlfa (4, 0, 0, 0x28, 0, 0), {R1, MR3= }, EMPTY}, - {"ld1.c.clr.acq.nt1", M, OpMXX6aHintHlfa (4, 0, 0, 0x28, 1, 0), {R1, M= R3}, EMPTY}, - {"ld1.c.clr.acq.d1", M, OpMXX6aHintHlfa (4, 0, 0, 0x28, 1, 0), {R1, MR= 3}, PSEUDO, 0, NULL}, - {"ld1.c.clr.acq.d2", M, OpMXX6aHintHlfa (4, 0, 0, 0x28, 2, 0), {R1, MR= 3}, EMPTY}, - {"ld1.c.clr.acq.nt2", M, OpMXX6aHintHlfa (4, 0, 0, 0x28, 2, 0), {R1, M= R3}, PSEUDO, 0, NULL}, - {"ld1.c.clr.acq.nta", M, OpMXX6aHintHlfa (4, 0, 0, 0x28, 3, 0), {R1, M= R3}, EMPTY}, - {"ld1.c.clr.acq.d3", M, OpMXX6aHintHlfa (4, 0, 0, 0x28, 3, 0), {R1, MR= 3}, PSEUDO, 0, NULL}, - {"ld1.c.clr.acq.d4", M, OpMXX6aHintHlfa (4, 0, 0, 0x28, 0, 1), {R1, MR= 3}, EMPTY}, - {"ld1.c.clr.acq.d5", M, OpMXX6aHintHlfa (4, 0, 0, 0x28, 1, 1), {R1, MR= 3}, EMPTY}, - {"ld1.c.clr.acq.d6", M, OpMXX6aHintHlfa (4, 0, 0, 0x28, 2, 1), {R1, MR= 3}, EMPTY}, - {"ld1.c.clr.acq.d7", M, OpMXX6aHintHlfa (4, 0, 0, 0x28, 3, 1), {R1, MR= 3}, EMPTY}, - {"ld2.c.clr.acq", M, OpMXX6aHintHlfa (4, 0, 0, 0x29, 0, 0), {R1, MR3= }, EMPTY}, - {"ld2.c.clr.acq.nt1", M, OpMXX6aHintHlfa (4, 0, 0, 0x29, 1, 0), {R1, M= R3}, EMPTY}, - {"ld2.c.clr.acq.d1", M, OpMXX6aHintHlfa (4, 0, 0, 0x29, 1, 0), {R1, MR= 3}, PSEUDO, 0, NULL}, - {"ld2.c.clr.acq.d2", M, OpMXX6aHintHlfa (4, 0, 0, 0x29, 2, 0), {R1, MR= 3}, EMPTY}, - {"ld2.c.clr.acq.nt2", M, OpMXX6aHintHlfa (4, 0, 0, 0x29, 2, 0), {R1, M= R3}, PSEUDO, 0, NULL}, - {"ld2.c.clr.acq.nta", M, OpMXX6aHintHlfa (4, 0, 0, 0x29, 3, 0), {R1, M= R3}, EMPTY}, - {"ld2.c.clr.acq.d3", M, OpMXX6aHintHlfa (4, 0, 0, 0x29, 3, 0), {R1, MR= 3}, PSEUDO, 0, NULL}, - {"ld2.c.clr.acq.d4", M, OpMXX6aHintHlfa (4, 0, 0, 0x29, 0, 1), {R1, MR= 3}, EMPTY}, - {"ld2.c.clr.acq.d5", M, OpMXX6aHintHlfa (4, 0, 0, 0x29, 1, 1), {R1, MR= 3}, EMPTY}, - {"ld2.c.clr.acq.d6", M, OpMXX6aHintHlfa (4, 0, 0, 0x29, 2, 1), {R1, MR= 3}, EMPTY}, - {"ld2.c.clr.acq.d7", M, OpMXX6aHintHlfa (4, 0, 0, 0x29, 3, 1), {R1, MR= 3}, EMPTY}, - {"ld4.c.clr.acq", M, OpMXX6aHintHlfa (4, 0, 0, 0x2a, 0, 0), {R1, MR3= }, EMPTY}, - {"ld4.c.clr.acq.nt1", M, OpMXX6aHintHlfa (4, 0, 0, 0x2a, 1, 0), {R1, M= R3}, EMPTY}, - {"ld4.c.clr.acq.d1", M, OpMXX6aHintHlfa (4, 0, 0, 0x2a, 1, 0), {R1, MR= 3}, PSEUDO, 0, NULL}, - {"ld4.c.clr.acq.d2", M, OpMXX6aHintHlfa (4, 0, 0, 0x2a, 2, 0), {R1, MR= 3}, EMPTY}, - {"ld4.c.clr.acq.nt2", M, OpMXX6aHintHlfa (4, 0, 0, 0x2a, 2, 0), {R1, M= R3}, PSEUDO, 0, NULL}, - {"ld4.c.clr.acq.nta", M, OpMXX6aHintHlfa (4, 0, 0, 0x2a, 3, 0), {R1, M= R3}, EMPTY}, - {"ld4.c.clr.acq.d3", M, OpMXX6aHintHlfa (4, 0, 0, 0x2a, 3, 0), {R1, MR= 3}, PSEUDO, 0, NULL}, - {"ld4.c.clr.acq.d4", M, OpMXX6aHintHlfa (4, 0, 0, 0x2a, 0, 1), {R1, MR= 3}, EMPTY}, - {"ld4.c.clr.acq.d5", M, OpMXX6aHintHlfa (4, 0, 0, 0x2a, 1, 1), {R1, MR= 3}, EMPTY}, - {"ld4.c.clr.acq.d6", M, OpMXX6aHintHlfa (4, 0, 0, 0x2a, 2, 1), {R1, MR= 3}, EMPTY}, - {"ld4.c.clr.acq.d7", M, OpMXX6aHintHlfa (4, 0, 0, 0x2a, 3, 1), {R1, MR= 3}, EMPTY}, - {"ld8.c.clr.acq", M, OpMXX6aHintHlfa (4, 0, 0, 0x2b, 0, 0), {R1, MR3= }, EMPTY}, - {"ld8.c.clr.acq.nt1", M, OpMXX6aHintHlfa (4, 0, 0, 0x2b, 1, 0), {R1, M= R3}, EMPTY}, - {"ld8.c.clr.acq.d1", M, OpMXX6aHintHlfa (4, 0, 0, 0x2b, 1, 0), {R1, MR= 3}, PSEUDO, 0, NULL}, - {"ld8.c.clr.acq.d2", M, OpMXX6aHintHlfa (4, 0, 0, 0x2b, 2, 0), {R1, MR= 3}, EMPTY}, - {"ld8.c.clr.acq.nt2", M, OpMXX6aHintHlfa (4, 0, 0, 0x2b, 2, 0), {R1, M= R3}, PSEUDO, 0, NULL}, - {"ld8.c.clr.acq.nta", M, OpMXX6aHintHlfa (4, 0, 0, 0x2b, 3, 0), {R1, M= R3}, EMPTY}, - {"ld8.c.clr.acq.d3", M, OpMXX6aHintHlfa (4, 0, 0, 0x2b, 3, 0), {R1, MR= 3}, PSEUDO, 0, NULL}, - {"ld8.c.clr.acq.d4", M, OpMXX6aHintHlfa (4, 0, 0, 0x2b, 0, 1), {R1, MR= 3}, EMPTY}, - {"ld8.c.clr.acq.d5", M, OpMXX6aHintHlfa (4, 0, 0, 0x2b, 1, 1), {R1, MR= 3}, EMPTY}, - {"ld8.c.clr.acq.d6", M, OpMXX6aHintHlfa (4, 0, 0, 0x2b, 2, 1), {R1, MR= 3}, EMPTY}, - {"ld8.c.clr.acq.d7", M, OpMXX6aHintHlfa (4, 0, 0, 0x2b, 3, 1), {R1, MR= 3}, EMPTY}, - {"ld16", M2, OpMXX6aHintHlfa (4, 0, 1, 0x28, 0, 0), {R1, AR_CSD, MR3}= , EMPTY}, - {"ld16", M, OpMXX6aHintHlfa (4, 0, 1, 0x28, 0, 0), {R1, MR3}, PSEUDO,= 0, NULL}, - {"ld16.nt1", M2, OpMXX6aHintHlfa (4, 0, 1, 0x28, 1, 0), {R1, AR_CSD, M= R3}, EMPTY}, - {"ld16.d1", M2, OpMXX6aHintHlfa (4, 0, 1, 0x28, 1, 0), {R1, AR_CSD, M= R3}, PSEUDO, 0, NULL}, - {"ld16.d2", M2, OpMXX6aHintHlfa (4, 0, 1, 0x28, 2, 0), {R1, AR_CSD, M= R3}, EMPTY}, - {"ld16.nt2", M2, OpMXX6aHintHlfa (4, 0, 1, 0x28, 2, 0), {R1, AR_CSD, M= R3}, PSEUDO, 0, NULL}, - {"ld16.nt1", M, OpMXX6aHintHlfa (4, 0, 1, 0x28, 1, 0), {R1, MR3}, PSEU= DO, 0, NULL}, - {"ld16.d1", M, OpMXX6aHintHlfa (4, 0, 1, 0x28, 1, 0), {R1, MR3}, PSEU= DO, 0, NULL}, - {"ld16.d2", M, OpMXX6aHintHlfa (4, 0, 1, 0x28, 2, 0), {R1, MR3}, PSEU= DO, 0, NULL}, - {"ld16.nt2", M, OpMXX6aHintHlfa (4, 0, 1, 0x28, 2, 0), {R1, MR3}, PSEU= DO, 0, NULL}, - {"ld16.nta", M2, OpMXX6aHintHlfa (4, 0, 1, 0x28, 3, 0), {R1, AR_CSD, M= R3}, EMPTY}, - {"ld16.d3", M2, OpMXX6aHintHlfa (4, 0, 1, 0x28, 3, 0), {R1, AR_CSD, M= R3}, PSEUDO, 0, NULL}, - {"ld16.d4", M2, OpMXX6aHintHlfa (4, 0, 1, 0x28, 0, 1), {R1, AR_CSD, M= R3}, EMPTY}, - {"ld16.d5", M2, OpMXX6aHintHlfa (4, 0, 1, 0x28, 1, 1), {R1, AR_CSD, M= R3}, EMPTY}, - {"ld16.d6", M2, OpMXX6aHintHlfa (4, 0, 1, 0x28, 2, 1), {R1, AR_CSD, M= R3}, EMPTY}, - {"ld16.d7", M2, OpMXX6aHintHlfa (4, 0, 1, 0x28, 3, 1), {R1, AR_CSD, M= R3}, EMPTY}, - {"ld16.nta", M, OpMXX6aHintHlfa (4, 0, 1, 0x28, 3, 0), {R1, MR3}, PSEU= DO, 0, NULL}, - {"ld16.d3", M, OpMXX6aHintHlfa (4, 0, 1, 0x28, 3, 0), {R1, MR3}, PSEU= DO, 0, NULL}, - {"ld16.d4", M, OpMXX6aHintHlfa (4, 0, 1, 0x28, 0, 1), {R1, MR3}, PSEU= DO, 0, NULL}, - {"ld16.d5", M, OpMXX6aHintHlfa (4, 0, 1, 0x28, 1, 1), {R1, MR3}, PSEU= DO, 0, NULL}, - {"ld16.d6", M, OpMXX6aHintHlfa (4, 0, 1, 0x28, 2, 1), {R1, MR3}, PSEU= DO, 0, NULL}, - {"ld16.d7", M, OpMXX6aHintHlfa (4, 0, 1, 0x28, 3, 1), {R1, MR3}, PSEU= DO, 0, NULL}, - {"ld16.acq", M2, OpMXX6aHintHlfa (4, 0, 1, 0x2c, 0, 0), {R1, AR_CSD, M= R3}, EMPTY}, - {"ld16.acq", M, OpMXX6aHintHlfa (4, 0, 1, 0x2c, 0, 0), {R1, MR3}, PSEU= DO, 0, NULL}, - {"ld16.acq.nt1", M2, OpMXX6aHintHlfa (4, 0, 1, 0x2c, 1, 0), {R1, AR_CS= D, MR3}, EMPTY}, - {"ld16.acq.d1", M2, OpMXX6aHintHlfa (4, 0, 1, 0x2c, 1, 0), {R1, AR_CSD= , MR3}, PSEUDO, 0, NULL}, - {"ld16.acq.d2", M2, OpMXX6aHintHlfa (4, 0, 1, 0x2c, 2, 0), {R1, AR_CSD= , MR3}, EMPTY}, - {"ld16.acq.nt2", M2, OpMXX6aHintHlfa (4, 0, 1, 0x2c, 2, 0), {R1, AR_CS= D, MR3}, PSEUDO, 0, NULL}, - {"ld16.acq.nt1", M, OpMXX6aHintHlfa (4, 0, 1, 0x2c, 1, 0), {R1, MR3}, = PSEUDO, 0, NULL}, - {"ld16.acq.d1", M, OpMXX6aHintHlfa (4, 0, 1, 0x2c, 1, 0), {R1, MR3}, P= SEUDO, 0, NULL}, - {"ld16.acq.d2", M, OpMXX6aHintHlfa (4, 0, 1, 0x2c, 2, 0), {R1, MR3}, P= SEUDO, 0, NULL}, - {"ld16.acq.nt2", M, OpMXX6aHintHlfa (4, 0, 1, 0x2c, 2, 0), {R1, MR3}, = PSEUDO, 0, NULL}, - {"ld16.acq.nta", M2, OpMXX6aHintHlfa (4, 0, 1, 0x2c, 3, 0), {R1, AR_CS= D, MR3}, EMPTY}, - {"ld16.acq.d3", M2, OpMXX6aHintHlfa (4, 0, 1, 0x2c, 3, 0), {R1, AR_CSD= , MR3}, PSEUDO, 0, NULL}, - {"ld16.acq.d4", M2, OpMXX6aHintHlfa (4, 0, 1, 0x2c, 0, 1), {R1, AR_CSD= , MR3}, EMPTY}, - {"ld16.acq.d5", M2, OpMXX6aHintHlfa (4, 0, 1, 0x2c, 1, 1), {R1, AR_CSD= , MR3}, EMPTY}, - {"ld16.acq.d6", M2, OpMXX6aHintHlfa (4, 0, 1, 0x2c, 2, 1), {R1, AR_CSD= , MR3}, EMPTY}, - {"ld16.acq.d7", M2, OpMXX6aHintHlfa (4, 0, 1, 0x2c, 3, 1), {R1, AR_CSD= , MR3}, EMPTY}, - {"ld16.acq.nta", M, OpMXX6aHintHlfa (4, 0, 1, 0x2c, 3, 0), {R1, MR3}, = PSEUDO, 0, NULL}, - {"ld16.acq.d3", M, OpMXX6aHintHlfa (4, 0, 1, 0x2c, 3, 0), {R1, MR3}, P= SEUDO, 0, NULL}, - {"ld16.acq.d4", M, OpMXX6aHintHlfa (4, 0, 1, 0x2c, 0, 1), {R1, MR3}, P= SEUDO, 0, NULL}, - {"ld16.acq.d5", M, OpMXX6aHintHlfa (4, 0, 1, 0x2c, 1, 1), {R1, MR3}, P= SEUDO, 0, NULL}, - {"ld16.acq.d6", M, OpMXX6aHintHlfa (4, 0, 1, 0x2c, 2, 1), {R1, MR3}, P= SEUDO, 0, NULL}, - {"ld16.acq.d7", M, OpMXX6aHintHlfa (4, 0, 1, 0x2c, 3, 1), {R1, MR3}, P= SEUDO, 0, NULL}, - - /* Pseudo-op that generates ldxmov relocation. */ - {"ld8.mov", M, OpMXX6aHint (4, 0, 0, 0x03, 0), - {R1, MR3, IA64_OPND_LDXMOV}, EMPTY}, -#endif - - /* Integer load w/increment by register. */ -#define LDINCREG(c,h) M, OpMXX6aHint (4, 1, 0, c, h), {R1, MR3, R2}, POSTI= NC, 0, NULL - {"ld1", LDINCREG (0x00, 0)}, - {"ld1.nt1", LDINCREG (0x00, 1)}, - {"ld1.nta", LDINCREG (0x00, 3)}, - {"ld2", LDINCREG (0x01, 0)}, - {"ld2.nt1", LDINCREG (0x01, 1)}, - {"ld2.nta", LDINCREG (0x01, 3)}, - {"ld4", LDINCREG (0x02, 0)}, - {"ld4.nt1", LDINCREG (0x02, 1)}, - {"ld4.nta", LDINCREG (0x02, 3)}, - {"ld8", LDINCREG (0x03, 0)}, - {"ld8.nt1", LDINCREG (0x03, 1)}, - {"ld8.nta", LDINCREG (0x03, 3)}, - {"ld1.s", LDINCREG (0x04, 0)}, - {"ld1.s.nt1", LDINCREG (0x04, 1)}, - {"ld1.s.nta", LDINCREG (0x04, 3)}, - {"ld2.s", LDINCREG (0x05, 0)}, - {"ld2.s.nt1", LDINCREG (0x05, 1)}, - {"ld2.s.nta", LDINCREG (0x05, 3)}, - {"ld4.s", LDINCREG (0x06, 0)}, - {"ld4.s.nt1", LDINCREG (0x06, 1)}, - {"ld4.s.nta", LDINCREG (0x06, 3)}, - {"ld8.s", LDINCREG (0x07, 0)}, - {"ld8.s.nt1", LDINCREG (0x07, 1)}, - {"ld8.s.nta", LDINCREG (0x07, 3)}, - {"ld1.a", LDINCREG (0x08, 0)}, - {"ld1.a.nt1", LDINCREG (0x08, 1)}, - {"ld1.a.nta", LDINCREG (0x08, 3)}, - {"ld2.a", LDINCREG (0x09, 0)}, - {"ld2.a.nt1", LDINCREG (0x09, 1)}, - {"ld2.a.nta", LDINCREG (0x09, 3)}, - {"ld4.a", LDINCREG (0x0a, 0)}, - {"ld4.a.nt1", LDINCREG (0x0a, 1)}, - {"ld4.a.nta", LDINCREG (0x0a, 3)}, - {"ld8.a", LDINCREG (0x0b, 0)}, - {"ld8.a.nt1", LDINCREG (0x0b, 1)}, - {"ld8.a.nta", LDINCREG (0x0b, 3)}, - {"ld1.sa", LDINCREG (0x0c, 0)}, - {"ld1.sa.nt1", LDINCREG (0x0c, 1)}, - {"ld1.sa.nta", LDINCREG (0x0c, 3)}, - {"ld2.sa", LDINCREG (0x0d, 0)}, - {"ld2.sa.nt1", LDINCREG (0x0d, 1)}, - {"ld2.sa.nta", LDINCREG (0x0d, 3)}, - {"ld4.sa", LDINCREG (0x0e, 0)}, - {"ld4.sa.nt1", LDINCREG (0x0e, 1)}, - {"ld4.sa.nta", LDINCREG (0x0e, 3)}, - {"ld8.sa", LDINCREG (0x0f, 0)}, - {"ld8.sa.nt1", LDINCREG (0x0f, 1)}, - {"ld8.sa.nta", LDINCREG (0x0f, 3)}, - {"ld1.bias", LDINCREG (0x10, 0)}, - {"ld1.bias.nt1", LDINCREG (0x10, 1)}, - {"ld1.bias.nta", LDINCREG (0x10, 3)}, - {"ld2.bias", LDINCREG (0x11, 0)}, - {"ld2.bias.nt1", LDINCREG (0x11, 1)}, - {"ld2.bias.nta", LDINCREG (0x11, 3)}, - {"ld4.bias", LDINCREG (0x12, 0)}, - {"ld4.bias.nt1", LDINCREG (0x12, 1)}, - {"ld4.bias.nta", LDINCREG (0x12, 3)}, - {"ld8.bias", LDINCREG (0x13, 0)}, - {"ld8.bias.nt1", LDINCREG (0x13, 1)}, - {"ld8.bias.nta", LDINCREG (0x13, 3)}, - {"ld1.acq", LDINCREG (0x14, 0)}, - {"ld1.acq.nt1", LDINCREG (0x14, 1)}, - {"ld1.acq.nta", LDINCREG (0x14, 3)}, - {"ld2.acq", LDINCREG (0x15, 0)}, - {"ld2.acq.nt1", LDINCREG (0x15, 1)}, - {"ld2.acq.nta", LDINCREG (0x15, 3)}, - {"ld4.acq", LDINCREG (0x16, 0)}, - {"ld4.acq.nt1", LDINCREG (0x16, 1)}, - {"ld4.acq.nta", LDINCREG (0x16, 3)}, - {"ld8.acq", LDINCREG (0x17, 0)}, - {"ld8.acq.nt1", LDINCREG (0x17, 1)}, - {"ld8.acq.nta", LDINCREG (0x17, 3)}, - {"ld8.fill", LDINCREG (0x1b, 0)}, - {"ld8.fill.nt1", LDINCREG (0x1b, 1)}, - {"ld8.fill.nta", LDINCREG (0x1b, 3)}, - {"ld1.c.clr", LDINCREG (0x20, 0)}, - {"ld1.c.clr.nt1", LDINCREG (0x20, 1)}, - {"ld1.c.clr.nta", LDINCREG (0x20, 3)}, - {"ld2.c.clr", LDINCREG (0x21, 0)}, - {"ld2.c.clr.nt1", LDINCREG (0x21, 1)}, - {"ld2.c.clr.nta", LDINCREG (0x21, 3)}, - {"ld4.c.clr", LDINCREG (0x22, 0)}, - {"ld4.c.clr.nt1", LDINCREG (0x22, 1)}, - {"ld4.c.clr.nta", LDINCREG (0x22, 3)}, - {"ld8.c.clr", LDINCREG (0x23, 0)}, - {"ld8.c.clr.nt1", LDINCREG (0x23, 1)}, - {"ld8.c.clr.nta", LDINCREG (0x23, 3)}, - {"ld1.c.nc", LDINCREG (0x24, 0)}, - {"ld1.c.nc.nt1", LDINCREG (0x24, 1)}, - {"ld1.c.nc.nta", LDINCREG (0x24, 3)}, - {"ld2.c.nc", LDINCREG (0x25, 0)}, - {"ld2.c.nc.nt1", LDINCREG (0x25, 1)}, - {"ld2.c.nc.nta", LDINCREG (0x25, 3)}, - {"ld4.c.nc", LDINCREG (0x26, 0)}, - {"ld4.c.nc.nt1", LDINCREG (0x26, 1)}, - {"ld4.c.nc.nta", LDINCREG (0x26, 3)}, - {"ld8.c.nc", LDINCREG (0x27, 0)}, - {"ld8.c.nc.nt1", LDINCREG (0x27, 1)}, - {"ld8.c.nc.nta", LDINCREG (0x27, 3)}, - {"ld1.c.clr.acq", LDINCREG (0x28, 0)}, - {"ld1.c.clr.acq.nt1", LDINCREG (0x28, 1)}, - {"ld1.c.clr.acq.nta", LDINCREG (0x28, 3)}, - {"ld2.c.clr.acq", LDINCREG (0x29, 0)}, - {"ld2.c.clr.acq.nt1", LDINCREG (0x29, 1)}, - {"ld2.c.clr.acq.nta", LDINCREG (0x29, 3)}, - {"ld4.c.clr.acq", LDINCREG (0x2a, 0)}, - {"ld4.c.clr.acq.nt1", LDINCREG (0x2a, 1)}, - {"ld4.c.clr.acq.nta", LDINCREG (0x2a, 3)}, - {"ld8.c.clr.acq", LDINCREG (0x2b, 0)}, - {"ld8.c.clr.acq.nt1", LDINCREG (0x2b, 1)}, - {"ld8.c.clr.acq.nta", LDINCREG (0x2b, 3)}, -#undef LDINCREG - -#if 0 -// old pre-psn variant with 2-bit hints; -// saved for reference - - {"st1", M, OpMXX6aHint (4, 0, 0, 0x30, 0), {MR3, R2}, EMPTY}, - {"st1.nta", M, OpMXX6aHint (4, 0, 0, 0x30, 3), {MR3, R2}, EMPTY}, - {"st2", M, OpMXX6aHint (4, 0, 0, 0x31, 0), {MR3, R2}, EMPTY}, - {"st2.nta", M, OpMXX6aHint (4, 0, 0, 0x31, 3), {MR3, R2}, EMPTY}, - {"st4", M, OpMXX6aHint (4, 0, 0, 0x32, 0), {MR3, R2}, EMPTY}, - {"st4.nta", M, OpMXX6aHint (4, 0, 0, 0x32, 3), {MR3, R2}, EMPTY}, - {"st8", M, OpMXX6aHint (4, 0, 0, 0x33, 0), {MR3, R2}, EMPTY}, - {"st8.nta", M, OpMXX6aHint (4, 0, 0, 0x33, 3), {MR3, R2}, EMPTY}, - {"st16", M, OpMXX6aHint (4, 0, 1, 0x30, 0), {MR3, R2, AR_CSD}, EMPTY}, - {"st16", M, OpMXX6aHint (4, 0, 1, 0x30, 0), {MR3, R2}, PSEUDO, 0, NUL= L}, - {"st16.nta", M, OpMXX6aHint (4, 0, 1, 0x30, 3), {MR3, R2, AR_CSD}, EMP= TY}, - {"st16.nta", M, OpMXX6aHint (4, 0, 1, 0x30, 3), {MR3, R2}, PSEUDO, 0, = NULL}, - {"st1.rel", M, OpMXX6aHint (4, 0, 0, 0x34, 0), {MR3, R2}, EMPTY}, - {"st1.rel.nta", M, OpMXX6aHint (4, 0, 0, 0x34, 3), {MR3, R2}, EMPTY}, - {"st2.rel", M, OpMXX6aHint (4, 0, 0, 0x35, 0), {MR3, R2}, EMPTY}, - {"st2.rel.nta", M, OpMXX6aHint (4, 0, 0, 0x35, 3), {MR3, R2}, EMPTY}, - {"st4.rel", M, OpMXX6aHint (4, 0, 0, 0x36, 0), {MR3, R2}, EMPTY}, - {"st4.rel.nta", M, OpMXX6aHint (4, 0, 0, 0x36, 3), {MR3, R2}, EMPTY}, - {"st8.rel", M, OpMXX6aHint (4, 0, 0, 0x37, 0), {MR3, R2}, EMPTY}, - {"st8.rel.nta", M, OpMXX6aHint (4, 0, 0, 0x37, 3), {MR3, R2}, EMPTY}, - {"st16.rel", M, OpMXX6aHint (4, 0, 1, 0x34, 0), {MR3, R2, AR_CSD}, EMP= TY}, - {"st16.rel", M, OpMXX6aHint (4, 0, 1, 0x34, 0), {MR3, R2}, PSEUDO, 0, = NULL}, - {"st16.rel.nta", M, OpMXX6aHint (4, 0, 1, 0x34, 3), {MR3, R2, AR_CSD},= EMPTY}, - {"st16.rel.nta", M, OpMXX6aHint (4, 0, 1, 0x34, 3), {MR3, R2}, PSEUDO,= 0, NULL}, - {"st8.spill", M, OpMXX6aHint (4, 0, 0, 0x3b, 0), {MR3, R2}, EMPTY}, - {"st8.spill.nta", M, OpMXX6aHint (4, 0, 0, 0x3b, 3), {MR3, R2}, EMPTY}, -#endif - - {"st1", M, OpMXX6aHintHlf (4, 0, 0, 0x30, 0, 0), {MR3, R2}, EMPTY}, - {"st1.d1", M, OpMXX6aHintHlf (4, 0, 0, 0x30, 1, 0), {MR3, R2}, EMPTY}, - {"st1.nt1", M, OpMXX6aHintHlf (4, 0, 0, 0x30, 1, 0), {MR3, R2}, PSEUD= O, 0, NULL}, - {"st1.d2", M, OpMXX6aHintHlf (4, 0, 0, 0x30, 2, 0), {MR3, R2}, EMPTY}, - {"st1.nt2", M, OpMXX6aHintHlf (4, 0, 0, 0x30, 2, 0), {MR3, R2}, PSEUD= O, 0, NULL}, - {"st1.nta", M, OpMXX6aHintHlf (4, 0, 0, 0x30, 3, 0), {MR3, R2}, EMPTY= }, - {"st1.d3", M, OpMXX6aHintHlf (4, 0, 0, 0x30, 3, 0), {MR3, R2}, PSEUDO= , 0, NULL}, - {"st1.d4", M, OpMXX6aHintHlf (4, 0, 0, 0x30, 0, 1), {MR3, R2}, EMPTY}, - {"st1.d5", M, OpMXX6aHintHlf (4, 0, 0, 0x30, 1, 1), {MR3, R2}, EMPTY}, - {"st1.d6", M, OpMXX6aHintHlf (4, 0, 0, 0x30, 2, 1), {MR3, R2}, EMPTY}, - {"st1.d7", M, OpMXX6aHintHlf (4, 0, 0, 0x30, 3, 1), {MR3, R2}, EMPTY}, - {"st2", M, OpMXX6aHintHlf (4, 0, 0, 0x31, 0, 0), {MR3, R2}, EMPTY}, - {"st2.d1", M, OpMXX6aHintHlf (4, 0, 0, 0x31, 1, 0), {MR3, R2}, EMPTY}, - {"st2.nt1", M, OpMXX6aHintHlf (4, 0, 0, 0x31, 1, 0), {MR3, R2}, PSEUD= O, 0, NULL}, - {"st2.d2", M, OpMXX6aHintHlf (4, 0, 0, 0x31, 2, 0), {MR3, R2}, EMPTY}, - {"st2.nt2", M, OpMXX6aHintHlf (4, 0, 0, 0x31, 2, 0), {MR3, R2}, PSEUD= O, 0, NULL}, - {"st2.nta", M, OpMXX6aHintHlf (4, 0, 0, 0x31, 3, 0), {MR3, R2}, EMPTY= }, - {"st2.d3", M, OpMXX6aHintHlf (4, 0, 0, 0x31, 3, 0), {MR3, R2}, PSEUDO= , 0, NULL}, - {"st2.d4", M, OpMXX6aHintHlf (4, 0, 0, 0x31, 0, 1), {MR3, R2}, EMPTY}, - {"st2.d5", M, OpMXX6aHintHlf (4, 0, 0, 0x31, 1, 1), {MR3, R2}, EMPTY}, - {"st2.d6", M, OpMXX6aHintHlf (4, 0, 0, 0x31, 2, 1), {MR3, R2}, EMPTY}, - {"st2.d7", M, OpMXX6aHintHlf (4, 0, 0, 0x31, 3, 1), {MR3, R2}, EMPTY}, - {"st4", M, OpMXX6aHintHlf (4, 0, 0, 0x32, 0, 0), {MR3, R2}, EMPTY}, - {"st4.d1", M, OpMXX6aHintHlf (4, 0, 0, 0x32, 1, 0), {MR3, R2}, EMPTY}, - {"st4.nt1", M, OpMXX6aHintHlf (4, 0, 0, 0x32, 1, 0), {MR3, R2}, PSEUD= O, 0, NULL}, - {"st4.d2", M, OpMXX6aHintHlf (4, 0, 0, 0x32, 2, 0), {MR3, R2}, EMPTY}, - {"st4.nt2", M, OpMXX6aHintHlf (4, 0, 0, 0x32, 2, 0), {MR3, R2}, PSEUD= O, 0, NULL}, - {"st4.nta", M, OpMXX6aHintHlf (4, 0, 0, 0x32, 3, 0), {MR3, R2}, EMPTY= }, - {"st4.d3", M, OpMXX6aHintHlf (4, 0, 0, 0x32, 3, 0), {MR3, R2}, PSEUDO= , 0, NULL}, - {"st4.d4", M, OpMXX6aHintHlf (4, 0, 0, 0x32, 0, 1), {MR3, R2}, EMPTY}, - {"st4.d5", M, OpMXX6aHintHlf (4, 0, 0, 0x32, 1, 1), {MR3, R2}, EMPTY}, - {"st4.d6", M, OpMXX6aHintHlf (4, 0, 0, 0x32, 2, 1), {MR3, R2}, EMPTY}, - {"st4.d7", M, OpMXX6aHintHlf (4, 0, 0, 0x32, 3, 1), {MR3, R2}, EMPTY}, - {"st8", M, OpMXX6aHintHlf (4, 0, 0, 0x33, 0, 0), {MR3, R2}, EMPTY}, - {"st8.d1", M, OpMXX6aHintHlf (4, 0, 0, 0x33, 1, 0), {MR3, R2}, EMPTY}, - {"st8.nt1", M, OpMXX6aHintHlf (4, 0, 0, 0x33, 1, 0), {MR3, R2}, PSEUD= O, 0, NULL}, - {"st8.d2", M, OpMXX6aHintHlf (4, 0, 0, 0x33, 2, 0), {MR3, R2}, EMPTY}, - {"st8.nt2", M, OpMXX6aHintHlf (4, 0, 0, 0x33, 2, 0), {MR3, R2}, PSEUD= O, 0, NULL}, - {"st8.nta", M, OpMXX6aHintHlf (4, 0, 0, 0x33, 3, 0), {MR3, R2}, EMPTY= }, - {"st8.d3", M, OpMXX6aHintHlf (4, 0, 0, 0x33, 3, 0), {MR3, R2}, PSEUDO= , 0, NULL}, - {"st8.d4", M, OpMXX6aHintHlf (4, 0, 0, 0x33, 0, 1), {MR3, R2}, EMPTY}, - {"st8.d5", M, OpMXX6aHintHlf (4, 0, 0, 0x33, 1, 1), {MR3, R2}, EMPTY}, - {"st8.d6", M, OpMXX6aHintHlf (4, 0, 0, 0x33, 2, 1), {MR3, R2}, EMPTY}, - {"st8.d7", M, OpMXX6aHintHlf (4, 0, 0, 0x33, 3, 1), {MR3, R2}, EMPTY}, - {"st16", M, OpMXX6aHintHlf (4, 0, 1, 0x30, 0, 0), {MR3, R2, AR_CSD}, = EMPTY}, - {"st16", M, OpMXX6aHintHlf (4, 0, 1, 0x30, 0, 0), {MR3, R2}, PSEUDO, = 0, NULL}, - {"st16.d1", M, OpMXX6aHintHlf (4, 0, 1, 0x30, 1, 0), {MR3, R2, AR_CSD= }, EMPTY}, - {"st16.d1", M, OpMXX6aHintHlf (4, 0, 1, 0x30, 1, 0), {MR3, R2}, PSEUD= O, 0, NULL}, - {"st16.nt1", M, OpMXX6aHintHlf (4, 0, 1, 0x30, 1, 0), {MR3, R2, AR_CSD= }, PSEUDO, 0, NULL}, - {"st16.nt1", M, OpMXX6aHintHlf (4, 0, 1, 0x30, 1, 0), {MR3, R2}, PSEUD= O, 0, NULL}, - {"st16.d2", M, OpMXX6aHintHlf (4, 0, 1, 0x30, 2, 0), {MR3, R2, AR_CSD= }, EMPTY}, - {"st16.d2", M, OpMXX6aHintHlf (4, 0, 1, 0x30, 2, 0), {MR3, R2}, PSEUD= O, 0, NULL}, - {"st16.nt2", M, OpMXX6aHintHlf (4, 0, 1, 0x30, 2, 0), {MR3, R2, AR_CSD= }, PSEUDO, 0, NULL}, - {"st16.nt2", M, OpMXX6aHintHlf (4, 0, 1, 0x30, 2, 0), {MR3, R2}, PSEUD= O, 0, NULL}, - {"st16.nta", M, OpMXX6aHintHlf (4, 0, 1, 0x30, 3, 0), {MR3, R2, AR_CSD= }, EMPTY}, - {"st16.d3", M, OpMXX6aHintHlf (4, 0, 1, 0x30, 3, 0), {MR3, R2, AR_CSD= }, PSEUDO, 0, NULL}, - {"st16.d4", M, OpMXX6aHintHlf (4, 0, 1, 0x30, 0, 1), {MR3, R2, AR_CSD= }, EMPTY}, - {"st16.d5", M, OpMXX6aHintHlf (4, 0, 1, 0x30, 1, 1), {MR3, R2, AR_CSD= }, EMPTY}, - {"st16.d6", M, OpMXX6aHintHlf (4, 0, 1, 0x30, 2, 1), {MR3, R2, AR_CSD= }, EMPTY}, - {"st16.d7", M, OpMXX6aHintHlf (4, 0, 1, 0x30, 3, 1), {MR3, R2, AR_CSD= }, EMPTY}, - {"st16.nta", M, OpMXX6aHintHlf (4, 0, 1, 0x30, 3, 0), {MR3, R2}, PSEUD= O, 0, NULL}, - {"st16.d3", M, OpMXX6aHintHlf (4, 0, 1, 0x30, 3, 0), {MR3, R2}, PSEUD= O, 0, NULL}, - {"st16.d4", M, OpMXX6aHintHlf (4, 0, 1, 0x30, 0, 1), {MR3, R2}, PSEUD= O, 0, NULL}, - {"st16.d5", M, OpMXX6aHintHlf (4, 0, 1, 0x30, 1, 1), {MR3, R2}, PSEUD= O, 0, NULL}, - {"st16.d6", M, OpMXX6aHintHlf (4, 0, 1, 0x30, 2, 1), {MR3, R2}, PSEUD= O, 0, NULL}, - {"st16.d7", M, OpMXX6aHintHlf (4, 0, 1, 0x30, 3, 1), {MR3, R2}, PSEUD= O, 0, NULL}, - {"st1.rel", M, OpMXX6aHintHlf (4, 0, 0, 0x34, 0, 0), {MR3, R2}, EMPTY= }, - {"st1.rel.d1", M, OpMXX6aHintHlf (4, 0, 0, 0x34, 1, 0), {MR3, R2}, EMP= TY}, - {"st1.rel.nt1", M, OpMXX6aHintHlf (4, 0, 0, 0x34, 1, 0), {MR3, R2}, PS= EUDO, 0, NULL}, - {"st1.rel.d2", M, OpMXX6aHintHlf (4, 0, 0, 0x34, 2, 0), {MR3, R2}, EMP= TY}, - {"st1.rel.nt2", M, OpMXX6aHintHlf (4, 0, 0, 0x34, 2, 0), {MR3, R2}, PS= EUDO, 0, NULL}, - {"st1.rel.nta", M, OpMXX6aHintHlf (4, 0, 0, 0x34, 3, 0), {MR3, R2}, EM= PTY}, - {"st1.rel.d3", M, OpMXX6aHintHlf (4, 0, 0, 0x34, 3, 0), {MR3, R2}, PSE= UDO, 0, NULL}, - {"st1.rel.d4", M, OpMXX6aHintHlf (4, 0, 0, 0x34, 0, 1), {MR3, R2}, EMP= TY}, - {"st1.rel.d5", M, OpMXX6aHintHlf (4, 0, 0, 0x34, 1, 1), {MR3, R2}, EMP= TY}, - {"st1.rel.d6", M, OpMXX6aHintHlf (4, 0, 0, 0x34, 2, 1), {MR3, R2}, EMP= TY}, - {"st1.rel.d7", M, OpMXX6aHintHlf (4, 0, 0, 0x34, 3, 1), {MR3, R2}, EMP= TY}, - {"st2.rel", M, OpMXX6aHintHlf (4, 0, 0, 0x35, 0, 0), {MR3, R2}, EMPTY= }, - {"st2.rel.d1", M, OpMXX6aHintHlf (4, 0, 0, 0x35, 1, 0), {MR3, R2}, EMP= TY}, - {"st2.rel.nt1", M, OpMXX6aHintHlf (4, 0, 0, 0x35, 1, 0), {MR3, R2}, PS= EUDO, 0, NULL}, - {"st2.rel.d2", M, OpMXX6aHintHlf (4, 0, 0, 0x35, 2, 0), {MR3, R2}, EMP= TY}, - {"st2.rel.nt2", M, OpMXX6aHintHlf (4, 0, 0, 0x35, 2, 0), {MR3, R2}, PS= EUDO, 0, NULL}, - {"st2.rel.nta", M, OpMXX6aHintHlf (4, 0, 0, 0x35, 3, 0), {MR3, R2}, EM= PTY}, - {"st2.rel.d3", M, OpMXX6aHintHlf (4, 0, 0, 0x35, 3, 0), {MR3, R2}, PSE= UDO, 0, NULL}, - {"st2.rel.d4", M, OpMXX6aHintHlf (4, 0, 0, 0x35, 0, 1), {MR3, R2}, EMP= TY}, - {"st2.rel.d5", M, OpMXX6aHintHlf (4, 0, 0, 0x35, 1, 1), {MR3, R2}, EMP= TY}, - {"st2.rel.d6", M, OpMXX6aHintHlf (4, 0, 0, 0x35, 2, 1), {MR3, R2}, EMP= TY}, - {"st2.rel.d7", M, OpMXX6aHintHlf (4, 0, 0, 0x35, 3, 1), {MR3, R2}, EMP= TY}, - {"st4.rel", M, OpMXX6aHintHlf (4, 0, 0, 0x36, 0, 0), {MR3, R2}, EMPTY= }, - {"st4.rel.d1", M, OpMXX6aHintHlf (4, 0, 0, 0x36, 1, 0), {MR3, R2}, EMP= TY}, - {"st4.rel.nt1", M, OpMXX6aHintHlf (4, 0, 0, 0x36, 1, 0), {MR3, R2}, PS= EUDO, 0, NULL}, - {"st4.rel.d2", M, OpMXX6aHintHlf (4, 0, 0, 0x36, 2, 0), {MR3, R2}, EMP= TY}, - {"st4.rel.nt2", M, OpMXX6aHintHlf (4, 0, 0, 0x36, 2, 0), {MR3, R2}, PS= EUDO, 0, NULL}, - {"st4.rel.nta", M, OpMXX6aHintHlf (4, 0, 0, 0x36, 3, 0), {MR3, R2}, EM= PTY}, - {"st4.rel.d3", M, OpMXX6aHintHlf (4, 0, 0, 0x36, 3, 0), {MR3, R2}, PSE= UDO, 0, NULL}, - {"st4.rel.d4", M, OpMXX6aHintHlf (4, 0, 0, 0x36, 0, 1), {MR3, R2}, EMP= TY}, - {"st4.rel.d5", M, OpMXX6aHintHlf (4, 0, 0, 0x36, 1, 1), {MR3, R2}, EMP= TY}, - {"st4.rel.d6", M, OpMXX6aHintHlf (4, 0, 0, 0x36, 2, 1), {MR3, R2}, EMP= TY}, - {"st4.rel.d7", M, OpMXX6aHintHlf (4, 0, 0, 0x36, 3, 1), {MR3, R2}, EMP= TY}, - {"st8.rel", M, OpMXX6aHintHlf (4, 0, 0, 0x37, 0, 0), {MR3, R2}, EMPTY= }, - {"st8.rel.d1", M, OpMXX6aHintHlf (4, 0, 0, 0x37, 1, 0), {MR3, R2}, EMP= TY}, - {"st8.rel.nt1", M, OpMXX6aHintHlf (4, 0, 0, 0x37, 1, 0), {MR3, R2}, PS= EUDO, 0, NULL}, - {"st8.rel.d2", M, OpMXX6aHintHlf (4, 0, 0, 0x37, 2, 0), {MR3, R2}, EMP= TY}, - {"st8.rel.nt2", M, OpMXX6aHintHlf (4, 0, 0, 0x37, 2, 0), {MR3, R2}, PS= EUDO, 0, NULL}, - {"st8.rel.nta", M, OpMXX6aHintHlf (4, 0, 0, 0x37, 3, 0), {MR3, R2}, EM= PTY}, - {"st8.rel.d3", M, OpMXX6aHintHlf (4, 0, 0, 0x37, 3, 0), {MR3, R2}, PSE= UDO, 0, NULL}, - {"st8.rel.d4", M, OpMXX6aHintHlf (4, 0, 0, 0x37, 0, 1), {MR3, R2}, EMP= TY}, - {"st8.rel.d5", M, OpMXX6aHintHlf (4, 0, 0, 0x37, 1, 1), {MR3, R2}, EMP= TY}, - {"st8.rel.d6", M, OpMXX6aHintHlf (4, 0, 0, 0x37, 2, 1), {MR3, R2}, EMP= TY}, - {"st8.rel.d7", M, OpMXX6aHintHlf (4, 0, 0, 0x37, 3, 1), {MR3, R2}, EMP= TY}, - {"st16.rel", M, OpMXX6aHintHlf (4, 0, 1, 0x34, 0, 0), {MR3, R2, AR_CSD= }, EMPTY}, - {"st16.rel", M, OpMXX6aHintHlf (4, 0, 1, 0x34, 0, 0), {MR3, R2}, PSEUD= O, 0, NULL}, - {"st16.rel.d1", M, OpMXX6aHintHlf (4, 0, 1, 0x34, 1, 0), {MR3, R2, AR_= CSD}, EMPTY}, - {"st16.rel.d1", M, OpMXX6aHintHlf (4, 0, 1, 0x34, 1, 0), {MR3, R2}, PS= EUDO, 0, NULL}, - {"st16.rel.nt1", M, OpMXX6aHintHlf (4, 0, 1, 0x34, 1, 0), {MR3, R2, AR= _CSD}, PSEUDO, 0, NULL}, - {"st16.rel.nt1", M, OpMXX6aHintHlf (4, 0, 1, 0x34, 1, 0), {MR3, R2}, P= SEUDO, 0, NULL}, - {"st16.rel.d2", M, OpMXX6aHintHlf (4, 0, 1, 0x34, 2, 0), {MR3, R2, AR_= CSD}, EMPTY}, - {"st16.rel.d2", M, OpMXX6aHintHlf (4, 0, 1, 0x34, 2, 0), {MR3, R2}, PS= EUDO, 0, NULL}, - {"st16.rel.nt2", M, OpMXX6aHintHlf (4, 0, 1, 0x34, 2, 0), {MR3, R2, AR= _CSD}, PSEUDO, 0, NULL}, - {"st16.rel.nt2", M, OpMXX6aHintHlf (4, 0, 1, 0x34, 2, 0), {MR3, R2}, P= SEUDO, 0, NULL}, - {"st16.rel.nta", M, OpMXX6aHintHlf (4, 0, 1, 0x34, 3, 0), {MR3, R2, AR= _CSD}, EMPTY}, - {"st16.rel.d3", M, OpMXX6aHintHlf (4, 0, 1, 0x34, 3, 0), {MR3, R2, AR_= CSD}, PSEUDO, 0, NULL}, - {"st16.rel.d4", M, OpMXX6aHintHlf (4, 0, 1, 0x34, 0, 1), {MR3, R2, AR_= CSD}, EMPTY}, - {"st16.rel.d5", M, OpMXX6aHintHlf (4, 0, 1, 0x34, 1, 1), {MR3, R2, AR_= CSD}, EMPTY}, - {"st16.rel.d6", M, OpMXX6aHintHlf (4, 0, 1, 0x34, 2, 1), {MR3, R2, AR_= CSD}, EMPTY}, - {"st16.rel.d7", M, OpMXX6aHintHlf (4, 0, 1, 0x34, 3, 1), {MR3, R2, AR_= CSD}, EMPTY}, - {"st16.rel.nta", M, OpMXX6aHintHlf (4, 0, 1, 0x34, 3, 0), {MR3, R2}, P= SEUDO, 0, NULL}, - {"st16.rel.d3", M, OpMXX6aHintHlf (4, 0, 1, 0x34, 3, 0), {MR3, R2}, PS= EUDO, 0, NULL}, - {"st16.rel.d4", M, OpMXX6aHintHlf (4, 0, 1, 0x34, 0, 1), {MR3, R2}, PS= EUDO, 0, NULL}, - {"st16.rel.d5", M, OpMXX6aHintHlf (4, 0, 1, 0x34, 1, 1), {MR3, R2}, PS= EUDO, 0, NULL}, - {"st16.rel.d6", M, OpMXX6aHintHlf (4, 0, 1, 0x34, 2, 1), {MR3, R2}, PS= EUDO, 0, NULL}, - {"st16.rel.d7", M, OpMXX6aHintHlf (4, 0, 1, 0x34, 3, 1), {MR3, R2}, PS= EUDO, 0, NULL}, - {"st8.spill", M, OpMXX6aHintHlf (4, 0, 0, 0x3b, 0, 0), {MR3, R2}, EMPT= Y}, - {"st8.spill.d1", M, OpMXX6aHintHlf (4, 0, 0, 0x3b, 1, 0), {MR3, R2}, E= MPTY}, - {"st8.spill.nt1", M, OpMXX6aHintHlf (4, 0, 0, 0x3b, 1, 0), {MR3, R2}, = PSEUDO, 0, NULL}, - {"st8.spill.d2", M, OpMXX6aHintHlf (4, 0, 0, 0x3b, 2, 0), {MR3, R2}, E= MPTY}, - {"st8.spill.nt2", M, OpMXX6aHintHlf (4, 0, 0, 0x3b, 2, 0), {MR3, R2}, = PSEUDO, 0, NULL}, - {"st8.spill.nta", M, OpMXX6aHintHlf (4, 0, 0, 0x3b, 3, 0), {MR3, R2}, = EMPTY}, - {"st8.spill.d3", M, OpMXX6aHintHlf (4, 0, 0, 0x3b, 3, 0), {MR3, R2}, P= SEUDO, 0, NULL}, - {"st8.spill.d4", M, OpMXX6aHintHlf (4, 0, 0, 0x3b, 0, 1), {MR3, R2}, E= MPTY}, - {"st8.spill.d5", M, OpMXX6aHintHlf (4, 0, 0, 0x3b, 1, 1), {MR3, R2}, E= MPTY}, - {"st8.spill.d6", M, OpMXX6aHintHlf (4, 0, 0, 0x3b, 2, 1), {MR3, R2}, E= MPTY}, - {"st8.spill.d7", M, OpMXX6aHintHlf (4, 0, 0, 0x3b, 3, 1), {MR3, R2}, E= MPTY}, - -#define CMPXCHG(c,h) M, OpMXX6aHint (4, 0, 1, c, h), {R1, MR3, R2, AR_CCV}= , EMPTY -#define CMPXCHG_P(c,h) M, OpMXX6aHint (4, 0, 1, c, h), {R1, MR3, R2}, PSEU= DO, 0, NULL -#define CMPXCHG16(c,h) M, OpMXX6aHint (4, 0, 1, c, h), {R1, MR3, R2, AR_CS= D, AR_CCV}, EMPTY -#define CMPXCHG16_P(c,h) M, OpMXX6aHint (4, 0, 1, c, h), {R1, MR3, R2}, PS= EUDO, 0, NULL -#define CMPXCHG_acq 0 -#define CMPXCHG_rel 4 -#define CMPXCHG_1 0 -#define CMPXCHG_2 1 -#define CMPXCHG_4 2 -#define CMPXCHG_8 3 -#define CMPXCHGn(n, s) \ - {"cmpxchg"#n"."#s, CMPXCHG (CMPXCHG_##n|CMPXCHG_##s, 0)}, \ - {"cmpxchg"#n"."#s, CMPXCHG_P (CMPXCHG_##n|CMPXCHG_##s, 0)}, \ - {"cmpxchg"#n"."#s".nt1", CMPXCHG (CMPXCHG_##n|CMPXCHG_##s, 1)}, \ - {"cmpxchg"#n"."#s".nt1", CMPXCHG_P (CMPXCHG_##n|CMPXCHG_##s, 1)}, \ - {"cmpxchg"#n"."#s".nta", CMPXCHG (CMPXCHG_##n|CMPXCHG_##s, 3)}, \ - {"cmpxchg"#n"."#s".nta", CMPXCHG_P (CMPXCHG_##n|CMPXCHG_##s, 3)} -#define CMP8XCHG16(s) \ - {"cmp8xchg16."#s, CMPXCHG16 (0x20|CMPXCHG_##s, 0)}, \ - {"cmp8xchg16."#s, CMPXCHG16_P (0x20|CMPXCHG_##s, 0)}, \ - {"cmp8xchg16."#s".nt1", CMPXCHG16 (0x20|CMPXCHG_##s, 1)}, \ - {"cmp8xchg16."#s".nt1", CMPXCHG16_P (0x20|CMPXCHG_##s, 1)}, \ - {"cmp8xchg16."#s".nta", CMPXCHG16 (0x20|CMPXCHG_##s, 3)}, \ - {"cmp8xchg16."#s".nta", CMPXCHG16_P (0x20|CMPXCHG_##s, 3)} -#define CMPXCHG_ALL(s) CMPXCHGn(1, s), \ - CMPXCHGn(2, s), \ - CMPXCHGn(4, s), \ - CMPXCHGn(8, s), \ - CMP8XCHG16(s) - CMPXCHG_ALL(acq), - CMPXCHG_ALL(rel), -#undef CMPXCHG -#undef CMPXCHG_P -#undef CMPXCHG16 -#undef CMPXCHG16_P -#undef CMPXCHG_acq -#undef CMPXCHG_rel -#undef CMPXCHG_1 -#undef CMPXCHG_2 -#undef CMPXCHG_4 -#undef CMPXCHG_8 -#undef CMPXCHGn -#undef CMPXCHG16 -#undef CMPXCHG_ALL - {"xchg1", M, OpMXX6aHint (4, 0, 1, 0x08, 0), {R1, MR3, R2}, EMPTY}, - {"xchg1.nt1", M, OpMXX6aHint (4, 0, 1, 0x08, 1), {R1, MR3, R2}, EMPT= Y}, - {"xchg1.nta", M, OpMXX6aHint (4, 0, 1, 0x08, 3), {R1, MR3, R2}, EMPT= Y}, - {"xchg2", M, OpMXX6aHint (4, 0, 1, 0x09, 0), {R1, MR3, R2}, EMPTY}, - {"xchg2.nt1", M, OpMXX6aHint (4, 0, 1, 0x09, 1), {R1, MR3, R2}, EMPT= Y}, - {"xchg2.nta", M, OpMXX6aHint (4, 0, 1, 0x09, 3), {R1, MR3, R2}, EMPT= Y}, - {"xchg4", M, OpMXX6aHint (4, 0, 1, 0x0a, 0), {R1, MR3, R2}, EMPTY}, - {"xchg4.nt1", M, OpMXX6aHint (4, 0, 1, 0x0a, 1), {R1, MR3, R2}, EMPT= Y}, - {"xchg4.nta", M, OpMXX6aHint (4, 0, 1, 0x0a, 3), {R1, MR3, R2}, EMPT= Y}, - {"xchg8", M, OpMXX6aHint (4, 0, 1, 0x0b, 0), {R1, MR3, R2}, EMPTY}, - {"xchg8.nt1", M, OpMXX6aHint (4, 0, 1, 0x0b, 1), {R1, MR3, R2}, EMPT= Y}, - {"xchg8.nta", M, OpMXX6aHint (4, 0, 1, 0x0b, 3), {R1, MR3, R2}, EMPT= Y}, - - {"fetchadd4.acq", M, OpMXX6aHint (4, 0, 1, 0x12, 0), {R1, MR3, INC3}= , EMPTY}, - {"fetchadd4.acq.nt1", M, OpMXX6aHint (4, 0, 1, 0x12, 1), {R1, MR3, INC= 3}, EMPTY}, - {"fetchadd4.acq.nta", M, OpMXX6aHint (4, 0, 1, 0x12, 3), {R1, MR3, INC= 3}, EMPTY}, - {"fetchadd8.acq", M, OpMXX6aHint (4, 0, 1, 0x13, 0), {R1, MR3, INC3}= , EMPTY}, - {"fetchadd8.acq.nt1", M, OpMXX6aHint (4, 0, 1, 0x13, 1), {R1, MR3, INC= 3}, EMPTY}, - {"fetchadd8.acq.nta", M, OpMXX6aHint (4, 0, 1, 0x13, 3), {R1, MR3, INC= 3}, EMPTY}, - {"fetchadd4.rel", M, OpMXX6aHint (4, 0, 1, 0x16, 0), {R1, MR3, INC3}= , EMPTY}, - {"fetchadd4.rel.nt1", M, OpMXX6aHint (4, 0, 1, 0x16, 1), {R1, MR3, INC= 3}, EMPTY}, - {"fetchadd4.rel.nta", M, OpMXX6aHint (4, 0, 1, 0x16, 3), {R1, MR3, INC= 3}, EMPTY}, - {"fetchadd8.rel", M, OpMXX6aHint (4, 0, 1, 0x17, 0), {R1, MR3, INC3}= , EMPTY}, - {"fetchadd8.rel.nt1", M, OpMXX6aHint (4, 0, 1, 0x17, 1), {R1, MR3, INC= 3}, EMPTY}, - {"fetchadd8.rel.nta", M, OpMXX6aHint (4, 0, 1, 0x17, 3), {R1, MR3, INC= 3}, EMPTY}, - - {"getf.sig", M, OpMXX6a (4, 0, 1, 0x1c), {R1, F2}, EMPTY}, - {"getf.exp", M, OpMXX6a (4, 0, 1, 0x1d), {R1, F2}, EMPTY}, - {"getf.s", M, OpMXX6a (4, 0, 1, 0x1e), {R1, F2}, EMPTY}, - {"getf.d", M, OpMXX6a (4, 0, 1, 0x1f), {R1, F2}, EMPTY}, - - /* Integer load w/increment by immediate. */ -#define LDINCIMMED(c,h) M, OpX6aHint (5, c, h), {R1, MR3, IMM9b}, POSTINC,= 0, NULL - {"ld1", LDINCIMMED (0x00, 0)}, - {"ld1.nt1", LDINCIMMED (0x00, 1)}, - {"ld1.nta", LDINCIMMED (0x00, 3)}, - {"ld2", LDINCIMMED (0x01, 0)}, - {"ld2.nt1", LDINCIMMED (0x01, 1)}, - {"ld2.nta", LDINCIMMED (0x01, 3)}, - {"ld4", LDINCIMMED (0x02, 0)}, - {"ld4.nt1", LDINCIMMED (0x02, 1)}, - {"ld4.nta", LDINCIMMED (0x02, 3)}, - {"ld8", LDINCIMMED (0x03, 0)}, - {"ld8.nt1", LDINCIMMED (0x03, 1)}, - {"ld8.nta", LDINCIMMED (0x03, 3)}, - {"ld1.s", LDINCIMMED (0x04, 0)}, - {"ld1.s.nt1", LDINCIMMED (0x04, 1)}, - {"ld1.s.nta", LDINCIMMED (0x04, 3)}, - {"ld2.s", LDINCIMMED (0x05, 0)}, - {"ld2.s.nt1", LDINCIMMED (0x05, 1)}, - {"ld2.s.nta", LDINCIMMED (0x05, 3)}, - {"ld4.s", LDINCIMMED (0x06, 0)}, - {"ld4.s.nt1", LDINCIMMED (0x06, 1)}, - {"ld4.s.nta", LDINCIMMED (0x06, 3)}, - {"ld8.s", LDINCIMMED (0x07, 0)}, - {"ld8.s.nt1", LDINCIMMED (0x07, 1)}, - {"ld8.s.nta", LDINCIMMED (0x07, 3)}, - {"ld1.a", LDINCIMMED (0x08, 0)}, - {"ld1.a.nt1", LDINCIMMED (0x08, 1)}, - {"ld1.a.nta", LDINCIMMED (0x08, 3)}, - {"ld2.a", LDINCIMMED (0x09, 0)}, - {"ld2.a.nt1", LDINCIMMED (0x09, 1)}, - {"ld2.a.nta", LDINCIMMED (0x09, 3)}, - {"ld4.a", LDINCIMMED (0x0a, 0)}, - {"ld4.a.nt1", LDINCIMMED (0x0a, 1)}, - {"ld4.a.nta", LDINCIMMED (0x0a, 3)}, - {"ld8.a", LDINCIMMED (0x0b, 0)}, - {"ld8.a.nt1", LDINCIMMED (0x0b, 1)}, - {"ld8.a.nta", LDINCIMMED (0x0b, 3)}, - {"ld1.sa", LDINCIMMED (0x0c, 0)}, - {"ld1.sa.nt1", LDINCIMMED (0x0c, 1)}, - {"ld1.sa.nta", LDINCIMMED (0x0c, 3)}, - {"ld2.sa", LDINCIMMED (0x0d, 0)}, - {"ld2.sa.nt1", LDINCIMMED (0x0d, 1)}, - {"ld2.sa.nta", LDINCIMMED (0x0d, 3)}, - {"ld4.sa", LDINCIMMED (0x0e, 0)}, - {"ld4.sa.nt1", LDINCIMMED (0x0e, 1)}, - {"ld4.sa.nta", LDINCIMMED (0x0e, 3)}, - {"ld8.sa", LDINCIMMED (0x0f, 0)}, - {"ld8.sa.nt1", LDINCIMMED (0x0f, 1)}, - {"ld8.sa.nta", LDINCIMMED (0x0f, 3)}, - {"ld1.bias", LDINCIMMED (0x10, 0)}, - {"ld1.bias.nt1", LDINCIMMED (0x10, 1)}, - {"ld1.bias.nta", LDINCIMMED (0x10, 3)}, - {"ld2.bias", LDINCIMMED (0x11, 0)}, - {"ld2.bias.nt1", LDINCIMMED (0x11, 1)}, - {"ld2.bias.nta", LDINCIMMED (0x11, 3)}, - {"ld4.bias", LDINCIMMED (0x12, 0)}, - {"ld4.bias.nt1", LDINCIMMED (0x12, 1)}, - {"ld4.bias.nta", LDINCIMMED (0x12, 3)}, - {"ld8.bias", LDINCIMMED (0x13, 0)}, - {"ld8.bias.nt1", LDINCIMMED (0x13, 1)}, - {"ld8.bias.nta", LDINCIMMED (0x13, 3)}, - {"ld1.acq", LDINCIMMED (0x14, 0)}, - {"ld1.acq.nt1", LDINCIMMED (0x14, 1)}, - {"ld1.acq.nta", LDINCIMMED (0x14, 3)}, - {"ld2.acq", LDINCIMMED (0x15, 0)}, - {"ld2.acq.nt1", LDINCIMMED (0x15, 1)}, - {"ld2.acq.nta", LDINCIMMED (0x15, 3)}, - {"ld4.acq", LDINCIMMED (0x16, 0)}, - {"ld4.acq.nt1", LDINCIMMED (0x16, 1)}, - {"ld4.acq.nta", LDINCIMMED (0x16, 3)}, - {"ld8.acq", LDINCIMMED (0x17, 0)}, - {"ld8.acq.nt1", LDINCIMMED (0x17, 1)}, - {"ld8.acq.nta", LDINCIMMED (0x17, 3)}, - {"ld8.fill", LDINCIMMED (0x1b, 0)}, - {"ld8.fill.nt1", LDINCIMMED (0x1b, 1)}, - {"ld8.fill.nta", LDINCIMMED (0x1b, 3)}, - {"ld1.c.clr", LDINCIMMED (0x20, 0)}, - {"ld1.c.clr.nt1", LDINCIMMED (0x20, 1)}, - {"ld1.c.clr.nta", LDINCIMMED (0x20, 3)}, - {"ld2.c.clr", LDINCIMMED (0x21, 0)}, - {"ld2.c.clr.nt1", LDINCIMMED (0x21, 1)}, - {"ld2.c.clr.nta", LDINCIMMED (0x21, 3)}, - {"ld4.c.clr", LDINCIMMED (0x22, 0)}, - {"ld4.c.clr.nt1", LDINCIMMED (0x22, 1)}, - {"ld4.c.clr.nta", LDINCIMMED (0x22, 3)}, - {"ld8.c.clr", LDINCIMMED (0x23, 0)}, - {"ld8.c.clr.nt1", LDINCIMMED (0x23, 1)}, - {"ld8.c.clr.nta", LDINCIMMED (0x23, 3)}, - {"ld1.c.nc", LDINCIMMED (0x24, 0)}, - {"ld1.c.nc.nt1", LDINCIMMED (0x24, 1)}, - {"ld1.c.nc.nta", LDINCIMMED (0x24, 3)}, - {"ld2.c.nc", LDINCIMMED (0x25, 0)}, - {"ld2.c.nc.nt1", LDINCIMMED (0x25, 1)}, - {"ld2.c.nc.nta", LDINCIMMED (0x25, 3)}, - {"ld4.c.nc", LDINCIMMED (0x26, 0)}, - {"ld4.c.nc.nt1", LDINCIMMED (0x26, 1)}, - {"ld4.c.nc.nta", LDINCIMMED (0x26, 3)}, - {"ld8.c.nc", LDINCIMMED (0x27, 0)}, - {"ld8.c.nc.nt1", LDINCIMMED (0x27, 1)}, - {"ld8.c.nc.nta", LDINCIMMED (0x27, 3)}, - {"ld1.c.clr.acq", LDINCIMMED (0x28, 0)}, - {"ld1.c.clr.acq.nt1", LDINCIMMED (0x28, 1)}, - {"ld1.c.clr.acq.nta", LDINCIMMED (0x28, 3)}, - {"ld2.c.clr.acq", LDINCIMMED (0x29, 0)}, - {"ld2.c.clr.acq.nt1", LDINCIMMED (0x29, 1)}, - {"ld2.c.clr.acq.nta", LDINCIMMED (0x29, 3)}, - {"ld4.c.clr.acq", LDINCIMMED (0x2a, 0)}, - {"ld4.c.clr.acq.nt1", LDINCIMMED (0x2a, 1)}, - {"ld4.c.clr.acq.nta", LDINCIMMED (0x2a, 3)}, - {"ld8.c.clr.acq", LDINCIMMED (0x2b, 0)}, - {"ld8.c.clr.acq.nt1", LDINCIMMED (0x2b, 1)}, - {"ld8.c.clr.acq.nta", LDINCIMMED (0x2b, 3)}, -#undef LDINCIMMED - - /* Store w/increment by immediate. */ -#define STINCIMMED(c,h) M, OpX6aHint (5, c, h), {MR3, R2, IMM9a}, POSTINC,= 0, NULL - {"st1", STINCIMMED (0x30, 0)}, - {"st1.nta", STINCIMMED (0x30, 3)}, - {"st2", STINCIMMED (0x31, 0)}, - {"st2.nta", STINCIMMED (0x31, 3)}, - {"st4", STINCIMMED (0x32, 0)}, - {"st4.nta", STINCIMMED (0x32, 3)}, - {"st8", STINCIMMED (0x33, 0)}, - {"st8.nta", STINCIMMED (0x33, 3)}, - {"st1.rel", STINCIMMED (0x34, 0)}, - {"st1.rel.nta", STINCIMMED (0x34, 3)}, - {"st2.rel", STINCIMMED (0x35, 0)}, - {"st2.rel.nta", STINCIMMED (0x35, 3)}, - {"st4.rel", STINCIMMED (0x36, 0)}, - {"st4.rel.nta", STINCIMMED (0x36, 3)}, - {"st8.rel", STINCIMMED (0x37, 0)}, - {"st8.rel.nta", STINCIMMED (0x37, 3)}, - {"st8.spill", STINCIMMED (0x3b, 0)}, - {"st8.spill.nta", STINCIMMED (0x3b, 3)}, -#undef STINCIMMED - -#if 0 -// old pre-psn variant with 2-bit hints; -// saved for reference - /* Floating-point load. */ - {"ldfs", M, OpMXX6aHint (6, 0, 0, 0x02, 0), {F1, MR3}, EMPTY}, - {"ldfs.nt1", M, OpMXX6aHint (6, 0, 0, 0x02, 1), {F1, MR3}, EMPTY}, - {"ldfs.nta", M, OpMXX6aHint (6, 0, 0, 0x02, 3), {F1, MR3}, EMPTY}, - {"ldfd", M, OpMXX6aHint (6, 0, 0, 0x03, 0), {F1, MR3}, EMPTY}, - {"ldfd.nt1", M, OpMXX6aHint (6, 0, 0, 0x03, 1), {F1, MR3}, EMPTY}, - {"ldfd.nta", M, OpMXX6aHint (6, 0, 0, 0x03, 3), {F1, MR3}, EMPTY}, - {"ldf8", M, OpMXX6aHint (6, 0, 0, 0x01, 0), {F1, MR3}, EMPTY}, - {"ldf8.nt1", M, OpMXX6aHint (6, 0, 0, 0x01, 1), {F1, MR3}, EMPTY}, - {"ldf8.nta", M, OpMXX6aHint (6, 0, 0, 0x01, 3), {F1, MR3}, EMPTY}, - {"ldfe", M, OpMXX6aHint (6, 0, 0, 0x00, 0), {F1, MR3}, EMPTY}, - {"ldfe.nt1", M, OpMXX6aHint (6, 0, 0, 0x00, 1), {F1, MR3}, EMPTY}, - {"ldfe.nta", M, OpMXX6aHint (6, 0, 0, 0x00, 3), {F1, MR3}, EMPTY}, - {"ldfs.s", M, OpMXX6aHint (6, 0, 0, 0x06, 0), {F1, MR3}, EMPTY}, - {"ldfs.s.nt1", M, OpMXX6aHint (6, 0, 0, 0x06, 1), {F1, MR3}, EMPTY}, - {"ldfs.s.nta", M, OpMXX6aHint (6, 0, 0, 0x06, 3), {F1, MR3}, EMPTY}, - {"ldfd.s", M, OpMXX6aHint (6, 0, 0, 0x07, 0), {F1, MR3}, EMPTY}, - {"ldfd.s.nt1", M, OpMXX6aHint (6, 0, 0, 0x07, 1), {F1, MR3}, EMPTY}, - {"ldfd.s.nta", M, OpMXX6aHint (6, 0, 0, 0x07, 3), {F1, MR3}, EMPTY}, - {"ldf8.s", M, OpMXX6aHint (6, 0, 0, 0x05, 0), {F1, MR3}, EMPTY}, - {"ldf8.s.nt1", M, OpMXX6aHint (6, 0, 0, 0x05, 1), {F1, MR3}, EMPTY}, - {"ldf8.s.nta", M, OpMXX6aHint (6, 0, 0, 0x05, 3), {F1, MR3}, EMPTY}, - {"ldfe.s", M, OpMXX6aHint (6, 0, 0, 0x04, 0), {F1, MR3}, EMPTY}, - {"ldfe.s.nt1", M, OpMXX6aHint (6, 0, 0, 0x04, 1), {F1, MR3}, EMPTY}, - {"ldfe.s.nta", M, OpMXX6aHint (6, 0, 0, 0x04, 3), {F1, MR3}, EMPTY}, - {"ldfs.a", M, OpMXX6aHint (6, 0, 0, 0x0a, 0), {F1, MR3}, EMPTY}, - {"ldfs.a.nt1", M, OpMXX6aHint (6, 0, 0, 0x0a, 1), {F1, MR3}, EMPTY}, - {"ldfs.a.nta", M, OpMXX6aHint (6, 0, 0, 0x0a, 3), {F1, MR3}, EMPTY}, - {"ldfd.a", M, OpMXX6aHint (6, 0, 0, 0x0b, 0), {F1, MR3}, EMPTY}, - {"ldfd.a.nt1", M, OpMXX6aHint (6, 0, 0, 0x0b, 1), {F1, MR3}, EMPTY}, - {"ldfd.a.nta", M, OpMXX6aHint (6, 0, 0, 0x0b, 3), {F1, MR3}, EMPTY}, - {"ldf8.a", M, OpMXX6aHint (6, 0, 0, 0x09, 0), {F1, MR3}, EMPTY}, - {"ldf8.a.nt1", M, OpMXX6aHint (6, 0, 0, 0x09, 1), {F1, MR3}, EMPTY}, - {"ldf8.a.nta", M, OpMXX6aHint (6, 0, 0, 0x09, 3), {F1, MR3}, EMPTY}, - {"ldfe.a", M, OpMXX6aHint (6, 0, 0, 0x08, 0), {F1, MR3}, EMPTY}, - {"ldfe.a.nt1", M, OpMXX6aHint (6, 0, 0, 0x08, 1), {F1, MR3}, EMPTY}, - {"ldfe.a.nta", M, OpMXX6aHint (6, 0, 0, 0x08, 3), {F1, MR3}, EMPTY}, - {"ldfs.sa", M, OpMXX6aHint (6, 0, 0, 0x0e, 0), {F1, MR3}, EMPTY}, - {"ldfs.sa.nt1", M, OpMXX6aHint (6, 0, 0, 0x0e, 1), {F1, MR3}, EMPTY}, - {"ldfs.sa.nta", M, OpMXX6aHint (6, 0, 0, 0x0e, 3), {F1, MR3}, EMPTY}, - {"ldfd.sa", M, OpMXX6aHint (6, 0, 0, 0x0f, 0), {F1, MR3}, EMPTY}, - {"ldfd.sa.nt1", M, OpMXX6aHint (6, 0, 0, 0x0f, 1), {F1, MR3}, EMPTY}, - {"ldfd.sa.nta", M, OpMXX6aHint (6, 0, 0, 0x0f, 3), {F1, MR3}, EMPTY}, - {"ldf8.sa", M, OpMXX6aHint (6, 0, 0, 0x0d, 0), {F1, MR3}, EMPTY}, - {"ldf8.sa.nt1", M, OpMXX6aHint (6, 0, 0, 0x0d, 1), {F1, MR3}, EMPTY}, - {"ldf8.sa.nta", M, OpMXX6aHint (6, 0, 0, 0x0d, 3), {F1, MR3}, EMPTY}, - {"ldfe.sa", M, OpMXX6aHint (6, 0, 0, 0x0c, 0), {F1, MR3}, EMPTY}, - {"ldfe.sa.nt1", M, OpMXX6aHint (6, 0, 0, 0x0c, 1), {F1, MR3}, EMPTY}, - {"ldfe.sa.nta", M, OpMXX6aHint (6, 0, 0, 0x0c, 3), {F1, MR3}, EMPTY}, - {"ldf.fill", M, OpMXX6aHint (6, 0, 0, 0x1b, 0), {F1, MR3}, EMPTY}, - {"ldf.fill.nt1", M, OpMXX6aHint (6, 0, 0, 0x1b, 1), {F1, MR3}, EMPTY}, - {"ldf.fill.nta", M, OpMXX6aHint (6, 0, 0, 0x1b, 3), {F1, MR3}, EMPTY}, - {"ldfs.c.clr", M, OpMXX6aHint (6, 0, 0, 0x22, 0), {F1, MR3}, EMPTY}, - {"ldfs.c.clr.nt1", M, OpMXX6aHint (6, 0, 0, 0x22, 1), {F1, MR3}, EMPTY= }, - {"ldfs.c.clr.nta", M, OpMXX6aHint (6, 0, 0, 0x22, 3), {F1, MR3}, EMPTY= }, - {"ldfd.c.clr", M, OpMXX6aHint (6, 0, 0, 0x23, 0), {F1, MR3}, EMPTY}, - {"ldfd.c.clr.nt1", M, OpMXX6aHint (6, 0, 0, 0x23, 1), {F1, MR3}, EMPTY= }, - {"ldfd.c.clr.nta", M, OpMXX6aHint (6, 0, 0, 0x23, 3), {F1, MR3}, EMPTY= }, - {"ldf8.c.clr", M, OpMXX6aHint (6, 0, 0, 0x21, 0), {F1, MR3}, EMPTY}, - {"ldf8.c.clr.nt1", M, OpMXX6aHint (6, 0, 0, 0x21, 1), {F1, MR3}, EMPTY= }, - {"ldf8.c.clr.nta", M, OpMXX6aHint (6, 0, 0, 0x21, 3), {F1, MR3}, EMPTY= }, - {"ldfe.c.clr", M, OpMXX6aHint (6, 0, 0, 0x20, 0), {F1, MR3}, EMPTY}, - {"ldfe.c.clr.nt1", M, OpMXX6aHint (6, 0, 0, 0x20, 1), {F1, MR3}, EMPTY= }, - {"ldfe.c.clr.nta", M, OpMXX6aHint (6, 0, 0, 0x20, 3), {F1, MR3}, EMPTY= }, - {"ldfs.c.nc", M, OpMXX6aHint (6, 0, 0, 0x26, 0), {F1, MR3}, EMPTY}, - {"ldfs.c.nc.nt1", M, OpMXX6aHint (6, 0, 0, 0x26, 1), {F1, MR3}, EMPTY}, - {"ldfs.c.nc.nta", M, OpMXX6aHint (6, 0, 0, 0x26, 3), {F1, MR3}, EMPTY}, - {"ldfd.c.nc", M, OpMXX6aHint (6, 0, 0, 0x27, 0), {F1, MR3}, EMPTY}, - {"ldfd.c.nc.nt1", M, OpMXX6aHint (6, 0, 0, 0x27, 1), {F1, MR3}, EMPTY}, - {"ldfd.c.nc.nta", M, OpMXX6aHint (6, 0, 0, 0x27, 3), {F1, MR3}, EMPTY}, - {"ldf8.c.nc", M, OpMXX6aHint (6, 0, 0, 0x25, 0), {F1, MR3}, EMPTY}, - {"ldf8.c.nc.nt1", M, OpMXX6aHint (6, 0, 0, 0x25, 1), {F1, MR3}, EMPTY}, - {"ldf8.c.nc.nta", M, OpMXX6aHint (6, 0, 0, 0x25, 3), {F1, MR3}, EMPTY}, - {"ldfe.c.nc", M, OpMXX6aHint (6, 0, 0, 0x24, 0), {F1, MR3}, EMPTY}, - {"ldfe.c.nc.nt1", M, OpMXX6aHint (6, 0, 0, 0x24, 1), {F1, MR3}, EMPTY}, - {"ldfe.c.nc.nta", M, OpMXX6aHint (6, 0, 0, 0x24, 3), {F1, MR3}, EMPTY}, -#endif - - /* Floating-point load. */ - {"ldfs", M, OpMXX6aHintHlfa (6, 0, 0, 0x02, 0, 0), {F1, MR3}, EMPTY}, - {"ldfs.nt1", M, OpMXX6aHintHlfa (6, 0, 0, 0x02, 1, 0), {F1, MR3}, EMPT= Y}, - {"ldfs.d1", M, OpMXX6aHintHlfa (6, 0, 0, 0x02, 1, 0), {F1, MR3}, PSEU= DO, 0, NULL}, - {"ldfs.d2", M, OpMXX6aHintHlfa (6, 0, 0, 0x02, 2, 0), {F1, MR3}, EMPT= Y}, - {"ldfs.nt2", M, OpMXX6aHintHlfa (6, 0, 0, 0x02, 2, 0), {F1, MR3}, PSEU= DO, 0, NULL}, - {"ldfs.nta", M, OpMXX6aHintHlfa (6, 0, 0, 0x02, 3, 0), {F1, MR3}, EMPT= Y}, - {"ldfs.d3", M, OpMXX6aHintHlfa (6, 0, 0, 0x02, 3, 0), {F1, MR3}, PSEU= DO, 0, NULL}, - {"ldfs.d4", M, OpMXX6aHintHlfa (6, 0, 0, 0x02, 0, 1), {F1, MR3}, EMPT= Y}, - {"ldfs.d5", M, OpMXX6aHintHlfa (6, 0, 0, 0x02, 1, 1), {F1, MR3}, EMPT= Y}, - {"ldfs.d6", M, OpMXX6aHintHlfa (6, 0, 0, 0x02, 2, 1), {F1, MR3}, EMPT= Y}, - {"ldfs.d7", M, OpMXX6aHintHlfa (6, 0, 0, 0x02, 3, 1), {F1, MR3}, EMPT= Y}, - {"ldfd", M, OpMXX6aHintHlfa (6, 0, 0, 0x03, 0, 0), {F1, MR3}, EMPTY}, - {"ldfd.nt1", M, OpMXX6aHintHlfa (6, 0, 0, 0x03, 1, 0), {F1, MR3}, EMPT= Y}, - {"ldfd.d1", M, OpMXX6aHintHlfa (6, 0, 0, 0x03, 1, 0), {F1, MR3}, PSEU= DO, 0, NULL}, - {"ldfd.d2", M, OpMXX6aHintHlfa (6, 0, 0, 0x03, 2, 0), {F1, MR3}, EMPT= Y}, - {"ldfd.nt2", M, OpMXX6aHintHlfa (6, 0, 0, 0x03, 2, 0), {F1, MR3}, PSEU= DO, 0, NULL}, - {"ldfd.nta", M, OpMXX6aHintHlfa (6, 0, 0, 0x03, 3, 0), {F1, MR3}, EMPT= Y}, - {"ldfd.d3", M, OpMXX6aHintHlfa (6, 0, 0, 0x03, 3, 0), {F1, MR3}, PSEU= DO, 0, NULL}, - {"ldfd.d4", M, OpMXX6aHintHlfa (6, 0, 0, 0x03, 0, 1), {F1, MR3}, EMPT= Y}, - {"ldfd.d5", M, OpMXX6aHintHlfa (6, 0, 0, 0x03, 1, 1), {F1, MR3}, EMPT= Y}, - {"ldfd.d6", M, OpMXX6aHintHlfa (6, 0, 0, 0x03, 2, 1), {F1, MR3}, EMPT= Y}, - {"ldfd.d7", M, OpMXX6aHintHlfa (6, 0, 0, 0x03, 3, 1), {F1, MR3}, EMPT= Y}, - {"ldf8", M, OpMXX6aHintHlfa (6, 0, 0, 0x01, 0, 0), {F1, MR3}, EMPTY}, - {"ldf8.nt1", M, OpMXX6aHintHlfa (6, 0, 0, 0x01, 1, 0), {F1, MR3}, EMPT= Y}, - {"ldf8.d1", M, OpMXX6aHintHlfa (6, 0, 0, 0x01, 1, 0), {F1, MR3}, PSEU= DO, 0, NULL}, - {"ldf8.d2", M, OpMXX6aHintHlfa (6, 0, 0, 0x01, 2, 0), {F1, MR3}, EMPT= Y}, - {"ldf8.nt2", M, OpMXX6aHintHlfa (6, 0, 0, 0x01, 2, 0), {F1, MR3}, PSEU= DO, 0, NULL}, - {"ldf8.nta", M, OpMXX6aHintHlfa (6, 0, 0, 0x01, 3, 0), {F1, MR3}, EMPT= Y}, - {"ldf8.d3", M, OpMXX6aHintHlfa (6, 0, 0, 0x01, 3, 0), {F1, MR3}, PSEU= DO, 0, NULL}, - {"ldf8.d4", M, OpMXX6aHintHlfa (6, 0, 0, 0x01, 0, 1), {F1, MR3}, EMPT= Y}, - {"ldf8.d5", M, OpMXX6aHintHlfa (6, 0, 0, 0x01, 1, 1), {F1, MR3}, EMPT= Y}, - {"ldf8.d6", M, OpMXX6aHintHlfa (6, 0, 0, 0x01, 2, 1), {F1, MR3}, EMPT= Y}, - {"ldf8.d7", M, OpMXX6aHintHlfa (6, 0, 0, 0x01, 3, 1), {F1, MR3}, EMPT= Y}, - {"ldfe", M, OpMXX6aHintHlfa (6, 0, 0, 0x00, 0, 0), {F1, MR3}, EMPTY}, - {"ldfe.nt1", M, OpMXX6aHintHlfa (6, 0, 0, 0x00, 1, 0), {F1, MR3}, EMPT= Y}, - {"ldfe.d1", M, OpMXX6aHintHlfa (6, 0, 0, 0x00, 1, 0), {F1, MR3}, PSEU= DO, 0, NULL}, - {"ldfe.d2", M, OpMXX6aHintHlfa (6, 0, 0, 0x00, 2, 0), {F1, MR3}, EMPT= Y}, - {"ldfe.nt2", M, OpMXX6aHintHlfa (6, 0, 0, 0x00, 2, 0), {F1, MR3}, PSEU= DO, 0, NULL}, - {"ldfe.nta", M, OpMXX6aHintHlfa (6, 0, 0, 0x00, 3, 0), {F1, MR3}, EMPT= Y}, - {"ldfe.d3", M, OpMXX6aHintHlfa (6, 0, 0, 0x00, 3, 0), {F1, MR3}, PSEU= DO, 0, NULL}, - {"ldfe.d4", M, OpMXX6aHintHlfa (6, 0, 0, 0x00, 0, 1), {F1, MR3}, EMPT= Y}, - {"ldfe.d5", M, OpMXX6aHintHlfa (6, 0, 0, 0x00, 1, 1), {F1, MR3}, EMPT= Y}, - {"ldfe.d6", M, OpMXX6aHintHlfa (6, 0, 0, 0x00, 2, 1), {F1, MR3}, EMPT= Y}, - {"ldfe.d7", M, OpMXX6aHintHlfa (6, 0, 0, 0x00, 3, 1), {F1, MR3}, EMPT= Y}, - {"ldfs.s", M, OpMXX6aHintHlfa (6, 0, 0, 0x06, 0, 0), {F1, MR3}, EMPTY= }, - {"ldfs.s.nt1", M, OpMXX6aHintHlfa (6, 0, 0, 0x06, 1, 0), {F1, MR3}, EM= PTY}, - {"ldfs.s.d1", M, OpMXX6aHintHlfa (6, 0, 0, 0x06, 1, 0), {F1, MR3}, PSE= UDO, 0, NULL}, - {"ldfs.s.d2", M, OpMXX6aHintHlfa (6, 0, 0, 0x06, 2, 0), {F1, MR3}, EMP= TY}, - {"ldfs.s.nt2", M, OpMXX6aHintHlfa (6, 0, 0, 0x06, 2, 0), {F1, MR3}, PS= EUDO, 0, NULL}, - {"ldfs.s.nta", M, OpMXX6aHintHlfa (6, 0, 0, 0x06, 3, 0), {F1, MR3}, EM= PTY}, - {"ldfs.s.d3", M, OpMXX6aHintHlfa (6, 0, 0, 0x06, 3, 0), {F1, MR3}, PSE= UDO, 0, NULL}, - {"ldfs.s.d4", M, OpMXX6aHintHlfa (6, 0, 0, 0x06, 0, 1), {F1, MR3}, EMP= TY}, - {"ldfs.s.d5", M, OpMXX6aHintHlfa (6, 0, 0, 0x06, 1, 1), {F1, MR3}, EMP= TY}, - {"ldfs.s.d6", M, OpMXX6aHintHlfa (6, 0, 0, 0x06, 2, 1), {F1, MR3}, EMP= TY}, - {"ldfs.s.d7", M, OpMXX6aHintHlfa (6, 0, 0, 0x06, 3, 1), {F1, MR3}, EMP= TY}, - {"ldfd.s", M, OpMXX6aHintHlfa (6, 0, 0, 0x07, 0, 0), {F1, MR3}, EMPTY= }, - {"ldfd.s.nt1", M, OpMXX6aHintHlfa (6, 0, 0, 0x07, 1, 0), {F1, MR3}, EM= PTY}, - {"ldfd.s.d1", M, OpMXX6aHintHlfa (6, 0, 0, 0x07, 1, 0), {F1, MR3}, PSE= UDO, 0, NULL}, - {"ldfd.s.d2", M, OpMXX6aHintHlfa (6, 0, 0, 0x07, 2, 0), {F1, MR3}, EMP= TY}, - {"ldfd.s.nt2", M, OpMXX6aHintHlfa (6, 0, 0, 0x07, 2, 0), {F1, MR3}, PS= EUDO, 0, NULL}, - {"ldfd.s.nta", M, OpMXX6aHintHlfa (6, 0, 0, 0x07, 3, 0), {F1, MR3}, EM= PTY}, - {"ldfd.s.d3", M, OpMXX6aHintHlfa (6, 0, 0, 0x07, 3, 0), {F1, MR3}, PSE= UDO, 0, NULL}, - {"ldfd.s.d4", M, OpMXX6aHintHlfa (6, 0, 0, 0x07, 0, 1), {F1, MR3}, EMP= TY}, - {"ldfd.s.d5", M, OpMXX6aHintHlfa (6, 0, 0, 0x07, 1, 1), {F1, MR3}, EMP= TY}, - {"ldfd.s.d6", M, OpMXX6aHintHlfa (6, 0, 0, 0x07, 2, 1), {F1, MR3}, EMP= TY}, - {"ldfd.s.d7", M, OpMXX6aHintHlfa (6, 0, 0, 0x07, 3, 1), {F1, MR3}, EMP= TY}, - {"ldf8.s", M, OpMXX6aHintHlfa (6, 0, 0, 0x05, 0, 0), {F1, MR3}, EMPTY= }, - {"ldf8.s.nt1", M, OpMXX6aHintHlfa (6, 0, 0, 0x05, 1, 0), {F1, MR3}, EM= PTY}, - {"ldf8.s.d1", M, OpMXX6aHintHlfa (6, 0, 0, 0x05, 1, 0), {F1, MR3}, PSE= UDO, 0, NULL}, - {"ldf8.s.d2", M, OpMXX6aHintHlfa (6, 0, 0, 0x05, 2, 0), {F1, MR3}, EMP= TY}, - {"ldf8.s.nt2", M, OpMXX6aHintHlfa (6, 0, 0, 0x05, 2, 0), {F1, MR3}, PS= EUDO, 0, NULL}, - {"ldf8.s.nta", M, OpMXX6aHintHlfa (6, 0, 0, 0x05, 3, 0), {F1, MR3}, EM= PTY}, - {"ldf8.s.d3", M, OpMXX6aHintHlfa (6, 0, 0, 0x05, 3, 0), {F1, MR3}, PSE= UDO, 0, NULL}, - {"ldf8.s.d4", M, OpMXX6aHintHlfa (6, 0, 0, 0x05, 0, 1), {F1, MR3}, EMP= TY}, - {"ldf8.s.d5", M, OpMXX6aHintHlfa (6, 0, 0, 0x05, 1, 1), {F1, MR3}, EMP= TY}, - {"ldf8.s.d6", M, OpMXX6aHintHlfa (6, 0, 0, 0x05, 2, 1), {F1, MR3}, EMP= TY}, - {"ldf8.s.d7", M, OpMXX6aHintHlfa (6, 0, 0, 0x05, 3, 1), {F1, MR3}, EMP= TY}, - {"ldfe.s", M, OpMXX6aHintHlfa (6, 0, 0, 0x04, 0, 0), {F1, MR3}, EMPTY= }, - {"ldfe.s.nt1", M, OpMXX6aHintHlfa (6, 0, 0, 0x04, 1, 0), {F1, MR3}, EM= PTY}, - {"ldfe.s.d1", M, OpMXX6aHintHlfa (6, 0, 0, 0x04, 1, 0), {F1, MR3}, PSE= UDO, 0, NULL}, - {"ldfe.s.d2", M, OpMXX6aHintHlfa (6, 0, 0, 0x04, 2, 0), {F1, MR3}, EMP= TY}, - {"ldfe.s.nt2", M, OpMXX6aHintHlfa (6, 0, 0, 0x04, 2, 0), {F1, MR3}, PS= EUDO, 0, NULL}, - {"ldfe.s.nta", M, OpMXX6aHintHlfa (6, 0, 0, 0x04, 3, 0), {F1, MR3}, EM= PTY}, - {"ldfe.s.d3", M, OpMXX6aHintHlfa (6, 0, 0, 0x04, 3, 0), {F1, MR3}, PSE= UDO, 0, NULL}, - {"ldfe.s.d4", M, OpMXX6aHintHlfa (6, 0, 0, 0x04, 0, 1), {F1, MR3}, EMP= TY}, - {"ldfe.s.d5", M, OpMXX6aHintHlfa (6, 0, 0, 0x04, 1, 1), {F1, MR3}, EMP= TY}, - {"ldfe.s.d6", M, OpMXX6aHintHlfa (6, 0, 0, 0x04, 2, 1), {F1, MR3}, EMP= TY}, - {"ldfe.s.d7", M, OpMXX6aHintHlfa (6, 0, 0, 0x04, 3, 1), {F1, MR3}, EMP= TY}, - {"ldfs.a", M, OpMXX6aHintHlfa (6, 0, 0, 0x0a, 0, 0), {F1, MR3}, EMPTY= }, - {"ldfs.a.nt1", M, OpMXX6aHintHlfa (6, 0, 0, 0x0a, 1, 0), {F1, MR3}, EM= PTY}, - {"ldfs.a.d1", M, OpMXX6aHintHlfa (6, 0, 0, 0x0a, 1, 0), {F1, MR3}, PSE= UDO, 0, NULL}, - {"ldfs.a.d2", M, OpMXX6aHintHlfa (6, 0, 0, 0x0a, 2, 0), {F1, MR3}, EMP= TY}, - {"ldfs.a.nt2", M, OpMXX6aHintHlfa (6, 0, 0, 0x0a, 2, 0), {F1, MR3}, PS= EUDO, 0, NULL}, - {"ldfs.a.nta", M, OpMXX6aHintHlfa (6, 0, 0, 0x0a, 3, 0), {F1, MR3}, EM= PTY}, - {"ldfs.a.d3", M, OpMXX6aHintHlfa (6, 0, 0, 0x0a, 3, 0), {F1, MR3}, PSE= UDO, 0, NULL}, - {"ldfs.a.d4", M, OpMXX6aHintHlfa (6, 0, 0, 0x0a, 0, 1), {F1, MR3}, EMP= TY}, - {"ldfs.a.d5", M, OpMXX6aHintHlfa (6, 0, 0, 0x0a, 1, 1), {F1, MR3}, EMP= TY}, - {"ldfs.a.d6", M, OpMXX6aHintHlfa (6, 0, 0, 0x0a, 2, 1), {F1, MR3}, EMP= TY}, - {"ldfs.a.d7", M, OpMXX6aHintHlfa (6, 0, 0, 0x0a, 3, 1), {F1, MR3}, EMP= TY}, - {"ldfd.a", M, OpMXX6aHintHlfa (6, 0, 0, 0x0b, 0, 0), {F1, MR3}, EMPTY= }, - {"ldfd.a.nt1", M, OpMXX6aHintHlfa (6, 0, 0, 0x0b, 1, 0), {F1, MR3}, EM= PTY}, - {"ldfd.a.d1", M, OpMXX6aHintHlfa (6, 0, 0, 0x0b, 1, 0), {F1, MR3}, PSE= UDO, 0, NULL}, - {"ldfd.a.d2", M, OpMXX6aHintHlfa (6, 0, 0, 0x0b, 2, 0), {F1, MR3}, EMP= TY}, - {"ldfd.a.nt2", M, OpMXX6aHintHlfa (6, 0, 0, 0x0b, 2, 0), {F1, MR3}, PS= EUDO, 0, NULL}, - {"ldfd.a.nta", M, OpMXX6aHintHlfa (6, 0, 0, 0x0b, 3, 0), {F1, MR3}, EM= PTY}, - {"ldfd.a.d3", M, OpMXX6aHintHlfa (6, 0, 0, 0x0b, 3, 0), {F1, MR3}, PSE= UDO, 0, NULL}, - {"ldfd.a.d4", M, OpMXX6aHintHlfa (6, 0, 0, 0x0b, 0, 1), {F1, MR3}, EMP= TY}, - {"ldfd.a.d5", M, OpMXX6aHintHlfa (6, 0, 0, 0x0b, 1, 1), {F1, MR3}, EMP= TY}, - {"ldfd.a.d6", M, OpMXX6aHintHlfa (6, 0, 0, 0x0b, 2, 1), {F1, MR3}, EMP= TY}, - {"ldfd.a.d7", M, OpMXX6aHintHlfa (6, 0, 0, 0x0b, 3, 1), {F1, MR3}, EMP= TY}, - {"ldf8.a", M, OpMXX6aHintHlfa (6, 0, 0, 0x09, 0, 0), {F1, MR3}, EMPTY= }, - {"ldf8.a.nt1", M, OpMXX6aHintHlfa (6, 0, 0, 0x09, 1, 0), {F1, MR3}, EM= PTY}, - {"ldf8.a.d1", M, OpMXX6aHintHlfa (6, 0, 0, 0x09, 1, 0), {F1, MR3}, PSE= UDO, 0, NULL}, - {"ldf8.a.d2", M, OpMXX6aHintHlfa (6, 0, 0, 0x09, 2, 0), {F1, MR3}, EMP= TY}, - {"ldf8.a.nt2", M, OpMXX6aHintHlfa (6, 0, 0, 0x09, 2, 0), {F1, MR3}, PS= EUDO, 0, NULL}, - {"ldf8.a.nta", M, OpMXX6aHintHlfa (6, 0, 0, 0x09, 3, 0), {F1, MR3}, EM= PTY}, - {"ldf8.a.d3", M, OpMXX6aHintHlfa (6, 0, 0, 0x09, 3, 0), {F1, MR3}, PSE= UDO, 0, NULL}, - {"ldf8.a.d4", M, OpMXX6aHintHlfa (6, 0, 0, 0x09, 0, 1), {F1, MR3}, EMP= TY}, - {"ldf8.a.d5", M, OpMXX6aHintHlfa (6, 0, 0, 0x09, 1, 1), {F1, MR3}, EMP= TY}, - {"ldf8.a.d6", M, OpMXX6aHintHlfa (6, 0, 0, 0x09, 2, 1), {F1, MR3}, EMP= TY}, - {"ldf8.a.d7", M, OpMXX6aHintHlfa (6, 0, 0, 0x09, 3, 1), {F1, MR3}, EMP= TY}, - {"ldfe.a", M, OpMXX6aHintHlfa (6, 0, 0, 0x08, 0, 0), {F1, MR3}, EMPTY= }, - {"ldfe.a.nt1", M, OpMXX6aHintHlfa (6, 0, 0, 0x08, 1, 0), {F1, MR3}, EM= PTY}, - {"ldfe.a.d1", M, OpMXX6aHintHlfa (6, 0, 0, 0x08, 1, 0), {F1, MR3}, PSE= UDO, 0, NULL}, - {"ldfe.a.d2", M, OpMXX6aHintHlfa (6, 0, 0, 0x08, 2, 0), {F1, MR3}, EMP= TY}, - {"ldfe.a.nt2", M, OpMXX6aHintHlfa (6, 0, 0, 0x08, 2, 0), {F1, MR3}, PS= EUDO, 0, NULL}, - {"ldfe.a.nta", M, OpMXX6aHintHlfa (6, 0, 0, 0x08, 3, 0), {F1, MR3}, EM= PTY}, - {"ldfe.a.d3", M, OpMXX6aHintHlfa (6, 0, 0, 0x08, 3, 0), {F1, MR3}, PSE= UDO, 0, NULL}, - {"ldfe.a.d4", M, OpMXX6aHintHlfa (6, 0, 0, 0x08, 0, 1), {F1, MR3}, EMP= TY}, - {"ldfe.a.d5", M, OpMXX6aHintHlfa (6, 0, 0, 0x08, 1, 1), {F1, MR3}, EMP= TY}, - {"ldfe.a.d6", M, OpMXX6aHintHlfa (6, 0, 0, 0x08, 2, 1), {F1, MR3}, EMP= TY}, - {"ldfe.a.d7", M, OpMXX6aHintHlfa (6, 0, 0, 0x08, 3, 1), {F1, MR3}, EMP= TY}, - {"ldfs.sa", M, OpMXX6aHintHlfa (6, 0, 0, 0x0e, 0, 0), {F1, MR3}, EMPT= Y}, - {"ldfs.sa.nt1", M, OpMXX6aHintHlfa (6, 0, 0, 0x0e, 1, 0), {F1, MR3}, E= MPTY}, - {"ldfs.sa.d1", M, OpMXX6aHintHlfa (6, 0, 0, 0x0e, 1, 0), {F1, MR3}, PS= EUDO, 0, NULL}, - {"ldfs.sa.d2", M, OpMXX6aHintHlfa (6, 0, 0, 0x0e, 2, 0), {F1, MR3}, EM= PTY}, - {"ldfs.sa.nt2", M, OpMXX6aHintHlfa (6, 0, 0, 0x0e, 2, 0), {F1, MR3}, P= SEUDO, 0, NULL}, - {"ldfs.sa.nta", M, OpMXX6aHintHlfa (6, 0, 0, 0x0e, 3, 0), {F1, MR3}, E= MPTY}, - {"ldfs.sa.d3", M, OpMXX6aHintHlfa (6, 0, 0, 0x0e, 3, 0), {F1, MR3}, PS= EUDO, 0, NULL}, - {"ldfs.sa.d4", M, OpMXX6aHintHlfa (6, 0, 0, 0x0e, 0, 1), {F1, MR3}, EM= PTY}, - {"ldfs.sa.d5", M, OpMXX6aHintHlfa (6, 0, 0, 0x0e, 1, 1), {F1, MR3}, EM= PTY}, - {"ldfs.sa.d6", M, OpMXX6aHintHlfa (6, 0, 0, 0x0e, 2, 1), {F1, MR3}, EM= PTY}, - {"ldfs.sa.d7", M, OpMXX6aHintHlfa (6, 0, 0, 0x0e, 3, 1), {F1, MR3}, EM= PTY}, - {"ldfd.sa", M, OpMXX6aHintHlfa (6, 0, 0, 0x0f, 0, 0), {F1, MR3}, EMPT= Y}, - {"ldfd.sa.nt1", M, OpMXX6aHintHlfa (6, 0, 0, 0x0f, 1, 0), {F1, MR3}, E= MPTY}, - {"ldfd.sa.d1", M, OpMXX6aHintHlfa (6, 0, 0, 0x0f, 1, 0), {F1, MR3}, PS= EUDO, 0, NULL}, - {"ldfd.sa.d2", M, OpMXX6aHintHlfa (6, 0, 0, 0x0f, 2, 0), {F1, MR3}, EM= PTY}, - {"ldfd.sa.nt2", M, OpMXX6aHintHlfa (6, 0, 0, 0x0f, 2, 0), {F1, MR3}, P= SEUDO, 0, NULL}, - {"ldfd.sa.nta", M, OpMXX6aHintHlfa (6, 0, 0, 0x0f, 3, 0), {F1, MR3}, E= MPTY}, - {"ldfd.sa.d3", M, OpMXX6aHintHlfa (6, 0, 0, 0x0f, 3, 0), {F1, MR3}, PS= EUDO, 0, NULL}, - {"ldfd.sa.d4", M, OpMXX6aHintHlfa (6, 0, 0, 0x0f, 0, 1), {F1, MR3}, EM= PTY}, - {"ldfd.sa.d5", M, OpMXX6aHintHlfa (6, 0, 0, 0x0f, 1, 1), {F1, MR3}, EM= PTY}, - {"ldfd.sa.d6", M, OpMXX6aHintHlfa (6, 0, 0, 0x0f, 2, 1), {F1, MR3}, EM= PTY}, - {"ldfd.sa.d7", M, OpMXX6aHintHlfa (6, 0, 0, 0x0f, 3, 1), {F1, MR3}, EM= PTY}, - {"ldf8.sa", M, OpMXX6aHintHlfa (6, 0, 0, 0x0d, 0, 0), {F1, MR3}, EMPT= Y}, - {"ldf8.sa.nt1", M, OpMXX6aHintHlfa (6, 0, 0, 0x0d, 1, 0), {F1, MR3}, E= MPTY}, - {"ldf8.sa.d1", M, OpMXX6aHintHlfa (6, 0, 0, 0x0d, 1, 0), {F1, MR3}, PS= EUDO, 0, NULL}, - {"ldf8.sa.d2", M, OpMXX6aHintHlfa (6, 0, 0, 0x0d, 2, 0), {F1, MR3}, EM= PTY}, - {"ldf8.sa.nt2", M, OpMXX6aHintHlfa (6, 0, 0, 0x0d, 2, 0), {F1, MR3}, P= SEUDO, 0, NULL}, - {"ldf8.sa.nta", M, OpMXX6aHintHlfa (6, 0, 0, 0x0d, 3, 0), {F1, MR3}, E= MPTY}, - {"ldf8.sa.d3", M, OpMXX6aHintHlfa (6, 0, 0, 0x0d, 3, 0), {F1, MR3}, PS= EUDO, 0, NULL}, - {"ldf8.sa.d4", M, OpMXX6aHintHlfa (6, 0, 0, 0x0d, 0, 1), {F1, MR3}, EM= PTY}, - {"ldf8.sa.d5", M, OpMXX6aHintHlfa (6, 0, 0, 0x0d, 1, 1), {F1, MR3}, EM= PTY}, - {"ldf8.sa.d6", M, OpMXX6aHintHlfa (6, 0, 0, 0x0d, 2, 1), {F1, MR3}, EM= PTY}, - {"ldf8.sa.d7", M, OpMXX6aHintHlfa (6, 0, 0, 0x0d, 3, 1), {F1, MR3}, EM= PTY}, - {"ldfe.sa", M, OpMXX6aHintHlfa (6, 0, 0, 0x0c, 0, 0), {F1, MR3}, EMPT= Y}, - {"ldfe.sa.nt1", M, OpMXX6aHintHlfa (6, 0, 0, 0x0c, 1, 0), {F1, MR3}, E= MPTY}, - {"ldfe.sa.d1", M, OpMXX6aHintHlfa (6, 0, 0, 0x0c, 1, 0), {F1, MR3}, PS= EUDO, 0, NULL}, - {"ldfe.sa.d2", M, OpMXX6aHintHlfa (6, 0, 0, 0x0c, 2, 0), {F1, MR3}, EM= PTY}, - {"ldfe.sa.nt2", M, OpMXX6aHintHlfa (6, 0, 0, 0x0c, 2, 0), {F1, MR3}, P= SEUDO, 0, NULL}, - {"ldfe.sa.nta", M, OpMXX6aHintHlfa (6, 0, 0, 0x0c, 3, 0), {F1, MR3}, E= MPTY}, - {"ldfe.sa.d3", M, OpMXX6aHintHlfa (6, 0, 0, 0x0c, 3, 0), {F1, MR3}, PS= EUDO, 0, NULL}, - {"ldfe.sa.d4", M, OpMXX6aHintHlfa (6, 0, 0, 0x0c, 0, 1), {F1, MR3}, EM= PTY}, - {"ldfe.sa.d5", M, OpMXX6aHintHlfa (6, 0, 0, 0x0c, 1, 1), {F1, MR3}, EM= PTY}, - {"ldfe.sa.d6", M, OpMXX6aHintHlfa (6, 0, 0, 0x0c, 2, 1), {F1, MR3}, EM= PTY}, - {"ldfe.sa.d7", M, OpMXX6aHintHlfa (6, 0, 0, 0x0c, 3, 1), {F1, MR3}, EM= PTY}, - {"ldf.fill", M, OpMXX6aHintHlfa (6, 0, 0, 0x1b, 0, 0), {F1, MR3}, EMPT= Y}, - {"ldf.fill.nt1", M, OpMXX6aHintHlfa (6, 0, 0, 0x1b, 1, 0), {F1, MR3}, = EMPTY}, - {"ldf.fill.d1", M, OpMXX6aHintHlfa (6, 0, 0, 0x1b, 1, 0), {F1, MR3}, P= SEUDO, 0, NULL}, - {"ldf.fill.d2", M, OpMXX6aHintHlfa (6, 0, 0, 0x1b, 2, 0), {F1, MR3}, E= MPTY}, - {"ldf.fill.nt2", M, OpMXX6aHintHlfa (6, 0, 0, 0x1b, 2, 0), {F1, MR3}, = PSEUDO, 0, NULL}, - {"ldf.fill.nta", M, OpMXX6aHintHlfa (6, 0, 0, 0x1b, 3, 0), {F1, MR3}, = EMPTY}, - {"ldf.fill.d3", M, OpMXX6aHintHlfa (6, 0, 0, 0x1b, 3, 0), {F1, MR3}, P= SEUDO, 0, NULL}, - {"ldf.fill.d4", M, OpMXX6aHintHlfa (6, 0, 0, 0x1b, 0, 1), {F1, MR3}, E= MPTY}, - {"ldf.fill.d5", M, OpMXX6aHintHlfa (6, 0, 0, 0x1b, 1, 1), {F1, MR3}, E= MPTY}, - {"ldf.fill.d6", M, OpMXX6aHintHlfa (6, 0, 0, 0x1b, 2, 1), {F1, MR3}, E= MPTY}, - {"ldf.fill.d7", M, OpMXX6aHintHlfa (6, 0, 0, 0x1b, 3, 1), {F1, MR3}, E= MPTY}, - {"ldfs.c.clr", M, OpMXX6aHintHlfa (6, 0, 0, 0x22, 0, 0), {F1, MR3}, EM= PTY}, - {"ldfs.c.clr.nt1", M, OpMXX6aHintHlfa (6, 0, 0, 0x22, 1, 0), {F1, MR3}= , EMPTY}, - {"ldfs.c.clr.d1", M, OpMXX6aHintHlfa (6, 0, 0, 0x22, 1, 0), {F1, MR3},= PSEUDO, 0, NULL}, - {"ldfs.c.clr.d2", M, OpMXX6aHintHlfa (6, 0, 0, 0x22, 2, 0), {F1, MR3},= EMPTY}, - {"ldfs.c.clr.nt2", M, OpMXX6aHintHlfa (6, 0, 0, 0x22, 2, 0), {F1, MR3}= , PSEUDO, 0, NULL}, - {"ldfs.c.clr.nta", M, OpMXX6aHintHlfa (6, 0, 0, 0x22, 3, 0), {F1, MR3}= , EMPTY}, - {"ldfs.c.clr.d3", M, OpMXX6aHintHlfa (6, 0, 0, 0x22, 3, 0), {F1, MR3},= PSEUDO, 0, NULL}, - {"ldfs.c.clr.d4", M, OpMXX6aHintHlfa (6, 0, 0, 0x22, 0, 1), {F1, MR3},= EMPTY}, - {"ldfs.c.clr.d5", M, OpMXX6aHintHlfa (6, 0, 0, 0x22, 1, 1), {F1, MR3},= EMPTY}, - {"ldfs.c.clr.d6", M, OpMXX6aHintHlfa (6, 0, 0, 0x22, 2, 1), {F1, MR3},= EMPTY}, - {"ldfs.c.clr.d7", M, OpMXX6aHintHlfa (6, 0, 0, 0x22, 3, 1), {F1, MR3},= EMPTY}, - {"ldfd.c.clr", M, OpMXX6aHintHlfa (6, 0, 0, 0x23, 0, 0), {F1, MR3}, EM= PTY}, - {"ldfd.c.clr.nt1", M, OpMXX6aHintHlfa (6, 0, 0, 0x23, 1, 0), {F1, MR3}= , EMPTY}, - {"ldfd.c.clr.d1", M, OpMXX6aHintHlfa (6, 0, 0, 0x23, 1, 0), {F1, MR3},= PSEUDO, 0, NULL}, - {"ldfd.c.clr.d2", M, OpMXX6aHintHlfa (6, 0, 0, 0x23, 2, 0), {F1, MR3},= EMPTY}, - {"ldfd.c.clr.nt2", M, OpMXX6aHintHlfa (6, 0, 0, 0x23, 2, 0), {F1, MR3}= , PSEUDO, 0, NULL}, - {"ldfd.c.clr.nta", M, OpMXX6aHintHlfa (6, 0, 0, 0x23, 3, 0), {F1, MR3}= , EMPTY}, - {"ldfd.c.clr.d3", M, OpMXX6aHintHlfa (6, 0, 0, 0x23, 3, 0), {F1, MR3},= PSEUDO, 0, NULL}, - {"ldfd.c.clr.d4", M, OpMXX6aHintHlfa (6, 0, 0, 0x23, 0, 1), {F1, MR3},= EMPTY}, - {"ldfd.c.clr.d5", M, OpMXX6aHintHlfa (6, 0, 0, 0x23, 1, 1), {F1, MR3},= EMPTY}, - {"ldfd.c.clr.d6", M, OpMXX6aHintHlfa (6, 0, 0, 0x23, 2, 1), {F1, MR3},= EMPTY}, - {"ldfd.c.clr.d7", M, OpMXX6aHintHlfa (6, 0, 0, 0x23, 3, 1), {F1, MR3},= EMPTY}, - {"ldf8.c.clr", M, OpMXX6aHintHlfa (6, 0, 0, 0x21, 0, 0), {F1, MR3}, EM= PTY}, - {"ldf8.c.clr.nt1", M, OpMXX6aHintHlfa (6, 0, 0, 0x21, 1, 0), {F1, MR3}= , EMPTY}, - {"ldf8.c.clr.d1", M, OpMXX6aHintHlfa (6, 0, 0, 0x21, 1, 0), {F1, MR3},= PSEUDO, 0, NULL}, - {"ldf8.c.clr.d2", M, OpMXX6aHintHlfa (6, 0, 0, 0x21, 2, 0), {F1, MR3},= EMPTY}, - {"ldf8.c.clr.nt2", M, OpMXX6aHintHlfa (6, 0, 0, 0x21, 2, 0), {F1, MR3}= , PSEUDO, 0, NULL}, - {"ldf8.c.clr.nta", M, OpMXX6aHintHlfa (6, 0, 0, 0x21, 3, 0), {F1, MR3}= , EMPTY}, - {"ldf8.c.clr.d3", M, OpMXX6aHintHlfa (6, 0, 0, 0x21, 3, 0), {F1, MR3},= PSEUDO, 0, NULL}, - {"ldf8.c.clr.d4", M, OpMXX6aHintHlfa (6, 0, 0, 0x21, 0, 1), {F1, MR3},= EMPTY}, - {"ldf8.c.clr.d5", M, OpMXX6aHintHlfa (6, 0, 0, 0x21, 1, 1), {F1, MR3},= EMPTY}, - {"ldf8.c.clr.d6", M, OpMXX6aHintHlfa (6, 0, 0, 0x21, 2, 1), {F1, MR3},= EMPTY}, - {"ldf8.c.clr.d7", M, OpMXX6aHintHlfa (6, 0, 0, 0x21, 3, 1), {F1, MR3},= EMPTY}, - {"ldfe.c.clr", M, OpMXX6aHintHlfa (6, 0, 0, 0x20, 0, 0), {F1, MR3}, EM= PTY}, - {"ldfe.c.clr.nt1", M, OpMXX6aHintHlfa (6, 0, 0, 0x20, 1, 0), {F1, MR3}= , EMPTY}, - {"ldfe.c.clr.d1", M, OpMXX6aHintHlfa (6, 0, 0, 0x20, 1, 0), {F1, MR3},= PSEUDO, 0, NULL}, - {"ldfe.c.clr.d2", M, OpMXX6aHintHlfa (6, 0, 0, 0x20, 2, 0), {F1, MR3},= EMPTY}, - {"ldfe.c.clr.nt2", M, OpMXX6aHintHlfa (6, 0, 0, 0x20, 2, 0), {F1, MR3}= , PSEUDO, 0, NULL}, - {"ldfe.c.clr.nta", M, OpMXX6aHintHlfa (6, 0, 0, 0x20, 3, 0), {F1, MR3}= , EMPTY}, - {"ldfe.c.clr.d3", M, OpMXX6aHintHlfa (6, 0, 0, 0x20, 3, 0), {F1, MR3},= PSEUDO, 0, NULL}, - {"ldfe.c.clr.d4", M, OpMXX6aHintHlfa (6, 0, 0, 0x20, 0, 1), {F1, MR3},= EMPTY}, - {"ldfe.c.clr.d5", M, OpMXX6aHintHlfa (6, 0, 0, 0x20, 1, 1), {F1, MR3},= EMPTY}, - {"ldfe.c.clr.d6", M, OpMXX6aHintHlfa (6, 0, 0, 0x20, 2, 1), {F1, MR3},= EMPTY}, - {"ldfe.c.clr.d7", M, OpMXX6aHintHlfa (6, 0, 0, 0x20, 3, 1), {F1, MR3},= EMPTY}, - {"ldfs.c.nc", M, OpMXX6aHintHlfa (6, 0, 0, 0x26, 0, 0), {F1, MR3}, EMP= TY}, - {"ldfs.c.nc.nt1", M, OpMXX6aHintHlfa (6, 0, 0, 0x26, 1, 0), {F1, MR3},= EMPTY}, - {"ldfs.c.nc.d1", M, OpMXX6aHintHlfa (6, 0, 0, 0x26, 1, 0), {F1, MR3}, = PSEUDO, 0, NULL}, - {"ldfs.c.nc.d2", M, OpMXX6aHintHlfa (6, 0, 0, 0x26, 2, 0), {F1, MR3}, = EMPTY}, - {"ldfs.c.nc.nt2", M, OpMXX6aHintHlfa (6, 0, 0, 0x26, 2, 0), {F1, MR3},= PSEUDO, 0, NULL}, - {"ldfs.c.nc.nta", M, OpMXX6aHintHlfa (6, 0, 0, 0x26, 3, 0), {F1, MR3},= EMPTY}, - {"ldfs.c.nc.d3", M, OpMXX6aHintHlfa (6, 0, 0, 0x26, 3, 0), {F1, MR3}, = PSEUDO, 0, NULL}, - {"ldfs.c.nc.d4", M, OpMXX6aHintHlfa (6, 0, 0, 0x26, 0, 1), {F1, MR3}, = EMPTY}, - {"ldfs.c.nc.d5", M, OpMXX6aHintHlfa (6, 0, 0, 0x26, 1, 1), {F1, MR3}, = EMPTY}, - {"ldfs.c.nc.d6", M, OpMXX6aHintHlfa (6, 0, 0, 0x26, 2, 1), {F1, MR3}, = EMPTY}, - {"ldfs.c.nc.d7", M, OpMXX6aHintHlfa (6, 0, 0, 0x26, 3, 1), {F1, MR3}, = EMPTY}, - {"ldfd.c.nc", M, OpMXX6aHintHlfa (6, 0, 0, 0x27, 0, 0), {F1, MR3}, EMP= TY}, - {"ldfd.c.nc.nt1", M, OpMXX6aHintHlfa (6, 0, 0, 0x27, 1, 0), {F1, MR3},= EMPTY}, - {"ldfd.c.nc.d1", M, OpMXX6aHintHlfa (6, 0, 0, 0x27, 1, 0), {F1, MR3}, = PSEUDO, 0, NULL}, - {"ldfd.c.nc.d2", M, OpMXX6aHintHlfa (6, 0, 0, 0x27, 2, 0), {F1, MR3}, = EMPTY}, - {"ldfd.c.nc.nt2", M, OpMXX6aHintHlfa (6, 0, 0, 0x27, 2, 0), {F1, MR3},= PSEUDO, 0, NULL}, - {"ldfd.c.nc.nta", M, OpMXX6aHintHlfa (6, 0, 0, 0x27, 3, 0), {F1, MR3},= EMPTY}, - {"ldfd.c.nc.d3", M, OpMXX6aHintHlfa (6, 0, 0, 0x27, 3, 0), {F1, MR3}, = PSEUDO, 0, NULL}, - {"ldfd.c.nc.d4", M, OpMXX6aHintHlfa (6, 0, 0, 0x27, 0, 1), {F1, MR3}, = EMPTY}, - {"ldfd.c.nc.d5", M, OpMXX6aHintHlfa (6, 0, 0, 0x27, 1, 1), {F1, MR3}, = EMPTY}, - {"ldfd.c.nc.d6", M, OpMXX6aHintHlfa (6, 0, 0, 0x27, 2, 1), {F1, MR3}, = EMPTY}, - {"ldfd.c.nc.d7", M, OpMXX6aHintHlfa (6, 0, 0, 0x27, 3, 1), {F1, MR3}, = EMPTY}, - {"ldf8.c.nc", M, OpMXX6aHintHlfa (6, 0, 0, 0x25, 0, 0), {F1, MR3}, EMP= TY}, - {"ldf8.c.nc.nt1", M, OpMXX6aHintHlfa (6, 0, 0, 0x25, 1, 0), {F1, MR3},= EMPTY}, - {"ldf8.c.nc.d1", M, OpMXX6aHintHlfa (6, 0, 0, 0x25, 1, 0), {F1, MR3}, = PSEUDO, 0, NULL}, - {"ldf8.c.nc.d2", M, OpMXX6aHintHlfa (6, 0, 0, 0x25, 2, 0), {F1, MR3}, = EMPTY}, - {"ldf8.c.nc.nt2", M, OpMXX6aHintHlfa (6, 0, 0, 0x25, 2, 0), {F1, MR3},= PSEUDO, 0, NULL}, - {"ldf8.c.nc.nta", M, OpMXX6aHintHlfa (6, 0, 0, 0x25, 3, 0), {F1, MR3},= EMPTY}, - {"ldf8.c.nc.d3", M, OpMXX6aHintHlfa (6, 0, 0, 0x25, 3, 0), {F1, MR3}, = PSEUDO, 0, NULL}, - {"ldf8.c.nc.d4", M, OpMXX6aHintHlfa (6, 0, 0, 0x25, 0, 1), {F1, MR3}, = EMPTY}, - {"ldf8.c.nc.d5", M, OpMXX6aHintHlfa (6, 0, 0, 0x25, 1, 1), {F1, MR3}, = EMPTY}, - {"ldf8.c.nc.d6", M, OpMXX6aHintHlfa (6, 0, 0, 0x25, 2, 1), {F1, MR3}, = EMPTY}, - {"ldf8.c.nc.d7", M, OpMXX6aHintHlfa (6, 0, 0, 0x25, 3, 1), {F1, MR3}, = EMPTY}, - {"ldfe.c.nc", M, OpMXX6aHintHlfa (6, 0, 0, 0x24, 0, 0), {F1, MR3}, EMP= TY}, - {"ldfe.c.nc.nt1", M, OpMXX6aHintHlfa (6, 0, 0, 0x24, 1, 0), {F1, MR3},= EMPTY}, - {"ldfe.c.nc.d1", M, OpMXX6aHintHlfa (6, 0, 0, 0x24, 1, 0), {F1, MR3}, = PSEUDO, 0, NULL}, - {"ldfe.c.nc.d2", M, OpMXX6aHintHlfa (6, 0, 0, 0x24, 2, 0), {F1, MR3}, = EMPTY}, - {"ldfe.c.nc.nt2", M, OpMXX6aHintHlfa (6, 0, 0, 0x24, 2, 0), {F1, MR3},= PSEUDO, 0, NULL}, - {"ldfe.c.nc.nta", M, OpMXX6aHintHlfa (6, 0, 0, 0x24, 3, 0), {F1, MR3},= EMPTY}, - {"ldfe.c.nc.d3", M, OpMXX6aHintHlfa (6, 0, 0, 0x24, 3, 0), {F1, MR3}, = PSEUDO, 0, NULL}, - {"ldfe.c.nc.d4", M, OpMXX6aHintHlfa (6, 0, 0, 0x24, 0, 1), {F1, MR3}, = EMPTY}, - {"ldfe.c.nc.d5", M, OpMXX6aHintHlfa (6, 0, 0, 0x24, 1, 1), {F1, MR3}, = EMPTY}, - {"ldfe.c.nc.d6", M, OpMXX6aHintHlfa (6, 0, 0, 0x24, 2, 1), {F1, MR3}, = EMPTY}, - {"ldfe.c.nc.d7", M, OpMXX6aHintHlfa (6, 0, 0, 0x24, 3, 1), {F1, MR3}, = EMPTY}, - - /* Floating-point load w/increment by register. */ -#define FLDINCREG(c,h) M, OpMXX6aHint (6, 1, 0, c, h), {F1, MR3, R2}, POST= INC, 0, NULL - {"ldfs", FLDINCREG (0x02, 0)}, - {"ldfs.nt1", FLDINCREG (0x02, 1)}, - {"ldfs.nta", FLDINCREG (0x02, 3)}, - {"ldfd", FLDINCREG (0x03, 0)}, - {"ldfd.nt1", FLDINCREG (0x03, 1)}, - {"ldfd.nta", FLDINCREG (0x03, 3)}, - {"ldf8", FLDINCREG (0x01, 0)}, - {"ldf8.nt1", FLDINCREG (0x01, 1)}, - {"ldf8.nta", FLDINCREG (0x01, 3)}, - {"ldfe", FLDINCREG (0x00, 0)}, - {"ldfe.nt1", FLDINCREG (0x00, 1)}, - {"ldfe.nta", FLDINCREG (0x00, 3)}, - {"ldfs.s", FLDINCREG (0x06, 0)}, - {"ldfs.s.nt1", FLDINCREG (0x06, 1)}, - {"ldfs.s.nta", FLDINCREG (0x06, 3)}, - {"ldfd.s", FLDINCREG (0x07, 0)}, - {"ldfd.s.nt1", FLDINCREG (0x07, 1)}, - {"ldfd.s.nta", FLDINCREG (0x07, 3)}, - {"ldf8.s", FLDINCREG (0x05, 0)}, - {"ldf8.s.nt1", FLDINCREG (0x05, 1)}, - {"ldf8.s.nta", FLDINCREG (0x05, 3)}, - {"ldfe.s", FLDINCREG (0x04, 0)}, - {"ldfe.s.nt1", FLDINCREG (0x04, 1)}, - {"ldfe.s.nta", FLDINCREG (0x04, 3)}, - {"ldfs.a", FLDINCREG (0x0a, 0)}, - {"ldfs.a.nt1", FLDINCREG (0x0a, 1)}, - {"ldfs.a.nta", FLDINCREG (0x0a, 3)}, - {"ldfd.a", FLDINCREG (0x0b, 0)}, - {"ldfd.a.nt1", FLDINCREG (0x0b, 1)}, - {"ldfd.a.nta", FLDINCREG (0x0b, 3)}, - {"ldf8.a", FLDINCREG (0x09, 0)}, - {"ldf8.a.nt1", FLDINCREG (0x09, 1)}, - {"ldf8.a.nta", FLDINCREG (0x09, 3)}, - {"ldfe.a", FLDINCREG (0x08, 0)}, - {"ldfe.a.nt1", FLDINCREG (0x08, 1)}, - {"ldfe.a.nta", FLDINCREG (0x08, 3)}, - {"ldfs.sa", FLDINCREG (0x0e, 0)}, - {"ldfs.sa.nt1", FLDINCREG (0x0e, 1)}, - {"ldfs.sa.nta", FLDINCREG (0x0e, 3)}, - {"ldfd.sa", FLDINCREG (0x0f, 0)}, - {"ldfd.sa.nt1", FLDINCREG (0x0f, 1)}, - {"ldfd.sa.nta", FLDINCREG (0x0f, 3)}, - {"ldf8.sa", FLDINCREG (0x0d, 0)}, - {"ldf8.sa.nt1", FLDINCREG (0x0d, 1)}, - {"ldf8.sa.nta", FLDINCREG (0x0d, 3)}, - {"ldfe.sa", FLDINCREG (0x0c, 0)}, - {"ldfe.sa.nt1", FLDINCREG (0x0c, 1)}, - {"ldfe.sa.nta", FLDINCREG (0x0c, 3)}, - {"ldf.fill", FLDINCREG (0x1b, 0)}, - {"ldf.fill.nt1", FLDINCREG (0x1b, 1)}, - {"ldf.fill.nta", FLDINCREG (0x1b, 3)}, - {"ldfs.c.clr", FLDINCREG (0x22, 0)}, - {"ldfs.c.clr.nt1", FLDINCREG (0x22, 1)}, - {"ldfs.c.clr.nta", FLDINCREG (0x22, 3)}, - {"ldfd.c.clr", FLDINCREG (0x23, 0)}, - {"ldfd.c.clr.nt1", FLDINCREG (0x23, 1)}, - {"ldfd.c.clr.nta", FLDINCREG (0x23, 3)}, - {"ldf8.c.clr", FLDINCREG (0x21, 0)}, - {"ldf8.c.clr.nt1", FLDINCREG (0x21, 1)}, - {"ldf8.c.clr.nta", FLDINCREG (0x21, 3)}, - {"ldfe.c.clr", FLDINCREG (0x20, 0)}, - {"ldfe.c.clr.nt1", FLDINCREG (0x20, 1)}, - {"ldfe.c.clr.nta", FLDINCREG (0x20, 3)}, - {"ldfs.c.nc", FLDINCREG (0x26, 0)}, - {"ldfs.c.nc.nt1", FLDINCREG (0x26, 1)}, - {"ldfs.c.nc.nta", FLDINCREG (0x26, 3)}, - {"ldfd.c.nc", FLDINCREG (0x27, 0)}, - {"ldfd.c.nc.nt1", FLDINCREG (0x27, 1)}, - {"ldfd.c.nc.nta", FLDINCREG (0x27, 3)}, - {"ldf8.c.nc", FLDINCREG (0x25, 0)}, - {"ldf8.c.nc.nt1", FLDINCREG (0x25, 1)}, - {"ldf8.c.nc.nta", FLDINCREG (0x25, 3)}, - {"ldfe.c.nc", FLDINCREG (0x24, 0)}, - {"ldfe.c.nc.nt1", FLDINCREG (0x24, 1)}, - {"ldfe.c.nc.nta", FLDINCREG (0x24, 3)}, -#undef FLDINCREG - -#if 0 -// old pre-psn variant with 2-bit hints; -// saved for reference - /* Floating-point store. */ - {"stfs", M, OpMXX6aHint (6, 0, 0, 0x32, 0), {MR3, F2}, EMPTY}, - {"stfs.nta", M, OpMXX6aHint (6, 0, 0, 0x32, 3), {MR3, F2}, EMPTY}, - {"stfd", M, OpMXX6aHint (6, 0, 0, 0x33, 0), {MR3, F2}, EMPTY}, - {"stfd.nta", M, OpMXX6aHint (6, 0, 0, 0x33, 3), {MR3, F2}, EMPTY}, - {"stf8", M, OpMXX6aHint (6, 0, 0, 0x31, 0), {MR3, F2}, EMPTY}, - {"stf8.nta", M, OpMXX6aHint (6, 0, 0, 0x31, 3), {MR3, F2}, EMPTY}, - {"stfe", M, OpMXX6aHint (6, 0, 0, 0x30, 0), {MR3, F2}, EMPTY}, - {"stfe.nta", M, OpMXX6aHint (6, 0, 0, 0x30, 3), {MR3, F2}, EMPTY}, - {"stf.spill", M, OpMXX6aHint (6, 0, 0, 0x3b, 0), {MR3, F2}, EMPTY}, - {"stf.spill.nta", M, OpMXX6aHint (6, 0, 0, 0x3b, 3), {MR3, F2}, EMPTY}, -#endif - - /* Floating-point store. */ - {"stfs", M, OpMXX6aHintHlf (6, 0, 0, 0x32, 0, 0), {MR3, F2}, EMPTY}, - {"stfs.d1", M, OpMXX6aHintHlf (6, 0, 0, 0x32, 1, 0), {MR3, F2}, EMPTY= }, - {"stfs.nt1", M, OpMXX6aHintHlf (6, 0, 0, 0x32, 1, 0), {MR3, F2}, PSEUD= O, 0, NULL}, - {"stfs.d2", M, OpMXX6aHintHlf (6, 0, 0, 0x32, 2, 0), {MR3, F2}, EMPTY= }, - {"stfs.nt2", M, OpMXX6aHintHlf (6, 0, 0, 0x32, 2, 0), {MR3, F2}, PSEUD= O, 0, NULL}, - {"stfs.nta", M, OpMXX6aHintHlf (6, 0, 0, 0x32, 3, 0), {MR3, F2}, EMPTY= }, - {"stfs.d3", M, OpMXX6aHintHlf (6, 0, 0, 0x32, 3, 0), {MR3, F2}, PSEUD= O, 0, NULL}, - {"stfs.d4", M, OpMXX6aHintHlf (6, 0, 0, 0x32, 0, 1), {MR3, F2}, EMPTY= }, - {"stfs.d5", M, OpMXX6aHintHlf (6, 0, 0, 0x32, 1, 1), {MR3, F2}, EMPTY= }, - {"stfs.d6", M, OpMXX6aHintHlf (6, 0, 0, 0x32, 2, 1), {MR3, F2}, EMPTY= }, - {"stfs.d7", M, OpMXX6aHintHlf (6, 0, 0, 0x32, 3, 1), {MR3, F2}, EMPTY= }, - {"stfd", M, OpMXX6aHintHlf (6, 0, 0, 0x33, 0, 0), {MR3, F2}, EMPTY}, - {"stfd.d1", M, OpMXX6aHintHlf (6, 0, 0, 0x33, 1, 0), {MR3, F2}, EMPTY= }, - {"stfd.nt1", M, OpMXX6aHintHlf (6, 0, 0, 0x33, 1, 0), {MR3, F2}, PSEUD= O, 0, NULL}, - {"stfd.d2", M, OpMXX6aHintHlf (6, 0, 0, 0x33, 2, 0), {MR3, F2}, EMPTY= }, - {"stfd.nt2", M, OpMXX6aHintHlf (6, 0, 0, 0x33, 2, 0), {MR3, F2}, PSEUD= O, 0, NULL}, - {"stfd.nta", M, OpMXX6aHintHlf (6, 0, 0, 0x33, 3, 0), {MR3, F2}, EMPTY= }, - {"stfd.d3", M, OpMXX6aHintHlf (6, 0, 0, 0x33, 3, 0), {MR3, F2}, PSEUD= O, 0, NULL}, - {"stfd.d4", M, OpMXX6aHintHlf (6, 0, 0, 0x33, 0, 1), {MR3, F2}, EMPTY= }, - {"stfd.d5", M, OpMXX6aHintHlf (6, 0, 0, 0x33, 1, 1), {MR3, F2}, EMPTY= }, - {"stfd.d6", M, OpMXX6aHintHlf (6, 0, 0, 0x33, 2, 1), {MR3, F2}, EMPTY= }, - {"stfd.d7", M, OpMXX6aHintHlf (6, 0, 0, 0x33, 3, 1), {MR3, F2}, EMPTY= }, - {"stf8", M, OpMXX6aHintHlf (6, 0, 0, 0x31, 0, 0), {MR3, F2}, EMPTY}, - {"stf8.d1", M, OpMXX6aHintHlf (6, 0, 0, 0x31, 1, 0), {MR3, F2}, EMPTY= }, - {"stf8.nt1", M, OpMXX6aHintHlf (6, 0, 0, 0x31, 1, 0), {MR3, F2}, PSEUD= O, 0, NULL}, - {"stf8.d2", M, OpMXX6aHintHlf (6, 0, 0, 0x31, 2, 0), {MR3, F2}, EMPTY= }, - {"stf8.nt2", M, OpMXX6aHintHlf (6, 0, 0, 0x31, 2, 0), {MR3, F2}, PSEUD= O, 0, NULL}, - {"stf8.nta", M, OpMXX6aHintHlf (6, 0, 0, 0x31, 3, 0), {MR3, F2}, EMPTY= }, - {"stf8.d3", M, OpMXX6aHintHlf (6, 0, 0, 0x31, 3, 0), {MR3, F2}, PSEUD= O, 0, NULL}, - {"stf8.d4", M, OpMXX6aHintHlf (6, 0, 0, 0x31, 0, 1), {MR3, F2}, EMPTY= }, - {"stf8.d5", M, OpMXX6aHintHlf (6, 0, 0, 0x31, 1, 1), {MR3, F2}, EMPTY= }, - {"stf8.d6", M, OpMXX6aHintHlf (6, 0, 0, 0x31, 2, 1), {MR3, F2}, EMPTY= }, - {"stf8.d7", M, OpMXX6aHintHlf (6, 0, 0, 0x31, 3, 1), {MR3, F2}, EMPTY= }, - {"stfe", M, OpMXX6aHintHlf (6, 0, 0, 0x30, 0, 0), {MR3, F2}, EMPTY}, - {"stfe.d1", M, OpMXX6aHintHlf (6, 0, 0, 0x30, 1, 0), {MR3, F2}, EMPTY= }, - {"stfe.nt1", M, OpMXX6aHintHlf (6, 0, 0, 0x30, 1, 0), {MR3, F2}, PSEUD= O, 0, NULL}, - {"stfe.d2", M, OpMXX6aHintHlf (6, 0, 0, 0x30, 2, 0), {MR3, F2}, EMPTY= }, - {"stfe.nt2", M, OpMXX6aHintHlf (6, 0, 0, 0x30, 2, 0), {MR3, F2}, PSEUD= O, 0, NULL}, - {"stfe.nta", M, OpMXX6aHintHlf (6, 0, 0, 0x30, 3, 0), {MR3, F2}, EMPTY= }, - {"stfe.d3", M, OpMXX6aHintHlf (6, 0, 0, 0x30, 3, 0), {MR3, F2}, PSEUD= O, 0, NULL}, - {"stfe.d4", M, OpMXX6aHintHlf (6, 0, 0, 0x30, 0, 1), {MR3, F2}, EMPTY= }, - {"stfe.d5", M, OpMXX6aHintHlf (6, 0, 0, 0x30, 1, 1), {MR3, F2}, EMPTY= }, - {"stfe.d6", M, OpMXX6aHintHlf (6, 0, 0, 0x30, 2, 1), {MR3, F2}, EMPTY= }, - {"stfe.d7", M, OpMXX6aHintHlf (6, 0, 0, 0x30, 3, 1), {MR3, F2}, EMPTY= }, - {"stf.spill", M, OpMXX6aHintHlf (6, 0, 0, 0x3b, 0, 0), {MR3, F2}, EMPT= Y}, - {"stf.spill.d1", M, OpMXX6aHintHlf (6, 0, 0, 0x3b, 1, 0), {MR3, F2}, E= MPTY}, - {"stf.spill.nt1", M, OpMXX6aHintHlf (6, 0, 0, 0x3b, 1, 0), {MR3, F2}, = PSEUDO, 0, NULL}, - {"stf.spill.d2", M, OpMXX6aHintHlf (6, 0, 0, 0x3b, 2, 0), {MR3, F2}, E= MPTY}, - {"stf.spill.nt2", M, OpMXX6aHintHlf (6, 0, 0, 0x3b, 2, 0), {MR3, F2}, = PSEUDO, 0, NULL}, - {"stf.spill.nta", M, OpMXX6aHintHlf (6, 0, 0, 0x3b, 3, 0), {MR3, F2}, = EMPTY}, - {"stf.spill.d3", M, OpMXX6aHintHlf (6, 0, 0, 0x3b, 3, 0), {MR3, F2}, P= SEUDO, 0, NULL}, - {"stf.spill.d4", M, OpMXX6aHintHlf (6, 0, 0, 0x3b, 0, 1), {MR3, F2}, E= MPTY}, - {"stf.spill.d5", M, OpMXX6aHintHlf (6, 0, 0, 0x3b, 1, 1), {MR3, F2}, E= MPTY}, - {"stf.spill.d6", M, OpMXX6aHintHlf (6, 0, 0, 0x3b, 2, 1), {MR3, F2}, E= MPTY}, - {"stf.spill.d7", M, OpMXX6aHintHlf (6, 0, 0, 0x3b, 3, 1), {MR3, F2}, E= MPTY}, - - /* Floating-point load pair. */ - {"ldfps", M2, OpMXX6aHint (6, 0, 1, 0x02, 0), {F1, F2, MR3}, EMPTY}, - {"ldfps.nt1", M2, OpMXX6aHint (6, 0, 1, 0x02, 1), {F1, F2, MR3}, EMPTY= }, - {"ldfps.nta", M2, OpMXX6aHint (6, 0, 1, 0x02, 3), {F1, F2, MR3}, EMPTY= }, - {"ldfpd", M2, OpMXX6aHint (6, 0, 1, 0x03, 0), {F1, F2, MR3}, EMPTY}, - {"ldfpd.nt1", M2, OpMXX6aHint (6, 0, 1, 0x03, 1), {F1, F2, MR3}, EMPTY= }, - {"ldfpd.nta", M2, OpMXX6aHint (6, 0, 1, 0x03, 3), {F1, F2, MR3}, EMPTY= }, - {"ldfp8", M2, OpMXX6aHint (6, 0, 1, 0x01, 0), {F1, F2, MR3}, EMPTY}, - {"ldfp8.nt1", M2, OpMXX6aHint (6, 0, 1, 0x01, 1), {F1, F2, MR3}, EMPTY= }, - {"ldfp8.nta", M2, OpMXX6aHint (6, 0, 1, 0x01, 3), {F1, F2, MR3}, EMPTY= }, - {"ldfps.s", M2, OpMXX6aHint (6, 0, 1, 0x06, 0), {F1, F2, MR3}, EMPTY}, - {"ldfps.s.nt1", M2, OpMXX6aHint (6, 0, 1, 0x06, 1), {F1, F2, MR3}, EMP= TY}, - {"ldfps.s.nta", M2, OpMXX6aHint (6, 0, 1, 0x06, 3), {F1, F2, MR3}, EMP= TY}, - {"ldfpd.s", M2, OpMXX6aHint (6, 0, 1, 0x07, 0), {F1, F2, MR3}, EMPTY}, - {"ldfpd.s.nt1", M2, OpMXX6aHint (6, 0, 1, 0x07, 1), {F1, F2, MR3}, EMP= TY}, - {"ldfpd.s.nta", M2, OpMXX6aHint (6, 0, 1, 0x07, 3), {F1, F2, MR3}, EMP= TY}, - {"ldfp8.s", M2, OpMXX6aHint (6, 0, 1, 0x05, 0), {F1, F2, MR3}, EMPTY}, - {"ldfp8.s.nt1", M2, OpMXX6aHint (6, 0, 1, 0x05, 1), {F1, F2, MR3}, EMP= TY}, - {"ldfp8.s.nta", M2, OpMXX6aHint (6, 0, 1, 0x05, 3), {F1, F2, MR3}, EMP= TY}, - {"ldfps.a", M2, OpMXX6aHint (6, 0, 1, 0x0a, 0), {F1, F2, MR3}, EMPTY}, - {"ldfps.a.nt1", M2, OpMXX6aHint (6, 0, 1, 0x0a, 1), {F1, F2, MR3}, EMP= TY}, - {"ldfps.a.nta", M2, OpMXX6aHint (6, 0, 1, 0x0a, 3), {F1, F2, MR3}, EMP= TY}, - {"ldfpd.a", M2, OpMXX6aHint (6, 0, 1, 0x0b, 0), {F1, F2, MR3}, EMPTY}, - {"ldfpd.a.nt1", M2, OpMXX6aHint (6, 0, 1, 0x0b, 1), {F1, F2, MR3}, EMP= TY}, - {"ldfpd.a.nta", M2, OpMXX6aHint (6, 0, 1, 0x0b, 3), {F1, F2, MR3}, EMP= TY}, - {"ldfp8.a", M2, OpMXX6aHint (6, 0, 1, 0x09, 0), {F1, F2, MR3}, EMPTY}, - {"ldfp8.a.nt1", M2, OpMXX6aHint (6, 0, 1, 0x09, 1), {F1, F2, MR3}, EMP= TY}, - {"ldfp8.a.nta", M2, OpMXX6aHint (6, 0, 1, 0x09, 3), {F1, F2, MR3}, EMP= TY}, - {"ldfps.sa", M2, OpMXX6aHint (6, 0, 1, 0x0e, 0), {F1, F2, MR3}, EMPTY}, - {"ldfps.sa.nt1", M2, OpMXX6aHint (6, 0, 1, 0x0e, 1), {F1, F2, MR3}, EM= PTY}, - {"ldfps.sa.nta", M2, OpMXX6aHint (6, 0, 1, 0x0e, 3), {F1, F2, MR3}, EM= PTY}, - {"ldfpd.sa", M2, OpMXX6aHint (6, 0, 1, 0x0f, 0), {F1, F2, MR3}, EMPTY}, - {"ldfpd.sa.nt1", M2, OpMXX6aHint (6, 0, 1, 0x0f, 1), {F1, F2, MR3}, EM= PTY}, - {"ldfpd.sa.nta", M2, OpMXX6aHint (6, 0, 1, 0x0f, 3), {F1, F2, MR3}, EM= PTY}, - {"ldfp8.sa", M2, OpMXX6aHint (6, 0, 1, 0x0d, 0), {F1, F2, MR3}, EMPTY}, - {"ldfp8.sa.nt1", M2, OpMXX6aHint (6, 0, 1, 0x0d, 1), {F1, F2, MR3}, EM= PTY}, - {"ldfp8.sa.nta", M2, OpMXX6aHint (6, 0, 1, 0x0d, 3), {F1, F2, MR3}, EM= PTY}, - {"ldfps.c.clr", M2, OpMXX6aHint (6, 0, 1, 0x22, 0), {F1, F2, MR3}, EMP= TY}, - {"ldfps.c.clr.nt1", M2, OpMXX6aHint (6, 0, 1, 0x22, 1), {F1, F2, MR3},= EMPTY}, - {"ldfps.c.clr.nta", M2, OpMXX6aHint (6, 0, 1, 0x22, 3), {F1, F2, MR3},= EMPTY}, - {"ldfpd.c.clr", M2, OpMXX6aHint (6, 0, 1, 0x23, 0), {F1, F2, MR3}, EMP= TY}, - {"ldfpd.c.clr.nt1", M2, OpMXX6aHint (6, 0, 1, 0x23, 1), {F1, F2, MR3},= EMPTY}, - {"ldfpd.c.clr.nta", M2, OpMXX6aHint (6, 0, 1, 0x23, 3), {F1, F2, MR3},= EMPTY}, - {"ldfp8.c.clr", M2, OpMXX6aHint (6, 0, 1, 0x21, 0), {F1, F2, MR3}, EMP= TY}, - {"ldfp8.c.clr.nt1", M2, OpMXX6aHint (6, 0, 1, 0x21, 1), {F1, F2, MR3},= EMPTY}, - {"ldfp8.c.clr.nta", M2, OpMXX6aHint (6, 0, 1, 0x21, 3), {F1, F2, MR3},= EMPTY}, - {"ldfps.c.nc", M2, OpMXX6aHint (6, 0, 1, 0x26, 0), {F1, F2, MR3}, EMPT= Y}, - {"ldfps.c.nc.nt1", M2, OpMXX6aHint (6, 0, 1, 0x26, 1), {F1, F2, MR3}, = EMPTY}, - {"ldfps.c.nc.nta", M2, OpMXX6aHint (6, 0, 1, 0x26, 3), {F1, F2, MR3}, = EMPTY}, - {"ldfpd.c.nc", M2, OpMXX6aHint (6, 0, 1, 0x27, 0), {F1, F2, MR3}, EMPT= Y}, - {"ldfpd.c.nc.nt1", M2, OpMXX6aHint (6, 0, 1, 0x27, 1), {F1, F2, MR3}, = EMPTY}, - {"ldfpd.c.nc.nta", M2, OpMXX6aHint (6, 0, 1, 0x27, 3), {F1, F2, MR3}, = EMPTY}, - {"ldfp8.c.nc", M2, OpMXX6aHint (6, 0, 1, 0x25, 0), {F1, F2, MR3}, EMPT= Y}, - {"ldfp8.c.nc.nt1", M2, OpMXX6aHint (6, 0, 1, 0x25, 1), {F1, F2, MR3}, = EMPTY}, - {"ldfp8.c.nc.nta", M2, OpMXX6aHint (6, 0, 1, 0x25, 3), {F1, F2, MR3}, = EMPTY}, - - /* Floating-point load pair w/increment by immediate. */ -#define LD(a,b,c) M2, OpMXX6aHint (6, 1, 1, a, b), {F1, F2, MR3, c}, POSTI= NC, 0, NULL - {"ldfps", LD (0x02, 0, C8)}, - {"ldfps.nt1", LD (0x02, 1, C8)}, - {"ldfps.nta", LD (0x02, 3, C8)}, - {"ldfpd", LD (0x03, 0, C16)}, - {"ldfpd.nt1", LD (0x03, 1, C16)}, - {"ldfpd.nta", LD (0x03, 3, C16)}, - {"ldfp8", LD (0x01, 0, C16)}, - {"ldfp8.nt1", LD (0x01, 1, C16)}, - {"ldfp8.nta", LD (0x01, 3, C16)}, - {"ldfps.s", LD (0x06, 0, C8)}, - {"ldfps.s.nt1", LD (0x06, 1, C8)}, - {"ldfps.s.nta", LD (0x06, 3, C8)}, - {"ldfpd.s", LD (0x07, 0, C16)}, - {"ldfpd.s.nt1", LD (0x07, 1, C16)}, - {"ldfpd.s.nta", LD (0x07, 3, C16)}, - {"ldfp8.s", LD (0x05, 0, C16)}, - {"ldfp8.s.nt1", LD (0x05, 1, C16)}, - {"ldfp8.s.nta", LD (0x05, 3, C16)}, - {"ldfps.a", LD (0x0a, 0, C8)}, - {"ldfps.a.nt1", LD (0x0a, 1, C8)}, - {"ldfps.a.nta", LD (0x0a, 3, C8)}, - {"ldfpd.a", LD (0x0b, 0, C16)}, - {"ldfpd.a.nt1", LD (0x0b, 1, C16)}, - {"ldfpd.a.nta", LD (0x0b, 3, C16)}, - {"ldfp8.a", LD (0x09, 0, C16)}, - {"ldfp8.a.nt1", LD (0x09, 1, C16)}, - {"ldfp8.a.nta", LD (0x09, 3, C16)}, - {"ldfps.sa", LD (0x0e, 0, C8)}, - {"ldfps.sa.nt1", LD (0x0e, 1, C8)}, - {"ldfps.sa.nta", LD (0x0e, 3, C8)}, - {"ldfpd.sa", LD (0x0f, 0, C16)}, - {"ldfpd.sa.nt1", LD (0x0f, 1, C16)}, - {"ldfpd.sa.nta", LD (0x0f, 3, C16)}, - {"ldfp8.sa", LD (0x0d, 0, C16)}, - {"ldfp8.sa.nt1", LD (0x0d, 1, C16)}, - {"ldfp8.sa.nta", LD (0x0d, 3, C16)}, - {"ldfps.c.clr", LD (0x22, 0, C8)}, - {"ldfps.c.clr.nt1", LD (0x22, 1, C8)}, - {"ldfps.c.clr.nta", LD (0x22, 3, C8)}, - {"ldfpd.c.clr", LD (0x23, 0, C16)}, - {"ldfpd.c.clr.nt1", LD (0x23, 1, C16)}, - {"ldfpd.c.clr.nta", LD (0x23, 3, C16)}, - {"ldfp8.c.clr", LD (0x21, 0, C16)}, - {"ldfp8.c.clr.nt1", LD (0x21, 1, C16)}, - {"ldfp8.c.clr.nta", LD (0x21, 3, C16)}, - {"ldfps.c.nc", LD (0x26, 0, C8)}, - {"ldfps.c.nc.nt1", LD (0x26, 1, C8)}, - {"ldfps.c.nc.nta", LD (0x26, 3, C8)}, - {"ldfpd.c.nc", LD (0x27, 0, C16)}, - {"ldfpd.c.nc.nt1", LD (0x27, 1, C16)}, - {"ldfpd.c.nc.nta", LD (0x27, 3, C16)}, - {"ldfp8.c.nc", LD (0x25, 0, C16)}, - {"ldfp8.c.nc.nt1", LD (0x25, 1, C16)}, - {"ldfp8.c.nc.nta", LD (0x25, 3, C16)}, -#undef LD - - /* Line prefetch. */ - /* Please note that X6 =3D=3D 2C and 2D, 2E and 2E are not uniform : - * 2C implies additional 1-b field "y" in the opcode while 2D - 2E don= 't - */ - - /* M51 -- X6 =3D=3D 0x2C =3D=3D> additional Y =3D 0 is used */ - {"lfetch", M0, OpMXY1X6aHintHlf (6, 0, 0, 0, 0x2c, 0, 0), {MR3}, EMP= TY}, - {"lfetch.d0", M0, OpMXY1X6aHintHlf (6, 0, 0, 0, 0x2c, 0, 0), {MR3}, P= SEUDO, 0, NULL}, - {"lfetch.nt1", M0, OpMXY1X6aHintHlf (6, 0, 0, 0, 0x2c, 1, 0), {MR3}, = EMPTY}, - {"lfetch.d1", M0, OpMXY1X6aHintHlf (6, 0, 0, 0, 0x2c, 1, 0), {MR3}, P= SEUDO, 0, NULL}, - {"lfetch.nt2", M0, OpMXY1X6aHintHlf (6, 0, 0, 0, 0x2c, 2, 0), {MR3}, = EMPTY}, - {"lfetch.d2", M0, OpMXY1X6aHintHlf (6, 0, 0, 0, 0x2c, 2, 0), {MR3}, P= SEUDO, 0, NULL}, - {"lfetch.nta", M0, OpMXY1X6aHintHlf (6, 0, 0, 0, 0x2c, 3, 0), {MR3}, = EMPTY}, - {"lfetch.d3", M0, OpMXY1X6aHintHlf (6, 0, 0, 0, 0x2c, 3, 0), {MR3}, P= SEUDO, 0, NULL}, - {"lfetch.d4", M0, OpMXY1X6aHintHlf (6, 0, 0, 0, 0x2c, 0, 1= ), {MR3}, EMPTY}, - {"lfetch.d5", M0, OpMXY1X6aHintHlf (6, 0, 0, 0, 0x2c, 1, 1= ), {MR3}, EMPTY}, - {"lfetch.d6", M0, OpMXY1X6aHintHlf (6, 0, 0, 0, 0x2c, 2, 1= ), {MR3}, EMPTY}, - {"lfetch.d7", M0, OpMXY1X6aHintHlf (6, 0, 0, 0, 0x2c, 3, 1= ), {MR3}, EMPTY}, - - /* M13 */ - {"lfetch.excl", M0, OpMXX6aHintHlf (6, 0, 0, 0x2d, 0, 0), {MR3}, EMPT= Y}, - {"lfetch.excl.d0", M0, OpMXX6aHintHlf (6, 0, 0, 0x2d, 0, 0), {MR3}, P= SEUDO, 0, NULL}, - {"lfetch.excl.nt1", M0, OpMXX6aHintHlf (6, 0, 0, 0x2d, 1, 0), {MR3}, = EMPTY}, - {"lfetch.excl.d1", M0, OpMXX6aHintHlf (6, 0, 0, 0x2d, 1, 0), {MR3}, P= SEUDO, 0, NULL}, - {"lfetch.excl.nt2", M0, OpMXX6aHintHlf (6, 0, 0, 0x2d, 2, 0), {MR3}, = EMPTY}, - {"lfetch.excl.d2", M0, OpMXX6aHintHlf (6, 0, 0, 0x2d, 2, 0), {MR3}, P= SEUDO, 0, NULL}, - {"lfetch.excl.nta", M0, OpMXX6aHintHlf (6, 0, 0, 0x2d, 3, 0), {MR3}, = EMPTY}, - {"lfetch.excl.d3", M0, OpMXX6aHintHlf (6, 0, 0, 0x2d, 3, 0), {MR3}, P= SEUDO, 0, NULL}, - {"lfetch.excl.d4", M0, OpMXX6aHintHlf (6, 0, 0, 0x2d, 0, 1), {MR3}, = EMPTY}, - {"lfetch.excl.d5", M0, OpMXX6aHintHlf (6, 0, 0, 0x2d, 1, 1), = {MR3}, EMPTY}, - {"lfetch.excl.d6", M0, OpMXX6aHintHlf (6, 0, 0, 0x2d, 2, 1), = {MR3}, EMPTY}, - {"lfetch.excl.d7", M0, OpMXX6aHintHlf (6, 0, 0, 0x2d, 3, 1), = {MR3}, EMPTY}, - {"lfetch.fault", M0, OpMXX6aHintHlf (6, 0, 0, 0x2e, 0, 0), {MR3}, EMP= TY}, - {"lfetch.fault.d0", M0, OpMXX6aHintHlf (6, 0, 0, 0x2e, 0, 0), {MR3}, = PSEUDO, 0, NULL}, - {"lfetch.fault.nt1", M0, OpMXX6aHintHlf (6, 0, 0, 0x2e, 1, 0), {MR3}, = EMPTY}, - {"lfetch.fault.d1", M0, OpMXX6aHintHlf (6, 0, 0, 0x2e, 1, 0), {MR3}, = PSEUDO, 0, NULL}, - {"lfetch.fault.nt2", M0, OpMXX6aHintHlf (6, 0, 0, 0x2e, 2, 0), {MR3}, = EMPTY}, - {"lfetch.fault.d2", M0, OpMXX6aHintHlf (6, 0, 0, 0x2e, 2, 0), {MR3}, = PSEUDO, 0, NULL}, - {"lfetch.fault.nta", M0, OpMXX6aHintHlf (6, 0, 0, 0x2e, 3, 0), {MR3}, = EMPTY}, - {"lfetch.fault.d3", M0, OpMXX6aHintHlf (6, 0, 0, 0x2e, 3, 0), {MR3}, = PSEUDO, 0, NULL}, - {"lfetch.fault.d4", M0, OpMXX6aHintHlf (6, 0, 0, 0x2e, 0, 1), {MR3}, = EMPTY}, - {"lfetch.fault.d5", M0, OpMXX6aHintHlf (6, 0, 0, 0x2e, 1, 1), = {MR3}, EMPTY}, - {"lfetch.fault.d6", M0, OpMXX6aHintHlf (6, 0, 0, 0x2e, 2, 1), = {MR3}, EMPTY}, - {"lfetch.fault.d7", M0, OpMXX6aHintHlf (6, 0, 0, 0x2e, 3, 1), = {MR3}, EMPTY}, - {"lfetch.fault.excl", M0, OpMXX6aHintHlf (6, 0, 0, 0x2f, 0, 0), {MR3},= EMPTY}, - {"lfetch.fault.excl.d0", M0, OpMXX6aHintHlf (6, 0, 0, 0x2f, 0, 0), {MR= 3}, PSEUDO, 0, NULL}, - {"lfetch.fault.excl.nt1", M0, OpMXX6aHintHlf (6, 0, 0, 0x2f, 1, 0), {M= R3}, EMPTY}, - {"lfetch.fault.excl.d1", M0, OpMXX6aHintHlf (6, 0, 0, 0x2f, 1, 0), {MR= 3}, PSEUDO, 0, NULL}, - {"lfetch.fault.excl.nt2", M0, OpMXX6aHintHlf (6, 0, 0, 0x2f, 2, 0), {M= R3}, EMPTY}, - {"lfetch.fault.excl.d2", M0, OpMXX6aHintHlf (6, 0, 0, 0x2f, 2, 0), {MR= 3}, PSEUDO, 0, NULL}, - {"lfetch.fault.excl.nta", M0, OpMXX6aHintHlf (6, 0, 0, 0x2f, 3, 0), {M= R3}, EMPTY}, - {"lfetch.fault.excl.d3", M0, OpMXX6aHintHlf (6, 0, 0, 0x2f, 3, 0), {MR= 3}, PSEUDO, 0, NULL}, - {"lfetch.fault.excl.d4", M0, OpMXX6aHintHlf (6, 0, 0, 0x2f, 0, 1), = {MR3}, EMPTY}, - {"lfetch.fault.excl.d5", M0, OpMXX6aHintHlf (6, 0, 0, 0x2f, 1, 1), = {MR3}, EMPTY}, - {"lfetch.fault.excl.d6", M0, OpMXX6aHintHlf (6, 0, 0, 0x2f, 2, 1), = {MR3}, EMPTY}, - {"lfetch.fault.excl.d7", M0, OpMXX6aHintHlf (6, 0, 0, 0x2f, 3, 1), = {MR3}, EMPTY}, - - /* M52 -- X6 =3D=3D 0x2C =3D=3D> additional Y =3D 1 is used */ - {"lfetch.count", M0, OpMXY1X6aHintHlf (6, 0, 0, 1, 0x2c, 0, 0), {M= R3, CNT6a, STRD5b}, EMPTY}, - {"lfetch.count.d0", M0, OpMXY1X6aHintHlf (6, 0, 0, 1, 0x2c, 0, 0),= {MR3, CNT6a, STRD5b}, PSEUDO, 0, NULL}, - {"lfetch.count.nt1", M0, OpMXY1X6aHintHlf (6, 0, 0, 1, 0x2c, 1, 0), {M= R3, CNT6a, STRD5b}, EMPTY}, - {"lfetch.count.d1", M0, OpMXY1X6aHintHlf (6, 0, 0, 1, 0x2c, 1, 0), {M= R3, CNT6a, STRD5b}, PSEUDO, 0, NULL}, - {"lfetch.count.nt2", M0, OpMXY1X6aHintHlf (6, 0, 0, 1, 0x2c, 2, 0), {M= R3, CNT6a, STRD5b}, EMPTY}, - {"lfetch.count.d2", M0, OpMXY1X6aHintHlf (6, 0, 0, 1, 0x2c, 2, 0), {M= R3, CNT6a, STRD5b}, PSEUDO, 0, NULL}, - {"lfetch.count.nta", M0, OpMXY1X6aHintHlf (6, 0, 0, 1, 0x2c, 3, 0), {M= R3, CNT6a, STRD5b}, EMPTY}, - {"lfetch.count.d3", M0, OpMXY1X6aHintHlf (6, 0, 0, 1, 0x2c, 3, 0), {M= R3, CNT6a, STRD5b}, PSEUDO, 0, NULL}, - {"lfetch.count.d4", M0, OpMXY1X6aHintHlf (6, 0, 0, 1, 0x2c, 0, 1), {M= R3, CNT6a, STRD5b}, EMPTY}, - {"lfetch.count.d5", M0, OpMXY1X6aHintHlf (6, 0, 0, 1, 0x2c, 1, 1), {M= R3, CNT6a, STRD5b}, EMPTY}, - {"lfetch.count.d6", M0, OpMXY1X6aHintHlf (6, 0, 0, 1, 0x2c, 2, 1), {M= R3, CNT6a, STRD5b}, EMPTY}, - {"lfetch.count.d7", M0, OpMXY1X6aHintHlf (6, 0, 0, 1, 0x2c, 3, 1), {M= R3, CNT6a, STRD5b}, EMPTY}, - - - /* Line prefetch w/increment by register. */ - /* M14 -- all four X6 ( 2C .. 2F ) are used uniformly; no additional o= pcode bits */ -#define LFETCHINCREG(x6,hnt,h) M0, OpMXX6aHintHlf (6, 1, 0, x6, hnt, h), {= MR3, R2}, POSTINC, 0, NULL -#define LFETCHINCREG_SYN(x6,hnt,h) M0, OpMXX6aHintHlf (6, 1, 0, x6, hnt, h= ), {MR3, R2}, POSTINC|PSEUDO, 0, NULL - - {"lfetch", LFETCHINCREG (0x2c, 0, 0)}, - {"lfetch.d0", LFETCHINCREG_SYN (0x2c, 0, 0)}, - {"lfetch.nt1", LFETCHINCREG (0x2c, 1, 0)}, - {"lfetch.d1", LFETCHINCREG_SYN (0x2c, 1, 0)}, - {"lfetch.nt2", LFETCHINCREG (0x2c, 2, 0)}, - {"lfetch.d2", LFETCHINCREG_SYN (0x2c, 2, 0)}, - {"lfetch.nta", LFETCHINCREG (0x2c, 3, 0)}, - {"lfetch.d3", LFETCHINCREG_SYN (0x2c, 3, 0)}, - {"lfetch.d4", LFETCHINCREG (0x2c, 0, 1)}, - {"lfetch.d5", LFETCHINCREG (0x2c, 1, 1)}, - {"lfetch.d6", LFETCHINCREG (0x2c, 2, 1)}, - {"lfetch.d7", LFETCHINCREG (0x2c, 3, 1)}, - {"lfetch.excl", LFETCHINCREG (0x2d, 0, 0)}, - {"lfetch.excl.d0", LFETCHINCREG_SYN (0x2d, 0, 0)}, - {"lfetch.excl.nt1", LFETCHINCREG (0x2d, 1, 0)}, - {"lfetch.excl.d1", LFETCHINCREG_SYN (0x2d, 1, 0)}, - {"lfetch.excl.nt2", LFETCHINCREG (0x2d, 2, 0)}, - {"lfetch.excl.d2", LFETCHINCREG_SYN (0x2d, 2, 0)}, - {"lfetch.excl.nta", LFETCHINCREG (0x2d, 3, 0)}, - {"lfetch.excl.d3", LFETCHINCREG_SYN (0x2d, 3, 0)}, - {"lfetch.excl.d4", LFETCHINCREG (0x2d, 0, 1)}, - {"lfetch.excl.d5", LFETCHINCREG (0x2d, 1, 1)}, - {"lfetch.excl.d6", LFETCHINCREG (0x2d, 2, 1)}, - {"lfetch.excl.d7", LFETCHINCREG (0x2d, 3, 1)}, - {"lfetch.fault", LFETCHINCREG (0x2e, 0, 0)}, - {"lfetch.fault.d0", LFETCHINCREG_SYN (0x2e, 0, 0)}, - {"lfetch.fault.nt1", LFETCHINCREG (0x2e, 1, 0)}, - {"lfetch.fault.d1", LFETCHINCREG_SYN (0x2e, 1, 0)}, - {"lfetch.fault.nt2", LFETCHINCREG (0x2e, 2, 0)}, - {"lfetch.fault.d2", LFETCHINCREG_SYN (0x2e, 2, 0)}, - {"lfetch.fault.nta", LFETCHINCREG (0x2e, 3, 0)}, - {"lfetch.fault.d3", LFETCHINCREG_SYN (0x2e, 3, 0)}, - {"lfetch.fault.d4", LFETCHINCREG (0x2e, 0, 1)}, - {"lfetch.fault.d5", LFETCHINCREG (0x2e, 1, 1)}, - {"lfetch.fault.d6", LFETCHINCREG (0x2e, 2, 1)}, - {"lfetch.fault.d7", LFETCHINCREG (0x2e, 3, 1)}, - {"lfetch.fault.excl", LFETCHINCREG (0x2f, 0, 0)}, - {"lfetch.fault.excl.d0", LFETCHINCREG_SYN (0x2f, 0, 0)}, - {"lfetch.fault.excl.nt1", LFETCHINCREG (0x2f, 1, 0)}, - {"lfetch.fault.excl.d1", LFETCHINCREG_SYN (0x2f, 1, 0)}, - {"lfetch.fault.excl.nt2", LFETCHINCREG (0x2f, 2, 0)}, - {"lfetch.fault.excl.d2", LFETCHINCREG_SYN (0x2f, 2, 0)}, - {"lfetch.fault.excl.nta", LFETCHINCREG (0x2f, 3, 0)}, - {"lfetch.fault.excl.d3", LFETCHINCREG_SYN (0x2f, 3, 0)}, - {"lfetch.fault.excl.d4", LFETCHINCREG (0x2f, 0, 1)}, - {"lfetch.fault.excl.d5", LFETCHINCREG (0x2f, 1, 1)}, - {"lfetch.fault.excl.d6", LFETCHINCREG (0x2f, 2, 1)}, - {"lfetch.fault.excl.d7", LFETCHINCREG (0x2f, 3, 1)}, - -#undef LFETCHINCREG -#undef LFETCHINCREG_SYN - - /* Semaphore operations. */ - {"setf.sig", M, OpMXX6a (6, 0, 1, 0x1c), {F1, R2}, EMPTY}, - {"setf.exp", M, OpMXX6a (6, 0, 1, 0x1d), {F1, R2}, EMPTY}, - {"setf.s", M, OpMXX6a (6, 0, 1, 0x1e), {F1, R2}, EMPTY}, - {"setf.d", M, OpMXX6a (6, 0, 1, 0x1f), {F1, R2}, EMPTY}, - - /* Floating-point load w/increment by immediate. */ -#define FLDINCIMMED(c,h) M, OpX6aHint (7, c, h), {F1, MR3, IMM9b}, POSTINC= , 0, NULL - {"ldfs", FLDINCIMMED (0x02, 0)}, - {"ldfs.nt1", FLDINCIMMED (0x02, 1)}, - {"ldfs.nta", FLDINCIMMED (0x02, 3)}, - {"ldfd", FLDINCIMMED (0x03, 0)}, - {"ldfd.nt1", FLDINCIMMED (0x03, 1)}, - {"ldfd.nta", FLDINCIMMED (0x03, 3)}, - {"ldf8", FLDINCIMMED (0x01, 0)}, - {"ldf8.nt1", FLDINCIMMED (0x01, 1)}, - {"ldf8.nta", FLDINCIMMED (0x01, 3)}, - {"ldfe", FLDINCIMMED (0x00, 0)}, - {"ldfe.nt1", FLDINCIMMED (0x00, 1)}, - {"ldfe.nta", FLDINCIMMED (0x00, 3)}, - {"ldfs.s", FLDINCIMMED (0x06, 0)}, - {"ldfs.s.nt1", FLDINCIMMED (0x06, 1)}, - {"ldfs.s.nta", FLDINCIMMED (0x06, 3)}, - {"ldfd.s", FLDINCIMMED (0x07, 0)}, - {"ldfd.s.nt1", FLDINCIMMED (0x07, 1)}, - {"ldfd.s.nta", FLDINCIMMED (0x07, 3)}, - {"ldf8.s", FLDINCIMMED (0x05, 0)}, - {"ldf8.s.nt1", FLDINCIMMED (0x05, 1)}, - {"ldf8.s.nta", FLDINCIMMED (0x05, 3)}, - {"ldfe.s", FLDINCIMMED (0x04, 0)}, - {"ldfe.s.nt1", FLDINCIMMED (0x04, 1)}, - {"ldfe.s.nta", FLDINCIMMED (0x04, 3)}, - {"ldfs.a", FLDINCIMMED (0x0a, 0)}, - {"ldfs.a.nt1", FLDINCIMMED (0x0a, 1)}, - {"ldfs.a.nta", FLDINCIMMED (0x0a, 3)}, - {"ldfd.a", FLDINCIMMED (0x0b, 0)}, - {"ldfd.a.nt1", FLDINCIMMED (0x0b, 1)}, - {"ldfd.a.nta", FLDINCIMMED (0x0b, 3)}, - {"ldf8.a", FLDINCIMMED (0x09, 0)}, - {"ldf8.a.nt1", FLDINCIMMED (0x09, 1)}, - {"ldf8.a.nta", FLDINCIMMED (0x09, 3)}, - {"ldfe.a", FLDINCIMMED (0x08, 0)}, - {"ldfe.a.nt1", FLDINCIMMED (0x08, 1)}, - {"ldfe.a.nta", FLDINCIMMED (0x08, 3)}, - {"ldfs.sa", FLDINCIMMED (0x0e, 0)}, - {"ldfs.sa.nt1", FLDINCIMMED (0x0e, 1)}, - {"ldfs.sa.nta", FLDINCIMMED (0x0e, 3)}, - {"ldfd.sa", FLDINCIMMED (0x0f, 0)}, - {"ldfd.sa.nt1", FLDINCIMMED (0x0f, 1)}, - {"ldfd.sa.nta", FLDINCIMMED (0x0f, 3)}, - {"ldf8.sa", FLDINCIMMED (0x0d, 0)}, - {"ldf8.sa.nt1", FLDINCIMMED (0x0d, 1)}, - {"ldf8.sa.nta", FLDINCIMMED (0x0d, 3)}, - {"ldfe.sa", FLDINCIMMED (0x0c, 0)}, - {"ldfe.sa.nt1", FLDINCIMMED (0x0c, 1)}, - {"ldfe.sa.nta", FLDINCIMMED (0x0c, 3)}, - {"ldf.fill", FLDINCIMMED (0x1b, 0)}, - {"ldf.fill.nt1", FLDINCIMMED (0x1b, 1)}, - {"ldf.fill.nta", FLDINCIMMED (0x1b, 3)}, - {"ldfs.c.clr", FLDINCIMMED (0x22, 0)}, - {"ldfs.c.clr.nt1", FLDINCIMMED (0x22, 1)}, - {"ldfs.c.clr.nta", FLDINCIMMED (0x22, 3)}, - {"ldfd.c.clr", FLDINCIMMED (0x23, 0)}, - {"ldfd.c.clr.nt1", FLDINCIMMED (0x23, 1)}, - {"ldfd.c.clr.nta", FLDINCIMMED (0x23, 3)}, - {"ldf8.c.clr", FLDINCIMMED (0x21, 0)}, - {"ldf8.c.clr.nt1", FLDINCIMMED (0x21, 1)}, - {"ldf8.c.clr.nta", FLDINCIMMED (0x21, 3)}, - {"ldfe.c.clr", FLDINCIMMED (0x20, 0)}, - {"ldfe.c.clr.nt1", FLDINCIMMED (0x20, 1)}, - {"ldfe.c.clr.nta", FLDINCIMMED (0x20, 3)}, - {"ldfs.c.nc", FLDINCIMMED (0x26, 0)}, - {"ldfs.c.nc.nt1", FLDINCIMMED (0x26, 1)}, - {"ldfs.c.nc.nta", FLDINCIMMED (0x26, 3)}, - {"ldfd.c.nc", FLDINCIMMED (0x27, 0)}, - {"ldfd.c.nc.nt1", FLDINCIMMED (0x27, 1)}, - {"ldfd.c.nc.nta", FLDINCIMMED (0x27, 3)}, - {"ldf8.c.nc", FLDINCIMMED (0x25, 0)}, - {"ldf8.c.nc.nt1", FLDINCIMMED (0x25, 1)}, - {"ldf8.c.nc.nta", FLDINCIMMED (0x25, 3)}, - {"ldfe.c.nc", FLDINCIMMED (0x24, 0)}, - {"ldfe.c.nc.nt1", FLDINCIMMED (0x24, 1)}, - {"ldfe.c.nc.nta", FLDINCIMMED (0x24, 3)}, -#undef FLDINCIMMED - - /* Floating-point store w/increment by immediate. */ -#define FSTINCIMMED(c,h) M, OpX6aHint (7, c, h), {MR3, F2, IMM9a}, POSTINC= , 0, NULL - {"stfs", FSTINCIMMED (0x32, 0)}, - {"stfs.nta", FSTINCIMMED (0x32, 3)}, - {"stfd", FSTINCIMMED (0x33, 0)}, - {"stfd.nta", FSTINCIMMED (0x33, 3)}, - {"stf8", FSTINCIMMED (0x31, 0)}, - {"stf8.nta", FSTINCIMMED (0x31, 3)}, - {"stfe", FSTINCIMMED (0x30, 0)}, - {"stfe.nta", FSTINCIMMED (0x30, 3)}, - {"stf.spill", FSTINCIMMED (0x3b, 0)}, - {"stf.spill.nta", FSTINCIMMED (0x3b, 3)}, -#undef FSTINCIMMED - - - /* Line prefetch w/increment by immediate. */ - /* M15 -- all four X6 ( 2C .. 2F ) are used uniformly; no additional o= pcode bits */ -#define LFETCHINCIMMED(x6,hnt,h) M0, OpX6aHintHlf (7, x6, hnt, h), {MR3, I= MM9b}, POSTINC, 0, NULL -#define LFETCHINCIMMED_SYN(x6,hnt,h) M0, OpX6aHintHlf (7, x6, hnt, h), {MR= 3, IMM9b}, POSTINC|PSEUDO, 0, NULL - - - {"lfetch", LFETCHINCIMMED (0x2c, 0, 0)}, - {"lfetch.d0", LFETCHINCIMMED_SYN (0x2c, 0, 0)}, - {"lfetch.nt1", LFETCHINCIMMED (0x2c, 1, 0)}, - {"lfetch.d1", LFETCHINCIMMED_SYN (0x2c, 1, 0)}, - {"lfetch.nt2", LFETCHINCIMMED (0x2c, 2, 0)}, - {"lfetch.d2", LFETCHINCIMMED_SYN (0x2c, 2, 0)}, - {"lfetch.nta", LFETCHINCIMMED (0x2c, 3, 0)}, - {"lfetch.d3", LFETCHINCIMMED_SYN (0x2c, 3, 0)}, - {"lfetch.d4", LFETCHINCIMMED (0x2c, 0, 1)}, - {"lfetch.d5", LFETCHINCIMMED (0x2c, 1, 1)}, - {"lfetch.d6", LFETCHINCIMMED (0x2c, 2, 1)}, - {"lfetch.d7", LFETCHINCIMMED (0x2c, 3, 1)}, - {"lfetch.excl", LFETCHINCIMMED (0x2d, 0, 0)}, - {"lfetch.excl.d0", LFETCHINCIMMED_SYN (0x2d, 0, 0)}, - {"lfetch.excl.nt1", LFETCHINCIMMED (0x2d, 1, 0)}, - {"lfetch.excl.d1", LFETCHINCIMMED_SYN (0x2d, 1, 0)}, - {"lfetch.excl.nt2", LFETCHINCIMMED (0x2d, 2, 0)}, - {"lfetch.excl.d2", LFETCHINCIMMED_SYN (0x2d, 2, 0)}, - {"lfetch.excl.nta", LFETCHINCIMMED (0x2d, 3, 0)}, - {"lfetch.excl.d3", LFETCHINCIMMED_SYN (0x2d, 3, 0)}, - {"lfetch.excl.d4", LFETCHINCIMMED (0x2d, 0, 1)}, - {"lfetch.excl.d5", LFETCHINCIMMED (0x2d, 1, 1)}, - {"lfetch.excl.d6", LFETCHINCIMMED (0x2d, 2, 1)}, - {"lfetch.excl.d7", LFETCHINCIMMED (0x2d, 3, 1)}, - {"lfetch.fault", LFETCHINCIMMED (0x2e, 0, 0)}, - {"lfetch.fault.d0", LFETCHINCIMMED_SYN (0x2e, 0, 0)}, - {"lfetch.fault.nt1", LFETCHINCIMMED (0x2e, 1, 0)}, - {"lfetch.fault.d1", LFETCHINCIMMED_SYN (0x2e, 1, 0)}, - {"lfetch.fault.nt2", LFETCHINCIMMED (0x2e, 2, 0)}, - {"lfetch.fault.d2", LFETCHINCIMMED_SYN (0x2e, 2, 0)}, - {"lfetch.fault.nta", LFETCHINCIMMED (0x2e, 3, 0)}, - {"lfetch.fault.d3", LFETCHINCIMMED_SYN (0x2e, 3, 0)}, - {"lfetch.fault.d4", LFETCHINCIMMED (0x2e, 0, 1)}, - {"lfetch.fault.d5", LFETCHINCIMMED (0x2e, 1, 1)}, - {"lfetch.fault.d6", LFETCHINCIMMED (0x2e, 2, 1)}, - {"lfetch.fault.d7", LFETCHINCIMMED (0x2e, 3, 1)}, - {"lfetch.fault.excl", LFETCHINCIMMED (0x2f, 0, 0)}, - {"lfetch.fault.excl.d0", LFETCHINCIMMED_SYN (0x2f, 0, 0)}, - {"lfetch.fault.excl.nt1", LFETCHINCIMMED (0x2f, 1, 0)}, - {"lfetch.fault.excl.d1", LFETCHINCIMMED_SYN (0x2f, 1, 0)}, - {"lfetch.fault.excl.nt2", LFETCHINCIMMED (0x2f, 2, 0)}, - {"lfetch.fault.excl.d2", LFETCHINCIMMED_SYN (0x2f, 2, 0)}, - {"lfetch.fault.excl.nta", LFETCHINCIMMED (0x2f, 3, 0)}, - {"lfetch.fault.excl.d3", LFETCHINCIMMED_SYN (0x2f, 3, 0)}, - {"lfetch.fault.excl.d4", LFETCHINCIMMED (0x2f, 0, 1)}, - {"lfetch.fault.excl.d5", LFETCHINCIMMED (0x2f, 1, 1)}, - {"lfetch.fault.excl.d6", LFETCHINCIMMED (0x2f, 2, 1)}, - {"lfetch.fault.excl.d7", LFETCHINCIMMED (0x2f, 3, 1)}, - -#undef LFETCHINCIMMED -#undef LFETCHINCIMMED_SYN - - {NULL, 0, 0, 0, 0, {0}, 0, 0, NULL} - }; - -#undef M0 -#undef M -#undef M2 -#undef bM -#undef bX -#undef bX2 -#undef bX3 -#undef bX4 -#undef bX6a -#undef bX6b -#undef bY -#undef bY1 -#undef bHint -#undef bHlf -#undef bHlfa -#undef mM -#undef mX -#undef mX2 -#undef mX3 -#undef mX4 -#undef mX6a -#undef mX6b -#undef mY -#undef mY1 -#undef mHint -#undef mHlf -#undef mHlfa -#undef OpX3 -#undef OpX3X6b -#undef OpX3X4 -#undef OpX3X4X2 -#undef OpX6aHint -#undef OpXX6aHint -#undef OpMXX6a -#undef OpMXX6aHint -#undef OpMXX6aHintHlfa -#undef OpMXX6aHintHlf -#undef OpMXY1X6aHintHlf -#undef EMPTY diff --git a/opcodes/ia64-opc-x.c b/opcodes/ia64-opc-x.c deleted file mode 100644 index 33f6039226a..00000000000 --- a/opcodes/ia64-opc-x.c +++ /dev/null @@ -1,188 +0,0 @@ -/* ia64-opc-x.c -- IA-64 `X' opcode table. - Copyright (C) 1998-2024 Free Software Foundation, Inc. - Contributed by Timothy Wall - - This file is part of the GNU opcodes library. - - This library is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3, or (at your option) - any later version. - - It is distributed in the hope that it will be useful, but WITHOUT - ANY WARRANTY; without even the implied warranty of MERCHANTABILITY - or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public - License for more details. - - You should have received a copy of the GNU General Public License - along with this file; see the file COPYING. If not, write to the - Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston, - MA 02110-1301, USA. */ - -#include "ia64-opc.h" - -/* Identify the specific X-unit type. */ -#define X0 IA64_TYPE_X, 0 -#define X IA64_TYPE_X, 1 - -/* Instruction bit fields: */ -#define bBtype(x) (((ia64_insn) ((x) & 0x7)) << 6) -#define bD(x) (((ia64_insn) ((x) & 0x1)) << 35) -#define bPa(x) (((ia64_insn) ((x) & 0x1)) << 12) -#define bPr(x) (((ia64_insn) ((x) & 0x3f)) << 0) -#define bVc(x) (((ia64_insn) ((x) & 0x1)) << 20) -#define bWha(x) (((ia64_insn) ((x) & 0x3)) << 33) -#define bX3(x) (((ia64_insn) ((x) & 0x7)) << 33) -#define bX6(x) (((ia64_insn) ((x) & 0x3f)) << 27) -#define bY(x) (((ia64_insn) ((x) & 0x1)) << 26) - -#define mBtype bBtype (-1) -#define mD bD (-1) -#define mPa bPa (-1) -#define mPr bPr (-1) -#define mVc bVc (-1) -#define mWha bWha (-1) -#define mX3 bX3 (-1) -#define mX6 bX6 (-1) -#define mY bY (-1) - -#define OpX3X6(a,b,c) (bOp (a) | bX3 (b) | bX6(c)), \ - (mOp | mX3 | mX6) -#define OpX3X6Y(a,b,c,d) (bOp (a) | bX3 (b) | bX6(c) | bY(d)), \ - (mOp | mX3 | mX6 | mY) -#define OpVc(a,b) (bOp (a) | bVc (b)), (mOp | mVc) -#define OpPaWhaD(a,b,c,d) \ - (bOp (a) | bPa (b) | bWha (c) | bD (d)), (mOp | mPa | mWha | mD) -#define OpBtypePaWhaD(a,b,c,d,e) \ - (bOp (a) | bBtype (b) | bPa (c) | bWha (d) | bD (e)), \ - (mOp | mBtype | mPa | mWha | mD) -#define OpBtypePaWhaDPr(a,b,c,d,e,f) \ - (bOp (a) | bBtype (b) | bPa (c) | bWha (d) | bD (e) | bPr (f)), \ - (mOp | mBtype | mPa | mWha | mD | mPr) - -struct ia64_opcode ia64_opcodes_x[] =3D - { - {"break.x", X0, OpX3X6 (0, 0, 0x00), {IMMU62}, 0, 0, NULL}, - {"nop.x", X0, OpX3X6Y (0, 0, 0x01, 0), {IMMU62}, 0, 0, NULL}, - {"hint.x", X0, OpX3X6Y (0, 0, 0x01, 1), {IMMU62}, 0, 0, NULL}, - {"movl", X, OpVc (6, 0), {R1, IMMU64}, 0, 0, NULL}, -#define BRL(a,b) \ - X0, OpBtypePaWhaDPr (0xC, 0, a, 0, b, 0), {TGT64}, PSEUDO, 0, NULL - {"brl.few", BRL (0, 0)}, - {"brl", BRL (0, 0)}, - {"brl.few.clr", BRL (0, 1)}, - {"brl.clr", BRL (0, 1)}, - {"brl.many", BRL (1, 0)}, - {"brl.many.clr", BRL (1, 1)}, -#undef BRL -#define BRL(a,b,c) \ - X0, OpBtypePaWhaD (0xC, 0, a, b, c), {TGT64}, 0, 0, NULL -#define BRLP(a,b,c) \ - X0, OpBtypePaWhaD (0xC, 0, a, b, c), {TGT64}, PSEUDO, 0, NULL - {"brl.cond.sptk.few", BRL (0, 0, 0)}, - {"brl.cond.sptk", BRLP (0, 0, 0)}, - {"brl.cond.sptk.few.clr", BRL (0, 0, 1)}, - {"brl.cond.sptk.clr", BRLP (0, 0, 1)}, - {"brl.cond.spnt.few", BRL (0, 1, 0)}, - {"brl.cond.spnt", BRLP (0, 1, 0)}, - {"brl.cond.spnt.few.clr", BRL (0, 1, 1)}, - {"brl.cond.spnt.clr", BRLP (0, 1, 1)}, - {"brl.cond.dptk.few", BRL (0, 2, 0)}, - {"brl.cond.dptk", BRLP (0, 2, 0)}, - {"brl.cond.dptk.few.clr", BRL (0, 2, 1)}, - {"brl.cond.dptk.clr", BRLP (0, 2, 1)}, - {"brl.cond.dpnt.few", BRL (0, 3, 0)}, - {"brl.cond.dpnt", BRLP (0, 3, 0)}, - {"brl.cond.dpnt.few.clr", BRL (0, 3, 1)}, - {"brl.cond.dpnt.clr", BRLP (0, 3, 1)}, - {"brl.cond.sptk.many", BRL (1, 0, 0)}, - {"brl.cond.sptk.many.clr", BRL (1, 0, 1)}, - {"brl.cond.spnt.many", BRL (1, 1, 0)}, - {"brl.cond.spnt.many.clr", BRL (1, 1, 1)}, - {"brl.cond.dptk.many", BRL (1, 2, 0)}, - {"brl.cond.dptk.many.clr", BRL (1, 2, 1)}, - {"brl.cond.dpnt.many", BRL (1, 3, 0)}, - {"brl.cond.dpnt.many.clr", BRL (1, 3, 1)}, - {"brl.sptk.few", BRL (0, 0, 0)}, - {"brl.sptk", BRLP (0, 0, 0)}, - {"brl.sptk.few.clr", BRL (0, 0, 1)}, - {"brl.sptk.clr", BRLP (0, 0, 1)}, - {"brl.spnt.few", BRL (0, 1, 0)}, - {"brl.spnt", BRLP (0, 1, 0)}, - {"brl.spnt.few.clr", BRL (0, 1, 1)}, - {"brl.spnt.clr", BRLP (0, 1, 1)}, - {"brl.dptk.few", BRL (0, 2, 0)}, - {"brl.dptk", BRLP (0, 2, 0)}, - {"brl.dptk.few.clr", BRL (0, 2, 1)}, - {"brl.dptk.clr", BRLP (0, 2, 1)}, - {"brl.dpnt.few", BRL (0, 3, 0)}, - {"brl.dpnt", BRLP (0, 3, 0)}, - {"brl.dpnt.few.clr", BRL (0, 3, 1)}, - {"brl.dpnt.clr", BRLP (0, 3, 1)}, - {"brl.sptk.many", BRL (1, 0, 0)}, - {"brl.sptk.many.clr", BRL (1, 0, 1)}, - {"brl.spnt.many", BRL (1, 1, 0)}, - {"brl.spnt.many.clr", BRL (1, 1, 1)}, - {"brl.dptk.many", BRL (1, 2, 0)}, - {"brl.dptk.many.clr", BRL (1, 2, 1)}, - {"brl.dpnt.many", BRL (1, 3, 0)}, - {"brl.dpnt.many.clr", BRL (1, 3, 1)}, -#undef BRL -#undef BRLP -#define BRL(a,b,c) X, OpPaWhaD (0xD, a, b, c), {B1, TGT64}, 0, 0, NULL -#define BRLP(a,b,c) X, OpPaWhaD (0xD, a, b, c), {B1, TGT64}, PSEUDO, 0, NU= LL - {"brl.call.sptk.few", BRL (0, 0, 0)}, - {"brl.call.sptk", BRLP (0, 0, 0)}, - {"brl.call.sptk.few.clr", BRL (0, 0, 1)}, - {"brl.call.sptk.clr", BRLP (0, 0, 1)}, - {"brl.call.spnt.few", BRL (0, 1, 0)}, - {"brl.call.spnt", BRLP (0, 1, 0)}, - {"brl.call.spnt.few.clr", BRL (0, 1, 1)}, - {"brl.call.spnt.clr", BRLP (0, 1, 1)}, - {"brl.call.dptk.few", BRL (0, 2, 0)}, - {"brl.call.dptk", BRLP (0, 2, 0)}, - {"brl.call.dptk.few.clr", BRL (0, 2, 1)}, - {"brl.call.dptk.clr", BRLP (0, 2, 1)}, - {"brl.call.dpnt.few", BRL (0, 3, 0)}, - {"brl.call.dpnt", BRLP (0, 3, 0)}, - {"brl.call.dpnt.few.clr", BRL (0, 3, 1)}, - {"brl.call.dpnt.clr", BRLP (0, 3, 1)}, - {"brl.call.sptk.many", BRL (1, 0, 0)}, - {"brl.call.sptk.many.clr", BRL (1, 0, 1)}, - {"brl.call.spnt.many", BRL (1, 1, 0)}, - {"brl.call.spnt.many.clr", BRL (1, 1, 1)}, - {"brl.call.dptk.many", BRL (1, 2, 0)}, - {"brl.call.dptk.many.clr", BRL (1, 2, 1)}, - {"brl.call.dpnt.many", BRL (1, 3, 0)}, - {"brl.call.dpnt.many.clr", BRL (1, 3, 1)}, -#undef BRL -#undef BRLP - {NULL, 0, 0, 0, 0, {0}, 0, 0, NULL} - }; - -#undef X0 -#undef X - -#undef bBtype -#undef bD -#undef bPa -#undef bPr -#undef bVc -#undef bWha -#undef bX3 -#undef bX6 - -#undef mBtype -#undef mD -#undef mPa -#undef mPr -#undef mVc -#undef mWha -#undef mX3 -#undef mX6 - -#undef OpX3X6 -#undef OpVc -#undef OpPaWhaD -#undef OpBtypePaWhaD -#undef OpBtypePaWhaDPr diff --git a/opcodes/ia64-opc.c b/opcodes/ia64-opc.c deleted file mode 100644 index 34684b4214f..00000000000 --- a/opcodes/ia64-opc.c +++ /dev/null @@ -1,735 +0,0 @@ -/* ia64-opc.c -- Functions to access the compacted opcode table - Copyright (C) 1999-2024 Free Software Foundation, Inc. - Written by Bob Manson of Cygnus Solutions, - - This file is part of the GNU opcodes library. - - This library is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3, or (at your option) - any later version. - - It is distributed in the hope that it will be useful, but WITHOUT - ANY WARRANTY; without even the implied warranty of MERCHANTABILITY - or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public - License for more details. - - You should have received a copy of the GNU General Public License - along with this file; see the file COPYING. If not, write to the - Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston, - MA 02110-1301, USA. */ - -#include "sysdep.h" -#include "libiberty.h" -#include "ia64-asmtab.h" -#include "ia64-asmtab.c" - -static void get_opc_prefix (const char **, char *); -static short int find_string_ent (const char *); -static short int find_main_ent (short int); -static short int find_completer (short int, short int, const char *); -static ia64_insn apply_completer (ia64_insn, int); -static int extract_op_bits (int, int, int); -static int extract_op (int, int *, unsigned int *); -static int opcode_verify (ia64_insn, int, enum ia64_insn_type); -static int locate_opcode_ent (ia64_insn, enum ia64_insn_type); -static struct ia64_opcode *make_ia64_opcode - (ia64_insn, const char *, int, int); -static struct ia64_opcode *ia64_find_matching_opcode - (const char *, short int); - -const struct ia64_templ_desc ia64_templ_desc[16] =3D - { - { 0, { IA64_UNIT_M, IA64_UNIT_I, IA64_UNIT_I }, "MII" }, /* 0 */ - { 2, { IA64_UNIT_M, IA64_UNIT_I, IA64_UNIT_I }, "MII" }, - { 0, { IA64_UNIT_M, IA64_UNIT_L, IA64_UNIT_X }, "MLX" }, - { 0, { 0, }, "-3-" }, - { 0, { IA64_UNIT_M, IA64_UNIT_M, IA64_UNIT_I }, "MMI" }, /* 4 */ - { 1, { IA64_UNIT_M, IA64_UNIT_M, IA64_UNIT_I }, "MMI" }, - { 0, { IA64_UNIT_M, IA64_UNIT_F, IA64_UNIT_I }, "MFI" }, - { 0, { IA64_UNIT_M, IA64_UNIT_M, IA64_UNIT_F }, "MMF" }, - { 0, { IA64_UNIT_M, IA64_UNIT_I, IA64_UNIT_B }, "MIB" }, /* 8 */ - { 0, { IA64_UNIT_M, IA64_UNIT_B, IA64_UNIT_B }, "MBB" }, - { 0, { 0, }, "-a-" }, - { 0, { IA64_UNIT_B, IA64_UNIT_B, IA64_UNIT_B }, "BBB" }, - { 0, { IA64_UNIT_M, IA64_UNIT_M, IA64_UNIT_B }, "MMB" }, /* c */ - { 0, { 0, }, "-d-" }, - { 0, { IA64_UNIT_M, IA64_UNIT_F, IA64_UNIT_B }, "MFB" }, - { 0, { 0, }, "-f-" }, - }; - - -/* Copy the prefix contained in *PTR (up to a '.' or a NUL) to DEST. - PTR will be adjusted to point to the start of the next portion - of the opcode, or at the NUL character. */ - -static void -get_opc_prefix (const char **ptr, char *dest) -{ - char *c =3D strchr (*ptr, '.'); - if (c !=3D NULL) - { - memcpy (dest, *ptr, c - *ptr); - dest[c - *ptr] =3D '\0'; - *ptr =3D c + 1; - } - else - { - int l =3D strlen (*ptr); - memcpy (dest, *ptr, l); - dest[l] =3D '\0'; - *ptr +=3D l; - } -} -=0C -/* Find the index of the entry in the string table corresponding to - STR; return -1 if one does not exist. */ - -static short -find_string_ent (const char *str) -{ - short start =3D 0; - short end =3D sizeof (ia64_strings) / sizeof (const char *); - short i =3D (start + end) / 2; - - if (strcmp (str, ia64_strings[end - 1]) > 0) - { - return -1; - } - while (start <=3D end) - { - int c =3D strcmp (str, ia64_strings[i]); - if (c < 0) - { - end =3D i - 1; - } - else if (c =3D=3D 0) - { - return i; - } - else - { - start =3D i + 1; - } - i =3D (start + end) / 2; - } - return -1; -} -=0C -/* Find the opcode in the main opcode table whose name is STRINGINDEX, or - return -1 if one does not exist. */ - -static short -find_main_ent (short nameindex) -{ - short start =3D 0; - short end =3D ARRAY_SIZE (main_table); - short i =3D (start + end) / 2; - - if (nameindex < main_table[0].name_index - || nameindex > main_table[end - 1].name_index) - { - return -1; - } - while (start <=3D end) - { - if (nameindex < main_table[i].name_index) - { - end =3D i - 1; - } - else if (nameindex =3D=3D main_table[i].name_index) - { - while (i > 0 && main_table[i - 1].name_index =3D=3D nameindex) - { - i--; - } - return i; - } - else - { - start =3D i + 1; - } - i =3D (start + end) / 2; - } - return -1; -} -=0C -/* Find the index of the entry in the completer table that is part of - MAIN_ENT (starting from PREV_COMPLETER) that matches NAME, or - return -1 if one does not exist. */ - -static short -find_completer (short main_ent, short prev_completer, const char *name) -{ - short name_index =3D find_string_ent (name); - - if (name_index < 0) - { - return -1; - } - - if (prev_completer =3D=3D -1) - { - prev_completer =3D main_table[main_ent].completers; - } - else - { - prev_completer =3D completer_table[prev_completer].subentries; - } - - while (prev_completer !=3D -1) - { - if (completer_table[prev_completer].name_index =3D=3D name_index) - { - return prev_completer; - } - prev_completer =3D completer_table[prev_completer].alternative; - } - return -1; -} -=0C -/* Apply the completer referred to by COMPLETER_INDEX to OPCODE, and - return the result. */ - -static ia64_insn -apply_completer (ia64_insn opcode, int completer_index) -{ - ia64_insn mask =3D completer_table[completer_index].mask; - ia64_insn bits =3D completer_table[completer_index].bits; - int shiftamt =3D (completer_table[completer_index].offset & 63); - - mask =3D mask << shiftamt; - bits =3D bits << shiftamt; - opcode =3D (opcode & ~mask) | bits; - return opcode; -} -=0C -/* Extract BITS number of bits starting from OP_POINTER + BITOFFSET in - the dis_table array, and return its value. (BITOFFSET is numbered - starting from MSB to LSB, so a BITOFFSET of 0 indicates the MSB of the - first byte in OP_POINTER.) */ - -static int -extract_op_bits (int op_pointer, int bitoffset, int bits) -{ - int res =3D 0; - - op_pointer +=3D (bitoffset / 8); - - if (bitoffset % 8) - { - unsigned int op =3D dis_table[op_pointer++]; - int numb =3D 8 - (bitoffset % 8); - int mask =3D (1 << numb) - 1; - int bata =3D (bits < numb) ? bits : numb; - int delta =3D numb - bata; - - res =3D (res << bata) | ((op & mask) >> delta); - bitoffset +=3D bata; - bits -=3D bata; - } - while (bits >=3D 8) - { - res =3D (res << 8) | (dis_table[op_pointer++] & 255); - bits -=3D 8; - } - if (bits > 0) - { - unsigned int op =3D (dis_table[op_pointer++] & 255); - res =3D (res << bits) | (op >> (8 - bits)); - } - return res; -} -=0C -/* Examine the state machine entry at OP_POINTER in the dis_table - array, and extract its values into OPVAL and OP. The length of the - state entry in bits is returned. */ - -static int -extract_op (int op_pointer, int *opval, unsigned int *op) -{ - int oplen =3D 5; - - *op =3D dis_table[op_pointer]; - - if ((*op) & 0x40) - { - opval[0] =3D extract_op_bits (op_pointer, oplen, 5); - oplen +=3D 5; - } - switch ((*op) & 0x30) - { - case 0x10: - { - opval[1] =3D extract_op_bits (op_pointer, oplen, 8); - oplen +=3D 8; - opval[1] +=3D op_pointer; - break; - } - case 0x20: - { - opval[1] =3D extract_op_bits (op_pointer, oplen, 16); - if (! (opval[1] & 32768)) - { - opval[1] +=3D op_pointer; - } - oplen +=3D 16; - break; - } - case 0x30: - { - oplen--; - opval[2] =3D extract_op_bits (op_pointer, oplen, 12); - oplen +=3D 12; - opval[2] |=3D 32768; - break; - } - } - if (((*op) & 0x08) && (((*op) & 0x30) !=3D 0x30)) - { - opval[2] =3D extract_op_bits (op_pointer, oplen, 16); - oplen +=3D 16; - if (! (opval[2] & 32768)) - { - opval[2] +=3D op_pointer; - } - } - return oplen; -} -=0C -/* Returns a non-zero value if the opcode in the main_table list at - PLACE matches OPCODE and is of type TYPE. */ - -static int -opcode_verify (ia64_insn opcode, int place, enum ia64_insn_type type) -{ - if (main_table[place].opcode_type !=3D type) - { - return 0; - } - if (main_table[place].flags - & (IA64_OPCODE_F2_EQ_F3 | IA64_OPCODE_LEN_EQ_64MCNT)) - { - const struct ia64_operand *o1, *o2; - ia64_insn f2, f3; - - if (main_table[place].flags & IA64_OPCODE_F2_EQ_F3) - { - o1 =3D elf64_ia64_operands + IA64_OPND_F2; - o2 =3D elf64_ia64_operands + IA64_OPND_F3; - (*o1->extract) (o1, opcode, &f2); - (*o2->extract) (o2, opcode, &f3); - if (f2 !=3D f3) - return 0; - } - else - { - ia64_insn len, count; - - /* length must equal 64-count: */ - o1 =3D elf64_ia64_operands + IA64_OPND_LEN6; - o2 =3D elf64_ia64_operands + main_table[place].operands[2]; - (*o1->extract) (o1, opcode, &len); - (*o2->extract) (o2, opcode, &count); - if (len !=3D 64 - count) - return 0; - } - } - return 1; -} -=0C -/* Find an instruction entry in the ia64_dis_names array that matches - opcode OPCODE and is of type TYPE. Returns either a positive index - into the array, or a negative value if an entry for OPCODE could - not be found. Checks all matches and returns the one with the highest - priority. */ - -static int -locate_opcode_ent (ia64_insn opcode, enum ia64_insn_type type) -{ - int currtest[41]; - int bitpos[41]; - int op_ptr[41]; - int currstatenum =3D 0; - short found_disent =3D -1; - short found_priority =3D -1; - - currtest[currstatenum] =3D 0; - op_ptr[currstatenum] =3D 0; - bitpos[currstatenum] =3D 40; - - while (1) - { - int op_pointer =3D op_ptr[currstatenum]; - unsigned int op; - int currbitnum =3D bitpos[currstatenum]; - int oplen; - int opval[3] =3D {0}; - int next_op; - int currbit; - - oplen =3D extract_op (op_pointer, opval, &op); - - bitpos[currstatenum] =3D currbitnum; - - /* Skip opval[0] bits in the instruction. */ - if (op & 0x40) - { - currbitnum -=3D opval[0]; - } - - if (currbitnum < 0) - currbitnum =3D 0; - - /* The value of the current bit being tested. */ - currbit =3D opcode & (((ia64_insn) 1) << currbitnum) ? 1 : 0; - next_op =3D -1; - - /* We always perform the tests specified in the current state in - a particular order, falling through to the next test if the - previous one failed. */ - switch (currtest[currstatenum]) - { - case 0: - currtest[currstatenum]++; - if (currbit =3D=3D 0 && (op & 0x80)) - { - /* Check for a zero bit. If this test solely checks for - a zero bit, we can check for up to 8 consecutive zero - bits (the number to check is specified by the lower 3 - bits in the state code.) - - If the state instruction matches, we go to the very - next state instruction; otherwise, try the next test. */ - - if ((op & 0xf8) =3D=3D 0x80) - { - int count =3D op & 0x7; - int x; - - for (x =3D 0; x <=3D count; x++) - { - int i =3D - opcode & (((ia64_insn) 1) << (currbitnum - x)) ? 1 : 0; - if (i) - { - break; - } - } - if (x > count) - { - next_op =3D op_pointer + ((oplen + 7) / 8); - currbitnum -=3D count; - break; - } - } - else if (! currbit) - { - next_op =3D op_pointer + ((oplen + 7) / 8); - break; - } - } - /* FALLTHROUGH */ - case 1: - /* If the bit in the instruction is one, go to the state - instruction specified by opval[1]. */ - currtest[currstatenum]++; - if (currbit && (op & 0x30) !=3D 0 && ((op & 0x30) !=3D 0x30)) - { - next_op =3D opval[1]; - break; - } - /* FALLTHROUGH */ - case 2: - /* Don't care. Skip the current bit and go to the state - instruction specified by opval[2]. - - An encoding of 0x30 is special; this means that a 12-bit - offset into the ia64_dis_names[] array is specified. */ - currtest[currstatenum]++; - if ((op & 0x08) || ((op & 0x30) =3D=3D 0x30)) - { - next_op =3D opval[2]; - break; - } - } - - /* If bit 15 is set in the address of the next state, an offset - in the ia64_dis_names array was specified instead. We then - check to see if an entry in the list of opcodes matches the - opcode we were given; if so, we have succeeded. */ - - if ((next_op >=3D 0) && (next_op & 32768)) - { - short disent =3D next_op & 32767; - short priority =3D -1; - - if (next_op > 65535) - { - return -1; - } - - /* Run through the list of opcodes to check, trying to find - one that matches. */ - while (disent >=3D 0) - { - int place =3D ia64_dis_names[disent].insn_index; - - priority =3D ia64_dis_names[disent].priority; - - if (opcode_verify (opcode, place, type) - && priority > found_priority) - { - break; - } - if (ia64_dis_names[disent].next_flag) - { - disent++; - } - else - { - disent =3D -1; - } - } - - if (disent >=3D 0) - { - found_disent =3D disent; - found_priority =3D priority; - } - /* Try the next test in this state, regardless of whether a match - was found. */ - next_op =3D -2; - } - - /* next_op =3D=3D -1 is "back up to the previous state". - next_op =3D=3D -2 is "stay in this state and try the next test". - Otherwise, transition to the state indicated by next_op. */ - - if (next_op =3D=3D -1) - { - currstatenum--; - if (currstatenum < 0) - { - return found_disent; - } - } - else if (next_op >=3D 0) - { - currstatenum++; - bitpos[currstatenum] =3D currbitnum - 1; - op_ptr[currstatenum] =3D next_op; - currtest[currstatenum] =3D 0; - } - } -} -=0C -/* Construct an ia64_opcode entry based on OPCODE, NAME and PLACE. */ - -static struct ia64_opcode * -make_ia64_opcode (ia64_insn opcode, const char *name, int place, int depin= d) -{ - struct ia64_opcode *res =3D - (struct ia64_opcode *) xmalloc (sizeof (struct ia64_opcode)); - res->name =3D xstrdup (name); - res->type =3D main_table[place].opcode_type; - res->num_outputs =3D main_table[place].num_outputs; - res->opcode =3D opcode; - res->mask =3D main_table[place].mask; - res->operands[0] =3D main_table[place].operands[0]; - res->operands[1] =3D main_table[place].operands[1]; - res->operands[2] =3D main_table[place].operands[2]; - res->operands[3] =3D main_table[place].operands[3]; - res->operands[4] =3D main_table[place].operands[4]; - res->flags =3D main_table[place].flags; - res->ent_index =3D place; - res->dependencies =3D &op_dependencies[depind]; - return res; -} -=0C -/* Determine the ia64_opcode entry for the opcode specified by INSN - and TYPE. If a valid entry is not found, return NULL. */ -struct ia64_opcode * -ia64_dis_opcode (ia64_insn insn, enum ia64_insn_type type) -{ - int disent =3D locate_opcode_ent (insn, type); - - if (disent < 0) - { - return NULL; - } - else - { - unsigned int cb =3D ia64_dis_names[disent].completer_index; - static char name[128]; - int place =3D ia64_dis_names[disent].insn_index; - int ci =3D main_table[place].completers; - ia64_insn tinsn =3D main_table[place].opcode; - - strcpy (name, ia64_strings [main_table[place].name_index]); - - while (cb) - { - if (cb & 1) - { - int cname =3D completer_table[ci].name_index; - - tinsn =3D apply_completer (tinsn, ci); - - if (ia64_strings[cname][0] !=3D '\0') - { - strcat (name, "."); - strcat (name, ia64_strings[cname]); - } - if (cb !=3D 1) - { - ci =3D completer_table[ci].subentries; - } - } - else - { - ci =3D completer_table[ci].alternative; - } - if (ci < 0) - { - abort (); - } - cb =3D cb >> 1; - } - if (tinsn !=3D (insn & main_table[place].mask)) - { - abort (); - } - return make_ia64_opcode (insn, name, place, - completer_table[ci].dependencies); - } -} -=0C -/* Search the main_opcode table starting from PLACE for an opcode that - matches NAME. Return NULL if one is not found. */ - -static struct ia64_opcode * -ia64_find_matching_opcode (const char *name, short place) -{ - char op[129]; - const char *suffix; - short name_index; - - if ((unsigned) place >=3D ARRAY_SIZE (main_table)) - return NULL; - - if (strlen (name) > 128) - { - return NULL; - } - suffix =3D name; - get_opc_prefix (&suffix, op); - name_index =3D find_string_ent (op); - if (name_index < 0) - { - return NULL; - } - - while (main_table[place].name_index =3D=3D name_index) - { - const char *curr_suffix =3D suffix; - ia64_insn curr_insn =3D main_table[place].opcode; - short completer =3D -1; - - do { - if (suffix[0] =3D=3D '\0') - { - completer =3D find_completer (place, completer, suffix); - } - else - { - get_opc_prefix (&curr_suffix, op); - completer =3D find_completer (place, completer, op); - } - if (completer !=3D -1) - { - curr_insn =3D apply_completer (curr_insn, completer); - } - } while (completer !=3D -1 && curr_suffix[0] !=3D '\0'); - - if (completer !=3D -1 && curr_suffix[0] =3D=3D '\0' - && completer_table[completer].terminal_completer) - { - int depind =3D completer_table[completer].dependencies; - return make_ia64_opcode (curr_insn, name, place, depind); - } - else - { - place++; - } - } - return NULL; -} -=0C -/* Find the next opcode after PREV_ENT that matches PREV_ENT, or return NU= LL - if one does not exist. - - It is the caller's responsibility to invoke ia64_free_opcode () to - release any resources used by the returned entry. */ - -struct ia64_opcode * -ia64_find_next_opcode (struct ia64_opcode *prev_ent) -{ - return ia64_find_matching_opcode (prev_ent->name, - prev_ent->ent_index + 1); -} - -/* Find the first opcode that matches NAME, or return NULL if it does - not exist. - - It is the caller's responsibility to invoke ia64_free_opcode () to - release any resources used by the returned entry. */ - -struct ia64_opcode * -ia64_find_opcode (const char *name) -{ - char op[129]; - const char *suffix; - short place; - short name_index; - - if (strlen (name) > 128) - { - return NULL; - } - suffix =3D name; - get_opc_prefix (&suffix, op); - name_index =3D find_string_ent (op); - if (name_index < 0) - { - return NULL; - } - - place =3D find_main_ent (name_index); - - if (place < 0) - { - return NULL; - } - return ia64_find_matching_opcode (name, place); -} - -/* Free any resources used by ENT. */ -void -ia64_free_opcode (struct ia64_opcode *ent) -{ - free ((void *)ent->name); - free (ent); -} - -const struct ia64_dependency * -ia64_find_dependency (int dep_index) -{ - dep_index =3D DEP(dep_index); - - if (dep_index < 0 - || dep_index >=3D (int) ARRAY_SIZE (dependencies)) - return NULL; - - return &dependencies[dep_index]; -} diff --git a/opcodes/ia64-opc.h b/opcodes/ia64-opc.h deleted file mode 100644 index 786790f767b..00000000000 --- a/opcodes/ia64-opc.h +++ /dev/null @@ -1,138 +0,0 @@ -/* ia64-opc.h -- IA-64 opcode table. - Copyright (C) 1998-2024 Free Software Foundation, Inc. - Contributed by David Mosberger-Tang - - This file is part of the GNU opcodes library. - - This library is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3, or (at your option) - any later version. - - It is distributed in the hope that it will be useful, but WITHOUT - ANY WARRANTY; without even the implied warranty of MERCHANTABILITY - or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public - License for more details. - - You should have received a copy of the GNU General Public License - along with this file; see the file COPYING. If not, write to the - Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston, - MA 02110-1301, USA. */ - -#ifndef IA64_OPC_H -#define IA64_OPC_H - -#include "opcode/ia64.h" - -/* define a couple of abbreviations: */ - -#define bOp(x) (((ia64_insn) ((x) & 0xf)) << 37) -#define mOp bOp (-1) -#define Op(x) bOp (x), mOp - -#define FIRST IA64_OPCODE_FIRST -#define X_IN_MLX IA64_OPCODE_X_IN_MLX -#define LAST IA64_OPCODE_LAST -#define PRIV IA64_OPCODE_PRIV -#define NO_PRED IA64_OPCODE_NO_PRED -#define SLOT2 IA64_OPCODE_SLOT2 -#define PSEUDO IA64_OPCODE_PSEUDO -#define F2_EQ_F3 IA64_OPCODE_F2_EQ_F3 -#define LEN_EQ_64MCNT IA64_OPCODE_LEN_EQ_64MCNT -#define MOD_RRBS IA64_OPCODE_MOD_RRBS -#define POSTINC IA64_OPCODE_POSTINC - -#define AR_CCV IA64_OPND_AR_CCV -#define AR_PFS IA64_OPND_AR_PFS -#define AR_CSD IA64_OPND_AR_CSD -#define C1 IA64_OPND_C1 -#define C8 IA64_OPND_C8 -#define C16 IA64_OPND_C16 -#define GR0 IA64_OPND_GR0 -#define IP IA64_OPND_IP -#define PR IA64_OPND_PR -#define PR_ROT IA64_OPND_PR_ROT -#define PSR IA64_OPND_PSR -#define PSR_L IA64_OPND_PSR_L -#define PSR_UM IA64_OPND_PSR_UM - -#define AR3 IA64_OPND_AR3 -#define B1 IA64_OPND_B1 -#define B2 IA64_OPND_B2 -#define CR3 IA64_OPND_CR3 -#define F1 IA64_OPND_F1 -#define F2 IA64_OPND_F2 -#define F3 IA64_OPND_F3 -#define F4 IA64_OPND_F4 -#define P1 IA64_OPND_P1 -#define P2 IA64_OPND_P2 -#define R1 IA64_OPND_R1 -#define R2 IA64_OPND_R2 -#define R3 IA64_OPND_R3 -#define R3_2 IA64_OPND_R3_2 -#define DAHR IA64_OPND_DAHR3 - -#define CPUID_R3 IA64_OPND_CPUID_R3 -#define DBR_R3 IA64_OPND_DBR_R3 -#define DTR_R3 IA64_OPND_DTR_R3 -#define ITR_R3 IA64_OPND_ITR_R3 -#define IBR_R3 IA64_OPND_IBR_R3 -#define MR3 IA64_OPND_MR3 -#define MSR_R3 IA64_OPND_MSR_R3 -#define PKR_R3 IA64_OPND_PKR_R3 -#define PMC_R3 IA64_OPND_PMC_R3 -#define PMD_R3 IA64_OPND_PMD_R3 -#define DAHR_R3 IA64_OPND_DAHR_R3 -#define RR_R3 IA64_OPND_RR_R3 - -#define CCNT5 IA64_OPND_CCNT5 -#define CNT2a IA64_OPND_CNT2a -#define CNT2b IA64_OPND_CNT2b -#define CNT2c IA64_OPND_CNT2c -#define CNT5 IA64_OPND_CNT5 -#define CNT6 IA64_OPND_CNT6 -#define CPOS6a IA64_OPND_CPOS6a -#define CPOS6b IA64_OPND_CPOS6b -#define CPOS6c IA64_OPND_CPOS6c -#define IMM1 IA64_OPND_IMM1 -#define IMM14 IA64_OPND_IMM14 -#define IMM17 IA64_OPND_IMM17 -#define IMM22 IA64_OPND_IMM22 -#define IMM44 IA64_OPND_IMM44 -#define SOF IA64_OPND_SOF -#define SOL IA64_OPND_SOL -#define SOR IA64_OPND_SOR -#define IMM8 IA64_OPND_IMM8 -#define IMM8U4 IA64_OPND_IMM8U4 -#define IMM8M1 IA64_OPND_IMM8M1 -#define IMM8M1U4 IA64_OPND_IMM8M1U4 -#define IMM8M1U8 IA64_OPND_IMM8M1U8 -#define IMM9a IA64_OPND_IMM9a -#define IMM9b IA64_OPND_IMM9b -#define IMMU2 IA64_OPND_IMMU2 -#define IMMU16 IA64_OPND_IMMU16 -#define IMMU19 IA64_OPND_IMMU19 -#define IMMU21 IA64_OPND_IMMU21 -#define IMMU24 IA64_OPND_IMMU24 -#define IMMU62 IA64_OPND_IMMU62 -#define IMMU64 IA64_OPND_IMMU64 -#define IMMU5b IA64_OPND_IMMU5b -#define IMMU7a IA64_OPND_IMMU7a -#define IMMU7b IA64_OPND_IMMU7b -#define IMMU9 IA64_OPND_IMMU9 -#define INC3 IA64_OPND_INC3 -#define LEN4 IA64_OPND_LEN4 -#define LEN6 IA64_OPND_LEN6 -#define MBTYPE4 IA64_OPND_MBTYPE4 -#define MHTYPE8 IA64_OPND_MHTYPE8 -#define POS6 IA64_OPND_POS6 -#define TAG13 IA64_OPND_TAG13 -#define TAG13b IA64_OPND_TAG13b -#define TGT25 IA64_OPND_TGT25 -#define TGT25b IA64_OPND_TGT25b -#define TGT25c IA64_OPND_TGT25c -#define TGT64 IA64_OPND_TGT64 -#define CNT6a IA64_OPND_CNT6a -#define STRD5b IA64_OPND_STRD5b - -#endif diff --git a/opcodes/ia64-raw.tbl b/opcodes/ia64-raw.tbl deleted file mode 100644 index 1dcb9082050..00000000000 --- a/opcodes/ia64-raw.tbl +++ /dev/null @@ -1,199 +0,0 @@ -Resource Name; Writers; Readers; Semantics of Dependency -ALAT; chk.a.clr, IC:mem-readers-alat, IC:mem-writers, IC:invala-all; IC:me= m-readers-alat, IC:mem-writers, IC:chk-a, invala.e; none -AR[BSP]; br.call, brl.call, br.ret, cover, IC:mov-to-AR-BSPSTORE, rfi; br.= call, brl.call, br.ia, br.ret, cover, flushrs, loadrs, IC:mov-from-AR-BSP, = rfi; impliedF -AR[BSPSTORE]; alloc, loadrs, flushrs, IC:mov-to-AR-BSPSTORE; alloc, br.ia,= flushrs, IC:mov-from-AR-BSPSTORE; impliedF -AR[CCV]; IC:mov-to-AR-CCV; br.ia, IC:cmpxchg, IC:mov-from-AR-CCV; impliedF -AR[CFLG]; IC:mov-to-AR-CFLG; br.ia, IC:mov-from-AR-CFLG; impliedF -AR[CSD]; ld16, IC:mov-to-AR-CSD; br.ia, cmp8xchg16, IC:mov-from-AR-CSD, st= 16; impliedF -AR[EC]; IC:mod-sched-brs, br.ret, IC:mov-to-AR-EC; br.call, brl.call, br.i= a, IC:mod-sched-brs, IC:mov-from-AR-EC; impliedF -AR[EFLAG]; IC:mov-to-AR-EFLAG; br.ia, IC:mov-from-AR-EFLAG; impliedF -AR[FCR]; IC:mov-to-AR-FCR; br.ia, IC:mov-from-AR-FCR; impliedF -AR[FDR]; IC:mov-to-AR-FDR; br.ia, IC:mov-from-AR-FDR; impliedF -AR[FIR]; IC:mov-to-AR-FIR; br.ia, IC:mov-from-AR-FIR; impliedF -AR[FPSR].sf0.controls; IC:mov-to-AR-FPSR, fsetc.s0; br.ia, IC:fp-arith-s0,= IC:fcmp-s0, IC:fpcmp-s0, fsetc, IC:mov-from-AR-FPSR; impliedF -AR[FPSR].sf1.controls; IC:mov-to-AR-FPSR, fsetc.s1; br.ia, IC:fp-arith-s1,= IC:fcmp-s1, IC:fpcmp-s1, IC:mov-from-AR-FPSR; impliedF -AR[FPSR].sf2.controls; IC:mov-to-AR-FPSR, fsetc.s2; br.ia, IC:fp-arith-s2,= IC:fcmp-s2, IC:fpcmp-s2, IC:mov-from-AR-FPSR; impliedF -AR[FPSR].sf3.controls; IC:mov-to-AR-FPSR, fsetc.s3; br.ia, IC:fp-arith-s3,= IC:fcmp-s3, IC:fpcmp-s3, IC:mov-from-AR-FPSR; impliedF -AR[FPSR].sf0.flags; IC:fp-arith-s0, fclrf.s0, IC:fcmp-s0, IC:fpcmp-s0, IC:= mov-to-AR-FPSR; br.ia, fchkf, IC:mov-from-AR-FPSR; impliedF -AR[FPSR].sf1.flags; IC:fp-arith-s1, fclrf.s1, IC:fcmp-s1, IC:fpcmp-s1, IC:= mov-to-AR-FPSR; br.ia, fchkf.s1, IC:mov-from-AR-FPSR; impliedF -AR[FPSR].sf2.flags; IC:fp-arith-s2, fclrf.s2, IC:fcmp-s2, IC:fpcmp-s2, IC:= mov-to-AR-FPSR; br.ia, fchkf.s2, IC:mov-from-AR-FPSR; impliedF -AR[FPSR].sf3.flags; IC:fp-arith-s3, fclrf.s3, IC:fcmp-s3, IC:fpcmp-s3, IC:= mov-to-AR-FPSR; br.ia, fchkf.s3, IC:mov-from-AR-FPSR; impliedF -AR[FPSR].traps; IC:mov-to-AR-FPSR; br.ia, IC:fp-arith, fchkf, fcmp, fpcmp,= IC:mov-from-AR-FPSR; impliedF -AR[FPSR].rv; IC:mov-to-AR-FPSR; br.ia, IC:fp-arith, fchkf, fcmp, fpcmp, IC= :mov-from-AR-FPSR; impliedF -AR[FSR]; IC:mov-to-AR-FSR; br.ia, IC:mov-from-AR-FSR; impliedF -AR[ITC]; IC:mov-to-AR-ITC; br.ia, IC:mov-from-AR-ITC; impliedF -AR[K%], % in 0 - 7; IC:mov-to-AR-K+1; br.ia, IC:mov-from-AR-K+1; impliedF -AR[LC]; IC:mod-sched-brs-counted, IC:mov-to-AR-LC; br.ia, IC:mod-sched-brs= -counted, IC:mov-from-AR-LC; impliedF -AR[PFS]; br.call, brl.call; alloc, br.ia, br.ret, epc, IC:mov-from-AR-PFS;= impliedF -AR[PFS]; IC:mov-to-AR-PFS; alloc, br.ia, epc, IC:mov-from-AR-PFS; impliedF -AR[PFS]; IC:mov-to-AR-PFS; br.ret; none -AR[RNAT]; alloc, flushrs, loadrs, IC:mov-to-AR-RNAT, IC:mov-to-AR-BSPSTORE= ; alloc, br.ia, flushrs, loadrs, IC:mov-from-AR-RNAT; impliedF -AR[RSC]; IC:mov-to-AR-RSC; alloc, br.ia, flushrs, loadrs, IC:mov-from-AR-R= SC, IC:mov-from-AR-BSPSTORE, IC:mov-to-AR-RNAT, IC:mov-from-AR-RNAT, IC:mov= -to-AR-BSPSTORE; impliedF -AR[RUC]; IC:mov-to-AR-RUC; br.ia, IC:mov-from-AR-RUC; impliedF -AR[SSD]; IC:mov-to-AR-SSD; br.ia, IC:mov-from-AR-SSD; impliedF -AR[UNAT]{%}, % in 0 - 63; IC:mov-to-AR-UNAT, st8.spill; br.ia, ld8.fill, I= C:mov-from-AR-UNAT; impliedF -AR%, % in 8-15, 20, 22-23, 31, 33-35, 37-39, 41-43, 46-47, 67-111; IC:none= ; br.ia, IC:mov-from-AR-rv+1; none -AR%, % in 48-63, 112-127; IC:mov-to-AR-ig+1; br.ia, IC:mov-from-AR-ig+1; i= mpliedF -BR%, % in 0 - 7; br.call+1, brl.call+1; IC:indirect-brs+1, IC:indirect-brp= +1, IC:mov-from-BR+1; impliedF -BR%, % in 0 - 7; IC:mov-to-BR+1; IC:indirect-brs+1; none -BR%, % in 0 - 7; IC:mov-to-BR+1; IC:indirect-brp+1, IC:mov-from-BR+1; impl= iedF -CFM; IC:mod-sched-brs; IC:mod-sched-brs; impliedF -CFM; IC:mod-sched-brs; cover, alloc, rfi, loadrs, br.ret, br.call, brl.cal= l; impliedF -CFM; IC:mod-sched-brs; IC:cfm-readers+2; impliedF -CFM; br.call, brl.call, br.ret, clrrrb, cover, rfi; IC:cfm-readers; implie= dF -CFM; alloc; IC:cfm-readers; none -CPUID#; IC:none; IC:mov-from-IND-CPUID+3; specific -CR[CMCV]; IC:mov-to-CR-CMCV; IC:mov-from-CR-CMCV; data -CR[DCR]; IC:mov-to-CR-DCR; IC:mov-from-CR-DCR, IC:mem-readers-spec; data -CR[EOI]; IC:mov-to-CR-EOI; IC:none; SC Section 5.8.3.4, "End of External I= nterrupt Register (EOI - CR67)" on page 2:119 -CR[GPTA]; IC:mov-to-CR-GPTA; IC:mov-from-CR-GPTA, thash; data -CR[IFA]; IC:mov-to-CR-IFA; itc.i, itc.d, itr.i, itr.d; implied -CR[IFA]; IC:mov-to-CR-IFA; IC:mov-from-CR-IFA; data -CR[IFS]; IC:mov-to-CR-IFS; IC:mov-from-CR-IFS; data -CR[IFS]; IC:mov-to-CR-IFS; rfi; implied -CR[IFS]; cover; rfi, IC:mov-from-CR-IFS; implied -CR[IHA]; IC:mov-to-CR-IHA; IC:mov-from-CR-IHA; data -CR[IIB%], % in 0 - 1; IC:mov-to-CR-IIB; IC:mov-from-CR-IIB; data -CR[IIM]; IC:mov-to-CR-IIM; IC:mov-from-CR-IIM; data -CR[IIP]; IC:mov-to-CR-IIP; IC:mov-from-CR-IIP; data -CR[IIP]; IC:mov-to-CR-IIP; rfi; implied -CR[IIPA]; IC:mov-to-CR-IIPA; IC:mov-from-CR-IIPA; data -CR[IPSR]; IC:mov-to-CR-IPSR; IC:mov-from-CR-IPSR; data -CR[IPSR]; IC:mov-to-CR-IPSR; rfi; implied -CR[IRR%], % in 0 - 3; IC:mov-from-CR-IVR; IC:mov-from-CR-IRR+1; data -CR[ISR]; IC:mov-to-CR-ISR; IC:mov-from-CR-ISR; data -CR[ITIR]; IC:mov-to-CR-ITIR; IC:mov-from-CR-ITIR; data -CR[ITIR]; IC:mov-to-CR-ITIR; itc.i, itc.d, itr.i, itr.d; implied -CR[ITM]; IC:mov-to-CR-ITM; IC:mov-from-CR-ITM; data -CR[ITV]; IC:mov-to-CR-ITV; IC:mov-from-CR-ITV; data -CR[IVA]; IC:mov-to-CR-IVA; IC:mov-from-CR-IVA; instr -CR[IVR]; IC:none; IC:mov-from-CR-IVR; SC Section 5.8.3.2, "External Interr= upt Vector Register (IVR - CR65)" on page 2:118 -CR[LID]; IC:mov-to-CR-LID; IC:mov-from-CR-LID; SC Section 5.8.3.1, "Local = ID (LID - CR64)" on page 2:117 -CR[LRR%], % in 0 - 1; IC:mov-to-CR-LRR+1; IC:mov-from-CR-LRR+1; data -CR[PMV]; IC:mov-to-CR-PMV; IC:mov-from-CR-PMV; data -CR[PTA]; IC:mov-to-CR-PTA; IC:mov-from-CR-PTA, IC:mem-readers, IC:mem-writ= ers, IC:non-access, thash; data -CR[TPR]; IC:mov-to-CR-TPR; IC:mov-from-CR-TPR, IC:mov-from-CR-IVR; data -CR[TPR]; IC:mov-to-CR-TPR; IC:mov-to-PSR-l+17, ssm+17; SC Section 5.8.3.3,= "Task Priority Register (TPR - CR66)" on page 2:119 -CR[TPR]; IC:mov-to-CR-TPR; rfi; implied -CR%, % in 3-7, 10-15, 18, 28-63, 75-79, 82-127; IC:none; IC:mov-from-CR-rv= +1; none -DAHR%, % in 0-7; br.call, brl.call, br.ret, IC:mov-to-DAHR; br.call, IC:me= m-readers, IC:mem-writers, IC:mov-from-DAHR; implied -DBR#; IC:mov-to-IND-DBR+3; IC:mov-from-IND-DBR+3; impliedF -DBR#; IC:mov-to-IND-DBR+3; IC:probe-all, IC:lfetch-all, IC:mem-readers, IC= :mem-writers; data -DTC; ptc.e, ptc.g, ptc.ga, ptc.l, ptr.i, ptr.d, itc.i, itc.d, itr.i, itr.d= ; IC:mem-readers, IC:mem-writers, IC:non-access; data -DTC; itc.i, itc.d, itr.i, itr.d; ptc.e, ptc.g, ptc.ga, ptc.l, ptr.i, ptr.d= , itc.i, itc.d, itr.i, itr.d; impliedF -DTC; ptc.e, ptc.g, ptc.ga, ptc.l, ptr.i, ptr.d; ptc.e, ptc.g, ptc.ga, ptc.= l, ptr.i, ptr.d; none -DTC; ptc.e, ptc.g, ptc.ga, ptc.l, ptr.i, ptr.d; itc.i, itc.d, itr.i, itr.d= ; impliedF -DTC_LIMIT*; ptc.g, ptc.ga; ptc.g, ptc.ga; impliedF -DTR; itr.d; IC:mem-readers, IC:mem-writers, IC:non-access; data -DTR; itr.d; ptc.g, ptc.ga, ptc.l, ptr.d, itr.d; impliedF -DTR; ptr.d; IC:mem-readers, IC:mem-writers, IC:non-access; data -DTR; ptr.d; ptc.g, ptc.ga, ptc.l, ptr.d; none -DTR; ptr.d; itr.d, itc.d; impliedF -FR%, % in 0 - 1; IC:none; IC:fr-readers+1; none -FR%, % in 2 - 127; IC:fr-writers+1\IC:ldf-c+1\IC:ldfp-c+1; IC:fr-readers+1= ; impliedF -FR%, % in 2 - 127; IC:ldf-c+1, IC:ldfp-c+1; IC:fr-readers+1; none -GR0; IC:none; IC:gr-readers+1; none -GR%, % in 1 - 127; IC:ld-c+1+13; IC:gr-readers+1; none -GR%, % in 1 - 127; IC:gr-writers+1\IC:ld-c+1+13; IC:gr-readers+1; impliedF -IBR#; IC:mov-to-IND-IBR+3; IC:mov-from-IND-IBR+3; impliedF -InService*; IC:mov-to-CR-EOI; IC:mov-from-CR-IVR; data -InService*; IC:mov-from-CR-IVR; IC:mov-from-CR-IVR; impliedF -InService*; IC:mov-to-CR-EOI; IC:mov-to-CR-EOI; impliedF -IP; IC:all; IC:all; none -ITC; ptc.e, ptc.g, ptc.ga, ptc.l, ptr.i, ptr.d; epc, vmsw; instr -ITC; ptc.e, ptc.g, ptc.ga, ptc.l, ptr.i, ptr.d; itc.i, itc.d, itr.i, itr.d= ; impliedF -ITC; ptc.e, ptc.g, ptc.ga, ptc.l, ptr.i, ptr.d; ptr.i, ptr.d, ptc.e, ptc.g= , ptc.ga, ptc.l; none -ITC; itc.i, itc.d, itr.i, itr.d; epc, vmsw; instr -ITC; itc.i, itc.d, itr.i, itr.d; itc.d, itc.i, itr.d, itr.i, ptr.d, ptr.i,= ptc.g, ptc.ga, ptc.l; impliedF -ITC_LIMIT*; ptc.g, ptc.ga; ptc.g, ptc.ga; impliedF -ITR; itr.i; itr.i, itc.i, ptc.g, ptc.ga, ptc.l, ptr.i; impliedF -ITR; itr.i; epc, vmsw; instr -ITR; ptr.i; itc.i, itr.i; impliedF -ITR; ptr.i; ptc.g, ptc.ga, ptc.l, ptr.i; none -ITR; ptr.i; epc, vmsw; instr -memory; IC:mem-writers; IC:mem-readers; none -MSR#; IC:mov-to-IND-MSR+5; IC:mov-from-IND-MSR+5; specific -PKR#; IC:mov-to-IND-PKR+3; IC:mem-readers, IC:mem-writers, IC:mov-from-IND= -PKR+4, IC:probe-all; data -PKR#; IC:mov-to-IND-PKR+3; IC:mov-to-IND-PKR+4; none -PKR#; IC:mov-to-IND-PKR+3; IC:mov-from-IND-PKR+3; impliedF -PKR#; IC:mov-to-IND-PKR+3; IC:mov-to-IND-PKR+3; impliedF -PMC#; IC:mov-to-IND-PMC+3; IC:mov-from-IND-PMC+3; impliedF -PMC#; IC:mov-to-IND-PMC+3; IC:mov-from-IND-PMD+3; SC Section 7.2.1, "Gener= ic Performance Counter Registers" for PMC[0].fr on page 2:150 -PMD#; IC:mov-to-IND-PMD+3; IC:mov-from-IND-PMD+3; impliedF -PR0; IC:pr-writers+1; IC:pr-readers-br+1, IC:pr-readers-nobr-nomovpr+1, IC= :mov-from-PR+12, IC:mov-to-PR+12; none -PR%, % in 1 - 15; IC:pr-writers+1, IC:mov-to-PR-allreg+7; IC:pr-readers-no= br-nomovpr+1, IC:mov-from-PR, IC:mov-to-PR+12; impliedF -PR%, % in 1 - 15; IC:pr-writers-fp+1; IC:pr-readers-br+1; impliedF -PR%, % in 1 - 15; IC:pr-writers-int+1, IC:mov-to-PR-allreg+7; IC:pr-reader= s-br+1; none -PR%, % in 16 - 62; IC:pr-writers+1, IC:mov-to-PR-allreg+7, IC:mov-to-PR-ro= treg; IC:pr-readers-nobr-nomovpr+1, IC:mov-from-PR, IC:mov-to-PR+12; implie= dF -PR%, % in 16 - 62; IC:pr-writers-fp+1; IC:pr-readers-br+1; impliedF -PR%, % in 16 - 62; IC:pr-writers-int+1, IC:mov-to-PR-allreg+7, IC:mov-to-P= R-rotreg; IC:pr-readers-br+1; none -PR63; IC:mod-sched-brs, IC:pr-writers+1, IC:mov-to-PR-allreg+7, IC:mov-to-= PR-rotreg; IC:pr-readers-nobr-nomovpr+1, IC:mov-from-PR, IC:mov-to-PR+12; i= mpliedF -PR63; IC:pr-writers-fp+1, IC:mod-sched-brs; IC:pr-readers-br+1; impliedF -PR63; IC:pr-writers-int+1, IC:mov-to-PR-allreg+7, IC:mov-to-PR-rotreg; IC:= pr-readers-br+1; none -PSR.ac; IC:user-mask-writers-partial+7, IC:mov-to-PSR-um; IC:mem-readers, = IC:mem-writers; implied -PSR.ac; IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l; IC:mem-readers, IC= :mem-writers; data -PSR.ac; IC:user-mask-writers-partial+7, IC:mov-to-PSR-um, IC:sys-mask-writ= ers-partial+7, IC:mov-to-PSR-l; IC:mov-from-PSR, IC:mov-from-PSR-um; implie= dF -PSR.ac; rfi; IC:mem-readers, IC:mem-writers, IC:mov-from-PSR, IC:mov-from-= PSR-um; impliedF -PSR.be; IC:user-mask-writers-partial+7, IC:mov-to-PSR-um; IC:mem-readers, = IC:mem-writers; implied -PSR.be; IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l; IC:mem-readers, IC= :mem-writers; data -PSR.be; IC:user-mask-writers-partial+7, IC:mov-to-PSR-um, IC:sys-mask-writ= ers-partial+7, IC:mov-to-PSR-l; IC:mov-from-PSR, IC:mov-from-PSR-um; implie= dF -PSR.be; rfi; IC:mem-readers, IC:mem-writers, IC:mov-from-PSR, IC:mov-from-= PSR-um; impliedF -PSR.bn; bsw, rfi; IC:gr-readers+10, IC:gr-writers+10; impliedF -PSR.cpl; epc, br.ret; IC:priv-ops, br.call, brl.call, epc, IC:mov-from-AR-= ITC, IC:mov-from-AR-RUC, IC:mov-to-AR-ITC, IC:mov-to-AR-RSC, IC:mov-to-AR-R= UC, IC:mov-to-AR-K, IC:mov-from-IND-PMD, IC:probe-all, IC:mem-readers, IC:m= em-writers, IC:lfetch-all; implied -PSR.cpl; rfi; IC:priv-ops, br.call, brl.call, epc, IC:mov-from-AR-ITC, IC:= mov-from-AR-RUC, IC:mov-to-AR-ITC, IC:mov-to-AR-RSC, IC:mov-to-AR-RUC, IC:m= ov-to-AR-K, IC:mov-from-IND-PMD, IC:probe-all, IC:mem-readers, IC:mem-write= rs, IC:lfetch-all; impliedF -PSR.da; rfi; IC:mem-readers, IC:lfetch-all, IC:mem-writers, IC:probe-fault= ; impliedF -PSR.db; IC:mov-to-PSR-l; IC:lfetch-all, IC:mem-readers, IC:mem-writers, IC= :probe-fault; data -PSR.db; IC:mov-to-PSR-l; IC:mov-from-PSR; impliedF -PSR.db; rfi; IC:lfetch-all, IC:mem-readers, IC:mem-writers, IC:mov-from-PS= R, IC:probe-fault; impliedF -PSR.dd; rfi; IC:lfetch-all, IC:mem-readers, IC:probe-fault, IC:mem-writers= ; impliedF -PSR.dfh; IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l; IC:fr-readers+8, = IC:fr-writers+8; data -PSR.dfh; IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l; IC:mov-from-PSR; = impliedF -PSR.dfh; rfi; IC:fr-readers+8, IC:fr-writers+8, IC:mov-from-PSR; impliedF -PSR.dfl; IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l; IC:fr-writers+8, = IC:fr-readers+8; data -PSR.dfl; IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l; IC:mov-from-PSR; = impliedF -PSR.dfl; rfi; IC:fr-writers+8, IC:fr-readers+8, IC:mov-from-PSR; impliedF -PSR.di; IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l; br.ia; data -PSR.di; IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l; IC:mov-from-PSR; i= mpliedF -PSR.di; rfi; br.ia, IC:mov-from-PSR; impliedF -PSR.dt; IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l; IC:mem-readers, IC= :mem-writers, IC:non-access; data -PSR.dt; IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l; IC:mov-from-PSR; i= mpliedF -PSR.dt; rfi; IC:mem-readers, IC:mem-writers, IC:non-access, IC:mov-from-PS= R; impliedF -PSR.ed; rfi; IC:lfetch-all, IC:mem-readers-spec; impliedF -PSR.i; IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; IC:mov-from-PS= R; impliedF -PSR.ia; rfi; IC:all; none -PSR.ic; IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l; IC:mov-from-PSR; i= mpliedF -PSR.ic; IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l; cover, itc.i, itc.= d, itr.i, itr.d, IC:mov-from-interruption-CR, IC:mov-to-interruption-CR; da= ta -PSR.ic; rfi; IC:mov-from-PSR, cover, itc.i, itc.d, itr.i, itr.d, IC:mov-fr= om-interruption-CR, IC:mov-to-interruption-CR; impliedF -PSR.id; rfi; IC:all; none -PSR.is; br.ia, rfi; IC:none; none -PSR.it; rfi; IC:branches, IC:mov-from-PSR, chk, epc, fchkf, vmsw; impliedF -PSR.lp; IC:mov-to-PSR-l; IC:mov-from-PSR; impliedF -PSR.lp; IC:mov-to-PSR-l; br.ret; data -PSR.lp; rfi; IC:mov-from-PSR, br.ret; impliedF -PSR.mc; rfi; IC:mov-from-PSR; impliedF -PSR.mfh; IC:fr-writers+9, IC:user-mask-writers-partial+7, IC:mov-to-PSR-um= , IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; IC:mov-from-PSR-um, = IC:mov-from-PSR; impliedF -PSR.mfl; IC:fr-writers+9, IC:user-mask-writers-partial+7, IC:mov-to-PSR-um= , IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; IC:mov-from-PSR-um, = IC:mov-from-PSR; impliedF -PSR.pk; IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l; IC:lfetch-all, IC:= mem-readers, IC:mem-writers, IC:probe-all; data -PSR.pk; IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l; IC:mov-from-PSR; i= mpliedF -PSR.pk; rfi; IC:lfetch-all, IC:mem-readers, IC:mem-writers, IC:mov-from-PS= R, IC:probe-all; impliedF -PSR.pp; IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; IC:mov-from-P= SR; impliedF -PSR.ri; rfi; IC:all; none -PSR.rt; IC:mov-to-PSR-l; IC:mov-from-PSR; impliedF -PSR.rt; IC:mov-to-PSR-l; alloc, flushrs, loadrs; data -PSR.rt; rfi; IC:mov-from-PSR, alloc, flushrs, loadrs; impliedF -PSR.si; IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l; IC:mov-from-PSR; i= mpliedF -PSR.si; IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l; IC:mov-from-AR-ITC= , IC:mov-from-AR-RUC; data -PSR.si; rfi; IC:mov-from-AR-ITC, IC:mov-from-AR-RUC, IC:mov-from-PSR; impl= iedF -PSR.sp; IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l; IC:mov-from-PSR; i= mpliedF -PSR.sp; IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l; IC:mov-from-IND-PM= D, IC:mov-to-PSR-um, rum, sum; data -PSR.sp; rfi; IC:mov-from-IND-PMD, IC:mov-from-PSR, IC:mov-to-PSR-um, rum, = sum; impliedF -PSR.ss; rfi; IC:all; impliedF -PSR.tb; IC:mov-to-PSR-l; IC:branches, chk, fchkf; data -PSR.tb; IC:mov-to-PSR-l; IC:mov-from-PSR; impliedF -PSR.tb; rfi; IC:branches, chk, fchkf, IC:mov-from-PSR; impliedF -PSR.up; IC:user-mask-writers-partial+7, IC:mov-to-PSR-um, IC:sys-mask-writ= ers-partial+7, IC:mov-to-PSR-l, rfi; IC:mov-from-PSR-um, IC:mov-from-PSR; i= mpliedF -PSR.vm; vmsw; IC:mem-readers, IC:mem-writers, IC:mov-from-AR-ITC, IC:mov-f= rom-AR-RUC, IC:mov-from-IND-CPUID, IC:mov-to-AR-ITC, IC:priv-ops\vmsw, cove= r, thash, ttag; implied -PSR.vm; rfi; IC:mem-readers, IC:mem-writers, IC:mov-from-AR-ITC, IC:mov-fr= om-AR-RUC, IC:mov-from-IND-CPUID, IC:mov-to-AR-ITC, IC:priv-ops\vmsw, cover= , thash, ttag; impliedF -RR#; IC:mov-to-IND-RR+6; IC:mem-readers, IC:mem-writers, itc.i, itc.d, itr= .i, itr.d, IC:non-access, ptc.g, ptc.ga, ptc.l, ptr.i, ptr.d, thash, ttag; = data -RR#; IC:mov-to-IND-RR+6; IC:mov-from-IND-RR+6; impliedF -RSE; IC:rse-writers+14; IC:rse-readers+14; impliedF diff --git a/opcodes/ia64-war.tbl b/opcodes/ia64-war.tbl deleted file mode 100644 index 8cdfac5b485..00000000000 --- a/opcodes/ia64-war.tbl +++ /dev/null @@ -1,2 +0,0 @@ -Resource Name; Readers; Writers; Semantics of Dependency -PR63; IC:pr-readers-br+1; IC:mod-sched-brs; stop diff --git a/opcodes/ia64-waw.tbl b/opcodes/ia64-waw.tbl deleted file mode 100644 index 6fe9a843506..00000000000 --- a/opcodes/ia64-waw.tbl +++ /dev/null @@ -1,140 +0,0 @@ -Resource Name; Writers; Writers; Semantics of Dependency -ALAT; IC:mem-readers-alat, IC:mem-writers, chk.a.clr, IC:invala-all; IC:me= m-readers-alat, IC:mem-writers, chk.a.clr, IC:invala-all; none -AR[BSP]; br.call, brl.call, br.ret, cover, IC:mov-to-AR-BSPSTORE, rfi; br.= call, brl.call, br.ret, cover, IC:mov-to-AR-BSPSTORE, rfi; impliedF -AR[BSPSTORE]; alloc, loadrs, flushrs, IC:mov-to-AR-BSPSTORE; alloc, loadrs= , flushrs, IC:mov-to-AR-BSPSTORE; impliedF -AR[CCV]; IC:mov-to-AR-CCV; IC:mov-to-AR-CCV; impliedF -AR[CFLG]; IC:mov-to-AR-CFLG; IC:mov-to-AR-CFLG; impliedF -AR[CSD]; ld16, IC:mov-to-AR-CSD; ld16, IC:mov-to-AR-CSD; impliedF -AR[EC]; br.ret, IC:mod-sched-brs, IC:mov-to-AR-EC; br.ret, IC:mod-sched-br= s, IC:mov-to-AR-EC; impliedF -AR[EFLAG]; IC:mov-to-AR-EFLAG; IC:mov-to-AR-EFLAG; impliedF -AR[FCR]; IC:mov-to-AR-FCR; IC:mov-to-AR-FCR; impliedF -AR[FDR]; IC:mov-to-AR-FDR; IC:mov-to-AR-FDR; impliedF -AR[FIR]; IC:mov-to-AR-FIR; IC:mov-to-AR-FIR; impliedF -AR[FPSR].sf0.controls; IC:mov-to-AR-FPSR, fsetc.s0; IC:mov-to-AR-FPSR, fse= tc.s0; impliedF -AR[FPSR].sf1.controls; IC:mov-to-AR-FPSR, fsetc.s1; IC:mov-to-AR-FPSR, fse= tc.s1; impliedF -AR[FPSR].sf2.controls; IC:mov-to-AR-FPSR, fsetc.s2; IC:mov-to-AR-FPSR, fse= tc.s2; impliedF -AR[FPSR].sf3.controls; IC:mov-to-AR-FPSR, fsetc.s3; IC:mov-to-AR-FPSR, fse= tc.s3; impliedF -AR[FPSR].sf0.flags; IC:fp-arith-s0, IC:fcmp-s0, IC:fpcmp-s0; IC:fp-arith-s= 0, IC:fcmp-s0, IC:fpcmp-s0; none -AR[FPSR].sf0.flags; fclrf.s0, IC:fcmp-s0, IC:fp-arith-s0, IC:fpcmp-s0, IC:= mov-to-AR-FPSR; fclrf.s0, IC:mov-to-AR-FPSR; impliedF -AR[FPSR].sf1.flags; IC:fp-arith-s1, IC:fcmp-s1, IC:fpcmp-s1; IC:fp-arith-s= 1, IC:fcmp-s1, IC:fpcmp-s1; none -AR[FPSR].sf1.flags; fclrf.s1, IC:fcmp-s1, IC:fp-arith-s1, IC:fpcmp-s1, IC:= mov-to-AR-FPSR; fclrf.s1, IC:mov-to-AR-FPSR; impliedF -AR[FPSR].sf2.flags; IC:fp-arith-s2, IC:fcmp-s2, IC:fpcmp-s2; IC:fp-arith-s= 2, IC:fcmp-s2, IC:fpcmp-s2; none -AR[FPSR].sf2.flags; fclrf.s2, IC:fcmp-s2, IC:fp-arith-s2, IC:fpcmp-s2, IC:= mov-to-AR-FPSR; fclrf.s2, IC:mov-to-AR-FPSR; impliedF -AR[FPSR].sf3.flags; IC:fp-arith-s3, IC:fcmp-s3, IC:fpcmp-s3; IC:fp-arith-s= 3, IC:fcmp-s3, IC:fpcmp-s3; none -AR[FPSR].sf3.flags; fclrf.s3, IC:fcmp-s3, IC:fp-arith-s3, IC:fpcmp-s3, IC:= mov-to-AR-FPSR; fclrf.s3, IC:mov-to-AR-FPSR; impliedF -AR[FPSR].rv; IC:mov-to-AR-FPSR; IC:mov-to-AR-FPSR; impliedF -AR[FPSR].traps; IC:mov-to-AR-FPSR; IC:mov-to-AR-FPSR; impliedF -AR[FSR]; IC:mov-to-AR-FSR; IC:mov-to-AR-FSR; impliedF -AR[ITC]; IC:mov-to-AR-ITC; IC:mov-to-AR-ITC; impliedF -AR[K%], % in 0 - 7; IC:mov-to-AR-K+1; IC:mov-to-AR-K+1; impliedF -AR[LC]; IC:mod-sched-brs-counted, IC:mov-to-AR-LC; IC:mod-sched-brs-counte= d, IC:mov-to-AR-LC; impliedF -AR[PFS]; br.call, brl.call; br.call, brl.call; none -AR[PFS]; br.call, brl.call; IC:mov-to-AR-PFS; impliedF -AR[RNAT]; alloc, flushrs, loadrs, IC:mov-to-AR-RNAT, IC:mov-to-AR-BSPSTORE= ; alloc, flushrs, loadrs, IC:mov-to-AR-RNAT, IC:mov-to-AR-BSPSTORE; impliedF -AR[RSC]; IC:mov-to-AR-RSC; IC:mov-to-AR-RSC; impliedF -AR[RUC]; IC:mov-to-AR-RUC; IC:mov-to-AR-RUC; impliedF -AR[SSD]; IC:mov-to-AR-SSD; IC:mov-to-AR-SSD; impliedF -AR[UNAT]{%}, % in 0 - 63; IC:mov-to-AR-UNAT, st8.spill; IC:mov-to-AR-UNAT,= st8.spill; impliedF -AR%, % in 8-15, 20, 22-23, 31, 33-35, 37-39, 41-43, 46-47, 67-111; IC:none= ; IC:none; none -AR%, % in 48 - 63, 112-127; IC:mov-to-AR-ig+1; IC:mov-to-AR-ig+1; impliedF -BR%, % in 0 - 7; br.call+1, brl.call+1; IC:mov-to-BR+1; impliedF -BR%, % in 0 - 7; IC:mov-to-BR+1; IC:mov-to-BR+1; impliedF -BR%, % in 0 - 7; br.call+1, brl.call+1; br.call+1, brl.call+1; none -CFM; IC:mod-sched-brs, br.call, brl.call, br.ret, alloc, clrrrb, cover, rf= i; IC:mod-sched-brs, br.call, brl.call, br.ret, alloc, clrrrb, cover, rfi; = impliedF -CPUID#; IC:none; IC:none; none -CR[CMCV]; IC:mov-to-CR-CMCV; IC:mov-to-CR-CMCV; impliedF -CR[DCR]; IC:mov-to-CR-DCR; IC:mov-to-CR-DCR; impliedF -CR[EOI]; IC:mov-to-CR-EOI; IC:mov-to-CR-EOI; SC Section 5.8.3.4, "End of E= xternal Interrupt Register (EOI - CR67)" on page 2:119 -CR[GPTA]; IC:mov-to-CR-GPTA; IC:mov-to-CR-GPTA; impliedF -CR[IFA]; IC:mov-to-CR-IFA; IC:mov-to-CR-IFA; impliedF -CR[IFS]; IC:mov-to-CR-IFS, cover; IC:mov-to-CR-IFS, cover; impliedF -CR[IHA]; IC:mov-to-CR-IHA; IC:mov-to-CR-IHA; impliedF -CR[IIB%], % in 0 - 1; IC:mov-to-CR-IIB; IC:mov-to-CR-IIB; impliedF -CR[IIM]; IC:mov-to-CR-IIM; IC:mov-to-CR-IIM; impliedF -CR[IIP]; IC:mov-to-CR-IIP; IC:mov-to-CR-IIP; impliedF -CR[IIPA]; IC:mov-to-CR-IIPA; IC:mov-to-CR-IIPA; impliedF -CR[IPSR]; IC:mov-to-CR-IPSR; IC:mov-to-CR-IPSR; impliedF -CR[IRR%], % in 0 - 3; IC:mov-from-CR-IVR; IC:mov-from-CR-IVR; impliedF -CR[ISR]; IC:mov-to-CR-ISR; IC:mov-to-CR-ISR; impliedF -CR[ITIR]; IC:mov-to-CR-ITIR; IC:mov-to-CR-ITIR; impliedF -CR[ITM]; IC:mov-to-CR-ITM; IC:mov-to-CR-ITM; impliedF -CR[ITV]; IC:mov-to-CR-ITV; IC:mov-to-CR-ITV; impliedF -CR[IVA]; IC:mov-to-CR-IVA; IC:mov-to-CR-IVA; impliedF -CR[IVR]; IC:none; IC:none; SC -CR[LID]; IC:mov-to-CR-LID; IC:mov-to-CR-LID; SC -CR[LRR%], % in 0 - 1; IC:mov-to-CR-LRR+1; IC:mov-to-CR-LRR+1; impliedF -CR[PMV]; IC:mov-to-CR-PMV; IC:mov-to-CR-PMV; impliedF -CR[PTA]; IC:mov-to-CR-PTA; IC:mov-to-CR-PTA; impliedF -CR[TPR]; IC:mov-to-CR-TPR; IC:mov-to-CR-TPR; impliedF -CR%, % in 3-7, 10-15, 18, 28-63, 75-79, 82-127; IC:none; IC:none; none -DAHR%, % in 0-7; IC:br.call, brl.call, br.ret, IC:mov-to-AR-BSPSTORE, IC:m= ov-to-DAHR, rfi; IC:br.call, brl.call, br.ret, IC:mov-to-AR-BSPSTORE, IC:mo= v-to-DAHR, rfi; implied -DBR#; IC:mov-to-IND-DBR+3; IC:mov-to-IND-DBR+3; impliedF -DTC; ptc.e, ptc.g, ptc.ga, ptc.l, ptr.i, ptr.d; ptc.e, ptc.g, ptc.ga, ptc.= l, ptr.i, ptr.d; none -DTC; ptc.e, ptc.g, ptc.ga, ptc.l, ptr.i, ptr.d, itc.i, itc.d, itr.i, itr.d= ; itc.i, itc.d, itr.i, itr.d; impliedF -DTC_LIMIT*; ptc.g, ptc.ga; ptc.g, ptc.ga; impliedF -DTR; itr.d; itr.d; impliedF -DTR; itr.d; ptr.d; impliedF -DTR; ptr.d; ptr.d; none -FR%, % in 0 - 1; IC:none; IC:none; none -FR%, % in 2 - 127; IC:fr-writers+1, IC:ldf-c+1, IC:ldfp-c+1; IC:fr-writers= +1, IC:ldf-c+1, IC:ldfp-c+1; impliedF -GR0; IC:none; IC:none; none -GR%, % in 1 - 127; IC:ld-c+1, IC:gr-writers+1; IC:ld-c+1, IC:gr-writers+1;= impliedF -IBR#; IC:mov-to-IND-IBR+3; IC:mov-to-IND-IBR+3; impliedF -InService*; IC:mov-to-CR-EOI, IC:mov-from-CR-IVR; IC:mov-to-CR-EOI, IC:mov= -from-CR-IVR; SC -IP; IC:all; IC:all; none -ITC; ptc.e, ptc.g, ptc.ga, ptc.l, ptr.i, ptr.d; ptc.e, ptc.g, ptc.ga, ptc.= l, ptr.i, ptr.d; none -ITC; ptc.e, ptc.g, ptc.ga, ptc.l, ptr.i, ptr.d, itc.i, itc.d, itr.i, itr.d= ; itc.i, itc.d, itr.i, itr.d; impliedF -ITR; itr.i; itr.i, ptr.i; impliedF -ITR; ptr.i; ptr.i; none -memory; IC:mem-writers; IC:mem-writers; none -MSR#; IC:mov-to-IND-MSR+5; IC:mov-to-IND-MSR+5; SC -PKR#; IC:mov-to-IND-PKR+3; IC:mov-to-IND-PKR+4; none -PKR#; IC:mov-to-IND-PKR+3; IC:mov-to-IND-PKR+3; impliedF -PMC#; IC:mov-to-IND-PMC+3; IC:mov-to-IND-PMC+3; impliedF -PMD#; IC:mov-to-IND-PMD+3; IC:mov-to-IND-PMD+3; impliedF -PR0; IC:pr-writers+1; IC:pr-writers+1; none -PR%, % in 1 - 15; IC:pr-and-writers+1; IC:pr-and-writers+1; none -PR%, % in 1 - 15; IC:pr-or-writers+1; IC:pr-or-writers+1; none -PR%, % in 1 - 15; IC:pr-unc-writers-fp+1, IC:pr-unc-writers-int+1, IC:pr-n= orm-writers-fp+1, IC:pr-norm-writers-int+1, IC:pr-and-writers+1, IC:mov-to-= PR-allreg+7; IC:pr-unc-writers-fp+1, IC:pr-unc-writers-int+1, IC:pr-norm-wr= iters-fp+1, IC:pr-norm-writers-int+1, IC:pr-or-writers+1, IC:mov-to-PR-allr= eg+7; impliedF -PR%, % in 16 - 62; IC:pr-and-writers+1; IC:pr-and-writers+1; none -PR%, % in 16 - 62; IC:pr-or-writers+1; IC:pr-or-writers+1; none -PR%, % in 16 - 62; IC:pr-unc-writers-fp+1, IC:pr-unc-writers-int+1, IC:pr-= norm-writers-fp+1, IC:pr-norm-writers-int+1, IC:pr-and-writers+1, IC:mov-to= -PR-allreg+7, IC:mov-to-PR-rotreg; IC:pr-unc-writers-fp+1, IC:pr-unc-writer= s-int+1, IC:pr-norm-writers-fp+1, IC:pr-norm-writers-int+1, IC:pr-or-writer= s+1, IC:mov-to-PR-allreg+7, IC:mov-to-PR-rotreg; impliedF -PR63; IC:pr-and-writers+1; IC:pr-and-writers+1; none -PR63; IC:pr-or-writers+1; IC:pr-or-writers+1; none -PR63; IC:mod-sched-brs, IC:pr-unc-writers-fp+1, IC:pr-unc-writers-int+1, I= C:pr-norm-writers-fp+1, IC:pr-norm-writers-int+1, IC:pr-and-writers+1, IC:m= ov-to-PR-allreg+7, IC:mov-to-PR-rotreg; IC:mod-sched-brs, IC:pr-unc-writers= -fp+1, IC:pr-unc-writers-int+1, IC:pr-norm-writers-fp+1, IC:pr-norm-writers= -int+1, IC:pr-or-writers+1, IC:mov-to-PR-allreg+7, IC:mov-to-PR-rotreg; imp= liedF -PSR.ac; IC:user-mask-writers-partial+7, IC:mov-to-PSR-um, IC:sys-mask-writ= ers-partial+7, IC:mov-to-PSR-l, rfi; IC:user-mask-writers-partial+7, IC:mov= -to-PSR-um, IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; impliedF -PSR.be; IC:user-mask-writers-partial+7, IC:mov-to-PSR-um, IC:sys-mask-writ= ers-partial+7, IC:mov-to-PSR-l, rfi; IC:user-mask-writers-partial+7, IC:mov= -to-PSR-um, IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; impliedF -PSR.bn; bsw, rfi; bsw, rfi; impliedF -PSR.cpl; epc, br.ret, rfi; epc, br.ret, rfi; impliedF -PSR.da; rfi; rfi; impliedF -PSR.db; IC:mov-to-PSR-l, rfi; IC:mov-to-PSR-l, rfi; impliedF -PSR.dd; rfi; rfi; impliedF -PSR.dfh; IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; IC:sys-mask-= writers-partial+7, IC:mov-to-PSR-l, rfi; impliedF -PSR.dfl; IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; IC:sys-mask-= writers-partial+7, IC:mov-to-PSR-l, rfi; impliedF -PSR.di; IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; IC:sys-mask-w= riters-partial+7, IC:mov-to-PSR-l, rfi; impliedF -PSR.dt; IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; IC:sys-mask-w= riters-partial+7, IC:mov-to-PSR-l, rfi; impliedF -PSR.ed; rfi; rfi; impliedF -PSR.i; IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; IC:sys-mask-wr= iters-partial+7, IC:mov-to-PSR-l, rfi; impliedF -PSR.ia; rfi; rfi; impliedF -PSR.ic; IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; IC:sys-mask-w= riters-partial+7, IC:mov-to-PSR-l, rfi; impliedF -PSR.id; rfi; rfi; impliedF -PSR.is; br.ia, rfi; br.ia, rfi; impliedF -PSR.it; rfi; rfi; impliedF -PSR.lp; IC:mov-to-PSR-l, rfi; IC:mov-to-PSR-l, rfi; impliedF -PSR.mc; rfi; rfi; impliedF -PSR.mfh; IC:fr-writers+9; IC:fr-writers+9; none -PSR.mfh; IC:user-mask-writers-partial+7, IC:mov-to-PSR-um, IC:fr-writers+9= , IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; IC:user-mask-writers= -partial+7, IC:mov-to-PSR-um, IC:sys-mask-writers-partial+7, IC:mov-to-PSR-= l, rfi; impliedF -PSR.mfl; IC:fr-writers+9; IC:fr-writers+9; none -PSR.mfl; IC:user-mask-writers-partial+7, IC:mov-to-PSR-um, IC:fr-writers+9= , IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; IC:user-mask-writers= -partial+7, IC:mov-to-PSR-um, IC:sys-mask-writers-partial+7, IC:mov-to-PSR-= l, rfi; impliedF -PSR.pk; IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; IC:sys-mask-w= riters-partial+7, IC:mov-to-PSR-l, rfi; impliedF -PSR.pp; IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; IC:sys-mask-w= riters-partial+7, IC:mov-to-PSR-l, rfi; impliedF -PSR.ri; rfi; rfi; impliedF -PSR.rt; IC:mov-to-PSR-l, rfi; IC:mov-to-PSR-l, rfi; impliedF -PSR.si; IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; IC:sys-mask-w= riters-partial+7, IC:mov-to-PSR-l, rfi; impliedF -PSR.sp; IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; IC:sys-mask-w= riters-partial+7, IC:mov-to-PSR-l, rfi; impliedF -PSR.ss; rfi; rfi; impliedF -PSR.tb; IC:mov-to-PSR-l, rfi; IC:mov-to-PSR-l, rfi; impliedF -PSR.up; IC:user-mask-writers-partial+7, IC:mov-to-PSR-um, IC:sys-mask-writ= ers-partial+7, IC:mov-to-PSR-l, rfi; IC:user-mask-writers-partial+7, IC:mov= -to-PSR-um, IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; impliedF -PSR.vm; rfi, vmsw; rfi, vmsw; impliedF -RR#; IC:mov-to-IND-RR+6; IC:mov-to-IND-RR+6; impliedF -RSE; IC:rse-writers+14; IC:rse-writers+14; impliedF diff --git a/readline/readline/support/config.guess b/readline/readline/sup= port/config.guess index cc7a8107011..4ca47981424 100755 --- a/readline/readline/support/config.guess +++ b/readline/readline/support/config.guess @@ -593,14 +593,6 @@ EOF i*86:AIX:*:*) echo i386-ibm-aix exit ;; - ia64:AIX:*:*) - if test -x /usr/bin/oslevel ; then - IBM_REV=3D$(/usr/bin/oslevel) - else - IBM_REV=3D"$UNAME_VERSION.$UNAME_RELEASE" - fi - echo "$UNAME_MACHINE"-ibm-aix"$IBM_REV" - exit ;; *:AIX:2:3) if grep bos325 /usr/include/stdio.h >/dev/null 2>&1; then set_cc_for_build @@ -745,10 +737,6 @@ EOF fi echo "$HP_ARCH"-hp-hpux"$HPUX_REV" exit ;; - ia64:HP-UX:*:*) - HPUX_REV=3D$(echo "$UNAME_RELEASE"|sed -e 's/[^.]*.[0B]*//') - echo ia64-hp-hpux"$HPUX_REV" - exit ;; 3050*:HI-UX:*:*) set_cc_for_build sed 's/^ //' << EOF > "$dummy.c" @@ -908,9 +896,6 @@ EOF authenticamd | genuineintel | EM64T) echo x86_64-unknown-interix"$UNAME_RELEASE" exit ;; - IA64) - echo ia64-unknown-interix"$UNAME_RELEASE" - exit ;; esac ;; i*:UWIN*:*) echo "$UNAME_MACHINE"-pc-uwin @@ -993,9 +978,6 @@ EOF i*86:Linux:*:*) echo "$UNAME_MACHINE"-pc-linux-"$LIBC" exit ;; - ia64:Linux:*:*) - echo "$UNAME_MACHINE"-unknown-linux-"$LIBC" - exit ;; k1om:Linux:*:*) echo "$UNAME_MACHINE"-unknown-linux-"$LIBC" exit ;; @@ -1474,7 +1456,6 @@ EOF UNAME_MACHINE=3D$( (uname -p) 2>/dev/null) case "$UNAME_MACHINE" in A*) echo alpha-dec-vms ; exit ;; - I*) echo ia64-dec-vms ; exit ;; V*) echo vax-dec-vms ; exit ;; esac ;; *:XENIX:*:SysV) diff --git a/readline/readline/support/config.rpath b/readline/readline/sup= port/config.rpath index fc5913d7878..a7e1f457999 100755 --- a/readline/readline/support/config.rpath +++ b/readline/readline/support/config.rpath @@ -177,9 +177,7 @@ if test "$with_gnu_ld" =3D yes; then case "$host_os" in aix[3-9]*) # On AIX/PPC, the GNU linker is very broken - if test "$host_cpu" !=3D ia64; then - ld_shlibs=3Dno - fi + ld_shlibs=3Dno ;; amigaos*) case "$host_cpu" in @@ -273,11 +271,6 @@ else fi ;; aix[4-9]*) - if test "$host_cpu" =3D ia64; then - # On IA64, the linker does run time linking by default, so we don't - # have to do anything special. - aix_use_runtimelinking=3Dno - else aix_use_runtimelinking=3Dno # Test if we are trying to use run time linking or normal # AIX style linking. If -brtl is somewhere in LDFLAGS, we @@ -291,7 +284,6 @@ else done ;; esac - fi hardcode_direct=3Dyes hardcode_libdir_separator=3D':' if test "$GCC" =3D yes; then @@ -326,15 +318,7 @@ else fi rm -f conftest.c conftest # End _LT_AC_SYS_LIBPATH_AIX. - if test "$aix_use_runtimelinking" =3D yes; then - hardcode_libdir_flag_spec=3D'${wl}-blibpath:$libdir:'"$aix_libpath" - else - if test "$host_cpu" =3D ia64; then - hardcode_libdir_flag_spec=3D'${wl}-R $libdir:/usr/lib:/lib' - else - hardcode_libdir_flag_spec=3D'${wl}-blibpath:$libdir:'"$aix_libpa= th" - fi - fi + hardcode_libdir_flag_spec=3D'${wl}-blibpath:$libdir:'"$aix_libpath" ;; amigaos*) case "$host_cpu" in @@ -398,7 +382,7 @@ else hardcode_libdir_flag_spec=3D'${wl}+b ${wl}$libdir' hardcode_libdir_separator=3D: case $host_cpu in - hppa*64*|ia64*) + hppa*64*) hardcode_direct=3Dno ;; *) @@ -558,9 +542,6 @@ case "$host_os" in ;; hpux9* | hpux10* | hpux11*) case $host_cpu in - ia64*) - shrext=3D.so - ;; hppa*64*) shrext=3D.sl ;; diff --git a/readline/readline/support/config.sub b/readline/readline/suppo= rt/config.sub index 7384e9198b4..c5824c5c62c 100755 --- a/readline/readline/support/config.sub +++ b/readline/readline/support/config.sub @@ -1180,7 +1180,7 @@ case $cpu-$vendor in | h8300 | h8500 \ | hppa | hppa1.[01] | hppa2.0 | hppa2.0[nw] | hppa64 \ | hexagon \ - | i370 | i*86 | i860 | i960 | ia16 | ia64 \ + | i370 | i*86 | i860 | i960 \ | ip2k | iq2000 \ | k1om \ | le32 | le64 \ diff --git a/sim/configure b/sim/configure index 1ebef377973..356bd46ccbb 100755 --- a/sim/configure +++ b/sim/configure @@ -6746,10 +6746,6 @@ haiku*) hpux10.20* | hpux11*) lt_cv_file_magic_cmd=3D/usr/bin/file case $host_cpu in - ia64*) - lt_cv_deplibs_check_method=3D'file_magic (s[0-9][0-9][0-9]|ELF-[0-9][0= -9]) shared object file - IA64' - lt_cv_file_magic_test_file=3D/usr/lib/hpux32/libc.so - ;; hppa*64*) lt_cv_deplibs_check_method=3D'file_magic (s[0-9][0-9][0-9]|ELF[ -][0-9= ][0-9])(-bit)?( [LM]SB)? shared object( file)?[, -]* PA-RISC [0-9]\.[0-9]' lt_cv_file_magic_test_file=3D/usr/lib/pa20_64/libc.sl @@ -7350,11 +7346,6 @@ aix*) cygwin* | mingw* | pw32* | cegcc*) symcode=3D'[ABCDGISTW]' ;; -hpux*) - if test "$host_cpu" =3D ia64; then - symcode=3D'[ABCDEGRST]' - fi - ;; irix* | nonstopux*) symcode=3D'[BCDEGRST]' ;; @@ -7385,7 +7376,7 @@ case `$NM -V 2>&1` in esac =20 # Transform an extracted symbol line into a proper C declaration. -# Some systems (esp. on ia64) link data and code symbols differently, +# Some systems link data and code symbols differently, # so use this general approach. lt_cv_sys_global_symbol_to_cdecl=3D"sed -n -e 's/^T .* \(.*\)$/extern int = \1();/p' -e 's/^$symcode* .* \(.*\)$/extern char \1;/p'" =20 @@ -7585,25 +7576,6 @@ test "x$enable_libtool_lock" !=3D xno && enable_libt= ool_lock=3Dyes # Some flags need to be propagated to the compiler or linker for good # libtool support. case $host in -ia64-*-hpux*) - # Find out which ABI we are using. - echo 'int i;' > conftest.$ac_ext - if { { eval echo "\"\$as_me\":${as_lineno-$LINENO}: \"$ac_compile\""; } = >&5 - (eval $ac_compile) 2>&5 - ac_status=3D$? - $as_echo "$as_me:${as_lineno-$LINENO}: \$? =3D $ac_status" >&5 - test $ac_status =3D 0; }; then - case `/usr/bin/file conftest.$ac_objext` in - *ELF-32*) - HPUX_IA64_MODE=3D"32" - ;; - *ELF-64*) - HPUX_IA64_MODE=3D"64" - ;; - esac - fi - rm -rf conftest* - ;; *-*-irix6*) # Find out which ABI we are using. echo '#line '$LINENO' "configure"' > conftest.$ac_ext @@ -9927,10 +9899,6 @@ $as_echo_n "checking for $compiler option to produce= PIC... " >&6; } case $host_os in aix*) # All AIX code is PIC. - if test "$host_cpu" =3D ia64; then - # AIX 5 now supports IA64 processor - lt_prog_compiler_static=3D'-Bstatic' - fi lt_prog_compiler_pic=3D'-fPIC' ;; =20 @@ -10027,12 +9995,7 @@ $as_echo_n "checking for $compiler option to produc= e PIC... " >&6; } case $host_os in aix*) lt_prog_compiler_wl=3D'-Wl,' - if test "$host_cpu" =3D ia64; then - # AIX 5 now supports IA64 processor - lt_prog_compiler_static=3D'-Bstatic' - else - lt_prog_compiler_static=3D'-bnso -bI:/lib/syscalls.exp' - fi + lt_prog_compiler_static=3D'-bnso -bI:/lib/syscalls.exp' ;; =20 mingw* | cygwin* | pw32* | os2* | cegcc*) @@ -10046,7 +10009,7 @@ $as_echo_n "checking for $compiler option to produc= e PIC... " >&6; } # PIC is the default for IA64 HP-UX and 64-bit HP-UX, but # not for PA HP-UX. case $host_cpu in - hppa*64*|ia64*) + hppa*64*) # +Z the default ;; *) @@ -10571,7 +10534,6 @@ $as_echo_n "checking whether the $compiler linker (= $LD) supports shared librarie case $host_os in aix[3-9]*) # On AIX/PPC, the GNU linker is very broken - if test "$host_cpu" !=3D ia64; then ld_shlibs=3Dno cat <<_LT_EOF 1>&2 =20 @@ -10583,7 +10545,6 @@ $as_echo_n "checking whether the $compiler linker (= $LD) supports shared librarie *** You will then need to restart the configuration process. =20 _LT_EOF - fi ;; =20 amigaos*) @@ -10679,10 +10640,6 @@ _LT_EOF # Portland Group f77 and f90 compilers whole_archive_flag_spec=3D'${wl}--whole-archive`for conv in $convenienc= e\"\"; do test -n \"$conv\" && new_convenience=3D\"$new_convenience,$conv\= "; done; func_echo_all \"$new_convenience\"` ${wl}--no-whole-archive' tmp_addflag=3D' $pic_flag -Mnomain' ;; - ecc*,ia64* | icc*,ia64*) # Intel C compiler on ia64 - tmp_addflag=3D' -i_dynamic' ;; - efc*,ia64* | ifort*,ia64*) # Intel Fortran compiler on ia64 - tmp_addflag=3D' -i_dynamic -nofor_main' ;; ifc* | ifort*) # Intel Fortran compiler tmp_addflag=3D' -nofor_main' ;; lf95*) # Lahey Fortran 8.1 @@ -10836,13 +10793,6 @@ _LT_EOF ;; =20 aix[4-9]*) - if test "$host_cpu" =3D ia64; then - # On IA64, the linker does run time linking by default, so we don't - # have to do anything special. - aix_use_runtimelinking=3Dno - exp_sym_flag=3D'-Bexport' - no_entry_flag=3D"" - else # If we're using GNU nm, then we don't want the "-C" option. # -C means demangle to AIX nm, but means don't demangle with GNU nm # Also, AIX nm treats weak defined symbols like other global @@ -10869,7 +10819,6 @@ _LT_EOF =20 exp_sym_flag=3D'-bexport' no_entry_flag=3D'-bnoentry' - fi =20 # When large executables or shared objects are built, AIX ld can # have problems creating the table of contents. If linking a library @@ -10912,17 +10861,11 @@ _LT_EOF fi else # not using gcc - if test "$host_cpu" =3D ia64; then - # VisualAge C++, Version 5.5 for AIX 5L for IA-64, Beta 3 Release - # chokes on -Wl,-G. The following line is correct: - shared_flag=3D'-G' - else if test "$aix_use_runtimelinking" =3D yes; then shared_flag=3D'${wl}-G' else shared_flag=3D'${wl}-bM:SRE' fi - fi fi =20 export_dynamic_flag_spec=3D'${wl}-bexpall' @@ -10968,11 +10911,6 @@ if test -z "$aix_libpath"; then aix_libpath=3D"/us= r/lib:/lib"; fi hardcode_libdir_flag_spec=3D'${wl}-blibpath:$libdir:'"$aix_libpath" archive_expsym_cmds=3D'$CC -o $output_objdir/$soname $libobjs $dep= libs '"\${wl}$no_entry_flag"' $compiler_flags `if test "x${allow_undefined_= flag}" !=3D "x"; then func_echo_all "${wl}${allow_undefined_flag}"; else :;= fi` '"\${wl}$exp_sym_flag:\$export_symbols $shared_flag" else - if test "$host_cpu" =3D ia64; then - hardcode_libdir_flag_spec=3D'${wl}-R $libdir:/usr/lib:/lib' - allow_undefined_flag=3D"-z nodefs" - archive_expsym_cmds=3D"\$CC $shared_flag"' -o $output_objdir/$soname $l= ibobjs $deplibs '"\${wl}$no_entry_flag"' $compiler_flags ${wl}${allow_undef= ined_flag} '"\${wl}$exp_sym_flag:\$export_symbols" - else # Determine the default libpath from the value encoded in an # empty executable. cat confdefs.h - <<_ACEOF >conftest.$ac_ext @@ -11020,7 +10958,6 @@ if test -z "$aix_libpath"; then aix_libpath=3D"/usr= /lib:/lib"; fi archive_cmds_need_lc=3Dyes # This is similar to how AIX traditionally builds its shared libraries. archive_expsym_cmds=3D"\$CC $shared_flag"' -o $output_objdir/$soname $l= ibobjs $deplibs ${wl}-bnoentry $compiler_flags ${wl}-bE:$export_symbols${al= low_undefined_flag}~$AR $AR_FLAGS $output_objdir/$libname$release.a $output= _objdir/$soname' - fi fi ;; =20 @@ -11169,9 +11106,6 @@ if test -z "$aix_libpath"; then aix_libpath=3D"/usr= /lib:/lib"; fi hppa*64*) archive_cmds=3D'$CC -shared ${wl}+h ${wl}$soname ${wl}+nodefaultrpath -= o $lib $libobjs $deplibs $compiler_flags' ;; - ia64*) - archive_cmds=3D'$CC -shared -fPIC ${wl}+h ${wl}$soname ${wl}+nodefaultr= path -o $lib $libobjs $deplibs $compiler_flags' - ;; *) archive_cmds=3D'$CC -shared -fPIC ${wl}+h ${wl}$soname ${wl}+b ${wl}$in= stall_libdir -o $lib $libobjs $deplibs $compiler_flags' ;; @@ -11181,9 +11115,6 @@ if test -z "$aix_libpath"; then aix_libpath=3D"/usr= /lib:/lib"; fi hppa*64*) archive_cmds=3D'$CC -b ${wl}+h ${wl}$soname ${wl}+nodefaultrpath -o $li= b $libobjs $deplibs $compiler_flags' ;; - ia64*) - archive_cmds=3D'$CC -b ${wl}+h ${wl}$soname ${wl}+nodefaultrpath -o $li= b $libobjs $deplibs $compiler_flags' - ;; *) =20 # Older versions of the 11.00 compiler do not understand -b yet @@ -11233,7 +11164,7 @@ fi hardcode_libdir_separator=3D: =20 case $host_cpu in - hppa*64*|ia64*) + hppa*64*) hardcode_direct=3Dno hardcode_shlibpath_var=3Dno ;; @@ -11870,11 +11801,6 @@ aix[4-9]*) need_lib_prefix=3Dno need_version=3Dno hardcode_into_libs=3Dyes - if test "$host_cpu" =3D ia64; then - # AIX 5 supports IA64 - library_names_spec=3D'${libname}${release}${shared_ext}$major ${libnam= e}${release}${shared_ext}$versuffix $libname${shared_ext}' - shlibpath_var=3DLD_LIBRARY_PATH - else # With GCC up to 2.95.x, collect2 would create an import file # for dependence libraries. The import file would start with # the line `#! .'. This would cause the generated library to @@ -11906,7 +11832,6 @@ aix[4-9]*) soname_spec=3D'${libname}${release}${shared_ext}$major' fi shlibpath_var=3DLIBPATH - fi ;; =20 amigaos*) @@ -12083,21 +12008,6 @@ hpux9* | hpux10* | hpux11*) need_lib_prefix=3Dno need_version=3Dno case $host_cpu in - ia64*) - shrext_cmds=3D'.so' - hardcode_into_libs=3Dyes - dynamic_linker=3D"$host_os dld.so" - shlibpath_var=3DLD_LIBRARY_PATH - shlibpath_overrides_runpath=3Dyes # Unless +noenvvar is specified. - library_names_spec=3D'${libname}${release}${shared_ext}$versuffix ${li= bname}${release}${shared_ext}$major $libname${shared_ext}' - soname_spec=3D'${libname}${release}${shared_ext}$major' - if test "X$HPUX_IA64_MODE" =3D X32; then - sys_lib_search_path_spec=3D"/usr/lib/hpux32 /usr/local/lib/hpux32 /u= sr/local/lib" - else - sys_lib_search_path_spec=3D"/usr/lib/hpux64 /usr/local/lib/hpux64" - fi - sys_lib_dlsearch_path_spec=3D$sys_lib_search_path_spec - ;; hppa*64*) shrext_cmds=3D'.sl' hardcode_into_libs=3Dyes @@ -13188,7 +13098,7 @@ $as_echo_n "checking whether to build shared librar= ies... " >&6; } ;; =20 aix[4-9]*) - if test "$host_cpu" !=3D ia64 && test "$aix_use_runtimelinking" =3D no= ; then + if test "$aix_use_runtimelinking" =3D no ; then test "$enable_shared" =3D yes && enable_static=3Dno fi ;; diff --git a/zlib/configure b/zlib/configure index 0e8a28a09a8..84a7e48c884 100755 --- a/zlib/configure +++ b/zlib/configure @@ -5330,10 +5330,6 @@ haiku*) hpux10.20* | hpux11*) lt_cv_file_magic_cmd=3D/usr/bin/file case $host_cpu in - ia64*) - lt_cv_deplibs_check_method=3D'file_magic (s[0-9][0-9][0-9]|ELF-[0-9][0= -9]) shared object file - IA64' - lt_cv_file_magic_test_file=3D/usr/lib/hpux32/libc.so - ;; hppa*64*) lt_cv_deplibs_check_method=3D'file_magic (s[0-9][0-9][0-9]|ELF[ -][0-9= ][0-9])(-bit)?( [LM]SB)? shared object( file)?[, -]* PA-RISC [0-9]\.[0-9]' lt_cv_file_magic_test_file=3D/usr/lib/pa20_64/libc.sl @@ -5892,11 +5888,6 @@ aix*) cygwin* | mingw* | pw32* | cegcc*) symcode=3D'[ABCDGISTW]' ;; -hpux*) - if test "$host_cpu" =3D ia64; then - symcode=3D'[ABCDEGRST]' - fi - ;; irix* | nonstopux*) symcode=3D'[BCDEGRST]' ;; @@ -5927,7 +5918,7 @@ case `$NM -V 2>&1` in esac =20 # Transform an extracted symbol line into a proper C declaration. -# Some systems (esp. on ia64) link data and code symbols differently, +# Some systems link data and code symbols differently, # so use this general approach. lt_cv_sys_global_symbol_to_cdecl=3D"sed -n -e 's/^T .* \(.*\)$/extern int = \1();/p' -e 's/^$symcode* .* \(.*\)$/extern char \1;/p'" =20 @@ -6128,25 +6119,6 @@ test "x$enable_libtool_lock" !=3D xno && enable_libt= ool_lock=3Dyes # Some flags need to be propagated to the compiler or linker for good # libtool support. case $host in -ia64-*-hpux*) - # Find out which ABI we are using. - echo 'int i;' > conftest.$ac_ext - if { { eval echo "\"\$as_me\":${as_lineno-$LINENO}: \"$ac_compile\""; } = >&5 - (eval $ac_compile) 2>&5 - ac_status=3D$? - $as_echo "$as_me:${as_lineno-$LINENO}: \$? =3D $ac_status" >&5 - test $ac_status =3D 0; }; then - case `/usr/bin/file conftest.$ac_objext` in - *ELF-32*) - HPUX_IA64_MODE=3D"32" - ;; - *ELF-64*) - HPUX_IA64_MODE=3D"64" - ;; - esac - fi - rm -rf conftest* - ;; *-*-irix6*) # Find out which ABI we are using. echo '#line '$LINENO' "configure"' > conftest.$ac_ext @@ -7754,10 +7726,6 @@ $as_echo_n "checking for $compiler option to produce= PIC... " >&6; } case $host_os in aix*) # All AIX code is PIC. - if test "$host_cpu" =3D ia64; then - # AIX 5 now supports IA64 processor - lt_prog_compiler_static=3D'-Bstatic' - fi lt_prog_compiler_pic=3D'-fPIC' ;; =20 @@ -7854,12 +7822,7 @@ $as_echo_n "checking for $compiler option to produce= PIC... " >&6; } case $host_os in aix*) lt_prog_compiler_wl=3D'-Wl,' - if test "$host_cpu" =3D ia64; then - # AIX 5 now supports IA64 processor - lt_prog_compiler_static=3D'-Bstatic' - else - lt_prog_compiler_static=3D'-bnso -bI:/lib/syscalls.exp' - fi + lt_prog_compiler_static=3D'-bnso -bI:/lib/syscalls.exp' ;; =20 mingw* | cygwin* | pw32* | os2* | cegcc*) @@ -7873,7 +7836,7 @@ $as_echo_n "checking for $compiler option to produce = PIC... " >&6; } # PIC is the default for IA64 HP-UX and 64-bit HP-UX, but # not for PA HP-UX. case $host_cpu in - hppa*64*|ia64*) + hppa*64*) # +Z the default ;; *) @@ -8398,7 +8361,6 @@ $as_echo_n "checking whether the $compiler linker ($L= D) supports shared librarie case $host_os in aix[3-9]*) # On AIX/PPC, the GNU linker is very broken - if test "$host_cpu" !=3D ia64; then ld_shlibs=3Dno cat <<_LT_EOF 1>&2 =20 @@ -8410,7 +8372,6 @@ $as_echo_n "checking whether the $compiler linker ($L= D) supports shared librarie *** You will then need to restart the configuration process. =20 _LT_EOF - fi ;; =20 amigaos*) @@ -8506,10 +8467,6 @@ _LT_EOF # Portland Group f77 and f90 compilers whole_archive_flag_spec=3D'${wl}--whole-archive`for conv in $convenienc= e\"\"; do test -n \"$conv\" && new_convenience=3D\"$new_convenience,$conv\= "; done; func_echo_all \"$new_convenience\"` ${wl}--no-whole-archive' tmp_addflag=3D' $pic_flag -Mnomain' ;; - ecc*,ia64* | icc*,ia64*) # Intel C compiler on ia64 - tmp_addflag=3D' -i_dynamic' ;; - efc*,ia64* | ifort*,ia64*) # Intel Fortran compiler on ia64 - tmp_addflag=3D' -i_dynamic -nofor_main' ;; ifc* | ifort*) # Intel Fortran compiler tmp_addflag=3D' -nofor_main' ;; lf95*) # Lahey Fortran 8.1 @@ -8663,13 +8620,6 @@ _LT_EOF ;; =20 aix[4-9]*) - if test "$host_cpu" =3D ia64; then - # On IA64, the linker does run time linking by default, so we don't - # have to do anything special. - aix_use_runtimelinking=3Dno - exp_sym_flag=3D'-Bexport' - no_entry_flag=3D"" - else # If we're using GNU nm, then we don't want the "-C" option. # -C means demangle to AIX nm, but means don't demangle with GNU nm # Also, AIX nm treats weak defined symbols like other global @@ -8696,7 +8646,6 @@ _LT_EOF =20 exp_sym_flag=3D'-bexport' no_entry_flag=3D'-bnoentry' - fi =20 # When large executables or shared objects are built, AIX ld can # have problems creating the table of contents. If linking a library @@ -8739,17 +8688,11 @@ _LT_EOF fi else # not using gcc - if test "$host_cpu" =3D ia64; then - # VisualAge C++, Version 5.5 for AIX 5L for IA-64, Beta 3 Release - # chokes on -Wl,-G. The following line is correct: - shared_flag=3D'-G' - else if test "$aix_use_runtimelinking" =3D yes; then shared_flag=3D'${wl}-G' else shared_flag=3D'${wl}-bM:SRE' fi - fi fi =20 export_dynamic_flag_spec=3D'${wl}-bexpall' @@ -8798,11 +8741,6 @@ if test -z "$aix_libpath"; then aix_libpath=3D"/usr/= lib:/lib"; fi hardcode_libdir_flag_spec=3D'${wl}-blibpath:$libdir:'"$aix_libpath" archive_expsym_cmds=3D'$CC -o $output_objdir/$soname $libobjs $dep= libs '"\${wl}$no_entry_flag"' $compiler_flags `if test "x${allow_undefined_= flag}" !=3D "x"; then func_echo_all "${wl}${allow_undefined_flag}"; else :;= fi` '"\${wl}$exp_sym_flag:\$export_symbols $shared_flag" else - if test "$host_cpu" =3D ia64; then - hardcode_libdir_flag_spec=3D'${wl}-R $libdir:/usr/lib:/lib' - allow_undefined_flag=3D"-z nodefs" - archive_expsym_cmds=3D"\$CC $shared_flag"' -o $output_objdir/$soname $l= ibobjs $deplibs '"\${wl}$no_entry_flag"' $compiler_flags ${wl}${allow_undef= ined_flag} '"\${wl}$exp_sym_flag:\$export_symbols" - else # Determine the default libpath from the value encoded in an # empty executable. if test x$gcc_no_link =3D xyes; then @@ -8853,7 +8791,6 @@ if test -z "$aix_libpath"; then aix_libpath=3D"/usr/l= ib:/lib"; fi archive_cmds_need_lc=3Dyes # This is similar to how AIX traditionally builds its shared libraries. archive_expsym_cmds=3D"\$CC $shared_flag"' -o $output_objdir/$soname $l= ibobjs $deplibs ${wl}-bnoentry $compiler_flags ${wl}-bE:$export_symbols${al= low_undefined_flag}~$AR $AR_FLAGS $output_objdir/$libname$release.a $output= _objdir/$soname' - fi fi ;; =20 @@ -9002,9 +8939,6 @@ if test -z "$aix_libpath"; then aix_libpath=3D"/usr/l= ib:/lib"; fi hppa*64*) archive_cmds=3D'$CC -shared ${wl}+h ${wl}$soname ${wl}+nodefaultrpath -= o $lib $libobjs $deplibs $compiler_flags' ;; - ia64*) - archive_cmds=3D'$CC -shared -fPIC ${wl}+h ${wl}$soname ${wl}+nodefaultr= path -o $lib $libobjs $deplibs $compiler_flags' - ;; *) archive_cmds=3D'$CC -shared -fPIC ${wl}+h ${wl}$soname ${wl}+b ${wl}$in= stall_libdir -o $lib $libobjs $deplibs $compiler_flags' ;; @@ -9014,9 +8948,6 @@ if test -z "$aix_libpath"; then aix_libpath=3D"/usr/l= ib:/lib"; fi hppa*64*) archive_cmds=3D'$CC -b ${wl}+h ${wl}$soname ${wl}+nodefaultrpath -o $li= b $libobjs $deplibs $compiler_flags' ;; - ia64*) - archive_cmds=3D'$CC -b ${wl}+h ${wl}$soname ${wl}+nodefaultrpath -o $li= b $libobjs $deplibs $compiler_flags' - ;; *) =20 # Older versions of the 11.00 compiler do not understand -b yet @@ -9066,7 +8997,7 @@ fi hardcode_libdir_separator=3D: =20 case $host_cpu in - hppa*64*|ia64*) + hppa*64*) hardcode_direct=3Dno hardcode_shlibpath_var=3Dno ;; @@ -9706,11 +9637,6 @@ aix[4-9]*) need_lib_prefix=3Dno need_version=3Dno hardcode_into_libs=3Dyes - if test "$host_cpu" =3D ia64; then - # AIX 5 supports IA64 - library_names_spec=3D'${libname}${release}${shared_ext}$major ${libnam= e}${release}${shared_ext}$versuffix $libname${shared_ext}' - shlibpath_var=3DLD_LIBRARY_PATH - else # With GCC up to 2.95.x, collect2 would create an import file # for dependence libraries. The import file would start with # the line `#! .'. This would cause the generated library to @@ -9742,7 +9668,6 @@ aix[4-9]*) soname_spec=3D'${libname}${release}${shared_ext}$major' fi shlibpath_var=3DLIBPATH - fi ;; =20 amigaos*) @@ -9919,21 +9844,6 @@ hpux9* | hpux10* | hpux11*) need_lib_prefix=3Dno need_version=3Dno case $host_cpu in - ia64*) - shrext_cmds=3D'.so' - hardcode_into_libs=3Dyes - dynamic_linker=3D"$host_os dld.so" - shlibpath_var=3DLD_LIBRARY_PATH - shlibpath_overrides_runpath=3Dyes # Unless +noenvvar is specified. - library_names_spec=3D'${libname}${release}${shared_ext}$versuffix ${li= bname}${release}${shared_ext}$major $libname${shared_ext}' - soname_spec=3D'${libname}${release}${shared_ext}$major' - if test "X$HPUX_IA64_MODE" =3D X32; then - sys_lib_search_path_spec=3D"/usr/lib/hpux32 /usr/local/lib/hpux32 /u= sr/local/lib" - else - sys_lib_search_path_spec=3D"/usr/lib/hpux64 /usr/local/lib/hpux64" - fi - sys_lib_dlsearch_path_spec=3D$sys_lib_search_path_spec - ;; hppa*64*) shrext_cmds=3D'.sl' hardcode_into_libs=3Dyes @@ -11042,7 +10952,7 @@ $as_echo_n "checking whether to build shared librar= ies... " >&6; } ;; =20 aix[4-9]*) - if test "$host_cpu" !=3D ia64 && test "$aix_use_runtimelinking" =3D no= ; then + if test "$aix_use_runtimelinking" =3D no ; then test "$enable_shared" =3D yes && enable_static=3Dno fi ;; diff --git a/zlib/make_vms.com b/zlib/make_vms.com index 65e9d0cbc8e..a26e8bf0656 100644 --- a/zlib/make_vms.com +++ b/zlib/make_vms.com @@ -55,12 +55,11 @@ $ mapfile =3D name + ".map" $ libdefs =3D "" $ vax =3D f$getsyi("HW_MODEL").lt.1024 $ axp =3D f$getsyi("HW_MODEL").ge.1024 .and. f$getsyi("HW_MODEL").lt.= 4096 -$ ia64 =3D f$getsyi("HW_MODEL").ge.4096 $! $! 2012-03-05 SMS. $! Why is this needed? And if it is needed, why not simply ".not. vax"? $! -$!!! if axp .or. ia64 then set proc/parse=3Dextended +$!!! if axp then set proc/parse=3Dextended $! $ whoami =3D f$parse(f$environment("Procedure"),,,,"NO_CONCEAL") $ mydef =3D F$parse(whoami,,,"DEVICE") @@ -107,7 +106,7 @@ $! $! 2012-03-05 SMS. $! Why /NAMES =3D AS_IS? Why not simply ".not. vax"? And why not on VAX? $! -$ if axp .or. ia64 +$ if axp $ then $ ccopt =3D ccopt + "/name=3Das_is/opt=3D(inline=3Dspeed)" $ s_case =3D true @@ -743,7 +742,7 @@ $ module2 =3D "gzclose#gzerror#gzgetc#gzgets#gzopen#gzp= rintf#gzputc#gzputs#gzread" $ module3 =3D "gzseek#gztell#inflate#inflateEnd#inflateInit_#inflateSetDic= tionary" $ module4 =3D "inflateSync#uncompress#zlibVersion#compress" $ open/read map 'p1 -$ if axp .or. ia64 +$ if axp $ then $ open/write aopt a.opt $ open/write bopt b.opt --=20 2.42.0