From: srinath <srinath.parvathaneni@arm.com>
To: <binutils@sourceware.org>
Cc: <richard.earnshaw@arm.com>, <nickc@redhat.com>,
Srinath Parvathaneni <srinath.parvathaneni@arm.com>
Subject: [PATCH v1 5/7][BINUTILS] aarch64: Fix the wrong constraint used for sve2p1 instructions.
Date: Wed, 22 May 2024 11:04:36 +0100 [thread overview]
Message-ID: <20240522100439.1050296-9-srinath.parvathaneni@arm.com> (raw)
In-Reply-To: <20240522100439.1050296-1-srinath.parvathaneni@arm.com>
[-- Attachment #1: Type: text/plain, Size: 1248 bytes --]
HI,
The current implementation for the following SVE2p1 instructions add a constraint in aarch64_opcode_table[]
array, so that these instruction might be immediately preceded in program order by a MOVPRFX instruction.
As per the spec these instruction does not immediately preceded in program order by a MOVPRFX instruction
and to fix this issue, SVE2p1_INSNC macro is replaced with SVE2p1_INSN macro for the entries of these
instructions in aarch64_opcode_table[] array.
List of instructions updated: addqv, andqv, smaxqv, sminqv, umaxqv, uminqv, eorqv, faddqv, fmaxnmqv,
fmaxqv, fminnmqv and fminqv
Regression testing for aarch64-none-elf target and found no regressions.
Ok for binutils-master?
Regards,
Srinath.
---
gas/testsuite/gas/aarch64/sve2p1-1-invalid.d | 4 +
gas/testsuite/gas/aarch64/sve2p1-1-invalid.l | 101 +++++++++++++++++++
gas/testsuite/gas/aarch64/sve2p1-1-invalid.s | 26 +++++
opcodes/aarch64-tbl.h | 25 +++--
4 files changed, 143 insertions(+), 13 deletions(-)
create mode 100644 gas/testsuite/gas/aarch64/sve2p1-1-invalid.d
create mode 100644 gas/testsuite/gas/aarch64/sve2p1-1-invalid.l
create mode 100644 gas/testsuite/gas/aarch64/sve2p1-1-invalid.s
[-- Warning: decoded text below may be mangled, UTF-8 assumed --]
[-- Attachment #2: 0008-PATCH-v1-5-7-BINUTILS-aarch64-Fix-the-wrong-constrai.patch --]
[-- Type: text/x-patch; name="0008-PATCH-v1-5-7-BINUTILS-aarch64-Fix-the-wrong-constrai.patch", Size: 14173 bytes --]
diff --git a/gas/testsuite/gas/aarch64/sve2p1-1-invalid.d b/gas/testsuite/gas/aarch64/sve2p1-1-invalid.d
new file mode 100644
index 00000000000..91066f751ac
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sve2p1-1-invalid.d
@@ -0,0 +1,4 @@
+#name: Illegal test of SVE2.1 min max instructions with movprfx.
+#as: -march=armv9.4-a
+#source: sve2p1-1-invalid.s
+#warning_output: sve2p1-1-invalid.l
diff --git a/gas/testsuite/gas/aarch64/sve2p1-1-invalid.l b/gas/testsuite/gas/aarch64/sve2p1-1-invalid.l
new file mode 100644
index 00000000000..ecece134cf8
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sve2p1-1-invalid.l
@@ -0,0 +1,101 @@
+.*: Assembler messages:
+.*: Warning: SVE `movprfx' compatible instruction expected -- `addqv v0.16b,p0,z0.b'
+.*: Warning: SVE `movprfx' compatible instruction expected -- `addqv v0.8h,p0,z0.h'
+.*: Warning: SVE `movprfx' compatible instruction expected -- `addqv v0.4s,p0,z0.s'
+.*: Warning: SVE `movprfx' compatible instruction expected -- `addqv v0.2d,p0,z0.d'
+.*: Warning: SVE `movprfx' compatible instruction expected -- `andqv v0.16b,p0,z0.b'
+.*: Warning: SVE `movprfx' compatible instruction expected -- `andqv v0.8h,p0,z0.h'
+.*: Warning: SVE `movprfx' compatible instruction expected -- `andqv v0.4s,p0,z0.s'
+.*: Warning: SVE `movprfx' compatible instruction expected -- `andqv v0.2d,p0,z0.d'
+.*: Warning: SVE `movprfx' compatible instruction expected -- `smaxqv v0.16b,p0,z0.b'
+.*: Warning: SVE `movprfx' compatible instruction expected -- `smaxqv v0.8h,p0,z0.h'
+.*: Warning: SVE `movprfx' compatible instruction expected -- `smaxqv v0.4s,p0,z0.s'
+.*: Warning: SVE `movprfx' compatible instruction expected -- `smaxqv v0.2d,p0,z0.d'
+.*: Warning: SVE `movprfx' compatible instruction expected -- `sminqv v0.16b,p0,z0.b'
+.*: Warning: SVE `movprfx' compatible instruction expected -- `sminqv v0.8h,p0,z0.h'
+.*: Warning: SVE `movprfx' compatible instruction expected -- `sminqv v0.4s,p0,z0.s'
+.*: Warning: SVE `movprfx' compatible instruction expected -- `sminqv v0.2d,p0,z0.d'
+.*: Warning: SVE `movprfx' compatible instruction expected -- `umaxqv v0.16b,p0,z0.b'
+.*: Warning: SVE `movprfx' compatible instruction expected -- `umaxqv v0.8h,p0,z0.h'
+.*: Warning: SVE `movprfx' compatible instruction expected -- `umaxqv v0.4s,p0,z0.s'
+.*: Warning: SVE `movprfx' compatible instruction expected -- `umaxqv v0.2d,p0,z0.d'
+.*: Warning: SVE `movprfx' compatible instruction expected -- `uminqv v0.16b,p0,z0.b'
+.*: Warning: SVE `movprfx' compatible instruction expected -- `uminqv v0.8h,p0,z0.h'
+.*: Warning: SVE `movprfx' compatible instruction expected -- `uminqv v0.4s,p0,z0.s'
+.*: Warning: SVE `movprfx' compatible instruction expected -- `uminqv v0.2d,p0,z0.d'
+.*: Warning: SVE `movprfx' compatible instruction expected -- `eorqv v0.16b,p0,z0.b'
+.*: Warning: SVE `movprfx' compatible instruction expected -- `eorqv v0.8h,p0,z0.h'
+.*: Warning: SVE `movprfx' compatible instruction expected -- `eorqv v0.4s,p0,z0.s'
+.*: Warning: SVE `movprfx' compatible instruction expected -- `eorqv v0.2d,p0,z0.d'
+.*: Warning: SVE `movprfx' compatible instruction expected -- `addqv v0.8h,p0,z0.h'
+.*: Warning: SVE `movprfx' compatible instruction expected -- `addqv v0.4s,p0,z0.s'
+.*: Warning: SVE `movprfx' compatible instruction expected -- `addqv v0.2d,p0,z0.d'
+.*: Warning: SVE `movprfx' compatible instruction expected -- `andqv v0.8h,p0,z0.h'
+.*: Warning: SVE `movprfx' compatible instruction expected -- `andqv v0.4s,p0,z0.s'
+.*: Warning: SVE `movprfx' compatible instruction expected -- `andqv v0.2d,p0,z0.d'
+.*: Warning: SVE `movprfx' compatible instruction expected -- `smaxqv v0.8h,p0,z0.h'
+.*: Warning: SVE `movprfx' compatible instruction expected -- `smaxqv v0.4s,p0,z0.s'
+.*: Warning: SVE `movprfx' compatible instruction expected -- `smaxqv v0.2d,p0,z0.d'
+.*: Warning: SVE `movprfx' compatible instruction expected -- `sminqv v0.8h,p0,z0.h'
+.*: Warning: SVE `movprfx' compatible instruction expected -- `sminqv v0.4s,p0,z0.s'
+.*: Warning: SVE `movprfx' compatible instruction expected -- `sminqv v0.2d,p0,z0.d'
+.*: Warning: SVE `movprfx' compatible instruction expected -- `umaxqv v0.8h,p0,z0.h'
+.*: Warning: SVE `movprfx' compatible instruction expected -- `umaxqv v0.4s,p0,z0.s'
+.*: Warning: SVE `movprfx' compatible instruction expected -- `umaxqv v0.2d,p0,z0.d'
+.*: Warning: SVE `movprfx' compatible instruction expected -- `uminqv v0.8h,p0,z0.h'
+.*: Warning: SVE `movprfx' compatible instruction expected -- `uminqv v0.4s,p0,z0.s'
+.*: Warning: SVE `movprfx' compatible instruction expected -- `uminqv v0.2d,p0,z0.d'
+.*: Warning: SVE `movprfx' compatible instruction expected -- `eorqv v0.8h,p0,z0.h'
+.*: Warning: SVE `movprfx' compatible instruction expected -- `eorqv v0.4s,p0,z0.s'
+.*: Warning: SVE `movprfx' compatible instruction expected -- `eorqv v0.2d,p0,z0.d'
+.*: Warning: SVE `movprfx' compatible instruction expected -- `faddqv v0.8h,p0,z0.h'
+.*: Warning: SVE `movprfx' compatible instruction expected -- `faddqv v0.4s,p0,z0.s'
+.*: Warning: SVE `movprfx' compatible instruction expected -- `faddqv v0.2d,p0,z0.d'
+.*: Warning: SVE `movprfx' compatible instruction expected -- `fmaxnmqv v0.8h,p0,z0.h'
+.*: Warning: SVE `movprfx' compatible instruction expected -- `fmaxnmqv v0.4s,p0,z0.s'
+.*: Warning: SVE `movprfx' compatible instruction expected -- `fmaxnmqv v0.2d,p0,z0.d'
+.*: Warning: SVE `movprfx' compatible instruction expected -- `fmaxqv v0.8h,p0,z0.h'
+.*: Warning: SVE `movprfx' compatible instruction expected -- `fmaxqv v0.4s,p0,z0.s'
+.*: Warning: SVE `movprfx' compatible instruction expected -- `fmaxqv v0.2d,p0,z0.d'
+.*: Warning: SVE `movprfx' compatible instruction expected -- `fminnmqv v0.8h,p0,z0.h'
+.*: Warning: SVE `movprfx' compatible instruction expected -- `fminnmqv v0.4s,p0,z0.s'
+.*: Warning: SVE `movprfx' compatible instruction expected -- `fminnmqv v0.2d,p0,z0.d'
+.*: Warning: SVE `movprfx' compatible instruction expected -- `fminqv v0.8h,p0,z0.h'
+.*: Warning: SVE `movprfx' compatible instruction expected -- `fminqv v0.4s,p0,z0.s'
+.*: Warning: SVE `movprfx' compatible instruction expected -- `fminqv v0.2d,p0,z0.d'
+.*: Warning: SVE `movprfx' compatible instruction expected -- `addqv v0.8h,p0,z0.h'
+.*: Warning: SVE `movprfx' compatible instruction expected -- `addqv v0.4s,p0,z0.s'
+.*: Warning: SVE `movprfx' compatible instruction expected -- `addqv v0.2d,p0,z0.d'
+.*: Warning: SVE `movprfx' compatible instruction expected -- `andqv v0.8h,p0,z0.h'
+.*: Warning: SVE `movprfx' compatible instruction expected -- `andqv v0.4s,p0,z0.s'
+.*: Warning: SVE `movprfx' compatible instruction expected -- `andqv v0.2d,p0,z0.d'
+.*: Warning: SVE `movprfx' compatible instruction expected -- `smaxqv v0.8h,p0,z0.h'
+.*: Warning: SVE `movprfx' compatible instruction expected -- `smaxqv v0.4s,p0,z0.s'
+.*: Warning: SVE `movprfx' compatible instruction expected -- `smaxqv v0.2d,p0,z0.d'
+.*: Warning: SVE `movprfx' compatible instruction expected -- `sminqv v0.8h,p0,z0.h'
+.*: Warning: SVE `movprfx' compatible instruction expected -- `sminqv v0.4s,p0,z0.s'
+.*: Warning: SVE `movprfx' compatible instruction expected -- `sminqv v0.2d,p0,z0.d'
+.*: Warning: SVE `movprfx' compatible instruction expected -- `umaxqv v0.8h,p0,z0.h'
+.*: Warning: SVE `movprfx' compatible instruction expected -- `umaxqv v0.4s,p0,z0.s'
+.*: Warning: SVE `movprfx' compatible instruction expected -- `umaxqv v0.2d,p0,z0.d'
+.*: Warning: SVE `movprfx' compatible instruction expected -- `uminqv v0.8h,p0,z0.h'
+.*: Warning: SVE `movprfx' compatible instruction expected -- `uminqv v0.4s,p0,z0.s'
+.*: Warning: SVE `movprfx' compatible instruction expected -- `uminqv v0.2d,p0,z0.d'
+.*: Warning: SVE `movprfx' compatible instruction expected -- `eorqv v0.8h,p0,z0.h'
+.*: Warning: SVE `movprfx' compatible instruction expected -- `eorqv v0.4s,p0,z0.s'
+.*: Warning: SVE `movprfx' compatible instruction expected -- `eorqv v0.2d,p0,z0.d'
+.*: Warning: SVE `movprfx' compatible instruction expected -- `faddqv v0.8h,p0,z0.h'
+.*: Warning: SVE `movprfx' compatible instruction expected -- `faddqv v0.4s,p0,z0.s'
+.*: Warning: SVE `movprfx' compatible instruction expected -- `faddqv v0.2d,p0,z0.d'
+.*: Warning: SVE `movprfx' compatible instruction expected -- `fmaxnmqv v0.8h,p0,z0.h'
+.*: Warning: SVE `movprfx' compatible instruction expected -- `fmaxnmqv v0.4s,p0,z0.s'
+.*: Warning: SVE `movprfx' compatible instruction expected -- `fmaxnmqv v0.2d,p0,z0.d'
+.*: Warning: SVE `movprfx' compatible instruction expected -- `fmaxqv v0.8h,p0,z0.h'
+.*: Warning: SVE `movprfx' compatible instruction expected -- `fmaxqv v0.4s,p0,z0.s'
+.*: Warning: SVE `movprfx' compatible instruction expected -- `fmaxqv v0.2d,p0,z0.d'
+.*: Warning: SVE `movprfx' compatible instruction expected -- `fminnmqv v0.8h,p0,z0.h'
+.*: Warning: SVE `movprfx' compatible instruction expected -- `fminnmqv v0.4s,p0,z0.s'
+.*: Warning: SVE `movprfx' compatible instruction expected -- `fminnmqv v0.2d,p0,z0.d'
+.*: Warning: SVE `movprfx' compatible instruction expected -- `fminqv v0.8h,p0,z0.h'
+.*: Warning: SVE `movprfx' compatible instruction expected -- `fminqv v0.4s,p0,z0.s'
+.*: Warning: SVE `movprfx' compatible instruction expected -- `fminqv v0.2d,p0,z0.d'
diff --git a/gas/testsuite/gas/aarch64/sve2p1-1-invalid.s b/gas/testsuite/gas/aarch64/sve2p1-1-invalid.s
new file mode 100644
index 00000000000..1808027b56e
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sve2p1-1-invalid.s
@@ -0,0 +1,26 @@
+ .irp op1 addqv, andqv, smaxqv, sminqv, umaxqv, uminqv, eorqv
+ movprfx z3, z5
+ \op1 v0.16b, p0, z0.b
+ movprfx z3, z5
+ \op1 v0.8h, p0, z0.h
+ movprfx z3, z5
+ \op1 v0.4s, p0, z0.s
+ movprfx z3, z5
+ \op1 v0.2d, p0, z0.d
+ .endr
+ .irp op1 addqv, andqv, smaxqv, sminqv, umaxqv, uminqv, eorqv, faddqv, fmaxnmqv, fmaxqv, fminnmqv, fminqv
+ movprfx z0.d, p0/m, z31.d
+ \op1 v0.8h, p0, z0.h
+ movprfx z0.d, p0/m, z31.d
+ \op1 v0.4s, p0, z0.s
+ movprfx z0.d, p0/m, z31.d
+ \op1 v0.2d, p0, z0.d
+ .endr
+ .irp op1 addqv, andqv, smaxqv, sminqv, umaxqv, uminqv, eorqv, faddqv, fmaxnmqv, fmaxqv, fminnmqv, fminqv
+ movprfx z0.d, p0/z, z31.d
+ \op1 v0.8h, p0, z0.h
+ movprfx z0.d, p0/z, z31.d
+ \op1 v0.4s, p0, z0.s
+ movprfx z0.d, p0/z, z31.d
+ \op1 v0.2d, p0, z0.d
+ .endr
diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h
index e9a39b3602a..100ae0bb1aa 100644
--- a/opcodes/aarch64-tbl.h
+++ b/opcodes/aarch64-tbl.h
@@ -6464,19 +6464,18 @@ const struct aarch64_opcode aarch64_opcode_table[] =
SME2p1_INSN ("movaz", 0xc0c60200, 0xffff1f01, sme2_movaz, 0, OP2 (SME_Zdnx2, SME_ZA_array_vrsd_1), OP_SVE_DD, 0, 0),
/* SVE2p1 Instructions. */
- SVE2p1_INSNC("addqv",0x04052000, 0xff3fe000, sve2_urqvs, 0, OP3 (Vd, SVE_Pg3, SVE_Zn), OP_SVE_vUS_BHSD_BHSD, F_OPD_SIZE, C_SCAN_MOVPRFX, 0),
- SVE2p1_INSNC("andqv",0x041e2000, 0xff3fe000, sve2_urqvs, 0, OP3 (Vd, SVE_Pg3, SVE_Zn), OP_SVE_vUS_BHSD_BHSD, F_OPD_SIZE, C_SCAN_MOVPRFX, 0),
- SVE2p1_INSNC("smaxqv",0x040c2000, 0xff3fe000, sve2_urqvs, 0, OP3 (Vd, SVE_Pg3, SVE_Zn), OP_SVE_vUS_BHSD_BHSD, F_OPD_SIZE, C_SCAN_MOVPRFX, 0),
- SVE2p1_INSNC("sminqv",0x040e2000, 0xff3fe000, sve2_urqvs, 0, OP3 (Vd, SVE_Pg3, SVE_Zn), OP_SVE_vUS_BHSD_BHSD, F_OPD_SIZE, C_SCAN_MOVPRFX, 0),
- SVE2p1_INSNC("umaxqv",0x040d2000, 0xff3fe000, sve2_urqvs, 0, OP3 (Vd, SVE_Pg3, SVE_Zn), OP_SVE_vUS_BHSD_BHSD, F_OPD_SIZE, C_SCAN_MOVPRFX, 0),
- SVE2p1_INSNC("uminqv",0x040f2000, 0xff3fe000, sve2_urqvs, 0, OP3 (Vd, SVE_Pg3, SVE_Zn), OP_SVE_vUS_BHSD_BHSD, F_OPD_SIZE, C_SCAN_MOVPRFX, 0),
- SVE2p1_INSNC("eorqv",0x041d2000, 0xff3fe000, sve2_urqvs, 0, OP3 (Vd, SVE_Pg3, SVE_Zn), OP_SVE_vUS_BHSD_BHSD, F_OPD_SIZE, C_SCAN_MOVPRFX, 0),
-
- SVE2p1_INSNC("faddqv",0x6410a000, 0xff3fe000, sve2_urqvs, 0, OP3 (Vd, SVE_Pg3, SVE_Zn), OP_SVE_vUS_HSD_HSD, F_OPD_SIZE, C_SCAN_MOVPRFX, 0),
- SVE2p1_INSNC("fmaxnmqv",0x6414a000, 0xff3fe000, sve2_urqvs, 0, OP3 (Vd, SVE_Pg3, SVE_Zn), OP_SVE_vUS_HSD_HSD, F_OPD_SIZE, C_SCAN_MOVPRFX, 0),
- SVE2p1_INSNC("fmaxqv",0x6416a000, 0xff3fe000, sve2_urqvs, 0, OP3 (Vd, SVE_Pg3, SVE_Zn), OP_SVE_vUS_HSD_HSD, F_OPD_SIZE, C_SCAN_MOVPRFX, 0),
- SVE2p1_INSNC("fminnmqv",0x6415a000, 0xff3fe000, sve2_urqvs, 0, OP3 (Vd, SVE_Pg3, SVE_Zn), OP_SVE_vUS_HSD_HSD, F_OPD_SIZE, C_SCAN_MOVPRFX, 0),
- SVE2p1_INSNC("fminqv",0x6417a000, 0xff3fe000, sve2_urqvs, 0, OP3 (Vd, SVE_Pg3, SVE_Zn), OP_SVE_vUS_HSD_HSD, F_OPD_SIZE, C_SCAN_MOVPRFX, 0),
+ SVE2p1_INSN("addqv",0x04052000, 0xff3fe000, sve2_urqvs, 0, OP3 (Vd, SVE_Pg3, SVE_Zn), OP_SVE_vUS_BHSD_BHSD, F_OPD_SIZE, 0),
+ SVE2p1_INSN("andqv",0x041e2000, 0xff3fe000, sve2_urqvs, 0, OP3 (Vd, SVE_Pg3, SVE_Zn), OP_SVE_vUS_BHSD_BHSD, F_OPD_SIZE, 0),
+ SVE2p1_INSN("smaxqv",0x040c2000, 0xff3fe000, sve2_urqvs, 0, OP3 (Vd, SVE_Pg3, SVE_Zn), OP_SVE_vUS_BHSD_BHSD, F_OPD_SIZE, 0),
+ SVE2p1_INSN("sminqv",0x040e2000, 0xff3fe000, sve2_urqvs, 0, OP3 (Vd, SVE_Pg3, SVE_Zn), OP_SVE_vUS_BHSD_BHSD, F_OPD_SIZE, 0),
+ SVE2p1_INSN("umaxqv",0x040d2000, 0xff3fe000, sve2_urqvs, 0, OP3 (Vd, SVE_Pg3, SVE_Zn), OP_SVE_vUS_BHSD_BHSD, F_OPD_SIZE, 0),
+ SVE2p1_INSN("uminqv",0x040f2000, 0xff3fe000, sve2_urqvs, 0, OP3 (Vd, SVE_Pg3, SVE_Zn), OP_SVE_vUS_BHSD_BHSD, F_OPD_SIZE, 0),
+ SVE2p1_INSN("eorqv",0x041d2000, 0xff3fe000, sve2_urqvs, 0, OP3 (Vd, SVE_Pg3, SVE_Zn), OP_SVE_vUS_BHSD_BHSD, F_OPD_SIZE, 0),
+ SVE2p1_INSN("faddqv",0x6410a000, 0xff3fe000, sve2_urqvs, 0, OP3 (Vd, SVE_Pg3, SVE_Zn), OP_SVE_vUS_HSD_HSD, F_OPD_SIZE, 0),
+ SVE2p1_INSN("fmaxnmqv",0x6414a000, 0xff3fe000, sve2_urqvs, 0, OP3 (Vd, SVE_Pg3, SVE_Zn), OP_SVE_vUS_HSD_HSD, F_OPD_SIZE, 0),
+ SVE2p1_INSN("fmaxqv",0x6416a000, 0xff3fe000, sve2_urqvs, 0, OP3 (Vd, SVE_Pg3, SVE_Zn), OP_SVE_vUS_HSD_HSD, F_OPD_SIZE, 0),
+ SVE2p1_INSN("fminnmqv",0x6415a000, 0xff3fe000, sve2_urqvs, 0, OP3 (Vd, SVE_Pg3, SVE_Zn), OP_SVE_vUS_HSD_HSD, F_OPD_SIZE, 0),
+ SVE2p1_INSN("fminqv",0x6417a000, 0xff3fe000, sve2_urqvs, 0, OP3 (Vd, SVE_Pg3, SVE_Zn), OP_SVE_vUS_HSD_HSD, F_OPD_SIZE, 0),
SVE2p1_INSN("dupq",0x05202400, 0xffe0fc00, sve_index, 0, OP2 (SVE_Zd, SVE_Zn_5_INDEX), OP_SVE_VV_BHSD, 0, 0),
SVE2p1_INSNC("extq",0x05602400, 0xfff0fc00, sve_misc, 0, OP4 (SVE_Zd, SVE_Zd, SVE_Zm_5, SVE_UIMM4), OP_SVE_BBBU, 0, C_SCAN_MOVPRFX, 1),
next prev parent reply other threads:[~2024-05-22 10:05 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-05-22 10:04 [PATCH 0/7][Binutils] aarch64: Fix the FEAT_SVE2p1 related issues srinath
2024-05-22 10:04 ` [PATCH 1/7][Binutils] aarch64: Enable mandatory feature bits for v9.4-A srinath
2024-05-22 10:04 ` [PATCH v2 2/7][Binutils] aarch64: Fix sve2p1 dupq instruction operands srinath
2024-05-22 10:04 ` [PATCH v1 2-R/7][Binutils] aarch64: Fix sve2p1 dupq instruction operands (regenerated files) srinath
2024-05-22 10:04 ` [PATCH 3/7][Binutils] aarch64: Fix sve2p1 extq instruction operands srinath
2024-05-22 10:04 ` [PATCH 3-R/7][Binutils] aarch64: Fix sve2p1 extq instruction operands (regenerated files) srinath
2024-05-22 10:04 ` [PATCH v2 4/7][Binutils] aarch64: Fix sve2p1 ld[1-4]/st[1-4]q instruction operands srinath
2024-05-22 10:23 ` Jan Beulich
2024-05-22 11:56 ` Srinath Parvathaneni
2024-05-22 10:04 ` [PATCH v1 4-R/7][Binutils] aarch64: Fix sve2p1 ld[1-4]/st[1-4]q instruction operands (regenerated files) srinath
2024-05-22 10:04 ` srinath [this message]
2024-05-22 10:04 ` [PATCH v1 6/7][Binutils] aarch64: Add extra tests for sve2p1 min max instructions srinath
2024-05-22 10:04 ` [PATCH v1 7/7][Binutils] aarch64: Fix FEAT_B16B16 sve2 instruction constraints srinath
2024-05-22 10:04 ` [PATCH v1 7-R/7][Binutils] aarch64: Fix FEAT_B16B16 sve2 instruction constraints (regenerated files) srinath
2024-06-07 12:52 ` [PATCH 0/7][Binutils] aarch64: Fix the FEAT_SVE2p1 related issues Srinath Parvathaneni
2024-06-07 13:23 ` Richard Earnshaw (lists)
2024-06-07 13:30 ` Srinath Parvathaneni
2024-06-07 14:27 ` Richard Earnshaw (lists)
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