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charset="UTF-8"; format=fixed Content-Transfer-Encoding: 8bit Adds generated files for the previous patch in the series. No other changes. --- opcodes/aarch64-asm-2.c | 116 +++++++++++------------ opcodes/aarch64-dis-2.c | 197 ++++++++++++++++++++++++++-------------- opcodes/aarch64-opc-2.c | 3 + 3 files changed, 191 insertions(+), 125 deletions(-) --------------2.43.2 Content-Type: text/x-patch; name="v6-0004-gas-aarch64-Add-SVE2-lut-extension-generated-file.patch" Content-Transfer-Encoding: 8bit Content-Disposition: attachment; filename="v6-0004-gas-aarch64-Add-SVE2-lut-extension-generated-file.patch" diff --git a/opcodes/aarch64-asm-2.c b/opcodes/aarch64-asm-2.c index 77dcc9a9eac..2e1ab782977 100644 --- a/opcodes/aarch64-asm-2.c +++ b/opcodes/aarch64-asm-2.c @@ -675,21 +675,21 @@ aarch64_insert_operand (const aarch64_operand *self, case 222: case 223: case 224: - case 232: - case 236: - case 240: - case 247: - case 248: - case 255: - case 256: - case 257: + case 235: + case 239: + case 243: + case 250: + case 251: case 258: + case 259: + case 260: + case 261: return aarch64_ins_regno (self, info, code, inst, errors); case 6: case 118: case 119: - case 290: - case 292: + case 293: + case 295: return aarch64_ins_none (self, info, code, inst, errors); case 17: return aarch64_ins_reg_extended (self, info, code, inst, errors); @@ -703,16 +703,13 @@ aarch64_insert_operand (const aarch64_operand *self, case 36: case 37: case 38: - case 294: + case 297: return aarch64_ins_reglane (self, info, code, inst, errors); case 39: case 40: case 41: - case 259: - case 260: - case 275: - case 276: - case 277: + case 262: + case 263: case 278: case 279: case 280: @@ -723,6 +720,9 @@ aarch64_insert_operand (const aarch64_operand *self, case 285: case 286: case 287: + case 288: + case 289: + case 290: return aarch64_ins_simple_index (self, info, code, inst, errors); case 42: return aarch64_ins_reglist (self, info, code, inst, errors); @@ -770,13 +770,13 @@ aarch64_insert_operand (const aarch64_operand *self, case 205: case 206: case 207: - case 261: - case 288: - case 289: + case 264: case 291: - case 293: - case 298: - case 299: + case 292: + case 294: + case 296: + case 301: + case 302: return aarch64_ins_imm (self, info, code, inst, errors); case 51: case 52: @@ -924,7 +924,7 @@ aarch64_insert_operand (const aarch64_operand *self, case 197: case 198: case 199: - case 274: + case 277: return aarch64_ins_sve_shrimm (self, info, code, inst, errors); case 212: case 213: @@ -938,67 +938,71 @@ aarch64_insert_operand (const aarch64_operand *self, return aarch64_ins_sme_za_vrs2 (self, info, code, inst, errors); case 225: case 226: + case 229: + return aarch64_ins_sve_bit_index (self, info, code, inst, errors); case 227: case 228: - case 229: case 230: case 231: - return aarch64_ins_sve_quad_index (self, info, code, inst, errors); + case 232: case 233: - return aarch64_ins_sve_index_imm (self, info, code, inst, errors); case 234: - return aarch64_ins_sve_index (self, info, code, inst, errors); - case 235: + return aarch64_ins_sve_quad_index (self, info, code, inst, errors); + case 236: + return aarch64_ins_sve_index_imm (self, info, code, inst, errors); case 237: - case 254: - case 300: - case 301: - case 302: - return aarch64_ins_sve_reglist (self, info, code, inst, errors); + return aarch64_ins_sve_index (self, info, code, inst, errors); case 238: - case 239: + case 240: + case 257: + case 303: + case 304: + case 305: + return aarch64_ins_sve_reglist (self, info, code, inst, errors); case 241: case 242: - case 243: case 244: - case 253: - return aarch64_ins_sve_aligned_reglist (self, info, code, inst, errors); case 245: case 246: - return aarch64_ins_sve_strided_reglist (self, info, code, inst, errors); + case 247: + case 256: + return aarch64_ins_sve_aligned_reglist (self, info, code, inst, errors); + case 248: case 249: - case 251: - case 262: - return aarch64_ins_sme_za_hv_tiles (self, info, code, inst, errors); - case 250: + return aarch64_ins_sve_strided_reglist (self, info, code, inst, errors); case 252: - return aarch64_ins_sme_za_hv_tiles_range (self, info, code, inst, errors); - case 263: - case 264: + case 254: case 265: + return aarch64_ins_sme_za_hv_tiles (self, info, code, inst, errors); + case 253: + case 255: + return aarch64_ins_sme_za_hv_tiles_range (self, info, code, inst, errors); case 266: case 267: case 268: case 269: - return aarch64_ins_sme_za_array (self, info, code, inst, errors); case 270: - return aarch64_ins_sme_addr_ri_u4xvl (self, info, code, inst, errors); case 271: - return aarch64_ins_sme_sm_za (self, info, code, inst, errors); case 272: - return aarch64_ins_sme_pred_reg_with_index (self, info, code, inst, errors); + return aarch64_ins_sme_za_array (self, info, code, inst, errors); case 273: + return aarch64_ins_sme_addr_ri_u4xvl (self, info, code, inst, errors); + case 274: + return aarch64_ins_sme_sm_za (self, info, code, inst, errors); + case 275: + return aarch64_ins_sme_pred_reg_with_index (self, info, code, inst, errors); + case 276: return aarch64_ins_plain_shrimm (self, info, code, inst, errors); - case 295: - case 296: - case 297: + case 298: + case 299: + case 300: return aarch64_ins_x0_to_x30 (self, info, code, inst, errors); - case 303: - case 304: - case 305: case 306: - return aarch64_ins_rcpc3_addr_opt_offset (self, info, code, inst, errors); case 307: + case 308: + case 309: + return aarch64_ins_rcpc3_addr_opt_offset (self, info, code, inst, errors); + case 310: return aarch64_ins_rcpc3_addr_offset (self, info, code, inst, errors); default: assert (0); abort (); } diff --git a/opcodes/aarch64-dis-2.c b/opcodes/aarch64-dis-2.c index a51cb080c15..626e71dd2d8 100644 --- a/opcodes/aarch64-dis-2.c +++ b/opcodes/aarch64-dis-2.c @@ -20059,17 +20059,72 @@ aarch64_opcode_lookup_1 (uint32_t word) } else { - if (((word >> 22) & 0x1) == 0) + if (((word >> 31) & 0x1) == 0) { - if (((word >> 31) & 0x1) == 0) + if (((word >> 10) & 0x1) == 0) { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - 010001x1x01xxxxx101xxxxxxxxxxxxx - histseg. */ - return 2154; + if (((word >> 11) & 0x1) == 0) + { + if (((word >> 12) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + 010001x1xx1xxxxx101000xxxxxxxxxx + histseg. */ + return 2154; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + 010001x1xx1xxxxx101100xxxxxxxxxx + luti2. */ + return 3347; + } + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + 010001x1xx1xxxxx101x10xxxxxxxxxx + luti2. */ + return 3348; + } } else + { + if (((word >> 11) & 0x1) == 0) + { + if (((word >> 12) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + 010001x1xx1xxxxx101001xxxxxxxxxx + luti4. */ + return 3349; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + 010001x1xx1xxxxx101101xxxxxxxxxx + luti4. */ + return 3350; + } + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + 010001x1xx1xxxxx101x11xxxxxxxxxx + luti4. */ + return 3351; + } + } + } + else + { + if (((word >> 22) & 0x1) == 0) { /* 33222222222211111111110000000000 10987654321098765432109876543210 @@ -20077,14 +20132,14 @@ aarch64_opcode_lookup_1 (uint32_t word) ldff1sw. */ return 1751; } - } - else - { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - x10001x1x11xxxxx101xxxxxxxxxxxxx - ldff1sw. */ - return 1750; + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + 110001x1x11xxxxx101xxxxxxxxxxxxx + ldff1sw. */ + return 1750; + } } } } @@ -33617,21 +33672,21 @@ aarch64_extract_operand (const aarch64_operand *self, case 222: case 223: case 224: - case 232: - case 236: - case 240: - case 247: - case 248: - case 255: - case 256: - case 257: + case 235: + case 239: + case 243: + case 250: + case 251: case 258: + case 259: + case 260: + case 261: return aarch64_ext_regno (self, info, code, inst, errors); case 6: case 118: case 119: - case 290: - case 292: + case 293: + case 295: return aarch64_ext_none (self, info, code, inst, errors); case 11: return aarch64_ext_regrt_sysins (self, info, code, inst, errors); @@ -33650,16 +33705,13 @@ aarch64_extract_operand (const aarch64_operand *self, case 36: case 37: case 38: - case 294: + case 297: return aarch64_ext_reglane (self, info, code, inst, errors); case 39: case 40: case 41: - case 259: - case 260: - case 275: - case 276: - case 277: + case 262: + case 263: case 278: case 279: case 280: @@ -33670,6 +33722,9 @@ aarch64_extract_operand (const aarch64_operand *self, case 285: case 286: case 287: + case 288: + case 289: + case 290: return aarch64_ext_simple_index (self, info, code, inst, errors); case 42: return aarch64_ext_reglist (self, info, code, inst, errors); @@ -33718,13 +33773,13 @@ aarch64_extract_operand (const aarch64_operand *self, case 205: case 206: case 207: - case 261: - case 288: - case 289: + case 264: case 291: - case 293: - case 298: - case 299: + case 292: + case 294: + case 296: + case 301: + case 302: return aarch64_ext_imm (self, info, code, inst, errors); case 51: case 52: @@ -33874,7 +33929,7 @@ aarch64_extract_operand (const aarch64_operand *self, case 197: case 198: case 199: - case 274: + case 277: return aarch64_ext_sve_shrimm (self, info, code, inst, errors); case 212: case 213: @@ -33888,68 +33943,72 @@ aarch64_extract_operand (const aarch64_operand *self, return aarch64_ext_sme_za_vrs2 (self, info, code, inst, errors); case 225: case 226: + case 229: + return aarch64_ext_sve_bit_index (self, info, code, inst, errors); case 227: case 228: - case 229: case 230: case 231: - return aarch64_ext_sve_quad_index (self, info, code, inst, errors); + case 232: case 233: - return aarch64_ext_sve_index_imm (self, info, code, inst, errors); case 234: - return aarch64_ext_sve_index (self, info, code, inst, errors); - case 235: + return aarch64_ext_sve_quad_index (self, info, code, inst, errors); + case 236: + return aarch64_ext_sve_index_imm (self, info, code, inst, errors); case 237: - case 254: - return aarch64_ext_sve_reglist (self, info, code, inst, errors); + return aarch64_ext_sve_index (self, info, code, inst, errors); case 238: - case 239: + case 240: + case 257: + return aarch64_ext_sve_reglist (self, info, code, inst, errors); case 241: case 242: - case 243: case 244: - case 253: - return aarch64_ext_sve_aligned_reglist (self, info, code, inst, errors); case 245: case 246: - return aarch64_ext_sve_strided_reglist (self, info, code, inst, errors); + case 247: + case 256: + return aarch64_ext_sve_aligned_reglist (self, info, code, inst, errors); + case 248: case 249: - case 251: - case 262: - return aarch64_ext_sme_za_hv_tiles (self, info, code, inst, errors); - case 250: + return aarch64_ext_sve_strided_reglist (self, info, code, inst, errors); case 252: - return aarch64_ext_sme_za_hv_tiles_range (self, info, code, inst, errors); - case 263: - case 264: + case 254: case 265: + return aarch64_ext_sme_za_hv_tiles (self, info, code, inst, errors); + case 253: + case 255: + return aarch64_ext_sme_za_hv_tiles_range (self, info, code, inst, errors); case 266: case 267: case 268: case 269: - return aarch64_ext_sme_za_array (self, info, code, inst, errors); case 270: - return aarch64_ext_sme_addr_ri_u4xvl (self, info, code, inst, errors); case 271: - return aarch64_ext_sme_sm_za (self, info, code, inst, errors); case 272: - return aarch64_ext_sme_pred_reg_with_index (self, info, code, inst, errors); + return aarch64_ext_sme_za_array (self, info, code, inst, errors); case 273: + return aarch64_ext_sme_addr_ri_u4xvl (self, info, code, inst, errors); + case 274: + return aarch64_ext_sme_sm_za (self, info, code, inst, errors); + case 275: + return aarch64_ext_sme_pred_reg_with_index (self, info, code, inst, errors); + case 276: return aarch64_ext_plain_shrimm (self, info, code, inst, errors); - case 295: - case 296: - case 297: - return aarch64_ext_x0_to_x30 (self, info, code, inst, errors); + case 298: + case 299: case 300: - case 301: - case 302: - return aarch64_ext_sve_reglist_zt (self, info, code, inst, errors); + return aarch64_ext_x0_to_x30 (self, info, code, inst, errors); case 303: case 304: case 305: + return aarch64_ext_sve_reglist_zt (self, info, code, inst, errors); case 306: - return aarch64_ext_rcpc3_addr_opt_offset (self, info, code, inst, errors); case 307: + case 308: + case 309: + return aarch64_ext_rcpc3_addr_opt_offset (self, info, code, inst, errors); + case 310: return aarch64_ext_rcpc3_addr_offset (self, info, code, inst, errors); default: assert (0); abort (); } diff --git a/opcodes/aarch64-opc-2.c b/opcodes/aarch64-opc-2.c index 7962b0f33e2..bd1aa4f27c1 100644 --- a/opcodes/aarch64-opc-2.c +++ b/opcodes/aarch64-opc-2.c @@ -249,8 +249,11 @@ const struct aarch64_operand aarch64_operands[] = {AARCH64_OPND_CLASS_SVE_REG, "SVE_Zd", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zd}, "an SVE vector register"}, {AARCH64_OPND_CLASS_SVE_REG, "SVE_Zm_5", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zm_5}, "an SVE vector register"}, {AARCH64_OPND_CLASS_SVE_REG, "SVE_Zm_16", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zm_16}, "an SVE vector register"}, + {AARCH64_OPND_CLASS_SVE_REG, "SVE_Zm1_23_INDEX", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zm_16, FLD_SVE_i1_23}, "an indexed SVE vector register"}, + {AARCH64_OPND_CLASS_SVE_REG, "SVE_Zm2_22_INDEX", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zm_16, FLD_SVE_i2}, "an indexed SVE vector register"}, {AARCH64_OPND_CLASS_SVE_REG, "SVE_Zm3_INDEX", 3 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zm_16}, "an indexed SVE vector register"}, {AARCH64_OPND_CLASS_SVE_REG, "SVE_Zm3_11_INDEX", 3 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_i3h2, FLD_SVE_i3l, FLD_SVE_imm3}, "an indexed SVE vector register"}, + {AARCH64_OPND_CLASS_SVE_REG, "SVE_Zm3_12_INDEX", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zm_16, FLD_SVE_i3h3, FLD_SVE_i3l2}, "an indexed SVE vector register"}, {AARCH64_OPND_CLASS_SVE_REG, "SVE_Zm3_19_INDEX", 3 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm2_19, FLD_SVE_imm3}, "an indexed SVE vector register"}, {AARCH64_OPND_CLASS_SVE_REG, "SVE_Zm3_22_INDEX", 3 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_i3h, FLD_SVE_Zm_16}, "an indexed SVE vector register"}, {AARCH64_OPND_CLASS_SVE_REG, "SVE_Zm4_11_INDEX", 4 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_i2h, FLD_SVE_i3l, FLD_SVE_imm4}, "an indexed SVE vector register"}, --------------2.43.2--