* [PATCH v3] RISC-V: Add Zcmt instructions and csr.
@ 2024-05-28 9:44 Jiawei
0 siblings, 0 replies; only message in thread
From: Jiawei @ 2024-05-28 9:44 UTC (permalink / raw)
To: binutils; +Cc: nelson, kito.cheng, Jiawei
This patch supports Zcmt instruction 'cm.jt' and 'cm.jalt'.
Add new CSR jvt for tablejump using.
Version log: update `-march=help` supports.
Co-Authored by: Charlie Keaney <charlie.keaney@embecosm.com>
Co-Authored by: Mary Bennett <mary.bennett@embecosm.com>
Co-Authored by: Nandni Jamnadas <nandni.jamnadas@embecosm.com>
Co-Authored by: Sinan Lin <sinan.lin@linux.alibaba.com>
Co-Authored by: Simon Cook <simon.cook@embecosm.com>
Co-Authored by: Shihua Liao <shihua@iscas.ac.cn>
Co-Authored by: Yulong Shi <yulong@iscas.ac.cn>
bfd/ChangeLog:
* elfxx-riscv.c (riscv_multi_subset_supports): New extension.
(riscv_multi_subset_supports_ext): Ditto.
gas/ChangeLog:
* config/tc-riscv.c (enum riscv_csr_class): New CSR.
(riscv_csr_address): Ditto.
(validate_riscv_insn): New operand.
(riscv_ip): Ditto.
* testsuite/gas/riscv/csr-version-1p10.d: New CSR case.
* testsuite/gas/riscv/csr-version-1p10.l: Ditto.
* testsuite/gas/riscv/csr-version-1p11.d: Ditto.
* testsuite/gas/riscv/csr-version-1p11.l: Ditto.
* testsuite/gas/riscv/csr-version-1p12.d: Ditto.
* testsuite/gas/riscv/csr-version-1p12.l: Ditto.
* testsuite/gas/riscv/csr.s: Ditto.
* testsuite/gas/riscv/march-help.l: New extension.
* testsuite/gas/riscv/zcmt.d: New test.
* testsuite/gas/riscv/zcmt.s: New test.
include/ChangeLog:
* opcode/riscv-opc.h (MATCH_CM_JT): New opcode.
(MASK_CM_JT): New mask.
(MATCH_CM_JALT): New opcode.
(MASK_CM_JALT): New mask.
(CSR_JVT): New CSR.
(DECLARE_INSN): New declaration.
(DECLARE_CSR): Ditto.
* opcode/riscv.h (EXTRACT_ZCMT_INDEX): New marco.
(ENCODE_ZCMT_INDEX): Ditto.
(enum riscv_insn_class): New class.
opcodes/ChangeLog:
* riscv-dis.c (struct riscv_private_data): New data.
(print_jvt_index): New function.
(print_insn_args): New operand.
* riscv-opc.c (match_cm_jt): New function.
(match_cm_jalt): Ditto.
---
bfd/elfxx-riscv.c | 7 +++++
gas/config/tc-riscv.c | 29 ++++++++++++++++++++
gas/testsuite/gas/riscv/csr-version-1p10.d | 2 ++
gas/testsuite/gas/riscv/csr-version-1p10.l | 4 +++
gas/testsuite/gas/riscv/csr-version-1p11.d | 2 ++
gas/testsuite/gas/riscv/csr-version-1p11.l | 4 +++
gas/testsuite/gas/riscv/csr-version-1p12.d | 2 ++
gas/testsuite/gas/riscv/csr-version-1p12.l | 4 +++
gas/testsuite/gas/riscv/csr.s | 3 ++
gas/testsuite/gas/riscv/march-help.l | 1 +
gas/testsuite/gas/riscv/zcmt.d | 14 ++++++++++
gas/testsuite/gas/riscv/zcmt.s | 5 ++++
include/opcode/riscv-opc.h | 12 ++++++++
include/opcode/riscv.h | 5 ++++
opcodes/riscv-dis.c | 32 ++++++++++++++++++++++
opcodes/riscv-opc.c | 23 ++++++++++++++++
16 files changed, 149 insertions(+)
create mode 100644 gas/testsuite/gas/riscv/zcmt.d
create mode 100644 gas/testsuite/gas/riscv/zcmt.s
diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
index dfacb87eda0..ddfb882b9ba 100644
--- a/bfd/elfxx-riscv.c
+++ b/bfd/elfxx-riscv.c
@@ -1268,6 +1268,8 @@ static struct riscv_implicit_subset riscv_implicit_subsets[] =
{"zcd", "zca", check_implicit_always},
{"zcb", "zca", check_implicit_always},
{"zcmp", "zca", check_implicit_always},
+ {"zcmt", "zca", check_implicit_always},
+ {"zcmt", "zicsr", check_implicit_always},
{"smaia", "ssaia", check_implicit_always},
{"smcntrpmf", "zicsr", check_implicit_always},
{"smstateen", "ssstateen", check_implicit_always},
@@ -1425,6 +1427,7 @@ static struct riscv_supported_ext riscv_supported_std_z_ext[] =
{"zcf", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"zcd", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"zcmp", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
+ {"zcmt", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{NULL, 0, 0, 0, 0}
};
@@ -2666,6 +2669,8 @@ riscv_multi_subset_supports (riscv_parse_subset_t *rps,
&& riscv_subset_supports (rps, "zmmul"));
case INSN_CLASS_ZCMP:
return riscv_subset_supports (rps, "zcmp");
+ case INSN_CLASS_ZCMT:
+ return riscv_subset_supports (rps, "zcmt");
case INSN_CLASS_SVINVAL:
return riscv_subset_supports (rps, "svinval");
case INSN_CLASS_H:
@@ -2924,6 +2929,8 @@ riscv_multi_subset_supports_ext (riscv_parse_subset_t *rps,
return _("zcb' and `zmmul', or `zcb' and `m");
case INSN_CLASS_ZCMP:
return "zcmp";
+ case INSN_CLASS_ZCMT:
+ return "zcmt";
case INSN_CLASS_SVINVAL:
return "svinval";
case INSN_CLASS_H:
diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c
index 8d749581c1d..fb66563fd7c 100644
--- a/gas/config/tc-riscv.c
+++ b/gas/config/tc-riscv.c
@@ -71,6 +71,7 @@ enum riscv_csr_class
CSR_CLASS_I_32, /* rv32 only */
CSR_CLASS_F, /* f-ext only */
CSR_CLASS_ZKR, /* zkr only */
+ CSR_CLASS_ZCMT, /* zcmt only */
CSR_CLASS_V, /* rvv only */
CSR_CLASS_DEBUG, /* debug CSR */
CSR_CLASS_H, /* hypervisor */
@@ -1050,6 +1051,9 @@ riscv_csr_address (const char *csr_name,
case CSR_CLASS_ZKR:
extension = "zkr";
break;
+ case CSR_CLASS_ZCMT:
+ extension = "zcmt";
+ break;
case CSR_CLASS_V:
extension = "zve32x";
break;
@@ -1608,6 +1612,9 @@ validate_riscv_insn (const struct riscv_opcode *opc, int length)
case 'p': used_bits |= ENCODE_ZCMP_SPIMM (-1U); break;
/* Register list operand for cm.push and cm.pop. */
case 'r': USE_BITS (OP_MASK_REG_LIST, OP_SH_REG_LIST); break;
+ /* Table jump used by cm.jt or cm.jalt. */
+ case 'i':
+ case 'I': used_bits |= ENCODE_ZCMT_INDEX (-1U); break;
case 'f': break;
default:
goto unknown_validate_operand;
@@ -3852,6 +3859,28 @@ riscv_ip (char *str, struct riscv_cl_insn *ip, expressionS *imm_expr,
asarg = expr_parse_end;
imm_expr->X_op = O_absent;
continue;
+ case 'I': /* index operand of cm.jt. The range is from 0 to 31. */
+ my_getExpression (imm_expr, asarg);
+ if (imm_expr->X_op != O_constant
+ || imm_expr->X_add_number < 0
+ || imm_expr->X_add_number > 31)
+ {
+ as_bad ("bad index value for cm.jt, range: [0, 31]");
+ break;
+ }
+ ip->insn_opcode |= ENCODE_ZCMT_INDEX (imm_expr->X_add_number);
+ goto rvc_imm_done;
+ case 'i': /* index operand of cm.jalt. The range is from 32 to 255. */
+ my_getExpression (imm_expr, asarg);
+ if (imm_expr->X_op != O_constant
+ || imm_expr->X_add_number < 32
+ || imm_expr->X_add_number > 255)
+ {
+ as_bad ("bad index value for cm.jalt, range: [32, 255]");
+ break;
+ }
+ ip->insn_opcode |= ENCODE_ZCMT_INDEX (imm_expr->X_add_number);
+ goto rvc_imm_done;
default:
goto unknown_riscv_ip_operand;
}
diff --git a/gas/testsuite/gas/riscv/csr-version-1p10.d b/gas/testsuite/gas/riscv/csr-version-1p10.d
index 2ee4ee55ecd..6e8e0f81c1e 100644
--- a/gas/testsuite/gas/riscv/csr-version-1p10.d
+++ b/gas/testsuite/gas/riscv/csr-version-1p10.d
@@ -869,3 +869,5 @@ Disassembly of section .text:
[ ]+[0-9a-f]+:[ ]+c2159073[ ]+csrw[ ]+vtype,a1
[ ]+[0-9a-f]+:[ ]+c2202573[ ]+csrr[ ]+a0,vlenb
[ ]+[0-9a-f]+:[ ]+c2259073[ ]+csrw[ ]+vlenb,a1
+[ ]+[0-9a-f]+:[ ]+01702573[ ]+csrr[ ]+a0,jvt
+[ ]+[0-9a-f]+:[ ]+01759073[ ]+csrw[ ]+jvt,a1
diff --git a/gas/testsuite/gas/riscv/csr-version-1p10.l b/gas/testsuite/gas/riscv/csr-version-1p10.l
index 63991d5023c..bdbc414613e 100644
--- a/gas/testsuite/gas/riscv/csr-version-1p10.l
+++ b/gas/testsuite/gas/riscv/csr-version-1p10.l
@@ -1561,3 +1561,7 @@
.*Info: macro .*
.*Warning: read-only CSR is written `csrw vlenb,a1'
.*Info: macro .*
+.*Warning: invalid CSR `jvt', needs `zcmt' extension
+.*Info: macro .*
+.*Warning: invalid CSR `jvt', needs `zcmt' extension
+.*Info: macro .*
diff --git a/gas/testsuite/gas/riscv/csr-version-1p11.d b/gas/testsuite/gas/riscv/csr-version-1p11.d
index 836dedef86a..d06282677db 100644
--- a/gas/testsuite/gas/riscv/csr-version-1p11.d
+++ b/gas/testsuite/gas/riscv/csr-version-1p11.d
@@ -869,3 +869,5 @@ Disassembly of section .text:
[ ]+[0-9a-f]+:[ ]+c2159073[ ]+csrw[ ]+vtype,a1
[ ]+[0-9a-f]+:[ ]+c2202573[ ]+csrr[ ]+a0,vlenb
[ ]+[0-9a-f]+:[ ]+c2259073[ ]+csrw[ ]+vlenb,a1
+[ ]+[0-9a-f]+:[ ]+01702573[ ]+csrr[ ]+a0,jvt
+[ ]+[0-9a-f]+:[ ]+01759073[ ]+csrw[ ]+jvt,a1
diff --git a/gas/testsuite/gas/riscv/csr-version-1p11.l b/gas/testsuite/gas/riscv/csr-version-1p11.l
index 6caec9f63a5..9f8ca8acd1d 100644
--- a/gas/testsuite/gas/riscv/csr-version-1p11.l
+++ b/gas/testsuite/gas/riscv/csr-version-1p11.l
@@ -1557,3 +1557,7 @@
.*Info: macro .*
.*Warning: read-only CSR is written `csrw vlenb,a1'
.*Info: macro .*
+.*Warning: invalid CSR `jvt', needs `zcmt' extension
+.*Info: macro .*
+.*Warning: invalid CSR `jvt', needs `zcmt' extension
+.*Info: macro .*
diff --git a/gas/testsuite/gas/riscv/csr-version-1p12.d b/gas/testsuite/gas/riscv/csr-version-1p12.d
index beeec9a580f..272b615a9d4 100644
--- a/gas/testsuite/gas/riscv/csr-version-1p12.d
+++ b/gas/testsuite/gas/riscv/csr-version-1p12.d
@@ -869,3 +869,5 @@ Disassembly of section .text:
[ ]+[0-9a-f]+:[ ]+c2159073[ ]+csrw[ ]+vtype,a1
[ ]+[0-9a-f]+:[ ]+c2202573[ ]+csrr[ ]+a0,vlenb
[ ]+[0-9a-f]+:[ ]+c2259073[ ]+csrw[ ]+vlenb,a1
+[ ]+[0-9a-f]+:[ ]+01702573[ ]+csrr[ ]+a0,jvt
+[ ]+[0-9a-f]+:[ ]+01759073[ ]+csrw[ ]+jvt,a1
diff --git a/gas/testsuite/gas/riscv/csr-version-1p12.l b/gas/testsuite/gas/riscv/csr-version-1p12.l
index b83a0012004..52afe294cae 100644
--- a/gas/testsuite/gas/riscv/csr-version-1p12.l
+++ b/gas/testsuite/gas/riscv/csr-version-1p12.l
@@ -1321,3 +1321,7 @@
.*Info: macro .*
.*Warning: read-only CSR is written `csrw vlenb,a1'
.*Info: macro .*
+.*Warning: invalid CSR `jvt', needs `zcmt' extension
+.*Info: macro .*
+.*Warning: invalid CSR `jvt', needs `zcmt' extension
+.*Info: macro .*
diff --git a/gas/testsuite/gas/riscv/csr.s b/gas/testsuite/gas/riscv/csr.s
index 42bb158547b..0f36f43572b 100644
--- a/gas/testsuite/gas/riscv/csr.s
+++ b/gas/testsuite/gas/riscv/csr.s
@@ -497,3 +497,6 @@
csr vl
csr vtype
csr vlenb
+
+ # Zcmt
+ csr jvt
diff --git a/gas/testsuite/gas/riscv/march-help.l b/gas/testsuite/gas/riscv/march-help.l
index c5754837e05..1bb1bfd09a2 100644
--- a/gas/testsuite/gas/riscv/march-help.l
+++ b/gas/testsuite/gas/riscv/march-help.l
@@ -91,6 +91,7 @@ All available -march extensions for RISC-V:
zcf 1.0
zcd 1.0
zcmp 1.0
+ zcmt 1.0
smaia 1.0
smcntrpmf 1.0
smepmp 1.0
diff --git a/gas/testsuite/gas/riscv/zcmt.d b/gas/testsuite/gas/riscv/zcmt.d
new file mode 100644
index 00000000000..d37e4644869
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zcmt.d
@@ -0,0 +1,14 @@
+#as: -march=rv32i_zcmt
+#source: zcmt.s
+#objdump: -dr -Mno-aliases
+
+.*:[ ]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+[ ]*[0-9a-f]+:[ ]+a002[ ]+cm.jt[ ]+0 # a07ea002 <target\+0xa07ea002>
+[ ]*[0-9a-f]+:[ ]+a07e[ ]+cm.jt[ ]+31
+[ ]*[0-9a-f]+:[ ]+a102[ ]+cm.jalt[ ]+64
+[ ]*[0-9a-f]+:[ ]+a3fe[ ]+cm.jalt[ ]+255
diff --git a/gas/testsuite/gas/riscv/zcmt.s b/gas/testsuite/gas/riscv/zcmt.s
new file mode 100644
index 00000000000..0392eea9846
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zcmt.s
@@ -0,0 +1,5 @@
+target:
+ cm.jt 0
+ cm.jt 31
+ cm.jalt 64
+ cm.jalt 255
diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h
index ae14e14d427..1eeceacc99e 100644
--- a/include/opcode/riscv-opc.h
+++ b/include/opcode/riscv-opc.h
@@ -2280,6 +2280,11 @@
#define MASK_CM_POPRET 0xff03
#define MATCH_CM_POPRETZ 0xbc02
#define MASK_CM_POPRETZ 0xff03
+/* Zcmt instructions. */
+#define MATCH_CM_JT 0xa002
+#define MASK_CM_JT 0xff03
+#define MATCH_CM_JALT 0xa002
+#define MASK_CM_JALT 0xfc03
/* Svinval instruction. */
#define MATCH_SINVAL_VMA 0x16000073
#define MASK_SINVAL_VMA 0xfe007fff
@@ -3504,6 +3509,8 @@
#define CSR_MSCONTEXT 0x7aa
/* Unprivileged Scalar Crypto CSR addresses. */
#define CSR_SEED 0x015
+/* Unprivileged Zcmt CSR addresses. */
+#define CSR_JVT 0x017
/* Unprivileged Vector CSR addresses. */
#define CSR_VSTART 0x008
#define CSR_VXSAT 0x009
@@ -3978,6 +3985,9 @@ DECLARE_INSN(cm_push, MATCH_CM_PUSH, MASK_CM_PUSH)
DECLARE_INSN(cm_pop, MATCH_CM_POP, MASK_CM_POP)
DECLARE_INSN(cm_popret, MATCH_CM_POPRET, MASK_CM_POPRET)
DECLARE_INSN(cm_popretz, MATCH_CM_POPRETZ, MASK_CM_POPRETZ)
+/* Zcmt instructions. */
+DECLARE_INSN(cm_jt, MATCH_CM_JT, MASK_CM_JT)
+DECLARE_INSN(cm_jalt, MATCH_CM_JALT, MASK_CM_JALT)
/* Vendor-specific (T-Head) XTheadBa instructions. */
DECLARE_INSN(th_addsl, MATCH_TH_ADDSL, MASK_TH_ADDSL)
/* Vendor-specific (T-Head) XTheadBb instructions. */
@@ -4529,6 +4539,8 @@ DECLARE_CSR(mcontext, CSR_MCONTEXT, CSR_CLASS_DEBUG, PRIV_SPEC_CLASS_NONE, PRIV_
DECLARE_CSR(mscontext, CSR_MSCONTEXT, CSR_CLASS_DEBUG, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
/* Unprivileged Scalar Crypto CSRs. */
DECLARE_CSR(seed, CSR_SEED, CSR_CLASS_ZKR, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
+/* Unprivileged Zcmt CSRs. */
+DECLARE_CSR(jvt, CSR_JVT, CSR_CLASS_ZCMT, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
/* Unprivileged Vector CSRs. */
DECLARE_CSR(vstart, CSR_VSTART, CSR_CLASS_V, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
DECLARE_CSR(vxsat, CSR_VXSAT, CSR_CLASS_V, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h
index 5f516a1026e..6ee6df10f04 100644
--- a/include/opcode/riscv.h
+++ b/include/opcode/riscv.h
@@ -114,6 +114,8 @@ static inline unsigned int riscv_insn_length (insn_t insn)
(RV_X(x, 5, 1) << 1)
#define EXTRACT_ZCMP_SPIMM(x) \
(RV_X(x, 2, 2) << 4)
+#define EXTRACT_ZCMT_INDEX(x) \
+ (RV_X(x, 2, 8))
/* Vendor-specific (CORE-V) extract macros. */
#define EXTRACT_CV_IS2_UIMM5(x) \
(RV_X(x, 20, 5))
@@ -172,6 +174,8 @@ static inline unsigned int riscv_insn_length (insn_t insn)
(RV_X(x, 1, 1) << 5)
#define ENCODE_ZCMP_SPIMM(x) \
(RV_X(x, 4, 2) << 2)
+#define ENCODE_ZCMT_INDEX(x) \
+ (RV_X(x, 0, 8) << 2)
/* Vendor-specific (CORE-V) encode macros. */
#define ENCODE_CV_IS2_UIMM5(x) \
(RV_X(x, 0, 5) << 20)
@@ -481,6 +485,7 @@ enum riscv_insn_class
INSN_CLASS_ZCB_AND_ZBB,
INSN_CLASS_ZCB_AND_ZMMUL,
INSN_CLASS_ZCMP,
+ INSN_CLASS_ZCMT,
INSN_CLASS_SVINVAL,
INSN_CLASS_ZICBOM,
INSN_CLASS_ZICBOP,
diff --git a/opcodes/riscv-dis.c b/opcodes/riscv-dis.c
index e6596c47423..1dc3f1fb3e8 100644
--- a/opcodes/riscv-dis.c
+++ b/opcodes/riscv-dis.c
@@ -56,6 +56,8 @@ struct riscv_private_data
{
bfd_vma gp;
bfd_vma print_addr;
+ bfd_vma jvt_base;
+ bfd_vma jvt_end;
bfd_vma hi_addr[OP_MASK_RD + 1];
bool to_print_addr;
bool has_gp;
@@ -215,6 +217,30 @@ maybe_print_address (struct riscv_private_data *pd, int base_reg, int offset,
pd->print_addr = (bfd_vma)(uint32_t)pd->print_addr;
}
+/* Print table jump index. */
+
+static bool
+print_jvt_index (disassemble_info *info, unsigned int index)
+{
+ bfd_vma entry_value;
+ bfd_vma memaddr;
+ int status;
+
+ bfd_byte packet[8] = {0};
+ struct riscv_private_data *pd = info->private_data;
+
+ memaddr = pd->jvt_base + index * (xlen/8);
+ status = (*info->read_memory_func) (memaddr, packet, xlen / 8, info);
+ if (status != 0)
+ return false;
+
+ entry_value = xlen == 32 ? bfd_getl32 (packet)
+ : bfd_getl64 (packet);
+
+ maybe_print_address (pd, 0, entry_value, 0);
+ return true;
+}
+
/* Get Zcmp reg_list field. */
static void
@@ -685,6 +711,12 @@ print_insn_args (const char *oparg, insn_t l, bfd_vma pc, disassemble_info *info
print (info->stream, dis_style_immediate, "%d",
riscv_get_spimm (l));
break;
+ case 'i':
+ case 'I':
+ print (info->stream, dis_style_address_offset,
+ "%lu", EXTRACT_ZCMT_INDEX (l));
+ print_jvt_index (info, EXTRACT_ZCMT_INDEX (l));
+ break;
default:
goto undefined_modifier;
}
diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
index 1ef4eaddf4d..c4a86cdcb01 100644
--- a/opcodes/riscv-opc.c
+++ b/opcodes/riscv-opc.c
@@ -307,6 +307,25 @@ match_vs1_eq_vs2 (const struct riscv_opcode *op,
return match_opcode (op, insn) && vs1 == vs2;
}
+/* This is used for cm.jt. This requires index operand to be less than 32. */
+
+static int
+match_cm_jt (const struct riscv_opcode *op, insn_t insn)
+{
+ return match_opcode (op, insn)
+ && EXTRACT_ZCMT_INDEX (insn) < 32;
+}
+
+/* This is used for cm.jalt. This requires index operand to be in 32 to 255. */
+
+static int
+match_cm_jalt (const struct riscv_opcode *op, insn_t insn)
+{
+ return match_opcode (op, insn)
+ && EXTRACT_ZCMT_INDEX (insn) >= 32
+ && EXTRACT_ZCMT_INDEX (insn) < 256;
+}
+
static int
match_vd_eq_vs1_eq_vs2 (const struct riscv_opcode *op,
insn_t insn)
@@ -2088,6 +2107,10 @@ const struct riscv_opcode riscv_opcodes[] =
{"cm.popret", 0, INSN_CLASS_ZCMP, "{Wcr},Wcp", MATCH_CM_POPRET, MASK_CM_POPRET, match_opcode, 0 },
{"cm.popretz", 0, INSN_CLASS_ZCMP, "{Wcr},Wcp", MATCH_CM_POPRETZ, MASK_CM_POPRETZ, match_opcode, 0 },
+/* Zcmt instructions */
+{"cm.jt", 0, INSN_CLASS_ZCMT, "WcI", MATCH_CM_JT, MASK_CM_JT, match_cm_jt, 0 },
+{"cm.jalt", 0, INSN_CLASS_ZCMT, "Wci", MATCH_CM_JALT, MASK_CM_JALT, match_cm_jalt, 0 },
+
/* Supervisor instructions. */
{"csrr", 0, INSN_CLASS_ZICSR, "d,E", MATCH_CSRRS, MASK_CSRRS|MASK_RS1, match_opcode, INSN_ALIAS },
{"csrwi", 0, INSN_CLASS_ZICSR, "E,Z", MATCH_CSRRWI, MASK_CSRRWI|MASK_RD, match_opcode, INSN_ALIAS },
--
2.25.1
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