From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from EUR04-DB3-obe.outbound.protection.outlook.com (mail-db3eur04on060a.outbound.protection.outlook.com [IPv6:2a01:111:f400:fe0c::60a]) by sourceware.org (Postfix) with ESMTPS id 175B438654B0 for ; Tue, 28 May 2024 14:47:27 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 175B438654B0 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=arm.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 175B438654B0 Authentication-Results: server2.sourceware.org; arc=pass smtp.remote-ip=2a01:111:f400:fe0c::60a ARC-Seal: i=3; a=rsa-sha256; d=sourceware.org; s=key; t=1716907652; cv=pass; b=oQwnnkdwwdxOoshotseEIK45ufb0FGQnuEcUDhJ6icnrAaGpuoXJFnE8j2zuqQ11oLoRV4xvTpFwC8GgBA7ZCv9gK4LVJDaUmrJG4DbmgkLwxREeWk4H1f81RwIJbnT69oqdI6w6P6ZJrRKWljjuS8NXFto821ZzRWJr48EuPoI= ARC-Message-Signature: i=3; a=rsa-sha256; d=sourceware.org; s=key; t=1716907652; c=relaxed/simple; bh=Jvc36c1dvP26aed709XNoJxFInLojdRuEXGfbFbov0I=; h=DKIM-Signature:DKIM-Signature:From:To:Subject:Date:Message-ID: MIME-Version; b=PWrTtqObyPIDjZoNpRXTzlKE/QCxCBg6jt77qI+UA/EZbP2063mE8yazsev4J5FJ43o+m2kA4NGzJLvs13wLQzoEAduI8OnjohD7h/lxJJscT5bLnqyRqRQSBGs8CFrSsUjSxtuxft+DYrnnBlObUN9WAHBfWfuyoRPkVgMcNOk= ARC-Authentication-Results: i=3; server2.sourceware.org ARC-Seal: i=2; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=pass; b=AnaG5cMdjtHI1Ay+oqCbCazkdTLwnuTKKynoykV3ZbL0gbS7qNDlCIJcQ9bR0qDzz0hgWwoNw6Dvu46iMWZ7EBkzTVM/CdqRnZuJwRqV8XVi6OxPl7xLEbR1T9u2tjnOHs1OBGMxUKInfmuZ/I/TbNtuV0y34VCC/tRJPvy66vcs6ygJiHAn0sCWGTrh+eeo1kcm3qD2U0Nu6eolxFUGpjv3qJyTCrjepvyy9ca0eL9pib2Qo/BEadjCxxZ3AuZq1eJXHAZs8j+00cGXtNHFkqxC53qy9uC3XZSZJ//SHEpl6p/MVJL5brRWCYVqwL1WyB67f05bNWYLJ9fyvVpjyA== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=PIu8GJu7iNJKAGuUT6I51nA0RwBLvSWjdNabSvd2eBE=; b=nQecQ0fQPcrjE9D6Iv5Jj2hLPfq6nrV4q5ggJfSNo2KCWyZLGdaCtRD8NCryTTzzeG8+vUpttTGm7XrIpDdOZg6pi+Re2KZQlfEZ5suQOsPm1vB26V6iCRMJ7X6RYHpAEJvNXRBBjyK3rVkCl3XMyHWG6O5nhCcjQqIyFoLjKpLoyXl2jQq4CmC41iMthwqDolhwnbgkF+EZbO16tlh8YT9t8PC3Z3wXxKDRNWNKjVjKB2pFWKaHGKxDoB9rZQX5KAtYC4Pd0to5Cn5slTgVEzDhWx3NW8xZJ3MNVjMe17PvBZMcDV6NpyE4qcdbt+7WFbclaMACnaH+8BkJ2jZL0Q== ARC-Authentication-Results: i=2; mx.microsoft.com 1; spf=pass (sender ip is 63.35.35.123) smtp.rcpttodomain=sourceware.org smtp.mailfrom=arm.com; dmarc=pass (p=none sp=none pct=100) action=none header.from=arm.com; dkim=pass (signature was verified) header.d=arm.com; arc=pass (0 oda=1 ltdi=1 spf=[1,1,smtp.mailfrom=arm.com] dmarc=[1,1,header.from=arm.com]) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=arm.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=PIu8GJu7iNJKAGuUT6I51nA0RwBLvSWjdNabSvd2eBE=; b=ADVS3+XwqlFyuMPTOMts/ycpsVBEWzwr1wtXWbqTrkYtGDtUHYScJeco5W2qH3b7ozbd8eTyr07hoRXmTssCjogLjw7N1vHXz4aP9ruYO2pLpeZDjtaB6DUdIIBPqnkAwmWRFRMf1tkYbfrt/DjKMP05zZEAhtdAY9Vyn4aa0S0= Received: from DU2PR04CA0281.eurprd04.prod.outlook.com (2603:10a6:10:28c::16) by DB5PR08MB10115.eurprd08.prod.outlook.com (2603:10a6:10:4a2::17) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7611.30; Tue, 28 May 2024 14:47:24 +0000 Received: from DB5PEPF00014B90.eurprd02.prod.outlook.com (2603:10a6:10:28c:cafe::e0) by DU2PR04CA0281.outlook.office365.com (2603:10a6:10:28c::16) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7611.28 via Frontend Transport; Tue, 28 May 2024 14:47:24 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 63.35.35.123) smtp.mailfrom=arm.com; dkim=pass (signature was verified) header.d=arm.com;dmarc=pass action=none header.from=arm.com; Received-SPF: Pass (protection.outlook.com: domain of arm.com designates 63.35.35.123 as permitted sender) receiver=protection.outlook.com; client-ip=63.35.35.123; helo=64aa7808-outbound-1.mta.getcheckrecipient.com; pr=C Received: from 64aa7808-outbound-1.mta.getcheckrecipient.com (63.35.35.123) by DB5PEPF00014B90.mail.protection.outlook.com (10.167.8.228) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.20.7633.15 via Frontend Transport; Tue, 28 May 2024 14:47:24 +0000 Received: ("Tessian outbound 2fd40f2ccfd7:v327"); Tue, 28 May 2024 14:47:23 +0000 X-CheckRecipientChecked: true X-CR-MTA-CID: 145996989cf02197 X-CR-MTA-TID: 64aa7808 Received: from ea707d0e801e.1 by 64aa7808-outbound-1.mta.getcheckrecipient.com id D867EE32-BA1E-4545-BF8C-C5B8234EF43D.1; Tue, 28 May 2024 14:47:16 +0000 Received: from EUR04-VI1-obe.outbound.protection.outlook.com by 64aa7808-outbound-1.mta.getcheckrecipient.com with ESMTPS id ea707d0e801e.1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384); Tue, 28 May 2024 14:47:16 +0000 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=hHVoe6FO53U1IYkZ7+ut3qZnJuJBlKF4GcQyhfSAUHpf9txXD2JulLOkclhap9Bo6eOSoAlyIVIuOjAzksN5qoc6X4/YFOF6+z9QarriRrZnGIc3ovtvxDAtwSX0zzagJzt+hvs+VKMig95729tZ5ULhU/ncCK+4UT6pjhSzPxpdW+BLfnLCpvHcsCu70sPeVHGaLG3cKdH2dpst2/ipfC5yeFm4YACgLmmJmSjrlMCJgwtjZM5rVvucacqVhyVLcmh+V8YN3tAtAkaExHi21j0AQVJy4LQQjUlqZjCTgObMpcSrEijj+oA2315TwoH4kzrTLxEaIz9cqAmIWbRFMw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=PIu8GJu7iNJKAGuUT6I51nA0RwBLvSWjdNabSvd2eBE=; b=j+/KINMUcy+0yjy35b472ACGotqUbj/pDR/O6+pR++t0z70JzV3DFEXMzV+OMvGmOjKOgeVTWtrE9ehvpre1W8xUU4lW5n8B4M9/Sv+YMTAhY06mu9xXB+pgleUlyn0Gp9eA8nFI30KLR9N9Weg3KgOXBv0Zf28JkZslM+YVRv0U9XfQIWompdYYd88dztqAD7M3KQMG+ydzhlIeNaAXFhWu8Nx+jij8VlGXbxfDvdhEB7ZYKQ5ZvZRt/qpRdw0SMwiqpu9b729gBiHt1atePmUzzevEHvTGDxQtPJ/dR5sBaf5hSMUcGUbkBBANvSzen0wbmGjq8Z6QdY5vf1FSeA== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 40.67.248.234) smtp.rcpttodomain=sourceware.org smtp.mailfrom=arm.com; dmarc=pass (p=none sp=none pct=100) action=none header.from=arm.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=arm.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=PIu8GJu7iNJKAGuUT6I51nA0RwBLvSWjdNabSvd2eBE=; b=ADVS3+XwqlFyuMPTOMts/ycpsVBEWzwr1wtXWbqTrkYtGDtUHYScJeco5W2qH3b7ozbd8eTyr07hoRXmTssCjogLjw7N1vHXz4aP9ruYO2pLpeZDjtaB6DUdIIBPqnkAwmWRFRMf1tkYbfrt/DjKMP05zZEAhtdAY9Vyn4aa0S0= Received: from DUZPR01CA0043.eurprd01.prod.exchangelabs.com (2603:10a6:10:468::6) by GV1PR08MB7730.eurprd08.prod.outlook.com (2603:10a6:150:51::7) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7611.30; Tue, 28 May 2024 14:47:13 +0000 Received: from DB1PEPF000509E8.eurprd03.prod.outlook.com (2603:10a6:10:468:cafe::8a) by DUZPR01CA0043.outlook.office365.com (2603:10a6:10:468::6) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7611.30 via Frontend Transport; Tue, 28 May 2024 14:47:12 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 40.67.248.234) smtp.mailfrom=arm.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=arm.com; Received-SPF: Pass (protection.outlook.com: domain of arm.com designates 40.67.248.234 as permitted sender) receiver=protection.outlook.com; client-ip=40.67.248.234; helo=nebula.arm.com; pr=C Received: from nebula.arm.com (40.67.248.234) by DB1PEPF000509E8.mail.protection.outlook.com (10.167.242.58) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.7633.15 via Frontend Transport; Tue, 28 May 2024 14:47:12 +0000 Received: from AZ-NEU-EX02.Emea.Arm.com (10.251.26.5) by AZ-NEU-EX03.Arm.com (10.251.24.31) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Tue, 28 May 2024 14:47:10 +0000 Received: from AZ-NEU-EX03.Arm.com (10.251.24.31) by AZ-NEU-EX02.Emea.Arm.com (10.251.26.5) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Tue, 28 May 2024 14:47:10 +0000 Received: from e130340.cambridge.arm.com (10.2.80.47) by mail.arm.com (10.251.24.31) with Microsoft SMTP Server id 15.1.2507.35 via Frontend Transport; Tue, 28 May 2024 14:47:10 +0000 From: To: CC: , Saurabh Jha Subject: [PATCH v7 2/4] gas, aarch64: Add AdvSIMD lut extension generated files Date: Tue, 28 May 2024 15:45:51 +0100 Message-ID: <20240528144553.2994250-2-saurabh.jha@arm.com> X-Mailer: git-send-email 2.43.2 In-Reply-To: <20240528144553.2994250-1-saurabh.jha@arm.com> References: <20240528144553.2994250-1-saurabh.jha@arm.com> MIME-Version: 1.0 Content-Type: multipart/mixed; boundary="------------2.43.2" Content-Transfer-Encoding: 8bit X-EOPAttributedMessage: 1 X-MS-TrafficTypeDiagnostic: DB1PEPF000509E8:EE_|GV1PR08MB7730:EE_|DB5PEPF00014B90:EE_|DB5PR08MB10115:EE_ X-MS-Office365-Filtering-Correlation-Id: b548e34f-617d-4857-46a2-08dc7f251614 x-checkrecipientrouted: true NoDisclaimer: true X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam-Untrusted: BCL:0;ARA:13230031|82310400017|1800799015|376005|36860700004; X-Microsoft-Antispam-Message-Info-Original: =?us-ascii?Q?UFEAtN9xpOatTWABpDhqaFm/1oz0hW+/l/rj+uPF9u4gvmP6hQX14//wsW4i?= =?us-ascii?Q?gxoODd2x045+1ouCT5CSzqPDdHGCngxgLgsEN3Lcm2rea3pOjpMkwagwuPvd?= =?us-ascii?Q?u+EC1ncyUgHUDPdGASyKrruyCSjcjq35astiOSXPwSfpjzJw0U9z4GpuCTxp?= =?us-ascii?Q?oeYa+L89Z+Hb+obKEyqQlO4gBHgNsIwGmCkyCVSf2CuMX+7THpccs1aXdTPp?= =?us-ascii?Q?ztn9X2HshtDCDGc+mHgjO+3H19YXhRKEWGU6GNAeA2RvbBhE7mNLQDSRsB8Q?= =?us-ascii?Q?pCwAZYD7E7TMg3ZG6051upc+nb1K2sBoVcrVnBexm+huaSC1hJQE23R5BYgq?= =?us-ascii?Q?Kwsr4996D6RtzUERLffW5GGjzQaRsZ2o8fnkKADfXxpS5IxDl5nvC/M/6+d7?= =?us-ascii?Q?F18DGmEh+8JDlBlWlAuz0+tRmjThwS+SB3dMAKaWbsCYbXG14ExY8ErdI9QJ?= =?us-ascii?Q?3Fhize85nep/pvuaAi+oglAsOPnnze5N70hanxxK1V95rMhoak7tSbBL77H1?= =?us-ascii?Q?qGqvxVGVUTJ+RJR257hrH6o7vN56o4Qse+BXDbyQkuNBuXkw/pK678YAOhTw?= =?us-ascii?Q?arx9yhwV/jGJ6waGYEjXTZ6+RARPiNy+twL+I2wsUbyInyHXn5nVqxRKQJ0U?= =?us-ascii?Q?b926frsMXdiiT0DrqCGhaJBbsdyZhBQeISBU1ukk3EQzTGX5W/98/ib9ioir?= =?us-ascii?Q?WVeGBIXJ+McdHNGFPfHh2CSMn+tpMVZQBRKlJp69zXbQ4rJp//S/Qpe9I15N?= =?us-ascii?Q?H4pgg7zBJuM6JZ8bkeCsNiJ0yxWswIN/RSa86lA6d2aC3CD4Kkpxw37Q19YI?= =?us-ascii?Q?UvIO0hm1U5McK9Xlw2xkN7vr2eLIDmwGBbx4ik/R2nF56pcxdx57QcXGhCiC?= =?us-ascii?Q?AQMYXEB7aQeS9h4IyU3MsczIqBcbgWBXZZbvnL/+KLOWyia+vmKM65VcpGvW?= =?us-ascii?Q?BqlndU9q0f4aaooS6W95A2yrCpSpr0nHQFEQERWwQB8AF7h3UhCcUfADQtkQ?= =?us-ascii?Q?6Cqv/Y1zP9A0dtUeJdNuGTtIQkAU0DKUOjKuo3ZANmanKQ19lDJsI8SUZTz1?= =?us-ascii?Q?NOLU/3D5SHVSnMyFCdxzVrBlktWpOhx3tmwHC/JntaJYjn+gJ2jIGNeXliz2?= =?us-ascii?Q?e4Kxw5LFjbbK6+OOc8uRLuuMgOLZrdVGgRUgOI5GzHSGpVAAbPCVJus7sunD?= =?us-ascii?Q?p9TYsn4PNlYH55f6rnXjGlfF2lSDwCys8tBmT6zvHslZoV4rMdLGwP6BcWKL?= =?us-ascii?Q?xfnIMOzfInPihh2l9h3MHwXorwG1w285SnBtEfQ/kNTg+q9A3/AUSRzTODC4?= =?us-ascii?Q?/qOVIu5enrUpqZhXsgiohATr0QorzRsDbY5v6XD1jpkt+lGrVf0V96ZLO1hh?= =?us-ascii?Q?Ke9roXaOKWEZAusJ9Meu7G5tffuG?= X-Forefront-Antispam-Report-Untrusted: CIP:40.67.248.234;CTRY:IE;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:nebula.arm.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230031)(82310400017)(1800799015)(376005)(36860700004);DIR:OUT;SFP:1101; X-MS-Exchange-Transport-CrossTenantHeadersStamped: GV1PR08MB7730 X-MS-Exchange-Transport-CrossTenantHeadersStripped: DB5PEPF00014B90.eurprd02.prod.outlook.com X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id-Prvs: 445b2154-4b07-49f4-ff6c-08dc7f250f75 X-Microsoft-Antispam: BCL:0;ARA:13230031|36860700004|376005|82310400017|1800799015|35042699013; X-Microsoft-Antispam-Message-Info: =?utf-8?B?cDFiOFQ1eFZJN1R1SVUyVjVpVnZGaDlaMkMwbDFSRUVoZHVKSklPZmxVb2xs?= =?utf-8?B?cUpTRjF4eVpvc0Vhcmt2SVhMc1QxYmt2bWtvOFlIY2U5LzZGTmsxYjdBRTZH?= =?utf-8?B?WFVPeHlHaE5mbnUzUGtNQThOam1wZms4aWpNOHJTUnM4UDJCelpSTktIMTJ4?= =?utf-8?B?QjNKV2ZSdUk3aUh4UVF2a085MU52eDVoeVE2Y1IxYTJtODBraEZMQzZDYUZz?= =?utf-8?B?QTZQUlZtR1doeUtnMUhUSUZxYTR1SzRnSXEwVVMrNUFuOTJkaVpuYkUzL2ph?= =?utf-8?B?N3VrZHhaWDBlR2dUWmVBaWRySVR1M3NURzBaSXhCU0ZZTFoxTGI1bml5MXVp?= =?utf-8?B?RjJlNEtWVExyMDBRSS9wOWtNdTM3b0xCd0lFOU5Ub0FHNGtiYW1BS3VpNlBz?= =?utf-8?B?OXd2V1NMSHVVMzNaaHR3OVdqak82WFlvbXpQaFBRN2F5K2EwOTZYRTJLMjN4?= =?utf-8?B?SlRMNG9RSmdvZnNYanVHc08zQnczV3VZYkl4MGlldm5qa212SG11QXgvOE1G?= =?utf-8?B?MmpkWXl1Mk8rU1FBWHlGSUp5OVcwd1pDZFo4QnRUeDByZ1JaUUVueVJBQ1Ex?= =?utf-8?B?TzhJS0hPSWpEcW9NNFovMWVUaU5GM1ZhRkd0VlR3cU1ocTI5UU1wN3EwRU05?= =?utf-8?B?UXh0S1RjWG03N3I2ZXFCUDY4OVAzV1d6M0tBa3RwWDFiRTBoT004djBWWjRL?= =?utf-8?B?RGRld2NFY2tUZGFObkl1OGdiUlNkK09MdjB2MlQvaC9ZaExOV0RYWEZSMHl1?= =?utf-8?B?SXBpYjdxckQrVWZqd3dKRmpxZHc1aVpLdUNJSll5ZDFoR014VXZVb0tSVHRv?= =?utf-8?B?dUpDVTdPTmwyNWpGYkllaFcrbHQrUTdUblA2L09ZRi9MdGY5b3dra2wvVmdV?= =?utf-8?B?dlJxWHVIVXZ1by80Q050eXFCWFMrZFRYWkZhc096bkZjVlZzanZMcnRwZXBH?= =?utf-8?B?a2RKdHNFME8rOHRxTithaGFSeDQzdWxxMVJBNG9FQm9SWjFwYW9GKzRPTkx5?= =?utf-8?B?MGp0SWRVaStuMTFLcGt3UDhoZmNNR1RmVTUxSlFBSHJUYmNsRnZFbnMrQklh?= =?utf-8?B?MVFiUzU0NERWRWpLbkN3RmVPMXYybldvNUl5bW9XcS9ObVJrbnpRelFwL2pH?= =?utf-8?B?REx6Y1NZaGFYL2xlUEFMWWtvSkRJVCs5RFdNVmNNTlErS1JiSmlyUktXTDZB?= =?utf-8?B?RWlqVFI2TWhXUGtjeHpaRDFhdXk5RDY3Z1QySm13akNRTjh6ZXliUkNnY2dN?= =?utf-8?B?czR1RS9hNTBOQ1NJOGwycDNlR0o3NzlpcVdqbmNWS0NMVnpYREttQklkemhQ?= =?utf-8?B?ZklYaVUrNFd5c2daNUJMZ3hjVDVnWDhqdGpnb1hwMk9NS3JQMjMycytndkJJ?= =?utf-8?B?QnJlOVUzOEdJaW4wY0hGZTdjRVZJU2ZHMEp6RFM3ZVZhd0p3Z3VNSStvZ0N6?= =?utf-8?B?S3MyekpjRXR2bHFQMDJYeUVwVWFkOXVSaG9pUjBsTjljeURaTzRxZTliVmpk?= =?utf-8?B?c0Q1OUkrVVUreU5iQ0ZkVE9IZ3p1OU9GT0tpTFczWlhiQ2wvdU90eVJvbTRU?= =?utf-8?B?NDlqUGtMV2xyT1FSUUwxVnQ5VktxQnhRSG9GemNiSTRUUWNUVWN4MlZSQVJX?= =?utf-8?B?ZTFXeXlNaG5oZHFqLysxMVhmSnpZZUFlN25XN014WDRTRzV4YU9NT2tQNmF1?= =?utf-8?B?OTN6Q1ZxeGJ6ck1QN0lub2V5eEFRZm1takthRWR2WVlCY1dLWU5lSmlQanU1?= =?utf-8?B?TjVKYkNzTmVzT1MwcU9TS0Q3bFBaajc2NnllRzh3QmM0WG8xUXB4dTFTSjNo?= =?utf-8?B?NjVzS2JaY3p1ZXFidXA5ZlJKeG9YbXJCZ2FzTjVNVjZwd2x6ZlJObmIzWkpv?= =?utf-8?Q?jzCtB6jnv3sM/?= X-Forefront-Antispam-Report: CIP:63.35.35.123;CTRY:IE;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:64aa7808-outbound-1.mta.getcheckrecipient.com;PTR:ec2-63-35-35-123.eu-west-1.compute.amazonaws.com;CAT:NONE;SFS:(13230031)(36860700004)(376005)(82310400017)(1800799015)(35042699013);DIR:OUT;SFP:1101; X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 28 May 2024 14:47:24.0712 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: b548e34f-617d-4857-46a2-08dc7f251614 X-MS-Exchange-CrossTenant-Id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=f34e5979-57d9-4aaa-ad4d-b122a662184d;Ip=[63.35.35.123];Helo=[64aa7808-outbound-1.mta.getcheckrecipient.com] X-MS-Exchange-CrossTenant-AuthSource: DB5PEPF00014B90.eurprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DB5PR08MB10115 X-Spam-Status: No, score=-11.7 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FORGED_SPF_HELO,GIT_PATCH_0,KAM_LOTSOFHASH,SPF_HELO_PASS,SPF_NONE,TXREP,T_SCC_BODY_TEXT_LINE,UNPARSEABLE_RELAY autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: --------------2.43.2 Content-Type: text/plain; charset="UTF-8"; format=fixed Content-Transfer-Encoding: 8bit Adds generated files for the previous patch in the series. No other changes. --- opcodes/aarch64-asm-2.c | 357 +++++++++++++++++----------------- opcodes/aarch64-dis-2.c | 419 ++++++++++++++++++++++------------------ opcodes/aarch64-opc-2.c | 4 + 3 files changed, 419 insertions(+), 361 deletions(-) --------------2.43.2 Content-Type: text/x-patch; name="v7-0002-gas-aarch64-Add-AdvSIMD-lut-extension-generated-f.patch" Content-Transfer-Encoding: 8bit Content-Disposition: attachment; filename="v7-0002-gas-aarch64-Add-AdvSIMD-lut-extension-generated-f.patch" diff --git a/opcodes/aarch64-asm-2.c b/opcodes/aarch64-asm-2.c index 53eb8c67204..77dcc9a9eac 100644 --- a/opcodes/aarch64-asm-2.c +++ b/opcodes/aarch64-asm-2.c @@ -650,12 +650,8 @@ aarch64_insert_operand (const aarch64_operand *self, case 32: case 33: case 34: - case 117: - case 118: - case 176: - case 177: - case 178: - case 179: + case 121: + case 122: case 180: case 181: case 182: @@ -666,30 +662,34 @@ aarch64_insert_operand (const aarch64_operand *self, case 187: case 188: case 189: - case 204: - case 205: - case 206: - case 207: - case 216: - case 217: - case 218: - case 219: + case 190: + case 191: + case 192: + case 193: + case 208: + case 209: + case 210: + case 211: case 220: - case 228: + case 221: + case 222: + case 223: + case 224: case 232: case 236: - case 243: - case 244: - case 251: - case 252: - case 253: - case 254: + case 240: + case 247: + case 248: + case 255: + case 256: + case 257: + case 258: return aarch64_ins_regno (self, info, code, inst, errors); case 6: - case 114: - case 115: - case 286: - case 288: + case 118: + case 119: + case 290: + case 292: return aarch64_ins_none (self, info, code, inst, errors); case 17: return aarch64_ins_reg_extended (self, info, code, inst, errors); @@ -703,24 +703,41 @@ aarch64_insert_operand (const aarch64_operand *self, case 36: case 37: case 38: - case 290: + case 294: return aarch64_ins_reglane (self, info, code, inst, errors); case 39: - return aarch64_ins_reglist (self, info, code, inst, errors); case 40: - return aarch64_ins_ldst_reglist (self, info, code, inst, errors); case 41: - return aarch64_ins_ldst_reglist_r (self, info, code, inst, errors); + case 259: + case 260: + case 275: + case 276: + case 277: + case 278: + case 279: + case 280: + case 281: + case 282: + case 283: + case 284: + case 285: + case 286: + case 287: + return aarch64_ins_simple_index (self, info, code, inst, errors); case 42: - return aarch64_ins_ldst_elemlist (self, info, code, inst, errors); + return aarch64_ins_reglist (self, info, code, inst, errors); case 43: + return aarch64_ins_ldst_reglist (self, info, code, inst, errors); case 44: + return aarch64_ins_ldst_reglist_r (self, info, code, inst, errors); case 45: + return aarch64_ins_lut_reglist (self, info, code, inst, errors); case 46: - case 56: - case 57: - case 58: - case 59: + return aarch64_ins_ldst_elemlist (self, info, code, inst, errors); + case 47: + case 48: + case 49: + case 50: case 60: case 61: case 62: @@ -734,120 +751,120 @@ aarch64_insert_operand (const aarch64_operand *self, case 70: case 71: case 72: - case 84: - case 85: - case 86: - case 87: - case 113: - case 173: - case 175: - case 196: - case 197: - case 198: - case 199: + case 73: + case 74: + case 75: + case 76: + case 88: + case 89: + case 90: + case 91: + case 117: + case 177: + case 179: case 200: case 201: case 202: case 203: - case 257: - case 284: - case 285: - case 287: + case 204: + case 205: + case 206: + case 207: + case 261: + case 288: case 289: - case 294: - case 295: + case 291: + case 293: + case 298: + case 299: return aarch64_ins_imm (self, info, code, inst, errors); - case 47: - case 48: - return aarch64_ins_advsimd_imm_shift (self, info, code, inst, errors); - case 49: - case 50: case 51: - return aarch64_ins_advsimd_imm_modified (self, info, code, inst, errors); + case 52: + return aarch64_ins_advsimd_imm_shift (self, info, code, inst, errors); + case 53: + case 54: case 55: - case 163: + return aarch64_ins_advsimd_imm_modified (self, info, code, inst, errors); + case 59: + case 167: return aarch64_ins_fpimm (self, info, code, inst, errors); - case 73: - case 171: + case 77: + case 175: return aarch64_ins_limm (self, info, code, inst, errors); - case 74: + case 78: return aarch64_ins_aimm (self, info, code, inst, errors); - case 75: + case 79: return aarch64_ins_imm_half (self, info, code, inst, errors); - case 76: + case 80: return aarch64_ins_fbits (self, info, code, inst, errors); - case 78: - case 79: - case 168: + case 82: + case 83: + case 172: return aarch64_ins_imm_rotate2 (self, info, code, inst, errors); - case 80: - case 167: - case 169: + case 84: + case 171: + case 173: return aarch64_ins_imm_rotate1 (self, info, code, inst, errors); - case 81: - case 82: + case 85: + case 86: return aarch64_ins_cond (self, info, code, inst, errors); - case 88: - case 97: + case 92: + case 101: return aarch64_ins_addr_simple (self, info, code, inst, errors); - case 89: + case 93: return aarch64_ins_addr_regoff (self, info, code, inst, errors); - case 90: - case 91: - case 92: case 94: + case 95: case 96: + case 98: + case 100: return aarch64_ins_addr_simm (self, info, code, inst, errors); - case 93: + case 97: return aarch64_ins_addr_simm10 (self, info, code, inst, errors); - case 95: - return aarch64_ins_addr_uimm12 (self, info, code, inst, errors); - case 98: - return aarch64_ins_addr_offset (self, info, code, inst, errors); case 99: - return aarch64_ins_simd_addr_post (self, info, code, inst, errors); - case 100: - case 101: - return aarch64_ins_sysreg (self, info, code, inst, errors); + return aarch64_ins_addr_uimm12 (self, info, code, inst, errors); case 102: - return aarch64_ins_pstatefield (self, info, code, inst, errors); + return aarch64_ins_addr_offset (self, info, code, inst, errors); case 103: + return aarch64_ins_simd_addr_post (self, info, code, inst, errors); case 104: case 105: + return aarch64_ins_sysreg (self, info, code, inst, errors); case 106: + return aarch64_ins_pstatefield (self, info, code, inst, errors); case 107: case 108: - return aarch64_ins_sysins_op (self, info, code, inst, errors); case 109: + case 110: case 111: + case 112: + return aarch64_ins_sysins_op (self, info, code, inst, errors); + case 113: + case 115: return aarch64_ins_barrier (self, info, code, inst, errors); - case 110: + case 114: return aarch64_ins_barrier_dsb_nxs (self, info, code, inst, errors); - case 112: - return aarch64_ins_prfop (self, info, code, inst, errors); case 116: - return aarch64_ins_hint (self, info, code, inst, errors); - case 119: + return aarch64_ins_prfop (self, info, code, inst, errors); case 120: - return aarch64_ins_sve_addr_ri_s4 (self, info, code, inst, errors); - case 121: - case 122: + return aarch64_ins_hint (self, info, code, inst, errors); case 123: case 124: - return aarch64_ins_sve_addr_ri_s4xvl (self, info, code, inst, errors); + return aarch64_ins_sve_addr_ri_s4 (self, info, code, inst, errors); case 125: - return aarch64_ins_sve_addr_ri_s6xvl (self, info, code, inst, errors); case 126: - return aarch64_ins_sve_addr_ri_s9xvl (self, info, code, inst, errors); case 127: case 128: + return aarch64_ins_sve_addr_ri_s4xvl (self, info, code, inst, errors); case 129: + return aarch64_ins_sve_addr_ri_s6xvl (self, info, code, inst, errors); case 130: - return aarch64_ins_sve_addr_ri_u6 (self, info, code, inst, errors); + return aarch64_ins_sve_addr_ri_s9xvl (self, info, code, inst, errors); case 131: case 132: case 133: case 134: + return aarch64_ins_sve_addr_ri_u6 (self, info, code, inst, errors); case 135: case 136: case 137: @@ -859,141 +876,129 @@ aarch64_insert_operand (const aarch64_operand *self, case 143: case 144: case 145: - return aarch64_ins_sve_addr_rr_lsl (self, info, code, inst, errors); case 146: case 147: case 148: case 149: + return aarch64_ins_sve_addr_rr_lsl (self, info, code, inst, errors); case 150: case 151: case 152: case 153: - return aarch64_ins_sve_addr_rz_xtw (self, info, code, inst, errors); case 154: case 155: case 156: case 157: - return aarch64_ins_sve_addr_zi_u5 (self, info, code, inst, errors); + return aarch64_ins_sve_addr_rz_xtw (self, info, code, inst, errors); case 158: - return aarch64_ins_sve_addr_zz_lsl (self, info, code, inst, errors); case 159: - return aarch64_ins_sve_addr_zz_sxtw (self, info, code, inst, errors); case 160: - return aarch64_ins_sve_addr_zz_uxtw (self, info, code, inst, errors); case 161: - return aarch64_ins_sve_aimm (self, info, code, inst, errors); + return aarch64_ins_sve_addr_zi_u5 (self, info, code, inst, errors); case 162: - return aarch64_ins_sve_asimm (self, info, code, inst, errors); + return aarch64_ins_sve_addr_zz_lsl (self, info, code, inst, errors); + case 163: + return aarch64_ins_sve_addr_zz_sxtw (self, info, code, inst, errors); case 164: - return aarch64_ins_sve_float_half_one (self, info, code, inst, errors); + return aarch64_ins_sve_addr_zz_uxtw (self, info, code, inst, errors); case 165: - return aarch64_ins_sve_float_half_two (self, info, code, inst, errors); + return aarch64_ins_sve_aimm (self, info, code, inst, errors); case 166: - return aarch64_ins_sve_float_zero_one (self, info, code, inst, errors); + return aarch64_ins_sve_asimm (self, info, code, inst, errors); + case 168: + return aarch64_ins_sve_float_half_one (self, info, code, inst, errors); + case 169: + return aarch64_ins_sve_float_half_two (self, info, code, inst, errors); case 170: + return aarch64_ins_sve_float_zero_one (self, info, code, inst, errors); + case 174: return aarch64_ins_inv_limm (self, info, code, inst, errors); - case 172: + case 176: return aarch64_ins_sve_limm_mov (self, info, code, inst, errors); - case 174: + case 178: return aarch64_ins_sve_scale (self, info, code, inst, errors); - case 190: - case 191: - case 192: - return aarch64_ins_sve_shlimm (self, info, code, inst, errors); - case 193: case 194: case 195: - case 270: + case 196: + return aarch64_ins_sve_shlimm (self, info, code, inst, errors); + case 197: + case 198: + case 199: + case 274: return aarch64_ins_sve_shrimm (self, info, code, inst, errors); - case 208: - case 209: - case 210: - case 211: - return aarch64_ins_sme_za_vrs1 (self, info, code, inst, errors); case 212: case 213: case 214: case 215: + return aarch64_ins_sme_za_vrs1 (self, info, code, inst, errors); + case 216: + case 217: + case 218: + case 219: return aarch64_ins_sme_za_vrs2 (self, info, code, inst, errors); - case 221: - case 222: - case 223: - case 224: case 225: case 226: case 227: - return aarch64_ins_sve_quad_index (self, info, code, inst, errors); + case 228: case 229: - return aarch64_ins_sve_index_imm (self, info, code, inst, errors); case 230: - return aarch64_ins_sve_index (self, info, code, inst, errors); case 231: + return aarch64_ins_sve_quad_index (self, info, code, inst, errors); case 233: - case 250: - case 296: - case 297: - case 298: - return aarch64_ins_sve_reglist (self, info, code, inst, errors); + return aarch64_ins_sve_index_imm (self, info, code, inst, errors); case 234: + return aarch64_ins_sve_index (self, info, code, inst, errors); case 235: case 237: + case 254: + case 300: + case 301: + case 302: + return aarch64_ins_sve_reglist (self, info, code, inst, errors); case 238: case 239: - case 240: - case 249: - return aarch64_ins_sve_aligned_reglist (self, info, code, inst, errors); case 241: case 242: - return aarch64_ins_sve_strided_reglist (self, info, code, inst, errors); + case 243: + case 244: + case 253: + return aarch64_ins_sve_aligned_reglist (self, info, code, inst, errors); case 245: - case 247: - case 258: - return aarch64_ins_sme_za_hv_tiles (self, info, code, inst, errors); case 246: - case 248: - return aarch64_ins_sme_za_hv_tiles_range (self, info, code, inst, errors); - case 255: - case 256: - case 271: - case 272: - case 273: - case 274: - case 275: - case 276: - case 277: - case 278: - case 279: - case 280: - case 281: - case 282: - case 283: - return aarch64_ins_simple_index (self, info, code, inst, errors); - case 259: - case 260: - case 261: + return aarch64_ins_sve_strided_reglist (self, info, code, inst, errors); + case 249: + case 251: case 262: + return aarch64_ins_sme_za_hv_tiles (self, info, code, inst, errors); + case 250: + case 252: + return aarch64_ins_sme_za_hv_tiles_range (self, info, code, inst, errors); case 263: case 264: case 265: - return aarch64_ins_sme_za_array (self, info, code, inst, errors); case 266: - return aarch64_ins_sme_addr_ri_u4xvl (self, info, code, inst, errors); case 267: - return aarch64_ins_sme_sm_za (self, info, code, inst, errors); case 268: - return aarch64_ins_sme_pred_reg_with_index (self, info, code, inst, errors); case 269: + return aarch64_ins_sme_za_array (self, info, code, inst, errors); + case 270: + return aarch64_ins_sme_addr_ri_u4xvl (self, info, code, inst, errors); + case 271: + return aarch64_ins_sme_sm_za (self, info, code, inst, errors); + case 272: + return aarch64_ins_sme_pred_reg_with_index (self, info, code, inst, errors); + case 273: return aarch64_ins_plain_shrimm (self, info, code, inst, errors); - case 291: - case 292: - case 293: + case 295: + case 296: + case 297: return aarch64_ins_x0_to_x30 (self, info, code, inst, errors); - case 299: - case 300: - case 301: - case 302: - return aarch64_ins_rcpc3_addr_opt_offset (self, info, code, inst, errors); case 303: + case 304: + case 305: + case 306: + return aarch64_ins_rcpc3_addr_opt_offset (self, info, code, inst, errors); + case 307: return aarch64_ins_rcpc3_addr_offset (self, info, code, inst, errors); default: assert (0); abort (); } diff --git a/opcodes/aarch64-dis-2.c b/opcodes/aarch64-dis-2.c index 36fd047ae67..ef51a9b88e2 100644 --- a/opcodes/aarch64-dis-2.c +++ b/opcodes/aarch64-dis-2.c @@ -25755,21 +25755,65 @@ aarch64_opcode_lookup_1 (uint32_t word) { if (((word >> 11) & 0x1) == 0) { - if (((word >> 12) & 0x1) == 0) + if (((word >> 22) & 0x1) == 0) { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - 0x001110xx0xxxxxxxx000xxxxxxxxxx - tbl. */ - return 420; + if (((word >> 12) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + 0x001110x00xxxxxxxx000xxxxxxxxxx + tbl. */ + return 420; + } + else + { + if (((word >> 23) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + 0x001110000xxxxxxxx100xxxxxxxxxx + tbx. */ + return 421; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + 0x001110100xxxxxxxx100xxxxxxxxxx + luti2. */ + return 3384; + } + } } else { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - 0x001110xx0xxxxxxxx100xxxxxxxxxx - tbx. */ - return 421; + if (((word >> 23) & 0x1) == 0) + { + if (((word >> 12) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + 0x001110010xxxxxxxx000xxxxxxxxxx + luti4. */ + return 3386; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + 0x001110010xxxxxxxx100xxxxxxxxxx + luti4. */ + return 3387; + } + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + 0x001110110xxxxxxxxx00xxxxxxxxxx + luti2. */ + return 3385; + } } } else @@ -33548,12 +33592,8 @@ aarch64_extract_operand (const aarch64_operand *self, case 32: case 33: case 34: - case 117: - case 118: - case 176: - case 177: - case 178: - case 179: + case 121: + case 122: case 180: case 181: case 182: @@ -33564,30 +33604,34 @@ aarch64_extract_operand (const aarch64_operand *self, case 187: case 188: case 189: - case 204: - case 205: - case 206: - case 207: - case 216: - case 217: - case 218: - case 219: + case 190: + case 191: + case 192: + case 193: + case 208: + case 209: + case 210: + case 211: case 220: - case 228: + case 221: + case 222: + case 223: + case 224: case 232: case 236: - case 243: - case 244: - case 251: - case 252: - case 253: - case 254: + case 240: + case 247: + case 248: + case 255: + case 256: + case 257: + case 258: return aarch64_ext_regno (self, info, code, inst, errors); case 6: - case 114: - case 115: - case 286: - case 288: + case 118: + case 119: + case 290: + case 292: return aarch64_ext_none (self, info, code, inst, errors); case 11: return aarch64_ext_regrt_sysins (self, info, code, inst, errors); @@ -33606,24 +33650,41 @@ aarch64_extract_operand (const aarch64_operand *self, case 36: case 37: case 38: - case 290: + case 294: return aarch64_ext_reglane (self, info, code, inst, errors); case 39: - return aarch64_ext_reglist (self, info, code, inst, errors); case 40: - return aarch64_ext_ldst_reglist (self, info, code, inst, errors); case 41: - return aarch64_ext_ldst_reglist_r (self, info, code, inst, errors); + case 259: + case 260: + case 275: + case 276: + case 277: + case 278: + case 279: + case 280: + case 281: + case 282: + case 283: + case 284: + case 285: + case 286: + case 287: + return aarch64_ext_simple_index (self, info, code, inst, errors); case 42: - return aarch64_ext_ldst_elemlist (self, info, code, inst, errors); + return aarch64_ext_reglist (self, info, code, inst, errors); case 43: + return aarch64_ext_ldst_reglist (self, info, code, inst, errors); case 44: + return aarch64_ext_ldst_reglist_r (self, info, code, inst, errors); case 45: + return aarch64_ext_lut_reglist (self, info, code, inst, errors); case 46: - case 56: - case 57: - case 58: - case 59: + return aarch64_ext_ldst_elemlist (self, info, code, inst, errors); + case 47: + case 48: + case 49: + case 50: case 60: case 61: case 62: @@ -33637,123 +33698,123 @@ aarch64_extract_operand (const aarch64_operand *self, case 70: case 71: case 72: - case 83: - case 84: - case 85: - case 86: + case 73: + case 74: + case 75: + case 76: case 87: - case 113: - case 173: - case 175: - case 196: - case 197: - case 198: - case 199: + case 88: + case 89: + case 90: + case 91: + case 117: + case 177: + case 179: case 200: case 201: case 202: case 203: - case 257: - case 284: - case 285: - case 287: + case 204: + case 205: + case 206: + case 207: + case 261: + case 288: case 289: - case 294: - case 295: + case 291: + case 293: + case 298: + case 299: return aarch64_ext_imm (self, info, code, inst, errors); - case 47: - case 48: - return aarch64_ext_advsimd_imm_shift (self, info, code, inst, errors); - case 49: - case 50: case 51: - return aarch64_ext_advsimd_imm_modified (self, info, code, inst, errors); case 52: - return aarch64_ext_shll_imm (self, info, code, inst, errors); + return aarch64_ext_advsimd_imm_shift (self, info, code, inst, errors); + case 53: + case 54: case 55: - case 163: + return aarch64_ext_advsimd_imm_modified (self, info, code, inst, errors); + case 56: + return aarch64_ext_shll_imm (self, info, code, inst, errors); + case 59: + case 167: return aarch64_ext_fpimm (self, info, code, inst, errors); - case 73: - case 171: + case 77: + case 175: return aarch64_ext_limm (self, info, code, inst, errors); - case 74: + case 78: return aarch64_ext_aimm (self, info, code, inst, errors); - case 75: + case 79: return aarch64_ext_imm_half (self, info, code, inst, errors); - case 76: + case 80: return aarch64_ext_fbits (self, info, code, inst, errors); - case 78: - case 79: - case 168: + case 82: + case 83: + case 172: return aarch64_ext_imm_rotate2 (self, info, code, inst, errors); - case 80: - case 167: - case 169: + case 84: + case 171: + case 173: return aarch64_ext_imm_rotate1 (self, info, code, inst, errors); - case 81: - case 82: + case 85: + case 86: return aarch64_ext_cond (self, info, code, inst, errors); - case 88: - case 97: + case 92: + case 101: return aarch64_ext_addr_simple (self, info, code, inst, errors); - case 89: + case 93: return aarch64_ext_addr_regoff (self, info, code, inst, errors); - case 90: - case 91: - case 92: case 94: + case 95: case 96: + case 98: + case 100: return aarch64_ext_addr_simm (self, info, code, inst, errors); - case 93: + case 97: return aarch64_ext_addr_simm10 (self, info, code, inst, errors); - case 95: - return aarch64_ext_addr_uimm12 (self, info, code, inst, errors); - case 98: - return aarch64_ext_addr_offset (self, info, code, inst, errors); case 99: - return aarch64_ext_simd_addr_post (self, info, code, inst, errors); - case 100: - case 101: - return aarch64_ext_sysreg (self, info, code, inst, errors); + return aarch64_ext_addr_uimm12 (self, info, code, inst, errors); case 102: - return aarch64_ext_pstatefield (self, info, code, inst, errors); + return aarch64_ext_addr_offset (self, info, code, inst, errors); case 103: + return aarch64_ext_simd_addr_post (self, info, code, inst, errors); case 104: case 105: + return aarch64_ext_sysreg (self, info, code, inst, errors); case 106: + return aarch64_ext_pstatefield (self, info, code, inst, errors); case 107: case 108: - return aarch64_ext_sysins_op (self, info, code, inst, errors); case 109: + case 110: case 111: + case 112: + return aarch64_ext_sysins_op (self, info, code, inst, errors); + case 113: + case 115: return aarch64_ext_barrier (self, info, code, inst, errors); - case 110: + case 114: return aarch64_ext_barrier_dsb_nxs (self, info, code, inst, errors); - case 112: - return aarch64_ext_prfop (self, info, code, inst, errors); case 116: - return aarch64_ext_hint (self, info, code, inst, errors); - case 119: + return aarch64_ext_prfop (self, info, code, inst, errors); case 120: - return aarch64_ext_sve_addr_ri_s4 (self, info, code, inst, errors); - case 121: - case 122: + return aarch64_ext_hint (self, info, code, inst, errors); case 123: case 124: - return aarch64_ext_sve_addr_ri_s4xvl (self, info, code, inst, errors); + return aarch64_ext_sve_addr_ri_s4 (self, info, code, inst, errors); case 125: - return aarch64_ext_sve_addr_ri_s6xvl (self, info, code, inst, errors); case 126: - return aarch64_ext_sve_addr_ri_s9xvl (self, info, code, inst, errors); case 127: case 128: + return aarch64_ext_sve_addr_ri_s4xvl (self, info, code, inst, errors); case 129: + return aarch64_ext_sve_addr_ri_s6xvl (self, info, code, inst, errors); case 130: - return aarch64_ext_sve_addr_ri_u6 (self, info, code, inst, errors); + return aarch64_ext_sve_addr_ri_s9xvl (self, info, code, inst, errors); case 131: case 132: case 133: case 134: + return aarch64_ext_sve_addr_ri_u6 (self, info, code, inst, errors); case 135: case 136: case 137: @@ -33765,142 +33826,130 @@ aarch64_extract_operand (const aarch64_operand *self, case 143: case 144: case 145: - return aarch64_ext_sve_addr_rr_lsl (self, info, code, inst, errors); case 146: case 147: case 148: case 149: + return aarch64_ext_sve_addr_rr_lsl (self, info, code, inst, errors); case 150: case 151: case 152: case 153: - return aarch64_ext_sve_addr_rz_xtw (self, info, code, inst, errors); case 154: case 155: case 156: case 157: - return aarch64_ext_sve_addr_zi_u5 (self, info, code, inst, errors); + return aarch64_ext_sve_addr_rz_xtw (self, info, code, inst, errors); case 158: - return aarch64_ext_sve_addr_zz_lsl (self, info, code, inst, errors); case 159: - return aarch64_ext_sve_addr_zz_sxtw (self, info, code, inst, errors); case 160: - return aarch64_ext_sve_addr_zz_uxtw (self, info, code, inst, errors); case 161: - return aarch64_ext_sve_aimm (self, info, code, inst, errors); + return aarch64_ext_sve_addr_zi_u5 (self, info, code, inst, errors); case 162: - return aarch64_ext_sve_asimm (self, info, code, inst, errors); + return aarch64_ext_sve_addr_zz_lsl (self, info, code, inst, errors); + case 163: + return aarch64_ext_sve_addr_zz_sxtw (self, info, code, inst, errors); case 164: - return aarch64_ext_sve_float_half_one (self, info, code, inst, errors); + return aarch64_ext_sve_addr_zz_uxtw (self, info, code, inst, errors); case 165: - return aarch64_ext_sve_float_half_two (self, info, code, inst, errors); + return aarch64_ext_sve_aimm (self, info, code, inst, errors); case 166: - return aarch64_ext_sve_float_zero_one (self, info, code, inst, errors); + return aarch64_ext_sve_asimm (self, info, code, inst, errors); + case 168: + return aarch64_ext_sve_float_half_one (self, info, code, inst, errors); + case 169: + return aarch64_ext_sve_float_half_two (self, info, code, inst, errors); case 170: + return aarch64_ext_sve_float_zero_one (self, info, code, inst, errors); + case 174: return aarch64_ext_inv_limm (self, info, code, inst, errors); - case 172: + case 176: return aarch64_ext_sve_limm_mov (self, info, code, inst, errors); - case 174: + case 178: return aarch64_ext_sve_scale (self, info, code, inst, errors); - case 190: - case 191: - case 192: - return aarch64_ext_sve_shlimm (self, info, code, inst, errors); - case 193: case 194: case 195: - case 270: + case 196: + return aarch64_ext_sve_shlimm (self, info, code, inst, errors); + case 197: + case 198: + case 199: + case 274: return aarch64_ext_sve_shrimm (self, info, code, inst, errors); - case 208: - case 209: - case 210: - case 211: - return aarch64_ext_sme_za_vrs1 (self, info, code, inst, errors); case 212: case 213: case 214: case 215: + return aarch64_ext_sme_za_vrs1 (self, info, code, inst, errors); + case 216: + case 217: + case 218: + case 219: return aarch64_ext_sme_za_vrs2 (self, info, code, inst, errors); - case 221: - case 222: - case 223: - case 224: case 225: case 226: case 227: - return aarch64_ext_sve_quad_index (self, info, code, inst, errors); + case 228: case 229: - return aarch64_ext_sve_index_imm (self, info, code, inst, errors); case 230: - return aarch64_ext_sve_index (self, info, code, inst, errors); case 231: + return aarch64_ext_sve_quad_index (self, info, code, inst, errors); case 233: - case 250: - return aarch64_ext_sve_reglist (self, info, code, inst, errors); + return aarch64_ext_sve_index_imm (self, info, code, inst, errors); case 234: + return aarch64_ext_sve_index (self, info, code, inst, errors); case 235: case 237: + case 254: + return aarch64_ext_sve_reglist (self, info, code, inst, errors); case 238: case 239: - case 240: - case 249: - return aarch64_ext_sve_aligned_reglist (self, info, code, inst, errors); case 241: case 242: - return aarch64_ext_sve_strided_reglist (self, info, code, inst, errors); + case 243: + case 244: + case 253: + return aarch64_ext_sve_aligned_reglist (self, info, code, inst, errors); case 245: - case 247: - case 258: - return aarch64_ext_sme_za_hv_tiles (self, info, code, inst, errors); case 246: - case 248: - return aarch64_ext_sme_za_hv_tiles_range (self, info, code, inst, errors); - case 255: - case 256: - case 271: - case 272: - case 273: - case 274: - case 275: - case 276: - case 277: - case 278: - case 279: - case 280: - case 281: - case 282: - case 283: - return aarch64_ext_simple_index (self, info, code, inst, errors); - case 259: - case 260: - case 261: + return aarch64_ext_sve_strided_reglist (self, info, code, inst, errors); + case 249: + case 251: case 262: + return aarch64_ext_sme_za_hv_tiles (self, info, code, inst, errors); + case 250: + case 252: + return aarch64_ext_sme_za_hv_tiles_range (self, info, code, inst, errors); case 263: case 264: case 265: - return aarch64_ext_sme_za_array (self, info, code, inst, errors); case 266: - return aarch64_ext_sme_addr_ri_u4xvl (self, info, code, inst, errors); case 267: - return aarch64_ext_sme_sm_za (self, info, code, inst, errors); case 268: - return aarch64_ext_sme_pred_reg_with_index (self, info, code, inst, errors); case 269: + return aarch64_ext_sme_za_array (self, info, code, inst, errors); + case 270: + return aarch64_ext_sme_addr_ri_u4xvl (self, info, code, inst, errors); + case 271: + return aarch64_ext_sme_sm_za (self, info, code, inst, errors); + case 272: + return aarch64_ext_sme_pred_reg_with_index (self, info, code, inst, errors); + case 273: return aarch64_ext_plain_shrimm (self, info, code, inst, errors); - case 291: - case 292: - case 293: - return aarch64_ext_x0_to_x30 (self, info, code, inst, errors); + case 295: case 296: case 297: - case 298: - return aarch64_ext_sve_reglist_zt (self, info, code, inst, errors); - case 299: + return aarch64_ext_x0_to_x30 (self, info, code, inst, errors); case 300: case 301: case 302: - return aarch64_ext_rcpc3_addr_opt_offset (self, info, code, inst, errors); + return aarch64_ext_sve_reglist_zt (self, info, code, inst, errors); case 303: + case 304: + case 305: + case 306: + return aarch64_ext_rcpc3_addr_opt_offset (self, info, code, inst, errors); + case 307: return aarch64_ext_rcpc3_addr_offset (self, info, code, inst, errors); default: assert (0); abort (); } diff --git a/opcodes/aarch64-opc-2.c b/opcodes/aarch64-opc-2.c index 034436bfa8e..7962b0f33e2 100644 --- a/opcodes/aarch64-opc-2.c +++ b/opcodes/aarch64-opc-2.c @@ -63,9 +63,13 @@ const struct aarch64_operand aarch64_operands[] = {AARCH64_OPND_CLASS_SIMD_ELEMENT, "En", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn}, "a SIMD vector element"}, {AARCH64_OPND_CLASS_SIMD_ELEMENT, "Em", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rm}, "a SIMD vector element"}, {AARCH64_OPND_CLASS_SIMD_ELEMENT, "Em16", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rm}, "a SIMD vector element limited to V0-V15"}, + {AARCH64_OPND_CLASS_SIMD_ELEMENT, "Em_INDEX1_14", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rm, FLD_imm1_14}, "a SIMD vector without a type qualifier encoding a bit index"}, + {AARCH64_OPND_CLASS_SIMD_ELEMENT, "Em_INDEX2_13", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rm, FLD_imm2_13}, "a SIMD vector without a type qualifier encoding a bit index"}, + {AARCH64_OPND_CLASS_SIMD_ELEMENT, "Em_INDEX3_12", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rm, FLD_imm3_12}, "a SIMD vector without a type qualifier encoding a bit index"}, {AARCH64_OPND_CLASS_SIMD_REGLIST, "LVn", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn}, "a SIMD vector register list"}, {AARCH64_OPND_CLASS_SIMD_REGLIST, "LVt", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "a SIMD vector register list"}, {AARCH64_OPND_CLASS_SIMD_REGLIST, "LVt_AL", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "a SIMD vector register list"}, + {AARCH64_OPND_CLASS_SIMD_REGLIST, "LVn_LUT", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn}, "a SIMD vector register list"}, {AARCH64_OPND_CLASS_SIMD_REGLIST, "LEt", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "a SIMD vector element list"}, {AARCH64_OPND_CLASS_IMMEDIATE, "CRn", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_CRn}, "a 4-bit opcode field named for historical reasons C0 - C15"}, {AARCH64_OPND_CLASS_IMMEDIATE, "CRm", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_CRm}, "a 4-bit opcode field named for historical reasons C0 - C15"}, --------------2.43.2--